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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
57822dc6 | 40 | #include "i915_gem_clflush.h" |
db18b6a6 | 41 | #include "intel_dsi.h" |
e5510fac | 42 | #include "i915_trace.h" |
319c1d42 | 43 | #include <drm/drm_atomic.h> |
c196e1d6 | 44 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
45 | #include <drm/drm_dp_helper.h> |
46 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
47 | #include <drm/drm_plane_helper.h> |
48 | #include <drm/drm_rect.h> | |
c0f372b3 | 49 | #include <linux/dma_remapping.h> |
fd8e058a | 50 | #include <linux/reservation.h> |
79e53945 | 51 | |
465c120c | 52 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 53 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
54 | DRM_FORMAT_C8, |
55 | DRM_FORMAT_RGB565, | |
465c120c | 56 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 57 | DRM_FORMAT_XRGB8888, |
465c120c MR |
58 | }; |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 61 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
62 | DRM_FORMAT_C8, |
63 | DRM_FORMAT_RGB565, | |
64 | DRM_FORMAT_XRGB8888, | |
65 | DRM_FORMAT_XBGR8888, | |
66 | DRM_FORMAT_XRGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | }; | |
69 | ||
714244e2 BW |
70 | static const uint64_t i9xx_format_modifiers[] = { |
71 | I915_FORMAT_MOD_X_TILED, | |
72 | DRM_FORMAT_MOD_LINEAR, | |
73 | DRM_FORMAT_MOD_INVALID | |
74 | }; | |
75 | ||
6c0fd451 | 76 | static const uint32_t skl_primary_formats[] = { |
67fe7dc5 DL |
77 | DRM_FORMAT_C8, |
78 | DRM_FORMAT_RGB565, | |
79 | DRM_FORMAT_XRGB8888, | |
465c120c | 80 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 81 | DRM_FORMAT_ARGB8888, |
465c120c MR |
82 | DRM_FORMAT_ABGR8888, |
83 | DRM_FORMAT_XRGB2101010, | |
465c120c | 84 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
85 | DRM_FORMAT_YUYV, |
86 | DRM_FORMAT_YVYU, | |
87 | DRM_FORMAT_UYVY, | |
88 | DRM_FORMAT_VYUY, | |
465c120c MR |
89 | }; |
90 | ||
714244e2 BW |
91 | static const uint64_t skl_format_modifiers_noccs[] = { |
92 | I915_FORMAT_MOD_Yf_TILED, | |
93 | I915_FORMAT_MOD_Y_TILED, | |
94 | I915_FORMAT_MOD_X_TILED, | |
95 | DRM_FORMAT_MOD_LINEAR, | |
96 | DRM_FORMAT_MOD_INVALID | |
97 | }; | |
98 | ||
99 | static const uint64_t skl_format_modifiers_ccs[] = { | |
100 | I915_FORMAT_MOD_Yf_TILED_CCS, | |
101 | I915_FORMAT_MOD_Y_TILED_CCS, | |
102 | I915_FORMAT_MOD_Yf_TILED, | |
103 | I915_FORMAT_MOD_Y_TILED, | |
104 | I915_FORMAT_MOD_X_TILED, | |
105 | DRM_FORMAT_MOD_LINEAR, | |
106 | DRM_FORMAT_MOD_INVALID | |
107 | }; | |
108 | ||
3d7d6510 MR |
109 | /* Cursor formats */ |
110 | static const uint32_t intel_cursor_formats[] = { | |
111 | DRM_FORMAT_ARGB8888, | |
112 | }; | |
113 | ||
714244e2 BW |
114 | static const uint64_t cursor_format_modifiers[] = { |
115 | DRM_FORMAT_MOD_LINEAR, | |
116 | DRM_FORMAT_MOD_INVALID | |
117 | }; | |
118 | ||
f1f644dc | 119 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 120 | struct intel_crtc_state *pipe_config); |
18442d08 | 121 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 122 | struct intel_crtc_state *pipe_config); |
f1f644dc | 123 | |
24dbf51a CW |
124 | static int intel_framebuffer_init(struct intel_framebuffer *ifb, |
125 | struct drm_i915_gem_object *obj, | |
126 | struct drm_mode_fb_cmd2 *mode_cmd); | |
5b18e57c DV |
127 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
128 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 129 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 130 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
131 | struct intel_link_m_n *m_n, |
132 | struct intel_link_m_n *m2_n2); | |
29407aab | 133 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 134 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 135 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 136 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 137 | const struct intel_crtc_state *pipe_config); |
d288f65f | 138 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 139 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
140 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
141 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
1c74eeaf NM |
142 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
143 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
144 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
145 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
146 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
aecd36b8 VS |
147 | static void intel_modeset_setup_hw_state(struct drm_device *dev, |
148 | struct drm_modeset_acquire_ctx *ctx); | |
2622a081 | 149 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
e7457a9a | 150 | |
d4906093 | 151 | struct intel_limit { |
4c5def93 ACO |
152 | struct { |
153 | int min, max; | |
154 | } dot, vco, n, m, m1, m2, p, p1; | |
155 | ||
156 | struct { | |
157 | int dot_limit; | |
158 | int p2_slow, p2_fast; | |
159 | } p2; | |
d4906093 | 160 | }; |
79e53945 | 161 | |
bfa7df01 | 162 | /* returns HPLL frequency in kHz */ |
49cd97a3 | 163 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) |
bfa7df01 VS |
164 | { |
165 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
166 | ||
167 | /* Obtain SKU information */ | |
168 | mutex_lock(&dev_priv->sb_lock); | |
169 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
170 | CCK_FUSE_HPLL_FREQ_MASK; | |
171 | mutex_unlock(&dev_priv->sb_lock); | |
172 | ||
173 | return vco_freq[hpll_freq] * 1000; | |
174 | } | |
175 | ||
c30fec65 VS |
176 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
177 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
178 | { |
179 | u32 val; | |
180 | int divider; | |
181 | ||
bfa7df01 VS |
182 | mutex_lock(&dev_priv->sb_lock); |
183 | val = vlv_cck_read(dev_priv, reg); | |
184 | mutex_unlock(&dev_priv->sb_lock); | |
185 | ||
186 | divider = val & CCK_FREQUENCY_VALUES; | |
187 | ||
188 | WARN((val & CCK_FREQUENCY_STATUS) != | |
189 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
190 | "%s change in progress\n", name); | |
191 | ||
c30fec65 VS |
192 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
193 | } | |
194 | ||
7ff89ca2 VS |
195 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
196 | const char *name, u32 reg) | |
c30fec65 VS |
197 | { |
198 | if (dev_priv->hpll_freq == 0) | |
49cd97a3 | 199 | dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); |
c30fec65 VS |
200 | |
201 | return vlv_get_cck_clock(dev_priv, name, reg, | |
202 | dev_priv->hpll_freq); | |
bfa7df01 VS |
203 | } |
204 | ||
bfa7df01 VS |
205 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
206 | { | |
666a4537 | 207 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
208 | return; |
209 | ||
210 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
211 | CCK_CZ_CLOCK_CONTROL); | |
212 | ||
213 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
214 | } | |
215 | ||
021357ac | 216 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
217 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
218 | const struct intel_crtc_state *pipe_config) | |
021357ac | 219 | { |
21a727b3 VS |
220 | if (HAS_DDI(dev_priv)) |
221 | return pipe_config->port_clock; /* SPLL */ | |
222 | else if (IS_GEN5(dev_priv)) | |
223 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 224 | else |
21a727b3 | 225 | return 270000; |
021357ac CW |
226 | } |
227 | ||
1b6f4958 | 228 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 229 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 230 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 231 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
232 | .m = { .min = 96, .max = 140 }, |
233 | .m1 = { .min = 18, .max = 26 }, | |
234 | .m2 = { .min = 6, .max = 16 }, | |
235 | .p = { .min = 4, .max = 128 }, | |
236 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
237 | .p2 = { .dot_limit = 165000, |
238 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
239 | }; |
240 | ||
1b6f4958 | 241 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 242 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 243 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 244 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
245 | .m = { .min = 96, .max = 140 }, |
246 | .m1 = { .min = 18, .max = 26 }, | |
247 | .m2 = { .min = 6, .max = 16 }, | |
248 | .p = { .min = 4, .max = 128 }, | |
249 | .p1 = { .min = 2, .max = 33 }, | |
250 | .p2 = { .dot_limit = 165000, | |
251 | .p2_slow = 4, .p2_fast = 4 }, | |
252 | }; | |
253 | ||
1b6f4958 | 254 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 255 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 256 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 257 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
258 | .m = { .min = 96, .max = 140 }, |
259 | .m1 = { .min = 18, .max = 26 }, | |
260 | .m2 = { .min = 6, .max = 16 }, | |
261 | .p = { .min = 4, .max = 128 }, | |
262 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
263 | .p2 = { .dot_limit = 165000, |
264 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 265 | }; |
273e27ca | 266 | |
1b6f4958 | 267 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
268 | .dot = { .min = 20000, .max = 400000 }, |
269 | .vco = { .min = 1400000, .max = 2800000 }, | |
270 | .n = { .min = 1, .max = 6 }, | |
271 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
272 | .m1 = { .min = 8, .max = 18 }, |
273 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
274 | .p = { .min = 5, .max = 80 }, |
275 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
276 | .p2 = { .dot_limit = 200000, |
277 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
278 | }; |
279 | ||
1b6f4958 | 280 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
281 | .dot = { .min = 20000, .max = 400000 }, |
282 | .vco = { .min = 1400000, .max = 2800000 }, | |
283 | .n = { .min = 1, .max = 6 }, | |
284 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
285 | .m1 = { .min = 8, .max = 18 }, |
286 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
287 | .p = { .min = 7, .max = 98 }, |
288 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
289 | .p2 = { .dot_limit = 112000, |
290 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
291 | }; |
292 | ||
273e27ca | 293 | |
1b6f4958 | 294 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
295 | .dot = { .min = 25000, .max = 270000 }, |
296 | .vco = { .min = 1750000, .max = 3500000}, | |
297 | .n = { .min = 1, .max = 4 }, | |
298 | .m = { .min = 104, .max = 138 }, | |
299 | .m1 = { .min = 17, .max = 23 }, | |
300 | .m2 = { .min = 5, .max = 11 }, | |
301 | .p = { .min = 10, .max = 30 }, | |
302 | .p1 = { .min = 1, .max = 3}, | |
303 | .p2 = { .dot_limit = 270000, | |
304 | .p2_slow = 10, | |
305 | .p2_fast = 10 | |
044c7c41 | 306 | }, |
e4b36699 KP |
307 | }; |
308 | ||
1b6f4958 | 309 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
310 | .dot = { .min = 22000, .max = 400000 }, |
311 | .vco = { .min = 1750000, .max = 3500000}, | |
312 | .n = { .min = 1, .max = 4 }, | |
313 | .m = { .min = 104, .max = 138 }, | |
314 | .m1 = { .min = 16, .max = 23 }, | |
315 | .m2 = { .min = 5, .max = 11 }, | |
316 | .p = { .min = 5, .max = 80 }, | |
317 | .p1 = { .min = 1, .max = 8}, | |
318 | .p2 = { .dot_limit = 165000, | |
319 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
320 | }; |
321 | ||
1b6f4958 | 322 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
323 | .dot = { .min = 20000, .max = 115000 }, |
324 | .vco = { .min = 1750000, .max = 3500000 }, | |
325 | .n = { .min = 1, .max = 3 }, | |
326 | .m = { .min = 104, .max = 138 }, | |
327 | .m1 = { .min = 17, .max = 23 }, | |
328 | .m2 = { .min = 5, .max = 11 }, | |
329 | .p = { .min = 28, .max = 112 }, | |
330 | .p1 = { .min = 2, .max = 8 }, | |
331 | .p2 = { .dot_limit = 0, | |
332 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 333 | }, |
e4b36699 KP |
334 | }; |
335 | ||
1b6f4958 | 336 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
337 | .dot = { .min = 80000, .max = 224000 }, |
338 | .vco = { .min = 1750000, .max = 3500000 }, | |
339 | .n = { .min = 1, .max = 3 }, | |
340 | .m = { .min = 104, .max = 138 }, | |
341 | .m1 = { .min = 17, .max = 23 }, | |
342 | .m2 = { .min = 5, .max = 11 }, | |
343 | .p = { .min = 14, .max = 42 }, | |
344 | .p1 = { .min = 2, .max = 6 }, | |
345 | .p2 = { .dot_limit = 0, | |
346 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 347 | }, |
e4b36699 KP |
348 | }; |
349 | ||
1b6f4958 | 350 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
351 | .dot = { .min = 20000, .max = 400000}, |
352 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 353 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
354 | .n = { .min = 3, .max = 6 }, |
355 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 356 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
357 | .m1 = { .min = 0, .max = 0 }, |
358 | .m2 = { .min = 0, .max = 254 }, | |
359 | .p = { .min = 5, .max = 80 }, | |
360 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
361 | .p2 = { .dot_limit = 200000, |
362 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
363 | }; |
364 | ||
1b6f4958 | 365 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
366 | .dot = { .min = 20000, .max = 400000 }, |
367 | .vco = { .min = 1700000, .max = 3500000 }, | |
368 | .n = { .min = 3, .max = 6 }, | |
369 | .m = { .min = 2, .max = 256 }, | |
370 | .m1 = { .min = 0, .max = 0 }, | |
371 | .m2 = { .min = 0, .max = 254 }, | |
372 | .p = { .min = 7, .max = 112 }, | |
373 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
374 | .p2 = { .dot_limit = 112000, |
375 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
376 | }; |
377 | ||
273e27ca EA |
378 | /* Ironlake / Sandybridge |
379 | * | |
380 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
381 | * the range value for them is (actual_value - 2). | |
382 | */ | |
1b6f4958 | 383 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
384 | .dot = { .min = 25000, .max = 350000 }, |
385 | .vco = { .min = 1760000, .max = 3510000 }, | |
386 | .n = { .min = 1, .max = 5 }, | |
387 | .m = { .min = 79, .max = 127 }, | |
388 | .m1 = { .min = 12, .max = 22 }, | |
389 | .m2 = { .min = 5, .max = 9 }, | |
390 | .p = { .min = 5, .max = 80 }, | |
391 | .p1 = { .min = 1, .max = 8 }, | |
392 | .p2 = { .dot_limit = 225000, | |
393 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
394 | }; |
395 | ||
1b6f4958 | 396 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
397 | .dot = { .min = 25000, .max = 350000 }, |
398 | .vco = { .min = 1760000, .max = 3510000 }, | |
399 | .n = { .min = 1, .max = 3 }, | |
400 | .m = { .min = 79, .max = 118 }, | |
401 | .m1 = { .min = 12, .max = 22 }, | |
402 | .m2 = { .min = 5, .max = 9 }, | |
403 | .p = { .min = 28, .max = 112 }, | |
404 | .p1 = { .min = 2, .max = 8 }, | |
405 | .p2 = { .dot_limit = 225000, | |
406 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
407 | }; |
408 | ||
1b6f4958 | 409 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
410 | .dot = { .min = 25000, .max = 350000 }, |
411 | .vco = { .min = 1760000, .max = 3510000 }, | |
412 | .n = { .min = 1, .max = 3 }, | |
413 | .m = { .min = 79, .max = 127 }, | |
414 | .m1 = { .min = 12, .max = 22 }, | |
415 | .m2 = { .min = 5, .max = 9 }, | |
416 | .p = { .min = 14, .max = 56 }, | |
417 | .p1 = { .min = 2, .max = 8 }, | |
418 | .p2 = { .dot_limit = 225000, | |
419 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
420 | }; |
421 | ||
273e27ca | 422 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 423 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
424 | .dot = { .min = 25000, .max = 350000 }, |
425 | .vco = { .min = 1760000, .max = 3510000 }, | |
426 | .n = { .min = 1, .max = 2 }, | |
427 | .m = { .min = 79, .max = 126 }, | |
428 | .m1 = { .min = 12, .max = 22 }, | |
429 | .m2 = { .min = 5, .max = 9 }, | |
430 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 431 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
432 | .p2 = { .dot_limit = 225000, |
433 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
434 | }; |
435 | ||
1b6f4958 | 436 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
437 | .dot = { .min = 25000, .max = 350000 }, |
438 | .vco = { .min = 1760000, .max = 3510000 }, | |
439 | .n = { .min = 1, .max = 3 }, | |
440 | .m = { .min = 79, .max = 126 }, | |
441 | .m1 = { .min = 12, .max = 22 }, | |
442 | .m2 = { .min = 5, .max = 9 }, | |
443 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 444 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
445 | .p2 = { .dot_limit = 225000, |
446 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
447 | }; |
448 | ||
1b6f4958 | 449 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
450 | /* |
451 | * These are the data rate limits (measured in fast clocks) | |
452 | * since those are the strictest limits we have. The fast | |
453 | * clock and actual rate limits are more relaxed, so checking | |
454 | * them would make no difference. | |
455 | */ | |
456 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 457 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 458 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
459 | .m1 = { .min = 2, .max = 3 }, |
460 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 461 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 462 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
463 | }; |
464 | ||
1b6f4958 | 465 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
466 | /* |
467 | * These are the data rate limits (measured in fast clocks) | |
468 | * since those are the strictest limits we have. The fast | |
469 | * clock and actual rate limits are more relaxed, so checking | |
470 | * them would make no difference. | |
471 | */ | |
472 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 473 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
474 | .n = { .min = 1, .max = 1 }, |
475 | .m1 = { .min = 2, .max = 2 }, | |
476 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
477 | .p1 = { .min = 2, .max = 4 }, | |
478 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
479 | }; | |
480 | ||
1b6f4958 | 481 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
482 | /* FIXME: find real dot limits */ |
483 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 484 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
485 | .n = { .min = 1, .max = 1 }, |
486 | .m1 = { .min = 2, .max = 2 }, | |
487 | /* FIXME: find real m2 limits */ | |
488 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
489 | .p1 = { .min = 2, .max = 4 }, | |
490 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
491 | }; | |
492 | ||
cdba954e ACO |
493 | static bool |
494 | needs_modeset(struct drm_crtc_state *state) | |
495 | { | |
fc596660 | 496 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
497 | } |
498 | ||
dccbea3b ID |
499 | /* |
500 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
501 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
502 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
503 | * The helpers' return value is the rate of the clock that is fed to the | |
504 | * display engine's pipe which can be the above fast dot clock rate or a | |
505 | * divided-down version of it. | |
506 | */ | |
f2b115e6 | 507 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 508 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 509 | { |
2177832f SL |
510 | clock->m = clock->m2 + 2; |
511 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 512 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 513 | return 0; |
fb03ac01 VS |
514 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
515 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
516 | |
517 | return clock->dot; | |
2177832f SL |
518 | } |
519 | ||
7429e9d4 DV |
520 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
521 | { | |
522 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
523 | } | |
524 | ||
9e2c8475 | 525 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 526 | { |
7429e9d4 | 527 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 528 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 529 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 530 | return 0; |
fb03ac01 VS |
531 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
532 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
533 | |
534 | return clock->dot; | |
79e53945 JB |
535 | } |
536 | ||
9e2c8475 | 537 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
538 | { |
539 | clock->m = clock->m1 * clock->m2; | |
540 | clock->p = clock->p1 * clock->p2; | |
541 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 542 | return 0; |
589eca67 ID |
543 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
544 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
545 | |
546 | return clock->dot / 5; | |
589eca67 ID |
547 | } |
548 | ||
9e2c8475 | 549 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
550 | { |
551 | clock->m = clock->m1 * clock->m2; | |
552 | clock->p = clock->p1 * clock->p2; | |
553 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 554 | return 0; |
ef9348c8 CML |
555 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
556 | clock->n << 22); | |
557 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
558 | |
559 | return clock->dot / 5; | |
ef9348c8 CML |
560 | } |
561 | ||
7c04d1d9 | 562 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
563 | /** |
564 | * Returns whether the given set of divisors are valid for a given refclk with | |
565 | * the given connectors. | |
566 | */ | |
567 | ||
e2d214ae | 568 | static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 569 | const struct intel_limit *limit, |
9e2c8475 | 570 | const struct dpll *clock) |
79e53945 | 571 | { |
f01b7962 VS |
572 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
573 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 574 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 575 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 576 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 577 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 578 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 579 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 580 | |
e2d214ae | 581 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
cc3f90f0 | 582 | !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) |
f01b7962 VS |
583 | if (clock->m1 <= clock->m2) |
584 | INTELPllInvalid("m1 <= m2\n"); | |
585 | ||
e2d214ae | 586 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 587 | !IS_GEN9_LP(dev_priv)) { |
f01b7962 VS |
588 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
589 | INTELPllInvalid("p out of range\n"); | |
590 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
591 | INTELPllInvalid("m out of range\n"); | |
592 | } | |
593 | ||
79e53945 | 594 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 595 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
596 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
597 | * connector, etc., rather than just a single range. | |
598 | */ | |
599 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 600 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
601 | |
602 | return true; | |
603 | } | |
604 | ||
3b1429d9 | 605 | static int |
1b6f4958 | 606 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
607 | const struct intel_crtc_state *crtc_state, |
608 | int target) | |
79e53945 | 609 | { |
3b1429d9 | 610 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 611 | |
2d84d2b3 | 612 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 613 | /* |
a210b028 DV |
614 | * For LVDS just rely on its current settings for dual-channel. |
615 | * We haven't figured out how to reliably set up different | |
616 | * single/dual channel state, if we even can. | |
79e53945 | 617 | */ |
1974cad0 | 618 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 619 | return limit->p2.p2_fast; |
79e53945 | 620 | else |
3b1429d9 | 621 | return limit->p2.p2_slow; |
79e53945 JB |
622 | } else { |
623 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 624 | return limit->p2.p2_slow; |
79e53945 | 625 | else |
3b1429d9 | 626 | return limit->p2.p2_fast; |
79e53945 | 627 | } |
3b1429d9 VS |
628 | } |
629 | ||
70e8aa21 ACO |
630 | /* |
631 | * Returns a set of divisors for the desired target clock with the given | |
632 | * refclk, or FALSE. The returned values represent the clock equation: | |
633 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
634 | * | |
635 | * Target and reference clocks are specified in kHz. | |
636 | * | |
637 | * If match_clock is provided, then best_clock P divider must match the P | |
638 | * divider from @match_clock used for LVDS downclocking. | |
639 | */ | |
3b1429d9 | 640 | static bool |
1b6f4958 | 641 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 642 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
643 | int target, int refclk, struct dpll *match_clock, |
644 | struct dpll *best_clock) | |
3b1429d9 VS |
645 | { |
646 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 647 | struct dpll clock; |
3b1429d9 | 648 | int err = target; |
79e53945 | 649 | |
0206e353 | 650 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 651 | |
3b1429d9 VS |
652 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
653 | ||
42158660 ZY |
654 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
655 | clock.m1++) { | |
656 | for (clock.m2 = limit->m2.min; | |
657 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 658 | if (clock.m2 >= clock.m1) |
42158660 ZY |
659 | break; |
660 | for (clock.n = limit->n.min; | |
661 | clock.n <= limit->n.max; clock.n++) { | |
662 | for (clock.p1 = limit->p1.min; | |
663 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
664 | int this_err; |
665 | ||
dccbea3b | 666 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
667 | if (!intel_PLL_is_valid(to_i915(dev), |
668 | limit, | |
ac58c3f0 DV |
669 | &clock)) |
670 | continue; | |
671 | if (match_clock && | |
672 | clock.p != match_clock->p) | |
673 | continue; | |
674 | ||
675 | this_err = abs(clock.dot - target); | |
676 | if (this_err < err) { | |
677 | *best_clock = clock; | |
678 | err = this_err; | |
679 | } | |
680 | } | |
681 | } | |
682 | } | |
683 | } | |
684 | ||
685 | return (err != target); | |
686 | } | |
687 | ||
70e8aa21 ACO |
688 | /* |
689 | * Returns a set of divisors for the desired target clock with the given | |
690 | * refclk, or FALSE. The returned values represent the clock equation: | |
691 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
692 | * | |
693 | * Target and reference clocks are specified in kHz. | |
694 | * | |
695 | * If match_clock is provided, then best_clock P divider must match the P | |
696 | * divider from @match_clock used for LVDS downclocking. | |
697 | */ | |
ac58c3f0 | 698 | static bool |
1b6f4958 | 699 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 700 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
701 | int target, int refclk, struct dpll *match_clock, |
702 | struct dpll *best_clock) | |
79e53945 | 703 | { |
3b1429d9 | 704 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 705 | struct dpll clock; |
79e53945 JB |
706 | int err = target; |
707 | ||
0206e353 | 708 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 709 | |
3b1429d9 VS |
710 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
711 | ||
42158660 ZY |
712 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
713 | clock.m1++) { | |
714 | for (clock.m2 = limit->m2.min; | |
715 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
716 | for (clock.n = limit->n.min; |
717 | clock.n <= limit->n.max; clock.n++) { | |
718 | for (clock.p1 = limit->p1.min; | |
719 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
720 | int this_err; |
721 | ||
dccbea3b | 722 | pnv_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
723 | if (!intel_PLL_is_valid(to_i915(dev), |
724 | limit, | |
1b894b59 | 725 | &clock)) |
79e53945 | 726 | continue; |
cec2f356 SP |
727 | if (match_clock && |
728 | clock.p != match_clock->p) | |
729 | continue; | |
79e53945 JB |
730 | |
731 | this_err = abs(clock.dot - target); | |
732 | if (this_err < err) { | |
733 | *best_clock = clock; | |
734 | err = this_err; | |
735 | } | |
736 | } | |
737 | } | |
738 | } | |
739 | } | |
740 | ||
741 | return (err != target); | |
742 | } | |
743 | ||
997c030c ACO |
744 | /* |
745 | * Returns a set of divisors for the desired target clock with the given | |
746 | * refclk, or FALSE. The returned values represent the clock equation: | |
747 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
748 | * |
749 | * Target and reference clocks are specified in kHz. | |
750 | * | |
751 | * If match_clock is provided, then best_clock P divider must match the P | |
752 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 753 | */ |
d4906093 | 754 | static bool |
1b6f4958 | 755 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 756 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
757 | int target, int refclk, struct dpll *match_clock, |
758 | struct dpll *best_clock) | |
d4906093 | 759 | { |
3b1429d9 | 760 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 761 | struct dpll clock; |
d4906093 | 762 | int max_n; |
3b1429d9 | 763 | bool found = false; |
6ba770dc AJ |
764 | /* approximately equals target * 0.00585 */ |
765 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
766 | |
767 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
768 | |
769 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
770 | ||
d4906093 | 771 | max_n = limit->n.max; |
f77f13e2 | 772 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 773 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 774 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
775 | for (clock.m1 = limit->m1.max; |
776 | clock.m1 >= limit->m1.min; clock.m1--) { | |
777 | for (clock.m2 = limit->m2.max; | |
778 | clock.m2 >= limit->m2.min; clock.m2--) { | |
779 | for (clock.p1 = limit->p1.max; | |
780 | clock.p1 >= limit->p1.min; clock.p1--) { | |
781 | int this_err; | |
782 | ||
dccbea3b | 783 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
784 | if (!intel_PLL_is_valid(to_i915(dev), |
785 | limit, | |
1b894b59 | 786 | &clock)) |
d4906093 | 787 | continue; |
1b894b59 CW |
788 | |
789 | this_err = abs(clock.dot - target); | |
d4906093 ML |
790 | if (this_err < err_most) { |
791 | *best_clock = clock; | |
792 | err_most = this_err; | |
793 | max_n = clock.n; | |
794 | found = true; | |
795 | } | |
796 | } | |
797 | } | |
798 | } | |
799 | } | |
2c07245f ZW |
800 | return found; |
801 | } | |
802 | ||
d5dd62bd ID |
803 | /* |
804 | * Check if the calculated PLL configuration is more optimal compared to the | |
805 | * best configuration and error found so far. Return the calculated error. | |
806 | */ | |
807 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
808 | const struct dpll *calculated_clock, |
809 | const struct dpll *best_clock, | |
d5dd62bd ID |
810 | unsigned int best_error_ppm, |
811 | unsigned int *error_ppm) | |
812 | { | |
9ca3ba01 ID |
813 | /* |
814 | * For CHV ignore the error and consider only the P value. | |
815 | * Prefer a bigger P value based on HW requirements. | |
816 | */ | |
920a14b2 | 817 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
818 | *error_ppm = 0; |
819 | ||
820 | return calculated_clock->p > best_clock->p; | |
821 | } | |
822 | ||
24be4e46 ID |
823 | if (WARN_ON_ONCE(!target_freq)) |
824 | return false; | |
825 | ||
d5dd62bd ID |
826 | *error_ppm = div_u64(1000000ULL * |
827 | abs(target_freq - calculated_clock->dot), | |
828 | target_freq); | |
829 | /* | |
830 | * Prefer a better P value over a better (smaller) error if the error | |
831 | * is small. Ensure this preference for future configurations too by | |
832 | * setting the error to 0. | |
833 | */ | |
834 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
835 | *error_ppm = 0; | |
836 | ||
837 | return true; | |
838 | } | |
839 | ||
840 | return *error_ppm + 10 < best_error_ppm; | |
841 | } | |
842 | ||
65b3d6a9 ACO |
843 | /* |
844 | * Returns a set of divisors for the desired target clock with the given | |
845 | * refclk, or FALSE. The returned values represent the clock equation: | |
846 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
847 | */ | |
a0c4da24 | 848 | static bool |
1b6f4958 | 849 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 850 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
851 | int target, int refclk, struct dpll *match_clock, |
852 | struct dpll *best_clock) | |
a0c4da24 | 853 | { |
a93e255f | 854 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 855 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 856 | struct dpll clock; |
69e4f900 | 857 | unsigned int bestppm = 1000000; |
27e639bf VS |
858 | /* min update 19.2 MHz */ |
859 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 860 | bool found = false; |
a0c4da24 | 861 | |
6b4bf1c4 VS |
862 | target *= 5; /* fast clock */ |
863 | ||
864 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
865 | |
866 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 867 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 868 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 869 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 870 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 871 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 872 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 873 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 874 | unsigned int ppm; |
69e4f900 | 875 | |
6b4bf1c4 VS |
876 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
877 | refclk * clock.m1); | |
878 | ||
dccbea3b | 879 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 880 | |
e2d214ae TU |
881 | if (!intel_PLL_is_valid(to_i915(dev), |
882 | limit, | |
f01b7962 | 883 | &clock)) |
43b0ac53 VS |
884 | continue; |
885 | ||
d5dd62bd ID |
886 | if (!vlv_PLL_is_optimal(dev, target, |
887 | &clock, | |
888 | best_clock, | |
889 | bestppm, &ppm)) | |
890 | continue; | |
6b4bf1c4 | 891 | |
d5dd62bd ID |
892 | *best_clock = clock; |
893 | bestppm = ppm; | |
894 | found = true; | |
a0c4da24 JB |
895 | } |
896 | } | |
897 | } | |
898 | } | |
a0c4da24 | 899 | |
49e497ef | 900 | return found; |
a0c4da24 | 901 | } |
a4fc5ed6 | 902 | |
65b3d6a9 ACO |
903 | /* |
904 | * Returns a set of divisors for the desired target clock with the given | |
905 | * refclk, or FALSE. The returned values represent the clock equation: | |
906 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
907 | */ | |
ef9348c8 | 908 | static bool |
1b6f4958 | 909 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 910 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
911 | int target, int refclk, struct dpll *match_clock, |
912 | struct dpll *best_clock) | |
ef9348c8 | 913 | { |
a93e255f | 914 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 915 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 916 | unsigned int best_error_ppm; |
9e2c8475 | 917 | struct dpll clock; |
ef9348c8 CML |
918 | uint64_t m2; |
919 | int found = false; | |
920 | ||
921 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 922 | best_error_ppm = 1000000; |
ef9348c8 CML |
923 | |
924 | /* | |
925 | * Based on hardware doc, the n always set to 1, and m1 always | |
926 | * set to 2. If requires to support 200Mhz refclk, we need to | |
927 | * revisit this because n may not 1 anymore. | |
928 | */ | |
929 | clock.n = 1, clock.m1 = 2; | |
930 | target *= 5; /* fast clock */ | |
931 | ||
932 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
933 | for (clock.p2 = limit->p2.p2_fast; | |
934 | clock.p2 >= limit->p2.p2_slow; | |
935 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 936 | unsigned int error_ppm; |
ef9348c8 CML |
937 | |
938 | clock.p = clock.p1 * clock.p2; | |
939 | ||
940 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
941 | clock.n) << 22, refclk * clock.m1); | |
942 | ||
943 | if (m2 > INT_MAX/clock.m1) | |
944 | continue; | |
945 | ||
946 | clock.m2 = m2; | |
947 | ||
dccbea3b | 948 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 949 | |
e2d214ae | 950 | if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
951 | continue; |
952 | ||
9ca3ba01 ID |
953 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
954 | best_error_ppm, &error_ppm)) | |
955 | continue; | |
956 | ||
957 | *best_clock = clock; | |
958 | best_error_ppm = error_ppm; | |
959 | found = true; | |
ef9348c8 CML |
960 | } |
961 | } | |
962 | ||
963 | return found; | |
964 | } | |
965 | ||
5ab7b0b7 | 966 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 967 | struct dpll *best_clock) |
5ab7b0b7 | 968 | { |
65b3d6a9 | 969 | int refclk = 100000; |
1b6f4958 | 970 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 971 | |
65b3d6a9 | 972 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
973 | target_clock, refclk, NULL, best_clock); |
974 | } | |
975 | ||
525b9311 | 976 | bool intel_crtc_active(struct intel_crtc *crtc) |
20ddf665 | 977 | { |
20ddf665 VS |
978 | /* Be paranoid as we can arrive here with only partial |
979 | * state retrieved from the hardware during setup. | |
980 | * | |
241bfc38 | 981 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
982 | * as Haswell has gained clock readout/fastboot support. |
983 | * | |
66e514c1 | 984 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 985 | * properly reconstruct framebuffers. |
c3d1f436 MR |
986 | * |
987 | * FIXME: The intel_crtc->active here should be switched to | |
988 | * crtc->state->active once we have proper CRTC states wired up | |
989 | * for atomic. | |
20ddf665 | 990 | */ |
525b9311 VS |
991 | return crtc->active && crtc->base.primary->state->fb && |
992 | crtc->config->base.adjusted_mode.crtc_clock; | |
20ddf665 VS |
993 | } |
994 | ||
a5c961d1 PZ |
995 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
996 | enum pipe pipe) | |
997 | { | |
98187836 | 998 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a5c961d1 | 999 | |
e2af48c6 | 1000 | return crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1001 | } |
1002 | ||
6315b5d3 | 1003 | static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) |
fbf49ea2 | 1004 | { |
f0f59a00 | 1005 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1006 | u32 line1, line2; |
1007 | u32 line_mask; | |
1008 | ||
5db94019 | 1009 | if (IS_GEN2(dev_priv)) |
fbf49ea2 VS |
1010 | line_mask = DSL_LINEMASK_GEN2; |
1011 | else | |
1012 | line_mask = DSL_LINEMASK_GEN3; | |
1013 | ||
1014 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1015 | msleep(5); |
fbf49ea2 VS |
1016 | line2 = I915_READ(reg) & line_mask; |
1017 | ||
1018 | return line1 == line2; | |
1019 | } | |
1020 | ||
ab7ad7f6 KP |
1021 | /* |
1022 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1023 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1024 | * |
1025 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1026 | * spinning on the vblank interrupt status bit, since we won't actually | |
1027 | * see an interrupt when the pipe is disabled. | |
1028 | * | |
ab7ad7f6 KP |
1029 | * On Gen4 and above: |
1030 | * wait for the pipe register state bit to turn off | |
1031 | * | |
1032 | * Otherwise: | |
1033 | * wait for the display line value to settle (it usually | |
1034 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1035 | * |
9d0498a2 | 1036 | */ |
575f7ab7 | 1037 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1038 | { |
6315b5d3 | 1039 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1040 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1041 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 | 1042 | |
6315b5d3 | 1043 | if (INTEL_GEN(dev_priv) >= 4) { |
f0f59a00 | 1044 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1045 | |
1046 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1047 | if (intel_wait_for_register(dev_priv, |
1048 | reg, I965_PIPECONF_ACTIVE, 0, | |
1049 | 100)) | |
284637d9 | 1050 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1051 | } else { |
ab7ad7f6 | 1052 | /* Wait for the display line to settle */ |
6315b5d3 | 1053 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) |
284637d9 | 1054 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1055 | } |
79e53945 JB |
1056 | } |
1057 | ||
b24e7179 | 1058 | /* Only for pre-ILK configs */ |
55607e8a DV |
1059 | void assert_pll(struct drm_i915_private *dev_priv, |
1060 | enum pipe pipe, bool state) | |
b24e7179 | 1061 | { |
b24e7179 JB |
1062 | u32 val; |
1063 | bool cur_state; | |
1064 | ||
649636ef | 1065 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1066 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1067 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1068 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1069 | onoff(state), onoff(cur_state)); |
b24e7179 | 1070 | } |
b24e7179 | 1071 | |
23538ef1 | 1072 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1073 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1074 | { |
1075 | u32 val; | |
1076 | bool cur_state; | |
1077 | ||
a580516d | 1078 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1079 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1080 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1081 | |
1082 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1083 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1084 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1085 | onoff(state), onoff(cur_state)); |
23538ef1 | 1086 | } |
23538ef1 | 1087 | |
040484af JB |
1088 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1089 | enum pipe pipe, bool state) | |
1090 | { | |
040484af | 1091 | bool cur_state; |
ad80a810 PZ |
1092 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1093 | pipe); | |
040484af | 1094 | |
2d1fe073 | 1095 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1096 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1097 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1098 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1099 | } else { |
649636ef | 1100 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1101 | cur_state = !!(val & FDI_TX_ENABLE); |
1102 | } | |
e2c719b7 | 1103 | I915_STATE_WARN(cur_state != state, |
040484af | 1104 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1105 | onoff(state), onoff(cur_state)); |
040484af JB |
1106 | } |
1107 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1108 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1109 | ||
1110 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1111 | enum pipe pipe, bool state) | |
1112 | { | |
040484af JB |
1113 | u32 val; |
1114 | bool cur_state; | |
1115 | ||
649636ef | 1116 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1117 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1118 | I915_STATE_WARN(cur_state != state, |
040484af | 1119 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1120 | onoff(state), onoff(cur_state)); |
040484af JB |
1121 | } |
1122 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1123 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1124 | ||
1125 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1126 | enum pipe pipe) | |
1127 | { | |
040484af JB |
1128 | u32 val; |
1129 | ||
1130 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1131 | if (IS_GEN5(dev_priv)) |
040484af JB |
1132 | return; |
1133 | ||
bf507ef7 | 1134 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1135 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1136 | return; |
1137 | ||
649636ef | 1138 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1139 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1140 | } |
1141 | ||
55607e8a DV |
1142 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1143 | enum pipe pipe, bool state) | |
040484af | 1144 | { |
040484af | 1145 | u32 val; |
55607e8a | 1146 | bool cur_state; |
040484af | 1147 | |
649636ef | 1148 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1149 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1150 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1151 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1152 | onoff(state), onoff(cur_state)); |
040484af JB |
1153 | } |
1154 | ||
4f8036a2 | 1155 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1156 | { |
f0f59a00 | 1157 | i915_reg_t pp_reg; |
ea0760cf JB |
1158 | u32 val; |
1159 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1160 | bool locked = true; |
ea0760cf | 1161 | |
4f8036a2 | 1162 | if (WARN_ON(HAS_DDI(dev_priv))) |
bedd4dba JN |
1163 | return; |
1164 | ||
4f8036a2 | 1165 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1166 | u32 port_sel; |
1167 | ||
44cb734c ID |
1168 | pp_reg = PP_CONTROL(0); |
1169 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1170 | |
1171 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1172 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1173 | panel_pipe = PIPE_B; | |
1174 | /* XXX: else fix for eDP */ | |
4f8036a2 | 1175 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1176 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1177 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1178 | panel_pipe = pipe; |
ea0760cf | 1179 | } else { |
44cb734c | 1180 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1181 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1182 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1183 | } |
1184 | ||
1185 | val = I915_READ(pp_reg); | |
1186 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1187 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1188 | locked = false; |
1189 | ||
e2c719b7 | 1190 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1191 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1192 | pipe_name(pipe)); |
ea0760cf JB |
1193 | } |
1194 | ||
93ce0ba6 JN |
1195 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1196 | enum pipe pipe, bool state) | |
1197 | { | |
93ce0ba6 JN |
1198 | bool cur_state; |
1199 | ||
2a307c2e | 1200 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 1201 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1202 | else |
5efb3e28 | 1203 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1204 | |
e2c719b7 | 1205 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1206 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1207 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1208 | } |
1209 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1210 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1211 | ||
b840d907 JB |
1212 | void assert_pipe(struct drm_i915_private *dev_priv, |
1213 | enum pipe pipe, bool state) | |
b24e7179 | 1214 | { |
63d7bbe9 | 1215 | bool cur_state; |
702e7a56 PZ |
1216 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1217 | pipe); | |
4feed0eb | 1218 | enum intel_display_power_domain power_domain; |
b24e7179 | 1219 | |
e56134bc VS |
1220 | /* we keep both pipes enabled on 830 */ |
1221 | if (IS_I830(dev_priv)) | |
8e636784 DV |
1222 | state = true; |
1223 | ||
4feed0eb ID |
1224 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1225 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1226 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1227 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1228 | |
1229 | intel_display_power_put(dev_priv, power_domain); | |
1230 | } else { | |
1231 | cur_state = false; | |
69310161 PZ |
1232 | } |
1233 | ||
e2c719b7 | 1234 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1235 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1236 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1237 | } |
1238 | ||
931872fc CW |
1239 | static void assert_plane(struct drm_i915_private *dev_priv, |
1240 | enum plane plane, bool state) | |
b24e7179 | 1241 | { |
b24e7179 | 1242 | u32 val; |
931872fc | 1243 | bool cur_state; |
b24e7179 | 1244 | |
649636ef | 1245 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1246 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1247 | I915_STATE_WARN(cur_state != state, |
931872fc | 1248 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1249 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1250 | } |
1251 | ||
931872fc CW |
1252 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1253 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1254 | ||
b24e7179 JB |
1255 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1256 | enum pipe pipe) | |
1257 | { | |
649636ef | 1258 | int i; |
b24e7179 | 1259 | |
653e1026 | 1260 | /* Primary planes are fixed to pipes on gen4+ */ |
6315b5d3 | 1261 | if (INTEL_GEN(dev_priv) >= 4) { |
649636ef | 1262 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1263 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1264 | "plane %c assertion failure, should be disabled but not\n", |
1265 | plane_name(pipe)); | |
19ec1358 | 1266 | return; |
28c05794 | 1267 | } |
19ec1358 | 1268 | |
b24e7179 | 1269 | /* Need to check both planes against the pipe */ |
055e393f | 1270 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1271 | u32 val = I915_READ(DSPCNTR(i)); |
1272 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1273 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1274 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1275 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1276 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1277 | } |
1278 | } | |
1279 | ||
19332d7a JB |
1280 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1281 | enum pipe pipe) | |
1282 | { | |
649636ef | 1283 | int sprite; |
19332d7a | 1284 | |
6315b5d3 | 1285 | if (INTEL_GEN(dev_priv) >= 9) { |
3bdcfc0c | 1286 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1287 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1288 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1289 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1290 | sprite, pipe_name(pipe)); | |
1291 | } | |
920a14b2 | 1292 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3bdcfc0c | 1293 | for_each_sprite(dev_priv, pipe, sprite) { |
83c04a62 | 1294 | u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite)); |
e2c719b7 | 1295 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1296 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1297 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef | 1298 | } |
6315b5d3 | 1299 | } else if (INTEL_GEN(dev_priv) >= 7) { |
649636ef | 1300 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1301 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1302 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1303 | plane_name(pipe), pipe_name(pipe)); |
ab33081a | 1304 | } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
649636ef | 1305 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1306 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1307 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1308 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1309 | } |
1310 | } | |
1311 | ||
08c71e5e VS |
1312 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1313 | { | |
e2c719b7 | 1314 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1315 | drm_crtc_vblank_put(crtc); |
1316 | } | |
1317 | ||
7abd4b35 ACO |
1318 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1319 | enum pipe pipe) | |
92f2584a | 1320 | { |
92f2584a JB |
1321 | u32 val; |
1322 | bool enabled; | |
1323 | ||
649636ef | 1324 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1325 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1326 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1327 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1328 | pipe_name(pipe)); | |
92f2584a JB |
1329 | } |
1330 | ||
4e634389 KP |
1331 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1332 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1333 | { |
1334 | if ((val & DP_PORT_EN) == 0) | |
1335 | return false; | |
1336 | ||
2d1fe073 | 1337 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1338 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1339 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1340 | return false; | |
2d1fe073 | 1341 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1342 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1343 | return false; | |
f0575e92 KP |
1344 | } else { |
1345 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1346 | return false; | |
1347 | } | |
1348 | return true; | |
1349 | } | |
1350 | ||
1519b995 KP |
1351 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1352 | enum pipe pipe, u32 val) | |
1353 | { | |
dc0fa718 | 1354 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1355 | return false; |
1356 | ||
2d1fe073 | 1357 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1358 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1359 | return false; |
2d1fe073 | 1360 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1361 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1362 | return false; | |
1519b995 | 1363 | } else { |
dc0fa718 | 1364 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1365 | return false; |
1366 | } | |
1367 | return true; | |
1368 | } | |
1369 | ||
1370 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1371 | enum pipe pipe, u32 val) | |
1372 | { | |
1373 | if ((val & LVDS_PORT_EN) == 0) | |
1374 | return false; | |
1375 | ||
2d1fe073 | 1376 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1377 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1378 | return false; | |
1379 | } else { | |
1380 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1381 | return false; | |
1382 | } | |
1383 | return true; | |
1384 | } | |
1385 | ||
1386 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1387 | enum pipe pipe, u32 val) | |
1388 | { | |
1389 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1390 | return false; | |
2d1fe073 | 1391 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1392 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1393 | return false; | |
1394 | } else { | |
1395 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1396 | return false; | |
1397 | } | |
1398 | return true; | |
1399 | } | |
1400 | ||
291906f1 | 1401 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1402 | enum pipe pipe, i915_reg_t reg, |
1403 | u32 port_sel) | |
291906f1 | 1404 | { |
47a05eca | 1405 | u32 val = I915_READ(reg); |
e2c719b7 | 1406 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1407 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1408 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1409 | |
2d1fe073 | 1410 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1411 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1412 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1413 | } |
1414 | ||
1415 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1416 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1417 | { |
47a05eca | 1418 | u32 val = I915_READ(reg); |
e2c719b7 | 1419 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1420 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1421 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1422 | |
2d1fe073 | 1423 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1424 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1425 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1426 | } |
1427 | ||
1428 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1429 | enum pipe pipe) | |
1430 | { | |
291906f1 | 1431 | u32 val; |
291906f1 | 1432 | |
f0575e92 KP |
1433 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1434 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1435 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1436 | |
649636ef | 1437 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1438 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1439 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1440 | pipe_name(pipe)); |
291906f1 | 1441 | |
649636ef | 1442 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1443 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1444 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1445 | pipe_name(pipe)); |
291906f1 | 1446 | |
e2debe91 PZ |
1447 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1448 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1449 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1450 | } |
1451 | ||
cd2d34d9 VS |
1452 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1453 | const struct intel_crtc_state *pipe_config) | |
1454 | { | |
1455 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1456 | enum pipe pipe = crtc->pipe; | |
1457 | ||
1458 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1459 | POSTING_READ(DPLL(pipe)); | |
1460 | udelay(150); | |
1461 | ||
2c30b43b CW |
1462 | if (intel_wait_for_register(dev_priv, |
1463 | DPLL(pipe), | |
1464 | DPLL_LOCK_VLV, | |
1465 | DPLL_LOCK_VLV, | |
1466 | 1)) | |
cd2d34d9 VS |
1467 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1468 | } | |
1469 | ||
d288f65f | 1470 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1471 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1472 | { |
cd2d34d9 | 1473 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1474 | enum pipe pipe = crtc->pipe; |
87442f73 | 1475 | |
8bd3f301 | 1476 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1477 | |
87442f73 | 1478 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1479 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1480 | |
cd2d34d9 VS |
1481 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1482 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1483 | |
8bd3f301 VS |
1484 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1485 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1486 | } |
1487 | ||
cd2d34d9 VS |
1488 | |
1489 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1490 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1491 | { |
cd2d34d9 | 1492 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1493 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1494 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1495 | u32 tmp; |
1496 | ||
a580516d | 1497 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1498 | |
1499 | /* Enable back the 10bit clock to display controller */ | |
1500 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1501 | tmp |= DPIO_DCLKP_EN; | |
1502 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1503 | ||
54433e91 VS |
1504 | mutex_unlock(&dev_priv->sb_lock); |
1505 | ||
9d556c99 CML |
1506 | /* |
1507 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1508 | */ | |
1509 | udelay(1); | |
1510 | ||
1511 | /* Enable PLL */ | |
d288f65f | 1512 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1513 | |
1514 | /* Check PLL is locked */ | |
6b18826a CW |
1515 | if (intel_wait_for_register(dev_priv, |
1516 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1517 | 1)) | |
9d556c99 | 1518 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1519 | } |
1520 | ||
1521 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1522 | const struct intel_crtc_state *pipe_config) | |
1523 | { | |
1524 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1525 | enum pipe pipe = crtc->pipe; | |
1526 | ||
1527 | assert_pipe_disabled(dev_priv, pipe); | |
1528 | ||
1529 | /* PLL is protected by panel, make sure we can write it */ | |
1530 | assert_panel_unlocked(dev_priv, pipe); | |
1531 | ||
1532 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1533 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1534 | |
c231775c VS |
1535 | if (pipe != PIPE_A) { |
1536 | /* | |
1537 | * WaPixelRepeatModeFixForC0:chv | |
1538 | * | |
1539 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1540 | * the value from DPLLBMD to either pipe B or C. | |
1541 | */ | |
dfa311f0 | 1542 | I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); |
c231775c VS |
1543 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); |
1544 | I915_WRITE(CBR4_VLV, 0); | |
1545 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1546 | ||
1547 | /* | |
1548 | * DPLLB VGA mode also seems to cause problems. | |
1549 | * We should always have it disabled. | |
1550 | */ | |
1551 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1552 | } else { | |
1553 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1554 | POSTING_READ(DPLL_MD(pipe)); | |
1555 | } | |
9d556c99 CML |
1556 | } |
1557 | ||
6315b5d3 | 1558 | static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) |
1c4e0274 VS |
1559 | { |
1560 | struct intel_crtc *crtc; | |
1561 | int count = 0; | |
1562 | ||
6315b5d3 | 1563 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
3538b9df | 1564 | count += crtc->base.state->active && |
2d84d2b3 VS |
1565 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1566 | } | |
1c4e0274 VS |
1567 | |
1568 | return count; | |
1569 | } | |
1570 | ||
939994da VS |
1571 | static void i9xx_enable_pll(struct intel_crtc *crtc, |
1572 | const struct intel_crtc_state *crtc_state) | |
63d7bbe9 | 1573 | { |
6315b5d3 | 1574 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 1575 | i915_reg_t reg = DPLL(crtc->pipe); |
939994da | 1576 | u32 dpll = crtc_state->dpll_hw_state.dpll; |
bb408dd2 | 1577 | int i; |
63d7bbe9 | 1578 | |
66e3d5c0 | 1579 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1580 | |
63d7bbe9 | 1581 | /* PLL is protected by panel, make sure we can write it */ |
50a0bc90 | 1582 | if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) |
66e3d5c0 | 1583 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1584 | |
1c4e0274 | 1585 | /* Enable DVO 2x clock on both PLLs if necessary */ |
6315b5d3 | 1586 | if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) { |
1c4e0274 VS |
1587 | /* |
1588 | * It appears to be important that we don't enable this | |
1589 | * for the current pipe before otherwise configuring the | |
1590 | * PLL. No idea how this should be handled if multiple | |
1591 | * DVO outputs are enabled simultaneosly. | |
1592 | */ | |
1593 | dpll |= DPLL_DVO_2X_MODE; | |
1594 | I915_WRITE(DPLL(!crtc->pipe), | |
1595 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1596 | } | |
66e3d5c0 | 1597 | |
c2b63374 VS |
1598 | /* |
1599 | * Apparently we need to have VGA mode enabled prior to changing | |
1600 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1601 | * dividers, even though the register value does change. | |
1602 | */ | |
1603 | I915_WRITE(reg, 0); | |
1604 | ||
8e7a65aa VS |
1605 | I915_WRITE(reg, dpll); |
1606 | ||
66e3d5c0 DV |
1607 | /* Wait for the clocks to stabilize. */ |
1608 | POSTING_READ(reg); | |
1609 | udelay(150); | |
1610 | ||
6315b5d3 | 1611 | if (INTEL_GEN(dev_priv) >= 4) { |
66e3d5c0 | 1612 | I915_WRITE(DPLL_MD(crtc->pipe), |
939994da | 1613 | crtc_state->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1614 | } else { |
1615 | /* The pixel multiplier can only be updated once the | |
1616 | * DPLL is enabled and the clocks are stable. | |
1617 | * | |
1618 | * So write it again. | |
1619 | */ | |
1620 | I915_WRITE(reg, dpll); | |
1621 | } | |
63d7bbe9 JB |
1622 | |
1623 | /* We do this three times for luck */ | |
bb408dd2 VS |
1624 | for (i = 0; i < 3; i++) { |
1625 | I915_WRITE(reg, dpll); | |
1626 | POSTING_READ(reg); | |
1627 | udelay(150); /* wait for warmup */ | |
1628 | } | |
63d7bbe9 JB |
1629 | } |
1630 | ||
1c4e0274 | 1631 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1632 | { |
6315b5d3 | 1633 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1c4e0274 VS |
1634 | enum pipe pipe = crtc->pipe; |
1635 | ||
1636 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
50a0bc90 | 1637 | if (IS_I830(dev_priv) && |
2d84d2b3 | 1638 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
6315b5d3 | 1639 | !intel_num_dvo_pipes(dev_priv)) { |
1c4e0274 VS |
1640 | I915_WRITE(DPLL(PIPE_B), |
1641 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1642 | I915_WRITE(DPLL(PIPE_A), | |
1643 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1644 | } | |
1645 | ||
b6b5d049 | 1646 | /* Don't disable pipe or pipe PLLs if needed */ |
e56134bc | 1647 | if (IS_I830(dev_priv)) |
63d7bbe9 JB |
1648 | return; |
1649 | ||
1650 | /* Make sure the pipe isn't still relying on us */ | |
1651 | assert_pipe_disabled(dev_priv, pipe); | |
1652 | ||
b8afb911 | 1653 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1654 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1655 | } |
1656 | ||
f6071166 JB |
1657 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1658 | { | |
b8afb911 | 1659 | u32 val; |
f6071166 JB |
1660 | |
1661 | /* Make sure the pipe isn't still relying on us */ | |
1662 | assert_pipe_disabled(dev_priv, pipe); | |
1663 | ||
03ed5cbf VS |
1664 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1665 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1666 | if (pipe != PIPE_A) | |
1667 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1668 | ||
f6071166 JB |
1669 | I915_WRITE(DPLL(pipe), val); |
1670 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1671 | } |
1672 | ||
1673 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1674 | { | |
d752048d | 1675 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1676 | u32 val; |
1677 | ||
a11b0703 VS |
1678 | /* Make sure the pipe isn't still relying on us */ |
1679 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1680 | |
60bfe44f VS |
1681 | val = DPLL_SSC_REF_CLK_CHV | |
1682 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1683 | if (pipe != PIPE_A) |
1684 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1685 | |
a11b0703 VS |
1686 | I915_WRITE(DPLL(pipe), val); |
1687 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1688 | |
a580516d | 1689 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1690 | |
1691 | /* Disable 10bit clock to display controller */ | |
1692 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1693 | val &= ~DPIO_DCLKP_EN; | |
1694 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1695 | ||
a580516d | 1696 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1697 | } |
1698 | ||
e4607fcf | 1699 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1700 | struct intel_digital_port *dport, |
1701 | unsigned int expected_mask) | |
89b667f8 JB |
1702 | { |
1703 | u32 port_mask; | |
f0f59a00 | 1704 | i915_reg_t dpll_reg; |
89b667f8 | 1705 | |
e4607fcf CML |
1706 | switch (dport->port) { |
1707 | case PORT_B: | |
89b667f8 | 1708 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1709 | dpll_reg = DPLL(0); |
e4607fcf CML |
1710 | break; |
1711 | case PORT_C: | |
89b667f8 | 1712 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1713 | dpll_reg = DPLL(0); |
9b6de0a1 | 1714 | expected_mask <<= 4; |
00fc31b7 CML |
1715 | break; |
1716 | case PORT_D: | |
1717 | port_mask = DPLL_PORTD_READY_MASK; | |
1718 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1719 | break; |
1720 | default: | |
1721 | BUG(); | |
1722 | } | |
89b667f8 | 1723 | |
370004d3 CW |
1724 | if (intel_wait_for_register(dev_priv, |
1725 | dpll_reg, port_mask, expected_mask, | |
1726 | 1000)) | |
9b6de0a1 VS |
1727 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1728 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1729 | } |
1730 | ||
b8a4f404 PZ |
1731 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1732 | enum pipe pipe) | |
040484af | 1733 | { |
98187836 VS |
1734 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
1735 | pipe); | |
f0f59a00 VS |
1736 | i915_reg_t reg; |
1737 | uint32_t val, pipeconf_val; | |
040484af | 1738 | |
040484af | 1739 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1740 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1741 | |
1742 | /* FDI must be feeding us bits for PCH ports */ | |
1743 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1744 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1745 | ||
6e266956 | 1746 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1747 | /* Workaround: Set the timing override bit before enabling the |
1748 | * pch transcoder. */ | |
1749 | reg = TRANS_CHICKEN2(pipe); | |
1750 | val = I915_READ(reg); | |
1751 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1752 | I915_WRITE(reg, val); | |
59c859d6 | 1753 | } |
23670b32 | 1754 | |
ab9412ba | 1755 | reg = PCH_TRANSCONF(pipe); |
040484af | 1756 | val = I915_READ(reg); |
5f7f726d | 1757 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1758 | |
2d1fe073 | 1759 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1760 | /* |
c5de7c6f VS |
1761 | * Make the BPC in transcoder be consistent with |
1762 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1763 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1764 | */ |
dfd07d72 | 1765 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1766 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1767 | val |= PIPECONF_8BPC; |
1768 | else | |
1769 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1770 | } |
5f7f726d PZ |
1771 | |
1772 | val &= ~TRANS_INTERLACE_MASK; | |
1773 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1774 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1775 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1776 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1777 | else | |
1778 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1779 | else |
1780 | val |= TRANS_PROGRESSIVE; | |
1781 | ||
040484af | 1782 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1783 | if (intel_wait_for_register(dev_priv, |
1784 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1785 | 100)) | |
4bb6f1f3 | 1786 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1787 | } |
1788 | ||
8fb033d7 | 1789 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1790 | enum transcoder cpu_transcoder) |
040484af | 1791 | { |
8fb033d7 | 1792 | u32 val, pipeconf_val; |
8fb033d7 | 1793 | |
8fb033d7 | 1794 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1795 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
a2196033 | 1796 | assert_fdi_rx_enabled(dev_priv, PIPE_A); |
8fb033d7 | 1797 | |
223a6fdf | 1798 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1799 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1800 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1801 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1802 | |
25f3ef11 | 1803 | val = TRANS_ENABLE; |
937bb610 | 1804 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1805 | |
9a76b1c6 PZ |
1806 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1807 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1808 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1809 | else |
1810 | val |= TRANS_PROGRESSIVE; | |
1811 | ||
ab9412ba | 1812 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1813 | if (intel_wait_for_register(dev_priv, |
1814 | LPT_TRANSCONF, | |
1815 | TRANS_STATE_ENABLE, | |
1816 | TRANS_STATE_ENABLE, | |
1817 | 100)) | |
937bb610 | 1818 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1819 | } |
1820 | ||
b8a4f404 PZ |
1821 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1822 | enum pipe pipe) | |
040484af | 1823 | { |
f0f59a00 VS |
1824 | i915_reg_t reg; |
1825 | uint32_t val; | |
040484af JB |
1826 | |
1827 | /* FDI relies on the transcoder */ | |
1828 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1829 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1830 | ||
291906f1 JB |
1831 | /* Ports must be off as well */ |
1832 | assert_pch_ports_disabled(dev_priv, pipe); | |
1833 | ||
ab9412ba | 1834 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1835 | val = I915_READ(reg); |
1836 | val &= ~TRANS_ENABLE; | |
1837 | I915_WRITE(reg, val); | |
1838 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1839 | if (intel_wait_for_register(dev_priv, |
1840 | reg, TRANS_STATE_ENABLE, 0, | |
1841 | 50)) | |
4bb6f1f3 | 1842 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1843 | |
6e266956 | 1844 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1845 | /* Workaround: Clear the timing override chicken bit again. */ |
1846 | reg = TRANS_CHICKEN2(pipe); | |
1847 | val = I915_READ(reg); | |
1848 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1849 | I915_WRITE(reg, val); | |
1850 | } | |
040484af JB |
1851 | } |
1852 | ||
b7076546 | 1853 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1854 | { |
8fb033d7 PZ |
1855 | u32 val; |
1856 | ||
ab9412ba | 1857 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1858 | val &= ~TRANS_ENABLE; |
ab9412ba | 1859 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1860 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1861 | if (intel_wait_for_register(dev_priv, |
1862 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1863 | 50)) | |
8a52fd9f | 1864 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1865 | |
1866 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1867 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1868 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1869 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1870 | } |
1871 | ||
a2196033 | 1872 | enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
65f2130c VS |
1873 | { |
1874 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1875 | ||
1876 | WARN_ON(!crtc->config->has_pch_encoder); | |
1877 | ||
1878 | if (HAS_PCH_LPT(dev_priv)) | |
a2196033 | 1879 | return PIPE_A; |
65f2130c | 1880 | else |
a2196033 | 1881 | return crtc->pipe; |
65f2130c VS |
1882 | } |
1883 | ||
b24e7179 | 1884 | /** |
309cfea8 | 1885 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1886 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1887 | * |
0372264a | 1888 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1889 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1890 | */ |
e1fdc473 | 1891 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1892 | { |
0372264a | 1893 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1894 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1895 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1896 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 1897 | i915_reg_t reg; |
b24e7179 JB |
1898 | u32 val; |
1899 | ||
9e2ee2dd VS |
1900 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1901 | ||
58c6eaa2 | 1902 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1903 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1904 | assert_sprites_disabled(dev_priv, pipe); |
1905 | ||
b24e7179 JB |
1906 | /* |
1907 | * A pipe without a PLL won't actually be able to drive bits from | |
1908 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1909 | * need the check. | |
1910 | */ | |
09fa8bb9 | 1911 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1912 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1913 | assert_dsi_pll_enabled(dev_priv); |
1914 | else | |
1915 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1916 | } else { |
6e3c9717 | 1917 | if (crtc->config->has_pch_encoder) { |
040484af | 1918 | /* if driving the PCH, we need FDI enabled */ |
65f2130c | 1919 | assert_fdi_rx_pll_enabled(dev_priv, |
a2196033 | 1920 | intel_crtc_pch_transcoder(crtc)); |
1a240d4d DV |
1921 | assert_fdi_tx_pll_enabled(dev_priv, |
1922 | (enum pipe) cpu_transcoder); | |
040484af JB |
1923 | } |
1924 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1925 | } | |
b24e7179 | 1926 | |
702e7a56 | 1927 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1928 | val = I915_READ(reg); |
7ad25d48 | 1929 | if (val & PIPECONF_ENABLE) { |
e56134bc VS |
1930 | /* we keep both pipes enabled on 830 */ |
1931 | WARN_ON(!IS_I830(dev_priv)); | |
00d70b15 | 1932 | return; |
7ad25d48 | 1933 | } |
00d70b15 CW |
1934 | |
1935 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1936 | POSTING_READ(reg); |
b7792d8b VS |
1937 | |
1938 | /* | |
1939 | * Until the pipe starts DSL will read as 0, which would cause | |
1940 | * an apparent vblank timestamp jump, which messes up also the | |
1941 | * frame count when it's derived from the timestamps. So let's | |
1942 | * wait for the pipe to start properly before we call | |
1943 | * drm_crtc_vblank_on() | |
1944 | */ | |
1945 | if (dev->max_vblank_count == 0 && | |
1946 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1947 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1948 | } |
1949 | ||
1950 | /** | |
309cfea8 | 1951 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 1952 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 1953 | * |
575f7ab7 VS |
1954 | * Disable the pipe of @crtc, making sure that various hardware |
1955 | * specific requirements are met, if applicable, e.g. plane | |
1956 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
1957 | * |
1958 | * Will wait until the pipe has shut down before returning. | |
1959 | */ | |
575f7ab7 | 1960 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1961 | { |
fac5e23e | 1962 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1963 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1964 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 1965 | i915_reg_t reg; |
b24e7179 JB |
1966 | u32 val; |
1967 | ||
9e2ee2dd VS |
1968 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
1969 | ||
b24e7179 JB |
1970 | /* |
1971 | * Make sure planes won't keep trying to pump pixels to us, | |
1972 | * or we might hang the display. | |
1973 | */ | |
1974 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1975 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1976 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 1977 | |
702e7a56 | 1978 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1979 | val = I915_READ(reg); |
00d70b15 CW |
1980 | if ((val & PIPECONF_ENABLE) == 0) |
1981 | return; | |
1982 | ||
67adc644 VS |
1983 | /* |
1984 | * Double wide has implications for planes | |
1985 | * so best keep it disabled when not needed. | |
1986 | */ | |
6e3c9717 | 1987 | if (crtc->config->double_wide) |
67adc644 VS |
1988 | val &= ~PIPECONF_DOUBLE_WIDE; |
1989 | ||
1990 | /* Don't disable pipe or pipe PLLs if needed */ | |
e56134bc | 1991 | if (!IS_I830(dev_priv)) |
67adc644 VS |
1992 | val &= ~PIPECONF_ENABLE; |
1993 | ||
1994 | I915_WRITE(reg, val); | |
1995 | if ((val & PIPECONF_ENABLE) == 0) | |
1996 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
1997 | } |
1998 | ||
832be82f VS |
1999 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2000 | { | |
2001 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2002 | } | |
2003 | ||
d88c4afd VS |
2004 | static unsigned int |
2005 | intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane) | |
7b49f948 | 2006 | { |
d88c4afd VS |
2007 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2008 | unsigned int cpp = fb->format->cpp[plane]; | |
2009 | ||
2010 | switch (fb->modifier) { | |
2f075565 | 2011 | case DRM_FORMAT_MOD_LINEAR: |
7b49f948 VS |
2012 | return cpp; |
2013 | case I915_FORMAT_MOD_X_TILED: | |
2014 | if (IS_GEN2(dev_priv)) | |
2015 | return 128; | |
2016 | else | |
2017 | return 512; | |
2e2adb05 VS |
2018 | case I915_FORMAT_MOD_Y_TILED_CCS: |
2019 | if (plane == 1) | |
2020 | return 128; | |
2021 | /* fall through */ | |
7b49f948 VS |
2022 | case I915_FORMAT_MOD_Y_TILED: |
2023 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2024 | return 128; | |
2025 | else | |
2026 | return 512; | |
2e2adb05 VS |
2027 | case I915_FORMAT_MOD_Yf_TILED_CCS: |
2028 | if (plane == 1) | |
2029 | return 128; | |
2030 | /* fall through */ | |
7b49f948 VS |
2031 | case I915_FORMAT_MOD_Yf_TILED: |
2032 | switch (cpp) { | |
2033 | case 1: | |
2034 | return 64; | |
2035 | case 2: | |
2036 | case 4: | |
2037 | return 128; | |
2038 | case 8: | |
2039 | case 16: | |
2040 | return 256; | |
2041 | default: | |
2042 | MISSING_CASE(cpp); | |
2043 | return cpp; | |
2044 | } | |
2045 | break; | |
2046 | default: | |
d88c4afd | 2047 | MISSING_CASE(fb->modifier); |
7b49f948 VS |
2048 | return cpp; |
2049 | } | |
2050 | } | |
2051 | ||
d88c4afd VS |
2052 | static unsigned int |
2053 | intel_tile_height(const struct drm_framebuffer *fb, int plane) | |
a57ce0b2 | 2054 | { |
2f075565 | 2055 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) |
832be82f VS |
2056 | return 1; |
2057 | else | |
d88c4afd VS |
2058 | return intel_tile_size(to_i915(fb->dev)) / |
2059 | intel_tile_width_bytes(fb, plane); | |
6761dd31 TU |
2060 | } |
2061 | ||
8d0deca8 | 2062 | /* Return the tile dimensions in pixel units */ |
d88c4afd | 2063 | static void intel_tile_dims(const struct drm_framebuffer *fb, int plane, |
8d0deca8 | 2064 | unsigned int *tile_width, |
d88c4afd | 2065 | unsigned int *tile_height) |
8d0deca8 | 2066 | { |
d88c4afd VS |
2067 | unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane); |
2068 | unsigned int cpp = fb->format->cpp[plane]; | |
8d0deca8 VS |
2069 | |
2070 | *tile_width = tile_width_bytes / cpp; | |
d88c4afd | 2071 | *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes; |
8d0deca8 VS |
2072 | } |
2073 | ||
6761dd31 | 2074 | unsigned int |
d88c4afd VS |
2075 | intel_fb_align_height(const struct drm_framebuffer *fb, |
2076 | int plane, unsigned int height) | |
6761dd31 | 2077 | { |
d88c4afd | 2078 | unsigned int tile_height = intel_tile_height(fb, plane); |
832be82f VS |
2079 | |
2080 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2081 | } |
2082 | ||
1663b9d6 VS |
2083 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2084 | { | |
2085 | unsigned int size = 0; | |
2086 | int i; | |
2087 | ||
2088 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2089 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2090 | ||
2091 | return size; | |
2092 | } | |
2093 | ||
75c82a53 | 2094 | static void |
3465c580 VS |
2095 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2096 | const struct drm_framebuffer *fb, | |
2097 | unsigned int rotation) | |
f64b98cd | 2098 | { |
7b92c047 | 2099 | view->type = I915_GGTT_VIEW_NORMAL; |
bd2ef25d | 2100 | if (drm_rotation_90_or_270(rotation)) { |
7b92c047 | 2101 | view->type = I915_GGTT_VIEW_ROTATED; |
8bab1193 | 2102 | view->rotated = to_intel_framebuffer(fb)->rot_info; |
2d7a215f VS |
2103 | } |
2104 | } | |
50470bb0 | 2105 | |
fabac484 VS |
2106 | static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv) |
2107 | { | |
2108 | if (IS_I830(dev_priv)) | |
2109 | return 16 * 1024; | |
2110 | else if (IS_I85X(dev_priv)) | |
2111 | return 256; | |
d9e1551e VS |
2112 | else if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
2113 | return 32; | |
fabac484 VS |
2114 | else |
2115 | return 4 * 1024; | |
2116 | } | |
2117 | ||
603525d7 | 2118 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2119 | { |
2120 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2121 | return 256 * 1024; | |
c0f86832 | 2122 | else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || |
666a4537 | 2123 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2124 | return 128 * 1024; |
2125 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2126 | return 4 * 1024; | |
2127 | else | |
44c5905e | 2128 | return 0; |
4e9a86b6 VS |
2129 | } |
2130 | ||
d88c4afd VS |
2131 | static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, |
2132 | int plane) | |
603525d7 | 2133 | { |
d88c4afd VS |
2134 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2135 | ||
b90c1ee1 | 2136 | /* AUX_DIST needs only 4K alignment */ |
2e2adb05 | 2137 | if (plane == 1) |
b90c1ee1 VS |
2138 | return 4096; |
2139 | ||
d88c4afd | 2140 | switch (fb->modifier) { |
2f075565 | 2141 | case DRM_FORMAT_MOD_LINEAR: |
603525d7 VS |
2142 | return intel_linear_alignment(dev_priv); |
2143 | case I915_FORMAT_MOD_X_TILED: | |
d88c4afd | 2144 | if (INTEL_GEN(dev_priv) >= 9) |
603525d7 VS |
2145 | return 256 * 1024; |
2146 | return 0; | |
2e2adb05 VS |
2147 | case I915_FORMAT_MOD_Y_TILED_CCS: |
2148 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
603525d7 VS |
2149 | case I915_FORMAT_MOD_Y_TILED: |
2150 | case I915_FORMAT_MOD_Yf_TILED: | |
2151 | return 1 * 1024 * 1024; | |
2152 | default: | |
d88c4afd | 2153 | MISSING_CASE(fb->modifier); |
603525d7 VS |
2154 | return 0; |
2155 | } | |
2156 | } | |
2157 | ||
058d88c4 CW |
2158 | struct i915_vma * |
2159 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2160 | { |
850c4cdc | 2161 | struct drm_device *dev = fb->dev; |
fac5e23e | 2162 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2163 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2164 | struct i915_ggtt_view view; |
058d88c4 | 2165 | struct i915_vma *vma; |
6b95a207 | 2166 | u32 alignment; |
6b95a207 | 2167 | |
ebcdd39e MR |
2168 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2169 | ||
d88c4afd | 2170 | alignment = intel_surf_alignment(fb, 0); |
6b95a207 | 2171 | |
3465c580 | 2172 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2173 | |
693db184 CW |
2174 | /* Note that the w/a also requires 64 PTE of padding following the |
2175 | * bo. We currently fill all unused PTE with the shadow page and so | |
2176 | * we should always have valid PTE following the scanout preventing | |
2177 | * the VT-d warning. | |
2178 | */ | |
48f112fe | 2179 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2180 | alignment = 256 * 1024; |
2181 | ||
d6dd6843 PZ |
2182 | /* |
2183 | * Global gtt pte registers are special registers which actually forward | |
2184 | * writes to a chunk of system memory. Which means that there is no risk | |
2185 | * that the register values disappear as soon as we call | |
2186 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2187 | * pin/unpin/fence and not more. | |
2188 | */ | |
2189 | intel_runtime_pm_get(dev_priv); | |
2190 | ||
9db529aa DV |
2191 | atomic_inc(&dev_priv->gpu_error.pending_fb_pin); |
2192 | ||
058d88c4 | 2193 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2194 | if (IS_ERR(vma)) |
2195 | goto err; | |
6b95a207 | 2196 | |
05a20d09 | 2197 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2198 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2199 | * fence, whereas 965+ only requires a fence if using | |
2200 | * framebuffer compression. For simplicity, we always, when | |
2201 | * possible, install a fence as the cost is not that onerous. | |
2202 | * | |
2203 | * If we fail to fence the tiled scanout, then either the | |
2204 | * modeset will reject the change (which is highly unlikely as | |
2205 | * the affected systems, all but one, do not have unmappable | |
2206 | * space) or we will not be able to enable full powersaving | |
2207 | * techniques (also likely not to apply due to various limits | |
2208 | * FBC and the like impose on the size of the buffer, which | |
2209 | * presumably we violated anyway with this unmappable buffer). | |
2210 | * Anyway, it is presumably better to stumble onwards with | |
2211 | * something and try to run the system in a "less than optimal" | |
2212 | * mode that matches the user configuration. | |
2213 | */ | |
3bd40735 | 2214 | i915_vma_pin_fence(vma); |
9807216f | 2215 | } |
6b95a207 | 2216 | |
be1e3415 | 2217 | i915_vma_get(vma); |
49ef5294 | 2218 | err: |
9db529aa DV |
2219 | atomic_dec(&dev_priv->gpu_error.pending_fb_pin); |
2220 | ||
d6dd6843 | 2221 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2222 | return vma; |
6b95a207 KH |
2223 | } |
2224 | ||
be1e3415 | 2225 | void intel_unpin_fb_vma(struct i915_vma *vma) |
1690e1eb | 2226 | { |
be1e3415 | 2227 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
f64b98cd | 2228 | |
49ef5294 | 2229 | i915_vma_unpin_fence(vma); |
058d88c4 | 2230 | i915_gem_object_unpin_from_display_plane(vma); |
be1e3415 | 2231 | i915_vma_put(vma); |
1690e1eb CW |
2232 | } |
2233 | ||
ef78ec94 VS |
2234 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2235 | unsigned int rotation) | |
2236 | { | |
bd2ef25d | 2237 | if (drm_rotation_90_or_270(rotation)) |
ef78ec94 VS |
2238 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
2239 | else | |
2240 | return fb->pitches[plane]; | |
2241 | } | |
2242 | ||
6687c906 VS |
2243 | /* |
2244 | * Convert the x/y offsets into a linear offset. | |
2245 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2246 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2247 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2248 | */ | |
2249 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2250 | const struct intel_plane_state *state, |
2251 | int plane) | |
6687c906 | 2252 | { |
2949056c | 2253 | const struct drm_framebuffer *fb = state->base.fb; |
353c8598 | 2254 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2255 | unsigned int pitch = fb->pitches[plane]; |
2256 | ||
2257 | return y * pitch + x * cpp; | |
2258 | } | |
2259 | ||
2260 | /* | |
2261 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2262 | * specified plane src x/y offsets. The resulting x/y offsets | |
2263 | * specify the start of scanout from the beginning of the gtt mapping. | |
2264 | */ | |
2265 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2266 | const struct intel_plane_state *state, |
2267 | int plane) | |
6687c906 VS |
2268 | |
2269 | { | |
2949056c VS |
2270 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2271 | unsigned int rotation = state->base.rotation; | |
6687c906 | 2272 | |
bd2ef25d | 2273 | if (drm_rotation_90_or_270(rotation)) { |
6687c906 VS |
2274 | *x += intel_fb->rotated[plane].x; |
2275 | *y += intel_fb->rotated[plane].y; | |
2276 | } else { | |
2277 | *x += intel_fb->normal[plane].x; | |
2278 | *y += intel_fb->normal[plane].y; | |
2279 | } | |
2280 | } | |
2281 | ||
e8837d98 VS |
2282 | static u32 __intel_adjust_tile_offset(int *x, int *y, |
2283 | unsigned int tile_width, | |
2284 | unsigned int tile_height, | |
2285 | unsigned int tile_size, | |
2286 | unsigned int pitch_tiles, | |
2287 | u32 old_offset, | |
2288 | u32 new_offset) | |
29cf9491 | 2289 | { |
b9b24038 | 2290 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2291 | unsigned int tiles; |
2292 | ||
2293 | WARN_ON(old_offset & (tile_size - 1)); | |
2294 | WARN_ON(new_offset & (tile_size - 1)); | |
2295 | WARN_ON(new_offset > old_offset); | |
2296 | ||
2297 | tiles = (old_offset - new_offset) / tile_size; | |
2298 | ||
2299 | *y += tiles / pitch_tiles * tile_height; | |
2300 | *x += tiles % pitch_tiles * tile_width; | |
2301 | ||
b9b24038 VS |
2302 | /* minimize x in case it got needlessly big */ |
2303 | *y += *x / pitch_pixels * tile_height; | |
2304 | *x %= pitch_pixels; | |
2305 | ||
29cf9491 VS |
2306 | return new_offset; |
2307 | } | |
2308 | ||
e8837d98 VS |
2309 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2310 | const struct drm_framebuffer *fb, int plane, | |
2311 | unsigned int rotation, | |
2312 | u32 old_offset, u32 new_offset) | |
66a2d927 | 2313 | { |
e8837d98 | 2314 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); |
353c8598 | 2315 | unsigned int cpp = fb->format->cpp[plane]; |
66a2d927 VS |
2316 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); |
2317 | ||
2318 | WARN_ON(new_offset > old_offset); | |
2319 | ||
2f075565 | 2320 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
66a2d927 VS |
2321 | unsigned int tile_size, tile_width, tile_height; |
2322 | unsigned int pitch_tiles; | |
2323 | ||
2324 | tile_size = intel_tile_size(dev_priv); | |
d88c4afd | 2325 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
66a2d927 | 2326 | |
bd2ef25d | 2327 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2328 | pitch_tiles = pitch / tile_height; |
2329 | swap(tile_width, tile_height); | |
2330 | } else { | |
2331 | pitch_tiles = pitch / (tile_width * cpp); | |
2332 | } | |
2333 | ||
e8837d98 VS |
2334 | __intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2335 | tile_size, pitch_tiles, | |
2336 | old_offset, new_offset); | |
66a2d927 VS |
2337 | } else { |
2338 | old_offset += *y * pitch + *x * cpp; | |
2339 | ||
2340 | *y = (old_offset - new_offset) / pitch; | |
2341 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2342 | } | |
2343 | ||
2344 | return new_offset; | |
2345 | } | |
2346 | ||
e8837d98 VS |
2347 | /* |
2348 | * Adjust the tile offset by moving the difference into | |
2349 | * the x/y offsets. | |
2350 | */ | |
2351 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2352 | const struct intel_plane_state *state, int plane, | |
2353 | u32 old_offset, u32 new_offset) | |
2354 | { | |
2355 | return _intel_adjust_tile_offset(x, y, state->base.fb, plane, | |
2356 | state->base.rotation, | |
2357 | old_offset, new_offset); | |
2358 | } | |
2359 | ||
8d0deca8 VS |
2360 | /* |
2361 | * Computes the linear offset to the base tile and adjusts | |
2362 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2363 | * | |
2364 | * In the 90/270 rotated case, x and y are assumed | |
2365 | * to be already rotated to match the rotated GTT view, and | |
2366 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2367 | * |
2368 | * This function is used when computing the derived information | |
2369 | * under intel_framebuffer, so using any of that information | |
2370 | * here is not allowed. Anything under drm_framebuffer can be | |
2371 | * used. This is why the user has to pass in the pitch since it | |
2372 | * is specified in the rotated orientation. | |
8d0deca8 | 2373 | */ |
6687c906 VS |
2374 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2375 | int *x, int *y, | |
2376 | const struct drm_framebuffer *fb, int plane, | |
2377 | unsigned int pitch, | |
2378 | unsigned int rotation, | |
2379 | u32 alignment) | |
c2c75131 | 2380 | { |
bae781b2 | 2381 | uint64_t fb_modifier = fb->modifier; |
353c8598 | 2382 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 | 2383 | u32 offset, offset_aligned; |
29cf9491 | 2384 | |
29cf9491 VS |
2385 | if (alignment) |
2386 | alignment--; | |
2387 | ||
2f075565 | 2388 | if (fb_modifier != DRM_FORMAT_MOD_LINEAR) { |
8d0deca8 VS |
2389 | unsigned int tile_size, tile_width, tile_height; |
2390 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2391 | |
d843310d | 2392 | tile_size = intel_tile_size(dev_priv); |
d88c4afd | 2393 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
8d0deca8 | 2394 | |
bd2ef25d | 2395 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2396 | pitch_tiles = pitch / tile_height; |
2397 | swap(tile_width, tile_height); | |
2398 | } else { | |
2399 | pitch_tiles = pitch / (tile_width * cpp); | |
2400 | } | |
d843310d VS |
2401 | |
2402 | tile_rows = *y / tile_height; | |
2403 | *y %= tile_height; | |
c2c75131 | 2404 | |
8d0deca8 VS |
2405 | tiles = *x / tile_width; |
2406 | *x %= tile_width; | |
bc752862 | 2407 | |
29cf9491 VS |
2408 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2409 | offset_aligned = offset & ~alignment; | |
bc752862 | 2410 | |
e8837d98 VS |
2411 | __intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2412 | tile_size, pitch_tiles, | |
2413 | offset, offset_aligned); | |
29cf9491 | 2414 | } else { |
bc752862 | 2415 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2416 | offset_aligned = offset & ~alignment; |
2417 | ||
4e9a86b6 VS |
2418 | *y = (offset & alignment) / pitch; |
2419 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2420 | } |
29cf9491 VS |
2421 | |
2422 | return offset_aligned; | |
c2c75131 DV |
2423 | } |
2424 | ||
6687c906 | 2425 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2426 | const struct intel_plane_state *state, |
2427 | int plane) | |
6687c906 | 2428 | { |
1e7b4fd8 VS |
2429 | struct intel_plane *intel_plane = to_intel_plane(state->base.plane); |
2430 | struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); | |
2949056c VS |
2431 | const struct drm_framebuffer *fb = state->base.fb; |
2432 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2433 | int pitch = intel_fb_pitch(fb, plane, rotation); |
1e7b4fd8 VS |
2434 | u32 alignment; |
2435 | ||
2436 | if (intel_plane->id == PLANE_CURSOR) | |
2437 | alignment = intel_cursor_alignment(dev_priv); | |
2438 | else | |
2439 | alignment = intel_surf_alignment(fb, plane); | |
6687c906 VS |
2440 | |
2441 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2442 | rotation, alignment); | |
2443 | } | |
2444 | ||
e8837d98 VS |
2445 | /* Convert the fb->offset[] into x/y offsets */ |
2446 | static int intel_fb_offset_to_xy(int *x, int *y, | |
2447 | const struct drm_framebuffer *fb, int plane) | |
6687c906 | 2448 | { |
e8837d98 VS |
2449 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2450 | ||
2451 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR && | |
2452 | fb->offsets[plane] % intel_tile_size(dev_priv)) | |
2453 | return -EINVAL; | |
2454 | ||
2455 | *x = 0; | |
2456 | *y = 0; | |
6687c906 | 2457 | |
e8837d98 VS |
2458 | _intel_adjust_tile_offset(x, y, |
2459 | fb, plane, DRM_MODE_ROTATE_0, | |
2460 | fb->offsets[plane], 0); | |
2461 | ||
2462 | return 0; | |
6687c906 VS |
2463 | } |
2464 | ||
72618ebf VS |
2465 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2466 | { | |
2467 | switch (fb_modifier) { | |
2468 | case I915_FORMAT_MOD_X_TILED: | |
2469 | return I915_TILING_X; | |
2470 | case I915_FORMAT_MOD_Y_TILED: | |
2e2adb05 | 2471 | case I915_FORMAT_MOD_Y_TILED_CCS: |
72618ebf VS |
2472 | return I915_TILING_Y; |
2473 | default: | |
2474 | return I915_TILING_NONE; | |
2475 | } | |
2476 | } | |
2477 | ||
bbfb6ce8 VS |
2478 | static const struct drm_format_info ccs_formats[] = { |
2479 | { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2480 | { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2481 | { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2482 | { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2483 | }; | |
2484 | ||
2485 | static const struct drm_format_info * | |
2486 | lookup_format_info(const struct drm_format_info formats[], | |
2487 | int num_formats, u32 format) | |
2488 | { | |
2489 | int i; | |
2490 | ||
2491 | for (i = 0; i < num_formats; i++) { | |
2492 | if (formats[i].format == format) | |
2493 | return &formats[i]; | |
2494 | } | |
2495 | ||
2496 | return NULL; | |
2497 | } | |
2498 | ||
2499 | static const struct drm_format_info * | |
2500 | intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) | |
2501 | { | |
2502 | switch (cmd->modifier[0]) { | |
2503 | case I915_FORMAT_MOD_Y_TILED_CCS: | |
2504 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
2505 | return lookup_format_info(ccs_formats, | |
2506 | ARRAY_SIZE(ccs_formats), | |
2507 | cmd->pixel_format); | |
2508 | default: | |
2509 | return NULL; | |
2510 | } | |
2511 | } | |
2512 | ||
6687c906 VS |
2513 | static int |
2514 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2515 | struct drm_framebuffer *fb) | |
2516 | { | |
2517 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2518 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2519 | u32 gtt_offset_rotated = 0; | |
2520 | unsigned int max_size = 0; | |
bcb0b461 | 2521 | int i, num_planes = fb->format->num_planes; |
6687c906 VS |
2522 | unsigned int tile_size = intel_tile_size(dev_priv); |
2523 | ||
2524 | for (i = 0; i < num_planes; i++) { | |
2525 | unsigned int width, height; | |
2526 | unsigned int cpp, size; | |
2527 | u32 offset; | |
2528 | int x, y; | |
e8837d98 | 2529 | int ret; |
6687c906 | 2530 | |
353c8598 | 2531 | cpp = fb->format->cpp[i]; |
145fcb11 VS |
2532 | width = drm_framebuffer_plane_width(fb->width, fb, i); |
2533 | height = drm_framebuffer_plane_height(fb->height, fb, i); | |
6687c906 | 2534 | |
e8837d98 VS |
2535 | ret = intel_fb_offset_to_xy(&x, &y, fb, i); |
2536 | if (ret) { | |
2537 | DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", | |
2538 | i, fb->offsets[i]); | |
2539 | return ret; | |
2540 | } | |
6687c906 | 2541 | |
2e2adb05 VS |
2542 | if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || |
2543 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) { | |
2544 | int hsub = fb->format->hsub; | |
2545 | int vsub = fb->format->vsub; | |
2546 | int tile_width, tile_height; | |
2547 | int main_x, main_y; | |
2548 | int ccs_x, ccs_y; | |
2549 | ||
2550 | intel_tile_dims(fb, i, &tile_width, &tile_height); | |
e8837d98 VS |
2551 | tile_width *= hsub; |
2552 | tile_height *= vsub; | |
2e2adb05 | 2553 | |
e8837d98 VS |
2554 | ccs_x = (x * hsub) % tile_width; |
2555 | ccs_y = (y * vsub) % tile_height; | |
2556 | main_x = intel_fb->normal[0].x % tile_width; | |
2557 | main_y = intel_fb->normal[0].y % tile_height; | |
2e2adb05 VS |
2558 | |
2559 | /* | |
2560 | * CCS doesn't have its own x/y offset register, so the intra CCS tile | |
2561 | * x/y offsets must match between CCS and the main surface. | |
2562 | */ | |
2563 | if (main_x != ccs_x || main_y != ccs_y) { | |
2564 | DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", | |
2565 | main_x, main_y, | |
2566 | ccs_x, ccs_y, | |
2567 | intel_fb->normal[0].x, | |
2568 | intel_fb->normal[0].y, | |
2569 | x, y); | |
2570 | return -EINVAL; | |
2571 | } | |
2572 | } | |
2573 | ||
60d5f2a4 VS |
2574 | /* |
2575 | * The fence (if used) is aligned to the start of the object | |
2576 | * so having the framebuffer wrap around across the edge of the | |
2577 | * fenced region doesn't really work. We have no API to configure | |
2578 | * the fence start offset within the object (nor could we probably | |
2579 | * on gen2/3). So it's just easier if we just require that the | |
2580 | * fb layout agrees with the fence layout. We already check that the | |
2581 | * fb stride matches the fence stride elsewhere. | |
2582 | */ | |
18db229d | 2583 | if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) && |
60d5f2a4 | 2584 | (x + width) * cpp > fb->pitches[i]) { |
144cc143 VS |
2585 | DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", |
2586 | i, fb->offsets[i]); | |
60d5f2a4 VS |
2587 | return -EINVAL; |
2588 | } | |
2589 | ||
6687c906 VS |
2590 | /* |
2591 | * First pixel of the framebuffer from | |
2592 | * the start of the normal gtt mapping. | |
2593 | */ | |
2594 | intel_fb->normal[i].x = x; | |
2595 | intel_fb->normal[i].y = y; | |
2596 | ||
2597 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
3ca46c0a | 2598 | fb, i, fb->pitches[i], |
c2c446ad | 2599 | DRM_MODE_ROTATE_0, tile_size); |
6687c906 VS |
2600 | offset /= tile_size; |
2601 | ||
2f075565 | 2602 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
6687c906 VS |
2603 | unsigned int tile_width, tile_height; |
2604 | unsigned int pitch_tiles; | |
2605 | struct drm_rect r; | |
2606 | ||
d88c4afd | 2607 | intel_tile_dims(fb, i, &tile_width, &tile_height); |
6687c906 VS |
2608 | |
2609 | rot_info->plane[i].offset = offset; | |
2610 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2611 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2612 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2613 | ||
2614 | intel_fb->rotated[i].pitch = | |
2615 | rot_info->plane[i].height * tile_height; | |
2616 | ||
2617 | /* how many tiles does this plane need */ | |
2618 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2619 | /* | |
2620 | * If the plane isn't horizontally tile aligned, | |
2621 | * we need one more tile. | |
2622 | */ | |
2623 | if (x != 0) | |
2624 | size++; | |
2625 | ||
2626 | /* rotate the x/y offsets to match the GTT view */ | |
2627 | r.x1 = x; | |
2628 | r.y1 = y; | |
2629 | r.x2 = x + width; | |
2630 | r.y2 = y + height; | |
2631 | drm_rect_rotate(&r, | |
2632 | rot_info->plane[i].width * tile_width, | |
2633 | rot_info->plane[i].height * tile_height, | |
c2c446ad | 2634 | DRM_MODE_ROTATE_270); |
6687c906 VS |
2635 | x = r.x1; |
2636 | y = r.y1; | |
2637 | ||
2638 | /* rotate the tile dimensions to match the GTT view */ | |
2639 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2640 | swap(tile_width, tile_height); | |
2641 | ||
2642 | /* | |
2643 | * We only keep the x/y offsets, so push all of the | |
2644 | * gtt offset into the x/y offsets. | |
2645 | */ | |
e8837d98 VS |
2646 | __intel_adjust_tile_offset(&x, &y, |
2647 | tile_width, tile_height, | |
2648 | tile_size, pitch_tiles, | |
2649 | gtt_offset_rotated * tile_size, 0); | |
6687c906 VS |
2650 | |
2651 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2652 | ||
2653 | /* | |
2654 | * First pixel of the framebuffer from | |
2655 | * the start of the rotated gtt mapping. | |
2656 | */ | |
2657 | intel_fb->rotated[i].x = x; | |
2658 | intel_fb->rotated[i].y = y; | |
2659 | } else { | |
2660 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2661 | x * cpp, tile_size); | |
2662 | } | |
2663 | ||
2664 | /* how many tiles in total needed in the bo */ | |
2665 | max_size = max(max_size, offset + size); | |
2666 | } | |
2667 | ||
144cc143 VS |
2668 | if (max_size * tile_size > intel_fb->obj->base.size) { |
2669 | DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2670 | max_size * tile_size, intel_fb->obj->base.size); | |
6687c906 VS |
2671 | return -EINVAL; |
2672 | } | |
2673 | ||
2674 | return 0; | |
2675 | } | |
2676 | ||
b35d63fa | 2677 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2678 | { |
2679 | switch (format) { | |
2680 | case DISPPLANE_8BPP: | |
2681 | return DRM_FORMAT_C8; | |
2682 | case DISPPLANE_BGRX555: | |
2683 | return DRM_FORMAT_XRGB1555; | |
2684 | case DISPPLANE_BGRX565: | |
2685 | return DRM_FORMAT_RGB565; | |
2686 | default: | |
2687 | case DISPPLANE_BGRX888: | |
2688 | return DRM_FORMAT_XRGB8888; | |
2689 | case DISPPLANE_RGBX888: | |
2690 | return DRM_FORMAT_XBGR8888; | |
2691 | case DISPPLANE_BGRX101010: | |
2692 | return DRM_FORMAT_XRGB2101010; | |
2693 | case DISPPLANE_RGBX101010: | |
2694 | return DRM_FORMAT_XBGR2101010; | |
2695 | } | |
2696 | } | |
2697 | ||
bc8d7dff DL |
2698 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2699 | { | |
2700 | switch (format) { | |
2701 | case PLANE_CTL_FORMAT_RGB_565: | |
2702 | return DRM_FORMAT_RGB565; | |
2703 | default: | |
2704 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2705 | if (rgb_order) { | |
2706 | if (alpha) | |
2707 | return DRM_FORMAT_ABGR8888; | |
2708 | else | |
2709 | return DRM_FORMAT_XBGR8888; | |
2710 | } else { | |
2711 | if (alpha) | |
2712 | return DRM_FORMAT_ARGB8888; | |
2713 | else | |
2714 | return DRM_FORMAT_XRGB8888; | |
2715 | } | |
2716 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2717 | if (rgb_order) | |
2718 | return DRM_FORMAT_XBGR2101010; | |
2719 | else | |
2720 | return DRM_FORMAT_XRGB2101010; | |
2721 | } | |
2722 | } | |
2723 | ||
5724dbd1 | 2724 | static bool |
f6936e29 DV |
2725 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2726 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2727 | { |
2728 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2729 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2730 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2731 | struct drm_i915_gem_object *obj = NULL; |
2732 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2733 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2734 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2735 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2736 | PAGE_SIZE); | |
2737 | ||
2738 | size_aligned -= base_aligned; | |
46f297fb | 2739 | |
ff2652ea CW |
2740 | if (plane_config->size == 0) |
2741 | return false; | |
2742 | ||
3badb49f PZ |
2743 | /* If the FB is too big, just don't use it since fbdev is not very |
2744 | * important and we should probably use that space with FBC or other | |
2745 | * features. */ | |
72e96d64 | 2746 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2747 | return false; |
2748 | ||
12c83d99 | 2749 | mutex_lock(&dev->struct_mutex); |
187685cb | 2750 | obj = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
f37b5c2b DV |
2751 | base_aligned, |
2752 | base_aligned, | |
2753 | size_aligned); | |
24dbf51a CW |
2754 | mutex_unlock(&dev->struct_mutex); |
2755 | if (!obj) | |
484b41dd | 2756 | return false; |
46f297fb | 2757 | |
3e510a8e CW |
2758 | if (plane_config->tiling == I915_TILING_X) |
2759 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2760 | |
438b74a5 | 2761 | mode_cmd.pixel_format = fb->format->format; |
6bf129df DL |
2762 | mode_cmd.width = fb->width; |
2763 | mode_cmd.height = fb->height; | |
2764 | mode_cmd.pitches[0] = fb->pitches[0]; | |
bae781b2 | 2765 | mode_cmd.modifier[0] = fb->modifier; |
18c5247e | 2766 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
46f297fb | 2767 | |
24dbf51a | 2768 | if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) { |
46f297fb JB |
2769 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2770 | goto out_unref_obj; | |
2771 | } | |
12c83d99 | 2772 | |
484b41dd | 2773 | |
f6936e29 | 2774 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2775 | return true; |
46f297fb JB |
2776 | |
2777 | out_unref_obj: | |
f8c417cd | 2778 | i915_gem_object_put(obj); |
484b41dd JB |
2779 | return false; |
2780 | } | |
2781 | ||
e9728bd8 VS |
2782 | static void |
2783 | intel_set_plane_visible(struct intel_crtc_state *crtc_state, | |
2784 | struct intel_plane_state *plane_state, | |
2785 | bool visible) | |
2786 | { | |
2787 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
2788 | ||
2789 | plane_state->base.visible = visible; | |
2790 | ||
2791 | /* FIXME pre-g4x don't work like this */ | |
2792 | if (visible) { | |
2793 | crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base)); | |
2794 | crtc_state->active_planes |= BIT(plane->id); | |
2795 | } else { | |
2796 | crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base)); | |
2797 | crtc_state->active_planes &= ~BIT(plane->id); | |
2798 | } | |
2799 | ||
2800 | DRM_DEBUG_KMS("%s active planes 0x%x\n", | |
2801 | crtc_state->base.crtc->name, | |
2802 | crtc_state->active_planes); | |
2803 | } | |
2804 | ||
5724dbd1 | 2805 | static void |
f6936e29 DV |
2806 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2807 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2808 | { |
2809 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2810 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 2811 | struct drm_crtc *c; |
2ff8fde1 | 2812 | struct drm_i915_gem_object *obj; |
88595ac9 | 2813 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2814 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2815 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2816 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2817 | struct intel_plane_state *intel_state = |
2818 | to_intel_plane_state(plane_state); | |
88595ac9 | 2819 | struct drm_framebuffer *fb; |
484b41dd | 2820 | |
2d14030b | 2821 | if (!plane_config->fb) |
484b41dd JB |
2822 | return; |
2823 | ||
f6936e29 | 2824 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2825 | fb = &plane_config->fb->base; |
2826 | goto valid_fb; | |
f55548b5 | 2827 | } |
484b41dd | 2828 | |
2d14030b | 2829 | kfree(plane_config->fb); |
484b41dd JB |
2830 | |
2831 | /* | |
2832 | * Failed to alloc the obj, check to see if we should share | |
2833 | * an fb with another CRTC instead | |
2834 | */ | |
70e1e0ec | 2835 | for_each_crtc(dev, c) { |
be1e3415 | 2836 | struct intel_plane_state *state; |
484b41dd JB |
2837 | |
2838 | if (c == &intel_crtc->base) | |
2839 | continue; | |
2840 | ||
be1e3415 | 2841 | if (!to_intel_crtc(c)->active) |
2ff8fde1 MR |
2842 | continue; |
2843 | ||
be1e3415 CW |
2844 | state = to_intel_plane_state(c->primary->state); |
2845 | if (!state->vma) | |
484b41dd JB |
2846 | continue; |
2847 | ||
be1e3415 CW |
2848 | if (intel_plane_ggtt_offset(state) == plane_config->base) { |
2849 | fb = c->primary->fb; | |
c3ed1103 | 2850 | drm_framebuffer_get(fb); |
88595ac9 | 2851 | goto valid_fb; |
484b41dd JB |
2852 | } |
2853 | } | |
88595ac9 | 2854 | |
200757f5 MR |
2855 | /* |
2856 | * We've failed to reconstruct the BIOS FB. Current display state | |
2857 | * indicates that the primary plane is visible, but has a NULL FB, | |
2858 | * which will lead to problems later if we don't fix it up. The | |
2859 | * simplest solution is to just disable the primary plane now and | |
2860 | * pretend the BIOS never had it enabled. | |
2861 | */ | |
e9728bd8 VS |
2862 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), |
2863 | to_intel_plane_state(plane_state), | |
2864 | false); | |
2622a081 | 2865 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
72259536 | 2866 | trace_intel_disable_plane(primary, intel_crtc); |
282dbf9b | 2867 | intel_plane->disable_plane(intel_plane, intel_crtc); |
200757f5 | 2868 | |
88595ac9 DV |
2869 | return; |
2870 | ||
2871 | valid_fb: | |
be1e3415 CW |
2872 | mutex_lock(&dev->struct_mutex); |
2873 | intel_state->vma = | |
2874 | intel_pin_and_fence_fb_obj(fb, primary->state->rotation); | |
2875 | mutex_unlock(&dev->struct_mutex); | |
2876 | if (IS_ERR(intel_state->vma)) { | |
2877 | DRM_ERROR("failed to pin boot fb on pipe %d: %li\n", | |
2878 | intel_crtc->pipe, PTR_ERR(intel_state->vma)); | |
2879 | ||
2880 | intel_state->vma = NULL; | |
c3ed1103 | 2881 | drm_framebuffer_put(fb); |
be1e3415 CW |
2882 | return; |
2883 | } | |
2884 | ||
f44e2659 VS |
2885 | plane_state->src_x = 0; |
2886 | plane_state->src_y = 0; | |
be5651f2 ML |
2887 | plane_state->src_w = fb->width << 16; |
2888 | plane_state->src_h = fb->height << 16; | |
2889 | ||
f44e2659 VS |
2890 | plane_state->crtc_x = 0; |
2891 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2892 | plane_state->crtc_w = fb->width; |
2893 | plane_state->crtc_h = fb->height; | |
2894 | ||
1638d30c RC |
2895 | intel_state->base.src = drm_plane_state_src(plane_state); |
2896 | intel_state->base.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 2897 | |
88595ac9 | 2898 | obj = intel_fb_obj(fb); |
3e510a8e | 2899 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2900 | dev_priv->preserve_bios_swizzle = true; |
2901 | ||
c3ed1103 | 2902 | drm_framebuffer_get(fb); |
be5651f2 | 2903 | primary->fb = primary->state->fb = fb; |
36750f28 | 2904 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
e9728bd8 VS |
2905 | |
2906 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), | |
2907 | to_intel_plane_state(plane_state), | |
2908 | true); | |
2909 | ||
faf5bf0a CW |
2910 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2911 | &obj->frontbuffer_bits); | |
46f297fb JB |
2912 | } |
2913 | ||
b63a16f6 VS |
2914 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2915 | unsigned int rotation) | |
2916 | { | |
353c8598 | 2917 | int cpp = fb->format->cpp[plane]; |
b63a16f6 | 2918 | |
bae781b2 | 2919 | switch (fb->modifier) { |
2f075565 | 2920 | case DRM_FORMAT_MOD_LINEAR: |
b63a16f6 VS |
2921 | case I915_FORMAT_MOD_X_TILED: |
2922 | switch (cpp) { | |
2923 | case 8: | |
2924 | return 4096; | |
2925 | case 4: | |
2926 | case 2: | |
2927 | case 1: | |
2928 | return 8192; | |
2929 | default: | |
2930 | MISSING_CASE(cpp); | |
2931 | break; | |
2932 | } | |
2933 | break; | |
2e2adb05 VS |
2934 | case I915_FORMAT_MOD_Y_TILED_CCS: |
2935 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
2936 | /* FIXME AUX plane? */ | |
b63a16f6 VS |
2937 | case I915_FORMAT_MOD_Y_TILED: |
2938 | case I915_FORMAT_MOD_Yf_TILED: | |
2939 | switch (cpp) { | |
2940 | case 8: | |
2941 | return 2048; | |
2942 | case 4: | |
2943 | return 4096; | |
2944 | case 2: | |
2945 | case 1: | |
2946 | return 8192; | |
2947 | default: | |
2948 | MISSING_CASE(cpp); | |
2949 | break; | |
2950 | } | |
2951 | break; | |
2952 | default: | |
bae781b2 | 2953 | MISSING_CASE(fb->modifier); |
b63a16f6 VS |
2954 | } |
2955 | ||
2956 | return 2048; | |
2957 | } | |
2958 | ||
2e2adb05 VS |
2959 | static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, |
2960 | int main_x, int main_y, u32 main_offset) | |
2961 | { | |
2962 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2963 | int hsub = fb->format->hsub; | |
2964 | int vsub = fb->format->vsub; | |
2965 | int aux_x = plane_state->aux.x; | |
2966 | int aux_y = plane_state->aux.y; | |
2967 | u32 aux_offset = plane_state->aux.offset; | |
2968 | u32 alignment = intel_surf_alignment(fb, 1); | |
2969 | ||
2970 | while (aux_offset >= main_offset && aux_y <= main_y) { | |
2971 | int x, y; | |
2972 | ||
2973 | if (aux_x == main_x && aux_y == main_y) | |
2974 | break; | |
2975 | ||
2976 | if (aux_offset == 0) | |
2977 | break; | |
2978 | ||
2979 | x = aux_x / hsub; | |
2980 | y = aux_y / vsub; | |
2981 | aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1, | |
2982 | aux_offset, aux_offset - alignment); | |
2983 | aux_x = x * hsub + aux_x % hsub; | |
2984 | aux_y = y * vsub + aux_y % vsub; | |
2985 | } | |
2986 | ||
2987 | if (aux_x != main_x || aux_y != main_y) | |
2988 | return false; | |
2989 | ||
2990 | plane_state->aux.offset = aux_offset; | |
2991 | plane_state->aux.x = aux_x; | |
2992 | plane_state->aux.y = aux_y; | |
2993 | ||
2994 | return true; | |
2995 | } | |
2996 | ||
b63a16f6 VS |
2997 | static int skl_check_main_surface(struct intel_plane_state *plane_state) |
2998 | { | |
b63a16f6 VS |
2999 | const struct drm_framebuffer *fb = plane_state->base.fb; |
3000 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
3001 | int x = plane_state->base.src.x1 >> 16; |
3002 | int y = plane_state->base.src.y1 >> 16; | |
3003 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
3004 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
3005 | int max_width = skl_max_plane_width(fb, 0, rotation); |
3006 | int max_height = 4096; | |
8d970654 | 3007 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
3008 | |
3009 | if (w > max_width || h > max_height) { | |
3010 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
3011 | w, h, max_width, max_height); | |
3012 | return -EINVAL; | |
3013 | } | |
3014 | ||
3015 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
3016 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
d88c4afd | 3017 | alignment = intel_surf_alignment(fb, 0); |
b63a16f6 | 3018 | |
8d970654 VS |
3019 | /* |
3020 | * AUX surface offset is specified as the distance from the | |
3021 | * main surface offset, and it must be non-negative. Make | |
3022 | * sure that is what we will get. | |
3023 | */ | |
3024 | if (offset > aux_offset) | |
3025 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
3026 | offset, aux_offset & ~(alignment - 1)); | |
3027 | ||
b63a16f6 VS |
3028 | /* |
3029 | * When using an X-tiled surface, the plane blows up | |
3030 | * if the x offset + width exceed the stride. | |
3031 | * | |
3032 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
3033 | */ | |
bae781b2 | 3034 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) { |
353c8598 | 3035 | int cpp = fb->format->cpp[0]; |
b63a16f6 VS |
3036 | |
3037 | while ((x + w) * cpp > fb->pitches[0]) { | |
3038 | if (offset == 0) { | |
2e2adb05 | 3039 | DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n"); |
b63a16f6 VS |
3040 | return -EINVAL; |
3041 | } | |
3042 | ||
3043 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
3044 | offset, offset - alignment); | |
3045 | } | |
3046 | } | |
3047 | ||
2e2adb05 VS |
3048 | /* |
3049 | * CCS AUX surface doesn't have its own x/y offsets, we must make sure | |
3050 | * they match with the main surface x/y offsets. | |
3051 | */ | |
3052 | if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || | |
3053 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) { | |
3054 | while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) { | |
3055 | if (offset == 0) | |
3056 | break; | |
3057 | ||
3058 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
3059 | offset, offset - alignment); | |
3060 | } | |
3061 | ||
3062 | if (x != plane_state->aux.x || y != plane_state->aux.y) { | |
3063 | DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n"); | |
3064 | return -EINVAL; | |
3065 | } | |
3066 | } | |
3067 | ||
b63a16f6 VS |
3068 | plane_state->main.offset = offset; |
3069 | plane_state->main.x = x; | |
3070 | plane_state->main.y = y; | |
3071 | ||
3072 | return 0; | |
3073 | } | |
3074 | ||
8d970654 VS |
3075 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
3076 | { | |
3077 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3078 | unsigned int rotation = plane_state->base.rotation; | |
3079 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
3080 | int max_height = 4096; | |
cc926387 DV |
3081 | int x = plane_state->base.src.x1 >> 17; |
3082 | int y = plane_state->base.src.y1 >> 17; | |
3083 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
3084 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
3085 | u32 offset; |
3086 | ||
3087 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
3088 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
3089 | ||
3090 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
3091 | if (w > max_width || h > max_height) { | |
3092 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
3093 | w, h, max_width, max_height); | |
3094 | return -EINVAL; | |
3095 | } | |
3096 | ||
3097 | plane_state->aux.offset = offset; | |
3098 | plane_state->aux.x = x; | |
3099 | plane_state->aux.y = y; | |
3100 | ||
3101 | return 0; | |
3102 | } | |
3103 | ||
2e2adb05 VS |
3104 | static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) |
3105 | { | |
3106 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
3107 | struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc); | |
3108 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3109 | int src_x = plane_state->base.src.x1 >> 16; | |
3110 | int src_y = plane_state->base.src.y1 >> 16; | |
3111 | int hsub = fb->format->hsub; | |
3112 | int vsub = fb->format->vsub; | |
3113 | int x = src_x / hsub; | |
3114 | int y = src_y / vsub; | |
3115 | u32 offset; | |
3116 | ||
3117 | switch (plane->id) { | |
3118 | case PLANE_PRIMARY: | |
3119 | case PLANE_SPRITE0: | |
3120 | break; | |
3121 | default: | |
3122 | DRM_DEBUG_KMS("RC support only on plane 1 and 2\n"); | |
3123 | return -EINVAL; | |
3124 | } | |
3125 | ||
3126 | if (crtc->pipe == PIPE_C) { | |
3127 | DRM_DEBUG_KMS("No RC support on pipe C\n"); | |
3128 | return -EINVAL; | |
3129 | } | |
3130 | ||
3131 | if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) { | |
3132 | DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n", | |
3133 | plane_state->base.rotation); | |
3134 | return -EINVAL; | |
3135 | } | |
3136 | ||
3137 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
3138 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
3139 | ||
3140 | plane_state->aux.offset = offset; | |
3141 | plane_state->aux.x = x * hsub + src_x % hsub; | |
3142 | plane_state->aux.y = y * vsub + src_y % vsub; | |
3143 | ||
3144 | return 0; | |
3145 | } | |
3146 | ||
b63a16f6 VS |
3147 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
3148 | { | |
3149 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3150 | unsigned int rotation = plane_state->base.rotation; | |
3151 | int ret; | |
3152 | ||
a5e4c7d0 VS |
3153 | if (!plane_state->base.visible) |
3154 | return 0; | |
3155 | ||
b63a16f6 | 3156 | /* Rotate src coordinates to match rotated GTT view */ |
bd2ef25d | 3157 | if (drm_rotation_90_or_270(rotation)) |
cc926387 | 3158 | drm_rect_rotate(&plane_state->base.src, |
da064b47 | 3159 | fb->width << 16, fb->height << 16, |
c2c446ad | 3160 | DRM_MODE_ROTATE_270); |
b63a16f6 | 3161 | |
8d970654 VS |
3162 | /* |
3163 | * Handle the AUX surface first since | |
3164 | * the main surface setup depends on it. | |
3165 | */ | |
438b74a5 | 3166 | if (fb->format->format == DRM_FORMAT_NV12) { |
8d970654 VS |
3167 | ret = skl_check_nv12_aux_surface(plane_state); |
3168 | if (ret) | |
3169 | return ret; | |
2e2adb05 VS |
3170 | } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || |
3171 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) { | |
3172 | ret = skl_check_ccs_aux_surface(plane_state); | |
3173 | if (ret) | |
3174 | return ret; | |
8d970654 VS |
3175 | } else { |
3176 | plane_state->aux.offset = ~0xfff; | |
3177 | plane_state->aux.x = 0; | |
3178 | plane_state->aux.y = 0; | |
3179 | } | |
3180 | ||
b63a16f6 VS |
3181 | ret = skl_check_main_surface(plane_state); |
3182 | if (ret) | |
3183 | return ret; | |
3184 | ||
3185 | return 0; | |
3186 | } | |
3187 | ||
7145f60a VS |
3188 | static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, |
3189 | const struct intel_plane_state *plane_state) | |
81255565 | 3190 | { |
7145f60a VS |
3191 | struct drm_i915_private *dev_priv = |
3192 | to_i915(plane_state->base.plane->dev); | |
3193 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3194 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
8d0deca8 | 3195 | unsigned int rotation = plane_state->base.rotation; |
7145f60a | 3196 | u32 dspcntr; |
c9ba6fad | 3197 | |
7145f60a | 3198 | dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE; |
f45651ba | 3199 | |
6a4407a6 VS |
3200 | if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) || |
3201 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
7145f60a | 3202 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
f45651ba | 3203 | |
6a4407a6 VS |
3204 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
3205 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
f45651ba | 3206 | |
d509e28b VS |
3207 | if (INTEL_GEN(dev_priv) < 4) |
3208 | dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); | |
81255565 | 3209 | |
438b74a5 | 3210 | switch (fb->format->format) { |
57779d06 | 3211 | case DRM_FORMAT_C8: |
81255565 JB |
3212 | dspcntr |= DISPPLANE_8BPP; |
3213 | break; | |
57779d06 | 3214 | case DRM_FORMAT_XRGB1555: |
57779d06 | 3215 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 3216 | break; |
57779d06 VS |
3217 | case DRM_FORMAT_RGB565: |
3218 | dspcntr |= DISPPLANE_BGRX565; | |
3219 | break; | |
3220 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
3221 | dspcntr |= DISPPLANE_BGRX888; |
3222 | break; | |
3223 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3224 | dspcntr |= DISPPLANE_RGBX888; |
3225 | break; | |
3226 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3227 | dspcntr |= DISPPLANE_BGRX101010; |
3228 | break; | |
3229 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3230 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3231 | break; |
3232 | default: | |
7145f60a VS |
3233 | MISSING_CASE(fb->format->format); |
3234 | return 0; | |
81255565 | 3235 | } |
57779d06 | 3236 | |
72618ebf | 3237 | if (INTEL_GEN(dev_priv) >= 4 && |
bae781b2 | 3238 | fb->modifier == I915_FORMAT_MOD_X_TILED) |
f45651ba | 3239 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3240 | |
c2c446ad | 3241 | if (rotation & DRM_MODE_ROTATE_180) |
df0cd455 VS |
3242 | dspcntr |= DISPPLANE_ROTATE_180; |
3243 | ||
c2c446ad | 3244 | if (rotation & DRM_MODE_REFLECT_X) |
4ea7be2b VS |
3245 | dspcntr |= DISPPLANE_MIRROR; |
3246 | ||
7145f60a VS |
3247 | return dspcntr; |
3248 | } | |
de1aa629 | 3249 | |
f9407ae1 | 3250 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state) |
5b7fcc44 VS |
3251 | { |
3252 | struct drm_i915_private *dev_priv = | |
3253 | to_i915(plane_state->base.plane->dev); | |
3254 | int src_x = plane_state->base.src.x1 >> 16; | |
3255 | int src_y = plane_state->base.src.y1 >> 16; | |
3256 | u32 offset; | |
81255565 | 3257 | |
5b7fcc44 | 3258 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); |
e506a0c6 | 3259 | |
5b7fcc44 VS |
3260 | if (INTEL_GEN(dev_priv) >= 4) |
3261 | offset = intel_compute_tile_offset(&src_x, &src_y, | |
3262 | plane_state, 0); | |
3263 | else | |
3264 | offset = 0; | |
3265 | ||
3266 | /* HSW/BDW do this automagically in hardware */ | |
3267 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { | |
3268 | unsigned int rotation = plane_state->base.rotation; | |
3269 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; | |
3270 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3271 | ||
c2c446ad | 3272 | if (rotation & DRM_MODE_ROTATE_180) { |
5b7fcc44 VS |
3273 | src_x += src_w - 1; |
3274 | src_y += src_h - 1; | |
c2c446ad | 3275 | } else if (rotation & DRM_MODE_REFLECT_X) { |
5b7fcc44 VS |
3276 | src_x += src_w - 1; |
3277 | } | |
48404c1e SJ |
3278 | } |
3279 | ||
5b7fcc44 VS |
3280 | plane_state->main.offset = offset; |
3281 | plane_state->main.x = src_x; | |
3282 | plane_state->main.y = src_y; | |
3283 | ||
3284 | return 0; | |
3285 | } | |
3286 | ||
282dbf9b | 3287 | static void i9xx_update_primary_plane(struct intel_plane *primary, |
7145f60a VS |
3288 | const struct intel_crtc_state *crtc_state, |
3289 | const struct intel_plane_state *plane_state) | |
3290 | { | |
282dbf9b | 3291 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
282dbf9b VS |
3292 | const struct drm_framebuffer *fb = plane_state->base.fb; |
3293 | enum plane plane = primary->plane; | |
7145f60a | 3294 | u32 linear_offset; |
a0864d59 | 3295 | u32 dspcntr = plane_state->ctl; |
7145f60a | 3296 | i915_reg_t reg = DSPCNTR(plane); |
5b7fcc44 VS |
3297 | int x = plane_state->main.x; |
3298 | int y = plane_state->main.y; | |
7145f60a | 3299 | unsigned long irqflags; |
e288881b | 3300 | u32 dspaddr_offset; |
7145f60a | 3301 | |
2949056c | 3302 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3303 | |
5b7fcc44 | 3304 | if (INTEL_GEN(dev_priv) >= 4) |
e288881b | 3305 | dspaddr_offset = plane_state->main.offset; |
5b7fcc44 | 3306 | else |
e288881b | 3307 | dspaddr_offset = linear_offset; |
2db3366b | 3308 | |
dd584fc0 VS |
3309 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
3310 | ||
78587de2 VS |
3311 | if (INTEL_GEN(dev_priv) < 4) { |
3312 | /* pipesrc and dspsize control the size that is scaled from, | |
3313 | * which should always be the user's requested size. | |
3314 | */ | |
dd584fc0 VS |
3315 | I915_WRITE_FW(DSPSIZE(plane), |
3316 | ((crtc_state->pipe_src_h - 1) << 16) | | |
3317 | (crtc_state->pipe_src_w - 1)); | |
3318 | I915_WRITE_FW(DSPPOS(plane), 0); | |
78587de2 | 3319 | } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { |
dd584fc0 VS |
3320 | I915_WRITE_FW(PRIMSIZE(plane), |
3321 | ((crtc_state->pipe_src_h - 1) << 16) | | |
3322 | (crtc_state->pipe_src_w - 1)); | |
3323 | I915_WRITE_FW(PRIMPOS(plane), 0); | |
3324 | I915_WRITE_FW(PRIMCNSTALPHA(plane), 0); | |
78587de2 VS |
3325 | } |
3326 | ||
dd584fc0 | 3327 | I915_WRITE_FW(reg, dspcntr); |
48404c1e | 3328 | |
dd584fc0 | 3329 | I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]); |
3ba35e53 VS |
3330 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3331 | I915_WRITE_FW(DSPSURF(plane), | |
3332 | intel_plane_ggtt_offset(plane_state) + | |
e288881b | 3333 | dspaddr_offset); |
3ba35e53 VS |
3334 | I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x); |
3335 | } else if (INTEL_GEN(dev_priv) >= 4) { | |
dd584fc0 VS |
3336 | I915_WRITE_FW(DSPSURF(plane), |
3337 | intel_plane_ggtt_offset(plane_state) + | |
e288881b | 3338 | dspaddr_offset); |
dd584fc0 VS |
3339 | I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x); |
3340 | I915_WRITE_FW(DSPLINOFF(plane), linear_offset); | |
bfb81049 | 3341 | } else { |
dd584fc0 VS |
3342 | I915_WRITE_FW(DSPADDR(plane), |
3343 | intel_plane_ggtt_offset(plane_state) + | |
e288881b | 3344 | dspaddr_offset); |
bfb81049 | 3345 | } |
dd584fc0 VS |
3346 | POSTING_READ_FW(reg); |
3347 | ||
3348 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
17638cd6 JB |
3349 | } |
3350 | ||
282dbf9b VS |
3351 | static void i9xx_disable_primary_plane(struct intel_plane *primary, |
3352 | struct intel_crtc *crtc) | |
17638cd6 | 3353 | { |
282dbf9b VS |
3354 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3355 | enum plane plane = primary->plane; | |
dd584fc0 VS |
3356 | unsigned long irqflags; |
3357 | ||
3358 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
f45651ba | 3359 | |
dd584fc0 | 3360 | I915_WRITE_FW(DSPCNTR(plane), 0); |
a8d201af | 3361 | if (INTEL_INFO(dev_priv)->gen >= 4) |
dd584fc0 | 3362 | I915_WRITE_FW(DSPSURF(plane), 0); |
a8d201af | 3363 | else |
dd584fc0 VS |
3364 | I915_WRITE_FW(DSPADDR(plane), 0); |
3365 | POSTING_READ_FW(DSPCNTR(plane)); | |
3366 | ||
3367 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 3368 | } |
c9ba6fad | 3369 | |
d88c4afd VS |
3370 | static u32 |
3371 | intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane) | |
b321803d | 3372 | { |
2f075565 | 3373 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) |
b321803d | 3374 | return 64; |
d88c4afd VS |
3375 | else |
3376 | return intel_tile_width_bytes(fb, plane); | |
b321803d DL |
3377 | } |
3378 | ||
e435d6e5 ML |
3379 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3380 | { | |
3381 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3382 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3383 | |
3384 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3385 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3386 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3387 | } |
3388 | ||
a1b2278e CK |
3389 | /* |
3390 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3391 | */ | |
0583236e | 3392 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3393 | { |
a1b2278e CK |
3394 | struct intel_crtc_scaler_state *scaler_state; |
3395 | int i; | |
3396 | ||
a1b2278e CK |
3397 | scaler_state = &intel_crtc->config->scaler_state; |
3398 | ||
3399 | /* loop through and disable scalers that aren't in use */ | |
3400 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3401 | if (!scaler_state->scalers[i].in_use) |
3402 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3403 | } |
3404 | } | |
3405 | ||
d2196774 VS |
3406 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3407 | unsigned int rotation) | |
3408 | { | |
1b500535 VS |
3409 | u32 stride; |
3410 | ||
3411 | if (plane >= fb->format->num_planes) | |
3412 | return 0; | |
3413 | ||
3414 | stride = intel_fb_pitch(fb, plane, rotation); | |
d2196774 VS |
3415 | |
3416 | /* | |
3417 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3418 | * linear buffers or in number of tiles for tiled buffers. | |
3419 | */ | |
d88c4afd VS |
3420 | if (drm_rotation_90_or_270(rotation)) |
3421 | stride /= intel_tile_height(fb, plane); | |
3422 | else | |
3423 | stride /= intel_fb_stride_alignment(fb, plane); | |
d2196774 VS |
3424 | |
3425 | return stride; | |
3426 | } | |
3427 | ||
2e881264 | 3428 | static u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3429 | { |
6156a456 | 3430 | switch (pixel_format) { |
d161cf7a | 3431 | case DRM_FORMAT_C8: |
c34ce3d1 | 3432 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3433 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3434 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3435 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3436 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3437 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3438 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3439 | /* |
3440 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3441 | * to be already pre-multiplied. We need to add a knob (or a different | |
3442 | * DRM_FORMAT) for user-space to configure that. | |
3443 | */ | |
f75fb42a | 3444 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3445 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3446 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3447 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3448 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3449 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3450 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3451 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3452 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3453 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3454 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3455 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3456 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3457 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3458 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3459 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3460 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3461 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3462 | default: |
4249eeef | 3463 | MISSING_CASE(pixel_format); |
70d21f0e | 3464 | } |
8cfcba41 | 3465 | |
c34ce3d1 | 3466 | return 0; |
6156a456 | 3467 | } |
70d21f0e | 3468 | |
2e881264 | 3469 | static u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
6156a456 | 3470 | { |
6156a456 | 3471 | switch (fb_modifier) { |
2f075565 | 3472 | case DRM_FORMAT_MOD_LINEAR: |
70d21f0e | 3473 | break; |
30af77c4 | 3474 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3475 | return PLANE_CTL_TILED_X; |
b321803d | 3476 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3477 | return PLANE_CTL_TILED_Y; |
2e2adb05 VS |
3478 | case I915_FORMAT_MOD_Y_TILED_CCS: |
3479 | return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE; | |
b321803d | 3480 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3481 | return PLANE_CTL_TILED_YF; |
2e2adb05 VS |
3482 | case I915_FORMAT_MOD_Yf_TILED_CCS: |
3483 | return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE; | |
70d21f0e | 3484 | default: |
6156a456 | 3485 | MISSING_CASE(fb_modifier); |
70d21f0e | 3486 | } |
8cfcba41 | 3487 | |
c34ce3d1 | 3488 | return 0; |
6156a456 | 3489 | } |
70d21f0e | 3490 | |
2e881264 | 3491 | static u32 skl_plane_ctl_rotation(unsigned int rotation) |
6156a456 | 3492 | { |
3b7a5119 | 3493 | switch (rotation) { |
c2c446ad | 3494 | case DRM_MODE_ROTATE_0: |
6156a456 | 3495 | break; |
1e8df167 | 3496 | /* |
c2c446ad | 3497 | * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr |
1e8df167 SJ |
3498 | * while i915 HW rotation is clockwise, thats why this swapping. |
3499 | */ | |
c2c446ad | 3500 | case DRM_MODE_ROTATE_90: |
1e8df167 | 3501 | return PLANE_CTL_ROTATE_270; |
c2c446ad | 3502 | case DRM_MODE_ROTATE_180: |
c34ce3d1 | 3503 | return PLANE_CTL_ROTATE_180; |
c2c446ad | 3504 | case DRM_MODE_ROTATE_270: |
1e8df167 | 3505 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3506 | default: |
3507 | MISSING_CASE(rotation); | |
3508 | } | |
3509 | ||
c34ce3d1 | 3510 | return 0; |
6156a456 CK |
3511 | } |
3512 | ||
2e881264 VS |
3513 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, |
3514 | const struct intel_plane_state *plane_state) | |
46f788ba VS |
3515 | { |
3516 | struct drm_i915_private *dev_priv = | |
3517 | to_i915(plane_state->base.plane->dev); | |
3518 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3519 | unsigned int rotation = plane_state->base.rotation; | |
2e881264 | 3520 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
46f788ba VS |
3521 | u32 plane_ctl; |
3522 | ||
3523 | plane_ctl = PLANE_CTL_ENABLE; | |
3524 | ||
6602be0e | 3525 | if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) { |
46f788ba VS |
3526 | plane_ctl |= |
3527 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3528 | PLANE_CTL_PIPE_CSC_ENABLE | | |
3529 | PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3530 | } | |
3531 | ||
3532 | plane_ctl |= skl_plane_ctl_format(fb->format->format); | |
3533 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier); | |
3534 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3535 | ||
2e881264 VS |
3536 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
3537 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; | |
3538 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
3539 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; | |
3540 | ||
46f788ba VS |
3541 | return plane_ctl; |
3542 | } | |
3543 | ||
73974893 ML |
3544 | static int |
3545 | __intel_display_resume(struct drm_device *dev, | |
581e49fe ML |
3546 | struct drm_atomic_state *state, |
3547 | struct drm_modeset_acquire_ctx *ctx) | |
73974893 ML |
3548 | { |
3549 | struct drm_crtc_state *crtc_state; | |
3550 | struct drm_crtc *crtc; | |
3551 | int i, ret; | |
11c22da6 | 3552 | |
aecd36b8 | 3553 | intel_modeset_setup_hw_state(dev, ctx); |
29b74b7f | 3554 | i915_redisable_vga(to_i915(dev)); |
73974893 ML |
3555 | |
3556 | if (!state) | |
3557 | return 0; | |
3558 | ||
aa5e9b47 ML |
3559 | /* |
3560 | * We've duplicated the state, pointers to the old state are invalid. | |
3561 | * | |
3562 | * Don't attempt to use the old state until we commit the duplicated state. | |
3563 | */ | |
3564 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { | |
73974893 ML |
3565 | /* |
3566 | * Force recalculation even if we restore | |
3567 | * current state. With fast modeset this may not result | |
3568 | * in a modeset when the state is compatible. | |
3569 | */ | |
3570 | crtc_state->mode_changed = true; | |
96a02917 | 3571 | } |
73974893 ML |
3572 | |
3573 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
602ae835 VS |
3574 | if (!HAS_GMCH_DISPLAY(to_i915(dev))) |
3575 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
73974893 | 3576 | |
581e49fe | 3577 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
73974893 ML |
3578 | |
3579 | WARN_ON(ret == -EDEADLK); | |
3580 | return ret; | |
96a02917 VS |
3581 | } |
3582 | ||
4ac2ba2f VS |
3583 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3584 | { | |
ae98104b VS |
3585 | return intel_has_gpu_reset(dev_priv) && |
3586 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3587 | } |
3588 | ||
c033666a | 3589 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3590 | { |
73974893 ML |
3591 | struct drm_device *dev = &dev_priv->drm; |
3592 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3593 | struct drm_atomic_state *state; | |
3594 | int ret; | |
3595 | ||
ce87ea15 DV |
3596 | |
3597 | /* reset doesn't touch the display */ | |
4f044a88 | 3598 | if (!i915_modparams.force_reset_modeset_test && |
ce87ea15 DV |
3599 | !gpu_reset_clobbers_display(dev_priv)) |
3600 | return; | |
3601 | ||
9db529aa DV |
3602 | /* We have a modeset vs reset deadlock, defensively unbreak it. */ |
3603 | set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); | |
3604 | wake_up_all(&dev_priv->gpu_error.wait_queue); | |
3605 | ||
3606 | if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { | |
3607 | DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n"); | |
3608 | i915_gem_set_wedged(dev_priv); | |
3609 | } | |
97154ec2 | 3610 | |
73974893 ML |
3611 | /* |
3612 | * Need mode_config.mutex so that we don't | |
3613 | * trample ongoing ->detect() and whatnot. | |
3614 | */ | |
3615 | mutex_lock(&dev->mode_config.mutex); | |
3616 | drm_modeset_acquire_init(ctx, 0); | |
3617 | while (1) { | |
3618 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3619 | if (ret != -EDEADLK) | |
3620 | break; | |
3621 | ||
3622 | drm_modeset_backoff(ctx); | |
3623 | } | |
f98ce92f VS |
3624 | /* |
3625 | * Disabling the crtcs gracefully seems nicer. Also the | |
3626 | * g33 docs say we should at least disable all the planes. | |
3627 | */ | |
73974893 ML |
3628 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3629 | if (IS_ERR(state)) { | |
3630 | ret = PTR_ERR(state); | |
73974893 | 3631 | DRM_ERROR("Duplicating state failed with %i\n", ret); |
1e5a15d6 | 3632 | return; |
73974893 ML |
3633 | } |
3634 | ||
3635 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3636 | if (ret) { | |
3637 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
1e5a15d6 ACO |
3638 | drm_atomic_state_put(state); |
3639 | return; | |
73974893 ML |
3640 | } |
3641 | ||
3642 | dev_priv->modeset_restore_state = state; | |
3643 | state->acquire_ctx = ctx; | |
7514747d VS |
3644 | } |
3645 | ||
c033666a | 3646 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3647 | { |
73974893 ML |
3648 | struct drm_device *dev = &dev_priv->drm; |
3649 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3650 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3651 | int ret; | |
3652 | ||
ce87ea15 | 3653 | /* reset doesn't touch the display */ |
4f044a88 | 3654 | if (!i915_modparams.force_reset_modeset_test && |
ce87ea15 DV |
3655 | !gpu_reset_clobbers_display(dev_priv)) |
3656 | return; | |
3657 | ||
3658 | if (!state) | |
3659 | goto unlock; | |
3660 | ||
73974893 ML |
3661 | dev_priv->modeset_restore_state = NULL; |
3662 | ||
7514747d | 3663 | /* reset doesn't touch the display */ |
4ac2ba2f | 3664 | if (!gpu_reset_clobbers_display(dev_priv)) { |
ce87ea15 DV |
3665 | /* for testing only restore the display */ |
3666 | ret = __intel_display_resume(dev, state, ctx); | |
942d5d0d CW |
3667 | if (ret) |
3668 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
73974893 ML |
3669 | } else { |
3670 | /* | |
3671 | * The display has been reset as well, | |
3672 | * so need a full re-initialization. | |
3673 | */ | |
3674 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3675 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3676 | |
51f59205 | 3677 | intel_pps_unlock_regs_wa(dev_priv); |
73974893 | 3678 | intel_modeset_init_hw(dev); |
6ac43272 | 3679 | intel_init_clock_gating(dev_priv); |
7514747d | 3680 | |
73974893 ML |
3681 | spin_lock_irq(&dev_priv->irq_lock); |
3682 | if (dev_priv->display.hpd_irq_setup) | |
3683 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3684 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3685 | |
581e49fe | 3686 | ret = __intel_display_resume(dev, state, ctx); |
73974893 ML |
3687 | if (ret) |
3688 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3689 | |
73974893 ML |
3690 | intel_hpd_init(dev_priv); |
3691 | } | |
7514747d | 3692 | |
ce87ea15 DV |
3693 | drm_atomic_state_put(state); |
3694 | unlock: | |
73974893 ML |
3695 | drm_modeset_drop_locks(ctx); |
3696 | drm_modeset_acquire_fini(ctx); | |
3697 | mutex_unlock(&dev->mode_config.mutex); | |
9db529aa DV |
3698 | |
3699 | clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); | |
7514747d VS |
3700 | } |
3701 | ||
1a15b77b VS |
3702 | static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state, |
3703 | const struct intel_crtc_state *new_crtc_state) | |
e30e8f75 | 3704 | { |
1a15b77b | 3705 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); |
6315b5d3 | 3706 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
e30e8f75 | 3707 | |
bfd16b2a | 3708 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
1a15b77b | 3709 | crtc->base.mode = new_crtc_state->base.mode; |
bfd16b2a | 3710 | |
e30e8f75 GP |
3711 | /* |
3712 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3713 | * that in compute_mode_changes we check the native mode (not the pfit | |
3714 | * mode) to see if we can flip rather than do a full mode set. In the | |
3715 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3716 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3717 | * sized surface. | |
e30e8f75 GP |
3718 | */ |
3719 | ||
e30e8f75 | 3720 | I915_WRITE(PIPESRC(crtc->pipe), |
1a15b77b VS |
3721 | ((new_crtc_state->pipe_src_w - 1) << 16) | |
3722 | (new_crtc_state->pipe_src_h - 1)); | |
bfd16b2a ML |
3723 | |
3724 | /* on skylake this is done by detaching scalers */ | |
6315b5d3 | 3725 | if (INTEL_GEN(dev_priv) >= 9) { |
bfd16b2a ML |
3726 | skl_detach_scalers(crtc); |
3727 | ||
1a15b77b | 3728 | if (new_crtc_state->pch_pfit.enabled) |
bfd16b2a | 3729 | skylake_pfit_enable(crtc); |
6e266956 | 3730 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
1a15b77b | 3731 | if (new_crtc_state->pch_pfit.enabled) |
bfd16b2a ML |
3732 | ironlake_pfit_enable(crtc); |
3733 | else if (old_crtc_state->pch_pfit.enabled) | |
3734 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3735 | } |
e30e8f75 GP |
3736 | } |
3737 | ||
4cbe4b2b | 3738 | static void intel_fdi_normal_train(struct intel_crtc *crtc) |
5e84e1a4 | 3739 | { |
4cbe4b2b | 3740 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3741 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3742 | int pipe = crtc->pipe; |
f0f59a00 VS |
3743 | i915_reg_t reg; |
3744 | u32 temp; | |
5e84e1a4 ZW |
3745 | |
3746 | /* enable normal train */ | |
3747 | reg = FDI_TX_CTL(pipe); | |
3748 | temp = I915_READ(reg); | |
fd6b8f43 | 3749 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
3750 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3751 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3752 | } else { |
3753 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3754 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3755 | } |
5e84e1a4 ZW |
3756 | I915_WRITE(reg, temp); |
3757 | ||
3758 | reg = FDI_RX_CTL(pipe); | |
3759 | temp = I915_READ(reg); | |
6e266956 | 3760 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
3761 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3762 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3763 | } else { | |
3764 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3765 | temp |= FDI_LINK_TRAIN_NONE; | |
3766 | } | |
3767 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3768 | ||
3769 | /* wait one idle pattern time */ | |
3770 | POSTING_READ(reg); | |
3771 | udelay(1000); | |
357555c0 JB |
3772 | |
3773 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 3774 | if (IS_IVYBRIDGE(dev_priv)) |
357555c0 JB |
3775 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
3776 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3777 | } |
3778 | ||
8db9d77b | 3779 | /* The FDI link training functions for ILK/Ibexpeak. */ |
dc4a1094 ACO |
3780 | static void ironlake_fdi_link_train(struct intel_crtc *crtc, |
3781 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3782 | { |
4cbe4b2b | 3783 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3784 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3785 | int pipe = crtc->pipe; |
f0f59a00 VS |
3786 | i915_reg_t reg; |
3787 | u32 temp, tries; | |
8db9d77b | 3788 | |
1c8562f6 | 3789 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3790 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3791 | |
e1a44743 AJ |
3792 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3793 | for train result */ | |
5eddb70b CW |
3794 | reg = FDI_RX_IMR(pipe); |
3795 | temp = I915_READ(reg); | |
e1a44743 AJ |
3796 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3797 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3798 | I915_WRITE(reg, temp); |
3799 | I915_READ(reg); | |
e1a44743 AJ |
3800 | udelay(150); |
3801 | ||
8db9d77b | 3802 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3803 | reg = FDI_TX_CTL(pipe); |
3804 | temp = I915_READ(reg); | |
627eb5a3 | 3805 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3806 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3807 | temp &= ~FDI_LINK_TRAIN_NONE; |
3808 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3809 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3810 | |
5eddb70b CW |
3811 | reg = FDI_RX_CTL(pipe); |
3812 | temp = I915_READ(reg); | |
8db9d77b ZW |
3813 | temp &= ~FDI_LINK_TRAIN_NONE; |
3814 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3815 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3816 | ||
3817 | POSTING_READ(reg); | |
8db9d77b ZW |
3818 | udelay(150); |
3819 | ||
5b2adf89 | 3820 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3821 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3822 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3823 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3824 | |
5eddb70b | 3825 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3826 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3827 | temp = I915_READ(reg); |
8db9d77b ZW |
3828 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3829 | ||
3830 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3831 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3832 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3833 | break; |
3834 | } | |
8db9d77b | 3835 | } |
e1a44743 | 3836 | if (tries == 5) |
5eddb70b | 3837 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3838 | |
3839 | /* Train 2 */ | |
5eddb70b CW |
3840 | reg = FDI_TX_CTL(pipe); |
3841 | temp = I915_READ(reg); | |
8db9d77b ZW |
3842 | temp &= ~FDI_LINK_TRAIN_NONE; |
3843 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3844 | I915_WRITE(reg, temp); |
8db9d77b | 3845 | |
5eddb70b CW |
3846 | reg = FDI_RX_CTL(pipe); |
3847 | temp = I915_READ(reg); | |
8db9d77b ZW |
3848 | temp &= ~FDI_LINK_TRAIN_NONE; |
3849 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3850 | I915_WRITE(reg, temp); |
8db9d77b | 3851 | |
5eddb70b CW |
3852 | POSTING_READ(reg); |
3853 | udelay(150); | |
8db9d77b | 3854 | |
5eddb70b | 3855 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3856 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3857 | temp = I915_READ(reg); |
8db9d77b ZW |
3858 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3859 | ||
3860 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3861 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3862 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3863 | break; | |
3864 | } | |
8db9d77b | 3865 | } |
e1a44743 | 3866 | if (tries == 5) |
5eddb70b | 3867 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3868 | |
3869 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3870 | |
8db9d77b ZW |
3871 | } |
3872 | ||
0206e353 | 3873 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3874 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3875 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3876 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3877 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3878 | }; | |
3879 | ||
3880 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
dc4a1094 ACO |
3881 | static void gen6_fdi_link_train(struct intel_crtc *crtc, |
3882 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3883 | { |
4cbe4b2b | 3884 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3885 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3886 | int pipe = crtc->pipe; |
f0f59a00 VS |
3887 | i915_reg_t reg; |
3888 | u32 temp, i, retry; | |
8db9d77b | 3889 | |
e1a44743 AJ |
3890 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3891 | for train result */ | |
5eddb70b CW |
3892 | reg = FDI_RX_IMR(pipe); |
3893 | temp = I915_READ(reg); | |
e1a44743 AJ |
3894 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3895 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3896 | I915_WRITE(reg, temp); |
3897 | ||
3898 | POSTING_READ(reg); | |
e1a44743 AJ |
3899 | udelay(150); |
3900 | ||
8db9d77b | 3901 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3902 | reg = FDI_TX_CTL(pipe); |
3903 | temp = I915_READ(reg); | |
627eb5a3 | 3904 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3905 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3906 | temp &= ~FDI_LINK_TRAIN_NONE; |
3907 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3908 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3909 | /* SNB-B */ | |
3910 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3911 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3912 | |
d74cf324 DV |
3913 | I915_WRITE(FDI_RX_MISC(pipe), |
3914 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3915 | ||
5eddb70b CW |
3916 | reg = FDI_RX_CTL(pipe); |
3917 | temp = I915_READ(reg); | |
6e266956 | 3918 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3919 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3920 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3921 | } else { | |
3922 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3923 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3924 | } | |
5eddb70b CW |
3925 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3926 | ||
3927 | POSTING_READ(reg); | |
8db9d77b ZW |
3928 | udelay(150); |
3929 | ||
0206e353 | 3930 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3931 | reg = FDI_TX_CTL(pipe); |
3932 | temp = I915_READ(reg); | |
8db9d77b ZW |
3933 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3934 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3935 | I915_WRITE(reg, temp); |
3936 | ||
3937 | POSTING_READ(reg); | |
8db9d77b ZW |
3938 | udelay(500); |
3939 | ||
fa37d39e SP |
3940 | for (retry = 0; retry < 5; retry++) { |
3941 | reg = FDI_RX_IIR(pipe); | |
3942 | temp = I915_READ(reg); | |
3943 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3944 | if (temp & FDI_RX_BIT_LOCK) { | |
3945 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3946 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3947 | break; | |
3948 | } | |
3949 | udelay(50); | |
8db9d77b | 3950 | } |
fa37d39e SP |
3951 | if (retry < 5) |
3952 | break; | |
8db9d77b ZW |
3953 | } |
3954 | if (i == 4) | |
5eddb70b | 3955 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3956 | |
3957 | /* Train 2 */ | |
5eddb70b CW |
3958 | reg = FDI_TX_CTL(pipe); |
3959 | temp = I915_READ(reg); | |
8db9d77b ZW |
3960 | temp &= ~FDI_LINK_TRAIN_NONE; |
3961 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5db94019 | 3962 | if (IS_GEN6(dev_priv)) { |
8db9d77b ZW |
3963 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3964 | /* SNB-B */ | |
3965 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3966 | } | |
5eddb70b | 3967 | I915_WRITE(reg, temp); |
8db9d77b | 3968 | |
5eddb70b CW |
3969 | reg = FDI_RX_CTL(pipe); |
3970 | temp = I915_READ(reg); | |
6e266956 | 3971 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3972 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3973 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3974 | } else { | |
3975 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3976 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3977 | } | |
5eddb70b CW |
3978 | I915_WRITE(reg, temp); |
3979 | ||
3980 | POSTING_READ(reg); | |
8db9d77b ZW |
3981 | udelay(150); |
3982 | ||
0206e353 | 3983 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3984 | reg = FDI_TX_CTL(pipe); |
3985 | temp = I915_READ(reg); | |
8db9d77b ZW |
3986 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3987 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3988 | I915_WRITE(reg, temp); |
3989 | ||
3990 | POSTING_READ(reg); | |
8db9d77b ZW |
3991 | udelay(500); |
3992 | ||
fa37d39e SP |
3993 | for (retry = 0; retry < 5; retry++) { |
3994 | reg = FDI_RX_IIR(pipe); | |
3995 | temp = I915_READ(reg); | |
3996 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3997 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3998 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3999 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
4000 | break; | |
4001 | } | |
4002 | udelay(50); | |
8db9d77b | 4003 | } |
fa37d39e SP |
4004 | if (retry < 5) |
4005 | break; | |
8db9d77b ZW |
4006 | } |
4007 | if (i == 4) | |
5eddb70b | 4008 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
4009 | |
4010 | DRM_DEBUG_KMS("FDI train done.\n"); | |
4011 | } | |
4012 | ||
357555c0 | 4013 | /* Manual link training for Ivy Bridge A0 parts */ |
dc4a1094 ACO |
4014 | static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, |
4015 | const struct intel_crtc_state *crtc_state) | |
357555c0 | 4016 | { |
4cbe4b2b | 4017 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4018 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 4019 | int pipe = crtc->pipe; |
f0f59a00 VS |
4020 | i915_reg_t reg; |
4021 | u32 temp, i, j; | |
357555c0 JB |
4022 | |
4023 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
4024 | for train result */ | |
4025 | reg = FDI_RX_IMR(pipe); | |
4026 | temp = I915_READ(reg); | |
4027 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
4028 | temp &= ~FDI_RX_BIT_LOCK; | |
4029 | I915_WRITE(reg, temp); | |
4030 | ||
4031 | POSTING_READ(reg); | |
4032 | udelay(150); | |
4033 | ||
01a415fd DV |
4034 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
4035 | I915_READ(FDI_RX_IIR(pipe))); | |
4036 | ||
139ccd3f JB |
4037 | /* Try each vswing and preemphasis setting twice before moving on */ |
4038 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
4039 | /* disable first in case we need to retry */ | |
4040 | reg = FDI_TX_CTL(pipe); | |
4041 | temp = I915_READ(reg); | |
4042 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
4043 | temp &= ~FDI_TX_ENABLE; | |
4044 | I915_WRITE(reg, temp); | |
357555c0 | 4045 | |
139ccd3f JB |
4046 | reg = FDI_RX_CTL(pipe); |
4047 | temp = I915_READ(reg); | |
4048 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
4049 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4050 | temp &= ~FDI_RX_ENABLE; | |
4051 | I915_WRITE(reg, temp); | |
357555c0 | 4052 | |
139ccd3f | 4053 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
4054 | reg = FDI_TX_CTL(pipe); |
4055 | temp = I915_READ(reg); | |
139ccd3f | 4056 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 4057 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
139ccd3f | 4058 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 4059 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
4060 | temp |= snb_b_fdi_train_param[j/2]; |
4061 | temp |= FDI_COMPOSITE_SYNC; | |
4062 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 4063 | |
139ccd3f JB |
4064 | I915_WRITE(FDI_RX_MISC(pipe), |
4065 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 4066 | |
139ccd3f | 4067 | reg = FDI_RX_CTL(pipe); |
357555c0 | 4068 | temp = I915_READ(reg); |
139ccd3f JB |
4069 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
4070 | temp |= FDI_COMPOSITE_SYNC; | |
4071 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 4072 | |
139ccd3f JB |
4073 | POSTING_READ(reg); |
4074 | udelay(1); /* should be 0.5us */ | |
357555c0 | 4075 | |
139ccd3f JB |
4076 | for (i = 0; i < 4; i++) { |
4077 | reg = FDI_RX_IIR(pipe); | |
4078 | temp = I915_READ(reg); | |
4079 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4080 | |
139ccd3f JB |
4081 | if (temp & FDI_RX_BIT_LOCK || |
4082 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
4083 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4084 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
4085 | i); | |
4086 | break; | |
4087 | } | |
4088 | udelay(1); /* should be 0.5us */ | |
4089 | } | |
4090 | if (i == 4) { | |
4091 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
4092 | continue; | |
4093 | } | |
357555c0 | 4094 | |
139ccd3f | 4095 | /* Train 2 */ |
357555c0 JB |
4096 | reg = FDI_TX_CTL(pipe); |
4097 | temp = I915_READ(reg); | |
139ccd3f JB |
4098 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
4099 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
4100 | I915_WRITE(reg, temp); | |
4101 | ||
4102 | reg = FDI_RX_CTL(pipe); | |
4103 | temp = I915_READ(reg); | |
4104 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4105 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
4106 | I915_WRITE(reg, temp); |
4107 | ||
4108 | POSTING_READ(reg); | |
139ccd3f | 4109 | udelay(2); /* should be 1.5us */ |
357555c0 | 4110 | |
139ccd3f JB |
4111 | for (i = 0; i < 4; i++) { |
4112 | reg = FDI_RX_IIR(pipe); | |
4113 | temp = I915_READ(reg); | |
4114 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4115 | |
139ccd3f JB |
4116 | if (temp & FDI_RX_SYMBOL_LOCK || |
4117 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
4118 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4119 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
4120 | i); | |
4121 | goto train_done; | |
4122 | } | |
4123 | udelay(2); /* should be 1.5us */ | |
357555c0 | 4124 | } |
139ccd3f JB |
4125 | if (i == 4) |
4126 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 4127 | } |
357555c0 | 4128 | |
139ccd3f | 4129 | train_done: |
357555c0 JB |
4130 | DRM_DEBUG_KMS("FDI train done.\n"); |
4131 | } | |
4132 | ||
88cefb6c | 4133 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 4134 | { |
88cefb6c | 4135 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4136 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 4137 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4138 | i915_reg_t reg; |
4139 | u32 temp; | |
c64e311e | 4140 | |
c98e9dcf | 4141 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
4142 | reg = FDI_RX_CTL(pipe); |
4143 | temp = I915_READ(reg); | |
627eb5a3 | 4144 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 4145 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 4146 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
4147 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
4148 | ||
4149 | POSTING_READ(reg); | |
c98e9dcf JB |
4150 | udelay(200); |
4151 | ||
4152 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4153 | temp = I915_READ(reg); |
4154 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4155 | ||
4156 | POSTING_READ(reg); | |
c98e9dcf JB |
4157 | udelay(200); |
4158 | ||
20749730 PZ |
4159 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4160 | reg = FDI_TX_CTL(pipe); | |
4161 | temp = I915_READ(reg); | |
4162 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4163 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4164 | |
20749730 PZ |
4165 | POSTING_READ(reg); |
4166 | udelay(100); | |
6be4a607 | 4167 | } |
0e23b99d JB |
4168 | } |
4169 | ||
88cefb6c DV |
4170 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4171 | { | |
4172 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4173 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4174 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4175 | i915_reg_t reg; |
4176 | u32 temp; | |
88cefb6c DV |
4177 | |
4178 | /* Switch from PCDclk to Rawclk */ | |
4179 | reg = FDI_RX_CTL(pipe); | |
4180 | temp = I915_READ(reg); | |
4181 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4182 | ||
4183 | /* Disable CPU FDI TX PLL */ | |
4184 | reg = FDI_TX_CTL(pipe); | |
4185 | temp = I915_READ(reg); | |
4186 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4187 | ||
4188 | POSTING_READ(reg); | |
4189 | udelay(100); | |
4190 | ||
4191 | reg = FDI_RX_CTL(pipe); | |
4192 | temp = I915_READ(reg); | |
4193 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4194 | ||
4195 | /* Wait for the clocks to turn off. */ | |
4196 | POSTING_READ(reg); | |
4197 | udelay(100); | |
4198 | } | |
4199 | ||
0fc932b8 JB |
4200 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4201 | { | |
4202 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4203 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4204 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4205 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4206 | i915_reg_t reg; |
4207 | u32 temp; | |
0fc932b8 JB |
4208 | |
4209 | /* disable CPU FDI tx and PCH FDI rx */ | |
4210 | reg = FDI_TX_CTL(pipe); | |
4211 | temp = I915_READ(reg); | |
4212 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4213 | POSTING_READ(reg); | |
4214 | ||
4215 | reg = FDI_RX_CTL(pipe); | |
4216 | temp = I915_READ(reg); | |
4217 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4218 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4219 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4220 | ||
4221 | POSTING_READ(reg); | |
4222 | udelay(100); | |
4223 | ||
4224 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 4225 | if (HAS_PCH_IBX(dev_priv)) |
6f06ce18 | 4226 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4227 | |
4228 | /* still set train pattern 1 */ | |
4229 | reg = FDI_TX_CTL(pipe); | |
4230 | temp = I915_READ(reg); | |
4231 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4232 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4233 | I915_WRITE(reg, temp); | |
4234 | ||
4235 | reg = FDI_RX_CTL(pipe); | |
4236 | temp = I915_READ(reg); | |
6e266956 | 4237 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
4238 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4239 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4240 | } else { | |
4241 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4242 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4243 | } | |
4244 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4245 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4246 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4247 | I915_WRITE(reg, temp); |
4248 | ||
4249 | POSTING_READ(reg); | |
4250 | udelay(100); | |
4251 | } | |
4252 | ||
49d73912 | 4253 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) |
5dce5b93 | 4254 | { |
fa05887a DV |
4255 | struct drm_crtc *crtc; |
4256 | bool cleanup_done; | |
4257 | ||
4258 | drm_for_each_crtc(crtc, &dev_priv->drm) { | |
4259 | struct drm_crtc_commit *commit; | |
4260 | spin_lock(&crtc->commit_lock); | |
4261 | commit = list_first_entry_or_null(&crtc->commit_list, | |
4262 | struct drm_crtc_commit, commit_entry); | |
4263 | cleanup_done = commit ? | |
4264 | try_wait_for_completion(&commit->cleanup_done) : true; | |
4265 | spin_unlock(&crtc->commit_lock); | |
4266 | ||
4267 | if (cleanup_done) | |
5dce5b93 CW |
4268 | continue; |
4269 | ||
fa05887a | 4270 | drm_crtc_wait_one_vblank(crtc); |
5dce5b93 CW |
4271 | |
4272 | return true; | |
4273 | } | |
4274 | ||
4275 | return false; | |
4276 | } | |
4277 | ||
b7076546 | 4278 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
4279 | { |
4280 | u32 temp; | |
4281 | ||
4282 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4283 | ||
4284 | mutex_lock(&dev_priv->sb_lock); | |
4285 | ||
4286 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4287 | temp |= SBI_SSCCTL_DISABLE; | |
4288 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4289 | ||
4290 | mutex_unlock(&dev_priv->sb_lock); | |
4291 | } | |
4292 | ||
e615efe4 | 4293 | /* Program iCLKIP clock to the desired frequency */ |
0dcdc382 | 4294 | static void lpt_program_iclkip(struct intel_crtc *crtc) |
e615efe4 | 4295 | { |
0dcdc382 ACO |
4296 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4297 | int clock = crtc->config->base.adjusted_mode.crtc_clock; | |
e615efe4 ED |
4298 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4299 | u32 temp; | |
4300 | ||
060f02d8 | 4301 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4302 | |
64b46a06 VS |
4303 | /* The iCLK virtual clock root frequency is in MHz, |
4304 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4305 | * divisors, it is necessary to divide one by another, so we | |
4306 | * convert the virtual clock precision to KHz here for higher | |
4307 | * precision. | |
4308 | */ | |
4309 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4310 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4311 | u32 iclk_pi_range = 64; | |
64b46a06 | 4312 | u32 desired_divisor; |
e615efe4 | 4313 | |
64b46a06 VS |
4314 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4315 | clock << auxdiv); | |
4316 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4317 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4318 | |
64b46a06 VS |
4319 | /* |
4320 | * Near 20MHz is a corner case which is | |
4321 | * out of range for the 7-bit divisor | |
4322 | */ | |
4323 | if (divsel <= 0x7f) | |
4324 | break; | |
e615efe4 ED |
4325 | } |
4326 | ||
4327 | /* This should not happen with any sane values */ | |
4328 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4329 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4330 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4331 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4332 | ||
4333 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4334 | clock, |
e615efe4 ED |
4335 | auxdiv, |
4336 | divsel, | |
4337 | phasedir, | |
4338 | phaseinc); | |
4339 | ||
060f02d8 VS |
4340 | mutex_lock(&dev_priv->sb_lock); |
4341 | ||
e615efe4 | 4342 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4343 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4344 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4345 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4346 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4347 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4348 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4349 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4350 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4351 | |
4352 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4353 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4354 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4355 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4356 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4357 | |
4358 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4359 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4360 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4361 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4362 | |
060f02d8 VS |
4363 | mutex_unlock(&dev_priv->sb_lock); |
4364 | ||
e615efe4 ED |
4365 | /* Wait for initialization time */ |
4366 | udelay(24); | |
4367 | ||
4368 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4369 | } | |
4370 | ||
8802e5b6 VS |
4371 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4372 | { | |
4373 | u32 divsel, phaseinc, auxdiv; | |
4374 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4375 | u32 iclk_pi_range = 64; | |
4376 | u32 desired_divisor; | |
4377 | u32 temp; | |
4378 | ||
4379 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4380 | return 0; | |
4381 | ||
4382 | mutex_lock(&dev_priv->sb_lock); | |
4383 | ||
4384 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4385 | if (temp & SBI_SSCCTL_DISABLE) { | |
4386 | mutex_unlock(&dev_priv->sb_lock); | |
4387 | return 0; | |
4388 | } | |
4389 | ||
4390 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4391 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4392 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4393 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4394 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4395 | ||
4396 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4397 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4398 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4399 | ||
4400 | mutex_unlock(&dev_priv->sb_lock); | |
4401 | ||
4402 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4403 | ||
4404 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4405 | desired_divisor << auxdiv); | |
4406 | } | |
4407 | ||
275f01b2 DV |
4408 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4409 | enum pipe pch_transcoder) | |
4410 | { | |
4411 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4412 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4413 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4414 | |
4415 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4416 | I915_READ(HTOTAL(cpu_transcoder))); | |
4417 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4418 | I915_READ(HBLANK(cpu_transcoder))); | |
4419 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4420 | I915_READ(HSYNC(cpu_transcoder))); | |
4421 | ||
4422 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4423 | I915_READ(VTOTAL(cpu_transcoder))); | |
4424 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4425 | I915_READ(VBLANK(cpu_transcoder))); | |
4426 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4427 | I915_READ(VSYNC(cpu_transcoder))); | |
4428 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4429 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4430 | } | |
4431 | ||
003632d9 | 4432 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4433 | { |
fac5e23e | 4434 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4435 | uint32_t temp; |
4436 | ||
4437 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4438 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4439 | return; |
4440 | ||
4441 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4442 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4443 | ||
003632d9 ACO |
4444 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4445 | if (enable) | |
4446 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4447 | ||
4448 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4449 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4450 | POSTING_READ(SOUTH_CHICKEN1); | |
4451 | } | |
4452 | ||
4453 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4454 | { | |
4455 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4456 | |
4457 | switch (intel_crtc->pipe) { | |
4458 | case PIPE_A: | |
4459 | break; | |
4460 | case PIPE_B: | |
6e3c9717 | 4461 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4462 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4463 | else |
003632d9 | 4464 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4465 | |
4466 | break; | |
4467 | case PIPE_C: | |
003632d9 | 4468 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4469 | |
4470 | break; | |
4471 | default: | |
4472 | BUG(); | |
4473 | } | |
4474 | } | |
4475 | ||
c48b5305 VS |
4476 | /* Return which DP Port should be selected for Transcoder DP control */ |
4477 | static enum port | |
4cbe4b2b | 4478 | intel_trans_dp_port_sel(struct intel_crtc *crtc) |
c48b5305 | 4479 | { |
4cbe4b2b | 4480 | struct drm_device *dev = crtc->base.dev; |
c48b5305 VS |
4481 | struct intel_encoder *encoder; |
4482 | ||
4cbe4b2b | 4483 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
cca0502b | 4484 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4485 | encoder->type == INTEL_OUTPUT_EDP) |
4486 | return enc_to_dig_port(&encoder->base)->port; | |
4487 | } | |
4488 | ||
4489 | return -1; | |
4490 | } | |
4491 | ||
f67a559d JB |
4492 | /* |
4493 | * Enable PCH resources required for PCH ports: | |
4494 | * - PCH PLLs | |
4495 | * - FDI training & RX/TX | |
4496 | * - update transcoder timings | |
4497 | * - DP transcoding bits | |
4498 | * - transcoder | |
4499 | */ | |
2ce42273 | 4500 | static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state) |
0e23b99d | 4501 | { |
2ce42273 | 4502 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
4cbe4b2b | 4503 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4504 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 4505 | int pipe = crtc->pipe; |
f0f59a00 | 4506 | u32 temp; |
2c07245f | 4507 | |
ab9412ba | 4508 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4509 | |
fd6b8f43 | 4510 | if (IS_IVYBRIDGE(dev_priv)) |
4cbe4b2b | 4511 | ivybridge_update_fdi_bc_bifurcation(crtc); |
1fbc0d78 | 4512 | |
cd986abb DV |
4513 | /* Write the TU size bits before fdi link training, so that error |
4514 | * detection works. */ | |
4515 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4516 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4517 | ||
c98e9dcf | 4518 | /* For PCH output, training FDI link */ |
dc4a1094 | 4519 | dev_priv->display.fdi_link_train(crtc, crtc_state); |
2c07245f | 4520 | |
3ad8a208 DV |
4521 | /* We need to program the right clock selection before writing the pixel |
4522 | * mutliplier into the DPLL. */ | |
6e266956 | 4523 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 4524 | u32 sel; |
4b645f14 | 4525 | |
c98e9dcf | 4526 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4527 | temp |= TRANS_DPLL_ENABLE(pipe); |
4528 | sel = TRANS_DPLLB_SEL(pipe); | |
2ce42273 | 4529 | if (crtc_state->shared_dpll == |
8106ddbd | 4530 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) |
ee7b9f93 JB |
4531 | temp |= sel; |
4532 | else | |
4533 | temp &= ~sel; | |
c98e9dcf | 4534 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4535 | } |
5eddb70b | 4536 | |
3ad8a208 DV |
4537 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4538 | * transcoder, and we actually should do this to not upset any PCH | |
4539 | * transcoder that already use the clock when we share it. | |
4540 | * | |
4541 | * Note that enable_shared_dpll tries to do the right thing, but | |
4542 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4543 | * the right LVDS enable sequence. */ | |
4cbe4b2b | 4544 | intel_enable_shared_dpll(crtc); |
3ad8a208 | 4545 | |
d9b6cb56 JB |
4546 | /* set transcoder timing, panel must allow it */ |
4547 | assert_panel_unlocked(dev_priv, pipe); | |
4cbe4b2b | 4548 | ironlake_pch_transcoder_set_timings(crtc, pipe); |
8db9d77b | 4549 | |
303b81e0 | 4550 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4551 | |
c98e9dcf | 4552 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 | 4553 | if (HAS_PCH_CPT(dev_priv) && |
2ce42273 | 4554 | intel_crtc_has_dp_encoder(crtc_state)) { |
9c4edaee | 4555 | const struct drm_display_mode *adjusted_mode = |
2ce42273 | 4556 | &crtc_state->base.adjusted_mode; |
dfd07d72 | 4557 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4558 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4559 | temp = I915_READ(reg); |
4560 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4561 | TRANS_DP_SYNC_MASK | |
4562 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4563 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4564 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4565 | |
9c4edaee | 4566 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4567 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4568 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4569 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4570 | |
4571 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4572 | case PORT_B: |
5eddb70b | 4573 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4574 | break; |
c48b5305 | 4575 | case PORT_C: |
5eddb70b | 4576 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4577 | break; |
c48b5305 | 4578 | case PORT_D: |
5eddb70b | 4579 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4580 | break; |
4581 | default: | |
e95d41e1 | 4582 | BUG(); |
32f9d658 | 4583 | } |
2c07245f | 4584 | |
5eddb70b | 4585 | I915_WRITE(reg, temp); |
6be4a607 | 4586 | } |
b52eb4dc | 4587 | |
b8a4f404 | 4588 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4589 | } |
4590 | ||
2ce42273 | 4591 | static void lpt_pch_enable(const struct intel_crtc_state *crtc_state) |
1507e5bd | 4592 | { |
2ce42273 | 4593 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
0dcdc382 | 4594 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2ce42273 | 4595 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
1507e5bd | 4596 | |
a2196033 | 4597 | assert_pch_transcoder_disabled(dev_priv, PIPE_A); |
1507e5bd | 4598 | |
8c52b5e8 | 4599 | lpt_program_iclkip(crtc); |
1507e5bd | 4600 | |
0540e488 | 4601 | /* Set transcoder timing. */ |
0dcdc382 | 4602 | ironlake_pch_transcoder_set_timings(crtc, PIPE_A); |
1507e5bd | 4603 | |
937bb610 | 4604 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4605 | } |
4606 | ||
a1520318 | 4607 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4608 | { |
fac5e23e | 4609 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4610 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4611 | u32 temp; |
4612 | ||
4613 | temp = I915_READ(dslreg); | |
4614 | udelay(500); | |
4615 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4616 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4617 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4618 | } |
4619 | } | |
4620 | ||
86adf9d7 ML |
4621 | static int |
4622 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
d96a7d2a | 4623 | unsigned int scaler_user, int *scaler_id, |
86adf9d7 | 4624 | int src_w, int src_h, int dst_w, int dst_h) |
a1b2278e | 4625 | { |
86adf9d7 ML |
4626 | struct intel_crtc_scaler_state *scaler_state = |
4627 | &crtc_state->scaler_state; | |
4628 | struct intel_crtc *intel_crtc = | |
4629 | to_intel_crtc(crtc_state->base.crtc); | |
7f58cbb1 MK |
4630 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
4631 | const struct drm_display_mode *adjusted_mode = | |
4632 | &crtc_state->base.adjusted_mode; | |
a1b2278e | 4633 | int need_scaling; |
6156a456 | 4634 | |
d96a7d2a VS |
4635 | /* |
4636 | * Src coordinates are already rotated by 270 degrees for | |
4637 | * the 90/270 degree plane rotation cases (to match the | |
4638 | * GTT mapping), hence no need to account for rotation here. | |
4639 | */ | |
4640 | need_scaling = src_w != dst_w || src_h != dst_h; | |
a1b2278e | 4641 | |
e5c05931 SS |
4642 | if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) |
4643 | need_scaling = true; | |
4644 | ||
7f58cbb1 MK |
4645 | /* |
4646 | * Scaling/fitting not supported in IF-ID mode in GEN9+ | |
4647 | * TODO: Interlace fetch mode doesn't support YUV420 planar formats. | |
4648 | * Once NV12 is enabled, handle it here while allocating scaler | |
4649 | * for NV12. | |
4650 | */ | |
4651 | if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable && | |
4652 | need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
4653 | DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n"); | |
4654 | return -EINVAL; | |
4655 | } | |
4656 | ||
a1b2278e CK |
4657 | /* |
4658 | * if plane is being disabled or scaler is no more required or force detach | |
4659 | * - free scaler binded to this plane/crtc | |
4660 | * - in order to do this, update crtc->scaler_usage | |
4661 | * | |
4662 | * Here scaler state in crtc_state is set free so that | |
4663 | * scaler can be assigned to other user. Actual register | |
4664 | * update to free the scaler is done in plane/panel-fit programming. | |
4665 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4666 | */ | |
86adf9d7 | 4667 | if (force_detach || !need_scaling) { |
a1b2278e | 4668 | if (*scaler_id >= 0) { |
86adf9d7 | 4669 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4670 | scaler_state->scalers[*scaler_id].in_use = 0; |
4671 | ||
86adf9d7 ML |
4672 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4673 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4674 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4675 | scaler_state->scaler_users); |
4676 | *scaler_id = -1; | |
4677 | } | |
4678 | return 0; | |
4679 | } | |
4680 | ||
4681 | /* range checks */ | |
4682 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4683 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4684 | ||
4685 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4686 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4687 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4688 | "size is out of scaler range\n", |
86adf9d7 | 4689 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4690 | return -EINVAL; |
4691 | } | |
4692 | ||
86adf9d7 ML |
4693 | /* mark this plane as a scaler user in crtc_state */ |
4694 | scaler_state->scaler_users |= (1 << scaler_user); | |
4695 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4696 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4697 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4698 | scaler_state->scaler_users); | |
4699 | ||
4700 | return 0; | |
4701 | } | |
4702 | ||
4703 | /** | |
4704 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4705 | * | |
4706 | * @state: crtc's scaler state | |
86adf9d7 ML |
4707 | * |
4708 | * Return | |
4709 | * 0 - scaler_usage updated successfully | |
4710 | * error - requested scaling cannot be supported or other error condition | |
4711 | */ | |
e435d6e5 | 4712 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 | 4713 | { |
7c5f93b0 | 4714 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4715 | |
e435d6e5 | 4716 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
d96a7d2a | 4717 | &state->scaler_state.scaler_id, |
86adf9d7 | 4718 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4719 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4720 | } |
4721 | ||
4722 | /** | |
4723 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4724 | * | |
4725 | * @state: crtc's scaler state | |
86adf9d7 ML |
4726 | * @plane_state: atomic plane state to update |
4727 | * | |
4728 | * Return | |
4729 | * 0 - scaler_usage updated successfully | |
4730 | * error - requested scaling cannot be supported or other error condition | |
4731 | */ | |
da20eabd ML |
4732 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4733 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4734 | { |
4735 | ||
da20eabd ML |
4736 | struct intel_plane *intel_plane = |
4737 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4738 | struct drm_framebuffer *fb = plane_state->base.fb; |
4739 | int ret; | |
4740 | ||
936e71e3 | 4741 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4742 | |
86adf9d7 ML |
4743 | ret = skl_update_scaler(crtc_state, force_detach, |
4744 | drm_plane_index(&intel_plane->base), | |
4745 | &plane_state->scaler_id, | |
936e71e3 VS |
4746 | drm_rect_width(&plane_state->base.src) >> 16, |
4747 | drm_rect_height(&plane_state->base.src) >> 16, | |
4748 | drm_rect_width(&plane_state->base.dst), | |
4749 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4750 | |
4751 | if (ret || plane_state->scaler_id < 0) | |
4752 | return ret; | |
4753 | ||
a1b2278e | 4754 | /* check colorkey */ |
818ed961 | 4755 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4756 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4757 | intel_plane->base.base.id, | |
4758 | intel_plane->base.name); | |
a1b2278e CK |
4759 | return -EINVAL; |
4760 | } | |
4761 | ||
4762 | /* Check src format */ | |
438b74a5 | 4763 | switch (fb->format->format) { |
86adf9d7 ML |
4764 | case DRM_FORMAT_RGB565: |
4765 | case DRM_FORMAT_XBGR8888: | |
4766 | case DRM_FORMAT_XRGB8888: | |
4767 | case DRM_FORMAT_ABGR8888: | |
4768 | case DRM_FORMAT_ARGB8888: | |
4769 | case DRM_FORMAT_XRGB2101010: | |
4770 | case DRM_FORMAT_XBGR2101010: | |
4771 | case DRM_FORMAT_YUYV: | |
4772 | case DRM_FORMAT_YVYU: | |
4773 | case DRM_FORMAT_UYVY: | |
4774 | case DRM_FORMAT_VYUY: | |
4775 | break; | |
4776 | default: | |
72660ce0 VS |
4777 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4778 | intel_plane->base.base.id, intel_plane->base.name, | |
438b74a5 | 4779 | fb->base.id, fb->format->format); |
86adf9d7 | 4780 | return -EINVAL; |
a1b2278e CK |
4781 | } |
4782 | ||
a1b2278e CK |
4783 | return 0; |
4784 | } | |
4785 | ||
e435d6e5 ML |
4786 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4787 | { | |
4788 | int i; | |
4789 | ||
4790 | for (i = 0; i < crtc->num_scalers; i++) | |
4791 | skl_detach_scaler(crtc, i); | |
4792 | } | |
4793 | ||
4794 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4795 | { |
4796 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4797 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4798 | int pipe = crtc->pipe; |
a1b2278e CK |
4799 | struct intel_crtc_scaler_state *scaler_state = |
4800 | &crtc->config->scaler_state; | |
4801 | ||
6e3c9717 | 4802 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4803 | int id; |
4804 | ||
c3f8ad57 | 4805 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) |
a1b2278e | 4806 | return; |
a1b2278e CK |
4807 | |
4808 | id = scaler_state->scaler_id; | |
4809 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4810 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4811 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4812 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
bd2e244f JB |
4813 | } |
4814 | } | |
4815 | ||
b074cec8 JB |
4816 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4817 | { | |
4818 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4819 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4820 | int pipe = crtc->pipe; |
4821 | ||
6e3c9717 | 4822 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4823 | /* Force use of hard-coded filter coefficients |
4824 | * as some pre-programmed values are broken, | |
4825 | * e.g. x201. | |
4826 | */ | |
fd6b8f43 | 4827 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) |
b074cec8 JB |
4828 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
4829 | PF_PIPE_SEL_IVB(pipe)); | |
4830 | else | |
4831 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4832 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4833 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4834 | } |
4835 | } | |
4836 | ||
20bc8673 | 4837 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4838 | { |
cea165c3 | 4839 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4840 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4841 | |
6e3c9717 | 4842 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4843 | return; |
4844 | ||
307e4498 ML |
4845 | /* |
4846 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4847 | * This function is called from post_plane_update, which is run after | |
4848 | * a vblank wait. | |
4849 | */ | |
cea165c3 | 4850 | |
d77e4531 | 4851 | assert_plane_enabled(dev_priv, crtc->plane); |
8652744b | 4852 | if (IS_BROADWELL(dev_priv)) { |
9f817501 | 4853 | mutex_lock(&dev_priv->pcu_lock); |
61843f0e VS |
4854 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, |
4855 | IPS_ENABLE | IPS_PCODE_CONTROL)); | |
9f817501 | 4856 | mutex_unlock(&dev_priv->pcu_lock); |
2a114cc1 BW |
4857 | /* Quoting Art Runyan: "its not safe to expect any particular |
4858 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4859 | * mailbox." Moreover, the mailbox may return a bogus state, |
4860 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4861 | */ |
4862 | } else { | |
4863 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4864 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4865 | * is essentially intel_wait_for_vblank. If we don't have this | |
4866 | * and don't wait for vblanks until the end of crtc_enable, then | |
4867 | * the HW state readout code will complain that the expected | |
4868 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4869 | if (intel_wait_for_register(dev_priv, |
4870 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4871 | 50)) | |
2a114cc1 BW |
4872 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4873 | } | |
d77e4531 PZ |
4874 | } |
4875 | ||
20bc8673 | 4876 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4877 | { |
4878 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4879 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4880 | |
6e3c9717 | 4881 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4882 | return; |
4883 | ||
4884 | assert_plane_enabled(dev_priv, crtc->plane); | |
8652744b | 4885 | if (IS_BROADWELL(dev_priv)) { |
9f817501 | 4886 | mutex_lock(&dev_priv->pcu_lock); |
2a114cc1 | 4887 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); |
9f817501 | 4888 | mutex_unlock(&dev_priv->pcu_lock); |
23d0b130 | 4889 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4890 | if (intel_wait_for_register(dev_priv, |
4891 | IPS_CTL, IPS_ENABLE, 0, | |
4892 | 42)) | |
23d0b130 | 4893 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4894 | } else { |
2a114cc1 | 4895 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4896 | POSTING_READ(IPS_CTL); |
4897 | } | |
d77e4531 PZ |
4898 | |
4899 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 4900 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
4901 | } |
4902 | ||
7cac945f | 4903 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4904 | { |
7cac945f | 4905 | if (intel_crtc->overlay) { |
d3eedb1a | 4906 | struct drm_device *dev = intel_crtc->base.dev; |
d3eedb1a VS |
4907 | |
4908 | mutex_lock(&dev->struct_mutex); | |
d3eedb1a | 4909 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
d3eedb1a VS |
4910 | mutex_unlock(&dev->struct_mutex); |
4911 | } | |
4912 | ||
4913 | /* Let userspace switch the overlay on again. In most cases userspace | |
4914 | * has to recompute where to put it anyway. | |
4915 | */ | |
4916 | } | |
4917 | ||
87d4300a ML |
4918 | /** |
4919 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4920 | * @crtc: the CRTC whose primary plane was just enabled | |
4921 | * | |
4922 | * Performs potentially sleeping operations that must be done after the primary | |
4923 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4924 | * called due to an explicit primary plane update, or due to an implicit | |
4925 | * re-enable that is caused when a sprite plane is updated to no longer | |
4926 | * completely hide the primary plane. | |
4927 | */ | |
4928 | static void | |
4929 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4930 | { |
4931 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4932 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4933 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4934 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4935 | |
87d4300a ML |
4936 | /* |
4937 | * FIXME IPS should be fine as long as one plane is | |
4938 | * enabled, but in practice it seems to have problems | |
4939 | * when going from primary only to sprite only and vice | |
4940 | * versa. | |
4941 | */ | |
a5c4d7bc VS |
4942 | hsw_enable_ips(intel_crtc); |
4943 | ||
f99d7069 | 4944 | /* |
87d4300a ML |
4945 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4946 | * So don't enable underrun reporting before at least some planes | |
4947 | * are enabled. | |
4948 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4949 | * but leave the pipe running. | |
f99d7069 | 4950 | */ |
5db94019 | 4951 | if (IS_GEN2(dev_priv)) |
87d4300a ML |
4952 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4953 | ||
aca7b684 VS |
4954 | /* Underruns don't always raise interrupts, so check manually. */ |
4955 | intel_check_cpu_fifo_underruns(dev_priv); | |
4956 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4957 | } |
4958 | ||
2622a081 | 4959 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4960 | static void |
4961 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4962 | { |
4963 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4964 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4965 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4966 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4967 | |
87d4300a ML |
4968 | /* |
4969 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4970 | * So diasble underrun reporting before all the planes get disabled. | |
4971 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4972 | * but leave the pipe running. | |
4973 | */ | |
5db94019 | 4974 | if (IS_GEN2(dev_priv)) |
87d4300a | 4975 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
a5c4d7bc | 4976 | |
2622a081 VS |
4977 | /* |
4978 | * FIXME IPS should be fine as long as one plane is | |
4979 | * enabled, but in practice it seems to have problems | |
4980 | * when going from primary only to sprite only and vice | |
4981 | * versa. | |
4982 | */ | |
4983 | hsw_disable_ips(intel_crtc); | |
4984 | } | |
4985 | ||
4986 | /* FIXME get rid of this and use pre_plane_update */ | |
4987 | static void | |
4988 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4989 | { | |
4990 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4991 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
4992 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4993 | int pipe = intel_crtc->pipe; | |
4994 | ||
4995 | intel_pre_disable_primary(crtc); | |
4996 | ||
87d4300a ML |
4997 | /* |
4998 | * Vblank time updates from the shadow to live plane control register | |
4999 | * are blocked if the memory self-refresh mode is active at that | |
5000 | * moment. So to make sure the plane gets truly disabled, disable | |
5001 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5002 | * will be checked/applied by the HW only at the next frame start | |
5003 | * event which is after the vblank start event, so we need to have a | |
5004 | * wait-for-vblank between disabling the plane and the pipe. | |
5005 | */ | |
11a85d6a VS |
5006 | if (HAS_GMCH_DISPLAY(dev_priv) && |
5007 | intel_set_memory_cxsr(dev_priv, false)) | |
0f0f74bc | 5008 | intel_wait_for_vblank(dev_priv, pipe); |
87d4300a ML |
5009 | } |
5010 | ||
5a21b665 DV |
5011 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
5012 | { | |
5013 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
5014 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
5015 | struct intel_crtc_state *pipe_config = | |
f9a8c149 VS |
5016 | intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state), |
5017 | crtc); | |
5a21b665 DV |
5018 | struct drm_plane *primary = crtc->base.primary; |
5019 | struct drm_plane_state *old_pri_state = | |
5020 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5021 | ||
5748b6a1 | 5022 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 | 5023 | |
5a21b665 | 5024 | if (pipe_config->update_wm_post && pipe_config->base.active) |
432081bc | 5025 | intel_update_watermarks(crtc); |
5a21b665 DV |
5026 | |
5027 | if (old_pri_state) { | |
5028 | struct intel_plane_state *primary_state = | |
f9a8c149 VS |
5029 | intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state), |
5030 | to_intel_plane(primary)); | |
5a21b665 DV |
5031 | struct intel_plane_state *old_primary_state = |
5032 | to_intel_plane_state(old_pri_state); | |
5033 | ||
5034 | intel_fbc_post_update(crtc); | |
5035 | ||
936e71e3 | 5036 | if (primary_state->base.visible && |
5a21b665 | 5037 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 5038 | !old_primary_state->base.visible)) |
5a21b665 DV |
5039 | intel_post_enable_primary(&crtc->base); |
5040 | } | |
5041 | } | |
5042 | ||
aa5e9b47 ML |
5043 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, |
5044 | struct intel_crtc_state *pipe_config) | |
ac21b225 | 5045 | { |
5c74cd73 | 5046 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 5047 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5048 | struct drm_i915_private *dev_priv = to_i915(dev); |
5c74cd73 ML |
5049 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
5050 | struct drm_plane *primary = crtc->base.primary; | |
5051 | struct drm_plane_state *old_pri_state = | |
5052 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5053 | bool modeset = needs_modeset(&pipe_config->base); | |
ccf010fb ML |
5054 | struct intel_atomic_state *old_intel_state = |
5055 | to_intel_atomic_state(old_state); | |
ac21b225 | 5056 | |
5c74cd73 ML |
5057 | if (old_pri_state) { |
5058 | struct intel_plane_state *primary_state = | |
f9a8c149 VS |
5059 | intel_atomic_get_new_plane_state(old_intel_state, |
5060 | to_intel_plane(primary)); | |
5c74cd73 ML |
5061 | struct intel_plane_state *old_primary_state = |
5062 | to_intel_plane_state(old_pri_state); | |
5063 | ||
faf68d92 | 5064 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 5065 | |
936e71e3 VS |
5066 | if (old_primary_state->base.visible && |
5067 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
5068 | intel_pre_disable_primary(&crtc->base); |
5069 | } | |
852eb00d | 5070 | |
5eeb798b VS |
5071 | /* |
5072 | * Vblank time updates from the shadow to live plane control register | |
5073 | * are blocked if the memory self-refresh mode is active at that | |
5074 | * moment. So to make sure the plane gets truly disabled, disable | |
5075 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5076 | * will be checked/applied by the HW only at the next frame start | |
5077 | * event which is after the vblank start event, so we need to have a | |
5078 | * wait-for-vblank between disabling the plane and the pipe. | |
5079 | */ | |
5080 | if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active && | |
5081 | pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) | |
5082 | intel_wait_for_vblank(dev_priv, crtc->pipe); | |
92826fcd | 5083 | |
ed4a6a7c MR |
5084 | /* |
5085 | * IVB workaround: must disable low power watermarks for at least | |
5086 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
5087 | * when scaling is disabled. | |
5088 | * | |
5089 | * WaCxSRDisabledForSpriteScaling:ivb | |
5090 | */ | |
ddd2b792 | 5091 | if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev)) |
0f0f74bc | 5092 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
ed4a6a7c MR |
5093 | |
5094 | /* | |
5095 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
5096 | * watermark programming here. | |
5097 | */ | |
5098 | if (needs_modeset(&pipe_config->base)) | |
5099 | return; | |
5100 | ||
5101 | /* | |
5102 | * For platforms that support atomic watermarks, program the | |
5103 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
5104 | * will be the intermediate values that are safe for both pre- and | |
5105 | * post- vblank; when vblank happens, the 'active' values will be set | |
5106 | * to the final 'target' values and we'll do this again to get the | |
5107 | * optimal watermarks. For gen9+ platforms, the values we program here | |
5108 | * will be the final target values which will get automatically latched | |
5109 | * at vblank time; no further programming will be necessary. | |
5110 | * | |
5111 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
5112 | * we'll continue to update watermarks the old way, if flags tell | |
5113 | * us to. | |
5114 | */ | |
5115 | if (dev_priv->display.initial_watermarks != NULL) | |
ccf010fb ML |
5116 | dev_priv->display.initial_watermarks(old_intel_state, |
5117 | pipe_config); | |
caed361d | 5118 | else if (pipe_config->update_wm_pre) |
432081bc | 5119 | intel_update_watermarks(crtc); |
ac21b225 ML |
5120 | } |
5121 | ||
d032ffa0 | 5122 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5123 | { |
5124 | struct drm_device *dev = crtc->dev; | |
5125 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5126 | struct drm_plane *p; |
87d4300a ML |
5127 | int pipe = intel_crtc->pipe; |
5128 | ||
7cac945f | 5129 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5130 | |
d032ffa0 | 5131 | drm_for_each_plane_mask(p, dev, plane_mask) |
282dbf9b | 5132 | to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc); |
f98551ae | 5133 | |
f99d7069 DV |
5134 | /* |
5135 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5136 | * to compute the mask of flip planes precisely. For the time being | |
5137 | * consider this a flip to a NULL plane. | |
5138 | */ | |
5748b6a1 | 5139 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
5140 | } |
5141 | ||
fb1c98b1 | 5142 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
fd6bbda9 | 5143 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5144 | struct drm_atomic_state *old_state) |
5145 | { | |
aa5e9b47 | 5146 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5147 | struct drm_connector *conn; |
5148 | int i; | |
5149 | ||
aa5e9b47 | 5150 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5151 | struct intel_encoder *encoder = |
5152 | to_intel_encoder(conn_state->best_encoder); | |
5153 | ||
5154 | if (conn_state->crtc != crtc) | |
5155 | continue; | |
5156 | ||
5157 | if (encoder->pre_pll_enable) | |
fd6bbda9 | 5158 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5159 | } |
5160 | } | |
5161 | ||
5162 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5163 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5164 | struct drm_atomic_state *old_state) |
5165 | { | |
aa5e9b47 | 5166 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5167 | struct drm_connector *conn; |
5168 | int i; | |
5169 | ||
aa5e9b47 | 5170 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5171 | struct intel_encoder *encoder = |
5172 | to_intel_encoder(conn_state->best_encoder); | |
5173 | ||
5174 | if (conn_state->crtc != crtc) | |
5175 | continue; | |
5176 | ||
5177 | if (encoder->pre_enable) | |
fd6bbda9 | 5178 | encoder->pre_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5179 | } |
5180 | } | |
5181 | ||
5182 | static void intel_encoders_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5183 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5184 | struct drm_atomic_state *old_state) |
5185 | { | |
aa5e9b47 | 5186 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5187 | struct drm_connector *conn; |
5188 | int i; | |
5189 | ||
aa5e9b47 | 5190 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5191 | struct intel_encoder *encoder = |
5192 | to_intel_encoder(conn_state->best_encoder); | |
5193 | ||
5194 | if (conn_state->crtc != crtc) | |
5195 | continue; | |
5196 | ||
fd6bbda9 | 5197 | encoder->enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5198 | intel_opregion_notify_encoder(encoder, true); |
5199 | } | |
5200 | } | |
5201 | ||
5202 | static void intel_encoders_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5203 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5204 | struct drm_atomic_state *old_state) |
5205 | { | |
5206 | struct drm_connector_state *old_conn_state; | |
5207 | struct drm_connector *conn; | |
5208 | int i; | |
5209 | ||
aa5e9b47 | 5210 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5211 | struct intel_encoder *encoder = |
5212 | to_intel_encoder(old_conn_state->best_encoder); | |
5213 | ||
5214 | if (old_conn_state->crtc != crtc) | |
5215 | continue; | |
5216 | ||
5217 | intel_opregion_notify_encoder(encoder, false); | |
fd6bbda9 | 5218 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5219 | } |
5220 | } | |
5221 | ||
5222 | static void intel_encoders_post_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5223 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5224 | struct drm_atomic_state *old_state) |
5225 | { | |
5226 | struct drm_connector_state *old_conn_state; | |
5227 | struct drm_connector *conn; | |
5228 | int i; | |
5229 | ||
aa5e9b47 | 5230 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5231 | struct intel_encoder *encoder = |
5232 | to_intel_encoder(old_conn_state->best_encoder); | |
5233 | ||
5234 | if (old_conn_state->crtc != crtc) | |
5235 | continue; | |
5236 | ||
5237 | if (encoder->post_disable) | |
fd6bbda9 | 5238 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5239 | } |
5240 | } | |
5241 | ||
5242 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5243 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5244 | struct drm_atomic_state *old_state) |
5245 | { | |
5246 | struct drm_connector_state *old_conn_state; | |
5247 | struct drm_connector *conn; | |
5248 | int i; | |
5249 | ||
aa5e9b47 | 5250 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5251 | struct intel_encoder *encoder = |
5252 | to_intel_encoder(old_conn_state->best_encoder); | |
5253 | ||
5254 | if (old_conn_state->crtc != crtc) | |
5255 | continue; | |
5256 | ||
5257 | if (encoder->post_pll_disable) | |
fd6bbda9 | 5258 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5259 | } |
5260 | } | |
5261 | ||
4a806558 ML |
5262 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
5263 | struct drm_atomic_state *old_state) | |
f67a559d | 5264 | { |
4a806558 | 5265 | struct drm_crtc *crtc = pipe_config->base.crtc; |
f67a559d | 5266 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5267 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d JB |
5268 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5269 | int pipe = intel_crtc->pipe; | |
ccf010fb ML |
5270 | struct intel_atomic_state *old_intel_state = |
5271 | to_intel_atomic_state(old_state); | |
f67a559d | 5272 | |
53d9f4e9 | 5273 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5274 | return; |
5275 | ||
b2c0593a VS |
5276 | /* |
5277 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5278 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5279 | * | |
5280 | * On ILK we get an occasional spurious CPU pipe underruns | |
5281 | * between eDP port A enable and vdd enable. Also PCH port | |
5282 | * enable seems to result in the occasional CPU pipe underrun. | |
5283 | * | |
5284 | * Spurious PCH underruns also occur during PCH enabling. | |
5285 | */ | |
5286 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5287 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5288 | if (intel_crtc->config->has_pch_encoder) |
5289 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5290 | ||
6e3c9717 | 5291 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5292 | intel_prepare_shared_dpll(intel_crtc); |
5293 | ||
37a5650b | 5294 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5295 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5296 | |
5297 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5298 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5299 | |
6e3c9717 | 5300 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5301 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5302 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5303 | } |
5304 | ||
5305 | ironlake_set_pipeconf(crtc); | |
5306 | ||
f67a559d | 5307 | intel_crtc->active = true; |
8664281b | 5308 | |
fd6bbda9 | 5309 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f67a559d | 5310 | |
6e3c9717 | 5311 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5312 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5313 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5314 | * enabling. */ | |
88cefb6c | 5315 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5316 | } else { |
5317 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5318 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5319 | } | |
f67a559d | 5320 | |
b074cec8 | 5321 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5322 | |
9c54c0dd JB |
5323 | /* |
5324 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5325 | * clocks enabled | |
5326 | */ | |
b95c5321 | 5327 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5328 | |
1d5bf5d9 | 5329 | if (dev_priv->display.initial_watermarks != NULL) |
ccf010fb | 5330 | dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); |
e1fdc473 | 5331 | intel_enable_pipe(intel_crtc); |
f67a559d | 5332 | |
6e3c9717 | 5333 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5334 | ironlake_pch_enable(pipe_config); |
c98e9dcf | 5335 | |
f9b61ff6 DV |
5336 | assert_vblank_disabled(crtc); |
5337 | drm_crtc_vblank_on(crtc); | |
5338 | ||
fd6bbda9 | 5339 | intel_encoders_enable(crtc, pipe_config, old_state); |
61b77ddd | 5340 | |
6e266956 | 5341 | if (HAS_PCH_CPT(dev_priv)) |
a1520318 | 5342 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5343 | |
5344 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5345 | if (intel_crtc->config->has_pch_encoder) | |
0f0f74bc | 5346 | intel_wait_for_vblank(dev_priv, pipe); |
b2c0593a | 5347 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5348 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5349 | } |
5350 | ||
42db64ef PZ |
5351 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5352 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5353 | { | |
50a0bc90 | 5354 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5355 | } |
5356 | ||
ed69cd40 ID |
5357 | static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, |
5358 | enum pipe pipe, bool apply) | |
5359 | { | |
5360 | u32 val = I915_READ(CLKGATE_DIS_PSL(pipe)); | |
5361 | u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; | |
5362 | ||
5363 | if (apply) | |
5364 | val |= mask; | |
5365 | else | |
5366 | val &= ~mask; | |
5367 | ||
5368 | I915_WRITE(CLKGATE_DIS_PSL(pipe), val); | |
5369 | } | |
5370 | ||
4a806558 ML |
5371 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
5372 | struct drm_atomic_state *old_state) | |
4f771f10 | 5373 | { |
4a806558 | 5374 | struct drm_crtc *crtc = pipe_config->base.crtc; |
6315b5d3 | 5375 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
4f771f10 | 5376 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99d736a2 | 5377 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5378 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ccf010fb ML |
5379 | struct intel_atomic_state *old_intel_state = |
5380 | to_intel_atomic_state(old_state); | |
ed69cd40 | 5381 | bool psl_clkgate_wa; |
4f771f10 | 5382 | |
53d9f4e9 | 5383 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5384 | return; |
5385 | ||
fd6bbda9 | 5386 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
95a7a2ae | 5387 | |
8106ddbd | 5388 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5389 | intel_enable_shared_dpll(intel_crtc); |
5390 | ||
37a5650b | 5391 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5392 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5393 | |
d7edc4e5 | 5394 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5395 | intel_set_pipe_timings(intel_crtc); |
5396 | ||
bc58be60 | 5397 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5398 | |
4d1de975 JN |
5399 | if (cpu_transcoder != TRANSCODER_EDP && |
5400 | !transcoder_is_dsi(cpu_transcoder)) { | |
5401 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5402 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5403 | } |
5404 | ||
6e3c9717 | 5405 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5406 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5407 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5408 | } |
5409 | ||
d7edc4e5 | 5410 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5411 | haswell_set_pipeconf(crtc); |
5412 | ||
391bf048 | 5413 | haswell_set_pipemisc(crtc); |
229fca97 | 5414 | |
b95c5321 | 5415 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5416 | |
4f771f10 | 5417 | intel_crtc->active = true; |
8664281b | 5418 | |
fd6bbda9 | 5419 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
4f771f10 | 5420 | |
d7edc4e5 | 5421 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5422 | intel_ddi_enable_pipe_clock(pipe_config); |
4f771f10 | 5423 | |
ed69cd40 ID |
5424 | /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */ |
5425 | psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) && | |
5426 | intel_crtc->config->pch_pfit.enabled; | |
5427 | if (psl_clkgate_wa) | |
5428 | glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); | |
5429 | ||
6315b5d3 | 5430 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5431 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5432 | else |
1c132b44 | 5433 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5434 | |
5435 | /* | |
5436 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5437 | * clocks enabled | |
5438 | */ | |
b95c5321 | 5439 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5440 | |
3dc38eea | 5441 | intel_ddi_set_pipe_settings(pipe_config); |
d7edc4e5 | 5442 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5443 | intel_ddi_enable_transcoder_func(pipe_config); |
4f771f10 | 5444 | |
1d5bf5d9 | 5445 | if (dev_priv->display.initial_watermarks != NULL) |
3125d39f | 5446 | dev_priv->display.initial_watermarks(old_intel_state, pipe_config); |
4d1de975 JN |
5447 | |
5448 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5449 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5450 | intel_enable_pipe(intel_crtc); |
42db64ef | 5451 | |
6e3c9717 | 5452 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5453 | lpt_pch_enable(pipe_config); |
4f771f10 | 5454 | |
0037071d | 5455 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5456 | intel_ddi_set_vc_payload_alloc(pipe_config, true); |
0e32b39c | 5457 | |
f9b61ff6 DV |
5458 | assert_vblank_disabled(crtc); |
5459 | drm_crtc_vblank_on(crtc); | |
5460 | ||
fd6bbda9 | 5461 | intel_encoders_enable(crtc, pipe_config, old_state); |
4f771f10 | 5462 | |
ed69cd40 | 5463 | if (psl_clkgate_wa) { |
0f0f74bc | 5464 | intel_wait_for_vblank(dev_priv, pipe); |
ed69cd40 | 5465 | glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); |
6b698516 | 5466 | } |
d2d65408 | 5467 | |
e4916946 PZ |
5468 | /* If we change the relative order between pipe/planes enabling, we need |
5469 | * to change the workaround. */ | |
99d736a2 | 5470 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
772c2a51 | 5471 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
5472 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
5473 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 5474 | } |
4f771f10 PZ |
5475 | } |
5476 | ||
bfd16b2a | 5477 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5478 | { |
5479 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5480 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5481 | int pipe = crtc->pipe; |
5482 | ||
5483 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5484 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5485 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5486 | I915_WRITE(PF_CTL(pipe), 0); |
5487 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5488 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5489 | } | |
5490 | } | |
5491 | ||
4a806558 ML |
5492 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5493 | struct drm_atomic_state *old_state) | |
6be4a607 | 5494 | { |
4a806558 | 5495 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6be4a607 | 5496 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5497 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 JB |
5498 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5499 | int pipe = intel_crtc->pipe; | |
b52eb4dc | 5500 | |
b2c0593a VS |
5501 | /* |
5502 | * Sometimes spurious CPU pipe underruns happen when the | |
5503 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5504 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5505 | */ | |
5506 | if (intel_crtc->config->has_pch_encoder) { | |
5507 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5508 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5509 | } |
37ca8d4c | 5510 | |
fd6bbda9 | 5511 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
ea9d758d | 5512 | |
f9b61ff6 DV |
5513 | drm_crtc_vblank_off(crtc); |
5514 | assert_vblank_disabled(crtc); | |
5515 | ||
575f7ab7 | 5516 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5517 | |
bfd16b2a | 5518 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5519 | |
b2c0593a | 5520 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5521 | ironlake_fdi_disable(crtc); |
5522 | ||
fd6bbda9 | 5523 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
2c07245f | 5524 | |
6e3c9717 | 5525 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5526 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5527 | |
6e266956 | 5528 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
5529 | i915_reg_t reg; |
5530 | u32 temp; | |
5531 | ||
d925c59a DV |
5532 | /* disable TRANS_DP_CTL */ |
5533 | reg = TRANS_DP_CTL(pipe); | |
5534 | temp = I915_READ(reg); | |
5535 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5536 | TRANS_DP_PORT_SEL_MASK); | |
5537 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5538 | I915_WRITE(reg, temp); | |
5539 | ||
5540 | /* disable DPLL_SEL */ | |
5541 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5542 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5543 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5544 | } |
e3421a18 | 5545 | |
d925c59a DV |
5546 | ironlake_fdi_pll_disable(intel_crtc); |
5547 | } | |
81b088ca | 5548 | |
b2c0593a | 5549 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5550 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5551 | } |
1b3c7a47 | 5552 | |
4a806558 ML |
5553 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5554 | struct drm_atomic_state *old_state) | |
ee7b9f93 | 5555 | { |
4a806558 | 5556 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6315b5d3 | 5557 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee7b9f93 | 5558 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 5559 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5560 | |
fd6bbda9 | 5561 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4f771f10 | 5562 | |
f9b61ff6 DV |
5563 | drm_crtc_vblank_off(crtc); |
5564 | assert_vblank_disabled(crtc); | |
5565 | ||
4d1de975 | 5566 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5567 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5568 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5569 | |
0037071d | 5570 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5571 | intel_ddi_set_vc_payload_alloc(intel_crtc->config, false); |
a4bf214f | 5572 | |
d7edc4e5 | 5573 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5574 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5575 | |
6315b5d3 | 5576 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5577 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5578 | else |
bfd16b2a | 5579 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5580 | |
d7edc4e5 | 5581 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5582 | intel_ddi_disable_pipe_clock(intel_crtc->config); |
4f771f10 | 5583 | |
fd6bbda9 | 5584 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
4f771f10 PZ |
5585 | } |
5586 | ||
2dd24552 JB |
5587 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5588 | { | |
5589 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5590 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5591 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5592 | |
681a8504 | 5593 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5594 | return; |
5595 | ||
2dd24552 | 5596 | /* |
c0b03411 DV |
5597 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5598 | * according to register description and PRM. | |
2dd24552 | 5599 | */ |
c0b03411 DV |
5600 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5601 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5602 | |
b074cec8 JB |
5603 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5604 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5605 | |
5606 | /* Border color in case we don't scale up to the full screen. Black by | |
5607 | * default, change to something else for debugging. */ | |
5608 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5609 | } |
5610 | ||
79f255a0 | 5611 | enum intel_display_power_domain intel_port_to_power_domain(enum port port) |
d05410f9 DA |
5612 | { |
5613 | switch (port) { | |
5614 | case PORT_A: | |
6331a704 | 5615 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5616 | case PORT_B: |
6331a704 | 5617 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5618 | case PORT_C: |
6331a704 | 5619 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5620 | case PORT_D: |
6331a704 | 5621 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5622 | case PORT_E: |
6331a704 | 5623 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5624 | default: |
b9fec167 | 5625 | MISSING_CASE(port); |
d05410f9 DA |
5626 | return POWER_DOMAIN_PORT_OTHER; |
5627 | } | |
5628 | } | |
5629 | ||
d8fc70b7 ACO |
5630 | static u64 get_crtc_power_domains(struct drm_crtc *crtc, |
5631 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5632 | { |
319be8ae | 5633 | struct drm_device *dev = crtc->dev; |
37255d8d | 5634 | struct drm_i915_private *dev_priv = to_i915(dev); |
74bff5f9 | 5635 | struct drm_encoder *encoder; |
319be8ae ID |
5636 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5637 | enum pipe pipe = intel_crtc->pipe; | |
d8fc70b7 | 5638 | u64 mask; |
74bff5f9 | 5639 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5640 | |
74bff5f9 | 5641 | if (!crtc_state->base.active) |
292b990e ML |
5642 | return 0; |
5643 | ||
77d22dca ID |
5644 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5645 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5646 | if (crtc_state->pch_pfit.enabled || |
5647 | crtc_state->pch_pfit.force_thru) | |
d8fc70b7 | 5648 | mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
77d22dca | 5649 | |
74bff5f9 ML |
5650 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5651 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5652 | ||
79f255a0 | 5653 | mask |= BIT_ULL(intel_encoder->power_domain); |
74bff5f9 | 5654 | } |
319be8ae | 5655 | |
37255d8d ML |
5656 | if (HAS_DDI(dev_priv) && crtc_state->has_audio) |
5657 | mask |= BIT(POWER_DOMAIN_AUDIO); | |
5658 | ||
15e7ec29 | 5659 | if (crtc_state->shared_dpll) |
d8fc70b7 | 5660 | mask |= BIT_ULL(POWER_DOMAIN_PLLS); |
15e7ec29 | 5661 | |
77d22dca ID |
5662 | return mask; |
5663 | } | |
5664 | ||
d2d15016 | 5665 | static u64 |
74bff5f9 ML |
5666 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, |
5667 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5668 | { |
fac5e23e | 5669 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5670 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5671 | enum intel_display_power_domain domain; | |
d8fc70b7 | 5672 | u64 domains, new_domains, old_domains; |
77d22dca | 5673 | |
292b990e | 5674 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5675 | intel_crtc->enabled_power_domains = new_domains = |
5676 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5677 | |
5a21b665 | 5678 | domains = new_domains & ~old_domains; |
292b990e ML |
5679 | |
5680 | for_each_power_domain(domain, domains) | |
5681 | intel_display_power_get(dev_priv, domain); | |
5682 | ||
5a21b665 | 5683 | return old_domains & ~new_domains; |
292b990e ML |
5684 | } |
5685 | ||
5686 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
d8fc70b7 | 5687 | u64 domains) |
292b990e ML |
5688 | { |
5689 | enum intel_display_power_domain domain; | |
5690 | ||
5691 | for_each_power_domain(domain, domains) | |
5692 | intel_display_power_put(dev_priv, domain); | |
5693 | } | |
77d22dca | 5694 | |
7ff89ca2 VS |
5695 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
5696 | struct drm_atomic_state *old_state) | |
adafdc6f | 5697 | { |
ff32c54e VS |
5698 | struct intel_atomic_state *old_intel_state = |
5699 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5700 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5701 | struct drm_device *dev = crtc->dev; | |
5702 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5703 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5704 | int pipe = intel_crtc->pipe; | |
adafdc6f | 5705 | |
7ff89ca2 VS |
5706 | if (WARN_ON(intel_crtc->active)) |
5707 | return; | |
adafdc6f | 5708 | |
7ff89ca2 VS |
5709 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5710 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
b2045352 | 5711 | |
7ff89ca2 VS |
5712 | intel_set_pipe_timings(intel_crtc); |
5713 | intel_set_pipe_src_size(intel_crtc); | |
b2045352 | 5714 | |
7ff89ca2 VS |
5715 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
5716 | struct drm_i915_private *dev_priv = to_i915(dev); | |
560a7ae4 | 5717 | |
7ff89ca2 VS |
5718 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); |
5719 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
560a7ae4 DL |
5720 | } |
5721 | ||
7ff89ca2 | 5722 | i9xx_set_pipeconf(intel_crtc); |
560a7ae4 | 5723 | |
7ff89ca2 | 5724 | intel_crtc->active = true; |
92891e45 | 5725 | |
7ff89ca2 | 5726 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5f199dfa | 5727 | |
7ff89ca2 | 5728 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
5f199dfa | 5729 | |
7ff89ca2 VS |
5730 | if (IS_CHERRYVIEW(dev_priv)) { |
5731 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
5732 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
5733 | } else { | |
5734 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
5735 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
5f199dfa VS |
5736 | } |
5737 | ||
7ff89ca2 | 5738 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
5f199dfa | 5739 | |
7ff89ca2 | 5740 | i9xx_pfit_enable(intel_crtc); |
89b3c3c7 | 5741 | |
7ff89ca2 | 5742 | intel_color_load_luts(&pipe_config->base); |
89b3c3c7 | 5743 | |
ff32c54e VS |
5744 | dev_priv->display.initial_watermarks(old_intel_state, |
5745 | pipe_config); | |
7ff89ca2 VS |
5746 | intel_enable_pipe(intel_crtc); |
5747 | ||
5748 | assert_vblank_disabled(crtc); | |
5749 | drm_crtc_vblank_on(crtc); | |
89b3c3c7 | 5750 | |
7ff89ca2 | 5751 | intel_encoders_enable(crtc, pipe_config, old_state); |
89b3c3c7 ACO |
5752 | } |
5753 | ||
7ff89ca2 | 5754 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
2b73001e | 5755 | { |
7ff89ca2 VS |
5756 | struct drm_device *dev = crtc->base.dev; |
5757 | struct drm_i915_private *dev_priv = to_i915(dev); | |
83d7c81f | 5758 | |
7ff89ca2 VS |
5759 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5760 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
2b73001e VS |
5761 | } |
5762 | ||
7ff89ca2 VS |
5763 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
5764 | struct drm_atomic_state *old_state) | |
2b73001e | 5765 | { |
04548cba VS |
5766 | struct intel_atomic_state *old_intel_state = |
5767 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5768 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5769 | struct drm_device *dev = crtc->dev; | |
5770 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5771 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5772 | enum pipe pipe = intel_crtc->pipe; | |
2b73001e | 5773 | |
7ff89ca2 VS |
5774 | if (WARN_ON(intel_crtc->active)) |
5775 | return; | |
2b73001e | 5776 | |
7ff89ca2 | 5777 | i9xx_set_pll_dividers(intel_crtc); |
2b73001e | 5778 | |
7ff89ca2 VS |
5779 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5780 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
83d7c81f | 5781 | |
7ff89ca2 VS |
5782 | intel_set_pipe_timings(intel_crtc); |
5783 | intel_set_pipe_src_size(intel_crtc); | |
2b73001e | 5784 | |
7ff89ca2 | 5785 | i9xx_set_pipeconf(intel_crtc); |
f8437dd1 | 5786 | |
7ff89ca2 | 5787 | intel_crtc->active = true; |
5f199dfa | 5788 | |
7ff89ca2 VS |
5789 | if (!IS_GEN2(dev_priv)) |
5790 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5f199dfa | 5791 | |
7ff89ca2 | 5792 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f8437dd1 | 5793 | |
939994da | 5794 | i9xx_enable_pll(intel_crtc, pipe_config); |
f8437dd1 | 5795 | |
7ff89ca2 | 5796 | i9xx_pfit_enable(intel_crtc); |
f8437dd1 | 5797 | |
7ff89ca2 | 5798 | intel_color_load_luts(&pipe_config->base); |
f8437dd1 | 5799 | |
04548cba VS |
5800 | if (dev_priv->display.initial_watermarks != NULL) |
5801 | dev_priv->display.initial_watermarks(old_intel_state, | |
5802 | intel_crtc->config); | |
5803 | else | |
5804 | intel_update_watermarks(intel_crtc); | |
7ff89ca2 | 5805 | intel_enable_pipe(intel_crtc); |
f8437dd1 | 5806 | |
7ff89ca2 VS |
5807 | assert_vblank_disabled(crtc); |
5808 | drm_crtc_vblank_on(crtc); | |
f8437dd1 | 5809 | |
7ff89ca2 VS |
5810 | intel_encoders_enable(crtc, pipe_config, old_state); |
5811 | } | |
f8437dd1 | 5812 | |
7ff89ca2 VS |
5813 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5814 | { | |
5815 | struct drm_device *dev = crtc->base.dev; | |
5816 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f8437dd1 | 5817 | |
7ff89ca2 | 5818 | if (!crtc->config->gmch_pfit.control) |
f8437dd1 | 5819 | return; |
f8437dd1 | 5820 | |
7ff89ca2 VS |
5821 | assert_pipe_disabled(dev_priv, crtc->pipe); |
5822 | ||
5823 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", | |
5824 | I915_READ(PFIT_CONTROL)); | |
5825 | I915_WRITE(PFIT_CONTROL, 0); | |
f8437dd1 VK |
5826 | } |
5827 | ||
7ff89ca2 VS |
5828 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5829 | struct drm_atomic_state *old_state) | |
f8437dd1 | 5830 | { |
7ff89ca2 VS |
5831 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
5832 | struct drm_device *dev = crtc->dev; | |
5833 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5834 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5835 | int pipe = intel_crtc->pipe; | |
d66a2194 | 5836 | |
d66a2194 | 5837 | /* |
7ff89ca2 VS |
5838 | * On gen2 planes are double buffered but the pipe isn't, so we must |
5839 | * wait for planes to fully turn off before disabling the pipe. | |
d66a2194 | 5840 | */ |
7ff89ca2 VS |
5841 | if (IS_GEN2(dev_priv)) |
5842 | intel_wait_for_vblank(dev_priv, pipe); | |
d66a2194 | 5843 | |
7ff89ca2 | 5844 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5845 | |
7ff89ca2 VS |
5846 | drm_crtc_vblank_off(crtc); |
5847 | assert_vblank_disabled(crtc); | |
d66a2194 | 5848 | |
7ff89ca2 | 5849 | intel_disable_pipe(intel_crtc); |
d66a2194 | 5850 | |
7ff89ca2 | 5851 | i9xx_pfit_disable(intel_crtc); |
89b3c3c7 | 5852 | |
7ff89ca2 | 5853 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5854 | |
7ff89ca2 VS |
5855 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
5856 | if (IS_CHERRYVIEW(dev_priv)) | |
5857 | chv_disable_pll(dev_priv, pipe); | |
5858 | else if (IS_VALLEYVIEW(dev_priv)) | |
5859 | vlv_disable_pll(dev_priv, pipe); | |
5860 | else | |
5861 | i9xx_disable_pll(intel_crtc); | |
5862 | } | |
c2e001ef | 5863 | |
7ff89ca2 | 5864 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
89b3c3c7 | 5865 | |
7ff89ca2 VS |
5866 | if (!IS_GEN2(dev_priv)) |
5867 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
ff32c54e VS |
5868 | |
5869 | if (!dev_priv->display.initial_watermarks) | |
5870 | intel_update_watermarks(intel_crtc); | |
2ee0da16 VS |
5871 | |
5872 | /* clock the pipe down to 640x480@60 to potentially save power */ | |
5873 | if (IS_I830(dev_priv)) | |
5874 | i830_enable_pipe(dev_priv, pipe); | |
f8437dd1 VK |
5875 | } |
5876 | ||
da1d0e26 VS |
5877 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc, |
5878 | struct drm_modeset_acquire_ctx *ctx) | |
f8437dd1 | 5879 | { |
7ff89ca2 VS |
5880 | struct intel_encoder *encoder; |
5881 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5882 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
5883 | enum intel_display_power_domain domain; | |
d2d15016 | 5884 | u64 domains; |
7ff89ca2 VS |
5885 | struct drm_atomic_state *state; |
5886 | struct intel_crtc_state *crtc_state; | |
5887 | int ret; | |
f8437dd1 | 5888 | |
7ff89ca2 VS |
5889 | if (!intel_crtc->active) |
5890 | return; | |
a8ca4934 | 5891 | |
7ff89ca2 | 5892 | if (crtc->primary->state->visible) { |
7ff89ca2 | 5893 | intel_pre_disable_primary_noatomic(crtc); |
709e05c3 | 5894 | |
7ff89ca2 VS |
5895 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); |
5896 | crtc->primary->state->visible = false; | |
5897 | } | |
5d96d8af | 5898 | |
7ff89ca2 VS |
5899 | state = drm_atomic_state_alloc(crtc->dev); |
5900 | if (!state) { | |
5901 | DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory", | |
5902 | crtc->base.id, crtc->name); | |
1c3f7700 | 5903 | return; |
7ff89ca2 | 5904 | } |
9f7eb31a | 5905 | |
da1d0e26 | 5906 | state->acquire_ctx = ctx; |
ea61791e | 5907 | |
7ff89ca2 VS |
5908 | /* Everything's already locked, -EDEADLK can't happen. */ |
5909 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
5910 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
9f7eb31a | 5911 | |
7ff89ca2 | 5912 | WARN_ON(IS_ERR(crtc_state) || ret); |
5d96d8af | 5913 | |
7ff89ca2 | 5914 | dev_priv->display.crtc_disable(crtc_state, state); |
4a806558 | 5915 | |
0853695c | 5916 | drm_atomic_state_put(state); |
842e0307 | 5917 | |
78108b7c VS |
5918 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
5919 | crtc->base.id, crtc->name); | |
842e0307 ML |
5920 | |
5921 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
5922 | crtc->state->active = false; | |
37d9078b | 5923 | intel_crtc->active = false; |
842e0307 ML |
5924 | crtc->enabled = false; |
5925 | crtc->state->connector_mask = 0; | |
5926 | crtc->state->encoder_mask = 0; | |
5927 | ||
5928 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
5929 | encoder->base.crtc = NULL; | |
5930 | ||
58f9c0bc | 5931 | intel_fbc_disable(intel_crtc); |
432081bc | 5932 | intel_update_watermarks(intel_crtc); |
1f7457b1 | 5933 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
5934 | |
5935 | domains = intel_crtc->enabled_power_domains; | |
5936 | for_each_power_domain(domain, domains) | |
5937 | intel_display_power_put(dev_priv, domain); | |
5938 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
5939 | |
5940 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
d305e061 | 5941 | dev_priv->min_cdclk[intel_crtc->pipe] = 0; |
b17d48e2 ML |
5942 | } |
5943 | ||
6b72d486 ML |
5944 | /* |
5945 | * turn all crtc's off, but do not adjust state | |
5946 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
5947 | */ | |
70e0bd74 | 5948 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 5949 | { |
e2c8b870 | 5950 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 5951 | struct drm_atomic_state *state; |
e2c8b870 | 5952 | int ret; |
70e0bd74 | 5953 | |
e2c8b870 ML |
5954 | state = drm_atomic_helper_suspend(dev); |
5955 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
5956 | if (ret) |
5957 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
5958 | else |
5959 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 5960 | return ret; |
ee7b9f93 JB |
5961 | } |
5962 | ||
ea5b213a | 5963 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5964 | { |
4ef69c7a | 5965 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5966 | |
ea5b213a CW |
5967 | drm_encoder_cleanup(encoder); |
5968 | kfree(intel_encoder); | |
7e7d76c3 JB |
5969 | } |
5970 | ||
0a91ca29 DV |
5971 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5972 | * internal consistency). */ | |
749d98b8 ML |
5973 | static void intel_connector_verify_state(struct drm_crtc_state *crtc_state, |
5974 | struct drm_connector_state *conn_state) | |
79e53945 | 5975 | { |
749d98b8 | 5976 | struct intel_connector *connector = to_intel_connector(conn_state->connector); |
35dd3c64 ML |
5977 | |
5978 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5979 | connector->base.base.id, | |
5980 | connector->base.name); | |
5981 | ||
0a91ca29 | 5982 | if (connector->get_hw_state(connector)) { |
e85376cb | 5983 | struct intel_encoder *encoder = connector->encoder; |
0a91ca29 | 5984 | |
749d98b8 | 5985 | I915_STATE_WARN(!crtc_state, |
35dd3c64 | 5986 | "connector enabled without attached crtc\n"); |
0a91ca29 | 5987 | |
749d98b8 | 5988 | if (!crtc_state) |
35dd3c64 ML |
5989 | return; |
5990 | ||
749d98b8 | 5991 | I915_STATE_WARN(!crtc_state->active, |
35dd3c64 ML |
5992 | "connector is active, but attached crtc isn't\n"); |
5993 | ||
e85376cb | 5994 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
5995 | return; |
5996 | ||
e85376cb | 5997 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
5998 | "atomic encoder doesn't match attached encoder\n"); |
5999 | ||
e85376cb | 6000 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6001 | "attached encoder crtc differs from connector crtc\n"); |
6002 | } else { | |
749d98b8 | 6003 | I915_STATE_WARN(crtc_state && crtc_state->active, |
4d688a2a | 6004 | "attached crtc is active, but connector isn't\n"); |
749d98b8 | 6005 | I915_STATE_WARN(!crtc_state && conn_state->best_encoder, |
35dd3c64 | 6006 | "best encoder set without crtc!\n"); |
0a91ca29 | 6007 | } |
79e53945 JB |
6008 | } |
6009 | ||
08d9bc92 ACO |
6010 | int intel_connector_init(struct intel_connector *connector) |
6011 | { | |
11c1a9ec | 6012 | struct intel_digital_connector_state *conn_state; |
08d9bc92 | 6013 | |
11c1a9ec ML |
6014 | /* |
6015 | * Allocate enough memory to hold intel_digital_connector_state, | |
6016 | * This might be a few bytes too many, but for connectors that don't | |
6017 | * need it we'll free the state and allocate a smaller one on the first | |
6018 | * succesful commit anyway. | |
6019 | */ | |
6020 | conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL); | |
6021 | if (!conn_state) | |
08d9bc92 ACO |
6022 | return -ENOMEM; |
6023 | ||
11c1a9ec ML |
6024 | __drm_atomic_helper_connector_reset(&connector->base, |
6025 | &conn_state->base); | |
6026 | ||
08d9bc92 ACO |
6027 | return 0; |
6028 | } | |
6029 | ||
6030 | struct intel_connector *intel_connector_alloc(void) | |
6031 | { | |
6032 | struct intel_connector *connector; | |
6033 | ||
6034 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6035 | if (!connector) | |
6036 | return NULL; | |
6037 | ||
6038 | if (intel_connector_init(connector) < 0) { | |
6039 | kfree(connector); | |
6040 | return NULL; | |
6041 | } | |
6042 | ||
6043 | return connector; | |
6044 | } | |
6045 | ||
091a4f91 JA |
6046 | /* |
6047 | * Free the bits allocated by intel_connector_alloc. | |
6048 | * This should only be used after intel_connector_alloc has returned | |
6049 | * successfully, and before drm_connector_init returns successfully. | |
6050 | * Otherwise the destroy callbacks for the connector and the state should | |
6051 | * take care of proper cleanup/free | |
6052 | */ | |
6053 | void intel_connector_free(struct intel_connector *connector) | |
6054 | { | |
6055 | kfree(to_intel_digital_connector_state(connector->base.state)); | |
6056 | kfree(connector); | |
6057 | } | |
6058 | ||
f0947c37 DV |
6059 | /* Simple connector->get_hw_state implementation for encoders that support only |
6060 | * one connector and no cloning and hence the encoder state determines the state | |
6061 | * of the connector. */ | |
6062 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6063 | { |
24929352 | 6064 | enum pipe pipe = 0; |
f0947c37 | 6065 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6066 | |
f0947c37 | 6067 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6068 | } |
6069 | ||
6d293983 | 6070 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6071 | { |
6d293983 ACO |
6072 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6073 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6074 | |
6075 | return 0; | |
6076 | } | |
6077 | ||
6d293983 | 6078 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6079 | struct intel_crtc_state *pipe_config) |
1857e1da | 6080 | { |
8652744b | 6081 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d293983 ACO |
6082 | struct drm_atomic_state *state = pipe_config->base.state; |
6083 | struct intel_crtc *other_crtc; | |
6084 | struct intel_crtc_state *other_crtc_state; | |
6085 | ||
1857e1da DV |
6086 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6087 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6088 | if (pipe_config->fdi_lanes > 4) { | |
6089 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6090 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6091 | return -EINVAL; |
1857e1da DV |
6092 | } |
6093 | ||
8652744b | 6094 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da DV |
6095 | if (pipe_config->fdi_lanes > 2) { |
6096 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6097 | pipe_config->fdi_lanes); | |
6d293983 | 6098 | return -EINVAL; |
1857e1da | 6099 | } else { |
6d293983 | 6100 | return 0; |
1857e1da DV |
6101 | } |
6102 | } | |
6103 | ||
b7f05d4a | 6104 | if (INTEL_INFO(dev_priv)->num_pipes == 2) |
6d293983 | 6105 | return 0; |
1857e1da DV |
6106 | |
6107 | /* Ivybridge 3 pipe is really complicated */ | |
6108 | switch (pipe) { | |
6109 | case PIPE_A: | |
6d293983 | 6110 | return 0; |
1857e1da | 6111 | case PIPE_B: |
6d293983 ACO |
6112 | if (pipe_config->fdi_lanes <= 2) |
6113 | return 0; | |
6114 | ||
b91eb5cc | 6115 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
6116 | other_crtc_state = |
6117 | intel_atomic_get_crtc_state(state, other_crtc); | |
6118 | if (IS_ERR(other_crtc_state)) | |
6119 | return PTR_ERR(other_crtc_state); | |
6120 | ||
6121 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6122 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6123 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6124 | return -EINVAL; |
1857e1da | 6125 | } |
6d293983 | 6126 | return 0; |
1857e1da | 6127 | case PIPE_C: |
251cc67c VS |
6128 | if (pipe_config->fdi_lanes > 2) { |
6129 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6130 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6131 | return -EINVAL; |
251cc67c | 6132 | } |
6d293983 | 6133 | |
b91eb5cc | 6134 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
6135 | other_crtc_state = |
6136 | intel_atomic_get_crtc_state(state, other_crtc); | |
6137 | if (IS_ERR(other_crtc_state)) | |
6138 | return PTR_ERR(other_crtc_state); | |
6139 | ||
6140 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6141 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6142 | return -EINVAL; |
1857e1da | 6143 | } |
6d293983 | 6144 | return 0; |
1857e1da DV |
6145 | default: |
6146 | BUG(); | |
6147 | } | |
6148 | } | |
6149 | ||
e29c22c0 DV |
6150 | #define RETRY 1 |
6151 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6152 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6153 | { |
1857e1da | 6154 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6155 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6156 | int lane, link_bw, fdi_dotclock, ret; |
6157 | bool needs_recompute = false; | |
877d48d5 | 6158 | |
e29c22c0 | 6159 | retry: |
877d48d5 DV |
6160 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6161 | * each output octet as 10 bits. The actual frequency | |
6162 | * is stored as a divider into a 100MHz clock, and the | |
6163 | * mode pixel clock is stored in units of 1KHz. | |
6164 | * Hence the bw of each lane in terms of the mode signal | |
6165 | * is: | |
6166 | */ | |
21a727b3 | 6167 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6168 | |
241bfc38 | 6169 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6170 | |
2bd89a07 | 6171 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6172 | pipe_config->pipe_bpp); |
6173 | ||
6174 | pipe_config->fdi_lanes = lane; | |
6175 | ||
2bd89a07 | 6176 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
b31e85ed | 6177 | link_bw, &pipe_config->fdi_m_n, false); |
1857e1da | 6178 | |
e3b247da | 6179 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6180 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 | 6181 | pipe_config->pipe_bpp -= 2*3; |
7ff89ca2 VS |
6182 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
6183 | pipe_config->pipe_bpp); | |
6184 | needs_recompute = true; | |
6185 | pipe_config->bw_constrained = true; | |
257a7ffc | 6186 | |
7ff89ca2 | 6187 | goto retry; |
257a7ffc | 6188 | } |
79e53945 | 6189 | |
7ff89ca2 VS |
6190 | if (needs_recompute) |
6191 | return RETRY; | |
e70236a8 | 6192 | |
7ff89ca2 | 6193 | return ret; |
e70236a8 JB |
6194 | } |
6195 | ||
7ff89ca2 VS |
6196 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6197 | struct intel_crtc_state *pipe_config) | |
e70236a8 | 6198 | { |
6e644626 VS |
6199 | if (pipe_config->ips_force_disable) |
6200 | return false; | |
6201 | ||
7ff89ca2 VS |
6202 | if (pipe_config->pipe_bpp > 24) |
6203 | return false; | |
e70236a8 | 6204 | |
7ff89ca2 VS |
6205 | /* HSW can handle pixel rate up to cdclk? */ |
6206 | if (IS_HASWELL(dev_priv)) | |
6207 | return true; | |
1b1d2716 | 6208 | |
65cd2b3f | 6209 | /* |
7ff89ca2 VS |
6210 | * We compare against max which means we must take |
6211 | * the increased cdclk requirement into account when | |
6212 | * calculating the new cdclk. | |
6213 | * | |
6214 | * Should measure whether using a lower cdclk w/o IPS | |
e70236a8 | 6215 | */ |
7ff89ca2 VS |
6216 | return pipe_config->pixel_rate <= |
6217 | dev_priv->max_cdclk_freq * 95 / 100; | |
e70236a8 | 6218 | } |
79e53945 | 6219 | |
7ff89ca2 VS |
6220 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
6221 | struct intel_crtc_state *pipe_config) | |
6222 | { | |
6223 | struct drm_device *dev = crtc->base.dev; | |
6224 | struct drm_i915_private *dev_priv = to_i915(dev); | |
34edce2f | 6225 | |
4f044a88 | 6226 | pipe_config->ips_enabled = i915_modparams.enable_ips && |
7ff89ca2 VS |
6227 | hsw_crtc_supports_ips(crtc) && |
6228 | pipe_config_supports_ips(dev_priv, pipe_config); | |
34edce2f VS |
6229 | } |
6230 | ||
7ff89ca2 | 6231 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
34edce2f | 6232 | { |
7ff89ca2 | 6233 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
34edce2f | 6234 | |
7ff89ca2 VS |
6235 | /* GDG double wide on either pipe, otherwise pipe A only */ |
6236 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6237 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
34edce2f VS |
6238 | } |
6239 | ||
ceb99320 VS |
6240 | static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
6241 | { | |
6242 | uint32_t pixel_rate; | |
6243 | ||
6244 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; | |
6245 | ||
6246 | /* | |
6247 | * We only use IF-ID interlacing. If we ever use | |
6248 | * PF-ID we'll need to adjust the pixel_rate here. | |
6249 | */ | |
6250 | ||
6251 | if (pipe_config->pch_pfit.enabled) { | |
6252 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; | |
6253 | uint32_t pfit_size = pipe_config->pch_pfit.size; | |
6254 | ||
6255 | pipe_w = pipe_config->pipe_src_w; | |
6256 | pipe_h = pipe_config->pipe_src_h; | |
6257 | ||
6258 | pfit_w = (pfit_size >> 16) & 0xFFFF; | |
6259 | pfit_h = pfit_size & 0xFFFF; | |
6260 | if (pipe_w < pfit_w) | |
6261 | pipe_w = pfit_w; | |
6262 | if (pipe_h < pfit_h) | |
6263 | pipe_h = pfit_h; | |
6264 | ||
6265 | if (WARN_ON(!pfit_w || !pfit_h)) | |
6266 | return pixel_rate; | |
6267 | ||
6268 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
6269 | pfit_w * pfit_h); | |
6270 | } | |
6271 | ||
6272 | return pixel_rate; | |
6273 | } | |
6274 | ||
7ff89ca2 | 6275 | static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) |
34edce2f | 6276 | { |
7ff89ca2 | 6277 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
34edce2f | 6278 | |
7ff89ca2 VS |
6279 | if (HAS_GMCH_DISPLAY(dev_priv)) |
6280 | /* FIXME calculate proper pipe pixel rate for GMCH pfit */ | |
6281 | crtc_state->pixel_rate = | |
6282 | crtc_state->base.adjusted_mode.crtc_clock; | |
6283 | else | |
6284 | crtc_state->pixel_rate = | |
6285 | ilk_pipe_pixel_rate(crtc_state); | |
6286 | } | |
34edce2f | 6287 | |
7ff89ca2 VS |
6288 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
6289 | struct intel_crtc_state *pipe_config) | |
6290 | { | |
6291 | struct drm_device *dev = crtc->base.dev; | |
6292 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6293 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
6294 | int clock_limit = dev_priv->max_dotclk_freq; | |
34edce2f | 6295 | |
7ff89ca2 VS |
6296 | if (INTEL_GEN(dev_priv) < 4) { |
6297 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; | |
34edce2f | 6298 | |
7ff89ca2 VS |
6299 | /* |
6300 | * Enable double wide mode when the dot clock | |
6301 | * is > 90% of the (display) core speed. | |
6302 | */ | |
6303 | if (intel_crtc_supports_double_wide(crtc) && | |
6304 | adjusted_mode->crtc_clock > clock_limit) { | |
6305 | clock_limit = dev_priv->max_dotclk_freq; | |
6306 | pipe_config->double_wide = true; | |
6307 | } | |
34edce2f VS |
6308 | } |
6309 | ||
7ff89ca2 VS |
6310 | if (adjusted_mode->crtc_clock > clock_limit) { |
6311 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6312 | adjusted_mode->crtc_clock, clock_limit, | |
6313 | yesno(pipe_config->double_wide)); | |
6314 | return -EINVAL; | |
6315 | } | |
34edce2f | 6316 | |
25edf915 SS |
6317 | if (pipe_config->ycbcr420 && pipe_config->base.ctm) { |
6318 | /* | |
6319 | * There is only one pipe CSC unit per pipe, and we need that | |
6320 | * for output conversion from RGB->YCBCR. So if CTM is already | |
6321 | * applied we can't support YCBCR420 output. | |
6322 | */ | |
6323 | DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n"); | |
6324 | return -EINVAL; | |
6325 | } | |
6326 | ||
7ff89ca2 VS |
6327 | /* |
6328 | * Pipe horizontal size must be even in: | |
6329 | * - DVO ganged mode | |
6330 | * - LVDS dual channel mode | |
6331 | * - Double wide pipe | |
6332 | */ | |
6333 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && | |
6334 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
6335 | pipe_config->pipe_src_w &= ~1; | |
34edce2f | 6336 | |
7ff89ca2 VS |
6337 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6338 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
6339 | */ | |
6340 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && | |
6341 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) | |
6342 | return -EINVAL; | |
34edce2f | 6343 | |
7ff89ca2 | 6344 | intel_crtc_compute_pixel_rate(pipe_config); |
34edce2f | 6345 | |
7ff89ca2 VS |
6346 | if (HAS_IPS(dev_priv)) |
6347 | hsw_compute_ips_config(crtc, pipe_config); | |
34edce2f | 6348 | |
7ff89ca2 VS |
6349 | if (pipe_config->has_pch_encoder) |
6350 | return ironlake_fdi_compute_config(crtc, pipe_config); | |
34edce2f | 6351 | |
7ff89ca2 | 6352 | return 0; |
34edce2f VS |
6353 | } |
6354 | ||
2c07245f | 6355 | static void |
a65851af | 6356 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6357 | { |
a65851af VS |
6358 | while (*num > DATA_LINK_M_N_MASK || |
6359 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6360 | *num >>= 1; |
6361 | *den >>= 1; | |
6362 | } | |
6363 | } | |
6364 | ||
a65851af | 6365 | static void compute_m_n(unsigned int m, unsigned int n, |
b31e85ed JN |
6366 | uint32_t *ret_m, uint32_t *ret_n, |
6367 | bool reduce_m_n) | |
a65851af | 6368 | { |
9a86cda0 JN |
6369 | /* |
6370 | * Reduce M/N as much as possible without loss in precision. Several DP | |
6371 | * dongles in particular seem to be fussy about too large *link* M/N | |
6372 | * values. The passed in values are more likely to have the least | |
6373 | * significant bits zero than M after rounding below, so do this first. | |
6374 | */ | |
b31e85ed JN |
6375 | if (reduce_m_n) { |
6376 | while ((m & 1) == 0 && (n & 1) == 0) { | |
6377 | m >>= 1; | |
6378 | n >>= 1; | |
6379 | } | |
9a86cda0 JN |
6380 | } |
6381 | ||
a65851af VS |
6382 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
6383 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6384 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6385 | } | |
6386 | ||
e69d0bc1 DV |
6387 | void |
6388 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6389 | int pixel_clock, int link_clock, | |
b31e85ed JN |
6390 | struct intel_link_m_n *m_n, |
6391 | bool reduce_m_n) | |
2c07245f | 6392 | { |
e69d0bc1 | 6393 | m_n->tu = 64; |
a65851af VS |
6394 | |
6395 | compute_m_n(bits_per_pixel * pixel_clock, | |
6396 | link_clock * nlanes * 8, | |
b31e85ed JN |
6397 | &m_n->gmch_m, &m_n->gmch_n, |
6398 | reduce_m_n); | |
a65851af VS |
6399 | |
6400 | compute_m_n(pixel_clock, link_clock, | |
b31e85ed JN |
6401 | &m_n->link_m, &m_n->link_n, |
6402 | reduce_m_n); | |
2c07245f ZW |
6403 | } |
6404 | ||
a7615030 CW |
6405 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6406 | { | |
4f044a88 MW |
6407 | if (i915_modparams.panel_use_ssc >= 0) |
6408 | return i915_modparams.panel_use_ssc != 0; | |
41aa3448 | 6409 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6410 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6411 | } |
6412 | ||
7429e9d4 | 6413 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6414 | { |
7df00d7a | 6415 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6416 | } |
f47709a9 | 6417 | |
7429e9d4 DV |
6418 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6419 | { | |
6420 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6421 | } |
6422 | ||
f47709a9 | 6423 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6424 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 6425 | struct dpll *reduced_clock) |
a7516a05 | 6426 | { |
9b1e14f4 | 6427 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
6428 | u32 fp, fp2 = 0; |
6429 | ||
9b1e14f4 | 6430 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 6431 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6432 | if (reduced_clock) |
7429e9d4 | 6433 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6434 | } else { |
190f68c5 | 6435 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6436 | if (reduced_clock) |
7429e9d4 | 6437 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6438 | } |
6439 | ||
190f68c5 | 6440 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6441 | |
2d84d2b3 | 6442 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6443 | reduced_clock) { |
190f68c5 | 6444 | crtc_state->dpll_hw_state.fp1 = fp2; |
a7516a05 | 6445 | } else { |
190f68c5 | 6446 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6447 | } |
6448 | } | |
6449 | ||
5e69f97f CML |
6450 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6451 | pipe) | |
89b667f8 JB |
6452 | { |
6453 | u32 reg_val; | |
6454 | ||
6455 | /* | |
6456 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6457 | * and set it to a reasonable value instead. | |
6458 | */ | |
ab3c759a | 6459 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6460 | reg_val &= 0xffffff00; |
6461 | reg_val |= 0x00000030; | |
ab3c759a | 6462 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6463 | |
ab3c759a | 6464 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
ed58570f ID |
6465 | reg_val &= 0x00ffffff; |
6466 | reg_val |= 0x8c000000; | |
ab3c759a | 6467 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6468 | |
ab3c759a | 6469 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6470 | reg_val &= 0xffffff00; |
ab3c759a | 6471 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6472 | |
ab3c759a | 6473 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6474 | reg_val &= 0x00ffffff; |
6475 | reg_val |= 0xb0000000; | |
ab3c759a | 6476 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6477 | } |
6478 | ||
b551842d DV |
6479 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6480 | struct intel_link_m_n *m_n) | |
6481 | { | |
6482 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6483 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
6484 | int pipe = crtc->pipe; |
6485 | ||
e3b95f1e DV |
6486 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6487 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6488 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6489 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6490 | } |
6491 | ||
6492 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6493 | struct intel_link_m_n *m_n, |
6494 | struct intel_link_m_n *m2_n2) | |
b551842d | 6495 | { |
6315b5d3 | 6496 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b551842d | 6497 | int pipe = crtc->pipe; |
6e3c9717 | 6498 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d | 6499 | |
6315b5d3 | 6500 | if (INTEL_GEN(dev_priv) >= 5) { |
b551842d DV |
6501 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6502 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6503 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6504 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6505 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6506 | * for gen < 8) and if DRRS is supported (to make sure the | |
6507 | * registers are not unnecessarily accessed). | |
6508 | */ | |
920a14b2 TU |
6509 | if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || |
6510 | INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { | |
f769cd24 VK |
6511 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6512 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6513 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6514 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6515 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6516 | } | |
b551842d | 6517 | } else { |
e3b95f1e DV |
6518 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6519 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6520 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6521 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6522 | } |
6523 | } | |
6524 | ||
fe3cd48d | 6525 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6526 | { |
fe3cd48d R |
6527 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6528 | ||
6529 | if (m_n == M1_N1) { | |
6530 | dp_m_n = &crtc->config->dp_m_n; | |
6531 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6532 | } else if (m_n == M2_N2) { | |
6533 | ||
6534 | /* | |
6535 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6536 | * needs to be programmed into M1_N1. | |
6537 | */ | |
6538 | dp_m_n = &crtc->config->dp_m2_n2; | |
6539 | } else { | |
6540 | DRM_ERROR("Unsupported divider value\n"); | |
6541 | return; | |
6542 | } | |
6543 | ||
6e3c9717 ACO |
6544 | if (crtc->config->has_pch_encoder) |
6545 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6546 | else |
fe3cd48d | 6547 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6548 | } |
6549 | ||
251ac862 DV |
6550 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
6551 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 6552 | { |
03ed5cbf | 6553 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 6554 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6555 | if (crtc->pipe != PIPE_A) |
6556 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 6557 | |
cd2d34d9 | 6558 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6559 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6560 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
6561 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
6562 | ||
03ed5cbf VS |
6563 | pipe_config->dpll_hw_state.dpll_md = |
6564 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6565 | } | |
bdd4b6a6 | 6566 | |
03ed5cbf VS |
6567 | static void chv_compute_dpll(struct intel_crtc *crtc, |
6568 | struct intel_crtc_state *pipe_config) | |
6569 | { | |
6570 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 6571 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6572 | if (crtc->pipe != PIPE_A) |
6573 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6574 | ||
cd2d34d9 | 6575 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6576 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6577 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
6578 | ||
03ed5cbf VS |
6579 | pipe_config->dpll_hw_state.dpll_md = |
6580 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
6581 | } |
6582 | ||
d288f65f | 6583 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6584 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6585 | { |
f47709a9 | 6586 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6587 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6588 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 6589 | u32 mdiv; |
a0c4da24 | 6590 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6591 | u32 coreclk, reg_val; |
a0c4da24 | 6592 | |
cd2d34d9 VS |
6593 | /* Enable Refclk */ |
6594 | I915_WRITE(DPLL(pipe), | |
6595 | pipe_config->dpll_hw_state.dpll & | |
6596 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
6597 | ||
6598 | /* No need to actually set up the DPLL with DSI */ | |
6599 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6600 | return; | |
6601 | ||
a580516d | 6602 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 6603 | |
d288f65f VS |
6604 | bestn = pipe_config->dpll.n; |
6605 | bestm1 = pipe_config->dpll.m1; | |
6606 | bestm2 = pipe_config->dpll.m2; | |
6607 | bestp1 = pipe_config->dpll.p1; | |
6608 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6609 | |
89b667f8 JB |
6610 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6611 | ||
6612 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6613 | if (pipe == PIPE_B) |
5e69f97f | 6614 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6615 | |
6616 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6617 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6618 | |
6619 | /* Disable target IRef on PLL */ | |
ab3c759a | 6620 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6621 | reg_val &= 0x00ffffff; |
ab3c759a | 6622 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6623 | |
6624 | /* Disable fast lock */ | |
ab3c759a | 6625 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6626 | |
6627 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6628 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6629 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6630 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6631 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6632 | |
6633 | /* | |
6634 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6635 | * but we don't support that). | |
6636 | * Note: don't use the DAC post divider as it seems unstable. | |
6637 | */ | |
6638 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6639 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6640 | |
a0c4da24 | 6641 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6642 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6643 | |
89b667f8 | 6644 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6645 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
6646 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
6647 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6648 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6649 | 0x009f0003); |
89b667f8 | 6650 | else |
ab3c759a | 6651 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6652 | 0x00d0000f); |
6653 | ||
37a5650b | 6654 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 6655 | /* Use SSC source */ |
bdd4b6a6 | 6656 | if (pipe == PIPE_A) |
ab3c759a | 6657 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6658 | 0x0df40000); |
6659 | else | |
ab3c759a | 6660 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6661 | 0x0df70000); |
6662 | } else { /* HDMI or VGA */ | |
6663 | /* Use bend source */ | |
bdd4b6a6 | 6664 | if (pipe == PIPE_A) |
ab3c759a | 6665 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6666 | 0x0df70000); |
6667 | else | |
ab3c759a | 6668 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6669 | 0x0df40000); |
6670 | } | |
a0c4da24 | 6671 | |
ab3c759a | 6672 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6673 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 6674 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 6675 | coreclk |= 0x01000000; |
ab3c759a | 6676 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6677 | |
ab3c759a | 6678 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 6679 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
6680 | } |
6681 | ||
d288f65f | 6682 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6683 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6684 | { |
6685 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6686 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6687 | enum pipe pipe = crtc->pipe; |
9d556c99 | 6688 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 6689 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6690 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6691 | u32 dpio_val; |
9cbe40c1 | 6692 | int vco; |
9d556c99 | 6693 | |
cd2d34d9 VS |
6694 | /* Enable Refclk and SSC */ |
6695 | I915_WRITE(DPLL(pipe), | |
6696 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
6697 | ||
6698 | /* No need to actually set up the DPLL with DSI */ | |
6699 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6700 | return; | |
6701 | ||
d288f65f VS |
6702 | bestn = pipe_config->dpll.n; |
6703 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6704 | bestm1 = pipe_config->dpll.m1; | |
6705 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6706 | bestp1 = pipe_config->dpll.p1; | |
6707 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6708 | vco = pipe_config->dpll.vco; |
a945ce7e | 6709 | dpio_val = 0; |
9cbe40c1 | 6710 | loopfilter = 0; |
9d556c99 | 6711 | |
a580516d | 6712 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 6713 | |
9d556c99 CML |
6714 | /* p1 and p2 divider */ |
6715 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6716 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6717 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6718 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6719 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6720 | ||
6721 | /* Feedback post-divider - m2 */ | |
6722 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6723 | ||
6724 | /* Feedback refclk divider - n and m1 */ | |
6725 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6726 | DPIO_CHV_M1_DIV_BY_2 | | |
6727 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6728 | ||
6729 | /* M2 fraction division */ | |
25a25dfc | 6730 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
6731 | |
6732 | /* M2 fraction division enable */ | |
a945ce7e VP |
6733 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6734 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6735 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6736 | if (bestm2_frac) | |
6737 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6738 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6739 | |
de3a0fde VP |
6740 | /* Program digital lock detect threshold */ |
6741 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6742 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6743 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6744 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6745 | if (!bestm2_frac) | |
6746 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6747 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6748 | ||
9d556c99 | 6749 | /* Loop filter */ |
9cbe40c1 VP |
6750 | if (vco == 5400000) { |
6751 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6752 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6753 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6754 | tribuf_calcntr = 0x9; | |
6755 | } else if (vco <= 6200000) { | |
6756 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6757 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6758 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6759 | tribuf_calcntr = 0x9; | |
6760 | } else if (vco <= 6480000) { | |
6761 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6762 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6763 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6764 | tribuf_calcntr = 0x8; | |
6765 | } else { | |
6766 | /* Not supported. Apply the same limits as in the max case */ | |
6767 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6768 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6769 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6770 | tribuf_calcntr = 0; | |
6771 | } | |
9d556c99 CML |
6772 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6773 | ||
968040b2 | 6774 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6775 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6776 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6777 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6778 | ||
9d556c99 CML |
6779 | /* AFC Recal */ |
6780 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6781 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6782 | DPIO_AFC_RECAL); | |
6783 | ||
a580516d | 6784 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
6785 | } |
6786 | ||
d288f65f VS |
6787 | /** |
6788 | * vlv_force_pll_on - forcibly enable just the PLL | |
6789 | * @dev_priv: i915 private structure | |
6790 | * @pipe: pipe PLL to enable | |
6791 | * @dpll: PLL configuration | |
6792 | * | |
6793 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6794 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6795 | * be enabled. | |
6796 | */ | |
30ad9814 | 6797 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 6798 | const struct dpll *dpll) |
d288f65f | 6799 | { |
b91eb5cc | 6800 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
6801 | struct intel_crtc_state *pipe_config; |
6802 | ||
6803 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
6804 | if (!pipe_config) | |
6805 | return -ENOMEM; | |
6806 | ||
6807 | pipe_config->base.crtc = &crtc->base; | |
6808 | pipe_config->pixel_multiplier = 1; | |
6809 | pipe_config->dpll = *dpll; | |
d288f65f | 6810 | |
30ad9814 | 6811 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
6812 | chv_compute_dpll(crtc, pipe_config); |
6813 | chv_prepare_pll(crtc, pipe_config); | |
6814 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 6815 | } else { |
3f36b937 TU |
6816 | vlv_compute_dpll(crtc, pipe_config); |
6817 | vlv_prepare_pll(crtc, pipe_config); | |
6818 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 6819 | } |
3f36b937 TU |
6820 | |
6821 | kfree(pipe_config); | |
6822 | ||
6823 | return 0; | |
d288f65f VS |
6824 | } |
6825 | ||
6826 | /** | |
6827 | * vlv_force_pll_off - forcibly disable just the PLL | |
6828 | * @dev_priv: i915 private structure | |
6829 | * @pipe: pipe PLL to disable | |
6830 | * | |
6831 | * Disable the PLL for @pipe. To be used in cases where we need | |
6832 | * the PLL enabled even when @pipe is not going to be enabled. | |
6833 | */ | |
30ad9814 | 6834 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 6835 | { |
30ad9814 VS |
6836 | if (IS_CHERRYVIEW(dev_priv)) |
6837 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 6838 | else |
30ad9814 | 6839 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
6840 | } |
6841 | ||
251ac862 DV |
6842 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
6843 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6844 | struct dpll *reduced_clock) |
eb1cbe48 | 6845 | { |
9b1e14f4 | 6846 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 6847 | u32 dpll; |
190f68c5 | 6848 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6849 | |
190f68c5 | 6850 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6851 | |
eb1cbe48 DV |
6852 | dpll = DPLL_VGA_MODE_DIS; |
6853 | ||
2d84d2b3 | 6854 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6855 | dpll |= DPLLB_MODE_LVDS; |
6856 | else | |
6857 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6858 | |
73f67aa8 JN |
6859 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
6860 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { | |
190f68c5 | 6861 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6862 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6863 | } |
198a037f | 6864 | |
3d6e9ee0 VS |
6865 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
6866 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 6867 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6868 | |
37a5650b | 6869 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 6870 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6871 | |
6872 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 6873 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
6874 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
6875 | else { | |
6876 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 6877 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
6878 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
6879 | } | |
6880 | switch (clock->p2) { | |
6881 | case 5: | |
6882 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6883 | break; | |
6884 | case 7: | |
6885 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6886 | break; | |
6887 | case 10: | |
6888 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6889 | break; | |
6890 | case 14: | |
6891 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6892 | break; | |
6893 | } | |
9b1e14f4 | 6894 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
6895 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
6896 | ||
190f68c5 | 6897 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6898 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 6899 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6900 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6901 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6902 | else | |
6903 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6904 | ||
6905 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6906 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6907 | |
9b1e14f4 | 6908 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 6909 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 6910 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 6911 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6912 | } |
6913 | } | |
6914 | ||
251ac862 DV |
6915 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
6916 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6917 | struct dpll *reduced_clock) |
eb1cbe48 | 6918 | { |
f47709a9 | 6919 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6920 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 6921 | u32 dpll; |
190f68c5 | 6922 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6923 | |
190f68c5 | 6924 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6925 | |
eb1cbe48 DV |
6926 | dpll = DPLL_VGA_MODE_DIS; |
6927 | ||
2d84d2b3 | 6928 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6929 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6930 | } else { | |
6931 | if (clock->p1 == 2) | |
6932 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6933 | else | |
6934 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6935 | if (clock->p2 == 4) | |
6936 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6937 | } | |
6938 | ||
50a0bc90 TU |
6939 | if (!IS_I830(dev_priv) && |
6940 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) | |
4a33e48d DV |
6941 | dpll |= DPLL_DVO_2X_MODE; |
6942 | ||
2d84d2b3 | 6943 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6944 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6945 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6946 | else | |
6947 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6948 | ||
6949 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6950 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6951 | } |
6952 | ||
8a654f3b | 6953 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c | 6954 | { |
6315b5d3 | 6955 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
b0e77b9c | 6956 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 6957 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 6958 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
6959 | uint32_t crtc_vtotal, crtc_vblank_end; |
6960 | int vsyncshift = 0; | |
4d8a62ea DV |
6961 | |
6962 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6963 | * the hw state checker will get angry at the mismatch. */ | |
6964 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6965 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6966 | |
609aeaca | 6967 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6968 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6969 | crtc_vtotal -= 1; |
6970 | crtc_vblank_end -= 1; | |
609aeaca | 6971 | |
2d84d2b3 | 6972 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6973 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6974 | else | |
6975 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6976 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6977 | if (vsyncshift < 0) |
6978 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6979 | } |
6980 | ||
6315b5d3 | 6981 | if (INTEL_GEN(dev_priv) > 3) |
fe2b8f9d | 6982 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6983 | |
fe2b8f9d | 6984 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6985 | (adjusted_mode->crtc_hdisplay - 1) | |
6986 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6987 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6988 | (adjusted_mode->crtc_hblank_start - 1) | |
6989 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6990 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6991 | (adjusted_mode->crtc_hsync_start - 1) | |
6992 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6993 | ||
fe2b8f9d | 6994 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6995 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6996 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6997 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6998 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6999 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7000 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7001 | (adjusted_mode->crtc_vsync_start - 1) | |
7002 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7003 | ||
b5e508d4 PZ |
7004 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7005 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7006 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7007 | * bits. */ | |
772c2a51 | 7008 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 PZ |
7009 | (pipe == PIPE_B || pipe == PIPE_C)) |
7010 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7011 | ||
bc58be60 JN |
7012 | } |
7013 | ||
7014 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7015 | { | |
7016 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7017 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
7018 | enum pipe pipe = intel_crtc->pipe; |
7019 | ||
b0e77b9c PZ |
7020 | /* pipesrc controls the size that is scaled from, which should |
7021 | * always be the user's requested size. | |
7022 | */ | |
7023 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7024 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7025 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7026 | } |
7027 | ||
1bd1bd80 | 7028 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7029 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7030 | { |
7031 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7032 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
7033 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
7034 | uint32_t tmp; | |
7035 | ||
7036 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7037 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7038 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7039 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7040 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7041 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7042 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7043 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7044 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7045 | |
7046 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7047 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7048 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7049 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7050 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7051 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7052 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7053 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7054 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7055 | |
7056 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7057 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7058 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7059 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7060 | } |
bc58be60 JN |
7061 | } |
7062 | ||
7063 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7064 | struct intel_crtc_state *pipe_config) | |
7065 | { | |
7066 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7067 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 7068 | u32 tmp; |
1bd1bd80 DV |
7069 | |
7070 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7071 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7072 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7073 | ||
2d112de7 ACO |
7074 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7075 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7076 | } |
7077 | ||
f6a83288 | 7078 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7079 | struct intel_crtc_state *pipe_config) |
babea61d | 7080 | { |
2d112de7 ACO |
7081 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7082 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7083 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7084 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7085 | |
2d112de7 ACO |
7086 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7087 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7088 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7089 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7090 | |
2d112de7 | 7091 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7092 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7093 | |
2d112de7 | 7094 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
cd13f5ab ML |
7095 | |
7096 | mode->hsync = drm_mode_hsync(mode); | |
7097 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7098 | drm_mode_set_name(mode); | |
babea61d JB |
7099 | } |
7100 | ||
84b046f3 DV |
7101 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7102 | { | |
6315b5d3 | 7103 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
84b046f3 DV |
7104 | uint32_t pipeconf; |
7105 | ||
9f11a9e4 | 7106 | pipeconf = 0; |
84b046f3 | 7107 | |
e56134bc VS |
7108 | /* we keep both pipes enabled on 830 */ |
7109 | if (IS_I830(dev_priv)) | |
b6b5d049 | 7110 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; |
67c72a12 | 7111 | |
6e3c9717 | 7112 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7113 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7114 | |
ff9ce46e | 7115 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
7116 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7117 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 7118 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7119 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7120 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7121 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7122 | |
6e3c9717 | 7123 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7124 | case 18: |
7125 | pipeconf |= PIPECONF_6BPC; | |
7126 | break; | |
7127 | case 24: | |
7128 | pipeconf |= PIPECONF_8BPC; | |
7129 | break; | |
7130 | case 30: | |
7131 | pipeconf |= PIPECONF_10BPC; | |
7132 | break; | |
7133 | default: | |
7134 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7135 | BUG(); | |
84b046f3 DV |
7136 | } |
7137 | } | |
7138 | ||
6e3c9717 | 7139 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6315b5d3 | 7140 | if (INTEL_GEN(dev_priv) < 4 || |
2d84d2b3 | 7141 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7142 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7143 | else | |
7144 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7145 | } else | |
84b046f3 DV |
7146 | pipeconf |= PIPECONF_PROGRESSIVE; |
7147 | ||
920a14b2 | 7148 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7149 | intel_crtc->config->limited_color_range) |
9f11a9e4 | 7150 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7151 | |
84b046f3 DV |
7152 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7153 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7154 | } | |
7155 | ||
81c97f52 ACO |
7156 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7157 | struct intel_crtc_state *crtc_state) | |
7158 | { | |
7159 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7160 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7161 | const struct intel_limit *limit; |
81c97f52 ACO |
7162 | int refclk = 48000; |
7163 | ||
7164 | memset(&crtc_state->dpll_hw_state, 0, | |
7165 | sizeof(crtc_state->dpll_hw_state)); | |
7166 | ||
2d84d2b3 | 7167 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
7168 | if (intel_panel_use_ssc(dev_priv)) { |
7169 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7170 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7171 | } | |
7172 | ||
7173 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 7174 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
7175 | limit = &intel_limits_i8xx_dvo; |
7176 | } else { | |
7177 | limit = &intel_limits_i8xx_dac; | |
7178 | } | |
7179 | ||
7180 | if (!crtc_state->clock_set && | |
7181 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7182 | refclk, NULL, &crtc_state->dpll)) { | |
7183 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7184 | return -EINVAL; | |
7185 | } | |
7186 | ||
7187 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7188 | ||
7189 | return 0; | |
7190 | } | |
7191 | ||
19ec6693 ACO |
7192 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7193 | struct intel_crtc_state *crtc_state) | |
7194 | { | |
7195 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7196 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7197 | const struct intel_limit *limit; |
19ec6693 ACO |
7198 | int refclk = 96000; |
7199 | ||
7200 | memset(&crtc_state->dpll_hw_state, 0, | |
7201 | sizeof(crtc_state->dpll_hw_state)); | |
7202 | ||
2d84d2b3 | 7203 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
7204 | if (intel_panel_use_ssc(dev_priv)) { |
7205 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7206 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7207 | } | |
7208 | ||
7209 | if (intel_is_dual_link_lvds(dev)) | |
7210 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7211 | else | |
7212 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
7213 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
7214 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 7215 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 7216 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
7217 | limit = &intel_limits_g4x_sdvo; |
7218 | } else { | |
7219 | /* The option is for other outputs */ | |
7220 | limit = &intel_limits_i9xx_sdvo; | |
7221 | } | |
7222 | ||
7223 | if (!crtc_state->clock_set && | |
7224 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7225 | refclk, NULL, &crtc_state->dpll)) { | |
7226 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7227 | return -EINVAL; | |
7228 | } | |
7229 | ||
7230 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7231 | ||
7232 | return 0; | |
7233 | } | |
7234 | ||
70e8aa21 ACO |
7235 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7236 | struct intel_crtc_state *crtc_state) | |
7237 | { | |
7238 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7239 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7240 | const struct intel_limit *limit; |
70e8aa21 ACO |
7241 | int refclk = 96000; |
7242 | ||
7243 | memset(&crtc_state->dpll_hw_state, 0, | |
7244 | sizeof(crtc_state->dpll_hw_state)); | |
7245 | ||
2d84d2b3 | 7246 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7247 | if (intel_panel_use_ssc(dev_priv)) { |
7248 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7249 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7250 | } | |
7251 | ||
7252 | limit = &intel_limits_pineview_lvds; | |
7253 | } else { | |
7254 | limit = &intel_limits_pineview_sdvo; | |
7255 | } | |
7256 | ||
7257 | if (!crtc_state->clock_set && | |
7258 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7259 | refclk, NULL, &crtc_state->dpll)) { | |
7260 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7261 | return -EINVAL; | |
7262 | } | |
7263 | ||
7264 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7265 | ||
7266 | return 0; | |
7267 | } | |
7268 | ||
190f68c5 ACO |
7269 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7270 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7271 | { |
c7653199 | 7272 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7273 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7274 | const struct intel_limit *limit; |
81c97f52 | 7275 | int refclk = 96000; |
79e53945 | 7276 | |
dd3cd74a ACO |
7277 | memset(&crtc_state->dpll_hw_state, 0, |
7278 | sizeof(crtc_state->dpll_hw_state)); | |
7279 | ||
2d84d2b3 | 7280 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7281 | if (intel_panel_use_ssc(dev_priv)) { |
7282 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7283 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7284 | } | |
43565a06 | 7285 | |
70e8aa21 ACO |
7286 | limit = &intel_limits_i9xx_lvds; |
7287 | } else { | |
7288 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 7289 | } |
79e53945 | 7290 | |
70e8aa21 ACO |
7291 | if (!crtc_state->clock_set && |
7292 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7293 | refclk, NULL, &crtc_state->dpll)) { | |
7294 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7295 | return -EINVAL; | |
f47709a9 | 7296 | } |
7026d4ac | 7297 | |
81c97f52 | 7298 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 7299 | |
c8f7a0db | 7300 | return 0; |
f564048e EA |
7301 | } |
7302 | ||
65b3d6a9 ACO |
7303 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
7304 | struct intel_crtc_state *crtc_state) | |
7305 | { | |
7306 | int refclk = 100000; | |
1b6f4958 | 7307 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
7308 | |
7309 | memset(&crtc_state->dpll_hw_state, 0, | |
7310 | sizeof(crtc_state->dpll_hw_state)); | |
7311 | ||
65b3d6a9 ACO |
7312 | if (!crtc_state->clock_set && |
7313 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7314 | refclk, NULL, &crtc_state->dpll)) { | |
7315 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7316 | return -EINVAL; | |
7317 | } | |
7318 | ||
7319 | chv_compute_dpll(crtc, crtc_state); | |
7320 | ||
7321 | return 0; | |
7322 | } | |
7323 | ||
7324 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
7325 | struct intel_crtc_state *crtc_state) | |
7326 | { | |
7327 | int refclk = 100000; | |
1b6f4958 | 7328 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
7329 | |
7330 | memset(&crtc_state->dpll_hw_state, 0, | |
7331 | sizeof(crtc_state->dpll_hw_state)); | |
7332 | ||
65b3d6a9 ACO |
7333 | if (!crtc_state->clock_set && |
7334 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7335 | refclk, NULL, &crtc_state->dpll)) { | |
7336 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7337 | return -EINVAL; | |
7338 | } | |
7339 | ||
7340 | vlv_compute_dpll(crtc, crtc_state); | |
7341 | ||
7342 | return 0; | |
7343 | } | |
7344 | ||
2fa2fe9a | 7345 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7346 | struct intel_crtc_state *pipe_config) |
2fa2fe9a | 7347 | { |
6315b5d3 | 7348 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2fa2fe9a DV |
7349 | uint32_t tmp; |
7350 | ||
50a0bc90 TU |
7351 | if (INTEL_GEN(dev_priv) <= 3 && |
7352 | (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) | |
dc9e7dec VS |
7353 | return; |
7354 | ||
2fa2fe9a | 7355 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7356 | if (!(tmp & PFIT_ENABLE)) |
7357 | return; | |
2fa2fe9a | 7358 | |
06922821 | 7359 | /* Check whether the pfit is attached to our pipe. */ |
6315b5d3 | 7360 | if (INTEL_GEN(dev_priv) < 4) { |
2fa2fe9a DV |
7361 | if (crtc->pipe != PIPE_B) |
7362 | return; | |
2fa2fe9a DV |
7363 | } else { |
7364 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7365 | return; | |
7366 | } | |
7367 | ||
06922821 | 7368 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 7369 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
7370 | } |
7371 | ||
acbec814 | 7372 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7373 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7374 | { |
7375 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7376 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 7377 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 7378 | struct dpll clock; |
acbec814 | 7379 | u32 mdiv; |
662c6ecb | 7380 | int refclk = 100000; |
acbec814 | 7381 | |
b521973b VS |
7382 | /* In case of DSI, DPLL will not be used */ |
7383 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
7384 | return; |
7385 | ||
a580516d | 7386 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7387 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7388 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7389 | |
7390 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7391 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7392 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7393 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7394 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7395 | ||
dccbea3b | 7396 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7397 | } |
7398 | ||
5724dbd1 DL |
7399 | static void |
7400 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7401 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7402 | { |
7403 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7404 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
7405 | u32 val, base, offset; |
7406 | int pipe = crtc->pipe, plane = crtc->plane; | |
7407 | int fourcc, pixel_format; | |
6761dd31 | 7408 | unsigned int aligned_height; |
b113d5ee | 7409 | struct drm_framebuffer *fb; |
1b842c89 | 7410 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7411 | |
42a7b088 DL |
7412 | val = I915_READ(DSPCNTR(plane)); |
7413 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7414 | return; | |
7415 | ||
d9806c9f | 7416 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7417 | if (!intel_fb) { |
1ad292b5 JB |
7418 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7419 | return; | |
7420 | } | |
7421 | ||
1b842c89 DL |
7422 | fb = &intel_fb->base; |
7423 | ||
d2e9f5fc VS |
7424 | fb->dev = dev; |
7425 | ||
6315b5d3 | 7426 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 7427 | if (val & DISPPLANE_TILED) { |
49af449b | 7428 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 7429 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
7430 | } |
7431 | } | |
1ad292b5 JB |
7432 | |
7433 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7434 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 7435 | fb->format = drm_format_info(fourcc); |
1ad292b5 | 7436 | |
6315b5d3 | 7437 | if (INTEL_GEN(dev_priv) >= 4) { |
49af449b | 7438 | if (plane_config->tiling) |
1ad292b5 JB |
7439 | offset = I915_READ(DSPTILEOFF(plane)); |
7440 | else | |
7441 | offset = I915_READ(DSPLINOFF(plane)); | |
7442 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7443 | } else { | |
7444 | base = I915_READ(DSPADDR(plane)); | |
7445 | } | |
7446 | plane_config->base = base; | |
7447 | ||
7448 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7449 | fb->width = ((val >> 16) & 0xfff) + 1; |
7450 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7451 | |
7452 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7453 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7454 | |
d88c4afd | 7455 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
1ad292b5 | 7456 | |
f37b5c2b | 7457 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7458 | |
2844a921 DL |
7459 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7460 | pipe_name(pipe), plane, fb->width, fb->height, | |
272725c7 | 7461 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 7462 | plane_config->size); |
1ad292b5 | 7463 | |
2d14030b | 7464 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7465 | } |
7466 | ||
70b23a98 | 7467 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7468 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7469 | { |
7470 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7471 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
7472 | int pipe = pipe_config->cpu_transcoder; |
7473 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 7474 | struct dpll clock; |
0d7b6b11 | 7475 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
7476 | int refclk = 100000; |
7477 | ||
b521973b VS |
7478 | /* In case of DSI, DPLL will not be used */ |
7479 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7480 | return; | |
7481 | ||
a580516d | 7482 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
7483 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
7484 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7485 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7486 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 7487 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 7488 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
7489 | |
7490 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
7491 | clock.m2 = (pll_dw0 & 0xff) << 22; |
7492 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
7493 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
7494 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
7495 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7496 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7497 | ||
dccbea3b | 7498 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
7499 | } |
7500 | ||
0e8ffe1b | 7501 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7502 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 7503 | { |
6315b5d3 | 7504 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 7505 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 7506 | uint32_t tmp; |
1729050e | 7507 | bool ret; |
0e8ffe1b | 7508 | |
1729050e ID |
7509 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
7510 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
7511 | return false; |
7512 | ||
e143a21c | 7513 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 7514 | pipe_config->shared_dpll = NULL; |
eccb140b | 7515 | |
1729050e ID |
7516 | ret = false; |
7517 | ||
0e8ffe1b DV |
7518 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7519 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 7520 | goto out; |
0e8ffe1b | 7521 | |
9beb5fea TU |
7522 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7523 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
7524 | switch (tmp & PIPECONF_BPC_MASK) { |
7525 | case PIPECONF_6BPC: | |
7526 | pipe_config->pipe_bpp = 18; | |
7527 | break; | |
7528 | case PIPECONF_8BPC: | |
7529 | pipe_config->pipe_bpp = 24; | |
7530 | break; | |
7531 | case PIPECONF_10BPC: | |
7532 | pipe_config->pipe_bpp = 30; | |
7533 | break; | |
7534 | default: | |
7535 | break; | |
7536 | } | |
7537 | } | |
7538 | ||
920a14b2 | 7539 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7540 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
7541 | pipe_config->limited_color_range = true; |
7542 | ||
6315b5d3 | 7543 | if (INTEL_GEN(dev_priv) < 4) |
282740f7 VS |
7544 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
7545 | ||
1bd1bd80 | 7546 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 7547 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 7548 | |
2fa2fe9a DV |
7549 | i9xx_get_pfit_config(crtc, pipe_config); |
7550 | ||
6315b5d3 | 7551 | if (INTEL_GEN(dev_priv) >= 4) { |
c231775c | 7552 | /* No way to read it out on pipes B and C */ |
920a14b2 | 7553 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
7554 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
7555 | else | |
7556 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
7557 | pipe_config->pixel_multiplier = |
7558 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7559 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7560 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 | 7561 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
73f67aa8 | 7562 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { |
6c49f241 DV |
7563 | tmp = I915_READ(DPLL(crtc->pipe)); |
7564 | pipe_config->pixel_multiplier = | |
7565 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7566 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7567 | } else { | |
7568 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7569 | * port and will be fixed up in the encoder->get_config | |
7570 | * function. */ | |
7571 | pipe_config->pixel_multiplier = 1; | |
7572 | } | |
8bcc2795 | 7573 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
920a14b2 | 7574 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1c4e0274 VS |
7575 | /* |
7576 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7577 | * on 830. Filter it out here so that we don't | |
7578 | * report errors due to that. | |
7579 | */ | |
50a0bc90 | 7580 | if (IS_I830(dev_priv)) |
1c4e0274 VS |
7581 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
7582 | ||
8bcc2795 DV |
7583 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7584 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7585 | } else { |
7586 | /* Mask out read-only status bits. */ | |
7587 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7588 | DPLL_PORTC_READY_MASK | | |
7589 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7590 | } |
6c49f241 | 7591 | |
920a14b2 | 7592 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 7593 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 7594 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
7595 | vlv_crtc_clock_get(crtc, pipe_config); |
7596 | else | |
7597 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7598 | |
0f64614d VS |
7599 | /* |
7600 | * Normally the dotclock is filled in by the encoder .get_config() | |
7601 | * but in case the pipe is enabled w/o any ports we need a sane | |
7602 | * default. | |
7603 | */ | |
7604 | pipe_config->base.adjusted_mode.crtc_clock = | |
7605 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
7606 | ||
1729050e ID |
7607 | ret = true; |
7608 | ||
7609 | out: | |
7610 | intel_display_power_put(dev_priv, power_domain); | |
7611 | ||
7612 | return ret; | |
0e8ffe1b DV |
7613 | } |
7614 | ||
c39055b0 | 7615 | static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv) |
13d83a67 | 7616 | { |
13d83a67 | 7617 | struct intel_encoder *encoder; |
1c1a24d2 | 7618 | int i; |
74cfd7ac | 7619 | u32 val, final; |
13d83a67 | 7620 | bool has_lvds = false; |
199e5d79 | 7621 | bool has_cpu_edp = false; |
199e5d79 | 7622 | bool has_panel = false; |
99eb6a01 KP |
7623 | bool has_ck505 = false; |
7624 | bool can_ssc = false; | |
1c1a24d2 | 7625 | bool using_ssc_source = false; |
13d83a67 JB |
7626 | |
7627 | /* We need to take the global config into account */ | |
c39055b0 | 7628 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
199e5d79 KP |
7629 | switch (encoder->type) { |
7630 | case INTEL_OUTPUT_LVDS: | |
7631 | has_panel = true; | |
7632 | has_lvds = true; | |
7633 | break; | |
7634 | case INTEL_OUTPUT_EDP: | |
7635 | has_panel = true; | |
2de6905f | 7636 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7637 | has_cpu_edp = true; |
7638 | break; | |
6847d71b PZ |
7639 | default: |
7640 | break; | |
13d83a67 JB |
7641 | } |
7642 | } | |
7643 | ||
6e266956 | 7644 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 7645 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7646 | can_ssc = has_ck505; |
7647 | } else { | |
7648 | has_ck505 = false; | |
7649 | can_ssc = true; | |
7650 | } | |
7651 | ||
1c1a24d2 L |
7652 | /* Check if any DPLLs are using the SSC source */ |
7653 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
7654 | u32 temp = I915_READ(PCH_DPLL(i)); | |
7655 | ||
7656 | if (!(temp & DPLL_VCO_ENABLE)) | |
7657 | continue; | |
7658 | ||
7659 | if ((temp & PLL_REF_INPUT_MASK) == | |
7660 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
7661 | using_ssc_source = true; | |
7662 | break; | |
7663 | } | |
7664 | } | |
7665 | ||
7666 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
7667 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
7668 | |
7669 | /* Ironlake: try to setup display ref clock before DPLL | |
7670 | * enabling. This is only under driver's control after | |
7671 | * PCH B stepping, previous chipset stepping should be | |
7672 | * ignoring this setting. | |
7673 | */ | |
74cfd7ac CW |
7674 | val = I915_READ(PCH_DREF_CONTROL); |
7675 | ||
7676 | /* As we must carefully and slowly disable/enable each source in turn, | |
7677 | * compute the final state we want first and check if we need to | |
7678 | * make any changes at all. | |
7679 | */ | |
7680 | final = val; | |
7681 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7682 | if (has_ck505) | |
7683 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7684 | else | |
7685 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7686 | ||
8c07eb68 | 7687 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 7688 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 7689 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
7690 | |
7691 | if (has_panel) { | |
7692 | final |= DREF_SSC_SOURCE_ENABLE; | |
7693 | ||
7694 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7695 | final |= DREF_SSC1_ENABLE; | |
7696 | ||
7697 | if (has_cpu_edp) { | |
7698 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7699 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7700 | else | |
7701 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7702 | } else | |
7703 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
7704 | } else if (using_ssc_source) { |
7705 | final |= DREF_SSC_SOURCE_ENABLE; | |
7706 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
7707 | } |
7708 | ||
7709 | if (final == val) | |
7710 | return; | |
7711 | ||
13d83a67 | 7712 | /* Always enable nonspread source */ |
74cfd7ac | 7713 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7714 | |
99eb6a01 | 7715 | if (has_ck505) |
74cfd7ac | 7716 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7717 | else |
74cfd7ac | 7718 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7719 | |
199e5d79 | 7720 | if (has_panel) { |
74cfd7ac CW |
7721 | val &= ~DREF_SSC_SOURCE_MASK; |
7722 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7723 | |
199e5d79 | 7724 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7725 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7726 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7727 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7728 | } else |
74cfd7ac | 7729 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7730 | |
7731 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7732 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7733 | POSTING_READ(PCH_DREF_CONTROL); |
7734 | udelay(200); | |
7735 | ||
74cfd7ac | 7736 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7737 | |
7738 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7739 | if (has_cpu_edp) { |
99eb6a01 | 7740 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7741 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7742 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7743 | } else |
74cfd7ac | 7744 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7745 | } else |
74cfd7ac | 7746 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7747 | |
74cfd7ac | 7748 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7749 | POSTING_READ(PCH_DREF_CONTROL); |
7750 | udelay(200); | |
7751 | } else { | |
1c1a24d2 | 7752 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 7753 | |
74cfd7ac | 7754 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7755 | |
7756 | /* Turn off CPU output */ | |
74cfd7ac | 7757 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7758 | |
74cfd7ac | 7759 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7760 | POSTING_READ(PCH_DREF_CONTROL); |
7761 | udelay(200); | |
7762 | ||
1c1a24d2 L |
7763 | if (!using_ssc_source) { |
7764 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 7765 | |
1c1a24d2 L |
7766 | /* Turn off the SSC source */ |
7767 | val &= ~DREF_SSC_SOURCE_MASK; | |
7768 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 7769 | |
1c1a24d2 L |
7770 | /* Turn off SSC1 */ |
7771 | val &= ~DREF_SSC1_ENABLE; | |
7772 | ||
7773 | I915_WRITE(PCH_DREF_CONTROL, val); | |
7774 | POSTING_READ(PCH_DREF_CONTROL); | |
7775 | udelay(200); | |
7776 | } | |
13d83a67 | 7777 | } |
74cfd7ac CW |
7778 | |
7779 | BUG_ON(val != final); | |
13d83a67 JB |
7780 | } |
7781 | ||
f31f2d55 | 7782 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7783 | { |
f31f2d55 | 7784 | uint32_t tmp; |
dde86e2d | 7785 | |
0ff066a9 PZ |
7786 | tmp = I915_READ(SOUTH_CHICKEN2); |
7787 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7788 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7789 | |
cf3598c2 ID |
7790 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
7791 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 7792 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 7793 | |
0ff066a9 PZ |
7794 | tmp = I915_READ(SOUTH_CHICKEN2); |
7795 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7796 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7797 | |
cf3598c2 ID |
7798 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
7799 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 7800 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
7801 | } |
7802 | ||
7803 | /* WaMPhyProgramming:hsw */ | |
7804 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7805 | { | |
7806 | uint32_t tmp; | |
dde86e2d PZ |
7807 | |
7808 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7809 | tmp &= ~(0xFF << 24); | |
7810 | tmp |= (0x12 << 24); | |
7811 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7812 | ||
dde86e2d PZ |
7813 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7814 | tmp |= (1 << 11); | |
7815 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7816 | ||
7817 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7818 | tmp |= (1 << 11); | |
7819 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7820 | ||
dde86e2d PZ |
7821 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7822 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7823 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7824 | ||
7825 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7826 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7827 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7828 | ||
0ff066a9 PZ |
7829 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7830 | tmp &= ~(7 << 13); | |
7831 | tmp |= (5 << 13); | |
7832 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7833 | |
0ff066a9 PZ |
7834 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7835 | tmp &= ~(7 << 13); | |
7836 | tmp |= (5 << 13); | |
7837 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7838 | |
7839 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7840 | tmp &= ~0xFF; | |
7841 | tmp |= 0x1C; | |
7842 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7843 | ||
7844 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7845 | tmp &= ~0xFF; | |
7846 | tmp |= 0x1C; | |
7847 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7848 | ||
7849 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7850 | tmp &= ~(0xFF << 16); | |
7851 | tmp |= (0x1C << 16); | |
7852 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7853 | ||
7854 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7855 | tmp &= ~(0xFF << 16); | |
7856 | tmp |= (0x1C << 16); | |
7857 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7858 | ||
0ff066a9 PZ |
7859 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7860 | tmp |= (1 << 27); | |
7861 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7862 | |
0ff066a9 PZ |
7863 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7864 | tmp |= (1 << 27); | |
7865 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7866 | |
0ff066a9 PZ |
7867 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7868 | tmp &= ~(0xF << 28); | |
7869 | tmp |= (4 << 28); | |
7870 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7871 | |
0ff066a9 PZ |
7872 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7873 | tmp &= ~(0xF << 28); | |
7874 | tmp |= (4 << 28); | |
7875 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7876 | } |
7877 | ||
2fa86a1f PZ |
7878 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7879 | * Programming" based on the parameters passed: | |
7880 | * - Sequence to enable CLKOUT_DP | |
7881 | * - Sequence to enable CLKOUT_DP without spread | |
7882 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7883 | */ | |
c39055b0 ACO |
7884 | static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, |
7885 | bool with_spread, bool with_fdi) | |
f31f2d55 | 7886 | { |
2fa86a1f PZ |
7887 | uint32_t reg, tmp; |
7888 | ||
7889 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7890 | with_spread = true; | |
4f8036a2 TU |
7891 | if (WARN(HAS_PCH_LPT_LP(dev_priv) && |
7892 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 7893 | with_fdi = false; |
f31f2d55 | 7894 | |
a580516d | 7895 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
7896 | |
7897 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7898 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7899 | tmp |= SBI_SSCCTL_PATHALT; | |
7900 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7901 | ||
7902 | udelay(24); | |
7903 | ||
2fa86a1f PZ |
7904 | if (with_spread) { |
7905 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7906 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7907 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7908 | |
2fa86a1f PZ |
7909 | if (with_fdi) { |
7910 | lpt_reset_fdi_mphy(dev_priv); | |
7911 | lpt_program_fdi_mphy(dev_priv); | |
7912 | } | |
7913 | } | |
dde86e2d | 7914 | |
4f8036a2 | 7915 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
7916 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7917 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7918 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 7919 | |
a580516d | 7920 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
7921 | } |
7922 | ||
47701c3b | 7923 | /* Sequence to disable CLKOUT_DP */ |
c39055b0 | 7924 | static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) |
47701c3b | 7925 | { |
47701c3b PZ |
7926 | uint32_t reg, tmp; |
7927 | ||
a580516d | 7928 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 7929 | |
4f8036a2 | 7930 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
7931 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7932 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7933 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7934 | ||
7935 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7936 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7937 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7938 | tmp |= SBI_SSCCTL_PATHALT; | |
7939 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7940 | udelay(32); | |
7941 | } | |
7942 | tmp |= SBI_SSCCTL_DISABLE; | |
7943 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7944 | } | |
7945 | ||
a580516d | 7946 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
7947 | } |
7948 | ||
f7be2c21 VS |
7949 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
7950 | ||
7951 | static const uint16_t sscdivintphase[] = { | |
7952 | [BEND_IDX( 50)] = 0x3B23, | |
7953 | [BEND_IDX( 45)] = 0x3B23, | |
7954 | [BEND_IDX( 40)] = 0x3C23, | |
7955 | [BEND_IDX( 35)] = 0x3C23, | |
7956 | [BEND_IDX( 30)] = 0x3D23, | |
7957 | [BEND_IDX( 25)] = 0x3D23, | |
7958 | [BEND_IDX( 20)] = 0x3E23, | |
7959 | [BEND_IDX( 15)] = 0x3E23, | |
7960 | [BEND_IDX( 10)] = 0x3F23, | |
7961 | [BEND_IDX( 5)] = 0x3F23, | |
7962 | [BEND_IDX( 0)] = 0x0025, | |
7963 | [BEND_IDX( -5)] = 0x0025, | |
7964 | [BEND_IDX(-10)] = 0x0125, | |
7965 | [BEND_IDX(-15)] = 0x0125, | |
7966 | [BEND_IDX(-20)] = 0x0225, | |
7967 | [BEND_IDX(-25)] = 0x0225, | |
7968 | [BEND_IDX(-30)] = 0x0325, | |
7969 | [BEND_IDX(-35)] = 0x0325, | |
7970 | [BEND_IDX(-40)] = 0x0425, | |
7971 | [BEND_IDX(-45)] = 0x0425, | |
7972 | [BEND_IDX(-50)] = 0x0525, | |
7973 | }; | |
7974 | ||
7975 | /* | |
7976 | * Bend CLKOUT_DP | |
7977 | * steps -50 to 50 inclusive, in steps of 5 | |
7978 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
7979 | * change in clock period = -(steps / 10) * 5.787 ps | |
7980 | */ | |
7981 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
7982 | { | |
7983 | uint32_t tmp; | |
7984 | int idx = BEND_IDX(steps); | |
7985 | ||
7986 | if (WARN_ON(steps % 5 != 0)) | |
7987 | return; | |
7988 | ||
7989 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
7990 | return; | |
7991 | ||
7992 | mutex_lock(&dev_priv->sb_lock); | |
7993 | ||
7994 | if (steps % 10 != 0) | |
7995 | tmp = 0xAAAAAAAB; | |
7996 | else | |
7997 | tmp = 0x00000000; | |
7998 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
7999 | ||
8000 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8001 | tmp &= 0xffff0000; | |
8002 | tmp |= sscdivintphase[idx]; | |
8003 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8004 | ||
8005 | mutex_unlock(&dev_priv->sb_lock); | |
8006 | } | |
8007 | ||
8008 | #undef BEND_IDX | |
8009 | ||
c39055b0 | 8010 | static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) |
bf8fa3d3 | 8011 | { |
bf8fa3d3 PZ |
8012 | struct intel_encoder *encoder; |
8013 | bool has_vga = false; | |
8014 | ||
c39055b0 | 8015 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
bf8fa3d3 PZ |
8016 | switch (encoder->type) { |
8017 | case INTEL_OUTPUT_ANALOG: | |
8018 | has_vga = true; | |
8019 | break; | |
6847d71b PZ |
8020 | default: |
8021 | break; | |
bf8fa3d3 PZ |
8022 | } |
8023 | } | |
8024 | ||
f7be2c21 | 8025 | if (has_vga) { |
c39055b0 ACO |
8026 | lpt_bend_clkout_dp(dev_priv, 0); |
8027 | lpt_enable_clkout_dp(dev_priv, true, true); | |
f7be2c21 | 8028 | } else { |
c39055b0 | 8029 | lpt_disable_clkout_dp(dev_priv); |
f7be2c21 | 8030 | } |
bf8fa3d3 PZ |
8031 | } |
8032 | ||
dde86e2d PZ |
8033 | /* |
8034 | * Initialize reference clocks when the driver loads | |
8035 | */ | |
c39055b0 | 8036 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv) |
dde86e2d | 8037 | { |
6e266956 | 8038 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
c39055b0 | 8039 | ironlake_init_pch_refclk(dev_priv); |
6e266956 | 8040 | else if (HAS_PCH_LPT(dev_priv)) |
c39055b0 | 8041 | lpt_init_pch_refclk(dev_priv); |
dde86e2d PZ |
8042 | } |
8043 | ||
6ff93609 | 8044 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8045 | { |
fac5e23e | 8046 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
8047 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8048 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8049 | uint32_t val; |
8050 | ||
78114071 | 8051 | val = 0; |
c8203565 | 8052 | |
6e3c9717 | 8053 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8054 | case 18: |
dfd07d72 | 8055 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8056 | break; |
8057 | case 24: | |
dfd07d72 | 8058 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8059 | break; |
8060 | case 30: | |
dfd07d72 | 8061 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8062 | break; |
8063 | case 36: | |
dfd07d72 | 8064 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8065 | break; |
8066 | default: | |
cc769b62 PZ |
8067 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8068 | BUG(); | |
c8203565 PZ |
8069 | } |
8070 | ||
6e3c9717 | 8071 | if (intel_crtc->config->dither) |
c8203565 PZ |
8072 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8073 | ||
6e3c9717 | 8074 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8075 | val |= PIPECONF_INTERLACED_ILK; |
8076 | else | |
8077 | val |= PIPECONF_PROGRESSIVE; | |
8078 | ||
6e3c9717 | 8079 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8080 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8081 | |
c8203565 PZ |
8082 | I915_WRITE(PIPECONF(pipe), val); |
8083 | POSTING_READ(PIPECONF(pipe)); | |
8084 | } | |
8085 | ||
6ff93609 | 8086 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8087 | { |
fac5e23e | 8088 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 8089 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8090 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8091 | u32 val = 0; |
ee2b0b38 | 8092 | |
391bf048 | 8093 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8094 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8095 | ||
6e3c9717 | 8096 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8097 | val |= PIPECONF_INTERLACED_ILK; |
8098 | else | |
8099 | val |= PIPECONF_PROGRESSIVE; | |
8100 | ||
702e7a56 PZ |
8101 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8102 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8103 | } |
8104 | ||
391bf048 JN |
8105 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8106 | { | |
fac5e23e | 8107 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 8108 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b22ca995 | 8109 | struct intel_crtc_state *config = intel_crtc->config; |
756f85cf | 8110 | |
391bf048 JN |
8111 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8112 | u32 val = 0; | |
756f85cf | 8113 | |
6e3c9717 | 8114 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8115 | case 18: |
8116 | val |= PIPEMISC_DITHER_6_BPC; | |
8117 | break; | |
8118 | case 24: | |
8119 | val |= PIPEMISC_DITHER_8_BPC; | |
8120 | break; | |
8121 | case 30: | |
8122 | val |= PIPEMISC_DITHER_10_BPC; | |
8123 | break; | |
8124 | case 36: | |
8125 | val |= PIPEMISC_DITHER_12_BPC; | |
8126 | break; | |
8127 | default: | |
8128 | /* Case prevented by pipe_config_set_bpp. */ | |
8129 | BUG(); | |
8130 | } | |
8131 | ||
6e3c9717 | 8132 | if (intel_crtc->config->dither) |
756f85cf PZ |
8133 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8134 | ||
b22ca995 SS |
8135 | if (config->ycbcr420) { |
8136 | val |= PIPEMISC_OUTPUT_COLORSPACE_YUV | | |
8137 | PIPEMISC_YUV420_ENABLE | | |
8138 | PIPEMISC_YUV420_MODE_FULL_BLEND; | |
8139 | } | |
8140 | ||
391bf048 | 8141 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8142 | } |
ee2b0b38 PZ |
8143 | } |
8144 | ||
d4b1931c PZ |
8145 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8146 | { | |
8147 | /* | |
8148 | * Account for spread spectrum to avoid | |
8149 | * oversubscribing the link. Max center spread | |
8150 | * is 2.5%; use 5% for safety's sake. | |
8151 | */ | |
8152 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8153 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8154 | } |
8155 | ||
7429e9d4 | 8156 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8157 | { |
7429e9d4 | 8158 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8159 | } |
8160 | ||
b75ca6f6 ACO |
8161 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8162 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8163 | struct dpll *reduced_clock) |
79e53945 | 8164 | { |
de13a2e3 | 8165 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 8166 | struct drm_device *dev = crtc->dev; |
fac5e23e | 8167 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 8168 | u32 dpll, fp, fp2; |
3d6e9ee0 | 8169 | int factor; |
79e53945 | 8170 | |
c1858123 | 8171 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 8172 | factor = 21; |
3d6e9ee0 | 8173 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 8174 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 8175 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6e266956 | 8176 | (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8177 | factor = 25; |
190f68c5 | 8178 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8179 | factor = 20; |
c1858123 | 8180 | |
b75ca6f6 ACO |
8181 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8182 | ||
190f68c5 | 8183 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8184 | fp |= FP_CB_TUNE; |
8185 | ||
8186 | if (reduced_clock) { | |
8187 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8188 | |
b75ca6f6 ACO |
8189 | if (reduced_clock->m < factor * reduced_clock->n) |
8190 | fp2 |= FP_CB_TUNE; | |
8191 | } else { | |
8192 | fp2 = fp; | |
8193 | } | |
9a7c7890 | 8194 | |
5eddb70b | 8195 | dpll = 0; |
2c07245f | 8196 | |
3d6e9ee0 | 8197 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
8198 | dpll |= DPLLB_MODE_LVDS; |
8199 | else | |
8200 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8201 | |
190f68c5 | 8202 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8203 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 8204 | |
3d6e9ee0 VS |
8205 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8206 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8207 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 8208 | |
37a5650b | 8209 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8210 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8211 | |
7d7f8633 VS |
8212 | /* |
8213 | * The high speed IO clock is only really required for | |
8214 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
8215 | * possible to share the DPLL between CRT and HDMI. Enabling | |
8216 | * the clock needlessly does no real harm, except use up a | |
8217 | * bit of power potentially. | |
8218 | * | |
8219 | * We'll limit this to IVB with 3 pipes, since it has only two | |
8220 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
8221 | * driving PCH ports at the same time. On SNB we could do this, | |
8222 | * and potentially avoid enabling the second DPLL, but it's not | |
8223 | * clear if it''s a win or loss power wise. No point in doing | |
8224 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
8225 | */ | |
8226 | if (INTEL_INFO(dev_priv)->num_pipes == 3 && | |
8227 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) | |
8228 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
8229 | ||
a07d6787 | 8230 | /* compute bitmask from p1 value */ |
190f68c5 | 8231 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8232 | /* also FPA1 */ |
190f68c5 | 8233 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8234 | |
190f68c5 | 8235 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8236 | case 5: |
8237 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8238 | break; | |
8239 | case 7: | |
8240 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8241 | break; | |
8242 | case 10: | |
8243 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8244 | break; | |
8245 | case 14: | |
8246 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8247 | break; | |
79e53945 JB |
8248 | } |
8249 | ||
3d6e9ee0 VS |
8250 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8251 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 8252 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8253 | else |
8254 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8255 | ||
b75ca6f6 ACO |
8256 | dpll |= DPLL_VCO_ENABLE; |
8257 | ||
8258 | crtc_state->dpll_hw_state.dpll = dpll; | |
8259 | crtc_state->dpll_hw_state.fp0 = fp; | |
8260 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8261 | } |
8262 | ||
190f68c5 ACO |
8263 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8264 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8265 | { |
997c030c | 8266 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8267 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8268 | const struct intel_limit *limit; |
997c030c | 8269 | int refclk = 120000; |
de13a2e3 | 8270 | |
dd3cd74a ACO |
8271 | memset(&crtc_state->dpll_hw_state, 0, |
8272 | sizeof(crtc_state->dpll_hw_state)); | |
8273 | ||
ded220e2 ACO |
8274 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8275 | if (!crtc_state->has_pch_encoder) | |
8276 | return 0; | |
79e53945 | 8277 | |
2d84d2b3 | 8278 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
8279 | if (intel_panel_use_ssc(dev_priv)) { |
8280 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8281 | dev_priv->vbt.lvds_ssc_freq); | |
8282 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8283 | } | |
8284 | ||
8285 | if (intel_is_dual_link_lvds(dev)) { | |
8286 | if (refclk == 100000) | |
8287 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8288 | else | |
8289 | limit = &intel_limits_ironlake_dual_lvds; | |
8290 | } else { | |
8291 | if (refclk == 100000) | |
8292 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8293 | else | |
8294 | limit = &intel_limits_ironlake_single_lvds; | |
8295 | } | |
8296 | } else { | |
8297 | limit = &intel_limits_ironlake_dac; | |
8298 | } | |
8299 | ||
364ee29d | 8300 | if (!crtc_state->clock_set && |
997c030c ACO |
8301 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8302 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
8303 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8304 | return -EINVAL; | |
f47709a9 | 8305 | } |
79e53945 | 8306 | |
cbaa3315 | 8307 | ironlake_compute_dpll(crtc, crtc_state, NULL); |
66e985c0 | 8308 | |
efd38b68 | 8309 | if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) { |
ded220e2 ACO |
8310 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
8311 | pipe_name(crtc->pipe)); | |
8312 | return -EINVAL; | |
3fb37703 | 8313 | } |
79e53945 | 8314 | |
c8f7a0db | 8315 | return 0; |
79e53945 JB |
8316 | } |
8317 | ||
eb14cb74 VS |
8318 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8319 | struct intel_link_m_n *m_n) | |
8320 | { | |
8321 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8322 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
8323 | enum pipe pipe = crtc->pipe; |
8324 | ||
8325 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8326 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8327 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8328 | & ~TU_SIZE_MASK; | |
8329 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8330 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8331 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8332 | } | |
8333 | ||
8334 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8335 | enum transcoder transcoder, | |
b95af8be VK |
8336 | struct intel_link_m_n *m_n, |
8337 | struct intel_link_m_n *m2_n2) | |
72419203 | 8338 | { |
6315b5d3 | 8339 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb14cb74 | 8340 | enum pipe pipe = crtc->pipe; |
72419203 | 8341 | |
6315b5d3 | 8342 | if (INTEL_GEN(dev_priv) >= 5) { |
eb14cb74 VS |
8343 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
8344 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8345 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8346 | & ~TU_SIZE_MASK; | |
8347 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8348 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8349 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8350 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8351 | * gen < 8) and if DRRS is supported (to make sure the | |
8352 | * registers are not unnecessarily read). | |
8353 | */ | |
6315b5d3 | 8354 | if (m2_n2 && INTEL_GEN(dev_priv) < 8 && |
6e3c9717 | 8355 | crtc->config->has_drrs) { |
b95af8be VK |
8356 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8357 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8358 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8359 | & ~TU_SIZE_MASK; | |
8360 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8361 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8362 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8363 | } | |
eb14cb74 VS |
8364 | } else { |
8365 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8366 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8367 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8368 | & ~TU_SIZE_MASK; | |
8369 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8370 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8371 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8372 | } | |
8373 | } | |
8374 | ||
8375 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8376 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8377 | { |
681a8504 | 8378 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8379 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8380 | else | |
8381 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8382 | &pipe_config->dp_m_n, |
8383 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8384 | } |
72419203 | 8385 | |
eb14cb74 | 8386 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8387 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8388 | { |
8389 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8390 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8391 | } |
8392 | ||
bd2e244f | 8393 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8394 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8395 | { |
8396 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8397 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
8398 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8399 | uint32_t ps_ctrl = 0; | |
8400 | int id = -1; | |
8401 | int i; | |
bd2e244f | 8402 | |
a1b2278e CK |
8403 | /* find scaler attached to this pipe */ |
8404 | for (i = 0; i < crtc->num_scalers; i++) { | |
8405 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8406 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8407 | id = i; | |
8408 | pipe_config->pch_pfit.enabled = true; | |
8409 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8410 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8411 | break; | |
8412 | } | |
8413 | } | |
bd2e244f | 8414 | |
a1b2278e CK |
8415 | scaler_state->scaler_id = id; |
8416 | if (id >= 0) { | |
8417 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8418 | } else { | |
8419 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8420 | } |
8421 | } | |
8422 | ||
5724dbd1 DL |
8423 | static void |
8424 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8425 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8426 | { |
8427 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8428 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 8429 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8430 | int pipe = crtc->pipe; |
8431 | int fourcc, pixel_format; | |
6761dd31 | 8432 | unsigned int aligned_height; |
bc8d7dff | 8433 | struct drm_framebuffer *fb; |
1b842c89 | 8434 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8435 | |
d9806c9f | 8436 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8437 | if (!intel_fb) { |
bc8d7dff DL |
8438 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8439 | return; | |
8440 | } | |
8441 | ||
1b842c89 DL |
8442 | fb = &intel_fb->base; |
8443 | ||
d2e9f5fc VS |
8444 | fb->dev = dev; |
8445 | ||
bc8d7dff | 8446 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8447 | if (!(val & PLANE_CTL_ENABLE)) |
8448 | goto error; | |
8449 | ||
bc8d7dff DL |
8450 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8451 | fourcc = skl_format_to_fourcc(pixel_format, | |
8452 | val & PLANE_CTL_ORDER_RGBX, | |
8453 | val & PLANE_CTL_ALPHA_MASK); | |
2f3f4763 | 8454 | fb->format = drm_format_info(fourcc); |
bc8d7dff | 8455 | |
40f46283 DL |
8456 | tiling = val & PLANE_CTL_TILED_MASK; |
8457 | switch (tiling) { | |
8458 | case PLANE_CTL_TILED_LINEAR: | |
2f075565 | 8459 | fb->modifier = DRM_FORMAT_MOD_LINEAR; |
40f46283 DL |
8460 | break; |
8461 | case PLANE_CTL_TILED_X: | |
8462 | plane_config->tiling = I915_TILING_X; | |
bae781b2 | 8463 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
40f46283 DL |
8464 | break; |
8465 | case PLANE_CTL_TILED_Y: | |
2e2adb05 VS |
8466 | if (val & PLANE_CTL_DECOMPRESSION_ENABLE) |
8467 | fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; | |
8468 | else | |
8469 | fb->modifier = I915_FORMAT_MOD_Y_TILED; | |
40f46283 DL |
8470 | break; |
8471 | case PLANE_CTL_TILED_YF: | |
2e2adb05 VS |
8472 | if (val & PLANE_CTL_DECOMPRESSION_ENABLE) |
8473 | fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; | |
8474 | else | |
8475 | fb->modifier = I915_FORMAT_MOD_Yf_TILED; | |
40f46283 DL |
8476 | break; |
8477 | default: | |
8478 | MISSING_CASE(tiling); | |
8479 | goto error; | |
8480 | } | |
8481 | ||
bc8d7dff DL |
8482 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8483 | plane_config->base = base; | |
8484 | ||
8485 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8486 | ||
8487 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8488 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8489 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8490 | ||
8491 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
d88c4afd | 8492 | stride_mult = intel_fb_stride_alignment(fb, 0); |
bc8d7dff DL |
8493 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8494 | ||
d88c4afd | 8495 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
bc8d7dff | 8496 | |
f37b5c2b | 8497 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8498 | |
8499 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8500 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8501 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
bc8d7dff DL |
8502 | plane_config->size); |
8503 | ||
2d14030b | 8504 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8505 | return; |
8506 | ||
8507 | error: | |
d1a3a036 | 8508 | kfree(intel_fb); |
bc8d7dff DL |
8509 | } |
8510 | ||
2fa2fe9a | 8511 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8512 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8513 | { |
8514 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8515 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8516 | uint32_t tmp; |
8517 | ||
8518 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8519 | ||
8520 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8521 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8522 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8523 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8524 | |
8525 | /* We currently do not free assignements of panel fitters on | |
8526 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8527 | * differentiates them) so just WARN about this case for now. */ | |
5db94019 | 8528 | if (IS_GEN7(dev_priv)) { |
cb8b2a30 DV |
8529 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
8530 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8531 | } | |
2fa2fe9a | 8532 | } |
79e53945 JB |
8533 | } |
8534 | ||
5724dbd1 DL |
8535 | static void |
8536 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8537 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8538 | { |
8539 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8540 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 8541 | u32 val, base, offset; |
aeee5a49 | 8542 | int pipe = crtc->pipe; |
4c6baa59 | 8543 | int fourcc, pixel_format; |
6761dd31 | 8544 | unsigned int aligned_height; |
b113d5ee | 8545 | struct drm_framebuffer *fb; |
1b842c89 | 8546 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8547 | |
42a7b088 DL |
8548 | val = I915_READ(DSPCNTR(pipe)); |
8549 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8550 | return; | |
8551 | ||
d9806c9f | 8552 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8553 | if (!intel_fb) { |
4c6baa59 JB |
8554 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8555 | return; | |
8556 | } | |
8557 | ||
1b842c89 DL |
8558 | fb = &intel_fb->base; |
8559 | ||
d2e9f5fc VS |
8560 | fb->dev = dev; |
8561 | ||
6315b5d3 | 8562 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 8563 | if (val & DISPPLANE_TILED) { |
49af449b | 8564 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 8565 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
8566 | } |
8567 | } | |
4c6baa59 JB |
8568 | |
8569 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8570 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 8571 | fb->format = drm_format_info(fourcc); |
4c6baa59 | 8572 | |
aeee5a49 | 8573 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
8652744b | 8574 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
aeee5a49 | 8575 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8576 | } else { |
49af449b | 8577 | if (plane_config->tiling) |
aeee5a49 | 8578 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8579 | else |
aeee5a49 | 8580 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8581 | } |
8582 | plane_config->base = base; | |
8583 | ||
8584 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8585 | fb->width = ((val >> 16) & 0xfff) + 1; |
8586 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8587 | |
8588 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8589 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8590 | |
d88c4afd | 8591 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
4c6baa59 | 8592 | |
f37b5c2b | 8593 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8594 | |
2844a921 DL |
8595 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8596 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8597 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 8598 | plane_config->size); |
b113d5ee | 8599 | |
2d14030b | 8600 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8601 | } |
8602 | ||
0e8ffe1b | 8603 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8604 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8605 | { |
8606 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8607 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8608 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8609 | uint32_t tmp; |
1729050e | 8610 | bool ret; |
0e8ffe1b | 8611 | |
1729050e ID |
8612 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8613 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
8614 | return false; |
8615 | ||
e143a21c | 8616 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8617 | pipe_config->shared_dpll = NULL; |
eccb140b | 8618 | |
1729050e | 8619 | ret = false; |
0e8ffe1b DV |
8620 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8621 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8622 | goto out; |
0e8ffe1b | 8623 | |
42571aef VS |
8624 | switch (tmp & PIPECONF_BPC_MASK) { |
8625 | case PIPECONF_6BPC: | |
8626 | pipe_config->pipe_bpp = 18; | |
8627 | break; | |
8628 | case PIPECONF_8BPC: | |
8629 | pipe_config->pipe_bpp = 24; | |
8630 | break; | |
8631 | case PIPECONF_10BPC: | |
8632 | pipe_config->pipe_bpp = 30; | |
8633 | break; | |
8634 | case PIPECONF_12BPC: | |
8635 | pipe_config->pipe_bpp = 36; | |
8636 | break; | |
8637 | default: | |
8638 | break; | |
8639 | } | |
8640 | ||
b5a9fa09 DV |
8641 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8642 | pipe_config->limited_color_range = true; | |
8643 | ||
ab9412ba | 8644 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 8645 | struct intel_shared_dpll *pll; |
8106ddbd | 8646 | enum intel_dpll_id pll_id; |
66e985c0 | 8647 | |
88adfff1 DV |
8648 | pipe_config->has_pch_encoder = true; |
8649 | ||
627eb5a3 DV |
8650 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8651 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8652 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8653 | |
8654 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8655 | |
2d1fe073 | 8656 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
8657 | /* |
8658 | * The pipe->pch transcoder and pch transcoder->pll | |
8659 | * mapping is fixed. | |
8660 | */ | |
8106ddbd | 8661 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
8662 | } else { |
8663 | tmp = I915_READ(PCH_DPLL_SEL); | |
8664 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 8665 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 8666 | else |
8106ddbd | 8667 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 8668 | } |
66e985c0 | 8669 | |
8106ddbd ACO |
8670 | pipe_config->shared_dpll = |
8671 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
8672 | pll = pipe_config->shared_dpll; | |
66e985c0 | 8673 | |
2edd6443 ACO |
8674 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
8675 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8676 | |
8677 | tmp = pipe_config->dpll_hw_state.dpll; | |
8678 | pipe_config->pixel_multiplier = | |
8679 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8680 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8681 | |
8682 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8683 | } else { |
8684 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8685 | } |
8686 | ||
1bd1bd80 | 8687 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8688 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8689 | |
2fa2fe9a DV |
8690 | ironlake_get_pfit_config(crtc, pipe_config); |
8691 | ||
1729050e ID |
8692 | ret = true; |
8693 | ||
8694 | out: | |
8695 | intel_display_power_put(dev_priv, power_domain); | |
8696 | ||
8697 | return ret; | |
0e8ffe1b DV |
8698 | } |
8699 | ||
be256dc7 PZ |
8700 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8701 | { | |
91c8a326 | 8702 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 8703 | struct intel_crtc *crtc; |
be256dc7 | 8704 | |
d3fcc808 | 8705 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8706 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8707 | pipe_name(crtc->pipe)); |
8708 | ||
9c3a16c8 ID |
8709 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)), |
8710 | "Display power well on\n"); | |
e2c719b7 | 8711 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
01403de3 VS |
8712 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
8713 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 8714 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 8715 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 8716 | "CPU PWM1 enabled\n"); |
772c2a51 | 8717 | if (IS_HASWELL(dev_priv)) |
e2c719b7 | 8718 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8719 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8720 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8721 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8722 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8723 | "Utility pin enabled\n"); |
e2c719b7 | 8724 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8725 | |
9926ada1 PZ |
8726 | /* |
8727 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8728 | * interrupts remain enabled. We used to check for that, but since it's | |
8729 | * gen-specific and since we only disable LCPLL after we fully disable | |
8730 | * the interrupts, the check below should be enough. | |
8731 | */ | |
e2c719b7 | 8732 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8733 | } |
8734 | ||
9ccd5aeb PZ |
8735 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8736 | { | |
772c2a51 | 8737 | if (IS_HASWELL(dev_priv)) |
9ccd5aeb PZ |
8738 | return I915_READ(D_COMP_HSW); |
8739 | else | |
8740 | return I915_READ(D_COMP_BDW); | |
8741 | } | |
8742 | ||
3c4c9b81 PZ |
8743 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8744 | { | |
772c2a51 | 8745 | if (IS_HASWELL(dev_priv)) { |
9f817501 | 8746 | mutex_lock(&dev_priv->pcu_lock); |
3c4c9b81 PZ |
8747 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, |
8748 | val)) | |
79cf219a | 8749 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
9f817501 | 8750 | mutex_unlock(&dev_priv->pcu_lock); |
3c4c9b81 | 8751 | } else { |
9ccd5aeb PZ |
8752 | I915_WRITE(D_COMP_BDW, val); |
8753 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8754 | } |
be256dc7 PZ |
8755 | } |
8756 | ||
8757 | /* | |
8758 | * This function implements pieces of two sequences from BSpec: | |
8759 | * - Sequence for display software to disable LCPLL | |
8760 | * - Sequence for display software to allow package C8+ | |
8761 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8762 | * register. Callers should take care of disabling all the display engine | |
8763 | * functions, doing the mode unset, fixing interrupts, etc. | |
8764 | */ | |
6ff58d53 PZ |
8765 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8766 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8767 | { |
8768 | uint32_t val; | |
8769 | ||
8770 | assert_can_disable_lcpll(dev_priv); | |
8771 | ||
8772 | val = I915_READ(LCPLL_CTL); | |
8773 | ||
8774 | if (switch_to_fclk) { | |
8775 | val |= LCPLL_CD_SOURCE_FCLK; | |
8776 | I915_WRITE(LCPLL_CTL, val); | |
8777 | ||
f53dd63f ID |
8778 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
8779 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
8780 | DRM_ERROR("Switching to FCLK failed\n"); |
8781 | ||
8782 | val = I915_READ(LCPLL_CTL); | |
8783 | } | |
8784 | ||
8785 | val |= LCPLL_PLL_DISABLE; | |
8786 | I915_WRITE(LCPLL_CTL, val); | |
8787 | POSTING_READ(LCPLL_CTL); | |
8788 | ||
24d8441d | 8789 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
8790 | DRM_ERROR("LCPLL still locked\n"); |
8791 | ||
9ccd5aeb | 8792 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8793 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8794 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8795 | ndelay(100); |
8796 | ||
9ccd5aeb PZ |
8797 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8798 | 1)) | |
be256dc7 PZ |
8799 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8800 | ||
8801 | if (allow_power_down) { | |
8802 | val = I915_READ(LCPLL_CTL); | |
8803 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8804 | I915_WRITE(LCPLL_CTL, val); | |
8805 | POSTING_READ(LCPLL_CTL); | |
8806 | } | |
8807 | } | |
8808 | ||
8809 | /* | |
8810 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8811 | * source. | |
8812 | */ | |
6ff58d53 | 8813 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8814 | { |
8815 | uint32_t val; | |
8816 | ||
8817 | val = I915_READ(LCPLL_CTL); | |
8818 | ||
8819 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8820 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8821 | return; | |
8822 | ||
a8a8bd54 PZ |
8823 | /* |
8824 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8825 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8826 | */ |
59bad947 | 8827 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8828 | |
be256dc7 PZ |
8829 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8830 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8831 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8832 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8833 | } |
8834 | ||
9ccd5aeb | 8835 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8836 | val |= D_COMP_COMP_FORCE; |
8837 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8838 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8839 | |
8840 | val = I915_READ(LCPLL_CTL); | |
8841 | val &= ~LCPLL_PLL_DISABLE; | |
8842 | I915_WRITE(LCPLL_CTL, val); | |
8843 | ||
93220c08 CW |
8844 | if (intel_wait_for_register(dev_priv, |
8845 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
8846 | 5)) | |
be256dc7 PZ |
8847 | DRM_ERROR("LCPLL not locked yet\n"); |
8848 | ||
8849 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8850 | val = I915_READ(LCPLL_CTL); | |
8851 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8852 | I915_WRITE(LCPLL_CTL, val); | |
8853 | ||
f53dd63f ID |
8854 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
8855 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
8856 | DRM_ERROR("Switching back to LCPLL failed\n"); |
8857 | } | |
215733fa | 8858 | |
59bad947 | 8859 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4c75b940 | 8860 | intel_update_cdclk(dev_priv); |
be256dc7 PZ |
8861 | } |
8862 | ||
765dab67 PZ |
8863 | /* |
8864 | * Package states C8 and deeper are really deep PC states that can only be | |
8865 | * reached when all the devices on the system allow it, so even if the graphics | |
8866 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8867 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8868 | * | |
8869 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8870 | * well is disabled and most interrupts are disabled, and these are also | |
8871 | * requirements for runtime PM. When these conditions are met, we manually do | |
8872 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8873 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8874 | * hang the machine. | |
8875 | * | |
8876 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8877 | * the state of some registers, so when we come back from PC8+ we need to | |
8878 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8879 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8880 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8881 | * because of the runtime PM support). | |
8882 | * | |
8883 | * For more, read "Display Sequences for Package C8" on the hardware | |
8884 | * documentation. | |
8885 | */ | |
a14cb6fc | 8886 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8887 | { |
c67a470b PZ |
8888 | uint32_t val; |
8889 | ||
c67a470b PZ |
8890 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8891 | ||
4f8036a2 | 8892 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8893 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8894 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8895 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8896 | } | |
8897 | ||
c39055b0 | 8898 | lpt_disable_clkout_dp(dev_priv); |
c67a470b PZ |
8899 | hsw_disable_lcpll(dev_priv, true, true); |
8900 | } | |
8901 | ||
a14cb6fc | 8902 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8903 | { |
c67a470b PZ |
8904 | uint32_t val; |
8905 | ||
c67a470b PZ |
8906 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
8907 | ||
8908 | hsw_restore_lcpll(dev_priv); | |
c39055b0 | 8909 | lpt_init_pch_refclk(dev_priv); |
c67a470b | 8910 | |
4f8036a2 | 8911 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8912 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8913 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
8914 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8915 | } | |
c67a470b PZ |
8916 | } |
8917 | ||
190f68c5 ACO |
8918 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
8919 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 8920 | { |
d7edc4e5 | 8921 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
44a126ba PZ |
8922 | struct intel_encoder *encoder = |
8923 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
8924 | ||
8925 | if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) { | |
8926 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8927 | pipe_name(crtc->pipe)); | |
af3997b5 | 8928 | return -EINVAL; |
44a126ba | 8929 | } |
af3997b5 | 8930 | } |
716c2e55 | 8931 | |
c8f7a0db | 8932 | return 0; |
79e53945 JB |
8933 | } |
8934 | ||
8b0f7e06 KM |
8935 | static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv, |
8936 | enum port port, | |
8937 | struct intel_crtc_state *pipe_config) | |
8938 | { | |
8939 | enum intel_dpll_id id; | |
8940 | u32 temp; | |
8941 | ||
8942 | temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); | |
dfbd4508 | 8943 | id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); |
8b0f7e06 KM |
8944 | |
8945 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2)) | |
8946 | return; | |
8947 | ||
8948 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
8949 | } | |
8950 | ||
3760b59c S |
8951 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
8952 | enum port port, | |
8953 | struct intel_crtc_state *pipe_config) | |
8954 | { | |
8106ddbd ACO |
8955 | enum intel_dpll_id id; |
8956 | ||
3760b59c S |
8957 | switch (port) { |
8958 | case PORT_A: | |
08250c4b | 8959 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
8960 | break; |
8961 | case PORT_B: | |
08250c4b | 8962 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
8963 | break; |
8964 | case PORT_C: | |
08250c4b | 8965 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
8966 | break; |
8967 | default: | |
8968 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 8969 | return; |
3760b59c | 8970 | } |
8106ddbd ACO |
8971 | |
8972 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
8973 | } |
8974 | ||
96b7dfb7 S |
8975 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
8976 | enum port port, | |
5cec258b | 8977 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 8978 | { |
8106ddbd | 8979 | enum intel_dpll_id id; |
a3c988ea | 8980 | u32 temp; |
96b7dfb7 S |
8981 | |
8982 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
c856052a | 8983 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 8984 | |
c856052a | 8985 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 8986 | return; |
8106ddbd ACO |
8987 | |
8988 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
8989 | } |
8990 | ||
7d2c8175 DL |
8991 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
8992 | enum port port, | |
5cec258b | 8993 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 8994 | { |
8106ddbd | 8995 | enum intel_dpll_id id; |
c856052a | 8996 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
8106ddbd | 8997 | |
c856052a | 8998 | switch (ddi_pll_sel) { |
7d2c8175 | 8999 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 9000 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
9001 | break; |
9002 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 9003 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 9004 | break; |
00490c22 | 9005 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 9006 | id = DPLL_ID_SPLL; |
79bd23da | 9007 | break; |
9d16da65 ACO |
9008 | case PORT_CLK_SEL_LCPLL_810: |
9009 | id = DPLL_ID_LCPLL_810; | |
9010 | break; | |
9011 | case PORT_CLK_SEL_LCPLL_1350: | |
9012 | id = DPLL_ID_LCPLL_1350; | |
9013 | break; | |
9014 | case PORT_CLK_SEL_LCPLL_2700: | |
9015 | id = DPLL_ID_LCPLL_2700; | |
9016 | break; | |
8106ddbd | 9017 | default: |
c856052a | 9018 | MISSING_CASE(ddi_pll_sel); |
8106ddbd ACO |
9019 | /* fall through */ |
9020 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 9021 | return; |
7d2c8175 | 9022 | } |
8106ddbd ACO |
9023 | |
9024 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
9025 | } |
9026 | ||
cf30429e JN |
9027 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
9028 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 9029 | u64 *power_domain_mask) |
cf30429e JN |
9030 | { |
9031 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9032 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
9033 | enum intel_display_power_domain power_domain; |
9034 | u32 tmp; | |
9035 | ||
d9a7bc67 ID |
9036 | /* |
9037 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
9038 | * transcoder handled below. | |
9039 | */ | |
cf30429e JN |
9040 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
9041 | ||
9042 | /* | |
9043 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
9044 | * consistency and less surprising code; it's in always on power). | |
9045 | */ | |
9046 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
9047 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9048 | enum pipe trans_edp_pipe; | |
9049 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9050 | default: | |
9051 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9052 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9053 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9054 | trans_edp_pipe = PIPE_A; | |
9055 | break; | |
9056 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9057 | trans_edp_pipe = PIPE_B; | |
9058 | break; | |
9059 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9060 | trans_edp_pipe = PIPE_C; | |
9061 | break; | |
9062 | } | |
9063 | ||
9064 | if (trans_edp_pipe == crtc->pipe) | |
9065 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9066 | } | |
9067 | ||
9068 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
9069 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9070 | return false; | |
d8fc70b7 | 9071 | *power_domain_mask |= BIT_ULL(power_domain); |
cf30429e JN |
9072 | |
9073 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
9074 | ||
9075 | return tmp & PIPECONF_ENABLE; | |
9076 | } | |
9077 | ||
4d1de975 JN |
9078 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
9079 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 9080 | u64 *power_domain_mask) |
4d1de975 JN |
9081 | { |
9082 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9083 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
9084 | enum intel_display_power_domain power_domain; |
9085 | enum port port; | |
9086 | enum transcoder cpu_transcoder; | |
9087 | u32 tmp; | |
9088 | ||
4d1de975 JN |
9089 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
9090 | if (port == PORT_A) | |
9091 | cpu_transcoder = TRANSCODER_DSI_A; | |
9092 | else | |
9093 | cpu_transcoder = TRANSCODER_DSI_C; | |
9094 | ||
9095 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
9096 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9097 | continue; | |
d8fc70b7 | 9098 | *power_domain_mask |= BIT_ULL(power_domain); |
4d1de975 | 9099 | |
db18b6a6 ID |
9100 | /* |
9101 | * The PLL needs to be enabled with a valid divider | |
9102 | * configuration, otherwise accessing DSI registers will hang | |
9103 | * the machine. See BSpec North Display Engine | |
9104 | * registers/MIPI[BXT]. We can break out here early, since we | |
9105 | * need the same DSI PLL to be enabled for both DSI ports. | |
9106 | */ | |
9107 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
9108 | break; | |
9109 | ||
4d1de975 JN |
9110 | /* XXX: this works for video mode only */ |
9111 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9112 | if (!(tmp & DPI_ENABLE)) | |
9113 | continue; | |
9114 | ||
9115 | tmp = I915_READ(MIPI_CTRL(port)); | |
9116 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9117 | continue; | |
9118 | ||
9119 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
9120 | break; |
9121 | } | |
9122 | ||
d7edc4e5 | 9123 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
9124 | } |
9125 | ||
26804afd | 9126 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9127 | struct intel_crtc_state *pipe_config) |
26804afd | 9128 | { |
6315b5d3 | 9129 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d452c5b6 | 9130 | struct intel_shared_dpll *pll; |
26804afd DV |
9131 | enum port port; |
9132 | uint32_t tmp; | |
9133 | ||
9134 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9135 | ||
9136 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9137 | ||
8b0f7e06 KM |
9138 | if (IS_CANNONLAKE(dev_priv)) |
9139 | cannonlake_get_ddi_pll(dev_priv, port, pipe_config); | |
9140 | else if (IS_GEN9_BC(dev_priv)) | |
96b7dfb7 | 9141 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
cc3f90f0 | 9142 | else if (IS_GEN9_LP(dev_priv)) |
3760b59c | 9143 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 S |
9144 | else |
9145 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9146 | |
8106ddbd ACO |
9147 | pll = pipe_config->shared_dpll; |
9148 | if (pll) { | |
2edd6443 ACO |
9149 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9150 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9151 | } |
9152 | ||
26804afd DV |
9153 | /* |
9154 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9155 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9156 | * the PCH transcoder is on. | |
9157 | */ | |
6315b5d3 | 9158 | if (INTEL_GEN(dev_priv) < 9 && |
ca370455 | 9159 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
26804afd DV |
9160 | pipe_config->has_pch_encoder = true; |
9161 | ||
9162 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9163 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9164 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9165 | ||
9166 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9167 | } | |
9168 | } | |
9169 | ||
0e8ffe1b | 9170 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9171 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 9172 | { |
6315b5d3 | 9173 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 9174 | enum intel_display_power_domain power_domain; |
d8fc70b7 | 9175 | u64 power_domain_mask; |
cf30429e | 9176 | bool active; |
0e8ffe1b | 9177 | |
e79dfb51 | 9178 | intel_crtc_init_scalers(crtc, pipe_config); |
5fb9dadf | 9179 | |
1729050e ID |
9180 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9181 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9182 | return false; |
d8fc70b7 | 9183 | power_domain_mask = BIT_ULL(power_domain); |
1729050e | 9184 | |
8106ddbd | 9185 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9186 | |
cf30429e | 9187 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9188 | |
cc3f90f0 | 9189 | if (IS_GEN9_LP(dev_priv) && |
d7edc4e5 VS |
9190 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { |
9191 | WARN_ON(active); | |
9192 | active = true; | |
4d1de975 JN |
9193 | } |
9194 | ||
cf30429e | 9195 | if (!active) |
1729050e | 9196 | goto out; |
0e8ffe1b | 9197 | |
d7edc4e5 | 9198 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
9199 | haswell_get_ddi_port_state(crtc, pipe_config); |
9200 | intel_get_pipe_timings(crtc, pipe_config); | |
9201 | } | |
627eb5a3 | 9202 | |
bc58be60 | 9203 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9204 | |
05dc698c LL |
9205 | pipe_config->gamma_mode = |
9206 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
9207 | ||
bd30ca2d | 9208 | if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) { |
b22ca995 SS |
9209 | u32 tmp = I915_READ(PIPEMISC(crtc->pipe)); |
9210 | bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV; | |
9211 | ||
bd30ca2d | 9212 | if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) { |
b22ca995 SS |
9213 | bool blend_mode_420 = tmp & |
9214 | PIPEMISC_YUV420_MODE_FULL_BLEND; | |
9215 | ||
9216 | pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE; | |
9217 | if (pipe_config->ycbcr420 != clrspace_yuv || | |
9218 | pipe_config->ycbcr420 != blend_mode_420) | |
9219 | DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp); | |
9220 | } else if (clrspace_yuv) { | |
9221 | DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n"); | |
9222 | } | |
9223 | } | |
9224 | ||
1729050e ID |
9225 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
9226 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
d8fc70b7 | 9227 | power_domain_mask |= BIT_ULL(power_domain); |
6315b5d3 | 9228 | if (INTEL_GEN(dev_priv) >= 9) |
bd2e244f | 9229 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9230 | else |
1c132b44 | 9231 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9232 | } |
88adfff1 | 9233 | |
772c2a51 | 9234 | if (IS_HASWELL(dev_priv)) |
e59150dc JB |
9235 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
9236 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9237 | |
4d1de975 JN |
9238 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
9239 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
9240 | pipe_config->pixel_multiplier = |
9241 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9242 | } else { | |
9243 | pipe_config->pixel_multiplier = 1; | |
9244 | } | |
6c49f241 | 9245 | |
1729050e ID |
9246 | out: |
9247 | for_each_power_domain(power_domain, power_domain_mask) | |
9248 | intel_display_power_put(dev_priv, power_domain); | |
9249 | ||
cf30429e | 9250 | return active; |
0e8ffe1b DV |
9251 | } |
9252 | ||
cd5dcbf1 | 9253 | static u32 intel_cursor_base(const struct intel_plane_state *plane_state) |
1cecc830 VS |
9254 | { |
9255 | struct drm_i915_private *dev_priv = | |
9256 | to_i915(plane_state->base.plane->dev); | |
9257 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
9258 | const struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
9259 | u32 base; | |
9260 | ||
9261 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) | |
9262 | base = obj->phys_handle->busaddr; | |
9263 | else | |
9264 | base = intel_plane_ggtt_offset(plane_state); | |
9265 | ||
1e7b4fd8 VS |
9266 | base += plane_state->main.offset; |
9267 | ||
1cecc830 VS |
9268 | /* ILK+ do this automagically */ |
9269 | if (HAS_GMCH_DISPLAY(dev_priv) && | |
a82256bc | 9270 | plane_state->base.rotation & DRM_MODE_ROTATE_180) |
1cecc830 VS |
9271 | base += (plane_state->base.crtc_h * |
9272 | plane_state->base.crtc_w - 1) * fb->format->cpp[0]; | |
9273 | ||
9274 | return base; | |
9275 | } | |
9276 | ||
ed270223 VS |
9277 | static u32 intel_cursor_position(const struct intel_plane_state *plane_state) |
9278 | { | |
9279 | int x = plane_state->base.crtc_x; | |
9280 | int y = plane_state->base.crtc_y; | |
9281 | u32 pos = 0; | |
9282 | ||
9283 | if (x < 0) { | |
9284 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9285 | x = -x; | |
9286 | } | |
9287 | pos |= x << CURSOR_X_SHIFT; | |
9288 | ||
9289 | if (y < 0) { | |
9290 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9291 | y = -y; | |
9292 | } | |
9293 | pos |= y << CURSOR_Y_SHIFT; | |
9294 | ||
9295 | return pos; | |
9296 | } | |
9297 | ||
3637ecf0 VS |
9298 | static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) |
9299 | { | |
9300 | const struct drm_mode_config *config = | |
9301 | &plane_state->base.plane->dev->mode_config; | |
9302 | int width = plane_state->base.crtc_w; | |
9303 | int height = plane_state->base.crtc_h; | |
9304 | ||
9305 | return width > 0 && width <= config->cursor_width && | |
9306 | height > 0 && height <= config->cursor_height; | |
9307 | } | |
9308 | ||
659056f2 VS |
9309 | static int intel_check_cursor(struct intel_crtc_state *crtc_state, |
9310 | struct intel_plane_state *plane_state) | |
9311 | { | |
9312 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
1e7b4fd8 VS |
9313 | int src_x, src_y; |
9314 | u32 offset; | |
659056f2 VS |
9315 | int ret; |
9316 | ||
9317 | ret = drm_plane_helper_check_state(&plane_state->base, | |
9318 | &plane_state->clip, | |
9319 | DRM_PLANE_HELPER_NO_SCALING, | |
9320 | DRM_PLANE_HELPER_NO_SCALING, | |
9321 | true, true); | |
9322 | if (ret) | |
9323 | return ret; | |
9324 | ||
9325 | if (!fb) | |
9326 | return 0; | |
9327 | ||
9328 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { | |
9329 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); | |
9330 | return -EINVAL; | |
9331 | } | |
9332 | ||
1e7b4fd8 VS |
9333 | src_x = plane_state->base.src_x >> 16; |
9334 | src_y = plane_state->base.src_y >> 16; | |
9335 | ||
9336 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); | |
9337 | offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0); | |
9338 | ||
9339 | if (src_x != 0 || src_y != 0) { | |
9340 | DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n"); | |
9341 | return -EINVAL; | |
9342 | } | |
9343 | ||
9344 | plane_state->main.offset = offset; | |
9345 | ||
659056f2 VS |
9346 | return 0; |
9347 | } | |
9348 | ||
292889e1 VS |
9349 | static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, |
9350 | const struct intel_plane_state *plane_state) | |
9351 | { | |
1e1bb871 | 9352 | const struct drm_framebuffer *fb = plane_state->base.fb; |
292889e1 | 9353 | |
292889e1 VS |
9354 | return CURSOR_ENABLE | |
9355 | CURSOR_GAMMA_ENABLE | | |
9356 | CURSOR_FORMAT_ARGB | | |
1e1bb871 | 9357 | CURSOR_STRIDE(fb->pitches[0]); |
292889e1 VS |
9358 | } |
9359 | ||
659056f2 VS |
9360 | static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) |
9361 | { | |
659056f2 | 9362 | int width = plane_state->base.crtc_w; |
659056f2 VS |
9363 | |
9364 | /* | |
9365 | * 845g/865g are only limited by the width of their cursors, | |
9366 | * the height is arbitrary up to the precision of the register. | |
9367 | */ | |
3637ecf0 | 9368 | return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64); |
659056f2 VS |
9369 | } |
9370 | ||
9371 | static int i845_check_cursor(struct intel_plane *plane, | |
9372 | struct intel_crtc_state *crtc_state, | |
9373 | struct intel_plane_state *plane_state) | |
9374 | { | |
9375 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
659056f2 VS |
9376 | int ret; |
9377 | ||
9378 | ret = intel_check_cursor(crtc_state, plane_state); | |
9379 | if (ret) | |
9380 | return ret; | |
9381 | ||
9382 | /* if we want to turn off the cursor ignore width and height */ | |
1e1bb871 | 9383 | if (!fb) |
659056f2 VS |
9384 | return 0; |
9385 | ||
9386 | /* Check for which cursor types we support */ | |
9387 | if (!i845_cursor_size_ok(plane_state)) { | |
9388 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
9389 | plane_state->base.crtc_w, | |
9390 | plane_state->base.crtc_h); | |
9391 | return -EINVAL; | |
9392 | } | |
9393 | ||
1e1bb871 | 9394 | switch (fb->pitches[0]) { |
292889e1 VS |
9395 | case 256: |
9396 | case 512: | |
9397 | case 1024: | |
9398 | case 2048: | |
9399 | break; | |
1e1bb871 VS |
9400 | default: |
9401 | DRM_DEBUG_KMS("Invalid cursor stride (%u)\n", | |
9402 | fb->pitches[0]); | |
9403 | return -EINVAL; | |
292889e1 VS |
9404 | } |
9405 | ||
659056f2 VS |
9406 | plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); |
9407 | ||
9408 | return 0; | |
292889e1 VS |
9409 | } |
9410 | ||
b2d03b0d VS |
9411 | static void i845_update_cursor(struct intel_plane *plane, |
9412 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 9413 | const struct intel_plane_state *plane_state) |
560b85bb | 9414 | { |
cd5dcbf1 | 9415 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
b2d03b0d VS |
9416 | u32 cntl = 0, base = 0, pos = 0, size = 0; |
9417 | unsigned long irqflags; | |
560b85bb | 9418 | |
936e71e3 | 9419 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
9420 | unsigned int width = plane_state->base.crtc_w; |
9421 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 | 9422 | |
a0864d59 | 9423 | cntl = plane_state->ctl; |
dc41c154 | 9424 | size = (height << 12) | width; |
560b85bb | 9425 | |
b2d03b0d VS |
9426 | base = intel_cursor_base(plane_state); |
9427 | pos = intel_cursor_position(plane_state); | |
4b0e333e | 9428 | } |
560b85bb | 9429 | |
b2d03b0d | 9430 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
4726e0b0 | 9431 | |
e11ffddb VS |
9432 | /* On these chipsets we can only modify the base/size/stride |
9433 | * whilst the cursor is disabled. | |
9434 | */ | |
9435 | if (plane->cursor.base != base || | |
9436 | plane->cursor.size != size || | |
9437 | plane->cursor.cntl != cntl) { | |
dd584fc0 | 9438 | I915_WRITE_FW(CURCNTR(PIPE_A), 0); |
dd584fc0 | 9439 | I915_WRITE_FW(CURBASE(PIPE_A), base); |
dd584fc0 | 9440 | I915_WRITE_FW(CURSIZE, size); |
b2d03b0d | 9441 | I915_WRITE_FW(CURPOS(PIPE_A), pos); |
dd584fc0 | 9442 | I915_WRITE_FW(CURCNTR(PIPE_A), cntl); |
75343a44 | 9443 | |
e11ffddb VS |
9444 | plane->cursor.base = base; |
9445 | plane->cursor.size = size; | |
9446 | plane->cursor.cntl = cntl; | |
9447 | } else { | |
9448 | I915_WRITE_FW(CURPOS(PIPE_A), pos); | |
560b85bb | 9449 | } |
e11ffddb | 9450 | |
75343a44 | 9451 | POSTING_READ_FW(CURCNTR(PIPE_A)); |
b2d03b0d VS |
9452 | |
9453 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
9454 | } | |
9455 | ||
9456 | static void i845_disable_cursor(struct intel_plane *plane, | |
9457 | struct intel_crtc *crtc) | |
9458 | { | |
9459 | i845_update_cursor(plane, NULL, NULL); | |
560b85bb CW |
9460 | } |
9461 | ||
292889e1 VS |
9462 | static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, |
9463 | const struct intel_plane_state *plane_state) | |
9464 | { | |
9465 | struct drm_i915_private *dev_priv = | |
9466 | to_i915(plane_state->base.plane->dev); | |
9467 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
292889e1 VS |
9468 | u32 cntl; |
9469 | ||
9470 | cntl = MCURSOR_GAMMA_ENABLE; | |
9471 | ||
9472 | if (HAS_DDI(dev_priv)) | |
9473 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
9474 | ||
d509e28b | 9475 | cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); |
292889e1 VS |
9476 | |
9477 | switch (plane_state->base.crtc_w) { | |
9478 | case 64: | |
9479 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9480 | break; | |
9481 | case 128: | |
9482 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9483 | break; | |
9484 | case 256: | |
9485 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9486 | break; | |
9487 | default: | |
9488 | MISSING_CASE(plane_state->base.crtc_w); | |
9489 | return 0; | |
9490 | } | |
9491 | ||
c2c446ad | 9492 | if (plane_state->base.rotation & DRM_MODE_ROTATE_180) |
292889e1 VS |
9493 | cntl |= CURSOR_ROTATE_180; |
9494 | ||
9495 | return cntl; | |
9496 | } | |
9497 | ||
659056f2 | 9498 | static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) |
65a21cd6 | 9499 | { |
024faac7 VS |
9500 | struct drm_i915_private *dev_priv = |
9501 | to_i915(plane_state->base.plane->dev); | |
659056f2 VS |
9502 | int width = plane_state->base.crtc_w; |
9503 | int height = plane_state->base.crtc_h; | |
4b0e333e | 9504 | |
3637ecf0 | 9505 | if (!intel_cursor_size_ok(plane_state)) |
659056f2 | 9506 | return false; |
4398ad45 | 9507 | |
024faac7 VS |
9508 | /* Cursor width is limited to a few power-of-two sizes */ |
9509 | switch (width) { | |
659056f2 VS |
9510 | case 256: |
9511 | case 128: | |
659056f2 VS |
9512 | case 64: |
9513 | break; | |
9514 | default: | |
9515 | return false; | |
65a21cd6 | 9516 | } |
4b0e333e | 9517 | |
024faac7 VS |
9518 | /* |
9519 | * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor | |
9520 | * height from 8 lines up to the cursor width, when the | |
9521 | * cursor is not rotated. Everything else requires square | |
9522 | * cursors. | |
9523 | */ | |
9524 | if (HAS_CUR_FBC(dev_priv) && | |
a82256bc | 9525 | plane_state->base.rotation & DRM_MODE_ROTATE_0) { |
024faac7 VS |
9526 | if (height < 8 || height > width) |
9527 | return false; | |
9528 | } else { | |
9529 | if (height != width) | |
9530 | return false; | |
9531 | } | |
99d1f387 | 9532 | |
659056f2 | 9533 | return true; |
65a21cd6 JB |
9534 | } |
9535 | ||
659056f2 VS |
9536 | static int i9xx_check_cursor(struct intel_plane *plane, |
9537 | struct intel_crtc_state *crtc_state, | |
9538 | struct intel_plane_state *plane_state) | |
cda4b7d3 | 9539 | { |
659056f2 VS |
9540 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
9541 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
659056f2 | 9542 | enum pipe pipe = plane->pipe; |
659056f2 | 9543 | int ret; |
cda4b7d3 | 9544 | |
659056f2 VS |
9545 | ret = intel_check_cursor(crtc_state, plane_state); |
9546 | if (ret) | |
9547 | return ret; | |
cda4b7d3 | 9548 | |
659056f2 | 9549 | /* if we want to turn off the cursor ignore width and height */ |
1e1bb871 | 9550 | if (!fb) |
659056f2 | 9551 | return 0; |
55a08b3f | 9552 | |
659056f2 VS |
9553 | /* Check for which cursor types we support */ |
9554 | if (!i9xx_cursor_size_ok(plane_state)) { | |
9555 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
9556 | plane_state->base.crtc_w, | |
9557 | plane_state->base.crtc_h); | |
9558 | return -EINVAL; | |
cda4b7d3 | 9559 | } |
cda4b7d3 | 9560 | |
1e1bb871 VS |
9561 | if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) { |
9562 | DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n", | |
9563 | fb->pitches[0], plane_state->base.crtc_w); | |
9564 | return -EINVAL; | |
659056f2 | 9565 | } |
dd584fc0 | 9566 | |
659056f2 VS |
9567 | /* |
9568 | * There's something wrong with the cursor on CHV pipe C. | |
9569 | * If it straddles the left edge of the screen then | |
9570 | * moving it away from the edge or disabling it often | |
9571 | * results in a pipe underrun, and often that can lead to | |
9572 | * dead pipe (constant underrun reported, and it scans | |
9573 | * out just a solid color). To recover from that, the | |
9574 | * display power well must be turned off and on again. | |
9575 | * Refuse the put the cursor into that compromised position. | |
9576 | */ | |
9577 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && | |
9578 | plane_state->base.visible && plane_state->base.crtc_x < 0) { | |
9579 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
9580 | return -EINVAL; | |
9581 | } | |
5efb3e28 | 9582 | |
659056f2 | 9583 | plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); |
dd584fc0 | 9584 | |
659056f2 | 9585 | return 0; |
cda4b7d3 CW |
9586 | } |
9587 | ||
b2d03b0d VS |
9588 | static void i9xx_update_cursor(struct intel_plane *plane, |
9589 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 9590 | const struct intel_plane_state *plane_state) |
dc41c154 | 9591 | { |
cd5dcbf1 VS |
9592 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
9593 | enum pipe pipe = plane->pipe; | |
024faac7 | 9594 | u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; |
b2d03b0d | 9595 | unsigned long irqflags; |
dc41c154 | 9596 | |
b2d03b0d | 9597 | if (plane_state && plane_state->base.visible) { |
a0864d59 | 9598 | cntl = plane_state->ctl; |
dc41c154 | 9599 | |
024faac7 VS |
9600 | if (plane_state->base.crtc_h != plane_state->base.crtc_w) |
9601 | fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1); | |
dc41c154 | 9602 | |
b2d03b0d VS |
9603 | base = intel_cursor_base(plane_state); |
9604 | pos = intel_cursor_position(plane_state); | |
9605 | } | |
9606 | ||
9607 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
9608 | ||
e11ffddb VS |
9609 | /* |
9610 | * On some platforms writing CURCNTR first will also | |
9611 | * cause CURPOS to be armed by the CURBASE write. | |
9612 | * Without the CURCNTR write the CURPOS write would | |
8753d2bc VS |
9613 | * arm itself. Thus we always start the full update |
9614 | * with a CURCNTR write. | |
9615 | * | |
9616 | * On other platforms CURPOS always requires the | |
9617 | * CURBASE write to arm the update. Additonally | |
9618 | * a write to any of the cursor register will cancel | |
9619 | * an already armed cursor update. Thus leaving out | |
9620 | * the CURBASE write after CURPOS could lead to a | |
9621 | * cursor that doesn't appear to move, or even change | |
9622 | * shape. Thus we always write CURBASE. | |
e11ffddb VS |
9623 | * |
9624 | * CURCNTR and CUR_FBC_CTL are always | |
9625 | * armed by the CURBASE write only. | |
9626 | */ | |
9627 | if (plane->cursor.base != base || | |
9628 | plane->cursor.size != fbc_ctl || | |
9629 | plane->cursor.cntl != cntl) { | |
dd584fc0 | 9630 | I915_WRITE_FW(CURCNTR(pipe), cntl); |
e11ffddb VS |
9631 | if (HAS_CUR_FBC(dev_priv)) |
9632 | I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl); | |
b2d03b0d | 9633 | I915_WRITE_FW(CURPOS(pipe), pos); |
75343a44 VS |
9634 | I915_WRITE_FW(CURBASE(pipe), base); |
9635 | ||
e11ffddb VS |
9636 | plane->cursor.base = base; |
9637 | plane->cursor.size = fbc_ctl; | |
9638 | plane->cursor.cntl = cntl; | |
dc41c154 | 9639 | } else { |
e11ffddb | 9640 | I915_WRITE_FW(CURPOS(pipe), pos); |
8753d2bc | 9641 | I915_WRITE_FW(CURBASE(pipe), base); |
dc41c154 VS |
9642 | } |
9643 | ||
dd584fc0 | 9644 | POSTING_READ_FW(CURBASE(pipe)); |
99d1f387 | 9645 | |
b2d03b0d | 9646 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
65a21cd6 JB |
9647 | } |
9648 | ||
b2d03b0d VS |
9649 | static void i9xx_disable_cursor(struct intel_plane *plane, |
9650 | struct intel_crtc *crtc) | |
cda4b7d3 | 9651 | { |
b2d03b0d | 9652 | i9xx_update_cursor(plane, NULL, NULL); |
dc41c154 VS |
9653 | } |
9654 | ||
dc41c154 | 9655 | |
79e53945 | 9656 | /* VESA 640x480x72Hz mode to set on the pipe */ |
bacdcd55 | 9657 | static const struct drm_display_mode load_detect_mode = { |
79e53945 JB |
9658 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
9659 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9660 | }; | |
9661 | ||
a8bb6818 | 9662 | struct drm_framebuffer * |
24dbf51a CW |
9663 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
9664 | struct drm_mode_fb_cmd2 *mode_cmd) | |
d2dff872 CW |
9665 | { |
9666 | struct intel_framebuffer *intel_fb; | |
9667 | int ret; | |
9668 | ||
9669 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 9670 | if (!intel_fb) |
d2dff872 | 9671 | return ERR_PTR(-ENOMEM); |
d2dff872 | 9672 | |
24dbf51a | 9673 | ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); |
dd4916c5 DV |
9674 | if (ret) |
9675 | goto err; | |
d2dff872 CW |
9676 | |
9677 | return &intel_fb->base; | |
dcb1394e | 9678 | |
dd4916c5 | 9679 | err: |
dd4916c5 | 9680 | kfree(intel_fb); |
dd4916c5 | 9681 | return ERR_PTR(ret); |
d2dff872 CW |
9682 | } |
9683 | ||
9684 | static u32 | |
9685 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9686 | { | |
9687 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9688 | return ALIGN(pitch, 64); | |
9689 | } | |
9690 | ||
9691 | static u32 | |
bacdcd55 | 9692 | intel_framebuffer_size_for_mode(const struct drm_display_mode *mode, int bpp) |
d2dff872 CW |
9693 | { |
9694 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9695 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9696 | } |
9697 | ||
9698 | static struct drm_framebuffer * | |
9699 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
bacdcd55 | 9700 | const struct drm_display_mode *mode, |
d2dff872 CW |
9701 | int depth, int bpp) |
9702 | { | |
dcb1394e | 9703 | struct drm_framebuffer *fb; |
d2dff872 | 9704 | struct drm_i915_gem_object *obj; |
0fed39bd | 9705 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 9706 | |
12d79d78 | 9707 | obj = i915_gem_object_create(to_i915(dev), |
d2dff872 | 9708 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
9709 | if (IS_ERR(obj)) |
9710 | return ERR_CAST(obj); | |
d2dff872 CW |
9711 | |
9712 | mode_cmd.width = mode->hdisplay; | |
9713 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9714 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9715 | bpp); | |
5ca0c34a | 9716 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 9717 | |
24dbf51a | 9718 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 9719 | if (IS_ERR(fb)) |
f0cd5182 | 9720 | i915_gem_object_put(obj); |
dcb1394e LW |
9721 | |
9722 | return fb; | |
d2dff872 CW |
9723 | } |
9724 | ||
9725 | static struct drm_framebuffer * | |
9726 | mode_fits_in_fbdev(struct drm_device *dev, | |
bacdcd55 | 9727 | const struct drm_display_mode *mode) |
d2dff872 | 9728 | { |
0695726e | 9729 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 9730 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
9731 | struct drm_i915_gem_object *obj; |
9732 | struct drm_framebuffer *fb; | |
9733 | ||
4c0e5528 | 9734 | if (!dev_priv->fbdev) |
d2dff872 CW |
9735 | return NULL; |
9736 | ||
4c0e5528 | 9737 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9738 | return NULL; |
9739 | ||
4c0e5528 DV |
9740 | obj = dev_priv->fbdev->fb->obj; |
9741 | BUG_ON(!obj); | |
9742 | ||
8bcd4553 | 9743 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 | 9744 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
272725c7 | 9745 | fb->format->cpp[0] * 8)) |
d2dff872 CW |
9746 | return NULL; |
9747 | ||
01f2c773 | 9748 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9749 | return NULL; |
9750 | ||
c3ed1103 | 9751 | drm_framebuffer_get(fb); |
d2dff872 | 9752 | return fb; |
4520f53a DV |
9753 | #else |
9754 | return NULL; | |
9755 | #endif | |
d2dff872 CW |
9756 | } |
9757 | ||
d3a40d1b ACO |
9758 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
9759 | struct drm_crtc *crtc, | |
bacdcd55 | 9760 | const struct drm_display_mode *mode, |
d3a40d1b ACO |
9761 | struct drm_framebuffer *fb, |
9762 | int x, int y) | |
9763 | { | |
9764 | struct drm_plane_state *plane_state; | |
9765 | int hdisplay, vdisplay; | |
9766 | int ret; | |
9767 | ||
9768 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
9769 | if (IS_ERR(plane_state)) | |
9770 | return PTR_ERR(plane_state); | |
9771 | ||
9772 | if (mode) | |
196cd5d3 | 9773 | drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay); |
d3a40d1b ACO |
9774 | else |
9775 | hdisplay = vdisplay = 0; | |
9776 | ||
9777 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
9778 | if (ret) | |
9779 | return ret; | |
9780 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
9781 | plane_state->crtc_x = 0; | |
9782 | plane_state->crtc_y = 0; | |
9783 | plane_state->crtc_w = hdisplay; | |
9784 | plane_state->crtc_h = vdisplay; | |
9785 | plane_state->src_x = x << 16; | |
9786 | plane_state->src_y = y << 16; | |
9787 | plane_state->src_w = hdisplay << 16; | |
9788 | plane_state->src_h = vdisplay << 16; | |
9789 | ||
9790 | return 0; | |
9791 | } | |
9792 | ||
6c5ed5ae | 9793 | int intel_get_load_detect_pipe(struct drm_connector *connector, |
bacdcd55 | 9794 | const struct drm_display_mode *mode, |
6c5ed5ae ML |
9795 | struct intel_load_detect_pipe *old, |
9796 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9797 | { |
9798 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9799 | struct intel_encoder *intel_encoder = |
9800 | intel_attached_encoder(connector); | |
79e53945 | 9801 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9802 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9803 | struct drm_crtc *crtc = NULL; |
9804 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 9805 | struct drm_i915_private *dev_priv = to_i915(dev); |
94352cf9 | 9806 | struct drm_framebuffer *fb; |
51fd371b | 9807 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 9808 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 9809 | struct drm_connector_state *connector_state; |
4be07317 | 9810 | struct intel_crtc_state *crtc_state; |
51fd371b | 9811 | int ret, i = -1; |
79e53945 | 9812 | |
d2dff872 | 9813 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9814 | connector->base.id, connector->name, |
8e329a03 | 9815 | encoder->base.id, encoder->name); |
d2dff872 | 9816 | |
edde3617 ML |
9817 | old->restore_state = NULL; |
9818 | ||
6c5ed5ae | 9819 | WARN_ON(!drm_modeset_is_locked(&config->connection_mutex)); |
6e9f798d | 9820 | |
79e53945 JB |
9821 | /* |
9822 | * Algorithm gets a little messy: | |
7a5e4805 | 9823 | * |
79e53945 JB |
9824 | * - if the connector already has an assigned crtc, use it (but make |
9825 | * sure it's on first) | |
7a5e4805 | 9826 | * |
79e53945 JB |
9827 | * - try to find the first unused crtc that can drive this connector, |
9828 | * and use that if we find one | |
79e53945 JB |
9829 | */ |
9830 | ||
9831 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
9832 | if (connector->state->crtc) { |
9833 | crtc = connector->state->crtc; | |
8261b191 | 9834 | |
51fd371b | 9835 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 9836 | if (ret) |
ad3c558f | 9837 | goto fail; |
8261b191 CW |
9838 | |
9839 | /* Make sure the crtc and connector are running */ | |
edde3617 | 9840 | goto found; |
79e53945 JB |
9841 | } |
9842 | ||
9843 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9844 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9845 | i++; |
9846 | if (!(encoder->possible_crtcs & (1 << i))) | |
9847 | continue; | |
edde3617 ML |
9848 | |
9849 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
9850 | if (ret) | |
9851 | goto fail; | |
9852 | ||
9853 | if (possible_crtc->state->enable) { | |
9854 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 9855 | continue; |
edde3617 | 9856 | } |
a459249c VS |
9857 | |
9858 | crtc = possible_crtc; | |
9859 | break; | |
79e53945 JB |
9860 | } |
9861 | ||
9862 | /* | |
9863 | * If we didn't find an unused CRTC, don't use any. | |
9864 | */ | |
9865 | if (!crtc) { | |
7173188d | 9866 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
f4bf77b4 | 9867 | ret = -ENODEV; |
ad3c558f | 9868 | goto fail; |
79e53945 JB |
9869 | } |
9870 | ||
edde3617 ML |
9871 | found: |
9872 | intel_crtc = to_intel_crtc(crtc); | |
9873 | ||
4d02e2de DV |
9874 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
9875 | if (ret) | |
ad3c558f | 9876 | goto fail; |
79e53945 | 9877 | |
83a57153 | 9878 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
9879 | restore_state = drm_atomic_state_alloc(dev); |
9880 | if (!state || !restore_state) { | |
9881 | ret = -ENOMEM; | |
9882 | goto fail; | |
9883 | } | |
83a57153 ACO |
9884 | |
9885 | state->acquire_ctx = ctx; | |
edde3617 | 9886 | restore_state->acquire_ctx = ctx; |
83a57153 | 9887 | |
944b0c76 ACO |
9888 | connector_state = drm_atomic_get_connector_state(state, connector); |
9889 | if (IS_ERR(connector_state)) { | |
9890 | ret = PTR_ERR(connector_state); | |
9891 | goto fail; | |
9892 | } | |
9893 | ||
edde3617 ML |
9894 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
9895 | if (ret) | |
9896 | goto fail; | |
944b0c76 | 9897 | |
4be07317 ACO |
9898 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9899 | if (IS_ERR(crtc_state)) { | |
9900 | ret = PTR_ERR(crtc_state); | |
9901 | goto fail; | |
9902 | } | |
9903 | ||
49d6fa21 | 9904 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 9905 | |
6492711d CW |
9906 | if (!mode) |
9907 | mode = &load_detect_mode; | |
79e53945 | 9908 | |
d2dff872 CW |
9909 | /* We need a framebuffer large enough to accommodate all accesses |
9910 | * that the plane may generate whilst we perform load detection. | |
9911 | * We can not rely on the fbcon either being present (we get called | |
9912 | * during its initialisation to detect all boot displays, or it may | |
9913 | * not even exist) or that it is large enough to satisfy the | |
9914 | * requested mode. | |
9915 | */ | |
94352cf9 DV |
9916 | fb = mode_fits_in_fbdev(dev, mode); |
9917 | if (fb == NULL) { | |
d2dff872 | 9918 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 9919 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
9920 | } else |
9921 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9922 | if (IS_ERR(fb)) { |
d2dff872 | 9923 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
f4bf77b4 | 9924 | ret = PTR_ERR(fb); |
412b61d8 | 9925 | goto fail; |
79e53945 | 9926 | } |
79e53945 | 9927 | |
d3a40d1b ACO |
9928 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
9929 | if (ret) | |
9930 | goto fail; | |
9931 | ||
c3ed1103 | 9932 | drm_framebuffer_put(fb); |
edde3617 ML |
9933 | |
9934 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
9935 | if (ret) | |
9936 | goto fail; | |
9937 | ||
9938 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
9939 | if (!ret) | |
9940 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
9941 | if (!ret) | |
9942 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
9943 | if (ret) { | |
9944 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
9945 | goto fail; | |
9946 | } | |
8c7b5ccb | 9947 | |
3ba86073 ML |
9948 | ret = drm_atomic_commit(state); |
9949 | if (ret) { | |
6492711d | 9950 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 9951 | goto fail; |
79e53945 | 9952 | } |
edde3617 ML |
9953 | |
9954 | old->restore_state = restore_state; | |
7abbd11f | 9955 | drm_atomic_state_put(state); |
7173188d | 9956 | |
79e53945 | 9957 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 9958 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 9959 | return true; |
412b61d8 | 9960 | |
ad3c558f | 9961 | fail: |
7fb71c8f CW |
9962 | if (state) { |
9963 | drm_atomic_state_put(state); | |
9964 | state = NULL; | |
9965 | } | |
9966 | if (restore_state) { | |
9967 | drm_atomic_state_put(restore_state); | |
9968 | restore_state = NULL; | |
9969 | } | |
83a57153 | 9970 | |
6c5ed5ae ML |
9971 | if (ret == -EDEADLK) |
9972 | return ret; | |
51fd371b | 9973 | |
412b61d8 | 9974 | return false; |
79e53945 JB |
9975 | } |
9976 | ||
d2434ab7 | 9977 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9978 | struct intel_load_detect_pipe *old, |
9979 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9980 | { |
d2434ab7 DV |
9981 | struct intel_encoder *intel_encoder = |
9982 | intel_attached_encoder(connector); | |
4ef69c7a | 9983 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 9984 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 9985 | int ret; |
79e53945 | 9986 | |
d2dff872 | 9987 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9988 | connector->base.id, connector->name, |
8e329a03 | 9989 | encoder->base.id, encoder->name); |
d2dff872 | 9990 | |
edde3617 | 9991 | if (!state) |
0622a53c | 9992 | return; |
79e53945 | 9993 | |
581e49fe | 9994 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
0853695c | 9995 | if (ret) |
edde3617 | 9996 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
0853695c | 9997 | drm_atomic_state_put(state); |
79e53945 JB |
9998 | } |
9999 | ||
da4a1efa | 10000 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10001 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 10002 | { |
fac5e23e | 10003 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
10004 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
10005 | ||
10006 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10007 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 10008 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 10009 | return 120000; |
5db94019 | 10010 | else if (!IS_GEN2(dev_priv)) |
da4a1efa VS |
10011 | return 96000; |
10012 | else | |
10013 | return 48000; | |
10014 | } | |
10015 | ||
79e53945 | 10016 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10017 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10018 | struct intel_crtc_state *pipe_config) |
79e53945 | 10019 | { |
f1f644dc | 10020 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 10021 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 10022 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10023 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 10024 | u32 fp; |
9e2c8475 | 10025 | struct dpll clock; |
dccbea3b | 10026 | int port_clock; |
da4a1efa | 10027 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10028 | |
10029 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10030 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10031 | else |
293623f7 | 10032 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10033 | |
10034 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 10035 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
10036 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
10037 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10038 | } else { |
10039 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10040 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10041 | } | |
10042 | ||
5db94019 | 10043 | if (!IS_GEN2(dev_priv)) { |
9b1e14f4 | 10044 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
10045 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
10046 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10047 | else |
10048 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10049 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10050 | ||
10051 | switch (dpll & DPLL_MODE_MASK) { | |
10052 | case DPLLB_MODE_DAC_SERIAL: | |
10053 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10054 | 5 : 10; | |
10055 | break; | |
10056 | case DPLLB_MODE_LVDS: | |
10057 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10058 | 7 : 14; | |
10059 | break; | |
10060 | default: | |
28c97730 | 10061 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10062 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10063 | return; |
79e53945 JB |
10064 | } |
10065 | ||
9b1e14f4 | 10066 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 10067 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10068 | else |
dccbea3b | 10069 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10070 | } else { |
50a0bc90 | 10071 | u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10072 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10073 | |
10074 | if (is_lvds) { | |
10075 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10076 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10077 | |
10078 | if (lvds & LVDS_CLKB_POWER_UP) | |
10079 | clock.p2 = 7; | |
10080 | else | |
10081 | clock.p2 = 14; | |
79e53945 JB |
10082 | } else { |
10083 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10084 | clock.p1 = 2; | |
10085 | else { | |
10086 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10087 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10088 | } | |
10089 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10090 | clock.p2 = 4; | |
10091 | else | |
10092 | clock.p2 = 2; | |
79e53945 | 10093 | } |
da4a1efa | 10094 | |
dccbea3b | 10095 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10096 | } |
10097 | ||
18442d08 VS |
10098 | /* |
10099 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10100 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10101 | * encoder's get_config() function. |
10102 | */ | |
dccbea3b | 10103 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10104 | } |
10105 | ||
6878da05 VS |
10106 | int intel_dotclock_calculate(int link_freq, |
10107 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10108 | { |
f1f644dc JB |
10109 | /* |
10110 | * The calculation for the data clock is: | |
1041a02f | 10111 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10112 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10113 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10114 | * |
10115 | * and the link clock is simpler: | |
1041a02f | 10116 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10117 | */ |
10118 | ||
6878da05 VS |
10119 | if (!m_n->link_n) |
10120 | return 0; | |
f1f644dc | 10121 | |
3123698f | 10122 | return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); |
6878da05 | 10123 | } |
f1f644dc | 10124 | |
18442d08 | 10125 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10126 | struct intel_crtc_state *pipe_config) |
6878da05 | 10127 | { |
e3b247da | 10128 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10129 | |
18442d08 VS |
10130 | /* read out port_clock from the DPLL */ |
10131 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10132 | |
f1f644dc | 10133 | /* |
e3b247da VS |
10134 | * In case there is an active pipe without active ports, |
10135 | * we may need some idea for the dotclock anyway. | |
10136 | * Calculate one based on the FDI configuration. | |
79e53945 | 10137 | */ |
2d112de7 | 10138 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10139 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10140 | &pipe_config->fdi_m_n); |
79e53945 JB |
10141 | } |
10142 | ||
de330815 VS |
10143 | /* Returns the currently programmed mode of the given encoder. */ |
10144 | struct drm_display_mode * | |
10145 | intel_encoder_current_mode(struct intel_encoder *encoder) | |
79e53945 | 10146 | { |
de330815 VS |
10147 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
10148 | struct intel_crtc_state *crtc_state; | |
79e53945 | 10149 | struct drm_display_mode *mode; |
de330815 VS |
10150 | struct intel_crtc *crtc; |
10151 | enum pipe pipe; | |
10152 | ||
10153 | if (!encoder->get_hw_state(encoder, &pipe)) | |
10154 | return NULL; | |
10155 | ||
10156 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); | |
79e53945 JB |
10157 | |
10158 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10159 | if (!mode) | |
10160 | return NULL; | |
10161 | ||
de330815 VS |
10162 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
10163 | if (!crtc_state) { | |
3f36b937 TU |
10164 | kfree(mode); |
10165 | return NULL; | |
10166 | } | |
10167 | ||
de330815 | 10168 | crtc_state->base.crtc = &crtc->base; |
79e53945 | 10169 | |
de330815 VS |
10170 | if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) { |
10171 | kfree(crtc_state); | |
10172 | kfree(mode); | |
10173 | return NULL; | |
10174 | } | |
79e53945 | 10175 | |
de330815 | 10176 | encoder->get_config(encoder, crtc_state); |
79e53945 | 10177 | |
de330815 | 10178 | intel_mode_from_pipe_config(mode, crtc_state); |
79e53945 | 10179 | |
de330815 | 10180 | kfree(crtc_state); |
3f36b937 | 10181 | |
79e53945 JB |
10182 | return mode; |
10183 | } | |
10184 | ||
10185 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
10186 | { | |
10187 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10188 | ||
10189 | drm_crtc_cleanup(crtc); | |
10190 | kfree(intel_crtc); | |
10191 | } | |
10192 | ||
5a21b665 DV |
10193 | /** |
10194 | * intel_wm_need_update - Check whether watermarks need updating | |
10195 | * @plane: drm plane | |
10196 | * @state: new plane state | |
10197 | * | |
10198 | * Check current plane state versus the new one to determine whether | |
10199 | * watermarks need to be recalculated. | |
10200 | * | |
10201 | * Returns true or false. | |
10202 | */ | |
10203 | static bool intel_wm_need_update(struct drm_plane *plane, | |
10204 | struct drm_plane_state *state) | |
10205 | { | |
10206 | struct intel_plane_state *new = to_intel_plane_state(state); | |
10207 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
10208 | ||
10209 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 10210 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
10211 | return true; |
10212 | ||
10213 | if (!cur->base.fb || !new->base.fb) | |
10214 | return false; | |
10215 | ||
bae781b2 | 10216 | if (cur->base.fb->modifier != new->base.fb->modifier || |
5a21b665 | 10217 | cur->base.rotation != new->base.rotation || |
936e71e3 VS |
10218 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
10219 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
10220 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
10221 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
10222 | return true; |
10223 | ||
10224 | return false; | |
10225 | } | |
10226 | ||
b2b55502 | 10227 | static bool needs_scaling(const struct intel_plane_state *state) |
5a21b665 | 10228 | { |
936e71e3 VS |
10229 | int src_w = drm_rect_width(&state->base.src) >> 16; |
10230 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
10231 | int dst_w = drm_rect_width(&state->base.dst); | |
10232 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
10233 | |
10234 | return (src_w != dst_w || src_h != dst_h); | |
10235 | } | |
d21fbe87 | 10236 | |
b2b55502 VS |
10237 | int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state, |
10238 | struct drm_crtc_state *crtc_state, | |
10239 | const struct intel_plane_state *old_plane_state, | |
da20eabd ML |
10240 | struct drm_plane_state *plane_state) |
10241 | { | |
ab1d3a0e | 10242 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
10243 | struct drm_crtc *crtc = crtc_state->crtc; |
10244 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e9728bd8 | 10245 | struct intel_plane *plane = to_intel_plane(plane_state->plane); |
da20eabd | 10246 | struct drm_device *dev = crtc->dev; |
ed4a6a7c | 10247 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd | 10248 | bool mode_changed = needs_modeset(crtc_state); |
b2b55502 | 10249 | bool was_crtc_enabled = old_crtc_state->base.active; |
da20eabd | 10250 | bool is_crtc_enabled = crtc_state->active; |
da20eabd ML |
10251 | bool turn_off, turn_on, visible, was_visible; |
10252 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 10253 | int ret; |
da20eabd | 10254 | |
e9728bd8 | 10255 | if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { |
da20eabd ML |
10256 | ret = skl_update_scaler_plane( |
10257 | to_intel_crtc_state(crtc_state), | |
10258 | to_intel_plane_state(plane_state)); | |
10259 | if (ret) | |
10260 | return ret; | |
10261 | } | |
10262 | ||
936e71e3 | 10263 | was_visible = old_plane_state->base.visible; |
1d4258db | 10264 | visible = plane_state->visible; |
da20eabd ML |
10265 | |
10266 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
10267 | was_visible = false; | |
10268 | ||
35c08f43 ML |
10269 | /* |
10270 | * Visibility is calculated as if the crtc was on, but | |
10271 | * after scaler setup everything depends on it being off | |
10272 | * when the crtc isn't active. | |
f818ffea VS |
10273 | * |
10274 | * FIXME this is wrong for watermarks. Watermarks should also | |
10275 | * be computed as if the pipe would be active. Perhaps move | |
10276 | * per-plane wm computation to the .check_plane() hook, and | |
10277 | * only combine the results from all planes in the current place? | |
35c08f43 | 10278 | */ |
e9728bd8 | 10279 | if (!is_crtc_enabled) { |
1d4258db | 10280 | plane_state->visible = visible = false; |
e9728bd8 VS |
10281 | to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id); |
10282 | } | |
da20eabd ML |
10283 | |
10284 | if (!was_visible && !visible) | |
10285 | return 0; | |
10286 | ||
e8861675 ML |
10287 | if (fb != old_plane_state->base.fb) |
10288 | pipe_config->fb_changed = true; | |
10289 | ||
da20eabd ML |
10290 | turn_off = was_visible && (!visible || mode_changed); |
10291 | turn_on = visible && (!was_visible || mode_changed); | |
10292 | ||
72660ce0 | 10293 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
e9728bd8 VS |
10294 | intel_crtc->base.base.id, intel_crtc->base.name, |
10295 | plane->base.base.id, plane->base.name, | |
72660ce0 | 10296 | fb ? fb->base.id : -1); |
da20eabd | 10297 | |
72660ce0 | 10298 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
e9728bd8 | 10299 | plane->base.base.id, plane->base.name, |
72660ce0 | 10300 | was_visible, visible, |
da20eabd ML |
10301 | turn_off, turn_on, mode_changed); |
10302 | ||
caed361d | 10303 | if (turn_on) { |
04548cba | 10304 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
b4ede6df | 10305 | pipe_config->update_wm_pre = true; |
caed361d VS |
10306 | |
10307 | /* must disable cxsr around plane enable/disable */ | |
e9728bd8 | 10308 | if (plane->id != PLANE_CURSOR) |
caed361d VS |
10309 | pipe_config->disable_cxsr = true; |
10310 | } else if (turn_off) { | |
04548cba | 10311 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
b4ede6df | 10312 | pipe_config->update_wm_post = true; |
92826fcd | 10313 | |
852eb00d | 10314 | /* must disable cxsr around plane enable/disable */ |
e9728bd8 | 10315 | if (plane->id != PLANE_CURSOR) |
ab1d3a0e | 10316 | pipe_config->disable_cxsr = true; |
e9728bd8 | 10317 | } else if (intel_wm_need_update(&plane->base, plane_state)) { |
04548cba | 10318 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
b4ede6df VS |
10319 | /* FIXME bollocks */ |
10320 | pipe_config->update_wm_pre = true; | |
10321 | pipe_config->update_wm_post = true; | |
10322 | } | |
852eb00d | 10323 | } |
da20eabd | 10324 | |
8be6ca85 | 10325 | if (visible || was_visible) |
e9728bd8 | 10326 | pipe_config->fb_bits |= plane->frontbuffer_bit; |
a9ff8714 | 10327 | |
31ae71fc ML |
10328 | /* |
10329 | * WaCxSRDisabledForSpriteScaling:ivb | |
10330 | * | |
10331 | * cstate->update_wm was already set above, so this flag will | |
10332 | * take effect when we commit and program watermarks. | |
10333 | */ | |
e9728bd8 | 10334 | if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) && |
31ae71fc ML |
10335 | needs_scaling(to_intel_plane_state(plane_state)) && |
10336 | !needs_scaling(old_plane_state)) | |
10337 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 10338 | |
da20eabd ML |
10339 | return 0; |
10340 | } | |
10341 | ||
6d3a1ce7 ML |
10342 | static bool encoders_cloneable(const struct intel_encoder *a, |
10343 | const struct intel_encoder *b) | |
10344 | { | |
10345 | /* masks could be asymmetric, so check both ways */ | |
10346 | return a == b || (a->cloneable & (1 << b->type) && | |
10347 | b->cloneable & (1 << a->type)); | |
10348 | } | |
10349 | ||
10350 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
10351 | struct intel_crtc *crtc, | |
10352 | struct intel_encoder *encoder) | |
10353 | { | |
10354 | struct intel_encoder *source_encoder; | |
10355 | struct drm_connector *connector; | |
10356 | struct drm_connector_state *connector_state; | |
10357 | int i; | |
10358 | ||
aa5e9b47 | 10359 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
6d3a1ce7 ML |
10360 | if (connector_state->crtc != &crtc->base) |
10361 | continue; | |
10362 | ||
10363 | source_encoder = | |
10364 | to_intel_encoder(connector_state->best_encoder); | |
10365 | if (!encoders_cloneable(encoder, source_encoder)) | |
10366 | return false; | |
10367 | } | |
10368 | ||
10369 | return true; | |
10370 | } | |
10371 | ||
6d3a1ce7 ML |
10372 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
10373 | struct drm_crtc_state *crtc_state) | |
10374 | { | |
cf5a15be | 10375 | struct drm_device *dev = crtc->dev; |
fac5e23e | 10376 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 10377 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
10378 | struct intel_crtc_state *pipe_config = |
10379 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 10380 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 10381 | int ret; |
6d3a1ce7 ML |
10382 | bool mode_changed = needs_modeset(crtc_state); |
10383 | ||
852eb00d | 10384 | if (mode_changed && !crtc_state->active) |
caed361d | 10385 | pipe_config->update_wm_post = true; |
eddfcbcd | 10386 | |
ad421372 ML |
10387 | if (mode_changed && crtc_state->enable && |
10388 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 10389 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
10390 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
10391 | pipe_config); | |
10392 | if (ret) | |
10393 | return ret; | |
10394 | } | |
10395 | ||
82cf435b LL |
10396 | if (crtc_state->color_mgmt_changed) { |
10397 | ret = intel_color_check(crtc, crtc_state); | |
10398 | if (ret) | |
10399 | return ret; | |
e7852a4b LL |
10400 | |
10401 | /* | |
10402 | * Changing color management on Intel hardware is | |
10403 | * handled as part of planes update. | |
10404 | */ | |
10405 | crtc_state->planes_changed = true; | |
82cf435b LL |
10406 | } |
10407 | ||
e435d6e5 | 10408 | ret = 0; |
86c8bbbe | 10409 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 10410 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
10411 | if (ret) { |
10412 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
10413 | return ret; | |
10414 | } | |
10415 | } | |
10416 | ||
10417 | if (dev_priv->display.compute_intermediate_wm && | |
10418 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
10419 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
10420 | return 0; | |
10421 | ||
10422 | /* | |
10423 | * Calculate 'intermediate' watermarks that satisfy both the | |
10424 | * old state and the new state. We can program these | |
10425 | * immediately. | |
10426 | */ | |
6315b5d3 | 10427 | ret = dev_priv->display.compute_intermediate_wm(dev, |
ed4a6a7c MR |
10428 | intel_crtc, |
10429 | pipe_config); | |
10430 | if (ret) { | |
10431 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 10432 | return ret; |
ed4a6a7c | 10433 | } |
e3d5457c VS |
10434 | } else if (dev_priv->display.compute_intermediate_wm) { |
10435 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
10436 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
10437 | } |
10438 | ||
6315b5d3 | 10439 | if (INTEL_GEN(dev_priv) >= 9) { |
e435d6e5 ML |
10440 | if (mode_changed) |
10441 | ret = skl_update_scaler_crtc(pipe_config); | |
10442 | ||
73b0ca8e MK |
10443 | if (!ret) |
10444 | ret = skl_check_pipe_max_pixel_rate(intel_crtc, | |
10445 | pipe_config); | |
e435d6e5 | 10446 | if (!ret) |
6ebc6923 | 10447 | ret = intel_atomic_setup_scalers(dev_priv, intel_crtc, |
e435d6e5 ML |
10448 | pipe_config); |
10449 | } | |
10450 | ||
10451 | return ret; | |
6d3a1ce7 ML |
10452 | } |
10453 | ||
65b38e0d | 10454 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
5a21b665 DV |
10455 | .atomic_begin = intel_begin_crtc_commit, |
10456 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 10457 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
10458 | }; |
10459 | ||
d29b2f9d ACO |
10460 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
10461 | { | |
10462 | struct intel_connector *connector; | |
f9e905ca | 10463 | struct drm_connector_list_iter conn_iter; |
d29b2f9d | 10464 | |
f9e905ca DV |
10465 | drm_connector_list_iter_begin(dev, &conn_iter); |
10466 | for_each_intel_connector_iter(connector, &conn_iter) { | |
8863dc7f DV |
10467 | if (connector->base.state->crtc) |
10468 | drm_connector_unreference(&connector->base); | |
10469 | ||
d29b2f9d ACO |
10470 | if (connector->base.encoder) { |
10471 | connector->base.state->best_encoder = | |
10472 | connector->base.encoder; | |
10473 | connector->base.state->crtc = | |
10474 | connector->base.encoder->crtc; | |
8863dc7f DV |
10475 | |
10476 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
10477 | } else { |
10478 | connector->base.state->best_encoder = NULL; | |
10479 | connector->base.state->crtc = NULL; | |
10480 | } | |
10481 | } | |
f9e905ca | 10482 | drm_connector_list_iter_end(&conn_iter); |
d29b2f9d ACO |
10483 | } |
10484 | ||
050f7aeb | 10485 | static void |
eba905b2 | 10486 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 10487 | struct intel_crtc_state *pipe_config) |
050f7aeb | 10488 | { |
6a2a5c5d | 10489 | const struct drm_display_info *info = &connector->base.display_info; |
050f7aeb DV |
10490 | int bpp = pipe_config->pipe_bpp; |
10491 | ||
10492 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
6a2a5c5d VS |
10493 | connector->base.base.id, |
10494 | connector->base.name); | |
050f7aeb DV |
10495 | |
10496 | /* Don't use an invalid EDID bpc value */ | |
6a2a5c5d | 10497 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
050f7aeb | 10498 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
6a2a5c5d VS |
10499 | bpp, info->bpc * 3); |
10500 | pipe_config->pipe_bpp = info->bpc * 3; | |
050f7aeb DV |
10501 | } |
10502 | ||
196f954e | 10503 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
6a2a5c5d | 10504 | if (info->bpc == 0 && bpp > 24) { |
196f954e MK |
10505 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
10506 | bpp); | |
10507 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
10508 | } |
10509 | } | |
10510 | ||
4e53c2e0 | 10511 | static int |
050f7aeb | 10512 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 10513 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 10514 | { |
9beb5fea | 10515 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1486017f | 10516 | struct drm_atomic_state *state; |
da3ced29 ACO |
10517 | struct drm_connector *connector; |
10518 | struct drm_connector_state *connector_state; | |
1486017f | 10519 | int bpp, i; |
4e53c2e0 | 10520 | |
9beb5fea TU |
10521 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
10522 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 10523 | bpp = 10*3; |
9beb5fea | 10524 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
10525 | bpp = 12*3; |
10526 | else | |
10527 | bpp = 8*3; | |
10528 | ||
4e53c2e0 | 10529 | |
4e53c2e0 DV |
10530 | pipe_config->pipe_bpp = bpp; |
10531 | ||
1486017f ACO |
10532 | state = pipe_config->base.state; |
10533 | ||
4e53c2e0 | 10534 | /* Clamp display bpp to EDID value */ |
aa5e9b47 | 10535 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
da3ced29 | 10536 | if (connector_state->crtc != &crtc->base) |
4e53c2e0 DV |
10537 | continue; |
10538 | ||
da3ced29 ACO |
10539 | connected_sink_compute_bpp(to_intel_connector(connector), |
10540 | pipe_config); | |
4e53c2e0 DV |
10541 | } |
10542 | ||
10543 | return bpp; | |
10544 | } | |
10545 | ||
644db711 DV |
10546 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
10547 | { | |
10548 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
10549 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 10550 | mode->crtc_clock, |
644db711 DV |
10551 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
10552 | mode->crtc_hsync_end, mode->crtc_htotal, | |
10553 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
10554 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
10555 | } | |
10556 | ||
f6982332 TU |
10557 | static inline void |
10558 | intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, | |
a4309657 | 10559 | unsigned int lane_count, struct intel_link_m_n *m_n) |
f6982332 | 10560 | { |
a4309657 TU |
10561 | DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10562 | id, lane_count, | |
f6982332 TU |
10563 | m_n->gmch_m, m_n->gmch_n, |
10564 | m_n->link_m, m_n->link_n, m_n->tu); | |
10565 | } | |
10566 | ||
40b2be41 VS |
10567 | #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x |
10568 | ||
10569 | static const char * const output_type_str[] = { | |
10570 | OUTPUT_TYPE(UNUSED), | |
10571 | OUTPUT_TYPE(ANALOG), | |
10572 | OUTPUT_TYPE(DVO), | |
10573 | OUTPUT_TYPE(SDVO), | |
10574 | OUTPUT_TYPE(LVDS), | |
10575 | OUTPUT_TYPE(TVOUT), | |
10576 | OUTPUT_TYPE(HDMI), | |
10577 | OUTPUT_TYPE(DP), | |
10578 | OUTPUT_TYPE(EDP), | |
10579 | OUTPUT_TYPE(DSI), | |
10580 | OUTPUT_TYPE(UNKNOWN), | |
10581 | OUTPUT_TYPE(DP_MST), | |
10582 | }; | |
10583 | ||
10584 | #undef OUTPUT_TYPE | |
10585 | ||
10586 | static void snprintf_output_types(char *buf, size_t len, | |
10587 | unsigned int output_types) | |
10588 | { | |
10589 | char *str = buf; | |
10590 | int i; | |
10591 | ||
10592 | str[0] = '\0'; | |
10593 | ||
10594 | for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { | |
10595 | int r; | |
10596 | ||
10597 | if ((output_types & BIT(i)) == 0) | |
10598 | continue; | |
10599 | ||
10600 | r = snprintf(str, len, "%s%s", | |
10601 | str != buf ? "," : "", output_type_str[i]); | |
10602 | if (r >= len) | |
10603 | break; | |
10604 | str += r; | |
10605 | len -= r; | |
10606 | ||
10607 | output_types &= ~BIT(i); | |
10608 | } | |
10609 | ||
10610 | WARN_ON_ONCE(output_types != 0); | |
10611 | } | |
10612 | ||
c0b03411 | 10613 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10614 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
10615 | const char *context) |
10616 | { | |
6a60cd87 | 10617 | struct drm_device *dev = crtc->base.dev; |
4f8036a2 | 10618 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a60cd87 CK |
10619 | struct drm_plane *plane; |
10620 | struct intel_plane *intel_plane; | |
10621 | struct intel_plane_state *state; | |
10622 | struct drm_framebuffer *fb; | |
40b2be41 | 10623 | char buf[64]; |
6a60cd87 | 10624 | |
66766e4f TU |
10625 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n", |
10626 | crtc->base.base.id, crtc->base.name, context); | |
c0b03411 | 10627 | |
40b2be41 VS |
10628 | snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); |
10629 | DRM_DEBUG_KMS("output_types: %s (0x%x)\n", | |
10630 | buf, pipe_config->output_types); | |
10631 | ||
2c89429e TU |
10632 | DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", |
10633 | transcoder_name(pipe_config->cpu_transcoder), | |
c0b03411 | 10634 | pipe_config->pipe_bpp, pipe_config->dither); |
a4309657 TU |
10635 | |
10636 | if (pipe_config->has_pch_encoder) | |
10637 | intel_dump_m_n_config(pipe_config, "fdi", | |
10638 | pipe_config->fdi_lanes, | |
10639 | &pipe_config->fdi_m_n); | |
f6982332 | 10640 | |
b22ca995 SS |
10641 | if (pipe_config->ycbcr420) |
10642 | DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n"); | |
10643 | ||
f6982332 | 10644 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
a4309657 TU |
10645 | intel_dump_m_n_config(pipe_config, "dp m_n", |
10646 | pipe_config->lane_count, &pipe_config->dp_m_n); | |
d806e682 TU |
10647 | if (pipe_config->has_drrs) |
10648 | intel_dump_m_n_config(pipe_config, "dp m2_n2", | |
10649 | pipe_config->lane_count, | |
10650 | &pipe_config->dp_m2_n2); | |
f6982332 | 10651 | } |
b95af8be | 10652 | |
55072d19 | 10653 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
2c89429e | 10654 | pipe_config->has_audio, pipe_config->has_infoframe); |
55072d19 | 10655 | |
c0b03411 | 10656 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 10657 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 10658 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
10659 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
10660 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
a7d1b3f4 | 10661 | DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n", |
2c89429e | 10662 | pipe_config->port_clock, |
a7d1b3f4 VS |
10663 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
10664 | pipe_config->pixel_rate); | |
dd2f616d TU |
10665 | |
10666 | if (INTEL_GEN(dev_priv) >= 9) | |
10667 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
10668 | crtc->num_scalers, | |
10669 | pipe_config->scaler_state.scaler_users, | |
10670 | pipe_config->scaler_state.scaler_id); | |
a74f8375 TU |
10671 | |
10672 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
10673 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
10674 | pipe_config->gmch_pfit.control, | |
10675 | pipe_config->gmch_pfit.pgm_ratios, | |
10676 | pipe_config->gmch_pfit.lvds_border_bits); | |
10677 | else | |
10678 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", | |
10679 | pipe_config->pch_pfit.pos, | |
10680 | pipe_config->pch_pfit.size, | |
08c4d7fc | 10681 | enableddisabled(pipe_config->pch_pfit.enabled)); |
a74f8375 | 10682 | |
2c89429e TU |
10683 | DRM_DEBUG_KMS("ips: %i, double wide: %i\n", |
10684 | pipe_config->ips_enabled, pipe_config->double_wide); | |
6a60cd87 | 10685 | |
f50b79f0 | 10686 | intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); |
415ff0f6 | 10687 | |
6a60cd87 CK |
10688 | DRM_DEBUG_KMS("planes on this crtc\n"); |
10689 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
b3c11ac2 | 10690 | struct drm_format_name_buf format_name; |
6a60cd87 CK |
10691 | intel_plane = to_intel_plane(plane); |
10692 | if (intel_plane->pipe != crtc->pipe) | |
10693 | continue; | |
10694 | ||
10695 | state = to_intel_plane_state(plane->state); | |
10696 | fb = state->base.fb; | |
10697 | if (!fb) { | |
1d577e02 VS |
10698 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
10699 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
10700 | continue; |
10701 | } | |
10702 | ||
dd2f616d TU |
10703 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n", |
10704 | plane->base.id, plane->name, | |
b3c11ac2 | 10705 | fb->base.id, fb->width, fb->height, |
438b74a5 | 10706 | drm_get_format_name(fb->format->format, &format_name)); |
dd2f616d TU |
10707 | if (INTEL_GEN(dev_priv) >= 9) |
10708 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
10709 | state->scaler_id, | |
10710 | state->base.src.x1 >> 16, | |
10711 | state->base.src.y1 >> 16, | |
10712 | drm_rect_width(&state->base.src) >> 16, | |
10713 | drm_rect_height(&state->base.src) >> 16, | |
10714 | state->base.dst.x1, state->base.dst.y1, | |
10715 | drm_rect_width(&state->base.dst), | |
10716 | drm_rect_height(&state->base.dst)); | |
6a60cd87 | 10717 | } |
c0b03411 DV |
10718 | } |
10719 | ||
5448a00d | 10720 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 10721 | { |
5448a00d | 10722 | struct drm_device *dev = state->dev; |
da3ced29 | 10723 | struct drm_connector *connector; |
2fd96b41 | 10724 | struct drm_connector_list_iter conn_iter; |
00f0b378 | 10725 | unsigned int used_ports = 0; |
477321e0 | 10726 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
10727 | |
10728 | /* | |
10729 | * Walk the connector list instead of the encoder | |
10730 | * list to detect the problem on ddi platforms | |
10731 | * where there's just one encoder per digital port. | |
10732 | */ | |
2fd96b41 GP |
10733 | drm_connector_list_iter_begin(dev, &conn_iter); |
10734 | drm_for_each_connector_iter(connector, &conn_iter) { | |
0bff4858 VS |
10735 | struct drm_connector_state *connector_state; |
10736 | struct intel_encoder *encoder; | |
10737 | ||
10738 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
10739 | if (!connector_state) | |
10740 | connector_state = connector->state; | |
10741 | ||
5448a00d | 10742 | if (!connector_state->best_encoder) |
00f0b378 VS |
10743 | continue; |
10744 | ||
5448a00d ACO |
10745 | encoder = to_intel_encoder(connector_state->best_encoder); |
10746 | ||
10747 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
10748 | |
10749 | switch (encoder->type) { | |
10750 | unsigned int port_mask; | |
10751 | case INTEL_OUTPUT_UNKNOWN: | |
4f8036a2 | 10752 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
00f0b378 | 10753 | break; |
cca0502b | 10754 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
10755 | case INTEL_OUTPUT_HDMI: |
10756 | case INTEL_OUTPUT_EDP: | |
10757 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
10758 | ||
10759 | /* the same port mustn't appear more than once */ | |
10760 | if (used_ports & port_mask) | |
10761 | return false; | |
10762 | ||
10763 | used_ports |= port_mask; | |
477321e0 VS |
10764 | break; |
10765 | case INTEL_OUTPUT_DP_MST: | |
10766 | used_mst_ports |= | |
10767 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
10768 | break; | |
00f0b378 VS |
10769 | default: |
10770 | break; | |
10771 | } | |
10772 | } | |
2fd96b41 | 10773 | drm_connector_list_iter_end(&conn_iter); |
00f0b378 | 10774 | |
477321e0 VS |
10775 | /* can't mix MST and SST/HDMI on the same port */ |
10776 | if (used_ports & used_mst_ports) | |
10777 | return false; | |
10778 | ||
00f0b378 VS |
10779 | return true; |
10780 | } | |
10781 | ||
83a57153 ACO |
10782 | static void |
10783 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
10784 | { | |
ff32c54e VS |
10785 | struct drm_i915_private *dev_priv = |
10786 | to_i915(crtc_state->base.crtc->dev); | |
663a3640 | 10787 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 10788 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 10789 | struct intel_shared_dpll *shared_dpll; |
ff32c54e | 10790 | struct intel_crtc_wm_state wm_state; |
6e644626 | 10791 | bool force_thru, ips_force_disable; |
83a57153 | 10792 | |
7546a384 ACO |
10793 | /* FIXME: before the switch to atomic started, a new pipe_config was |
10794 | * kzalloc'd. Code that depends on any field being zero should be | |
10795 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
10796 | * only fields that are know to not cause problems are preserved. */ | |
10797 | ||
663a3640 | 10798 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
10799 | shared_dpll = crtc_state->shared_dpll; |
10800 | dpll_hw_state = crtc_state->dpll_hw_state; | |
c4e2d043 | 10801 | force_thru = crtc_state->pch_pfit.force_thru; |
6e644626 | 10802 | ips_force_disable = crtc_state->ips_force_disable; |
04548cba VS |
10803 | if (IS_G4X(dev_priv) || |
10804 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
ff32c54e | 10805 | wm_state = crtc_state->wm; |
4978cc93 | 10806 | |
d2fa80a5 CW |
10807 | /* Keep base drm_crtc_state intact, only clear our extended struct */ |
10808 | BUILD_BUG_ON(offsetof(struct intel_crtc_state, base)); | |
10809 | memset(&crtc_state->base + 1, 0, | |
10810 | sizeof(*crtc_state) - sizeof(crtc_state->base)); | |
4978cc93 | 10811 | |
663a3640 | 10812 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
10813 | crtc_state->shared_dpll = shared_dpll; |
10814 | crtc_state->dpll_hw_state = dpll_hw_state; | |
c4e2d043 | 10815 | crtc_state->pch_pfit.force_thru = force_thru; |
6e644626 | 10816 | crtc_state->ips_force_disable = ips_force_disable; |
04548cba VS |
10817 | if (IS_G4X(dev_priv) || |
10818 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
ff32c54e | 10819 | crtc_state->wm = wm_state; |
83a57153 ACO |
10820 | } |
10821 | ||
548ee15b | 10822 | static int |
b8cecdf5 | 10823 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 10824 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 10825 | { |
b359283a | 10826 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 10827 | struct intel_encoder *encoder; |
da3ced29 | 10828 | struct drm_connector *connector; |
0b901879 | 10829 | struct drm_connector_state *connector_state; |
d328c9d7 | 10830 | int base_bpp, ret = -EINVAL; |
0b901879 | 10831 | int i; |
e29c22c0 | 10832 | bool retry = true; |
ee7b9f93 | 10833 | |
83a57153 | 10834 | clear_intel_crtc_state(pipe_config); |
7758a113 | 10835 | |
e143a21c DV |
10836 | pipe_config->cpu_transcoder = |
10837 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 10838 | |
2960bc9c ID |
10839 | /* |
10840 | * Sanitize sync polarity flags based on requested ones. If neither | |
10841 | * positive or negative polarity is requested, treat this as meaning | |
10842 | * negative polarity. | |
10843 | */ | |
2d112de7 | 10844 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10845 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 10846 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 10847 | |
2d112de7 | 10848 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10849 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 10850 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 10851 | |
d328c9d7 DV |
10852 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
10853 | pipe_config); | |
10854 | if (base_bpp < 0) | |
4e53c2e0 DV |
10855 | goto fail; |
10856 | ||
e41a56be VS |
10857 | /* |
10858 | * Determine the real pipe dimensions. Note that stereo modes can | |
10859 | * increase the actual pipe size due to the frame doubling and | |
10860 | * insertion of additional space for blanks between the frame. This | |
10861 | * is stored in the crtc timings. We use the requested mode to do this | |
10862 | * computation to clearly distinguish it from the adjusted mode, which | |
10863 | * can be changed by the connectors in the below retry loop. | |
10864 | */ | |
196cd5d3 | 10865 | drm_mode_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
10866 | &pipe_config->pipe_src_w, |
10867 | &pipe_config->pipe_src_h); | |
e41a56be | 10868 | |
aa5e9b47 | 10869 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
253c84c8 VS |
10870 | if (connector_state->crtc != crtc) |
10871 | continue; | |
10872 | ||
10873 | encoder = to_intel_encoder(connector_state->best_encoder); | |
10874 | ||
e25148d0 VS |
10875 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
10876 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
10877 | goto fail; | |
10878 | } | |
10879 | ||
253c84c8 VS |
10880 | /* |
10881 | * Determine output_types before calling the .compute_config() | |
10882 | * hooks so that the hooks can use this information safely. | |
10883 | */ | |
10884 | pipe_config->output_types |= 1 << encoder->type; | |
10885 | } | |
10886 | ||
e29c22c0 | 10887 | encoder_retry: |
ef1b460d | 10888 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10889 | pipe_config->port_clock = 0; |
ef1b460d | 10890 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10891 | |
135c81b8 | 10892 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
10893 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
10894 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 10895 | |
7758a113 DV |
10896 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10897 | * adjust it according to limitations or connector properties, and also | |
10898 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10899 | */ |
aa5e9b47 | 10900 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 10901 | if (connector_state->crtc != crtc) |
7758a113 | 10902 | continue; |
7ae89233 | 10903 | |
0b901879 ACO |
10904 | encoder = to_intel_encoder(connector_state->best_encoder); |
10905 | ||
0a478c27 | 10906 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
efea6e8e | 10907 | DRM_DEBUG_KMS("Encoder config failure\n"); |
7758a113 DV |
10908 | goto fail; |
10909 | } | |
ee7b9f93 | 10910 | } |
47f1c6c9 | 10911 | |
ff9a6750 DV |
10912 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10913 | * done afterwards in case the encoder adjusts the mode. */ | |
10914 | if (!pipe_config->port_clock) | |
2d112de7 | 10915 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 10916 | * pipe_config->pixel_multiplier; |
ff9a6750 | 10917 | |
a43f6e0f | 10918 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10919 | if (ret < 0) { |
7758a113 DV |
10920 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10921 | goto fail; | |
ee7b9f93 | 10922 | } |
e29c22c0 DV |
10923 | |
10924 | if (ret == RETRY) { | |
10925 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10926 | ret = -EINVAL; | |
10927 | goto fail; | |
10928 | } | |
10929 | ||
10930 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10931 | retry = false; | |
10932 | goto encoder_retry; | |
10933 | } | |
10934 | ||
e8fa4270 | 10935 | /* Dithering seems to not pass-through bits correctly when it should, so |
611032bf MN |
10936 | * only enable it on 6bpc panels and when its not a compliance |
10937 | * test requesting 6bpc video pattern. | |
10938 | */ | |
10939 | pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && | |
10940 | !pipe_config->dither_force_disable; | |
62f0ace5 | 10941 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 10942 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 10943 | |
7758a113 | 10944 | fail: |
548ee15b | 10945 | return ret; |
ee7b9f93 | 10946 | } |
47f1c6c9 | 10947 | |
ea9d758d | 10948 | static void |
4740b0f2 | 10949 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 10950 | { |
0a9ab303 | 10951 | struct drm_crtc *crtc; |
aa5e9b47 | 10952 | struct drm_crtc_state *new_crtc_state; |
8a75d157 | 10953 | int i; |
ea9d758d | 10954 | |
7668851f | 10955 | /* Double check state. */ |
aa5e9b47 ML |
10956 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
10957 | to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state); | |
fc467a22 | 10958 | |
61067a5e ML |
10959 | /* |
10960 | * Update legacy state to satisfy fbc code. This can | |
10961 | * be removed when fbc uses the atomic state. | |
10962 | */ | |
10963 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
10964 | struct drm_plane_state *plane_state = crtc->primary->state; | |
10965 | ||
10966 | crtc->primary->fb = plane_state->fb; | |
10967 | crtc->x = plane_state->src_x >> 16; | |
10968 | crtc->y = plane_state->src_y >> 16; | |
10969 | } | |
ea9d758d | 10970 | } |
ea9d758d DV |
10971 | } |
10972 | ||
3bd26263 | 10973 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 10974 | { |
3bd26263 | 10975 | int diff; |
f1f644dc JB |
10976 | |
10977 | if (clock1 == clock2) | |
10978 | return true; | |
10979 | ||
10980 | if (!clock1 || !clock2) | |
10981 | return false; | |
10982 | ||
10983 | diff = abs(clock1 - clock2); | |
10984 | ||
10985 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
10986 | return true; | |
10987 | ||
10988 | return false; | |
10989 | } | |
10990 | ||
cfb23ed6 ML |
10991 | static bool |
10992 | intel_compare_m_n(unsigned int m, unsigned int n, | |
10993 | unsigned int m2, unsigned int n2, | |
10994 | bool exact) | |
10995 | { | |
10996 | if (m == m2 && n == n2) | |
10997 | return true; | |
10998 | ||
10999 | if (exact || !m || !n || !m2 || !n2) | |
11000 | return false; | |
11001 | ||
11002 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
11003 | ||
31d10b57 ML |
11004 | if (n > n2) { |
11005 | while (n > n2) { | |
cfb23ed6 ML |
11006 | m2 <<= 1; |
11007 | n2 <<= 1; | |
11008 | } | |
31d10b57 ML |
11009 | } else if (n < n2) { |
11010 | while (n < n2) { | |
cfb23ed6 ML |
11011 | m <<= 1; |
11012 | n <<= 1; | |
11013 | } | |
11014 | } | |
11015 | ||
31d10b57 ML |
11016 | if (n != n2) |
11017 | return false; | |
11018 | ||
11019 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
11020 | } |
11021 | ||
11022 | static bool | |
11023 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
11024 | struct intel_link_m_n *m2_n2, | |
11025 | bool adjust) | |
11026 | { | |
11027 | if (m_n->tu == m2_n2->tu && | |
11028 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
11029 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
11030 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
11031 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
11032 | if (adjust) | |
11033 | *m2_n2 = *m_n; | |
11034 | ||
11035 | return true; | |
11036 | } | |
11037 | ||
11038 | return false; | |
11039 | } | |
11040 | ||
4e8048f8 TU |
11041 | static void __printf(3, 4) |
11042 | pipe_config_err(bool adjust, const char *name, const char *format, ...) | |
11043 | { | |
11044 | char *level; | |
11045 | unsigned int category; | |
11046 | struct va_format vaf; | |
11047 | va_list args; | |
11048 | ||
11049 | if (adjust) { | |
11050 | level = KERN_DEBUG; | |
11051 | category = DRM_UT_KMS; | |
11052 | } else { | |
11053 | level = KERN_ERR; | |
11054 | category = DRM_UT_NONE; | |
11055 | } | |
11056 | ||
11057 | va_start(args, format); | |
11058 | vaf.fmt = format; | |
11059 | vaf.va = &args; | |
11060 | ||
11061 | drm_printk(level, category, "mismatch in %s %pV", name, &vaf); | |
11062 | ||
11063 | va_end(args); | |
11064 | } | |
11065 | ||
0e8ffe1b | 11066 | static bool |
6315b5d3 | 11067 | intel_pipe_config_compare(struct drm_i915_private *dev_priv, |
5cec258b | 11068 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
11069 | struct intel_crtc_state *pipe_config, |
11070 | bool adjust) | |
0e8ffe1b | 11071 | { |
cfb23ed6 ML |
11072 | bool ret = true; |
11073 | ||
66e985c0 DV |
11074 | #define PIPE_CONF_CHECK_X(name) \ |
11075 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11076 | pipe_config_err(adjust, __stringify(name), \ |
66e985c0 DV |
11077 | "(expected 0x%08x, found 0x%08x)\n", \ |
11078 | current_config->name, \ | |
11079 | pipe_config->name); \ | |
cfb23ed6 | 11080 | ret = false; \ |
66e985c0 DV |
11081 | } |
11082 | ||
08a24034 DV |
11083 | #define PIPE_CONF_CHECK_I(name) \ |
11084 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11085 | pipe_config_err(adjust, __stringify(name), \ |
08a24034 DV |
11086 | "(expected %i, found %i)\n", \ |
11087 | current_config->name, \ | |
11088 | pipe_config->name); \ | |
cfb23ed6 ML |
11089 | ret = false; \ |
11090 | } | |
11091 | ||
8106ddbd ACO |
11092 | #define PIPE_CONF_CHECK_P(name) \ |
11093 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11094 | pipe_config_err(adjust, __stringify(name), \ |
8106ddbd ACO |
11095 | "(expected %p, found %p)\n", \ |
11096 | current_config->name, \ | |
11097 | pipe_config->name); \ | |
11098 | ret = false; \ | |
11099 | } | |
11100 | ||
cfb23ed6 ML |
11101 | #define PIPE_CONF_CHECK_M_N(name) \ |
11102 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11103 | &pipe_config->name,\ | |
11104 | adjust)) { \ | |
4e8048f8 | 11105 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11106 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11107 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11108 | current_config->name.tu, \ | |
11109 | current_config->name.gmch_m, \ | |
11110 | current_config->name.gmch_n, \ | |
11111 | current_config->name.link_m, \ | |
11112 | current_config->name.link_n, \ | |
11113 | pipe_config->name.tu, \ | |
11114 | pipe_config->name.gmch_m, \ | |
11115 | pipe_config->name.gmch_n, \ | |
11116 | pipe_config->name.link_m, \ | |
11117 | pipe_config->name.link_n); \ | |
11118 | ret = false; \ | |
11119 | } | |
11120 | ||
55c561a7 DV |
11121 | /* This is required for BDW+ where there is only one set of registers for |
11122 | * switching between high and low RR. | |
11123 | * This macro can be used whenever a comparison has to be made between one | |
11124 | * hw state and multiple sw state variables. | |
11125 | */ | |
cfb23ed6 ML |
11126 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
11127 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11128 | &pipe_config->name, adjust) && \ | |
11129 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
11130 | &pipe_config->name, adjust)) { \ | |
4e8048f8 | 11131 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11132 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11133 | "or tu %i gmch %i/%i link %i/%i, " \ | |
11134 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11135 | current_config->name.tu, \ | |
11136 | current_config->name.gmch_m, \ | |
11137 | current_config->name.gmch_n, \ | |
11138 | current_config->name.link_m, \ | |
11139 | current_config->name.link_n, \ | |
11140 | current_config->alt_name.tu, \ | |
11141 | current_config->alt_name.gmch_m, \ | |
11142 | current_config->alt_name.gmch_n, \ | |
11143 | current_config->alt_name.link_m, \ | |
11144 | current_config->alt_name.link_n, \ | |
11145 | pipe_config->name.tu, \ | |
11146 | pipe_config->name.gmch_m, \ | |
11147 | pipe_config->name.gmch_n, \ | |
11148 | pipe_config->name.link_m, \ | |
11149 | pipe_config->name.link_n); \ | |
11150 | ret = false; \ | |
88adfff1 DV |
11151 | } |
11152 | ||
1bd1bd80 DV |
11153 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11154 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
4e8048f8 TU |
11155 | pipe_config_err(adjust, __stringify(name), \ |
11156 | "(%x) (expected %i, found %i)\n", \ | |
11157 | (mask), \ | |
1bd1bd80 DV |
11158 | current_config->name & (mask), \ |
11159 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 11160 | ret = false; \ |
1bd1bd80 DV |
11161 | } |
11162 | ||
5e550656 VS |
11163 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11164 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
4e8048f8 | 11165 | pipe_config_err(adjust, __stringify(name), \ |
5e550656 VS |
11166 | "(expected %i, found %i)\n", \ |
11167 | current_config->name, \ | |
11168 | pipe_config->name); \ | |
cfb23ed6 | 11169 | ret = false; \ |
5e550656 VS |
11170 | } |
11171 | ||
bb760063 DV |
11172 | #define PIPE_CONF_QUIRK(quirk) \ |
11173 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11174 | ||
eccb140b DV |
11175 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11176 | ||
08a24034 DV |
11177 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11178 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 11179 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 11180 | |
90a6b7b0 | 11181 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 11182 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be | 11183 | |
6315b5d3 | 11184 | if (INTEL_GEN(dev_priv) < 8) { |
cfb23ed6 ML |
11185 | PIPE_CONF_CHECK_M_N(dp_m_n); |
11186 | ||
cfb23ed6 ML |
11187 | if (current_config->has_drrs) |
11188 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
11189 | } else | |
11190 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 11191 | |
253c84c8 | 11192 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 11193 | |
2d112de7 ACO |
11194 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11195 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11196 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11197 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11198 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11199 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11200 | |
2d112de7 ACO |
11201 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11202 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11203 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11204 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11205 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11206 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11207 | |
c93f54cf | 11208 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11209 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
772c2a51 | 11210 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 11211 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
b5a9fa09 | 11212 | PIPE_CONF_CHECK_I(limited_color_range); |
15953637 SS |
11213 | |
11214 | PIPE_CONF_CHECK_I(hdmi_scrambling); | |
11215 | PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio); | |
e43823ec | 11216 | PIPE_CONF_CHECK_I(has_infoframe); |
60436fd4 | 11217 | PIPE_CONF_CHECK_I(ycbcr420); |
6c49f241 | 11218 | |
9ed109a7 DV |
11219 | PIPE_CONF_CHECK_I(has_audio); |
11220 | ||
2d112de7 | 11221 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11222 | DRM_MODE_FLAG_INTERLACE); |
11223 | ||
bb760063 | 11224 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11225 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11226 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11227 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11228 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11229 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11230 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11231 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11232 | DRM_MODE_FLAG_NVSYNC); |
11233 | } | |
045ac3b5 | 11234 | |
333b8ca8 | 11235 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a | 11236 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
6315b5d3 | 11237 | if (INTEL_GEN(dev_priv) < 4) |
7f7d8dd6 | 11238 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 11239 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 11240 | |
bfd16b2a ML |
11241 | if (!adjust) { |
11242 | PIPE_CONF_CHECK_I(pipe_src_w); | |
11243 | PIPE_CONF_CHECK_I(pipe_src_h); | |
11244 | ||
11245 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
11246 | if (current_config->pch_pfit.enabled) { | |
11247 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
11248 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
11249 | } | |
2fa2fe9a | 11250 | |
7aefe2b5 | 11251 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
a7d1b3f4 | 11252 | PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); |
7aefe2b5 | 11253 | } |
a1b2278e | 11254 | |
e59150dc | 11255 | /* BDW+ don't expose a synchronous way to read the state */ |
772c2a51 | 11256 | if (IS_HASWELL(dev_priv)) |
e59150dc | 11257 | PIPE_CONF_CHECK_I(ips_enabled); |
42db64ef | 11258 | |
282740f7 VS |
11259 | PIPE_CONF_CHECK_I(double_wide); |
11260 | ||
8106ddbd | 11261 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 11262 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11263 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11264 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11265 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11266 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 11267 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
11268 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11269 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11270 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
2de38138 PZ |
11271 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); |
11272 | PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); | |
11273 | PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); | |
11274 | PIPE_CONF_CHECK_X(dpll_hw_state.pll0); | |
11275 | PIPE_CONF_CHECK_X(dpll_hw_state.pll1); | |
11276 | PIPE_CONF_CHECK_X(dpll_hw_state.pll2); | |
11277 | PIPE_CONF_CHECK_X(dpll_hw_state.pll3); | |
11278 | PIPE_CONF_CHECK_X(dpll_hw_state.pll6); | |
11279 | PIPE_CONF_CHECK_X(dpll_hw_state.pll8); | |
11280 | PIPE_CONF_CHECK_X(dpll_hw_state.pll9); | |
11281 | PIPE_CONF_CHECK_X(dpll_hw_state.pll10); | |
11282 | PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); | |
c0d43d62 | 11283 | |
47eacbab VS |
11284 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
11285 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
11286 | ||
9beb5fea | 11287 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
11288 | PIPE_CONF_CHECK_I(pipe_bpp); |
11289 | ||
2d112de7 | 11290 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11291 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11292 | |
66e985c0 | 11293 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11294 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 11295 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 11296 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11297 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11298 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11299 | |
cfb23ed6 | 11300 | return ret; |
0e8ffe1b DV |
11301 | } |
11302 | ||
e3b247da VS |
11303 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
11304 | const struct intel_crtc_state *pipe_config) | |
11305 | { | |
11306 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 11307 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
11308 | &pipe_config->fdi_m_n); |
11309 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
11310 | ||
11311 | /* | |
11312 | * FDI already provided one idea for the dotclock. | |
11313 | * Yell if the encoder disagrees. | |
11314 | */ | |
11315 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
11316 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
11317 | fdi_dotclock, dotclock); | |
11318 | } | |
11319 | } | |
11320 | ||
c0ead703 ML |
11321 | static void verify_wm_state(struct drm_crtc *crtc, |
11322 | struct drm_crtc_state *new_state) | |
08db6652 | 11323 | { |
6315b5d3 | 11324 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
08db6652 | 11325 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
3de8a14c | 11326 | struct skl_pipe_wm hw_wm, *sw_wm; |
11327 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; | |
11328 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; | |
e7c84544 ML |
11329 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11330 | const enum pipe pipe = intel_crtc->pipe; | |
3de8a14c | 11331 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 11332 | |
6315b5d3 | 11333 | if (INTEL_GEN(dev_priv) < 9 || !new_state->active) |
08db6652 DL |
11334 | return; |
11335 | ||
3de8a14c | 11336 | skl_pipe_wm_get_hw_state(crtc, &hw_wm); |
03af79e0 | 11337 | sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; |
3de8a14c | 11338 | |
08db6652 DL |
11339 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
11340 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11341 | ||
e7c84544 | 11342 | /* planes */ |
8b364b41 | 11343 | for_each_universal_plane(dev_priv, pipe, plane) { |
3de8a14c | 11344 | hw_plane_wm = &hw_wm.planes[plane]; |
11345 | sw_plane_wm = &sw_wm->planes[plane]; | |
08db6652 | 11346 | |
3de8a14c | 11347 | /* Watermarks */ |
11348 | for (level = 0; level <= max_level; level++) { | |
11349 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11350 | &sw_plane_wm->wm[level])) | |
11351 | continue; | |
11352 | ||
11353 | DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11354 | pipe_name(pipe), plane + 1, level, | |
11355 | sw_plane_wm->wm[level].plane_en, | |
11356 | sw_plane_wm->wm[level].plane_res_b, | |
11357 | sw_plane_wm->wm[level].plane_res_l, | |
11358 | hw_plane_wm->wm[level].plane_en, | |
11359 | hw_plane_wm->wm[level].plane_res_b, | |
11360 | hw_plane_wm->wm[level].plane_res_l); | |
11361 | } | |
08db6652 | 11362 | |
3de8a14c | 11363 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
11364 | &sw_plane_wm->trans_wm)) { | |
11365 | DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11366 | pipe_name(pipe), plane + 1, | |
11367 | sw_plane_wm->trans_wm.plane_en, | |
11368 | sw_plane_wm->trans_wm.plane_res_b, | |
11369 | sw_plane_wm->trans_wm.plane_res_l, | |
11370 | hw_plane_wm->trans_wm.plane_en, | |
11371 | hw_plane_wm->trans_wm.plane_res_b, | |
11372 | hw_plane_wm->trans_wm.plane_res_l); | |
11373 | } | |
11374 | ||
11375 | /* DDB */ | |
11376 | hw_ddb_entry = &hw_ddb.plane[pipe][plane]; | |
11377 | sw_ddb_entry = &sw_ddb->plane[pipe][plane]; | |
11378 | ||
11379 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
faccd994 | 11380 | DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", |
3de8a14c | 11381 | pipe_name(pipe), plane + 1, |
11382 | sw_ddb_entry->start, sw_ddb_entry->end, | |
11383 | hw_ddb_entry->start, hw_ddb_entry->end); | |
11384 | } | |
e7c84544 | 11385 | } |
08db6652 | 11386 | |
27082493 L |
11387 | /* |
11388 | * cursor | |
11389 | * If the cursor plane isn't active, we may not have updated it's ddb | |
11390 | * allocation. In that case since the ddb allocation will be updated | |
11391 | * once the plane becomes visible, we can skip this check | |
11392 | */ | |
cd5dcbf1 | 11393 | if (1) { |
3de8a14c | 11394 | hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; |
11395 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; | |
11396 | ||
11397 | /* Watermarks */ | |
11398 | for (level = 0; level <= max_level; level++) { | |
11399 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11400 | &sw_plane_wm->wm[level])) | |
11401 | continue; | |
11402 | ||
11403 | DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11404 | pipe_name(pipe), level, | |
11405 | sw_plane_wm->wm[level].plane_en, | |
11406 | sw_plane_wm->wm[level].plane_res_b, | |
11407 | sw_plane_wm->wm[level].plane_res_l, | |
11408 | hw_plane_wm->wm[level].plane_en, | |
11409 | hw_plane_wm->wm[level].plane_res_b, | |
11410 | hw_plane_wm->wm[level].plane_res_l); | |
11411 | } | |
11412 | ||
11413 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
11414 | &sw_plane_wm->trans_wm)) { | |
11415 | DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11416 | pipe_name(pipe), | |
11417 | sw_plane_wm->trans_wm.plane_en, | |
11418 | sw_plane_wm->trans_wm.plane_res_b, | |
11419 | sw_plane_wm->trans_wm.plane_res_l, | |
11420 | hw_plane_wm->trans_wm.plane_en, | |
11421 | hw_plane_wm->trans_wm.plane_res_b, | |
11422 | hw_plane_wm->trans_wm.plane_res_l); | |
11423 | } | |
11424 | ||
11425 | /* DDB */ | |
11426 | hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
11427 | sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
27082493 | 11428 | |
3de8a14c | 11429 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
faccd994 | 11430 | DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", |
27082493 | 11431 | pipe_name(pipe), |
3de8a14c | 11432 | sw_ddb_entry->start, sw_ddb_entry->end, |
11433 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 11434 | } |
08db6652 DL |
11435 | } |
11436 | } | |
11437 | ||
91d1b4bd | 11438 | static void |
677100ce ML |
11439 | verify_connector_state(struct drm_device *dev, |
11440 | struct drm_atomic_state *state, | |
11441 | struct drm_crtc *crtc) | |
8af6cf88 | 11442 | { |
35dd3c64 | 11443 | struct drm_connector *connector; |
aa5e9b47 | 11444 | struct drm_connector_state *new_conn_state; |
677100ce | 11445 | int i; |
8af6cf88 | 11446 | |
aa5e9b47 | 11447 | for_each_new_connector_in_state(state, connector, new_conn_state, i) { |
35dd3c64 | 11448 | struct drm_encoder *encoder = connector->encoder; |
749d98b8 | 11449 | struct drm_crtc_state *crtc_state = NULL; |
ad3c558f | 11450 | |
aa5e9b47 | 11451 | if (new_conn_state->crtc != crtc) |
e7c84544 ML |
11452 | continue; |
11453 | ||
749d98b8 ML |
11454 | if (crtc) |
11455 | crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); | |
11456 | ||
11457 | intel_connector_verify_state(crtc_state, new_conn_state); | |
8af6cf88 | 11458 | |
aa5e9b47 | 11459 | I915_STATE_WARN(new_conn_state->best_encoder != encoder, |
35dd3c64 | 11460 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 11461 | } |
91d1b4bd DV |
11462 | } |
11463 | ||
11464 | static void | |
86b04268 | 11465 | verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state) |
91d1b4bd DV |
11466 | { |
11467 | struct intel_encoder *encoder; | |
86b04268 DV |
11468 | struct drm_connector *connector; |
11469 | struct drm_connector_state *old_conn_state, *new_conn_state; | |
11470 | int i; | |
8af6cf88 | 11471 | |
b2784e15 | 11472 | for_each_intel_encoder(dev, encoder) { |
86b04268 | 11473 | bool enabled = false, found = false; |
4d20cd86 | 11474 | enum pipe pipe; |
8af6cf88 DV |
11475 | |
11476 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11477 | encoder->base.base.id, | |
8e329a03 | 11478 | encoder->base.name); |
8af6cf88 | 11479 | |
86b04268 DV |
11480 | for_each_oldnew_connector_in_state(state, connector, old_conn_state, |
11481 | new_conn_state, i) { | |
11482 | if (old_conn_state->best_encoder == &encoder->base) | |
11483 | found = true; | |
11484 | ||
11485 | if (new_conn_state->best_encoder != &encoder->base) | |
8af6cf88 | 11486 | continue; |
86b04268 | 11487 | found = enabled = true; |
ad3c558f | 11488 | |
86b04268 | 11489 | I915_STATE_WARN(new_conn_state->crtc != |
ad3c558f ML |
11490 | encoder->base.crtc, |
11491 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 11492 | } |
86b04268 DV |
11493 | |
11494 | if (!found) | |
11495 | continue; | |
0e32b39c | 11496 | |
e2c719b7 | 11497 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11498 | "encoder's enabled state mismatch " |
11499 | "(expected %i, found %i)\n", | |
11500 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
11501 | |
11502 | if (!encoder->base.crtc) { | |
4d20cd86 | 11503 | bool active; |
7c60d198 | 11504 | |
4d20cd86 ML |
11505 | active = encoder->get_hw_state(encoder, &pipe); |
11506 | I915_STATE_WARN(active, | |
11507 | "encoder detached but still enabled on pipe %c.\n", | |
11508 | pipe_name(pipe)); | |
7c60d198 | 11509 | } |
8af6cf88 | 11510 | } |
91d1b4bd DV |
11511 | } |
11512 | ||
11513 | static void | |
c0ead703 ML |
11514 | verify_crtc_state(struct drm_crtc *crtc, |
11515 | struct drm_crtc_state *old_crtc_state, | |
11516 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 11517 | { |
e7c84544 | 11518 | struct drm_device *dev = crtc->dev; |
fac5e23e | 11519 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 11520 | struct intel_encoder *encoder; |
e7c84544 ML |
11521 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11522 | struct intel_crtc_state *pipe_config, *sw_config; | |
11523 | struct drm_atomic_state *old_state; | |
11524 | bool active; | |
045ac3b5 | 11525 | |
e7c84544 | 11526 | old_state = old_crtc_state->state; |
ec2dc6a0 | 11527 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
11528 | pipe_config = to_intel_crtc_state(old_crtc_state); |
11529 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
11530 | pipe_config->base.crtc = crtc; | |
11531 | pipe_config->base.state = old_state; | |
8af6cf88 | 11532 | |
78108b7c | 11533 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 11534 | |
e7c84544 | 11535 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 11536 | |
e56134bc VS |
11537 | /* we keep both pipes enabled on 830 */ |
11538 | if (IS_I830(dev_priv)) | |
e7c84544 | 11539 | active = new_crtc_state->active; |
6c49f241 | 11540 | |
e7c84544 ML |
11541 | I915_STATE_WARN(new_crtc_state->active != active, |
11542 | "crtc active state doesn't match with hw state " | |
11543 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 11544 | |
e7c84544 ML |
11545 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
11546 | "transitional active state does not match atomic hw state " | |
11547 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 11548 | |
e7c84544 ML |
11549 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
11550 | enum pipe pipe; | |
4d20cd86 | 11551 | |
e7c84544 ML |
11552 | active = encoder->get_hw_state(encoder, &pipe); |
11553 | I915_STATE_WARN(active != new_crtc_state->active, | |
11554 | "[ENCODER:%i] active %i with crtc active %i\n", | |
11555 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 11556 | |
e7c84544 ML |
11557 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
11558 | "Encoder connected to wrong pipe %c\n", | |
11559 | pipe_name(pipe)); | |
4d20cd86 | 11560 | |
253c84c8 VS |
11561 | if (active) { |
11562 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 11563 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 11564 | } |
e7c84544 | 11565 | } |
53d9f4e9 | 11566 | |
a7d1b3f4 VS |
11567 | intel_crtc_compute_pixel_rate(pipe_config); |
11568 | ||
e7c84544 ML |
11569 | if (!new_crtc_state->active) |
11570 | return; | |
cfb23ed6 | 11571 | |
e7c84544 | 11572 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 11573 | |
749d98b8 | 11574 | sw_config = to_intel_crtc_state(new_crtc_state); |
6315b5d3 | 11575 | if (!intel_pipe_config_compare(dev_priv, sw_config, |
e7c84544 ML |
11576 | pipe_config, false)) { |
11577 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
11578 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
11579 | "[hw state]"); | |
11580 | intel_dump_pipe_config(intel_crtc, sw_config, | |
11581 | "[sw state]"); | |
8af6cf88 DV |
11582 | } |
11583 | } | |
11584 | ||
91d1b4bd | 11585 | static void |
c0ead703 ML |
11586 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
11587 | struct intel_shared_dpll *pll, | |
11588 | struct drm_crtc *crtc, | |
11589 | struct drm_crtc_state *new_state) | |
91d1b4bd | 11590 | { |
91d1b4bd | 11591 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
11592 | unsigned crtc_mask; |
11593 | bool active; | |
5358901f | 11594 | |
e7c84544 | 11595 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 11596 | |
e7c84544 | 11597 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 11598 | |
e7c84544 | 11599 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 11600 | |
e7c84544 ML |
11601 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
11602 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
11603 | "pll in active use but not on in sw tracking\n"); | |
11604 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
11605 | "pll is on but not used by any active crtc\n"); | |
11606 | I915_STATE_WARN(pll->on != active, | |
11607 | "pll on state mismatch (expected %i, found %i)\n", | |
11608 | pll->on, active); | |
11609 | } | |
5358901f | 11610 | |
e7c84544 | 11611 | if (!crtc) { |
2c42e535 | 11612 | I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask, |
e7c84544 | 11613 | "more active pll users than references: %x vs %x\n", |
2c42e535 | 11614 | pll->active_mask, pll->state.crtc_mask); |
5358901f | 11615 | |
e7c84544 ML |
11616 | return; |
11617 | } | |
11618 | ||
11619 | crtc_mask = 1 << drm_crtc_index(crtc); | |
11620 | ||
11621 | if (new_state->active) | |
11622 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
11623 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
11624 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
11625 | else | |
11626 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
11627 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
11628 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 11629 | |
2c42e535 | 11630 | I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), |
e7c84544 | 11631 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", |
2c42e535 | 11632 | crtc_mask, pll->state.crtc_mask); |
66e985c0 | 11633 | |
2c42e535 | 11634 | I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, |
e7c84544 ML |
11635 | &dpll_hw_state, |
11636 | sizeof(dpll_hw_state)), | |
11637 | "pll hw state mismatch\n"); | |
11638 | } | |
11639 | ||
11640 | static void | |
c0ead703 ML |
11641 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
11642 | struct drm_crtc_state *old_crtc_state, | |
11643 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 11644 | { |
fac5e23e | 11645 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
11646 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
11647 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
11648 | ||
11649 | if (new_state->shared_dpll) | |
c0ead703 | 11650 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
11651 | |
11652 | if (old_state->shared_dpll && | |
11653 | old_state->shared_dpll != new_state->shared_dpll) { | |
11654 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
11655 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
11656 | ||
11657 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
11658 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
11659 | pipe_name(drm_crtc_index(crtc))); | |
2c42e535 | 11660 | I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, |
e7c84544 ML |
11661 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", |
11662 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 11663 | } |
8af6cf88 DV |
11664 | } |
11665 | ||
e7c84544 | 11666 | static void |
c0ead703 | 11667 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
677100ce ML |
11668 | struct drm_atomic_state *state, |
11669 | struct drm_crtc_state *old_state, | |
11670 | struct drm_crtc_state *new_state) | |
e7c84544 | 11671 | { |
5a21b665 DV |
11672 | if (!needs_modeset(new_state) && |
11673 | !to_intel_crtc_state(new_state)->update_pipe) | |
11674 | return; | |
11675 | ||
c0ead703 | 11676 | verify_wm_state(crtc, new_state); |
677100ce | 11677 | verify_connector_state(crtc->dev, state, crtc); |
c0ead703 ML |
11678 | verify_crtc_state(crtc, old_state, new_state); |
11679 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
11680 | } |
11681 | ||
11682 | static void | |
c0ead703 | 11683 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 11684 | { |
fac5e23e | 11685 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
11686 | int i; |
11687 | ||
11688 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 11689 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
11690 | } |
11691 | ||
11692 | static void | |
677100ce ML |
11693 | intel_modeset_verify_disabled(struct drm_device *dev, |
11694 | struct drm_atomic_state *state) | |
e7c84544 | 11695 | { |
86b04268 | 11696 | verify_encoder_state(dev, state); |
677100ce | 11697 | verify_connector_state(dev, state, NULL); |
c0ead703 | 11698 | verify_disabled_dpll_state(dev); |
e7c84544 ML |
11699 | } |
11700 | ||
80715b2f VS |
11701 | static void update_scanline_offset(struct intel_crtc *crtc) |
11702 | { | |
4f8036a2 | 11703 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
80715b2f VS |
11704 | |
11705 | /* | |
11706 | * The scanline counter increments at the leading edge of hsync. | |
11707 | * | |
11708 | * On most platforms it starts counting from vtotal-1 on the | |
11709 | * first active line. That means the scanline counter value is | |
11710 | * always one less than what we would expect. Ie. just after | |
11711 | * start of vblank, which also occurs at start of hsync (on the | |
11712 | * last active line), the scanline counter will read vblank_start-1. | |
11713 | * | |
11714 | * On gen2 the scanline counter starts counting from 1 instead | |
11715 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
11716 | * to keep the value positive), instead of adding one. | |
11717 | * | |
11718 | * On HSW+ the behaviour of the scanline counter depends on the output | |
11719 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
11720 | * there's an extra 1 line difference. So we need to add two instead of | |
11721 | * one to the value. | |
ec1b4ee2 VS |
11722 | * |
11723 | * On VLV/CHV DSI the scanline counter would appear to increment | |
11724 | * approx. 1/3 of a scanline before start of vblank. Unfortunately | |
11725 | * that means we can't tell whether we're in vblank or not while | |
11726 | * we're on that particular line. We must still set scanline_offset | |
11727 | * to 1 so that the vblank timestamps come out correct when we query | |
11728 | * the scanline counter from within the vblank interrupt handler. | |
11729 | * However if queried just before the start of vblank we'll get an | |
11730 | * answer that's slightly in the future. | |
80715b2f | 11731 | */ |
4f8036a2 | 11732 | if (IS_GEN2(dev_priv)) { |
124abe07 | 11733 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
11734 | int vtotal; |
11735 | ||
124abe07 VS |
11736 | vtotal = adjusted_mode->crtc_vtotal; |
11737 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
11738 | vtotal /= 2; |
11739 | ||
11740 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 11741 | } else if (HAS_DDI(dev_priv) && |
2d84d2b3 | 11742 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
11743 | crtc->scanline_offset = 2; |
11744 | } else | |
11745 | crtc->scanline_offset = 1; | |
11746 | } | |
11747 | ||
ad421372 | 11748 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 11749 | { |
225da59b | 11750 | struct drm_device *dev = state->dev; |
ed6739ef | 11751 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9ab303 | 11752 | struct drm_crtc *crtc; |
aa5e9b47 | 11753 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
0a9ab303 | 11754 | int i; |
ed6739ef ACO |
11755 | |
11756 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 11757 | return; |
ed6739ef | 11758 | |
aa5e9b47 | 11759 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
fb1a38a9 | 11760 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd | 11761 | struct intel_shared_dpll *old_dpll = |
aa5e9b47 | 11762 | to_intel_crtc_state(old_crtc_state)->shared_dpll; |
0a9ab303 | 11763 | |
aa5e9b47 | 11764 | if (!needs_modeset(new_crtc_state)) |
225da59b ACO |
11765 | continue; |
11766 | ||
aa5e9b47 | 11767 | to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 11768 | |
8106ddbd | 11769 | if (!old_dpll) |
fb1a38a9 | 11770 | continue; |
0a9ab303 | 11771 | |
a1c414ee | 11772 | intel_release_shared_dpll(old_dpll, intel_crtc, state); |
ad421372 | 11773 | } |
ed6739ef ACO |
11774 | } |
11775 | ||
99d736a2 ML |
11776 | /* |
11777 | * This implements the workaround described in the "notes" section of the mode | |
11778 | * set sequence documentation. When going from no pipes or single pipe to | |
11779 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
11780 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
11781 | */ | |
11782 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
11783 | { | |
11784 | struct drm_crtc_state *crtc_state; | |
11785 | struct intel_crtc *intel_crtc; | |
11786 | struct drm_crtc *crtc; | |
11787 | struct intel_crtc_state *first_crtc_state = NULL; | |
11788 | struct intel_crtc_state *other_crtc_state = NULL; | |
11789 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
11790 | int i; | |
11791 | ||
11792 | /* look at all crtc's that are going to be enabled in during modeset */ | |
aa5e9b47 | 11793 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { |
99d736a2 ML |
11794 | intel_crtc = to_intel_crtc(crtc); |
11795 | ||
11796 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
11797 | continue; | |
11798 | ||
11799 | if (first_crtc_state) { | |
11800 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
11801 | break; | |
11802 | } else { | |
11803 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
11804 | first_pipe = intel_crtc->pipe; | |
11805 | } | |
11806 | } | |
11807 | ||
11808 | /* No workaround needed? */ | |
11809 | if (!first_crtc_state) | |
11810 | return 0; | |
11811 | ||
11812 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
11813 | for_each_intel_crtc(state->dev, intel_crtc) { | |
11814 | struct intel_crtc_state *pipe_config; | |
11815 | ||
11816 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
11817 | if (IS_ERR(pipe_config)) | |
11818 | return PTR_ERR(pipe_config); | |
11819 | ||
11820 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
11821 | ||
11822 | if (!pipe_config->base.active || | |
11823 | needs_modeset(&pipe_config->base)) | |
11824 | continue; | |
11825 | ||
11826 | /* 2 or more enabled crtcs means no need for w/a */ | |
11827 | if (enabled_pipe != INVALID_PIPE) | |
11828 | return 0; | |
11829 | ||
11830 | enabled_pipe = intel_crtc->pipe; | |
11831 | } | |
11832 | ||
11833 | if (enabled_pipe != INVALID_PIPE) | |
11834 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
11835 | else if (other_crtc_state) | |
11836 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
11837 | ||
11838 | return 0; | |
11839 | } | |
11840 | ||
8d96561a VS |
11841 | static int intel_lock_all_pipes(struct drm_atomic_state *state) |
11842 | { | |
11843 | struct drm_crtc *crtc; | |
11844 | ||
11845 | /* Add all pipes to the state */ | |
11846 | for_each_crtc(state->dev, crtc) { | |
11847 | struct drm_crtc_state *crtc_state; | |
11848 | ||
11849 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
11850 | if (IS_ERR(crtc_state)) | |
11851 | return PTR_ERR(crtc_state); | |
11852 | } | |
11853 | ||
11854 | return 0; | |
11855 | } | |
11856 | ||
27c329ed ML |
11857 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
11858 | { | |
11859 | struct drm_crtc *crtc; | |
27c329ed | 11860 | |
8d96561a VS |
11861 | /* |
11862 | * Add all pipes to the state, and force | |
11863 | * a modeset on all the active ones. | |
11864 | */ | |
27c329ed | 11865 | for_each_crtc(state->dev, crtc) { |
9780aad5 VS |
11866 | struct drm_crtc_state *crtc_state; |
11867 | int ret; | |
11868 | ||
27c329ed ML |
11869 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
11870 | if (IS_ERR(crtc_state)) | |
11871 | return PTR_ERR(crtc_state); | |
11872 | ||
11873 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
11874 | continue; | |
11875 | ||
11876 | crtc_state->mode_changed = true; | |
11877 | ||
11878 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
11879 | if (ret) | |
9780aad5 | 11880 | return ret; |
27c329ed ML |
11881 | |
11882 | ret = drm_atomic_add_affected_planes(state, crtc); | |
11883 | if (ret) | |
9780aad5 | 11884 | return ret; |
27c329ed ML |
11885 | } |
11886 | ||
9780aad5 | 11887 | return 0; |
27c329ed ML |
11888 | } |
11889 | ||
c347a676 | 11890 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 11891 | { |
565602d7 | 11892 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 11893 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 | 11894 | struct drm_crtc *crtc; |
aa5e9b47 | 11895 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
565602d7 | 11896 | int ret = 0, i; |
054518dd | 11897 | |
b359283a ML |
11898 | if (!check_digital_port_conflicts(state)) { |
11899 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
11900 | return -EINVAL; | |
11901 | } | |
11902 | ||
565602d7 ML |
11903 | intel_state->modeset = true; |
11904 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
bb0f4aab VS |
11905 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
11906 | intel_state->cdclk.actual = dev_priv->cdclk.actual; | |
565602d7 | 11907 | |
aa5e9b47 ML |
11908 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
11909 | if (new_crtc_state->active) | |
565602d7 ML |
11910 | intel_state->active_crtcs |= 1 << i; |
11911 | else | |
11912 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 | 11913 | |
aa5e9b47 | 11914 | if (old_crtc_state->active != new_crtc_state->active) |
8b4a7d05 | 11915 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); |
565602d7 ML |
11916 | } |
11917 | ||
054518dd ACO |
11918 | /* |
11919 | * See if the config requires any additional preparation, e.g. | |
11920 | * to adjust global state with pipes off. We need to do this | |
11921 | * here so we can get the modeset_pipe updated config for the new | |
11922 | * mode set on this crtc. For other crtcs we need to use the | |
11923 | * adjusted_mode bits in the crtc directly. | |
11924 | */ | |
27c329ed | 11925 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed | 11926 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
11927 | if (ret < 0) |
11928 | return ret; | |
27c329ed | 11929 | |
8d96561a | 11930 | /* |
bb0f4aab | 11931 | * Writes to dev_priv->cdclk.logical must protected by |
8d96561a VS |
11932 | * holding all the crtc locks, even if we don't end up |
11933 | * touching the hardware | |
11934 | */ | |
bb0f4aab VS |
11935 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical, |
11936 | &intel_state->cdclk.logical)) { | |
8d96561a VS |
11937 | ret = intel_lock_all_pipes(state); |
11938 | if (ret < 0) | |
11939 | return ret; | |
11940 | } | |
11941 | ||
11942 | /* All pipes must be switched off while we change the cdclk. */ | |
bb0f4aab VS |
11943 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual, |
11944 | &intel_state->cdclk.actual)) { | |
27c329ed | 11945 | ret = intel_modeset_all_pipes(state); |
8d96561a VS |
11946 | if (ret < 0) |
11947 | return ret; | |
11948 | } | |
e8788cbc | 11949 | |
bb0f4aab VS |
11950 | DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n", |
11951 | intel_state->cdclk.logical.cdclk, | |
11952 | intel_state->cdclk.actual.cdclk); | |
e0ca7a6b | 11953 | } else { |
bb0f4aab | 11954 | to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 11955 | } |
054518dd | 11956 | |
ad421372 | 11957 | intel_modeset_clear_plls(state); |
054518dd | 11958 | |
565602d7 | 11959 | if (IS_HASWELL(dev_priv)) |
ad421372 | 11960 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 11961 | |
ad421372 | 11962 | return 0; |
c347a676 ACO |
11963 | } |
11964 | ||
aa363136 MR |
11965 | /* |
11966 | * Handle calculation of various watermark data at the end of the atomic check | |
11967 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
11968 | * handlers to ensure that all derived state has been updated. | |
11969 | */ | |
55994c2c | 11970 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
11971 | { |
11972 | struct drm_device *dev = state->dev; | |
98d39494 | 11973 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
11974 | |
11975 | /* Is there platform-specific watermark information to calculate? */ | |
11976 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
11977 | return dev_priv->display.compute_global_watermarks(state); |
11978 | ||
11979 | return 0; | |
aa363136 MR |
11980 | } |
11981 | ||
74c090b1 ML |
11982 | /** |
11983 | * intel_atomic_check - validate state object | |
11984 | * @dev: drm device | |
11985 | * @state: state to validate | |
11986 | */ | |
11987 | static int intel_atomic_check(struct drm_device *dev, | |
11988 | struct drm_atomic_state *state) | |
c347a676 | 11989 | { |
dd8b3bdb | 11990 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 11991 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 | 11992 | struct drm_crtc *crtc; |
aa5e9b47 | 11993 | struct drm_crtc_state *old_crtc_state, *crtc_state; |
c347a676 | 11994 | int ret, i; |
61333b60 | 11995 | bool any_ms = false; |
c347a676 | 11996 | |
74c090b1 | 11997 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
11998 | if (ret) |
11999 | return ret; | |
12000 | ||
aa5e9b47 | 12001 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) { |
cfb23ed6 ML |
12002 | struct intel_crtc_state *pipe_config = |
12003 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
12004 | |
12005 | /* Catch I915_MODE_FLAG_INHERITED */ | |
aa5e9b47 | 12006 | if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags) |
1ed51de9 | 12007 | crtc_state->mode_changed = true; |
cfb23ed6 | 12008 | |
af4a879e | 12009 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
12010 | continue; |
12011 | ||
af4a879e DV |
12012 | if (!crtc_state->enable) { |
12013 | any_ms = true; | |
cfb23ed6 | 12014 | continue; |
af4a879e | 12015 | } |
cfb23ed6 | 12016 | |
26495481 DV |
12017 | /* FIXME: For only active_changed we shouldn't need to do any |
12018 | * state recomputation at all. */ | |
12019 | ||
1ed51de9 DV |
12020 | ret = drm_atomic_add_affected_connectors(state, crtc); |
12021 | if (ret) | |
12022 | return ret; | |
b359283a | 12023 | |
cfb23ed6 | 12024 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
12025 | if (ret) { |
12026 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
12027 | pipe_config, "[failed]"); | |
c347a676 | 12028 | return ret; |
25aa1c39 | 12029 | } |
c347a676 | 12030 | |
4f044a88 | 12031 | if (i915_modparams.fastboot && |
6315b5d3 | 12032 | intel_pipe_config_compare(dev_priv, |
aa5e9b47 | 12033 | to_intel_crtc_state(old_crtc_state), |
1ed51de9 | 12034 | pipe_config, true)) { |
26495481 | 12035 | crtc_state->mode_changed = false; |
aa5e9b47 | 12036 | pipe_config->update_pipe = true; |
26495481 DV |
12037 | } |
12038 | ||
af4a879e | 12039 | if (needs_modeset(crtc_state)) |
26495481 | 12040 | any_ms = true; |
cfb23ed6 | 12041 | |
af4a879e DV |
12042 | ret = drm_atomic_add_affected_planes(state, crtc); |
12043 | if (ret) | |
12044 | return ret; | |
61333b60 | 12045 | |
26495481 DV |
12046 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
12047 | needs_modeset(crtc_state) ? | |
12048 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
12049 | } |
12050 | ||
61333b60 ML |
12051 | if (any_ms) { |
12052 | ret = intel_modeset_checks(state); | |
12053 | ||
12054 | if (ret) | |
12055 | return ret; | |
e0ca7a6b | 12056 | } else { |
bb0f4aab | 12057 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 12058 | } |
76305b1a | 12059 | |
dd8b3bdb | 12060 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
12061 | if (ret) |
12062 | return ret; | |
12063 | ||
f51be2e0 | 12064 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 12065 | return calc_watermark_data(state); |
054518dd ACO |
12066 | } |
12067 | ||
5008e874 | 12068 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
d07f0e59 | 12069 | struct drm_atomic_state *state) |
5008e874 | 12070 | { |
fd70075f | 12071 | return drm_atomic_helper_prepare_planes(dev, state); |
5008e874 ML |
12072 | } |
12073 | ||
a2991414 ML |
12074 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
12075 | { | |
12076 | struct drm_device *dev = crtc->base.dev; | |
12077 | ||
12078 | if (!dev->max_vblank_count) | |
ca814b25 | 12079 | return drm_crtc_accurate_vblank_count(&crtc->base); |
a2991414 ML |
12080 | |
12081 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
12082 | } | |
12083 | ||
896e5bb0 L |
12084 | static void intel_update_crtc(struct drm_crtc *crtc, |
12085 | struct drm_atomic_state *state, | |
12086 | struct drm_crtc_state *old_crtc_state, | |
b44d5c0c | 12087 | struct drm_crtc_state *new_crtc_state) |
896e5bb0 L |
12088 | { |
12089 | struct drm_device *dev = crtc->dev; | |
12090 | struct drm_i915_private *dev_priv = to_i915(dev); | |
12091 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
aa5e9b47 ML |
12092 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state); |
12093 | bool modeset = needs_modeset(new_crtc_state); | |
896e5bb0 L |
12094 | |
12095 | if (modeset) { | |
12096 | update_scanline_offset(intel_crtc); | |
12097 | dev_priv->display.crtc_enable(pipe_config, state); | |
12098 | } else { | |
aa5e9b47 ML |
12099 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), |
12100 | pipe_config); | |
896e5bb0 L |
12101 | } |
12102 | ||
12103 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12104 | intel_fbc_enable( | |
12105 | intel_crtc, pipe_config, | |
12106 | to_intel_plane_state(crtc->primary->state)); | |
12107 | } | |
12108 | ||
12109 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
896e5bb0 L |
12110 | } |
12111 | ||
b44d5c0c | 12112 | static void intel_update_crtcs(struct drm_atomic_state *state) |
896e5bb0 L |
12113 | { |
12114 | struct drm_crtc *crtc; | |
aa5e9b47 | 12115 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
896e5bb0 L |
12116 | int i; |
12117 | ||
aa5e9b47 ML |
12118 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
12119 | if (!new_crtc_state->active) | |
896e5bb0 L |
12120 | continue; |
12121 | ||
12122 | intel_update_crtc(crtc, state, old_crtc_state, | |
b44d5c0c | 12123 | new_crtc_state); |
896e5bb0 L |
12124 | } |
12125 | } | |
12126 | ||
b44d5c0c | 12127 | static void skl_update_crtcs(struct drm_atomic_state *state) |
27082493 | 12128 | { |
0f0f74bc | 12129 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
27082493 L |
12130 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
12131 | struct drm_crtc *crtc; | |
ce0ba283 | 12132 | struct intel_crtc *intel_crtc; |
aa5e9b47 | 12133 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
ce0ba283 | 12134 | struct intel_crtc_state *cstate; |
27082493 L |
12135 | unsigned int updated = 0; |
12136 | bool progress; | |
12137 | enum pipe pipe; | |
5eff503b ML |
12138 | int i; |
12139 | ||
12140 | const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; | |
12141 | ||
aa5e9b47 | 12142 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) |
5eff503b | 12143 | /* ignore allocations for crtc's that have been turned off. */ |
aa5e9b47 | 12144 | if (new_crtc_state->active) |
5eff503b | 12145 | entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; |
27082493 L |
12146 | |
12147 | /* | |
12148 | * Whenever the number of active pipes changes, we need to make sure we | |
12149 | * update the pipes in the right order so that their ddb allocations | |
12150 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll | |
12151 | * cause pipe underruns and other bad stuff. | |
12152 | */ | |
12153 | do { | |
27082493 L |
12154 | progress = false; |
12155 | ||
aa5e9b47 | 12156 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
27082493 L |
12157 | bool vbl_wait = false; |
12158 | unsigned int cmask = drm_crtc_mask(crtc); | |
ce0ba283 L |
12159 | |
12160 | intel_crtc = to_intel_crtc(crtc); | |
21794813 | 12161 | cstate = to_intel_crtc_state(new_crtc_state); |
ce0ba283 | 12162 | pipe = intel_crtc->pipe; |
27082493 | 12163 | |
5eff503b | 12164 | if (updated & cmask || !cstate->base.active) |
27082493 | 12165 | continue; |
5eff503b | 12166 | |
2b68504b MK |
12167 | if (skl_ddb_allocation_overlaps(dev_priv, |
12168 | entries, | |
12169 | &cstate->wm.skl.ddb, | |
12170 | i)) | |
27082493 L |
12171 | continue; |
12172 | ||
12173 | updated |= cmask; | |
5eff503b | 12174 | entries[i] = &cstate->wm.skl.ddb; |
27082493 L |
12175 | |
12176 | /* | |
12177 | * If this is an already active pipe, it's DDB changed, | |
12178 | * and this isn't the last pipe that needs updating | |
12179 | * then we need to wait for a vblank to pass for the | |
12180 | * new ddb allocation to take effect. | |
12181 | */ | |
ce0ba283 | 12182 | if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, |
512b5527 | 12183 | &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && |
aa5e9b47 | 12184 | !new_crtc_state->active_changed && |
27082493 L |
12185 | intel_state->wm_results.dirty_pipes != updated) |
12186 | vbl_wait = true; | |
12187 | ||
12188 | intel_update_crtc(crtc, state, old_crtc_state, | |
b44d5c0c | 12189 | new_crtc_state); |
27082493 L |
12190 | |
12191 | if (vbl_wait) | |
0f0f74bc | 12192 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 L |
12193 | |
12194 | progress = true; | |
12195 | } | |
12196 | } while (progress); | |
12197 | } | |
12198 | ||
ba318c61 CW |
12199 | static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) |
12200 | { | |
12201 | struct intel_atomic_state *state, *next; | |
12202 | struct llist_node *freed; | |
12203 | ||
12204 | freed = llist_del_all(&dev_priv->atomic_helper.free_list); | |
12205 | llist_for_each_entry_safe(state, next, freed, freed) | |
12206 | drm_atomic_state_put(&state->base); | |
12207 | } | |
12208 | ||
12209 | static void intel_atomic_helper_free_state_worker(struct work_struct *work) | |
12210 | { | |
12211 | struct drm_i915_private *dev_priv = | |
12212 | container_of(work, typeof(*dev_priv), atomic_helper.free_work); | |
12213 | ||
12214 | intel_atomic_helper_free_state(dev_priv); | |
12215 | } | |
12216 | ||
9db529aa DV |
12217 | static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) |
12218 | { | |
12219 | struct wait_queue_entry wait_fence, wait_reset; | |
12220 | struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); | |
12221 | ||
12222 | init_wait_entry(&wait_fence, 0); | |
12223 | init_wait_entry(&wait_reset, 0); | |
12224 | for (;;) { | |
12225 | prepare_to_wait(&intel_state->commit_ready.wait, | |
12226 | &wait_fence, TASK_UNINTERRUPTIBLE); | |
12227 | prepare_to_wait(&dev_priv->gpu_error.wait_queue, | |
12228 | &wait_reset, TASK_UNINTERRUPTIBLE); | |
12229 | ||
12230 | ||
12231 | if (i915_sw_fence_done(&intel_state->commit_ready) | |
12232 | || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags)) | |
12233 | break; | |
12234 | ||
12235 | schedule(); | |
12236 | } | |
12237 | finish_wait(&intel_state->commit_ready.wait, &wait_fence); | |
12238 | finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset); | |
12239 | } | |
12240 | ||
94f05024 | 12241 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 12242 | { |
94f05024 | 12243 | struct drm_device *dev = state->dev; |
565602d7 | 12244 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 12245 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa5e9b47 | 12246 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
7580d774 | 12247 | struct drm_crtc *crtc; |
5a21b665 | 12248 | struct intel_crtc_state *intel_cstate; |
d8fc70b7 | 12249 | u64 put_domains[I915_MAX_PIPES] = {}; |
e95433c7 | 12250 | int i; |
a6778b3c | 12251 | |
9db529aa | 12252 | intel_atomic_commit_fence_wait(intel_state); |
42b062b0 | 12253 | |
ea0000f0 DV |
12254 | drm_atomic_helper_wait_for_dependencies(state); |
12255 | ||
c3b32658 | 12256 | if (intel_state->modeset) |
5a21b665 | 12257 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
565602d7 | 12258 | |
aa5e9b47 | 12259 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
a539205a ML |
12260 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12261 | ||
aa5e9b47 ML |
12262 | if (needs_modeset(new_crtc_state) || |
12263 | to_intel_crtc_state(new_crtc_state)->update_pipe) { | |
5a21b665 DV |
12264 | |
12265 | put_domains[to_intel_crtc(crtc)->pipe] = | |
12266 | modeset_get_crtc_power_domains(crtc, | |
aa5e9b47 | 12267 | to_intel_crtc_state(new_crtc_state)); |
5a21b665 DV |
12268 | } |
12269 | ||
aa5e9b47 | 12270 | if (!needs_modeset(new_crtc_state)) |
61333b60 ML |
12271 | continue; |
12272 | ||
aa5e9b47 ML |
12273 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), |
12274 | to_intel_crtc_state(new_crtc_state)); | |
460da916 | 12275 | |
29ceb0e6 VS |
12276 | if (old_crtc_state->active) { |
12277 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
4a806558 | 12278 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
eddfcbcd | 12279 | intel_crtc->active = false; |
58f9c0bc | 12280 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 12281 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
12282 | |
12283 | /* | |
12284 | * Underruns don't always raise | |
12285 | * interrupts, so check manually. | |
12286 | */ | |
12287 | intel_check_cpu_fifo_underruns(dev_priv); | |
12288 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 | 12289 | |
21794813 | 12290 | if (!new_crtc_state->active) { |
e62929b3 ML |
12291 | /* |
12292 | * Make sure we don't call initial_watermarks | |
12293 | * for ILK-style watermark updates. | |
ff32c54e VS |
12294 | * |
12295 | * No clue what this is supposed to achieve. | |
e62929b3 | 12296 | */ |
ff32c54e | 12297 | if (INTEL_GEN(dev_priv) >= 9) |
e62929b3 | 12298 | dev_priv->display.initial_watermarks(intel_state, |
21794813 | 12299 | to_intel_crtc_state(new_crtc_state)); |
e62929b3 | 12300 | } |
a539205a | 12301 | } |
b8cecdf5 | 12302 | } |
7758a113 | 12303 | |
ea9d758d DV |
12304 | /* Only after disabling all output pipelines that will be changed can we |
12305 | * update the the output configuration. */ | |
4740b0f2 | 12306 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 12307 | |
565602d7 | 12308 | if (intel_state->modeset) { |
4740b0f2 | 12309 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 | 12310 | |
b0587e4d | 12311 | intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual); |
f6d1973d | 12312 | |
656d1b89 L |
12313 | /* |
12314 | * SKL workaround: bspec recommends we disable the SAGV when we | |
12315 | * have more then one pipe enabled | |
12316 | */ | |
56feca91 | 12317 | if (!intel_can_enable_sagv(state)) |
16dcdc4e | 12318 | intel_disable_sagv(dev_priv); |
656d1b89 | 12319 | |
677100ce | 12320 | intel_modeset_verify_disabled(dev, state); |
4740b0f2 | 12321 | } |
47fab737 | 12322 | |
896e5bb0 | 12323 | /* Complete the events for pipes that have now been disabled */ |
aa5e9b47 ML |
12324 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
12325 | bool modeset = needs_modeset(new_crtc_state); | |
80715b2f | 12326 | |
1f7528c4 | 12327 | /* Complete events for now disable pipes here. */ |
aa5e9b47 | 12328 | if (modeset && !new_crtc_state->active && new_crtc_state->event) { |
1f7528c4 | 12329 | spin_lock_irq(&dev->event_lock); |
aa5e9b47 | 12330 | drm_crtc_send_vblank_event(crtc, new_crtc_state->event); |
1f7528c4 DV |
12331 | spin_unlock_irq(&dev->event_lock); |
12332 | ||
aa5e9b47 | 12333 | new_crtc_state->event = NULL; |
1f7528c4 | 12334 | } |
177246a8 MR |
12335 | } |
12336 | ||
896e5bb0 | 12337 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
b44d5c0c | 12338 | dev_priv->display.update_crtcs(state); |
896e5bb0 | 12339 | |
94f05024 DV |
12340 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
12341 | * already, but still need the state for the delayed optimization. To | |
12342 | * fix this: | |
12343 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
12344 | * - schedule that vblank worker _before_ calling hw_done | |
12345 | * - at the start of commit_tail, cancel it _synchrously | |
12346 | * - switch over to the vblank wait helper in the core after that since | |
12347 | * we don't need out special handling any more. | |
12348 | */ | |
b44d5c0c | 12349 | drm_atomic_helper_wait_for_flip_done(dev, state); |
5a21b665 DV |
12350 | |
12351 | /* | |
12352 | * Now that the vblank has passed, we can go ahead and program the | |
12353 | * optimal watermarks on platforms that need two-step watermark | |
12354 | * programming. | |
12355 | * | |
12356 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
12357 | */ | |
aa5e9b47 ML |
12358 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
12359 | intel_cstate = to_intel_crtc_state(new_crtc_state); | |
5a21b665 DV |
12360 | |
12361 | if (dev_priv->display.optimize_watermarks) | |
ccf010fb ML |
12362 | dev_priv->display.optimize_watermarks(intel_state, |
12363 | intel_cstate); | |
5a21b665 DV |
12364 | } |
12365 | ||
aa5e9b47 | 12366 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
5a21b665 DV |
12367 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); |
12368 | ||
12369 | if (put_domains[i]) | |
12370 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
12371 | ||
aa5e9b47 | 12372 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); |
5a21b665 DV |
12373 | } |
12374 | ||
56feca91 | 12375 | if (intel_state->modeset && intel_can_enable_sagv(state)) |
16dcdc4e | 12376 | intel_enable_sagv(dev_priv); |
656d1b89 | 12377 | |
94f05024 DV |
12378 | drm_atomic_helper_commit_hw_done(state); |
12379 | ||
d5553c09 CW |
12380 | if (intel_state->modeset) { |
12381 | /* As one of the primary mmio accessors, KMS has a high | |
12382 | * likelihood of triggering bugs in unclaimed access. After we | |
12383 | * finish modesetting, see if an error has been flagged, and if | |
12384 | * so enable debugging for the next modeset - and hope we catch | |
12385 | * the culprit. | |
12386 | */ | |
12387 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
5a21b665 | 12388 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); |
d5553c09 | 12389 | } |
5a21b665 | 12390 | |
5a21b665 | 12391 | drm_atomic_helper_cleanup_planes(dev, state); |
5a21b665 | 12392 | |
ea0000f0 DV |
12393 | drm_atomic_helper_commit_cleanup_done(state); |
12394 | ||
0853695c | 12395 | drm_atomic_state_put(state); |
f30da187 | 12396 | |
ba318c61 | 12397 | intel_atomic_helper_free_state(dev_priv); |
94f05024 DV |
12398 | } |
12399 | ||
12400 | static void intel_atomic_commit_work(struct work_struct *work) | |
12401 | { | |
c004a90b CW |
12402 | struct drm_atomic_state *state = |
12403 | container_of(work, struct drm_atomic_state, commit_work); | |
12404 | ||
94f05024 DV |
12405 | intel_atomic_commit_tail(state); |
12406 | } | |
12407 | ||
c004a90b CW |
12408 | static int __i915_sw_fence_call |
12409 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
12410 | enum i915_sw_fence_notify notify) | |
12411 | { | |
12412 | struct intel_atomic_state *state = | |
12413 | container_of(fence, struct intel_atomic_state, commit_ready); | |
12414 | ||
12415 | switch (notify) { | |
12416 | case FENCE_COMPLETE: | |
42b062b0 | 12417 | /* we do blocking waits in the worker, nothing to do here */ |
c004a90b | 12418 | break; |
c004a90b | 12419 | case FENCE_FREE: |
eb955eee CW |
12420 | { |
12421 | struct intel_atomic_helper *helper = | |
12422 | &to_i915(state->base.dev)->atomic_helper; | |
12423 | ||
12424 | if (llist_add(&state->freed, &helper->free_list)) | |
12425 | schedule_work(&helper->free_work); | |
12426 | break; | |
12427 | } | |
c004a90b CW |
12428 | } |
12429 | ||
12430 | return NOTIFY_DONE; | |
12431 | } | |
12432 | ||
6c9c1b38 DV |
12433 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
12434 | { | |
aa5e9b47 | 12435 | struct drm_plane_state *old_plane_state, *new_plane_state; |
6c9c1b38 | 12436 | struct drm_plane *plane; |
6c9c1b38 DV |
12437 | int i; |
12438 | ||
aa5e9b47 | 12439 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) |
faf5bf0a | 12440 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), |
aa5e9b47 | 12441 | intel_fb_obj(new_plane_state->fb), |
faf5bf0a | 12442 | to_intel_plane(plane)->frontbuffer_bit); |
6c9c1b38 DV |
12443 | } |
12444 | ||
94f05024 DV |
12445 | /** |
12446 | * intel_atomic_commit - commit validated state object | |
12447 | * @dev: DRM device | |
12448 | * @state: the top-level driver state object | |
12449 | * @nonblock: nonblocking commit | |
12450 | * | |
12451 | * This function commits a top-level state object that has been validated | |
12452 | * with drm_atomic_helper_check(). | |
12453 | * | |
94f05024 DV |
12454 | * RETURNS |
12455 | * Zero for success or -errno. | |
12456 | */ | |
12457 | static int intel_atomic_commit(struct drm_device *dev, | |
12458 | struct drm_atomic_state *state, | |
12459 | bool nonblock) | |
12460 | { | |
12461 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 12462 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
12463 | int ret = 0; |
12464 | ||
c004a90b CW |
12465 | drm_atomic_state_get(state); |
12466 | i915_sw_fence_init(&intel_state->commit_ready, | |
12467 | intel_atomic_commit_ready); | |
94f05024 | 12468 | |
440df938 VS |
12469 | /* |
12470 | * The intel_legacy_cursor_update() fast path takes care | |
12471 | * of avoiding the vblank waits for simple cursor | |
12472 | * movement and flips. For cursor on/off and size changes, | |
12473 | * we want to perform the vblank waits so that watermark | |
12474 | * updates happen during the correct frames. Gen9+ have | |
12475 | * double buffered watermarks and so shouldn't need this. | |
12476 | * | |
3cf50c63 ML |
12477 | * Unset state->legacy_cursor_update before the call to |
12478 | * drm_atomic_helper_setup_commit() because otherwise | |
12479 | * drm_atomic_helper_wait_for_flip_done() is a noop and | |
12480 | * we get FIFO underruns because we didn't wait | |
12481 | * for vblank. | |
440df938 VS |
12482 | * |
12483 | * FIXME doing watermarks and fb cleanup from a vblank worker | |
12484 | * (assuming we had any) would solve these problems. | |
12485 | */ | |
213f1bd0 ML |
12486 | if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) { |
12487 | struct intel_crtc_state *new_crtc_state; | |
12488 | struct intel_crtc *crtc; | |
12489 | int i; | |
12490 | ||
12491 | for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i) | |
12492 | if (new_crtc_state->wm.need_postvbl_update || | |
12493 | new_crtc_state->update_wm_post) | |
12494 | state->legacy_cursor_update = false; | |
12495 | } | |
440df938 | 12496 | |
3cf50c63 ML |
12497 | ret = intel_atomic_prepare_commit(dev, state); |
12498 | if (ret) { | |
12499 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
12500 | i915_sw_fence_commit(&intel_state->commit_ready); | |
12501 | return ret; | |
12502 | } | |
12503 | ||
12504 | ret = drm_atomic_helper_setup_commit(state, nonblock); | |
12505 | if (!ret) | |
12506 | ret = drm_atomic_helper_swap_state(state, true); | |
440df938 | 12507 | |
0806f4ee ML |
12508 | if (ret) { |
12509 | i915_sw_fence_commit(&intel_state->commit_ready); | |
12510 | ||
0806f4ee | 12511 | drm_atomic_helper_cleanup_planes(dev, state); |
0806f4ee ML |
12512 | return ret; |
12513 | } | |
94f05024 | 12514 | dev_priv->wm.distrust_bios_wm = false; |
3c0fb588 | 12515 | intel_shared_dpll_swap_state(state); |
6c9c1b38 | 12516 | intel_atomic_track_fbs(state); |
94f05024 | 12517 | |
c3b32658 | 12518 | if (intel_state->modeset) { |
d305e061 VS |
12519 | memcpy(dev_priv->min_cdclk, intel_state->min_cdclk, |
12520 | sizeof(intel_state->min_cdclk)); | |
c3b32658 | 12521 | dev_priv->active_crtcs = intel_state->active_crtcs; |
bb0f4aab VS |
12522 | dev_priv->cdclk.logical = intel_state->cdclk.logical; |
12523 | dev_priv->cdclk.actual = intel_state->cdclk.actual; | |
c3b32658 ML |
12524 | } |
12525 | ||
0853695c | 12526 | drm_atomic_state_get(state); |
42b062b0 | 12527 | INIT_WORK(&state->commit_work, intel_atomic_commit_work); |
c004a90b CW |
12528 | |
12529 | i915_sw_fence_commit(&intel_state->commit_ready); | |
42b062b0 DV |
12530 | if (nonblock) |
12531 | queue_work(system_unbound_wq, &state->commit_work); | |
12532 | else | |
94f05024 | 12533 | intel_atomic_commit_tail(state); |
42b062b0 | 12534 | |
75714940 | 12535 | |
74c090b1 | 12536 | return 0; |
7f27126e JB |
12537 | } |
12538 | ||
f6e5b160 | 12539 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
3fab2f09 | 12540 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 12541 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 | 12542 | .destroy = intel_crtc_destroy, |
4c01ded5 | 12543 | .page_flip = drm_atomic_helper_page_flip, |
1356837e MR |
12544 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
12545 | .atomic_destroy_state = intel_crtc_destroy_state, | |
8c6b709d | 12546 | .set_crc_source = intel_crtc_set_crc_source, |
f6e5b160 CW |
12547 | }; |
12548 | ||
74d290f8 CW |
12549 | struct wait_rps_boost { |
12550 | struct wait_queue_entry wait; | |
12551 | ||
12552 | struct drm_crtc *crtc; | |
12553 | struct drm_i915_gem_request *request; | |
12554 | }; | |
12555 | ||
12556 | static int do_rps_boost(struct wait_queue_entry *_wait, | |
12557 | unsigned mode, int sync, void *key) | |
12558 | { | |
12559 | struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait); | |
12560 | struct drm_i915_gem_request *rq = wait->request; | |
12561 | ||
12562 | gen6_rps_boost(rq, NULL); | |
12563 | i915_gem_request_put(rq); | |
12564 | ||
12565 | drm_crtc_vblank_put(wait->crtc); | |
12566 | ||
12567 | list_del(&wait->wait.entry); | |
12568 | kfree(wait); | |
12569 | return 1; | |
12570 | } | |
12571 | ||
12572 | static void add_rps_boost_after_vblank(struct drm_crtc *crtc, | |
12573 | struct dma_fence *fence) | |
12574 | { | |
12575 | struct wait_rps_boost *wait; | |
12576 | ||
12577 | if (!dma_fence_is_i915(fence)) | |
12578 | return; | |
12579 | ||
12580 | if (INTEL_GEN(to_i915(crtc->dev)) < 6) | |
12581 | return; | |
12582 | ||
12583 | if (drm_crtc_vblank_get(crtc)) | |
12584 | return; | |
12585 | ||
12586 | wait = kmalloc(sizeof(*wait), GFP_KERNEL); | |
12587 | if (!wait) { | |
12588 | drm_crtc_vblank_put(crtc); | |
12589 | return; | |
12590 | } | |
12591 | ||
12592 | wait->request = to_request(dma_fence_get(fence)); | |
12593 | wait->crtc = crtc; | |
12594 | ||
12595 | wait->wait.func = do_rps_boost; | |
12596 | wait->wait.flags = 0; | |
12597 | ||
12598 | add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait); | |
12599 | } | |
12600 | ||
6beb8c23 MR |
12601 | /** |
12602 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
12603 | * @plane: drm plane to prepare for | |
12604 | * @fb: framebuffer to prepare for presentation | |
12605 | * | |
12606 | * Prepares a framebuffer for usage on a display plane. Generally this | |
12607 | * involves pinning the underlying object and updating the frontbuffer tracking | |
12608 | * bits. Some older platforms need special physical address handling for | |
12609 | * cursor planes. | |
12610 | * | |
f935675f ML |
12611 | * Must be called with struct_mutex held. |
12612 | * | |
6beb8c23 MR |
12613 | * Returns 0 on success, negative error code on failure. |
12614 | */ | |
12615 | int | |
12616 | intel_prepare_plane_fb(struct drm_plane *plane, | |
1832040d | 12617 | struct drm_plane_state *new_state) |
465c120c | 12618 | { |
c004a90b CW |
12619 | struct intel_atomic_state *intel_state = |
12620 | to_intel_atomic_state(new_state->state); | |
b7f05d4a | 12621 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
844f9111 | 12622 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 12623 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 12624 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c004a90b | 12625 | int ret; |
465c120c | 12626 | |
5008e874 ML |
12627 | if (old_obj) { |
12628 | struct drm_crtc_state *crtc_state = | |
c004a90b CW |
12629 | drm_atomic_get_existing_crtc_state(new_state->state, |
12630 | plane->state->crtc); | |
5008e874 ML |
12631 | |
12632 | /* Big Hammer, we also need to ensure that any pending | |
12633 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
12634 | * current scanout is retired before unpinning the old | |
12635 | * framebuffer. Note that we rely on userspace rendering | |
12636 | * into the buffer attached to the pipe they are waiting | |
12637 | * on. If not, userspace generates a GPU hang with IPEHR | |
12638 | * point to the MI_WAIT_FOR_EVENT. | |
12639 | * | |
12640 | * This should only fail upon a hung GPU, in which case we | |
12641 | * can safely continue. | |
12642 | */ | |
c004a90b CW |
12643 | if (needs_modeset(crtc_state)) { |
12644 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
12645 | old_obj->resv, NULL, | |
12646 | false, 0, | |
12647 | GFP_KERNEL); | |
12648 | if (ret < 0) | |
12649 | return ret; | |
f4457ae7 | 12650 | } |
5008e874 ML |
12651 | } |
12652 | ||
c004a90b CW |
12653 | if (new_state->fence) { /* explicit fencing */ |
12654 | ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, | |
12655 | new_state->fence, | |
12656 | I915_FENCE_TIMEOUT, | |
12657 | GFP_KERNEL); | |
12658 | if (ret < 0) | |
12659 | return ret; | |
12660 | } | |
12661 | ||
c37efb99 CW |
12662 | if (!obj) |
12663 | return 0; | |
12664 | ||
4d3088c7 | 12665 | ret = i915_gem_object_pin_pages(obj); |
fd70075f CW |
12666 | if (ret) |
12667 | return ret; | |
12668 | ||
4d3088c7 CW |
12669 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
12670 | if (ret) { | |
12671 | i915_gem_object_unpin_pages(obj); | |
12672 | return ret; | |
12673 | } | |
12674 | ||
fd70075f CW |
12675 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
12676 | INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
12677 | const int align = intel_cursor_alignment(dev_priv); | |
12678 | ||
12679 | ret = i915_gem_object_attach_phys(obj, align); | |
12680 | } else { | |
12681 | struct i915_vma *vma; | |
12682 | ||
12683 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
12684 | if (!IS_ERR(vma)) | |
12685 | to_intel_plane_state(new_state)->vma = vma; | |
12686 | else | |
12687 | ret = PTR_ERR(vma); | |
12688 | } | |
12689 | ||
12690 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); | |
12691 | ||
12692 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4d3088c7 | 12693 | i915_gem_object_unpin_pages(obj); |
fd70075f CW |
12694 | if (ret) |
12695 | return ret; | |
12696 | ||
c004a90b | 12697 | if (!new_state->fence) { /* implicit fencing */ |
74d290f8 CW |
12698 | struct dma_fence *fence; |
12699 | ||
c004a90b CW |
12700 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, |
12701 | obj->resv, NULL, | |
12702 | false, I915_FENCE_TIMEOUT, | |
12703 | GFP_KERNEL); | |
12704 | if (ret < 0) | |
12705 | return ret; | |
74d290f8 CW |
12706 | |
12707 | fence = reservation_object_get_excl_rcu(obj->resv); | |
12708 | if (fence) { | |
12709 | add_rps_boost_after_vblank(new_state->crtc, fence); | |
12710 | dma_fence_put(fence); | |
12711 | } | |
12712 | } else { | |
12713 | add_rps_boost_after_vblank(new_state->crtc, new_state->fence); | |
c004a90b | 12714 | } |
5a21b665 | 12715 | |
d07f0e59 | 12716 | return 0; |
6beb8c23 MR |
12717 | } |
12718 | ||
38f3ce3a MR |
12719 | /** |
12720 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
12721 | * @plane: drm plane to clean up for | |
12722 | * @fb: old framebuffer that was on plane | |
12723 | * | |
12724 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
12725 | * |
12726 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
12727 | */ |
12728 | void | |
12729 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
1832040d | 12730 | struct drm_plane_state *old_state) |
38f3ce3a | 12731 | { |
be1e3415 | 12732 | struct i915_vma *vma; |
38f3ce3a | 12733 | |
be1e3415 CW |
12734 | /* Should only be called after a successful intel_prepare_plane_fb()! */ |
12735 | vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma); | |
fd70075f CW |
12736 | if (vma) { |
12737 | mutex_lock(&plane->dev->struct_mutex); | |
be1e3415 | 12738 | intel_unpin_fb_vma(vma); |
fd70075f CW |
12739 | mutex_unlock(&plane->dev->struct_mutex); |
12740 | } | |
465c120c MR |
12741 | } |
12742 | ||
6156a456 CK |
12743 | int |
12744 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
12745 | { | |
5b7280f0 | 12746 | struct drm_i915_private *dev_priv; |
6156a456 | 12747 | int max_scale; |
5b7280f0 | 12748 | int crtc_clock, max_dotclk; |
6156a456 | 12749 | |
bf8a0af0 | 12750 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
12751 | return DRM_PLANE_HELPER_NO_SCALING; |
12752 | ||
5b7280f0 ACO |
12753 | dev_priv = to_i915(intel_crtc->base.dev); |
12754 | ||
6156a456 | 12755 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
5b7280f0 ACO |
12756 | max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk; |
12757 | ||
12758 | if (IS_GEMINILAKE(dev_priv)) | |
12759 | max_dotclk *= 2; | |
6156a456 | 12760 | |
5b7280f0 | 12761 | if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)) |
6156a456 CK |
12762 | return DRM_PLANE_HELPER_NO_SCALING; |
12763 | ||
12764 | /* | |
12765 | * skl max scale is lower of: | |
12766 | * close to 3 but not 3, -1 is for that purpose | |
12767 | * or | |
12768 | * cdclk/crtc_clock | |
12769 | */ | |
5b7280f0 ACO |
12770 | max_scale = min((1 << 16) * 3 - 1, |
12771 | (1 << 8) * ((max_dotclk << 8) / crtc_clock)); | |
6156a456 CK |
12772 | |
12773 | return max_scale; | |
12774 | } | |
12775 | ||
465c120c | 12776 | static int |
282dbf9b | 12777 | intel_check_primary_plane(struct intel_plane *plane, |
061e4b8d | 12778 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
12779 | struct intel_plane_state *state) |
12780 | { | |
282dbf9b | 12781 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
2b875c22 | 12782 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 12783 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
12784 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
12785 | bool can_position = false; | |
b63a16f6 | 12786 | int ret; |
465c120c | 12787 | |
b63a16f6 | 12788 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
12789 | /* use scaler when colorkey is not required */ |
12790 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
12791 | min_scale = 1; | |
12792 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
12793 | } | |
d8106366 | 12794 | can_position = true; |
6156a456 | 12795 | } |
d8106366 | 12796 | |
cc926387 DV |
12797 | ret = drm_plane_helper_check_state(&state->base, |
12798 | &state->clip, | |
12799 | min_scale, max_scale, | |
12800 | can_position, true); | |
b63a16f6 VS |
12801 | if (ret) |
12802 | return ret; | |
12803 | ||
cc926387 | 12804 | if (!state->base.fb) |
b63a16f6 VS |
12805 | return 0; |
12806 | ||
12807 | if (INTEL_GEN(dev_priv) >= 9) { | |
12808 | ret = skl_check_plane_surface(state); | |
12809 | if (ret) | |
12810 | return ret; | |
a0864d59 VS |
12811 | |
12812 | state->ctl = skl_plane_ctl(crtc_state, state); | |
12813 | } else { | |
5b7fcc44 VS |
12814 | ret = i9xx_check_plane_surface(state); |
12815 | if (ret) | |
12816 | return ret; | |
12817 | ||
a0864d59 | 12818 | state->ctl = i9xx_plane_ctl(crtc_state, state); |
b63a16f6 VS |
12819 | } |
12820 | ||
12821 | return 0; | |
14af293f GP |
12822 | } |
12823 | ||
5a21b665 DV |
12824 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
12825 | struct drm_crtc_state *old_crtc_state) | |
12826 | { | |
12827 | struct drm_device *dev = crtc->dev; | |
62e0fb88 | 12828 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 12829 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ccf010fb | 12830 | struct intel_crtc_state *old_intel_cstate = |
5a21b665 | 12831 | to_intel_crtc_state(old_crtc_state); |
ccf010fb ML |
12832 | struct intel_atomic_state *old_intel_state = |
12833 | to_intel_atomic_state(old_crtc_state->state); | |
d3a8fb32 VS |
12834 | struct intel_crtc_state *intel_cstate = |
12835 | intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc); | |
12836 | bool modeset = needs_modeset(&intel_cstate->base); | |
5a21b665 | 12837 | |
567f0792 ML |
12838 | if (!modeset && |
12839 | (intel_cstate->base.color_mgmt_changed || | |
12840 | intel_cstate->update_pipe)) { | |
5c857e60 VS |
12841 | intel_color_set_csc(&intel_cstate->base); |
12842 | intel_color_load_luts(&intel_cstate->base); | |
567f0792 ML |
12843 | } |
12844 | ||
5a21b665 | 12845 | /* Perform vblank evasion around commit operation */ |
d3a8fb32 | 12846 | intel_pipe_update_start(intel_cstate); |
5a21b665 DV |
12847 | |
12848 | if (modeset) | |
e62929b3 | 12849 | goto out; |
5a21b665 | 12850 | |
ccf010fb | 12851 | if (intel_cstate->update_pipe) |
1a15b77b | 12852 | intel_update_pipe_config(old_intel_cstate, intel_cstate); |
ccf010fb | 12853 | else if (INTEL_GEN(dev_priv) >= 9) |
5a21b665 | 12854 | skl_detach_scalers(intel_crtc); |
62e0fb88 | 12855 | |
e62929b3 | 12856 | out: |
ccf010fb ML |
12857 | if (dev_priv->display.atomic_update_watermarks) |
12858 | dev_priv->display.atomic_update_watermarks(old_intel_state, | |
12859 | intel_cstate); | |
5a21b665 DV |
12860 | } |
12861 | ||
12862 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
12863 | struct drm_crtc_state *old_crtc_state) | |
12864 | { | |
12865 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d3a8fb32 VS |
12866 | struct intel_atomic_state *old_intel_state = |
12867 | to_intel_atomic_state(old_crtc_state->state); | |
12868 | struct intel_crtc_state *new_crtc_state = | |
12869 | intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc); | |
5a21b665 | 12870 | |
d3a8fb32 | 12871 | intel_pipe_update_end(new_crtc_state); |
5a21b665 DV |
12872 | } |
12873 | ||
cf4c7c12 | 12874 | /** |
4a3b8769 MR |
12875 | * intel_plane_destroy - destroy a plane |
12876 | * @plane: plane to destroy | |
cf4c7c12 | 12877 | * |
4a3b8769 MR |
12878 | * Common destruction function for all types of planes (primary, cursor, |
12879 | * sprite). | |
cf4c7c12 | 12880 | */ |
4a3b8769 | 12881 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 12882 | { |
465c120c | 12883 | drm_plane_cleanup(plane); |
69ae561f | 12884 | kfree(to_intel_plane(plane)); |
465c120c MR |
12885 | } |
12886 | ||
714244e2 BW |
12887 | static bool i8xx_mod_supported(uint32_t format, uint64_t modifier) |
12888 | { | |
12889 | switch (format) { | |
12890 | case DRM_FORMAT_C8: | |
12891 | case DRM_FORMAT_RGB565: | |
12892 | case DRM_FORMAT_XRGB1555: | |
12893 | case DRM_FORMAT_XRGB8888: | |
12894 | return modifier == DRM_FORMAT_MOD_LINEAR || | |
12895 | modifier == I915_FORMAT_MOD_X_TILED; | |
12896 | default: | |
12897 | return false; | |
12898 | } | |
12899 | } | |
12900 | ||
12901 | static bool i965_mod_supported(uint32_t format, uint64_t modifier) | |
12902 | { | |
12903 | switch (format) { | |
12904 | case DRM_FORMAT_C8: | |
12905 | case DRM_FORMAT_RGB565: | |
12906 | case DRM_FORMAT_XRGB8888: | |
12907 | case DRM_FORMAT_XBGR8888: | |
12908 | case DRM_FORMAT_XRGB2101010: | |
12909 | case DRM_FORMAT_XBGR2101010: | |
12910 | return modifier == DRM_FORMAT_MOD_LINEAR || | |
12911 | modifier == I915_FORMAT_MOD_X_TILED; | |
12912 | default: | |
12913 | return false; | |
12914 | } | |
12915 | } | |
12916 | ||
12917 | static bool skl_mod_supported(uint32_t format, uint64_t modifier) | |
12918 | { | |
12919 | switch (format) { | |
12920 | case DRM_FORMAT_XRGB8888: | |
12921 | case DRM_FORMAT_XBGR8888: | |
12922 | case DRM_FORMAT_ARGB8888: | |
12923 | case DRM_FORMAT_ABGR8888: | |
12924 | if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS || | |
12925 | modifier == I915_FORMAT_MOD_Y_TILED_CCS) | |
12926 | return true; | |
12927 | /* fall through */ | |
12928 | case DRM_FORMAT_RGB565: | |
12929 | case DRM_FORMAT_XRGB2101010: | |
12930 | case DRM_FORMAT_XBGR2101010: | |
12931 | case DRM_FORMAT_YUYV: | |
12932 | case DRM_FORMAT_YVYU: | |
12933 | case DRM_FORMAT_UYVY: | |
12934 | case DRM_FORMAT_VYUY: | |
12935 | if (modifier == I915_FORMAT_MOD_Yf_TILED) | |
12936 | return true; | |
12937 | /* fall through */ | |
12938 | case DRM_FORMAT_C8: | |
12939 | if (modifier == DRM_FORMAT_MOD_LINEAR || | |
12940 | modifier == I915_FORMAT_MOD_X_TILED || | |
12941 | modifier == I915_FORMAT_MOD_Y_TILED) | |
12942 | return true; | |
12943 | /* fall through */ | |
12944 | default: | |
12945 | return false; | |
12946 | } | |
12947 | } | |
12948 | ||
12949 | static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane, | |
12950 | uint32_t format, | |
12951 | uint64_t modifier) | |
12952 | { | |
12953 | struct drm_i915_private *dev_priv = to_i915(plane->dev); | |
12954 | ||
12955 | if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) | |
12956 | return false; | |
12957 | ||
12958 | if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL && | |
12959 | modifier != DRM_FORMAT_MOD_LINEAR) | |
12960 | return false; | |
12961 | ||
12962 | if (INTEL_GEN(dev_priv) >= 9) | |
12963 | return skl_mod_supported(format, modifier); | |
12964 | else if (INTEL_GEN(dev_priv) >= 4) | |
12965 | return i965_mod_supported(format, modifier); | |
12966 | else | |
12967 | return i8xx_mod_supported(format, modifier); | |
12968 | ||
12969 | unreachable(); | |
12970 | } | |
12971 | ||
12972 | static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane, | |
12973 | uint32_t format, | |
12974 | uint64_t modifier) | |
12975 | { | |
12976 | if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) | |
12977 | return false; | |
12978 | ||
12979 | return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888; | |
12980 | } | |
12981 | ||
12982 | static struct drm_plane_funcs intel_plane_funcs = { | |
70a101f8 MR |
12983 | .update_plane = drm_atomic_helper_update_plane, |
12984 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 12985 | .destroy = intel_plane_destroy, |
a98b3431 MR |
12986 | .atomic_get_property = intel_plane_atomic_get_property, |
12987 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
12988 | .atomic_duplicate_state = intel_plane_duplicate_state, |
12989 | .atomic_destroy_state = intel_plane_destroy_state, | |
714244e2 | 12990 | .format_mod_supported = intel_primary_plane_format_mod_supported, |
465c120c MR |
12991 | }; |
12992 | ||
f79f2692 ML |
12993 | static int |
12994 | intel_legacy_cursor_update(struct drm_plane *plane, | |
12995 | struct drm_crtc *crtc, | |
12996 | struct drm_framebuffer *fb, | |
12997 | int crtc_x, int crtc_y, | |
12998 | unsigned int crtc_w, unsigned int crtc_h, | |
12999 | uint32_t src_x, uint32_t src_y, | |
34a2ab5e DV |
13000 | uint32_t src_w, uint32_t src_h, |
13001 | struct drm_modeset_acquire_ctx *ctx) | |
f79f2692 ML |
13002 | { |
13003 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
13004 | int ret; | |
13005 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
13006 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13007 | struct drm_framebuffer *old_fb; | |
13008 | struct drm_crtc_state *crtc_state = crtc->state; | |
fd70075f | 13009 | struct i915_vma *old_vma, *vma; |
f79f2692 ML |
13010 | |
13011 | /* | |
13012 | * When crtc is inactive or there is a modeset pending, | |
13013 | * wait for it to complete in the slowpath | |
13014 | */ | |
13015 | if (!crtc_state->active || needs_modeset(crtc_state) || | |
13016 | to_intel_crtc_state(crtc_state)->update_pipe) | |
13017 | goto slow; | |
13018 | ||
13019 | old_plane_state = plane->state; | |
669c9215 ML |
13020 | /* |
13021 | * Don't do an async update if there is an outstanding commit modifying | |
13022 | * the plane. This prevents our async update's changes from getting | |
13023 | * overridden by a previous synchronous update's state. | |
13024 | */ | |
13025 | if (old_plane_state->commit && | |
13026 | !try_wait_for_completion(&old_plane_state->commit->hw_done)) | |
13027 | goto slow; | |
f79f2692 ML |
13028 | |
13029 | /* | |
13030 | * If any parameters change that may affect watermarks, | |
13031 | * take the slowpath. Only changing fb or position should be | |
13032 | * in the fastpath. | |
13033 | */ | |
13034 | if (old_plane_state->crtc != crtc || | |
13035 | old_plane_state->src_w != src_w || | |
13036 | old_plane_state->src_h != src_h || | |
13037 | old_plane_state->crtc_w != crtc_w || | |
13038 | old_plane_state->crtc_h != crtc_h || | |
a5509abd | 13039 | !old_plane_state->fb != !fb) |
f79f2692 ML |
13040 | goto slow; |
13041 | ||
13042 | new_plane_state = intel_plane_duplicate_state(plane); | |
13043 | if (!new_plane_state) | |
13044 | return -ENOMEM; | |
13045 | ||
13046 | drm_atomic_set_fb_for_plane(new_plane_state, fb); | |
13047 | ||
13048 | new_plane_state->src_x = src_x; | |
13049 | new_plane_state->src_y = src_y; | |
13050 | new_plane_state->src_w = src_w; | |
13051 | new_plane_state->src_h = src_h; | |
13052 | new_plane_state->crtc_x = crtc_x; | |
13053 | new_plane_state->crtc_y = crtc_y; | |
13054 | new_plane_state->crtc_w = crtc_w; | |
13055 | new_plane_state->crtc_h = crtc_h; | |
13056 | ||
13057 | ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state), | |
b2b55502 VS |
13058 | to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */ |
13059 | to_intel_plane_state(plane->state), | |
f79f2692 ML |
13060 | to_intel_plane_state(new_plane_state)); |
13061 | if (ret) | |
13062 | goto out_free; | |
13063 | ||
f79f2692 ML |
13064 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
13065 | if (ret) | |
13066 | goto out_free; | |
13067 | ||
13068 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
fabac484 | 13069 | int align = intel_cursor_alignment(dev_priv); |
f79f2692 ML |
13070 | |
13071 | ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align); | |
13072 | if (ret) { | |
13073 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13074 | goto out_unlock; | |
13075 | } | |
13076 | } else { | |
f79f2692 ML |
13077 | vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation); |
13078 | if (IS_ERR(vma)) { | |
13079 | DRM_DEBUG_KMS("failed to pin object\n"); | |
13080 | ||
13081 | ret = PTR_ERR(vma); | |
13082 | goto out_unlock; | |
13083 | } | |
be1e3415 CW |
13084 | |
13085 | to_intel_plane_state(new_plane_state)->vma = vma; | |
f79f2692 ML |
13086 | } |
13087 | ||
13088 | old_fb = old_plane_state->fb; | |
13089 | ||
13090 | i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb), | |
13091 | intel_plane->frontbuffer_bit); | |
13092 | ||
13093 | /* Swap plane state */ | |
669c9215 | 13094 | plane->state = new_plane_state; |
f79f2692 | 13095 | |
72259536 VS |
13096 | if (plane->state->visible) { |
13097 | trace_intel_update_plane(plane, to_intel_crtc(crtc)); | |
282dbf9b | 13098 | intel_plane->update_plane(intel_plane, |
a5509abd VS |
13099 | to_intel_crtc_state(crtc->state), |
13100 | to_intel_plane_state(plane->state)); | |
72259536 VS |
13101 | } else { |
13102 | trace_intel_disable_plane(plane, to_intel_crtc(crtc)); | |
282dbf9b | 13103 | intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc)); |
72259536 | 13104 | } |
f79f2692 | 13105 | |
669c9215 | 13106 | old_vma = fetch_and_zero(&to_intel_plane_state(old_plane_state)->vma); |
fd70075f CW |
13107 | if (old_vma) |
13108 | intel_unpin_fb_vma(old_vma); | |
f79f2692 ML |
13109 | |
13110 | out_unlock: | |
13111 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
13112 | out_free: | |
669c9215 ML |
13113 | if (ret) |
13114 | intel_plane_destroy_state(plane, new_plane_state); | |
13115 | else | |
13116 | intel_plane_destroy_state(plane, old_plane_state); | |
f79f2692 ML |
13117 | return ret; |
13118 | ||
f79f2692 ML |
13119 | slow: |
13120 | return drm_atomic_helper_update_plane(plane, crtc, fb, | |
13121 | crtc_x, crtc_y, crtc_w, crtc_h, | |
34a2ab5e | 13122 | src_x, src_y, src_w, src_h, ctx); |
f79f2692 ML |
13123 | } |
13124 | ||
13125 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
13126 | .update_plane = intel_legacy_cursor_update, | |
13127 | .disable_plane = drm_atomic_helper_disable_plane, | |
13128 | .destroy = intel_plane_destroy, | |
f79f2692 ML |
13129 | .atomic_get_property = intel_plane_atomic_get_property, |
13130 | .atomic_set_property = intel_plane_atomic_set_property, | |
13131 | .atomic_duplicate_state = intel_plane_duplicate_state, | |
13132 | .atomic_destroy_state = intel_plane_destroy_state, | |
714244e2 | 13133 | .format_mod_supported = intel_cursor_plane_format_mod_supported, |
f79f2692 ML |
13134 | }; |
13135 | ||
b079bd17 | 13136 | static struct intel_plane * |
580503c7 | 13137 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 13138 | { |
fca0ce2a VS |
13139 | struct intel_plane *primary = NULL; |
13140 | struct intel_plane_state *state = NULL; | |
465c120c | 13141 | const uint32_t *intel_primary_formats; |
93ca7e00 | 13142 | unsigned int supported_rotations; |
45e3743a | 13143 | unsigned int num_formats; |
714244e2 | 13144 | const uint64_t *modifiers; |
fca0ce2a | 13145 | int ret; |
465c120c MR |
13146 | |
13147 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
b079bd17 VS |
13148 | if (!primary) { |
13149 | ret = -ENOMEM; | |
fca0ce2a | 13150 | goto fail; |
b079bd17 | 13151 | } |
465c120c | 13152 | |
8e7d688b | 13153 | state = intel_create_plane_state(&primary->base); |
b079bd17 VS |
13154 | if (!state) { |
13155 | ret = -ENOMEM; | |
fca0ce2a | 13156 | goto fail; |
b079bd17 VS |
13157 | } |
13158 | ||
8e7d688b | 13159 | primary->base.state = &state->base; |
ea2c67bb | 13160 | |
465c120c MR |
13161 | primary->can_scale = false; |
13162 | primary->max_downscale = 1; | |
580503c7 | 13163 | if (INTEL_GEN(dev_priv) >= 9) { |
6156a456 | 13164 | primary->can_scale = true; |
af99ceda | 13165 | state->scaler_id = -1; |
6156a456 | 13166 | } |
465c120c | 13167 | primary->pipe = pipe; |
e3c566df VS |
13168 | /* |
13169 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS | |
13170 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. | |
13171 | */ | |
13172 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) | |
13173 | primary->plane = (enum plane) !pipe; | |
13174 | else | |
13175 | primary->plane = (enum plane) pipe; | |
b14e5848 | 13176 | primary->id = PLANE_PRIMARY; |
a9ff8714 | 13177 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 13178 | primary->check_plane = intel_check_primary_plane; |
465c120c | 13179 | |
714244e2 | 13180 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { |
6c0fd451 DL |
13181 | intel_primary_formats = skl_primary_formats; |
13182 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
714244e2 BW |
13183 | modifiers = skl_format_modifiers_ccs; |
13184 | ||
9a8cc576 | 13185 | primary->update_plane = skl_update_plane; |
779d4d8f | 13186 | primary->disable_plane = skl_disable_plane; |
714244e2 BW |
13187 | } else if (INTEL_GEN(dev_priv) >= 9) { |
13188 | intel_primary_formats = skl_primary_formats; | |
13189 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
13190 | if (pipe < PIPE_C) | |
13191 | modifiers = skl_format_modifiers_ccs; | |
13192 | else | |
13193 | modifiers = skl_format_modifiers_noccs; | |
a8d201af | 13194 | |
9a8cc576 | 13195 | primary->update_plane = skl_update_plane; |
779d4d8f | 13196 | primary->disable_plane = skl_disable_plane; |
580503c7 | 13197 | } else if (INTEL_GEN(dev_priv) >= 4) { |
568db4f2 DL |
13198 | intel_primary_formats = i965_primary_formats; |
13199 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
714244e2 | 13200 | modifiers = i9xx_format_modifiers; |
a8d201af ML |
13201 | |
13202 | primary->update_plane = i9xx_update_primary_plane; | |
13203 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
13204 | } else { |
13205 | intel_primary_formats = i8xx_primary_formats; | |
13206 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
714244e2 | 13207 | modifiers = i9xx_format_modifiers; |
a8d201af ML |
13208 | |
13209 | primary->update_plane = i9xx_update_primary_plane; | |
13210 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
13211 | } |
13212 | ||
580503c7 VS |
13213 | if (INTEL_GEN(dev_priv) >= 9) |
13214 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, | |
13215 | 0, &intel_plane_funcs, | |
38573dc1 | 13216 | intel_primary_formats, num_formats, |
714244e2 | 13217 | modifiers, |
38573dc1 VS |
13218 | DRM_PLANE_TYPE_PRIMARY, |
13219 | "plane 1%c", pipe_name(pipe)); | |
9beb5fea | 13220 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
580503c7 VS |
13221 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13222 | 0, &intel_plane_funcs, | |
38573dc1 | 13223 | intel_primary_formats, num_formats, |
714244e2 | 13224 | modifiers, |
38573dc1 VS |
13225 | DRM_PLANE_TYPE_PRIMARY, |
13226 | "primary %c", pipe_name(pipe)); | |
13227 | else | |
580503c7 VS |
13228 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13229 | 0, &intel_plane_funcs, | |
38573dc1 | 13230 | intel_primary_formats, num_formats, |
714244e2 | 13231 | modifiers, |
38573dc1 VS |
13232 | DRM_PLANE_TYPE_PRIMARY, |
13233 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
13234 | if (ret) |
13235 | goto fail; | |
48404c1e | 13236 | |
5481e27f | 13237 | if (INTEL_GEN(dev_priv) >= 9) { |
93ca7e00 | 13238 | supported_rotations = |
c2c446ad RF |
13239 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | |
13240 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; | |
4ea7be2b VS |
13241 | } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
13242 | supported_rotations = | |
c2c446ad RF |
13243 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | |
13244 | DRM_MODE_REFLECT_X; | |
5481e27f | 13245 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 | 13246 | supported_rotations = |
c2c446ad | 13247 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; |
93ca7e00 | 13248 | } else { |
c2c446ad | 13249 | supported_rotations = DRM_MODE_ROTATE_0; |
93ca7e00 VS |
13250 | } |
13251 | ||
5481e27f | 13252 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 | 13253 | drm_plane_create_rotation_property(&primary->base, |
c2c446ad | 13254 | DRM_MODE_ROTATE_0, |
93ca7e00 | 13255 | supported_rotations); |
48404c1e | 13256 | |
ea2c67bb MR |
13257 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13258 | ||
b079bd17 | 13259 | return primary; |
fca0ce2a VS |
13260 | |
13261 | fail: | |
13262 | kfree(state); | |
13263 | kfree(primary); | |
13264 | ||
b079bd17 | 13265 | return ERR_PTR(ret); |
465c120c MR |
13266 | } |
13267 | ||
b079bd17 | 13268 | static struct intel_plane * |
b2d03b0d VS |
13269 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, |
13270 | enum pipe pipe) | |
3d7d6510 | 13271 | { |
fca0ce2a VS |
13272 | struct intel_plane *cursor = NULL; |
13273 | struct intel_plane_state *state = NULL; | |
13274 | int ret; | |
3d7d6510 MR |
13275 | |
13276 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
b079bd17 VS |
13277 | if (!cursor) { |
13278 | ret = -ENOMEM; | |
fca0ce2a | 13279 | goto fail; |
b079bd17 | 13280 | } |
3d7d6510 | 13281 | |
8e7d688b | 13282 | state = intel_create_plane_state(&cursor->base); |
b079bd17 VS |
13283 | if (!state) { |
13284 | ret = -ENOMEM; | |
fca0ce2a | 13285 | goto fail; |
b079bd17 VS |
13286 | } |
13287 | ||
8e7d688b | 13288 | cursor->base.state = &state->base; |
ea2c67bb | 13289 | |
3d7d6510 MR |
13290 | cursor->can_scale = false; |
13291 | cursor->max_downscale = 1; | |
13292 | cursor->pipe = pipe; | |
13293 | cursor->plane = pipe; | |
b14e5848 | 13294 | cursor->id = PLANE_CURSOR; |
a9ff8714 | 13295 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
b2d03b0d VS |
13296 | |
13297 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { | |
13298 | cursor->update_plane = i845_update_cursor; | |
13299 | cursor->disable_plane = i845_disable_cursor; | |
659056f2 | 13300 | cursor->check_plane = i845_check_cursor; |
b2d03b0d VS |
13301 | } else { |
13302 | cursor->update_plane = i9xx_update_cursor; | |
13303 | cursor->disable_plane = i9xx_disable_cursor; | |
659056f2 | 13304 | cursor->check_plane = i9xx_check_cursor; |
b2d03b0d | 13305 | } |
3d7d6510 | 13306 | |
cd5dcbf1 VS |
13307 | cursor->cursor.base = ~0; |
13308 | cursor->cursor.cntl = ~0; | |
024faac7 VS |
13309 | |
13310 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) | |
13311 | cursor->cursor.size = ~0; | |
3d7d6510 | 13312 | |
580503c7 | 13313 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
f79f2692 | 13314 | 0, &intel_cursor_plane_funcs, |
fca0ce2a VS |
13315 | intel_cursor_formats, |
13316 | ARRAY_SIZE(intel_cursor_formats), | |
714244e2 BW |
13317 | cursor_format_modifiers, |
13318 | DRM_PLANE_TYPE_CURSOR, | |
38573dc1 | 13319 | "cursor %c", pipe_name(pipe)); |
fca0ce2a VS |
13320 | if (ret) |
13321 | goto fail; | |
4398ad45 | 13322 | |
5481e27f | 13323 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 | 13324 | drm_plane_create_rotation_property(&cursor->base, |
c2c446ad RF |
13325 | DRM_MODE_ROTATE_0, |
13326 | DRM_MODE_ROTATE_0 | | |
13327 | DRM_MODE_ROTATE_180); | |
4398ad45 | 13328 | |
580503c7 | 13329 | if (INTEL_GEN(dev_priv) >= 9) |
af99ceda CK |
13330 | state->scaler_id = -1; |
13331 | ||
ea2c67bb MR |
13332 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13333 | ||
b079bd17 | 13334 | return cursor; |
fca0ce2a VS |
13335 | |
13336 | fail: | |
13337 | kfree(state); | |
13338 | kfree(cursor); | |
13339 | ||
b079bd17 | 13340 | return ERR_PTR(ret); |
3d7d6510 MR |
13341 | } |
13342 | ||
1c74eeaf NM |
13343 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
13344 | struct intel_crtc_state *crtc_state) | |
549e2bfb | 13345 | { |
65edccce VS |
13346 | struct intel_crtc_scaler_state *scaler_state = |
13347 | &crtc_state->scaler_state; | |
1c74eeaf | 13348 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
549e2bfb | 13349 | int i; |
549e2bfb | 13350 | |
1c74eeaf NM |
13351 | crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe]; |
13352 | if (!crtc->num_scalers) | |
13353 | return; | |
13354 | ||
65edccce VS |
13355 | for (i = 0; i < crtc->num_scalers; i++) { |
13356 | struct intel_scaler *scaler = &scaler_state->scalers[i]; | |
13357 | ||
13358 | scaler->in_use = 0; | |
13359 | scaler->mode = PS_SCALER_MODE_DYN; | |
549e2bfb CK |
13360 | } |
13361 | ||
13362 | scaler_state->scaler_id = -1; | |
13363 | } | |
13364 | ||
5ab0d85b | 13365 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
79e53945 JB |
13366 | { |
13367 | struct intel_crtc *intel_crtc; | |
f5de6e07 | 13368 | struct intel_crtc_state *crtc_state = NULL; |
b079bd17 VS |
13369 | struct intel_plane *primary = NULL; |
13370 | struct intel_plane *cursor = NULL; | |
a81d6fa0 | 13371 | int sprite, ret; |
79e53945 | 13372 | |
955382f3 | 13373 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
b079bd17 VS |
13374 | if (!intel_crtc) |
13375 | return -ENOMEM; | |
79e53945 | 13376 | |
f5de6e07 | 13377 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
b079bd17 VS |
13378 | if (!crtc_state) { |
13379 | ret = -ENOMEM; | |
f5de6e07 | 13380 | goto fail; |
b079bd17 | 13381 | } |
550acefd ACO |
13382 | intel_crtc->config = crtc_state; |
13383 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 13384 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13385 | |
580503c7 | 13386 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
13387 | if (IS_ERR(primary)) { |
13388 | ret = PTR_ERR(primary); | |
3d7d6510 | 13389 | goto fail; |
b079bd17 | 13390 | } |
d97d7b48 | 13391 | intel_crtc->plane_ids_mask |= BIT(primary->id); |
3d7d6510 | 13392 | |
a81d6fa0 | 13393 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
13394 | struct intel_plane *plane; |
13395 | ||
580503c7 | 13396 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
d2b2cbce | 13397 | if (IS_ERR(plane)) { |
b079bd17 VS |
13398 | ret = PTR_ERR(plane); |
13399 | goto fail; | |
13400 | } | |
d97d7b48 | 13401 | intel_crtc->plane_ids_mask |= BIT(plane->id); |
a81d6fa0 VS |
13402 | } |
13403 | ||
580503c7 | 13404 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
d2b2cbce | 13405 | if (IS_ERR(cursor)) { |
b079bd17 | 13406 | ret = PTR_ERR(cursor); |
3d7d6510 | 13407 | goto fail; |
b079bd17 | 13408 | } |
d97d7b48 | 13409 | intel_crtc->plane_ids_mask |= BIT(cursor->id); |
3d7d6510 | 13410 | |
5ab0d85b | 13411 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, |
b079bd17 VS |
13412 | &primary->base, &cursor->base, |
13413 | &intel_crtc_funcs, | |
4d5d72b7 | 13414 | "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
13415 | if (ret) |
13416 | goto fail; | |
79e53945 | 13417 | |
80824003 | 13418 | intel_crtc->pipe = pipe; |
e3c566df | 13419 | intel_crtc->plane = primary->plane; |
80824003 | 13420 | |
1c74eeaf NM |
13421 | /* initialize shared scalers */ |
13422 | intel_crtc_init_scalers(intel_crtc, crtc_state); | |
13423 | ||
22fd0fab JB |
13424 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13425 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
e2af48c6 VS |
13426 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; |
13427 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; | |
22fd0fab | 13428 | |
79e53945 | 13429 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 13430 | |
8563b1e8 LL |
13431 | intel_color_init(&intel_crtc->base); |
13432 | ||
87b6b101 | 13433 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
b079bd17 VS |
13434 | |
13435 | return 0; | |
3d7d6510 MR |
13436 | |
13437 | fail: | |
b079bd17 VS |
13438 | /* |
13439 | * drm_mode_config_cleanup() will free up any | |
13440 | * crtcs/planes already initialized. | |
13441 | */ | |
f5de6e07 | 13442 | kfree(crtc_state); |
3d7d6510 | 13443 | kfree(intel_crtc); |
b079bd17 VS |
13444 | |
13445 | return ret; | |
79e53945 JB |
13446 | } |
13447 | ||
752aa88a JB |
13448 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13449 | { | |
6e9f798d | 13450 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13451 | |
51fd371b | 13452 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13453 | |
51ec53da | 13454 | if (!connector->base.state->crtc) |
752aa88a JB |
13455 | return INVALID_PIPE; |
13456 | ||
51ec53da | 13457 | return to_intel_crtc(connector->base.state->crtc)->pipe; |
752aa88a JB |
13458 | } |
13459 | ||
08d7b3d1 | 13460 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13461 | struct drm_file *file) |
08d7b3d1 | 13462 | { |
08d7b3d1 | 13463 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13464 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13465 | struct intel_crtc *crtc; |
08d7b3d1 | 13466 | |
418da172 | 13467 | drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); |
71240ed2 | 13468 | if (!drmmode_crtc) |
3f2c2057 | 13469 | return -ENOENT; |
08d7b3d1 | 13470 | |
7707e653 | 13471 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13472 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13473 | |
c05422d5 | 13474 | return 0; |
08d7b3d1 CW |
13475 | } |
13476 | ||
66a9278e | 13477 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13478 | { |
66a9278e DV |
13479 | struct drm_device *dev = encoder->base.dev; |
13480 | struct intel_encoder *source_encoder; | |
79e53945 | 13481 | int index_mask = 0; |
79e53945 JB |
13482 | int entry = 0; |
13483 | ||
b2784e15 | 13484 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13485 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13486 | index_mask |= (1 << entry); |
13487 | ||
79e53945 JB |
13488 | entry++; |
13489 | } | |
4ef69c7a | 13490 | |
79e53945 JB |
13491 | return index_mask; |
13492 | } | |
13493 | ||
646d5772 | 13494 | static bool has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 13495 | { |
646d5772 | 13496 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
13497 | return false; |
13498 | ||
13499 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13500 | return false; | |
13501 | ||
5db94019 | 13502 | if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13503 | return false; |
13504 | ||
13505 | return true; | |
13506 | } | |
13507 | ||
6315b5d3 | 13508 | static bool intel_crt_present(struct drm_i915_private *dev_priv) |
84b4e042 | 13509 | { |
6315b5d3 | 13510 | if (INTEL_GEN(dev_priv) >= 9) |
884497ed DL |
13511 | return false; |
13512 | ||
50a0bc90 | 13513 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
13514 | return false; |
13515 | ||
920a14b2 | 13516 | if (IS_CHERRYVIEW(dev_priv)) |
84b4e042 JB |
13517 | return false; |
13518 | ||
4f8036a2 TU |
13519 | if (HAS_PCH_LPT_H(dev_priv) && |
13520 | I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
65e472e4 VS |
13521 | return false; |
13522 | ||
70ac54d0 | 13523 | /* DDI E can't be used if DDI A requires 4 lanes */ |
4f8036a2 | 13524 | if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
13525 | return false; |
13526 | ||
e4abb733 | 13527 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
13528 | return false; |
13529 | ||
13530 | return true; | |
13531 | } | |
13532 | ||
8090ba8c ID |
13533 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
13534 | { | |
13535 | int pps_num; | |
13536 | int pps_idx; | |
13537 | ||
13538 | if (HAS_DDI(dev_priv)) | |
13539 | return; | |
13540 | /* | |
13541 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
13542 | * everywhere where registers can be write protected. | |
13543 | */ | |
13544 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13545 | pps_num = 2; | |
13546 | else | |
13547 | pps_num = 1; | |
13548 | ||
13549 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
13550 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
13551 | ||
13552 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
13553 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
13554 | } | |
13555 | } | |
13556 | ||
44cb734c ID |
13557 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
13558 | { | |
cc3f90f0 | 13559 | if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) |
44cb734c ID |
13560 | dev_priv->pps_mmio_base = PCH_PPS_BASE; |
13561 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13562 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
13563 | else | |
13564 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
13565 | |
13566 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
13567 | } |
13568 | ||
c39055b0 | 13569 | static void intel_setup_outputs(struct drm_i915_private *dev_priv) |
79e53945 | 13570 | { |
4ef69c7a | 13571 | struct intel_encoder *encoder; |
cb0953d7 | 13572 | bool dpd_is_edp = false; |
79e53945 | 13573 | |
44cb734c ID |
13574 | intel_pps_init(dev_priv); |
13575 | ||
97a824e1 ID |
13576 | /* |
13577 | * intel_edp_init_connector() depends on this completing first, to | |
13578 | * prevent the registeration of both eDP and LVDS and the incorrect | |
13579 | * sharing of the PPS. | |
13580 | */ | |
c39055b0 | 13581 | intel_lvds_init(dev_priv); |
79e53945 | 13582 | |
6315b5d3 | 13583 | if (intel_crt_present(dev_priv)) |
c39055b0 | 13584 | intel_crt_init(dev_priv); |
cb0953d7 | 13585 | |
cc3f90f0 | 13586 | if (IS_GEN9_LP(dev_priv)) { |
c776eb2e VK |
13587 | /* |
13588 | * FIXME: Broxton doesn't support port detection via the | |
13589 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
13590 | * detect the ports. | |
13591 | */ | |
c39055b0 ACO |
13592 | intel_ddi_init(dev_priv, PORT_A); |
13593 | intel_ddi_init(dev_priv, PORT_B); | |
13594 | intel_ddi_init(dev_priv, PORT_C); | |
c6c794a2 | 13595 | |
c39055b0 | 13596 | intel_dsi_init(dev_priv); |
4f8036a2 | 13597 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
13598 | int found; |
13599 | ||
de31facd JB |
13600 | /* |
13601 | * Haswell uses DDI functions to detect digital outputs. | |
13602 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13603 | * it's there. | |
13604 | */ | |
77179400 | 13605 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 13606 | /* WaIgnoreDDIAStrap: skl */ |
b976dc53 | 13607 | if (found || IS_GEN9_BC(dev_priv)) |
c39055b0 | 13608 | intel_ddi_init(dev_priv, PORT_A); |
0e72a5b5 ED |
13609 | |
13610 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13611 | * register */ | |
13612 | found = I915_READ(SFUSE_STRAP); | |
13613 | ||
13614 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
c39055b0 | 13615 | intel_ddi_init(dev_priv, PORT_B); |
0e72a5b5 | 13616 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
c39055b0 | 13617 | intel_ddi_init(dev_priv, PORT_C); |
0e72a5b5 | 13618 | if (found & SFUSE_STRAP_DDID_DETECTED) |
c39055b0 | 13619 | intel_ddi_init(dev_priv, PORT_D); |
2800e4c2 RV |
13620 | /* |
13621 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
13622 | */ | |
b976dc53 | 13623 | if (IS_GEN9_BC(dev_priv) && |
2800e4c2 RV |
13624 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
13625 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
13626 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
c39055b0 | 13627 | intel_ddi_init(dev_priv, PORT_E); |
2800e4c2 | 13628 | |
6e266956 | 13629 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 13630 | int found; |
7b91bf7f | 13631 | dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); |
270b3042 | 13632 | |
646d5772 | 13633 | if (has_edp_a(dev_priv)) |
c39055b0 | 13634 | intel_dp_init(dev_priv, DP_A, PORT_A); |
cb0953d7 | 13635 | |
dc0fa718 | 13636 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 13637 | /* PCH SDVOB multiplex with HDMIB */ |
c39055b0 | 13638 | found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); |
30ad48b7 | 13639 | if (!found) |
c39055b0 | 13640 | intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); |
5eb08b69 | 13641 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
c39055b0 | 13642 | intel_dp_init(dev_priv, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
13643 | } |
13644 | ||
dc0fa718 | 13645 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
c39055b0 | 13646 | intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); |
30ad48b7 | 13647 | |
dc0fa718 | 13648 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
c39055b0 | 13649 | intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); |
30ad48b7 | 13650 | |
5eb08b69 | 13651 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
c39055b0 | 13652 | intel_dp_init(dev_priv, PCH_DP_C, PORT_C); |
5eb08b69 | 13653 | |
270b3042 | 13654 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
c39055b0 | 13655 | intel_dp_init(dev_priv, PCH_DP_D, PORT_D); |
920a14b2 | 13656 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 13657 | bool has_edp, has_port; |
457c52d8 | 13658 | |
e17ac6db VS |
13659 | /* |
13660 | * The DP_DETECTED bit is the latched state of the DDC | |
13661 | * SDA pin at boot. However since eDP doesn't require DDC | |
13662 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
13663 | * eDP ports may have been muxed to an alternate function. | |
13664 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
13665 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
13666 | * detect eDP ports. | |
22f35042 VS |
13667 | * |
13668 | * Sadly the straps seem to be missing sometimes even for HDMI | |
13669 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
13670 | * and VBT for the presence of the port. Additionally we can't | |
13671 | * trust the port type the VBT declares as we've seen at least | |
13672 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 13673 | */ |
7b91bf7f | 13674 | has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); |
22f35042 VS |
13675 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
13676 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
c39055b0 | 13677 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); |
22f35042 | 13678 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 13679 | intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); |
585a94b8 | 13680 | |
7b91bf7f | 13681 | has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); |
22f35042 VS |
13682 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
13683 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
c39055b0 | 13684 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); |
22f35042 | 13685 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 13686 | intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); |
19c03924 | 13687 | |
920a14b2 | 13688 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
13689 | /* |
13690 | * eDP not supported on port D, | |
13691 | * so no need to worry about it | |
13692 | */ | |
13693 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
13694 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
c39055b0 | 13695 | intel_dp_init(dev_priv, CHV_DP_D, PORT_D); |
22f35042 | 13696 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
c39055b0 | 13697 | intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); |
9418c1f1 VS |
13698 | } |
13699 | ||
c39055b0 | 13700 | intel_dsi_init(dev_priv); |
5db94019 | 13701 | } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { |
27185ae1 | 13702 | bool found = false; |
7d57382e | 13703 | |
e2debe91 | 13704 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13705 | DRM_DEBUG_KMS("probing SDVOB\n"); |
c39055b0 | 13706 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); |
9beb5fea | 13707 | if (!found && IS_G4X(dev_priv)) { |
b01f2c3a | 13708 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
c39055b0 | 13709 | intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); |
b01f2c3a | 13710 | } |
27185ae1 | 13711 | |
9beb5fea | 13712 | if (!found && IS_G4X(dev_priv)) |
c39055b0 | 13713 | intel_dp_init(dev_priv, DP_B, PORT_B); |
725e30ad | 13714 | } |
13520b05 KH |
13715 | |
13716 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 13717 | |
e2debe91 | 13718 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13719 | DRM_DEBUG_KMS("probing SDVOC\n"); |
c39055b0 | 13720 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); |
b01f2c3a | 13721 | } |
27185ae1 | 13722 | |
e2debe91 | 13723 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 13724 | |
9beb5fea | 13725 | if (IS_G4X(dev_priv)) { |
b01f2c3a | 13726 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
c39055b0 | 13727 | intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); |
b01f2c3a | 13728 | } |
9beb5fea | 13729 | if (IS_G4X(dev_priv)) |
c39055b0 | 13730 | intel_dp_init(dev_priv, DP_C, PORT_C); |
725e30ad | 13731 | } |
27185ae1 | 13732 | |
9beb5fea | 13733 | if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) |
c39055b0 | 13734 | intel_dp_init(dev_priv, DP_D, PORT_D); |
5db94019 | 13735 | } else if (IS_GEN2(dev_priv)) |
c39055b0 | 13736 | intel_dvo_init(dev_priv); |
79e53945 | 13737 | |
56b857a5 | 13738 | if (SUPPORTS_TV(dev_priv)) |
c39055b0 | 13739 | intel_tv_init(dev_priv); |
79e53945 | 13740 | |
c39055b0 | 13741 | intel_psr_init(dev_priv); |
7c8f8a70 | 13742 | |
c39055b0 | 13743 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
4ef69c7a CW |
13744 | encoder->base.possible_crtcs = encoder->crtc_mask; |
13745 | encoder->base.possible_clones = | |
66a9278e | 13746 | intel_encoder_clones(encoder); |
79e53945 | 13747 | } |
47356eb6 | 13748 | |
c39055b0 | 13749 | intel_init_pch_refclk(dev_priv); |
270b3042 | 13750 | |
c39055b0 | 13751 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
79e53945 JB |
13752 | } |
13753 | ||
13754 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
13755 | { | |
13756 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 13757 | |
ef2d633e | 13758 | drm_framebuffer_cleanup(fb); |
70001cd2 | 13759 | |
dd689287 CW |
13760 | i915_gem_object_lock(intel_fb->obj); |
13761 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
13762 | i915_gem_object_unlock(intel_fb->obj); | |
13763 | ||
f8c417cd | 13764 | i915_gem_object_put(intel_fb->obj); |
70001cd2 | 13765 | |
79e53945 JB |
13766 | kfree(intel_fb); |
13767 | } | |
13768 | ||
13769 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 13770 | struct drm_file *file, |
79e53945 JB |
13771 | unsigned int *handle) |
13772 | { | |
13773 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 13774 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 13775 | |
cc917ab4 CW |
13776 | if (obj->userptr.mm) { |
13777 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
13778 | return -EINVAL; | |
13779 | } | |
13780 | ||
05394f39 | 13781 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
13782 | } |
13783 | ||
86c98588 RV |
13784 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
13785 | struct drm_file *file, | |
13786 | unsigned flags, unsigned color, | |
13787 | struct drm_clip_rect *clips, | |
13788 | unsigned num_clips) | |
13789 | { | |
5a97bcc6 | 13790 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
86c98588 | 13791 | |
5a97bcc6 | 13792 | i915_gem_object_flush_if_display(obj); |
d59b21ec | 13793 | intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); |
86c98588 RV |
13794 | |
13795 | return 0; | |
13796 | } | |
13797 | ||
79e53945 JB |
13798 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
13799 | .destroy = intel_user_framebuffer_destroy, | |
13800 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 13801 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
13802 | }; |
13803 | ||
b321803d | 13804 | static |
920a14b2 TU |
13805 | u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, |
13806 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 13807 | { |
24dbf51a | 13808 | u32 gen = INTEL_GEN(dev_priv); |
b321803d DL |
13809 | |
13810 | if (gen >= 9) { | |
ac484963 VS |
13811 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
13812 | ||
b321803d DL |
13813 | /* "The stride in bytes must not exceed the of the size of 8K |
13814 | * pixels and 32K bytes." | |
13815 | */ | |
ac484963 | 13816 | return min(8192 * cpp, 32768); |
6401c37d | 13817 | } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) { |
b321803d DL |
13818 | return 32*1024; |
13819 | } else if (gen >= 4) { | |
13820 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13821 | return 16*1024; | |
13822 | else | |
13823 | return 32*1024; | |
13824 | } else if (gen >= 3) { | |
13825 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13826 | return 8*1024; | |
13827 | else | |
13828 | return 16*1024; | |
13829 | } else { | |
13830 | /* XXX DSPC is limited to 4k tiled */ | |
13831 | return 8*1024; | |
13832 | } | |
13833 | } | |
13834 | ||
24dbf51a CW |
13835 | static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, |
13836 | struct drm_i915_gem_object *obj, | |
13837 | struct drm_mode_fb_cmd2 *mode_cmd) | |
79e53945 | 13838 | { |
24dbf51a | 13839 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2e2adb05 | 13840 | struct drm_framebuffer *fb = &intel_fb->base; |
b3c11ac2 | 13841 | struct drm_format_name_buf format_name; |
2e2adb05 | 13842 | u32 pitch_limit; |
dd689287 | 13843 | unsigned int tiling, stride; |
24dbf51a | 13844 | int ret = -EINVAL; |
2e2adb05 | 13845 | int i; |
79e53945 | 13846 | |
dd689287 CW |
13847 | i915_gem_object_lock(obj); |
13848 | obj->framebuffer_references++; | |
13849 | tiling = i915_gem_object_get_tiling(obj); | |
13850 | stride = i915_gem_object_get_stride(obj); | |
13851 | i915_gem_object_unlock(obj); | |
dd4916c5 | 13852 | |
2a80eada | 13853 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
13854 | /* |
13855 | * If there's a fence, enforce that | |
13856 | * the fb modifier and tiling mode match. | |
13857 | */ | |
13858 | if (tiling != I915_TILING_NONE && | |
13859 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 13860 | DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n"); |
24dbf51a | 13861 | goto err; |
2a80eada DV |
13862 | } |
13863 | } else { | |
c2ff7370 | 13864 | if (tiling == I915_TILING_X) { |
2a80eada | 13865 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 13866 | } else if (tiling == I915_TILING_Y) { |
144cc143 | 13867 | DRM_DEBUG_KMS("No Y tiling for legacy addfb\n"); |
24dbf51a | 13868 | goto err; |
2a80eada DV |
13869 | } |
13870 | } | |
13871 | ||
9a8f0a12 TU |
13872 | /* Passed in modifier sanity checking. */ |
13873 | switch (mode_cmd->modifier[0]) { | |
2e2adb05 VS |
13874 | case I915_FORMAT_MOD_Y_TILED_CCS: |
13875 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
13876 | switch (mode_cmd->pixel_format) { | |
13877 | case DRM_FORMAT_XBGR8888: | |
13878 | case DRM_FORMAT_ABGR8888: | |
13879 | case DRM_FORMAT_XRGB8888: | |
13880 | case DRM_FORMAT_ARGB8888: | |
13881 | break; | |
13882 | default: | |
13883 | DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n"); | |
13884 | goto err; | |
13885 | } | |
13886 | /* fall through */ | |
9a8f0a12 TU |
13887 | case I915_FORMAT_MOD_Y_TILED: |
13888 | case I915_FORMAT_MOD_Yf_TILED: | |
6315b5d3 | 13889 | if (INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
13890 | DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n", |
13891 | mode_cmd->modifier[0]); | |
24dbf51a | 13892 | goto err; |
9a8f0a12 | 13893 | } |
2f075565 | 13894 | case DRM_FORMAT_MOD_LINEAR: |
9a8f0a12 TU |
13895 | case I915_FORMAT_MOD_X_TILED: |
13896 | break; | |
13897 | default: | |
144cc143 VS |
13898 | DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n", |
13899 | mode_cmd->modifier[0]); | |
24dbf51a | 13900 | goto err; |
c16ed4be | 13901 | } |
57cd6508 | 13902 | |
c2ff7370 VS |
13903 | /* |
13904 | * gen2/3 display engine uses the fence if present, | |
13905 | * so the tiling mode must match the fb modifier exactly. | |
13906 | */ | |
13907 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
13908 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 13909 | DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n"); |
9aceb5c1 | 13910 | goto err; |
c2ff7370 VS |
13911 | } |
13912 | ||
920a14b2 | 13913 | pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], |
b321803d | 13914 | mode_cmd->pixel_format); |
a35cdaa0 | 13915 | if (mode_cmd->pitches[0] > pitch_limit) { |
144cc143 | 13916 | DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n", |
2f075565 | 13917 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? |
144cc143 VS |
13918 | "tiled" : "linear", |
13919 | mode_cmd->pitches[0], pitch_limit); | |
24dbf51a | 13920 | goto err; |
c16ed4be | 13921 | } |
5d7bd705 | 13922 | |
c2ff7370 VS |
13923 | /* |
13924 | * If there's a fence, enforce that | |
13925 | * the fb pitch and fence stride match. | |
13926 | */ | |
144cc143 VS |
13927 | if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { |
13928 | DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n", | |
13929 | mode_cmd->pitches[0], stride); | |
24dbf51a | 13930 | goto err; |
c16ed4be | 13931 | } |
5d7bd705 | 13932 | |
57779d06 | 13933 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 13934 | switch (mode_cmd->pixel_format) { |
57779d06 | 13935 | case DRM_FORMAT_C8: |
04b3924d VS |
13936 | case DRM_FORMAT_RGB565: |
13937 | case DRM_FORMAT_XRGB8888: | |
13938 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
13939 | break; |
13940 | case DRM_FORMAT_XRGB1555: | |
6315b5d3 | 13941 | if (INTEL_GEN(dev_priv) > 3) { |
144cc143 VS |
13942 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13943 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13944 | goto err; |
c16ed4be | 13945 | } |
57779d06 | 13946 | break; |
57779d06 | 13947 | case DRM_FORMAT_ABGR8888: |
920a14b2 | 13948 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
6315b5d3 | 13949 | INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
13950 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13951 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13952 | goto err; |
6c0fd451 DL |
13953 | } |
13954 | break; | |
13955 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 13956 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 13957 | case DRM_FORMAT_XBGR2101010: |
6315b5d3 | 13958 | if (INTEL_GEN(dev_priv) < 4) { |
144cc143 VS |
13959 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13960 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13961 | goto err; |
c16ed4be | 13962 | } |
b5626747 | 13963 | break; |
7531208b | 13964 | case DRM_FORMAT_ABGR2101010: |
920a14b2 | 13965 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
144cc143 VS |
13966 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13967 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13968 | goto err; |
7531208b DL |
13969 | } |
13970 | break; | |
04b3924d VS |
13971 | case DRM_FORMAT_YUYV: |
13972 | case DRM_FORMAT_UYVY: | |
13973 | case DRM_FORMAT_YVYU: | |
13974 | case DRM_FORMAT_VYUY: | |
ab33081a | 13975 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
144cc143 VS |
13976 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13977 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13978 | goto err; |
c16ed4be | 13979 | } |
57cd6508 CW |
13980 | break; |
13981 | default: | |
144cc143 VS |
13982 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13983 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13984 | goto err; |
57cd6508 CW |
13985 | } |
13986 | ||
90f9a336 VS |
13987 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
13988 | if (mode_cmd->offsets[0] != 0) | |
24dbf51a | 13989 | goto err; |
90f9a336 | 13990 | |
2e2adb05 | 13991 | drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); |
d88c4afd | 13992 | |
2e2adb05 VS |
13993 | for (i = 0; i < fb->format->num_planes; i++) { |
13994 | u32 stride_alignment; | |
13995 | ||
13996 | if (mode_cmd->handles[i] != mode_cmd->handles[0]) { | |
13997 | DRM_DEBUG_KMS("bad plane %d handle\n", i); | |
814feed3 | 13998 | goto err; |
2e2adb05 VS |
13999 | } |
14000 | ||
14001 | stride_alignment = intel_fb_stride_alignment(fb, i); | |
14002 | ||
14003 | /* | |
14004 | * Display WA #0531: skl,bxt,kbl,glk | |
14005 | * | |
14006 | * Render decompression and plane width > 3840 | |
14007 | * combined with horizontal panning requires the | |
14008 | * plane stride to be a multiple of 4. We'll just | |
14009 | * require the entire fb to accommodate that to avoid | |
14010 | * potential runtime errors at plane configuration time. | |
14011 | */ | |
14012 | if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 && | |
14013 | (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || | |
14014 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) | |
14015 | stride_alignment *= 4; | |
14016 | ||
14017 | if (fb->pitches[i] & (stride_alignment - 1)) { | |
14018 | DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n", | |
14019 | i, fb->pitches[i], stride_alignment); | |
14020 | goto err; | |
14021 | } | |
d88c4afd VS |
14022 | } |
14023 | ||
c7d73f6a DV |
14024 | intel_fb->obj = obj; |
14025 | ||
2e2adb05 | 14026 | ret = intel_fill_fb_info(dev_priv, fb); |
6687c906 | 14027 | if (ret) |
9aceb5c1 | 14028 | goto err; |
2d7a215f | 14029 | |
2e2adb05 | 14030 | ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); |
79e53945 JB |
14031 | if (ret) { |
14032 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
24dbf51a | 14033 | goto err; |
79e53945 JB |
14034 | } |
14035 | ||
79e53945 | 14036 | return 0; |
24dbf51a CW |
14037 | |
14038 | err: | |
dd689287 CW |
14039 | i915_gem_object_lock(obj); |
14040 | obj->framebuffer_references--; | |
14041 | i915_gem_object_unlock(obj); | |
24dbf51a | 14042 | return ret; |
79e53945 JB |
14043 | } |
14044 | ||
79e53945 JB |
14045 | static struct drm_framebuffer * |
14046 | intel_user_framebuffer_create(struct drm_device *dev, | |
14047 | struct drm_file *filp, | |
1eb83451 | 14048 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14049 | { |
dcb1394e | 14050 | struct drm_framebuffer *fb; |
05394f39 | 14051 | struct drm_i915_gem_object *obj; |
76dc3769 | 14052 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14053 | |
03ac0642 CW |
14054 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
14055 | if (!obj) | |
cce13ff7 | 14056 | return ERR_PTR(-ENOENT); |
79e53945 | 14057 | |
24dbf51a | 14058 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 14059 | if (IS_ERR(fb)) |
f0cd5182 | 14060 | i915_gem_object_put(obj); |
dcb1394e LW |
14061 | |
14062 | return fb; | |
79e53945 JB |
14063 | } |
14064 | ||
778e23a9 CW |
14065 | static void intel_atomic_state_free(struct drm_atomic_state *state) |
14066 | { | |
14067 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
14068 | ||
14069 | drm_atomic_state_default_release(state); | |
14070 | ||
14071 | i915_sw_fence_fini(&intel_state->commit_ready); | |
14072 | ||
14073 | kfree(state); | |
14074 | } | |
14075 | ||
79e53945 | 14076 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14077 | .fb_create = intel_user_framebuffer_create, |
bbfb6ce8 | 14078 | .get_format_info = intel_get_format_info, |
0632fef6 | 14079 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14080 | .atomic_check = intel_atomic_check, |
14081 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14082 | .atomic_state_alloc = intel_atomic_state_alloc, |
14083 | .atomic_state_clear = intel_atomic_state_clear, | |
778e23a9 | 14084 | .atomic_state_free = intel_atomic_state_free, |
79e53945 JB |
14085 | }; |
14086 | ||
88212941 ID |
14087 | /** |
14088 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14089 | * @dev_priv: device private | |
14090 | */ | |
14091 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 14092 | { |
7ff89ca2 VS |
14093 | intel_init_cdclk_hooks(dev_priv); |
14094 | ||
88212941 | 14095 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 14096 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14097 | dev_priv->display.get_initial_plane_config = |
14098 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14099 | dev_priv->display.crtc_compute_clock = |
14100 | haswell_crtc_compute_clock; | |
14101 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14102 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14103 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 14104 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14105 | dev_priv->display.get_initial_plane_config = |
14106 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14107 | dev_priv->display.crtc_compute_clock = |
14108 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14109 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14110 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14111 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 14112 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14113 | dev_priv->display.get_initial_plane_config = |
14114 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14115 | dev_priv->display.crtc_compute_clock = |
14116 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14117 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14118 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 14119 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 14120 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14121 | dev_priv->display.get_initial_plane_config = |
14122 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
14123 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
14124 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
14125 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14126 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
14127 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14128 | dev_priv->display.get_initial_plane_config = | |
14129 | i9xx_get_initial_plane_config; | |
14130 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
14131 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14132 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
14133 | } else if (IS_G4X(dev_priv)) { |
14134 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14135 | dev_priv->display.get_initial_plane_config = | |
14136 | i9xx_get_initial_plane_config; | |
14137 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
14138 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14139 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
14140 | } else if (IS_PINEVIEW(dev_priv)) { |
14141 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14142 | dev_priv->display.get_initial_plane_config = | |
14143 | i9xx_get_initial_plane_config; | |
14144 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
14145 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14146 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 14147 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 14148 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14149 | dev_priv->display.get_initial_plane_config = |
14150 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14151 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14152 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14153 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
14154 | } else { |
14155 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14156 | dev_priv->display.get_initial_plane_config = | |
14157 | i9xx_get_initial_plane_config; | |
14158 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
14159 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14160 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14161 | } |
e70236a8 | 14162 | |
88212941 | 14163 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 14164 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 14165 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 14166 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 14167 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
14168 | /* FIXME: detect B0+ stepping and use auto training */ |
14169 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 14170 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 14171 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
14172 | } |
14173 | ||
bd30ca2d | 14174 | if (INTEL_GEN(dev_priv) >= 9) |
27082493 L |
14175 | dev_priv->display.update_crtcs = skl_update_crtcs; |
14176 | else | |
14177 | dev_priv->display.update_crtcs = intel_update_crtcs; | |
e70236a8 JB |
14178 | } |
14179 | ||
435793df KP |
14180 | /* |
14181 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14182 | */ | |
14183 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14184 | { | |
fac5e23e | 14185 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 14186 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 14187 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14188 | } |
14189 | ||
4dca20ef | 14190 | /* |
5a15ab5b CE |
14191 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14192 | * brightness value | |
4dca20ef CE |
14193 | */ |
14194 | static void quirk_invert_brightness(struct drm_device *dev) | |
14195 | { | |
fac5e23e | 14196 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 14197 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 14198 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14199 | } |
14200 | ||
9c72cc6f SD |
14201 | /* Some VBT's incorrectly indicate no backlight is present */ |
14202 | static void quirk_backlight_present(struct drm_device *dev) | |
14203 | { | |
fac5e23e | 14204 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
14205 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
14206 | DRM_INFO("applying backlight present quirk\n"); | |
14207 | } | |
14208 | ||
c99a259b MN |
14209 | /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms |
14210 | * which is 300 ms greater than eDP spec T12 min. | |
14211 | */ | |
14212 | static void quirk_increase_t12_delay(struct drm_device *dev) | |
14213 | { | |
14214 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14215 | ||
14216 | dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY; | |
14217 | DRM_INFO("Applying T12 delay quirk\n"); | |
14218 | } | |
14219 | ||
b690e96c JB |
14220 | struct intel_quirk { |
14221 | int device; | |
14222 | int subsystem_vendor; | |
14223 | int subsystem_device; | |
14224 | void (*hook)(struct drm_device *dev); | |
14225 | }; | |
14226 | ||
5f85f176 EE |
14227 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14228 | struct intel_dmi_quirk { | |
14229 | void (*hook)(struct drm_device *dev); | |
14230 | const struct dmi_system_id (*dmi_id_list)[]; | |
14231 | }; | |
14232 | ||
14233 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14234 | { | |
14235 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14236 | return 1; | |
14237 | } | |
14238 | ||
14239 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14240 | { | |
14241 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14242 | { | |
14243 | .callback = intel_dmi_reverse_brightness, | |
14244 | .ident = "NCR Corporation", | |
14245 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14246 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14247 | }, | |
14248 | }, | |
14249 | { } /* terminating entry */ | |
14250 | }, | |
14251 | .hook = quirk_invert_brightness, | |
14252 | }, | |
14253 | }; | |
14254 | ||
c43b5634 | 14255 | static struct intel_quirk intel_quirks[] = { |
435793df KP |
14256 | /* Lenovo U160 cannot use SSC on LVDS */ |
14257 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14258 | |
14259 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14260 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14261 | |
be505f64 AH |
14262 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14263 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14264 | ||
14265 | /* Acer/eMachines G725 */ | |
14266 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14267 | ||
14268 | /* Acer/eMachines e725 */ | |
14269 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14270 | ||
14271 | /* Acer/Packard Bell NCL20 */ | |
14272 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14273 | ||
14274 | /* Acer Aspire 4736Z */ | |
14275 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14276 | |
14277 | /* Acer Aspire 5336 */ | |
14278 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14279 | |
14280 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14281 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14282 | |
dfb3d47b SD |
14283 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14284 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14285 | ||
b2a9601c | 14286 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14287 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14288 | ||
1b9448b0 JN |
14289 | /* Apple Macbook 4,1 */ |
14290 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
14291 | ||
d4967d8c SD |
14292 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14293 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14294 | |
14295 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14296 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14297 | |
14298 | /* Dell Chromebook 11 */ | |
14299 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
14300 | |
14301 | /* Dell Chromebook 11 (2015 version) */ | |
14302 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
c99a259b MN |
14303 | |
14304 | /* Toshiba Satellite P50-C-18C */ | |
14305 | { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay }, | |
b690e96c JB |
14306 | }; |
14307 | ||
14308 | static void intel_init_quirks(struct drm_device *dev) | |
14309 | { | |
14310 | struct pci_dev *d = dev->pdev; | |
14311 | int i; | |
14312 | ||
14313 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14314 | struct intel_quirk *q = &intel_quirks[i]; | |
14315 | ||
14316 | if (d->device == q->device && | |
14317 | (d->subsystem_vendor == q->subsystem_vendor || | |
14318 | q->subsystem_vendor == PCI_ANY_ID) && | |
14319 | (d->subsystem_device == q->subsystem_device || | |
14320 | q->subsystem_device == PCI_ANY_ID)) | |
14321 | q->hook(dev); | |
14322 | } | |
5f85f176 EE |
14323 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14324 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14325 | intel_dmi_quirks[i].hook(dev); | |
14326 | } | |
b690e96c JB |
14327 | } |
14328 | ||
9cce37f4 | 14329 | /* Disable the VGA plane that we never use */ |
29b74b7f | 14330 | static void i915_disable_vga(struct drm_i915_private *dev_priv) |
9cce37f4 | 14331 | { |
52a05c30 | 14332 | struct pci_dev *pdev = dev_priv->drm.pdev; |
9cce37f4 | 14333 | u8 sr1; |
920a14b2 | 14334 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
9cce37f4 | 14335 | |
2b37c616 | 14336 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
52a05c30 | 14337 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14338 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14339 | sr1 = inb(VGA_SR_DATA); |
14340 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
52a05c30 | 14341 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
9cce37f4 JB |
14342 | udelay(300); |
14343 | ||
01f5a626 | 14344 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14345 | POSTING_READ(vga_reg); |
14346 | } | |
14347 | ||
f817586c DV |
14348 | void intel_modeset_init_hw(struct drm_device *dev) |
14349 | { | |
fac5e23e | 14350 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 14351 | |
4c75b940 | 14352 | intel_update_cdclk(dev_priv); |
bb0f4aab | 14353 | dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw; |
f817586c DV |
14354 | } |
14355 | ||
d93c0372 MR |
14356 | /* |
14357 | * Calculate what we think the watermarks should be for the state we've read | |
14358 | * out of the hardware and then immediately program those watermarks so that | |
14359 | * we ensure the hardware settings match our internal state. | |
14360 | * | |
14361 | * We can calculate what we think WM's should be by creating a duplicate of the | |
14362 | * current state (which was constructed during hardware readout) and running it | |
14363 | * through the atomic check code to calculate new watermark values in the | |
14364 | * state object. | |
14365 | */ | |
14366 | static void sanitize_watermarks(struct drm_device *dev) | |
14367 | { | |
14368 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14369 | struct drm_atomic_state *state; | |
ccf010fb | 14370 | struct intel_atomic_state *intel_state; |
d93c0372 MR |
14371 | struct drm_crtc *crtc; |
14372 | struct drm_crtc_state *cstate; | |
14373 | struct drm_modeset_acquire_ctx ctx; | |
14374 | int ret; | |
14375 | int i; | |
14376 | ||
14377 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 14378 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
14379 | return; |
14380 | ||
14381 | /* | |
14382 | * We need to hold connection_mutex before calling duplicate_state so | |
14383 | * that the connector loop is protected. | |
14384 | */ | |
14385 | drm_modeset_acquire_init(&ctx, 0); | |
14386 | retry: | |
0cd1262d | 14387 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
14388 | if (ret == -EDEADLK) { |
14389 | drm_modeset_backoff(&ctx); | |
14390 | goto retry; | |
14391 | } else if (WARN_ON(ret)) { | |
0cd1262d | 14392 | goto fail; |
d93c0372 MR |
14393 | } |
14394 | ||
14395 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
14396 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 14397 | goto fail; |
d93c0372 | 14398 | |
ccf010fb ML |
14399 | intel_state = to_intel_atomic_state(state); |
14400 | ||
ed4a6a7c MR |
14401 | /* |
14402 | * Hardware readout is the only time we don't want to calculate | |
14403 | * intermediate watermarks (since we don't trust the current | |
14404 | * watermarks). | |
14405 | */ | |
602ae835 VS |
14406 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
14407 | intel_state->skip_intermediate_wm = true; | |
ed4a6a7c | 14408 | |
d93c0372 MR |
14409 | ret = intel_atomic_check(dev, state); |
14410 | if (ret) { | |
14411 | /* | |
14412 | * If we fail here, it means that the hardware appears to be | |
14413 | * programmed in a way that shouldn't be possible, given our | |
14414 | * understanding of watermark requirements. This might mean a | |
14415 | * mistake in the hardware readout code or a mistake in the | |
14416 | * watermark calculations for a given platform. Raise a WARN | |
14417 | * so that this is noticeable. | |
14418 | * | |
14419 | * If this actually happens, we'll have to just leave the | |
14420 | * BIOS-programmed watermarks untouched and hope for the best. | |
14421 | */ | |
14422 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
b9a1b717 | 14423 | goto put_state; |
d93c0372 MR |
14424 | } |
14425 | ||
14426 | /* Write calculated watermark values back */ | |
aa5e9b47 | 14427 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
d93c0372 MR |
14428 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); |
14429 | ||
ed4a6a7c | 14430 | cs->wm.need_postvbl_update = true; |
ccf010fb | 14431 | dev_priv->display.optimize_watermarks(intel_state, cs); |
d93c0372 MR |
14432 | } |
14433 | ||
b9a1b717 | 14434 | put_state: |
0853695c | 14435 | drm_atomic_state_put(state); |
0cd1262d | 14436 | fail: |
d93c0372 MR |
14437 | drm_modeset_drop_locks(&ctx); |
14438 | drm_modeset_acquire_fini(&ctx); | |
14439 | } | |
14440 | ||
b079bd17 | 14441 | int intel_modeset_init(struct drm_device *dev) |
79e53945 | 14442 | { |
72e96d64 JL |
14443 | struct drm_i915_private *dev_priv = to_i915(dev); |
14444 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
8cc87b75 | 14445 | enum pipe pipe; |
46f297fb | 14446 | struct intel_crtc *crtc; |
79e53945 JB |
14447 | |
14448 | drm_mode_config_init(dev); | |
14449 | ||
14450 | dev->mode_config.min_width = 0; | |
14451 | dev->mode_config.min_height = 0; | |
14452 | ||
019d96cb DA |
14453 | dev->mode_config.preferred_depth = 24; |
14454 | dev->mode_config.prefer_shadow = 1; | |
14455 | ||
25bab385 TU |
14456 | dev->mode_config.allow_fb_modifiers = true; |
14457 | ||
e6ecefaa | 14458 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14459 | |
400c19d9 | 14460 | init_llist_head(&dev_priv->atomic_helper.free_list); |
eb955eee | 14461 | INIT_WORK(&dev_priv->atomic_helper.free_work, |
ba318c61 | 14462 | intel_atomic_helper_free_state_worker); |
eb955eee | 14463 | |
b690e96c JB |
14464 | intel_init_quirks(dev); |
14465 | ||
62d75df7 | 14466 | intel_init_pm(dev_priv); |
1fa61106 | 14467 | |
b7f05d4a | 14468 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
b079bd17 | 14469 | return 0; |
e3c74757 | 14470 | |
69f92f67 LW |
14471 | /* |
14472 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14473 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14474 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14475 | * indicates as much. | |
14476 | */ | |
6e266956 | 14477 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
69f92f67 LW |
14478 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
14479 | DREF_SSC1_ENABLE); | |
14480 | ||
14481 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
14482 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
14483 | bios_lvds_use_ssc ? "en" : "dis", | |
14484 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
14485 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
14486 | } | |
14487 | } | |
14488 | ||
5db94019 | 14489 | if (IS_GEN2(dev_priv)) { |
a6c45cf0 CW |
14490 | dev->mode_config.max_width = 2048; |
14491 | dev->mode_config.max_height = 2048; | |
5db94019 | 14492 | } else if (IS_GEN3(dev_priv)) { |
5e4d6fa7 KP |
14493 | dev->mode_config.max_width = 4096; |
14494 | dev->mode_config.max_height = 4096; | |
79e53945 | 14495 | } else { |
a6c45cf0 CW |
14496 | dev->mode_config.max_width = 8192; |
14497 | dev->mode_config.max_height = 8192; | |
79e53945 | 14498 | } |
068be561 | 14499 | |
2a307c2e JN |
14500 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
14501 | dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; | |
dc41c154 | 14502 | dev->mode_config.cursor_height = 1023; |
5db94019 | 14503 | } else if (IS_GEN2(dev_priv)) { |
068be561 DL |
14504 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14505 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14506 | } else { | |
14507 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14508 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14509 | } | |
14510 | ||
72e96d64 | 14511 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 14512 | |
28c97730 | 14513 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
b7f05d4a TU |
14514 | INTEL_INFO(dev_priv)->num_pipes, |
14515 | INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14516 | |
055e393f | 14517 | for_each_pipe(dev_priv, pipe) { |
b079bd17 VS |
14518 | int ret; |
14519 | ||
5ab0d85b | 14520 | ret = intel_crtc_init(dev_priv, pipe); |
b079bd17 VS |
14521 | if (ret) { |
14522 | drm_mode_config_cleanup(dev); | |
14523 | return ret; | |
14524 | } | |
79e53945 JB |
14525 | } |
14526 | ||
e72f9fbf | 14527 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14528 | |
5be6e334 VS |
14529 | intel_update_czclk(dev_priv); |
14530 | intel_modeset_init_hw(dev); | |
14531 | ||
b2045352 | 14532 | if (dev_priv->max_cdclk_freq == 0) |
4c75b940 | 14533 | intel_update_max_cdclk(dev_priv); |
b2045352 | 14534 | |
9cce37f4 | 14535 | /* Just disable it once at startup */ |
29b74b7f | 14536 | i915_disable_vga(dev_priv); |
c39055b0 | 14537 | intel_setup_outputs(dev_priv); |
11be49eb | 14538 | |
6e9f798d | 14539 | drm_modeset_lock_all(dev); |
aecd36b8 | 14540 | intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); |
6e9f798d | 14541 | drm_modeset_unlock_all(dev); |
46f297fb | 14542 | |
d3fcc808 | 14543 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
14544 | struct intel_initial_plane_config plane_config = {}; |
14545 | ||
46f297fb JB |
14546 | if (!crtc->active) |
14547 | continue; | |
14548 | ||
46f297fb | 14549 | /* |
46f297fb JB |
14550 | * Note that reserving the BIOS fb up front prevents us |
14551 | * from stuffing other stolen allocations like the ring | |
14552 | * on top. This prevents some ugliness at boot time, and | |
14553 | * can even allow for smooth boot transitions if the BIOS | |
14554 | * fb is large enough for the active pipe configuration. | |
14555 | */ | |
eeebeac5 ML |
14556 | dev_priv->display.get_initial_plane_config(crtc, |
14557 | &plane_config); | |
14558 | ||
14559 | /* | |
14560 | * If the fb is shared between multiple heads, we'll | |
14561 | * just get the first one. | |
14562 | */ | |
14563 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 14564 | } |
d93c0372 MR |
14565 | |
14566 | /* | |
14567 | * Make sure hardware watermarks really match the state we read out. | |
14568 | * Note that we need to do this after reconstructing the BIOS fb's | |
14569 | * since the watermark calculation done here will use pstate->fb. | |
14570 | */ | |
602ae835 VS |
14571 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
14572 | sanitize_watermarks(dev); | |
b079bd17 VS |
14573 | |
14574 | return 0; | |
2c7111db CW |
14575 | } |
14576 | ||
2ee0da16 VS |
14577 | void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) |
14578 | { | |
14579 | /* 640x480@60Hz, ~25175 kHz */ | |
14580 | struct dpll clock = { | |
14581 | .m1 = 18, | |
14582 | .m2 = 7, | |
14583 | .p1 = 13, | |
14584 | .p2 = 4, | |
14585 | .n = 2, | |
14586 | }; | |
14587 | u32 dpll, fp; | |
14588 | int i; | |
14589 | ||
14590 | WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154); | |
14591 | ||
14592 | DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n", | |
14593 | pipe_name(pipe), clock.vco, clock.dot); | |
14594 | ||
14595 | fp = i9xx_dpll_compute_fp(&clock); | |
14596 | dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) | | |
14597 | DPLL_VGA_MODE_DIS | | |
14598 | ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | | |
14599 | PLL_P2_DIVIDE_BY_4 | | |
14600 | PLL_REF_INPUT_DREFCLK | | |
14601 | DPLL_VCO_ENABLE; | |
14602 | ||
14603 | I915_WRITE(FP0(pipe), fp); | |
14604 | I915_WRITE(FP1(pipe), fp); | |
14605 | ||
14606 | I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); | |
14607 | I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); | |
14608 | I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); | |
14609 | I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); | |
14610 | I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); | |
14611 | I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); | |
14612 | I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); | |
14613 | ||
14614 | /* | |
14615 | * Apparently we need to have VGA mode enabled prior to changing | |
14616 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
14617 | * dividers, even though the register value does change. | |
14618 | */ | |
14619 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); | |
14620 | I915_WRITE(DPLL(pipe), dpll); | |
14621 | ||
14622 | /* Wait for the clocks to stabilize. */ | |
14623 | POSTING_READ(DPLL(pipe)); | |
14624 | udelay(150); | |
14625 | ||
14626 | /* The pixel multiplier can only be updated once the | |
14627 | * DPLL is enabled and the clocks are stable. | |
14628 | * | |
14629 | * So write it again. | |
14630 | */ | |
14631 | I915_WRITE(DPLL(pipe), dpll); | |
14632 | ||
14633 | /* We do this three times for luck */ | |
14634 | for (i = 0; i < 3 ; i++) { | |
14635 | I915_WRITE(DPLL(pipe), dpll); | |
14636 | POSTING_READ(DPLL(pipe)); | |
14637 | udelay(150); /* wait for warmup */ | |
14638 | } | |
14639 | ||
14640 | I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE); | |
14641 | POSTING_READ(PIPECONF(pipe)); | |
14642 | } | |
14643 | ||
14644 | void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) | |
14645 | { | |
14646 | DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n", | |
14647 | pipe_name(pipe)); | |
14648 | ||
14649 | assert_plane_disabled(dev_priv, PLANE_A); | |
14650 | assert_plane_disabled(dev_priv, PLANE_B); | |
14651 | ||
14652 | I915_WRITE(PIPECONF(pipe), 0); | |
14653 | POSTING_READ(PIPECONF(pipe)); | |
14654 | ||
14655 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) | |
14656 | DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe)); | |
14657 | ||
14658 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); | |
14659 | POSTING_READ(DPLL(pipe)); | |
14660 | } | |
14661 | ||
fa555837 DV |
14662 | static bool |
14663 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14664 | { | |
b7f05d4a | 14665 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
649636ef | 14666 | u32 val; |
fa555837 | 14667 | |
b7f05d4a | 14668 | if (INTEL_INFO(dev_priv)->num_pipes == 1) |
fa555837 DV |
14669 | return true; |
14670 | ||
649636ef | 14671 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
14672 | |
14673 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14674 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14675 | return false; | |
14676 | ||
14677 | return true; | |
14678 | } | |
14679 | ||
02e93c35 VS |
14680 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
14681 | { | |
14682 | struct drm_device *dev = crtc->base.dev; | |
14683 | struct intel_encoder *encoder; | |
14684 | ||
14685 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
14686 | return true; | |
14687 | ||
14688 | return false; | |
14689 | } | |
14690 | ||
496b0fc3 ML |
14691 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
14692 | { | |
14693 | struct drm_device *dev = encoder->base.dev; | |
14694 | struct intel_connector *connector; | |
14695 | ||
14696 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
14697 | return connector; | |
14698 | ||
14699 | return NULL; | |
14700 | } | |
14701 | ||
a168f5b3 | 14702 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
ecf837d9 | 14703 | enum pipe pch_transcoder) |
a168f5b3 VS |
14704 | { |
14705 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
ecf837d9 | 14706 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A); |
a168f5b3 VS |
14707 | } |
14708 | ||
aecd36b8 VS |
14709 | static void intel_sanitize_crtc(struct intel_crtc *crtc, |
14710 | struct drm_modeset_acquire_ctx *ctx) | |
24929352 DV |
14711 | { |
14712 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 14713 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 14714 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 14715 | |
24929352 | 14716 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
14717 | if (!transcoder_is_dsi(cpu_transcoder)) { |
14718 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
14719 | ||
14720 | I915_WRITE(reg, | |
14721 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
14722 | } | |
24929352 | 14723 | |
d3eaf884 | 14724 | /* restore vblank interrupts to correct state */ |
9625604c | 14725 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 14726 | if (crtc->active) { |
f9cd7b88 VS |
14727 | struct intel_plane *plane; |
14728 | ||
9625604c | 14729 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
14730 | |
14731 | /* Disable everything but the primary plane */ | |
14732 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
14733 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
14734 | continue; | |
14735 | ||
72259536 | 14736 | trace_intel_disable_plane(&plane->base, crtc); |
282dbf9b | 14737 | plane->disable_plane(plane, crtc); |
f9cd7b88 | 14738 | } |
9625604c | 14739 | } |
d3eaf884 | 14740 | |
24929352 | 14741 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14742 | * disable the crtc (and hence change the state) if it is wrong. Note |
14743 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
6315b5d3 | 14744 | if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { |
24929352 DV |
14745 | bool plane; |
14746 | ||
78108b7c VS |
14747 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
14748 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
14749 | |
14750 | /* Pipe has the wrong plane attached and the plane is active. | |
14751 | * Temporarily change the plane mapping and disable everything | |
14752 | * ... */ | |
14753 | plane = crtc->plane; | |
1d4258db | 14754 | crtc->base.primary->state->visible = true; |
24929352 | 14755 | crtc->plane = !plane; |
da1d0e26 | 14756 | intel_crtc_disable_noatomic(&crtc->base, ctx); |
24929352 | 14757 | crtc->plane = plane; |
24929352 | 14758 | } |
24929352 DV |
14759 | |
14760 | /* Adjust the state of the output pipe according to whether we | |
14761 | * have active connectors/encoders. */ | |
842e0307 | 14762 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
da1d0e26 | 14763 | intel_crtc_disable_noatomic(&crtc->base, ctx); |
24929352 | 14764 | |
49cff963 | 14765 | if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { |
4cc31489 DV |
14766 | /* |
14767 | * We start out with underrun reporting disabled to avoid races. | |
14768 | * For correct bookkeeping mark this on active crtcs. | |
14769 | * | |
c5ab3bc0 DV |
14770 | * Also on gmch platforms we dont have any hardware bits to |
14771 | * disable the underrun reporting. Which means we need to start | |
14772 | * out with underrun reporting disabled also on inactive pipes, | |
14773 | * since otherwise we'll complain about the garbage we read when | |
14774 | * e.g. coming up after runtime pm. | |
14775 | * | |
4cc31489 DV |
14776 | * No protection against concurrent access is required - at |
14777 | * worst a fifo underrun happens which also sets this to false. | |
14778 | */ | |
14779 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
14780 | /* |
14781 | * We track the PCH trancoder underrun reporting state | |
14782 | * within the crtc. With crtc for pipe A housing the underrun | |
14783 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
14784 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
14785 | * and marking underrun reporting as disabled for the non-existing | |
14786 | * PCH transcoders B and C would prevent enabling the south | |
14787 | * error interrupt (see cpt_can_enable_serr_int()). | |
14788 | */ | |
ecf837d9 | 14789 | if (has_pch_trancoder(dev_priv, crtc->pipe)) |
a168f5b3 | 14790 | crtc->pch_fifo_underrun_disabled = true; |
4cc31489 | 14791 | } |
24929352 DV |
14792 | } |
14793 | ||
14794 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
14795 | { | |
14796 | struct intel_connector *connector; | |
24929352 DV |
14797 | |
14798 | /* We need to check both for a crtc link (meaning that the | |
14799 | * encoder is active and trying to read from a pipe) and the | |
14800 | * pipe itself being active. */ | |
14801 | bool has_active_crtc = encoder->base.crtc && | |
14802 | to_intel_crtc(encoder->base.crtc)->active; | |
14803 | ||
496b0fc3 ML |
14804 | connector = intel_encoder_find_connector(encoder); |
14805 | if (connector && !has_active_crtc) { | |
24929352 DV |
14806 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
14807 | encoder->base.base.id, | |
8e329a03 | 14808 | encoder->base.name); |
24929352 DV |
14809 | |
14810 | /* Connector is active, but has no active pipe. This is | |
14811 | * fallout from our resume register restoring. Disable | |
14812 | * the encoder manually again. */ | |
14813 | if (encoder->base.crtc) { | |
fd6bbda9 ML |
14814 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
14815 | ||
24929352 DV |
14816 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
14817 | encoder->base.base.id, | |
8e329a03 | 14818 | encoder->base.name); |
fd6bbda9 | 14819 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
a62d1497 | 14820 | if (encoder->post_disable) |
fd6bbda9 | 14821 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
24929352 | 14822 | } |
7f1950fb | 14823 | encoder->base.crtc = NULL; |
24929352 DV |
14824 | |
14825 | /* Inconsistent output/port/pipe state happens presumably due to | |
14826 | * a bug in one of the get_hw_state functions. Or someplace else | |
14827 | * in our code, like the register restore mess on resume. Clamp | |
14828 | * things to off as a safer default. */ | |
fd6bbda9 ML |
14829 | |
14830 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14831 | connector->base.encoder = NULL; | |
24929352 DV |
14832 | } |
14833 | /* Enabled encoders without active connectors will be fixed in | |
14834 | * the crtc fixup. */ | |
14835 | } | |
14836 | ||
29b74b7f | 14837 | void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) |
0fde901f | 14838 | { |
920a14b2 | 14839 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
0fde901f | 14840 | |
04098753 ID |
14841 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
14842 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
29b74b7f | 14843 | i915_disable_vga(dev_priv); |
04098753 ID |
14844 | } |
14845 | } | |
14846 | ||
29b74b7f | 14847 | void i915_redisable_vga(struct drm_i915_private *dev_priv) |
04098753 | 14848 | { |
8dc8a27c PZ |
14849 | /* This function can be called both from intel_modeset_setup_hw_state or |
14850 | * at a very early point in our resume sequence, where the power well | |
14851 | * structures are not yet restored. Since this function is at a very | |
14852 | * paranoid "someone might have enabled VGA while we were not looking" | |
14853 | * level, just check if the power well is enabled instead of trying to | |
14854 | * follow the "don't touch the power well if we don't need it" policy | |
14855 | * the rest of the driver uses. */ | |
6392f847 | 14856 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
14857 | return; |
14858 | ||
29b74b7f | 14859 | i915_redisable_vga_power_on(dev_priv); |
6392f847 ID |
14860 | |
14861 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
14862 | } |
14863 | ||
f9cd7b88 | 14864 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 14865 | { |
f9cd7b88 | 14866 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 14867 | |
f9cd7b88 | 14868 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
14869 | } |
14870 | ||
f9cd7b88 VS |
14871 | /* FIXME read out full plane state for all planes */ |
14872 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 14873 | { |
e9728bd8 VS |
14874 | struct intel_plane *primary = to_intel_plane(crtc->base.primary); |
14875 | bool visible; | |
d032ffa0 | 14876 | |
e9728bd8 | 14877 | visible = crtc->active && primary_get_hw_state(primary); |
b26d3ea3 | 14878 | |
e9728bd8 VS |
14879 | intel_set_plane_visible(to_intel_crtc_state(crtc->base.state), |
14880 | to_intel_plane_state(primary->base.state), | |
14881 | visible); | |
98ec7739 VS |
14882 | } |
14883 | ||
30e984df | 14884 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 14885 | { |
fac5e23e | 14886 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 14887 | enum pipe pipe; |
24929352 DV |
14888 | struct intel_crtc *crtc; |
14889 | struct intel_encoder *encoder; | |
14890 | struct intel_connector *connector; | |
f9e905ca | 14891 | struct drm_connector_list_iter conn_iter; |
5358901f | 14892 | int i; |
24929352 | 14893 | |
565602d7 ML |
14894 | dev_priv->active_crtcs = 0; |
14895 | ||
d3fcc808 | 14896 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
14897 | struct intel_crtc_state *crtc_state = |
14898 | to_intel_crtc_state(crtc->base.state); | |
3b117c8f | 14899 | |
ec2dc6a0 | 14900 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
14901 | memset(crtc_state, 0, sizeof(*crtc_state)); |
14902 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 14903 | |
565602d7 ML |
14904 | crtc_state->base.active = crtc_state->base.enable = |
14905 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
14906 | ||
14907 | crtc->base.enabled = crtc_state->base.enable; | |
14908 | crtc->active = crtc_state->base.active; | |
14909 | ||
aca1ebf4 | 14910 | if (crtc_state->base.active) |
565602d7 ML |
14911 | dev_priv->active_crtcs |= 1 << crtc->pipe; |
14912 | ||
f9cd7b88 | 14913 | readout_plane_state(crtc); |
24929352 | 14914 | |
78108b7c VS |
14915 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
14916 | crtc->base.base.id, crtc->base.name, | |
a8cd6da0 | 14917 | enableddisabled(crtc_state->base.active)); |
24929352 DV |
14918 | } |
14919 | ||
5358901f DV |
14920 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14921 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14922 | ||
2edd6443 | 14923 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
2c42e535 ACO |
14924 | &pll->state.hw_state); |
14925 | pll->state.crtc_mask = 0; | |
d3fcc808 | 14926 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
14927 | struct intel_crtc_state *crtc_state = |
14928 | to_intel_crtc_state(crtc->base.state); | |
14929 | ||
14930 | if (crtc_state->base.active && | |
14931 | crtc_state->shared_dpll == pll) | |
2c42e535 | 14932 | pll->state.crtc_mask |= 1 << crtc->pipe; |
5358901f | 14933 | } |
2c42e535 | 14934 | pll->active_mask = pll->state.crtc_mask; |
5358901f | 14935 | |
1e6f2ddc | 14936 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
2c42e535 | 14937 | pll->name, pll->state.crtc_mask, pll->on); |
5358901f DV |
14938 | } |
14939 | ||
b2784e15 | 14940 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14941 | pipe = 0; |
14942 | ||
14943 | if (encoder->get_hw_state(encoder, &pipe)) { | |
a8cd6da0 VS |
14944 | struct intel_crtc_state *crtc_state; |
14945 | ||
98187836 | 14946 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a8cd6da0 | 14947 | crtc_state = to_intel_crtc_state(crtc->base.state); |
e2af48c6 | 14948 | |
045ac3b5 | 14949 | encoder->base.crtc = &crtc->base; |
a8cd6da0 VS |
14950 | crtc_state->output_types |= 1 << encoder->type; |
14951 | encoder->get_config(encoder, crtc_state); | |
24929352 DV |
14952 | } else { |
14953 | encoder->base.crtc = NULL; | |
14954 | } | |
14955 | ||
6f2bcceb | 14956 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
08c4d7fc TU |
14957 | encoder->base.base.id, encoder->base.name, |
14958 | enableddisabled(encoder->base.crtc), | |
6f2bcceb | 14959 | pipe_name(pipe)); |
24929352 DV |
14960 | } |
14961 | ||
f9e905ca DV |
14962 | drm_connector_list_iter_begin(dev, &conn_iter); |
14963 | for_each_intel_connector_iter(connector, &conn_iter) { | |
24929352 DV |
14964 | if (connector->get_hw_state(connector)) { |
14965 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
14966 | |
14967 | encoder = connector->encoder; | |
14968 | connector->base.encoder = &encoder->base; | |
14969 | ||
14970 | if (encoder->base.crtc && | |
14971 | encoder->base.crtc->state->active) { | |
14972 | /* | |
14973 | * This has to be done during hardware readout | |
14974 | * because anything calling .crtc_disable may | |
14975 | * rely on the connector_mask being accurate. | |
14976 | */ | |
14977 | encoder->base.crtc->state->connector_mask |= | |
14978 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
14979 | encoder->base.crtc->state->encoder_mask |= |
14980 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
14981 | } |
14982 | ||
24929352 DV |
14983 | } else { |
14984 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14985 | connector->base.encoder = NULL; | |
14986 | } | |
14987 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
08c4d7fc TU |
14988 | connector->base.base.id, connector->base.name, |
14989 | enableddisabled(connector->base.encoder)); | |
24929352 | 14990 | } |
f9e905ca | 14991 | drm_connector_list_iter_end(&conn_iter); |
7f4c6284 VS |
14992 | |
14993 | for_each_intel_crtc(dev, crtc) { | |
a8cd6da0 VS |
14994 | struct intel_crtc_state *crtc_state = |
14995 | to_intel_crtc_state(crtc->base.state); | |
d305e061 | 14996 | int min_cdclk = 0; |
aca1ebf4 | 14997 | |
7f4c6284 | 14998 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); |
a8cd6da0 VS |
14999 | if (crtc_state->base.active) { |
15000 | intel_mode_from_pipe_config(&crtc->base.mode, crtc_state); | |
15001 | intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state); | |
7f4c6284 VS |
15002 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); |
15003 | ||
15004 | /* | |
15005 | * The initial mode needs to be set in order to keep | |
15006 | * the atomic core happy. It wants a valid mode if the | |
15007 | * crtc's enabled, so we do the above call. | |
15008 | * | |
7800fb69 DV |
15009 | * But we don't set all the derived state fully, hence |
15010 | * set a flag to indicate that a full recalculation is | |
15011 | * needed on the next commit. | |
7f4c6284 | 15012 | */ |
a8cd6da0 | 15013 | crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED; |
9eca6832 | 15014 | |
a7d1b3f4 VS |
15015 | intel_crtc_compute_pixel_rate(crtc_state); |
15016 | ||
9c61de4c | 15017 | if (dev_priv->display.modeset_calc_cdclk) { |
d305e061 | 15018 | min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); |
9c61de4c VS |
15019 | if (WARN_ON(min_cdclk < 0)) |
15020 | min_cdclk = 0; | |
15021 | } | |
aca1ebf4 | 15022 | |
5caa0fea DV |
15023 | drm_calc_timestamping_constants(&crtc->base, |
15024 | &crtc_state->base.adjusted_mode); | |
9eca6832 | 15025 | update_scanline_offset(crtc); |
7f4c6284 | 15026 | } |
e3b247da | 15027 | |
d305e061 | 15028 | dev_priv->min_cdclk[crtc->pipe] = min_cdclk; |
aca1ebf4 | 15029 | |
a8cd6da0 | 15030 | intel_pipe_config_sanity_check(dev_priv, crtc_state); |
7f4c6284 | 15031 | } |
30e984df DV |
15032 | } |
15033 | ||
62b69566 ACO |
15034 | static void |
15035 | get_encoder_power_domains(struct drm_i915_private *dev_priv) | |
15036 | { | |
15037 | struct intel_encoder *encoder; | |
15038 | ||
15039 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
15040 | u64 get_domains; | |
15041 | enum intel_display_power_domain domain; | |
15042 | ||
15043 | if (!encoder->get_power_domains) | |
15044 | continue; | |
15045 | ||
15046 | get_domains = encoder->get_power_domains(encoder); | |
15047 | for_each_power_domain(domain, get_domains) | |
15048 | intel_display_power_get(dev_priv, domain); | |
15049 | } | |
15050 | } | |
15051 | ||
043e9bda ML |
15052 | /* Scan out the current hw modeset state, |
15053 | * and sanitizes it to the current state | |
15054 | */ | |
15055 | static void | |
aecd36b8 VS |
15056 | intel_modeset_setup_hw_state(struct drm_device *dev, |
15057 | struct drm_modeset_acquire_ctx *ctx) | |
30e984df | 15058 | { |
fac5e23e | 15059 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 15060 | enum pipe pipe; |
30e984df DV |
15061 | struct intel_crtc *crtc; |
15062 | struct intel_encoder *encoder; | |
35c95375 | 15063 | int i; |
30e984df | 15064 | |
6ac43272 VS |
15065 | if (IS_HASWELL(dev_priv)) { |
15066 | /* | |
15067 | * WaRsPkgCStateDisplayPMReq:hsw | |
15068 | * System hang if this isn't done before disabling all planes! | |
15069 | */ | |
15070 | I915_WRITE(CHICKEN_PAR1_1, | |
15071 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
15072 | } | |
15073 | ||
30e984df | 15074 | intel_modeset_readout_hw_state(dev); |
24929352 DV |
15075 | |
15076 | /* HW state is read out, now we need to sanitize this mess. */ | |
62b69566 ACO |
15077 | get_encoder_power_domains(dev_priv); |
15078 | ||
b2784e15 | 15079 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15080 | intel_sanitize_encoder(encoder); |
15081 | } | |
15082 | ||
055e393f | 15083 | for_each_pipe(dev_priv, pipe) { |
98187836 | 15084 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 15085 | |
aecd36b8 | 15086 | intel_sanitize_crtc(crtc, ctx); |
6e3c9717 ACO |
15087 | intel_dump_pipe_config(crtc, crtc->config, |
15088 | "[setup_hw_state]"); | |
24929352 | 15089 | } |
9a935856 | 15090 | |
d29b2f9d ACO |
15091 | intel_modeset_update_connector_atomic_state(dev); |
15092 | ||
35c95375 DV |
15093 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15094 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15095 | ||
2dd66ebd | 15096 | if (!pll->on || pll->active_mask) |
35c95375 DV |
15097 | continue; |
15098 | ||
15099 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15100 | ||
2edd6443 | 15101 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
15102 | pll->on = false; |
15103 | } | |
15104 | ||
04548cba VS |
15105 | if (IS_G4X(dev_priv)) { |
15106 | g4x_wm_get_hw_state(dev); | |
15107 | g4x_wm_sanitize(dev_priv); | |
15108 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
6eb1a681 | 15109 | vlv_wm_get_hw_state(dev); |
602ae835 | 15110 | vlv_wm_sanitize(dev_priv); |
a029fa4d | 15111 | } else if (INTEL_GEN(dev_priv) >= 9) { |
3078999f | 15112 | skl_wm_get_hw_state(dev); |
602ae835 | 15113 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
243e6a44 | 15114 | ilk_wm_get_hw_state(dev); |
602ae835 | 15115 | } |
292b990e ML |
15116 | |
15117 | for_each_intel_crtc(dev, crtc) { | |
d8fc70b7 | 15118 | u64 put_domains; |
292b990e | 15119 | |
74bff5f9 | 15120 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15121 | if (WARN_ON(put_domains)) |
15122 | modeset_put_power_domains(dev_priv, put_domains); | |
15123 | } | |
15124 | intel_display_set_init_power(dev_priv, false); | |
010cf73d | 15125 | |
8d8c386c ID |
15126 | intel_power_domains_verify_state(dev_priv); |
15127 | ||
010cf73d | 15128 | intel_fbc_init_pipe_state(dev_priv); |
043e9bda | 15129 | } |
7d0bc1ea | 15130 | |
043e9bda ML |
15131 | void intel_display_resume(struct drm_device *dev) |
15132 | { | |
e2c8b870 ML |
15133 | struct drm_i915_private *dev_priv = to_i915(dev); |
15134 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15135 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15136 | int ret; |
f30da187 | 15137 | |
e2c8b870 | 15138 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
15139 | if (state) |
15140 | state->acquire_ctx = &ctx; | |
043e9bda | 15141 | |
e2c8b870 | 15142 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15143 | |
73974893 ML |
15144 | while (1) { |
15145 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
15146 | if (ret != -EDEADLK) | |
15147 | break; | |
043e9bda | 15148 | |
e2c8b870 | 15149 | drm_modeset_backoff(&ctx); |
e2c8b870 | 15150 | } |
043e9bda | 15151 | |
73974893 | 15152 | if (!ret) |
581e49fe | 15153 | ret = __intel_display_resume(dev, state, &ctx); |
73974893 | 15154 | |
2503a0fe | 15155 | intel_enable_ipc(dev_priv); |
e2c8b870 ML |
15156 | drm_modeset_drop_locks(&ctx); |
15157 | drm_modeset_acquire_fini(&ctx); | |
043e9bda | 15158 | |
0853695c | 15159 | if (ret) |
e2c8b870 | 15160 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
3c5e37f1 CW |
15161 | if (state) |
15162 | drm_atomic_state_put(state); | |
2c7111db CW |
15163 | } |
15164 | ||
15165 | void intel_modeset_gem_init(struct drm_device *dev) | |
15166 | { | |
dc97997a | 15167 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 15168 | |
dc97997a | 15169 | intel_init_gt_powersave(dev_priv); |
ae48434c | 15170 | |
6ac43272 VS |
15171 | intel_init_clock_gating(dev_priv); |
15172 | ||
1ee8da6d | 15173 | intel_setup_overlay(dev_priv); |
1ebaa0b9 CW |
15174 | } |
15175 | ||
15176 | int intel_connector_register(struct drm_connector *connector) | |
15177 | { | |
15178 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
15179 | int ret; | |
15180 | ||
15181 | ret = intel_backlight_device_register(intel_connector); | |
15182 | if (ret) | |
15183 | goto err; | |
15184 | ||
15185 | return 0; | |
0962c3c9 | 15186 | |
1ebaa0b9 CW |
15187 | err: |
15188 | return ret; | |
79e53945 JB |
15189 | } |
15190 | ||
c191eca1 | 15191 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 15192 | { |
e63d87c0 | 15193 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 15194 | |
e63d87c0 | 15195 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 15196 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
15197 | } |
15198 | ||
713946d1 MN |
15199 | static void intel_hpd_poll_fini(struct drm_device *dev) |
15200 | { | |
15201 | struct intel_connector *connector; | |
15202 | struct drm_connector_list_iter conn_iter; | |
15203 | ||
15204 | /* First disable polling... */ | |
15205 | drm_kms_helper_poll_fini(dev); | |
15206 | ||
15207 | /* Then kill the work that may have been queued by hpd. */ | |
15208 | drm_connector_list_iter_begin(dev, &conn_iter); | |
15209 | for_each_intel_connector_iter(connector, &conn_iter) { | |
15210 | if (connector->modeset_retry_work.func) | |
15211 | cancel_work_sync(&connector->modeset_retry_work); | |
15212 | } | |
15213 | drm_connector_list_iter_end(&conn_iter); | |
15214 | } | |
15215 | ||
79e53945 JB |
15216 | void intel_modeset_cleanup(struct drm_device *dev) |
15217 | { | |
fac5e23e | 15218 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 15219 | |
eb955eee CW |
15220 | flush_work(&dev_priv->atomic_helper.free_work); |
15221 | WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); | |
15222 | ||
dc97997a | 15223 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 15224 | |
fd0c0642 DV |
15225 | /* |
15226 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15227 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15228 | * experience fancy races otherwise. |
15229 | */ | |
2aeb7d3a | 15230 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15231 | |
fd0c0642 DV |
15232 | /* |
15233 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15234 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15235 | */ | |
713946d1 | 15236 | intel_hpd_poll_fini(dev); |
fd0c0642 | 15237 | |
4f256d82 DV |
15238 | /* poll work can call into fbdev, hence clean that up afterwards */ |
15239 | intel_fbdev_fini(dev_priv); | |
15240 | ||
723bfd70 JB |
15241 | intel_unregister_dsm_handler(); |
15242 | ||
c937ab3e | 15243 | intel_fbc_global_disable(dev_priv); |
69341a5e | 15244 | |
1630fe75 CW |
15245 | /* flush any delayed tasks or pending work */ |
15246 | flush_scheduled_work(); | |
15247 | ||
79e53945 | 15248 | drm_mode_config_cleanup(dev); |
4d7bb011 | 15249 | |
1ee8da6d | 15250 | intel_cleanup_overlay(dev_priv); |
ae48434c | 15251 | |
dc97997a | 15252 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 | 15253 | |
40196446 | 15254 | intel_teardown_gmbus(dev_priv); |
79e53945 JB |
15255 | } |
15256 | ||
df0e9248 CW |
15257 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15258 | struct intel_encoder *encoder) | |
15259 | { | |
15260 | connector->encoder = encoder; | |
15261 | drm_mode_connector_attach_encoder(&connector->base, | |
15262 | &encoder->base); | |
79e53945 | 15263 | } |
28d52043 DA |
15264 | |
15265 | /* | |
15266 | * set vga decode state - true == enable VGA decode | |
15267 | */ | |
6315b5d3 | 15268 | int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) |
28d52043 | 15269 | { |
6315b5d3 | 15270 | unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15271 | u16 gmch_ctrl; |
15272 | ||
75fa041d CW |
15273 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15274 | DRM_ERROR("failed to read control word\n"); | |
15275 | return -EIO; | |
15276 | } | |
15277 | ||
c0cc8a55 CW |
15278 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15279 | return 0; | |
15280 | ||
28d52043 DA |
15281 | if (state) |
15282 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15283 | else | |
15284 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15285 | |
15286 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15287 | DRM_ERROR("failed to write control word\n"); | |
15288 | return -EIO; | |
15289 | } | |
15290 | ||
28d52043 DA |
15291 | return 0; |
15292 | } | |
c4a1d9e4 | 15293 | |
98a2f411 CW |
15294 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
15295 | ||
c4a1d9e4 | 15296 | struct intel_display_error_state { |
ff57f1b0 PZ |
15297 | |
15298 | u32 power_well_driver; | |
15299 | ||
63b66e5b CW |
15300 | int num_transcoders; |
15301 | ||
c4a1d9e4 CW |
15302 | struct intel_cursor_error_state { |
15303 | u32 control; | |
15304 | u32 position; | |
15305 | u32 base; | |
15306 | u32 size; | |
52331309 | 15307 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15308 | |
15309 | struct intel_pipe_error_state { | |
ddf9c536 | 15310 | bool power_domain_on; |
c4a1d9e4 | 15311 | u32 source; |
f301b1e1 | 15312 | u32 stat; |
52331309 | 15313 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15314 | |
15315 | struct intel_plane_error_state { | |
15316 | u32 control; | |
15317 | u32 stride; | |
15318 | u32 size; | |
15319 | u32 pos; | |
15320 | u32 addr; | |
15321 | u32 surface; | |
15322 | u32 tile_offset; | |
52331309 | 15323 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15324 | |
15325 | struct intel_transcoder_error_state { | |
ddf9c536 | 15326 | bool power_domain_on; |
63b66e5b CW |
15327 | enum transcoder cpu_transcoder; |
15328 | ||
15329 | u32 conf; | |
15330 | ||
15331 | u32 htotal; | |
15332 | u32 hblank; | |
15333 | u32 hsync; | |
15334 | u32 vtotal; | |
15335 | u32 vblank; | |
15336 | u32 vsync; | |
15337 | } transcoder[4]; | |
c4a1d9e4 CW |
15338 | }; |
15339 | ||
15340 | struct intel_display_error_state * | |
c033666a | 15341 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 15342 | { |
c4a1d9e4 | 15343 | struct intel_display_error_state *error; |
63b66e5b CW |
15344 | int transcoders[] = { |
15345 | TRANSCODER_A, | |
15346 | TRANSCODER_B, | |
15347 | TRANSCODER_C, | |
15348 | TRANSCODER_EDP, | |
15349 | }; | |
c4a1d9e4 CW |
15350 | int i; |
15351 | ||
c033666a | 15352 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
15353 | return NULL; |
15354 | ||
9d1cb914 | 15355 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15356 | if (error == NULL) |
15357 | return NULL; | |
15358 | ||
c033666a | 15359 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
9c3a16c8 ID |
15360 | error->power_well_driver = |
15361 | I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)); | |
ff57f1b0 | 15362 | |
055e393f | 15363 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15364 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15365 | __intel_display_power_is_enabled(dev_priv, |
15366 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15367 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15368 | continue; |
15369 | ||
5efb3e28 VS |
15370 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15371 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15372 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15373 | |
15374 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15375 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 15376 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 15377 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15378 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15379 | } | |
c033666a | 15380 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 15381 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 15382 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
15383 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
15384 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15385 | } | |
15386 | ||
c4a1d9e4 | 15387 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15388 | |
c033666a | 15389 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 15390 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15391 | } |
15392 | ||
4d1de975 | 15393 | /* Note: this does not include DSI transcoders. */ |
c033666a | 15394 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 15395 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
15396 | error->num_transcoders++; /* Account for eDP. */ |
15397 | ||
15398 | for (i = 0; i < error->num_transcoders; i++) { | |
15399 | enum transcoder cpu_transcoder = transcoders[i]; | |
15400 | ||
ddf9c536 | 15401 | error->transcoder[i].power_domain_on = |
f458ebbc | 15402 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15403 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15404 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15405 | continue; |
15406 | ||
63b66e5b CW |
15407 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15408 | ||
15409 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15410 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15411 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15412 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15413 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15414 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15415 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15416 | } |
15417 | ||
15418 | return error; | |
15419 | } | |
15420 | ||
edc3d884 MK |
15421 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15422 | ||
c4a1d9e4 | 15423 | void |
edc3d884 | 15424 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15425 | struct intel_display_error_state *error) |
15426 | { | |
5a4c6f1b | 15427 | struct drm_i915_private *dev_priv = m->i915; |
c4a1d9e4 CW |
15428 | int i; |
15429 | ||
63b66e5b CW |
15430 | if (!error) |
15431 | return; | |
15432 | ||
b7f05d4a | 15433 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); |
8652744b | 15434 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 15435 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15436 | error->power_well_driver); |
055e393f | 15437 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15438 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 15439 | err_printf(m, " Power: %s\n", |
87ad3212 | 15440 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 15441 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15442 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15443 | |
15444 | err_printf(m, "Plane [%d]:\n", i); | |
15445 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15446 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
5f56d5f9 | 15447 | if (INTEL_GEN(dev_priv) <= 3) { |
edc3d884 MK |
15448 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15449 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15450 | } |
772c2a51 | 15451 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 15452 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
5f56d5f9 | 15453 | if (INTEL_GEN(dev_priv) >= 4) { |
edc3d884 MK |
15454 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15455 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15456 | } |
15457 | ||
edc3d884 MK |
15458 | err_printf(m, "Cursor [%d]:\n", i); |
15459 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15460 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15461 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15462 | } |
63b66e5b CW |
15463 | |
15464 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 15465 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 15466 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 15467 | err_printf(m, " Power: %s\n", |
87ad3212 | 15468 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
15469 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15470 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15471 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15472 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15473 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15474 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15475 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15476 | } | |
c4a1d9e4 | 15477 | } |
98a2f411 CW |
15478 | |
15479 | #endif |