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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
fd8e058a AG |
47 | #include <linux/reservation.h> |
48 | #include <linux/dma-buf.h> | |
79e53945 | 49 | |
465c120c | 50 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 51 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
52 | DRM_FORMAT_C8, |
53 | DRM_FORMAT_RGB565, | |
465c120c | 54 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 55 | DRM_FORMAT_XRGB8888, |
465c120c MR |
56 | }; |
57 | ||
58 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 59 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
60 | DRM_FORMAT_C8, |
61 | DRM_FORMAT_RGB565, | |
62 | DRM_FORMAT_XRGB8888, | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_XRGB2101010, | |
65 | DRM_FORMAT_XBGR2101010, | |
66 | }; | |
67 | ||
68 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
69 | DRM_FORMAT_C8, |
70 | DRM_FORMAT_RGB565, | |
71 | DRM_FORMAT_XRGB8888, | |
465c120c | 72 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 73 | DRM_FORMAT_ARGB8888, |
465c120c MR |
74 | DRM_FORMAT_ABGR8888, |
75 | DRM_FORMAT_XRGB2101010, | |
465c120c | 76 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
77 | DRM_FORMAT_YUYV, |
78 | DRM_FORMAT_YVYU, | |
79 | DRM_FORMAT_UYVY, | |
80 | DRM_FORMAT_VYUY, | |
465c120c MR |
81 | }; |
82 | ||
3d7d6510 MR |
83 | /* Cursor formats */ |
84 | static const uint32_t intel_cursor_formats[] = { | |
85 | DRM_FORMAT_ARGB8888, | |
86 | }; | |
87 | ||
f1f644dc | 88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 89 | struct intel_crtc_state *pipe_config); |
18442d08 | 90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
f1f644dc | 92 | |
eb1bfe80 JB |
93 | static int intel_framebuffer_init(struct drm_device *dev, |
94 | struct intel_framebuffer *ifb, | |
95 | struct drm_mode_fb_cmd2 *mode_cmd, | |
96 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
97 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
98 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 99 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
100 | struct intel_link_m_n *m_n, |
101 | struct intel_link_m_n *m2_n2); | |
29407aab | 102 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
103 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
104 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 105 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 106 | const struct intel_crtc_state *pipe_config); |
d288f65f | 107 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
109 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
110 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
111 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
112 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
113 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
114 | int num_connectors); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
200757f5 | 119 | static void intel_pre_disable_primary(struct drm_crtc *crtc); |
e7457a9a | 120 | |
79e53945 | 121 | typedef struct { |
0206e353 | 122 | int min, max; |
79e53945 JB |
123 | } intel_range_t; |
124 | ||
125 | typedef struct { | |
0206e353 AJ |
126 | int dot_limit; |
127 | int p2_slow, p2_fast; | |
79e53945 JB |
128 | } intel_p2_t; |
129 | ||
d4906093 ML |
130 | typedef struct intel_limit intel_limit_t; |
131 | struct intel_limit { | |
0206e353 AJ |
132 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
133 | intel_p2_t p2; | |
d4906093 | 134 | }; |
79e53945 | 135 | |
bfa7df01 VS |
136 | /* returns HPLL frequency in kHz */ |
137 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
138 | { | |
139 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
140 | ||
141 | /* Obtain SKU information */ | |
142 | mutex_lock(&dev_priv->sb_lock); | |
143 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
144 | CCK_FUSE_HPLL_FREQ_MASK; | |
145 | mutex_unlock(&dev_priv->sb_lock); | |
146 | ||
147 | return vco_freq[hpll_freq] * 1000; | |
148 | } | |
149 | ||
150 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
151 | const char *name, u32 reg) | |
152 | { | |
153 | u32 val; | |
154 | int divider; | |
155 | ||
156 | if (dev_priv->hpll_freq == 0) | |
157 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
158 | ||
159 | mutex_lock(&dev_priv->sb_lock); | |
160 | val = vlv_cck_read(dev_priv, reg); | |
161 | mutex_unlock(&dev_priv->sb_lock); | |
162 | ||
163 | divider = val & CCK_FREQUENCY_VALUES; | |
164 | ||
165 | WARN((val & CCK_FREQUENCY_STATUS) != | |
166 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
167 | "%s change in progress\n", name); | |
168 | ||
169 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
170 | } | |
171 | ||
d2acd215 DV |
172 | int |
173 | intel_pch_rawclk(struct drm_device *dev) | |
174 | { | |
175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
176 | ||
177 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
178 | ||
179 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
180 | } | |
181 | ||
79e50a4f JN |
182 | /* hrawclock is 1/4 the FSB frequency */ |
183 | int intel_hrawclk(struct drm_device *dev) | |
184 | { | |
185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
186 | uint32_t clkcfg; | |
187 | ||
188 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ | |
666a4537 | 189 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
79e50a4f JN |
190 | return 200; |
191 | ||
192 | clkcfg = I915_READ(CLKCFG); | |
193 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
194 | case CLKCFG_FSB_400: | |
195 | return 100; | |
196 | case CLKCFG_FSB_533: | |
197 | return 133; | |
198 | case CLKCFG_FSB_667: | |
199 | return 166; | |
200 | case CLKCFG_FSB_800: | |
201 | return 200; | |
202 | case CLKCFG_FSB_1067: | |
203 | return 266; | |
204 | case CLKCFG_FSB_1333: | |
205 | return 333; | |
206 | /* these two are just a guess; one of them might be right */ | |
207 | case CLKCFG_FSB_1600: | |
208 | case CLKCFG_FSB_1600_ALT: | |
209 | return 400; | |
210 | default: | |
211 | return 133; | |
212 | } | |
213 | } | |
214 | ||
bfa7df01 VS |
215 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
216 | { | |
666a4537 | 217 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
218 | return; |
219 | ||
220 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
221 | CCK_CZ_CLOCK_CONTROL); | |
222 | ||
223 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
224 | } | |
225 | ||
021357ac CW |
226 | static inline u32 /* units of 100MHz */ |
227 | intel_fdi_link_freq(struct drm_device *dev) | |
228 | { | |
8b99e68c CW |
229 | if (IS_GEN5(dev)) { |
230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
232 | } else | |
233 | return 27; | |
021357ac CW |
234 | } |
235 | ||
5d536e28 | 236 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 237 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 238 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 239 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
240 | .m = { .min = 96, .max = 140 }, |
241 | .m1 = { .min = 18, .max = 26 }, | |
242 | .m2 = { .min = 6, .max = 16 }, | |
243 | .p = { .min = 4, .max = 128 }, | |
244 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
245 | .p2 = { .dot_limit = 165000, |
246 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
247 | }; |
248 | ||
5d536e28 DV |
249 | static const intel_limit_t intel_limits_i8xx_dvo = { |
250 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 251 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 252 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
253 | .m = { .min = 96, .max = 140 }, |
254 | .m1 = { .min = 18, .max = 26 }, | |
255 | .m2 = { .min = 6, .max = 16 }, | |
256 | .p = { .min = 4, .max = 128 }, | |
257 | .p1 = { .min = 2, .max = 33 }, | |
258 | .p2 = { .dot_limit = 165000, | |
259 | .p2_slow = 4, .p2_fast = 4 }, | |
260 | }; | |
261 | ||
e4b36699 | 262 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 263 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 264 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 265 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
266 | .m = { .min = 96, .max = 140 }, |
267 | .m1 = { .min = 18, .max = 26 }, | |
268 | .m2 = { .min = 6, .max = 16 }, | |
269 | .p = { .min = 4, .max = 128 }, | |
270 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
271 | .p2 = { .dot_limit = 165000, |
272 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 273 | }; |
273e27ca | 274 | |
e4b36699 | 275 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
276 | .dot = { .min = 20000, .max = 400000 }, |
277 | .vco = { .min = 1400000, .max = 2800000 }, | |
278 | .n = { .min = 1, .max = 6 }, | |
279 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
280 | .m1 = { .min = 8, .max = 18 }, |
281 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
282 | .p = { .min = 5, .max = 80 }, |
283 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
284 | .p2 = { .dot_limit = 200000, |
285 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
286 | }; |
287 | ||
288 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
289 | .dot = { .min = 20000, .max = 400000 }, |
290 | .vco = { .min = 1400000, .max = 2800000 }, | |
291 | .n = { .min = 1, .max = 6 }, | |
292 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
293 | .m1 = { .min = 8, .max = 18 }, |
294 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
295 | .p = { .min = 7, .max = 98 }, |
296 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
297 | .p2 = { .dot_limit = 112000, |
298 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
299 | }; |
300 | ||
273e27ca | 301 | |
e4b36699 | 302 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
303 | .dot = { .min = 25000, .max = 270000 }, |
304 | .vco = { .min = 1750000, .max = 3500000}, | |
305 | .n = { .min = 1, .max = 4 }, | |
306 | .m = { .min = 104, .max = 138 }, | |
307 | .m1 = { .min = 17, .max = 23 }, | |
308 | .m2 = { .min = 5, .max = 11 }, | |
309 | .p = { .min = 10, .max = 30 }, | |
310 | .p1 = { .min = 1, .max = 3}, | |
311 | .p2 = { .dot_limit = 270000, | |
312 | .p2_slow = 10, | |
313 | .p2_fast = 10 | |
044c7c41 | 314 | }, |
e4b36699 KP |
315 | }; |
316 | ||
317 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
318 | .dot = { .min = 22000, .max = 400000 }, |
319 | .vco = { .min = 1750000, .max = 3500000}, | |
320 | .n = { .min = 1, .max = 4 }, | |
321 | .m = { .min = 104, .max = 138 }, | |
322 | .m1 = { .min = 16, .max = 23 }, | |
323 | .m2 = { .min = 5, .max = 11 }, | |
324 | .p = { .min = 5, .max = 80 }, | |
325 | .p1 = { .min = 1, .max = 8}, | |
326 | .p2 = { .dot_limit = 165000, | |
327 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
328 | }; |
329 | ||
330 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
331 | .dot = { .min = 20000, .max = 115000 }, |
332 | .vco = { .min = 1750000, .max = 3500000 }, | |
333 | .n = { .min = 1, .max = 3 }, | |
334 | .m = { .min = 104, .max = 138 }, | |
335 | .m1 = { .min = 17, .max = 23 }, | |
336 | .m2 = { .min = 5, .max = 11 }, | |
337 | .p = { .min = 28, .max = 112 }, | |
338 | .p1 = { .min = 2, .max = 8 }, | |
339 | .p2 = { .dot_limit = 0, | |
340 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 341 | }, |
e4b36699 KP |
342 | }; |
343 | ||
344 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
345 | .dot = { .min = 80000, .max = 224000 }, |
346 | .vco = { .min = 1750000, .max = 3500000 }, | |
347 | .n = { .min = 1, .max = 3 }, | |
348 | .m = { .min = 104, .max = 138 }, | |
349 | .m1 = { .min = 17, .max = 23 }, | |
350 | .m2 = { .min = 5, .max = 11 }, | |
351 | .p = { .min = 14, .max = 42 }, | |
352 | .p1 = { .min = 2, .max = 6 }, | |
353 | .p2 = { .dot_limit = 0, | |
354 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 355 | }, |
e4b36699 KP |
356 | }; |
357 | ||
f2b115e6 | 358 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
359 | .dot = { .min = 20000, .max = 400000}, |
360 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 361 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
362 | .n = { .min = 3, .max = 6 }, |
363 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 364 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
365 | .m1 = { .min = 0, .max = 0 }, |
366 | .m2 = { .min = 0, .max = 254 }, | |
367 | .p = { .min = 5, .max = 80 }, | |
368 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
369 | .p2 = { .dot_limit = 200000, |
370 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
371 | }; |
372 | ||
f2b115e6 | 373 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
374 | .dot = { .min = 20000, .max = 400000 }, |
375 | .vco = { .min = 1700000, .max = 3500000 }, | |
376 | .n = { .min = 3, .max = 6 }, | |
377 | .m = { .min = 2, .max = 256 }, | |
378 | .m1 = { .min = 0, .max = 0 }, | |
379 | .m2 = { .min = 0, .max = 254 }, | |
380 | .p = { .min = 7, .max = 112 }, | |
381 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
382 | .p2 = { .dot_limit = 112000, |
383 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
384 | }; |
385 | ||
273e27ca EA |
386 | /* Ironlake / Sandybridge |
387 | * | |
388 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
389 | * the range value for them is (actual_value - 2). | |
390 | */ | |
b91ad0ec | 391 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
392 | .dot = { .min = 25000, .max = 350000 }, |
393 | .vco = { .min = 1760000, .max = 3510000 }, | |
394 | .n = { .min = 1, .max = 5 }, | |
395 | .m = { .min = 79, .max = 127 }, | |
396 | .m1 = { .min = 12, .max = 22 }, | |
397 | .m2 = { .min = 5, .max = 9 }, | |
398 | .p = { .min = 5, .max = 80 }, | |
399 | .p1 = { .min = 1, .max = 8 }, | |
400 | .p2 = { .dot_limit = 225000, | |
401 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
402 | }; |
403 | ||
b91ad0ec | 404 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
405 | .dot = { .min = 25000, .max = 350000 }, |
406 | .vco = { .min = 1760000, .max = 3510000 }, | |
407 | .n = { .min = 1, .max = 3 }, | |
408 | .m = { .min = 79, .max = 118 }, | |
409 | .m1 = { .min = 12, .max = 22 }, | |
410 | .m2 = { .min = 5, .max = 9 }, | |
411 | .p = { .min = 28, .max = 112 }, | |
412 | .p1 = { .min = 2, .max = 8 }, | |
413 | .p2 = { .dot_limit = 225000, | |
414 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
415 | }; |
416 | ||
417 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
418 | .dot = { .min = 25000, .max = 350000 }, |
419 | .vco = { .min = 1760000, .max = 3510000 }, | |
420 | .n = { .min = 1, .max = 3 }, | |
421 | .m = { .min = 79, .max = 127 }, | |
422 | .m1 = { .min = 12, .max = 22 }, | |
423 | .m2 = { .min = 5, .max = 9 }, | |
424 | .p = { .min = 14, .max = 56 }, | |
425 | .p1 = { .min = 2, .max = 8 }, | |
426 | .p2 = { .dot_limit = 225000, | |
427 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
428 | }; |
429 | ||
273e27ca | 430 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 431 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
432 | .dot = { .min = 25000, .max = 350000 }, |
433 | .vco = { .min = 1760000, .max = 3510000 }, | |
434 | .n = { .min = 1, .max = 2 }, | |
435 | .m = { .min = 79, .max = 126 }, | |
436 | .m1 = { .min = 12, .max = 22 }, | |
437 | .m2 = { .min = 5, .max = 9 }, | |
438 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 439 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
440 | .p2 = { .dot_limit = 225000, |
441 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
442 | }; |
443 | ||
444 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
445 | .dot = { .min = 25000, .max = 350000 }, |
446 | .vco = { .min = 1760000, .max = 3510000 }, | |
447 | .n = { .min = 1, .max = 3 }, | |
448 | .m = { .min = 79, .max = 126 }, | |
449 | .m1 = { .min = 12, .max = 22 }, | |
450 | .m2 = { .min = 5, .max = 9 }, | |
451 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 452 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
453 | .p2 = { .dot_limit = 225000, |
454 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
455 | }; |
456 | ||
dc730512 | 457 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
458 | /* |
459 | * These are the data rate limits (measured in fast clocks) | |
460 | * since those are the strictest limits we have. The fast | |
461 | * clock and actual rate limits are more relaxed, so checking | |
462 | * them would make no difference. | |
463 | */ | |
464 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 465 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 466 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
467 | .m1 = { .min = 2, .max = 3 }, |
468 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 469 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 470 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
471 | }; |
472 | ||
ef9348c8 CML |
473 | static const intel_limit_t intel_limits_chv = { |
474 | /* | |
475 | * These are the data rate limits (measured in fast clocks) | |
476 | * since those are the strictest limits we have. The fast | |
477 | * clock and actual rate limits are more relaxed, so checking | |
478 | * them would make no difference. | |
479 | */ | |
480 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 481 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
482 | .n = { .min = 1, .max = 1 }, |
483 | .m1 = { .min = 2, .max = 2 }, | |
484 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
485 | .p1 = { .min = 2, .max = 4 }, | |
486 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
487 | }; | |
488 | ||
5ab7b0b7 ID |
489 | static const intel_limit_t intel_limits_bxt = { |
490 | /* FIXME: find real dot limits */ | |
491 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 492 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
493 | .n = { .min = 1, .max = 1 }, |
494 | .m1 = { .min = 2, .max = 2 }, | |
495 | /* FIXME: find real m2 limits */ | |
496 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
497 | .p1 = { .min = 2, .max = 4 }, | |
498 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
499 | }; | |
500 | ||
cdba954e ACO |
501 | static bool |
502 | needs_modeset(struct drm_crtc_state *state) | |
503 | { | |
fc596660 | 504 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
505 | } |
506 | ||
e0638cdf PZ |
507 | /** |
508 | * Returns whether any output on the specified pipe is of the specified type | |
509 | */ | |
4093561b | 510 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 511 | { |
409ee761 | 512 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
513 | struct intel_encoder *encoder; |
514 | ||
409ee761 | 515 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
516 | if (encoder->type == type) |
517 | return true; | |
518 | ||
519 | return false; | |
520 | } | |
521 | ||
d0737e1d ACO |
522 | /** |
523 | * Returns whether any output on the specified pipe will have the specified | |
524 | * type after a staged modeset is complete, i.e., the same as | |
525 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
526 | * encoder->crtc. | |
527 | */ | |
a93e255f ACO |
528 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
529 | int type) | |
d0737e1d | 530 | { |
a93e255f | 531 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 532 | struct drm_connector *connector; |
a93e255f | 533 | struct drm_connector_state *connector_state; |
d0737e1d | 534 | struct intel_encoder *encoder; |
a93e255f ACO |
535 | int i, num_connectors = 0; |
536 | ||
da3ced29 | 537 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
538 | if (connector_state->crtc != crtc_state->base.crtc) |
539 | continue; | |
540 | ||
541 | num_connectors++; | |
d0737e1d | 542 | |
a93e255f ACO |
543 | encoder = to_intel_encoder(connector_state->best_encoder); |
544 | if (encoder->type == type) | |
d0737e1d | 545 | return true; |
a93e255f ACO |
546 | } |
547 | ||
548 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
549 | |
550 | return false; | |
551 | } | |
552 | ||
a93e255f ACO |
553 | static const intel_limit_t * |
554 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 555 | { |
a93e255f | 556 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 557 | const intel_limit_t *limit; |
b91ad0ec | 558 | |
a93e255f | 559 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 560 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 561 | if (refclk == 100000) |
b91ad0ec ZW |
562 | limit = &intel_limits_ironlake_dual_lvds_100m; |
563 | else | |
564 | limit = &intel_limits_ironlake_dual_lvds; | |
565 | } else { | |
1b894b59 | 566 | if (refclk == 100000) |
b91ad0ec ZW |
567 | limit = &intel_limits_ironlake_single_lvds_100m; |
568 | else | |
569 | limit = &intel_limits_ironlake_single_lvds; | |
570 | } | |
c6bb3538 | 571 | } else |
b91ad0ec | 572 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
573 | |
574 | return limit; | |
575 | } | |
576 | ||
a93e255f ACO |
577 | static const intel_limit_t * |
578 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 579 | { |
a93e255f | 580 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
581 | const intel_limit_t *limit; |
582 | ||
a93e255f | 583 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 584 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 585 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 586 | else |
e4b36699 | 587 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
588 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
589 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 590 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 591 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 592 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 593 | } else /* The option is for other outputs */ |
e4b36699 | 594 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
595 | |
596 | return limit; | |
597 | } | |
598 | ||
a93e255f ACO |
599 | static const intel_limit_t * |
600 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 601 | { |
a93e255f | 602 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
603 | const intel_limit_t *limit; |
604 | ||
5ab7b0b7 ID |
605 | if (IS_BROXTON(dev)) |
606 | limit = &intel_limits_bxt; | |
607 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 608 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 609 | else if (IS_G4X(dev)) { |
a93e255f | 610 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 611 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 612 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 613 | limit = &intel_limits_pineview_lvds; |
2177832f | 614 | else |
f2b115e6 | 615 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
616 | } else if (IS_CHERRYVIEW(dev)) { |
617 | limit = &intel_limits_chv; | |
a0c4da24 | 618 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 619 | limit = &intel_limits_vlv; |
a6c45cf0 | 620 | } else if (!IS_GEN2(dev)) { |
a93e255f | 621 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
622 | limit = &intel_limits_i9xx_lvds; |
623 | else | |
624 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 625 | } else { |
a93e255f | 626 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 627 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 628 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 629 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
630 | else |
631 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
632 | } |
633 | return limit; | |
634 | } | |
635 | ||
dccbea3b ID |
636 | /* |
637 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
638 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
639 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
640 | * The helpers' return value is the rate of the clock that is fed to the | |
641 | * display engine's pipe which can be the above fast dot clock rate or a | |
642 | * divided-down version of it. | |
643 | */ | |
f2b115e6 | 644 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 645 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 646 | { |
2177832f SL |
647 | clock->m = clock->m2 + 2; |
648 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 649 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 650 | return 0; |
fb03ac01 VS |
651 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
652 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
653 | |
654 | return clock->dot; | |
2177832f SL |
655 | } |
656 | ||
7429e9d4 DV |
657 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
658 | { | |
659 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
660 | } | |
661 | ||
dccbea3b | 662 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 663 | { |
7429e9d4 | 664 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 665 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 666 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 667 | return 0; |
fb03ac01 VS |
668 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
669 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
670 | |
671 | return clock->dot; | |
79e53945 JB |
672 | } |
673 | ||
dccbea3b | 674 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
675 | { |
676 | clock->m = clock->m1 * clock->m2; | |
677 | clock->p = clock->p1 * clock->p2; | |
678 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 679 | return 0; |
589eca67 ID |
680 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
681 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
682 | |
683 | return clock->dot / 5; | |
589eca67 ID |
684 | } |
685 | ||
dccbea3b | 686 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
687 | { |
688 | clock->m = clock->m1 * clock->m2; | |
689 | clock->p = clock->p1 * clock->p2; | |
690 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 691 | return 0; |
ef9348c8 CML |
692 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
693 | clock->n << 22); | |
694 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
695 | |
696 | return clock->dot / 5; | |
ef9348c8 CML |
697 | } |
698 | ||
7c04d1d9 | 699 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
700 | /** |
701 | * Returns whether the given set of divisors are valid for a given refclk with | |
702 | * the given connectors. | |
703 | */ | |
704 | ||
1b894b59 CW |
705 | static bool intel_PLL_is_valid(struct drm_device *dev, |
706 | const intel_limit_t *limit, | |
707 | const intel_clock_t *clock) | |
79e53945 | 708 | { |
f01b7962 VS |
709 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
710 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 711 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 712 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 713 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 714 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 715 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 716 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 717 | |
666a4537 WB |
718 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
719 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
720 | if (clock->m1 <= clock->m2) |
721 | INTELPllInvalid("m1 <= m2\n"); | |
722 | ||
666a4537 | 723 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
724 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
725 | INTELPllInvalid("p out of range\n"); | |
726 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
727 | INTELPllInvalid("m out of range\n"); | |
728 | } | |
729 | ||
79e53945 | 730 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 731 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
732 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
733 | * connector, etc., rather than just a single range. | |
734 | */ | |
735 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 736 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
737 | |
738 | return true; | |
739 | } | |
740 | ||
3b1429d9 VS |
741 | static int |
742 | i9xx_select_p2_div(const intel_limit_t *limit, | |
743 | const struct intel_crtc_state *crtc_state, | |
744 | int target) | |
79e53945 | 745 | { |
3b1429d9 | 746 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 747 | |
a93e255f | 748 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 749 | /* |
a210b028 DV |
750 | * For LVDS just rely on its current settings for dual-channel. |
751 | * We haven't figured out how to reliably set up different | |
752 | * single/dual channel state, if we even can. | |
79e53945 | 753 | */ |
1974cad0 | 754 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 755 | return limit->p2.p2_fast; |
79e53945 | 756 | else |
3b1429d9 | 757 | return limit->p2.p2_slow; |
79e53945 JB |
758 | } else { |
759 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 760 | return limit->p2.p2_slow; |
79e53945 | 761 | else |
3b1429d9 | 762 | return limit->p2.p2_fast; |
79e53945 | 763 | } |
3b1429d9 VS |
764 | } |
765 | ||
766 | static bool | |
767 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
768 | struct intel_crtc_state *crtc_state, | |
769 | int target, int refclk, intel_clock_t *match_clock, | |
770 | intel_clock_t *best_clock) | |
771 | { | |
772 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
773 | intel_clock_t clock; | |
774 | int err = target; | |
79e53945 | 775 | |
0206e353 | 776 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 777 | |
3b1429d9 VS |
778 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
779 | ||
42158660 ZY |
780 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
781 | clock.m1++) { | |
782 | for (clock.m2 = limit->m2.min; | |
783 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 784 | if (clock.m2 >= clock.m1) |
42158660 ZY |
785 | break; |
786 | for (clock.n = limit->n.min; | |
787 | clock.n <= limit->n.max; clock.n++) { | |
788 | for (clock.p1 = limit->p1.min; | |
789 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
790 | int this_err; |
791 | ||
dccbea3b | 792 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
793 | if (!intel_PLL_is_valid(dev, limit, |
794 | &clock)) | |
795 | continue; | |
796 | if (match_clock && | |
797 | clock.p != match_clock->p) | |
798 | continue; | |
799 | ||
800 | this_err = abs(clock.dot - target); | |
801 | if (this_err < err) { | |
802 | *best_clock = clock; | |
803 | err = this_err; | |
804 | } | |
805 | } | |
806 | } | |
807 | } | |
808 | } | |
809 | ||
810 | return (err != target); | |
811 | } | |
812 | ||
813 | static bool | |
a93e255f ACO |
814 | pnv_find_best_dpll(const intel_limit_t *limit, |
815 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
816 | int target, int refclk, intel_clock_t *match_clock, |
817 | intel_clock_t *best_clock) | |
79e53945 | 818 | { |
3b1429d9 | 819 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 820 | intel_clock_t clock; |
79e53945 JB |
821 | int err = target; |
822 | ||
0206e353 | 823 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 824 | |
3b1429d9 VS |
825 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
826 | ||
42158660 ZY |
827 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
828 | clock.m1++) { | |
829 | for (clock.m2 = limit->m2.min; | |
830 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
831 | for (clock.n = limit->n.min; |
832 | clock.n <= limit->n.max; clock.n++) { | |
833 | for (clock.p1 = limit->p1.min; | |
834 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
835 | int this_err; |
836 | ||
dccbea3b | 837 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
838 | if (!intel_PLL_is_valid(dev, limit, |
839 | &clock)) | |
79e53945 | 840 | continue; |
cec2f356 SP |
841 | if (match_clock && |
842 | clock.p != match_clock->p) | |
843 | continue; | |
79e53945 JB |
844 | |
845 | this_err = abs(clock.dot - target); | |
846 | if (this_err < err) { | |
847 | *best_clock = clock; | |
848 | err = this_err; | |
849 | } | |
850 | } | |
851 | } | |
852 | } | |
853 | } | |
854 | ||
855 | return (err != target); | |
856 | } | |
857 | ||
d4906093 | 858 | static bool |
a93e255f ACO |
859 | g4x_find_best_dpll(const intel_limit_t *limit, |
860 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
861 | int target, int refclk, intel_clock_t *match_clock, |
862 | intel_clock_t *best_clock) | |
d4906093 | 863 | { |
3b1429d9 | 864 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
865 | intel_clock_t clock; |
866 | int max_n; | |
3b1429d9 | 867 | bool found = false; |
6ba770dc AJ |
868 | /* approximately equals target * 0.00585 */ |
869 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
870 | |
871 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
872 | |
873 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
874 | ||
d4906093 | 875 | max_n = limit->n.max; |
f77f13e2 | 876 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 877 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 878 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
879 | for (clock.m1 = limit->m1.max; |
880 | clock.m1 >= limit->m1.min; clock.m1--) { | |
881 | for (clock.m2 = limit->m2.max; | |
882 | clock.m2 >= limit->m2.min; clock.m2--) { | |
883 | for (clock.p1 = limit->p1.max; | |
884 | clock.p1 >= limit->p1.min; clock.p1--) { | |
885 | int this_err; | |
886 | ||
dccbea3b | 887 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
888 | if (!intel_PLL_is_valid(dev, limit, |
889 | &clock)) | |
d4906093 | 890 | continue; |
1b894b59 CW |
891 | |
892 | this_err = abs(clock.dot - target); | |
d4906093 ML |
893 | if (this_err < err_most) { |
894 | *best_clock = clock; | |
895 | err_most = this_err; | |
896 | max_n = clock.n; | |
897 | found = true; | |
898 | } | |
899 | } | |
900 | } | |
901 | } | |
902 | } | |
2c07245f ZW |
903 | return found; |
904 | } | |
905 | ||
d5dd62bd ID |
906 | /* |
907 | * Check if the calculated PLL configuration is more optimal compared to the | |
908 | * best configuration and error found so far. Return the calculated error. | |
909 | */ | |
910 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
911 | const intel_clock_t *calculated_clock, | |
912 | const intel_clock_t *best_clock, | |
913 | unsigned int best_error_ppm, | |
914 | unsigned int *error_ppm) | |
915 | { | |
9ca3ba01 ID |
916 | /* |
917 | * For CHV ignore the error and consider only the P value. | |
918 | * Prefer a bigger P value based on HW requirements. | |
919 | */ | |
920 | if (IS_CHERRYVIEW(dev)) { | |
921 | *error_ppm = 0; | |
922 | ||
923 | return calculated_clock->p > best_clock->p; | |
924 | } | |
925 | ||
24be4e46 ID |
926 | if (WARN_ON_ONCE(!target_freq)) |
927 | return false; | |
928 | ||
d5dd62bd ID |
929 | *error_ppm = div_u64(1000000ULL * |
930 | abs(target_freq - calculated_clock->dot), | |
931 | target_freq); | |
932 | /* | |
933 | * Prefer a better P value over a better (smaller) error if the error | |
934 | * is small. Ensure this preference for future configurations too by | |
935 | * setting the error to 0. | |
936 | */ | |
937 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
938 | *error_ppm = 0; | |
939 | ||
940 | return true; | |
941 | } | |
942 | ||
943 | return *error_ppm + 10 < best_error_ppm; | |
944 | } | |
945 | ||
a0c4da24 | 946 | static bool |
a93e255f ACO |
947 | vlv_find_best_dpll(const intel_limit_t *limit, |
948 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
949 | int target, int refclk, intel_clock_t *match_clock, |
950 | intel_clock_t *best_clock) | |
a0c4da24 | 951 | { |
a93e255f | 952 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 953 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 954 | intel_clock_t clock; |
69e4f900 | 955 | unsigned int bestppm = 1000000; |
27e639bf VS |
956 | /* min update 19.2 MHz */ |
957 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 958 | bool found = false; |
a0c4da24 | 959 | |
6b4bf1c4 VS |
960 | target *= 5; /* fast clock */ |
961 | ||
962 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
963 | |
964 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 965 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 966 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 967 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 968 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 969 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 970 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 971 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 972 | unsigned int ppm; |
69e4f900 | 973 | |
6b4bf1c4 VS |
974 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
975 | refclk * clock.m1); | |
976 | ||
dccbea3b | 977 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 978 | |
f01b7962 VS |
979 | if (!intel_PLL_is_valid(dev, limit, |
980 | &clock)) | |
43b0ac53 VS |
981 | continue; |
982 | ||
d5dd62bd ID |
983 | if (!vlv_PLL_is_optimal(dev, target, |
984 | &clock, | |
985 | best_clock, | |
986 | bestppm, &ppm)) | |
987 | continue; | |
6b4bf1c4 | 988 | |
d5dd62bd ID |
989 | *best_clock = clock; |
990 | bestppm = ppm; | |
991 | found = true; | |
a0c4da24 JB |
992 | } |
993 | } | |
994 | } | |
995 | } | |
a0c4da24 | 996 | |
49e497ef | 997 | return found; |
a0c4da24 | 998 | } |
a4fc5ed6 | 999 | |
ef9348c8 | 1000 | static bool |
a93e255f ACO |
1001 | chv_find_best_dpll(const intel_limit_t *limit, |
1002 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
1003 | int target, int refclk, intel_clock_t *match_clock, |
1004 | intel_clock_t *best_clock) | |
1005 | { | |
a93e255f | 1006 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 1007 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 1008 | unsigned int best_error_ppm; |
ef9348c8 CML |
1009 | intel_clock_t clock; |
1010 | uint64_t m2; | |
1011 | int found = false; | |
1012 | ||
1013 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1014 | best_error_ppm = 1000000; |
ef9348c8 CML |
1015 | |
1016 | /* | |
1017 | * Based on hardware doc, the n always set to 1, and m1 always | |
1018 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1019 | * revisit this because n may not 1 anymore. | |
1020 | */ | |
1021 | clock.n = 1, clock.m1 = 2; | |
1022 | target *= 5; /* fast clock */ | |
1023 | ||
1024 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1025 | for (clock.p2 = limit->p2.p2_fast; | |
1026 | clock.p2 >= limit->p2.p2_slow; | |
1027 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1028 | unsigned int error_ppm; |
ef9348c8 CML |
1029 | |
1030 | clock.p = clock.p1 * clock.p2; | |
1031 | ||
1032 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1033 | clock.n) << 22, refclk * clock.m1); | |
1034 | ||
1035 | if (m2 > INT_MAX/clock.m1) | |
1036 | continue; | |
1037 | ||
1038 | clock.m2 = m2; | |
1039 | ||
dccbea3b | 1040 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1041 | |
1042 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1043 | continue; | |
1044 | ||
9ca3ba01 ID |
1045 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1046 | best_error_ppm, &error_ppm)) | |
1047 | continue; | |
1048 | ||
1049 | *best_clock = clock; | |
1050 | best_error_ppm = error_ppm; | |
1051 | found = true; | |
ef9348c8 CML |
1052 | } |
1053 | } | |
1054 | ||
1055 | return found; | |
1056 | } | |
1057 | ||
5ab7b0b7 ID |
1058 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1059 | intel_clock_t *best_clock) | |
1060 | { | |
1061 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1062 | ||
1063 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1064 | target_clock, refclk, NULL, best_clock); | |
1065 | } | |
1066 | ||
20ddf665 VS |
1067 | bool intel_crtc_active(struct drm_crtc *crtc) |
1068 | { | |
1069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1070 | ||
1071 | /* Be paranoid as we can arrive here with only partial | |
1072 | * state retrieved from the hardware during setup. | |
1073 | * | |
241bfc38 | 1074 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1075 | * as Haswell has gained clock readout/fastboot support. |
1076 | * | |
66e514c1 | 1077 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1078 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1079 | * |
1080 | * FIXME: The intel_crtc->active here should be switched to | |
1081 | * crtc->state->active once we have proper CRTC states wired up | |
1082 | * for atomic. | |
20ddf665 | 1083 | */ |
c3d1f436 | 1084 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1085 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1086 | } |
1087 | ||
a5c961d1 PZ |
1088 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1089 | enum pipe pipe) | |
1090 | { | |
1091 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1092 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1093 | ||
6e3c9717 | 1094 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1095 | } |
1096 | ||
fbf49ea2 VS |
1097 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1098 | { | |
1099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1100 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1101 | u32 line1, line2; |
1102 | u32 line_mask; | |
1103 | ||
1104 | if (IS_GEN2(dev)) | |
1105 | line_mask = DSL_LINEMASK_GEN2; | |
1106 | else | |
1107 | line_mask = DSL_LINEMASK_GEN3; | |
1108 | ||
1109 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1110 | msleep(5); |
fbf49ea2 VS |
1111 | line2 = I915_READ(reg) & line_mask; |
1112 | ||
1113 | return line1 == line2; | |
1114 | } | |
1115 | ||
ab7ad7f6 KP |
1116 | /* |
1117 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1118 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1119 | * |
1120 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1121 | * spinning on the vblank interrupt status bit, since we won't actually | |
1122 | * see an interrupt when the pipe is disabled. | |
1123 | * | |
ab7ad7f6 KP |
1124 | * On Gen4 and above: |
1125 | * wait for the pipe register state bit to turn off | |
1126 | * | |
1127 | * Otherwise: | |
1128 | * wait for the display line value to settle (it usually | |
1129 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1130 | * |
9d0498a2 | 1131 | */ |
575f7ab7 | 1132 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1133 | { |
575f7ab7 | 1134 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1135 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1136 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1137 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1138 | |
1139 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1140 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1141 | |
1142 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1143 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1144 | 100)) | |
284637d9 | 1145 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1146 | } else { |
ab7ad7f6 | 1147 | /* Wait for the display line to settle */ |
fbf49ea2 | 1148 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1149 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1150 | } |
79e53945 JB |
1151 | } |
1152 | ||
b24e7179 | 1153 | /* Only for pre-ILK configs */ |
55607e8a DV |
1154 | void assert_pll(struct drm_i915_private *dev_priv, |
1155 | enum pipe pipe, bool state) | |
b24e7179 | 1156 | { |
b24e7179 JB |
1157 | u32 val; |
1158 | bool cur_state; | |
1159 | ||
649636ef | 1160 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1161 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1162 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1163 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1164 | onoff(state), onoff(cur_state)); |
b24e7179 | 1165 | } |
b24e7179 | 1166 | |
23538ef1 JN |
1167 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1168 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1169 | { | |
1170 | u32 val; | |
1171 | bool cur_state; | |
1172 | ||
a580516d | 1173 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1174 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1175 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1176 | |
1177 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1178 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1179 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1180 | onoff(state), onoff(cur_state)); |
23538ef1 JN |
1181 | } |
1182 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1183 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1184 | ||
55607e8a | 1185 | struct intel_shared_dpll * |
e2b78267 DV |
1186 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1187 | { | |
1188 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1189 | ||
6e3c9717 | 1190 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1191 | return NULL; |
1192 | ||
6e3c9717 | 1193 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1194 | } |
1195 | ||
040484af | 1196 | /* For ILK+ */ |
55607e8a DV |
1197 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1198 | struct intel_shared_dpll *pll, | |
1199 | bool state) | |
040484af | 1200 | { |
040484af | 1201 | bool cur_state; |
5358901f | 1202 | struct intel_dpll_hw_state hw_state; |
040484af | 1203 | |
87ad3212 | 1204 | if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) |
ee7b9f93 | 1205 | return; |
ee7b9f93 | 1206 | |
5358901f | 1207 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1208 | I915_STATE_WARN(cur_state != state, |
5358901f | 1209 | "%s assertion failure (expected %s, current %s)\n", |
87ad3212 | 1210 | pll->name, onoff(state), onoff(cur_state)); |
040484af | 1211 | } |
040484af JB |
1212 | |
1213 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1214 | enum pipe pipe, bool state) | |
1215 | { | |
040484af | 1216 | bool cur_state; |
ad80a810 PZ |
1217 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1218 | pipe); | |
040484af | 1219 | |
affa9354 PZ |
1220 | if (HAS_DDI(dev_priv->dev)) { |
1221 | /* DDI does not have a specific FDI_TX register */ | |
649636ef | 1222 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1223 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1224 | } else { |
649636ef | 1225 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1226 | cur_state = !!(val & FDI_TX_ENABLE); |
1227 | } | |
e2c719b7 | 1228 | I915_STATE_WARN(cur_state != state, |
040484af | 1229 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1230 | onoff(state), onoff(cur_state)); |
040484af JB |
1231 | } |
1232 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1233 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1234 | ||
1235 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1236 | enum pipe pipe, bool state) | |
1237 | { | |
040484af JB |
1238 | u32 val; |
1239 | bool cur_state; | |
1240 | ||
649636ef | 1241 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1242 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1243 | I915_STATE_WARN(cur_state != state, |
040484af | 1244 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1245 | onoff(state), onoff(cur_state)); |
040484af JB |
1246 | } |
1247 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1248 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1249 | ||
1250 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1251 | enum pipe pipe) | |
1252 | { | |
040484af JB |
1253 | u32 val; |
1254 | ||
1255 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1256 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1257 | return; |
1258 | ||
bf507ef7 | 1259 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1260 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1261 | return; |
1262 | ||
649636ef | 1263 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1264 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1265 | } |
1266 | ||
55607e8a DV |
1267 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1268 | enum pipe pipe, bool state) | |
040484af | 1269 | { |
040484af | 1270 | u32 val; |
55607e8a | 1271 | bool cur_state; |
040484af | 1272 | |
649636ef | 1273 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1274 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1275 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1276 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1277 | onoff(state), onoff(cur_state)); |
040484af JB |
1278 | } |
1279 | ||
b680c37a DV |
1280 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1281 | enum pipe pipe) | |
ea0760cf | 1282 | { |
bedd4dba | 1283 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1284 | i915_reg_t pp_reg; |
ea0760cf JB |
1285 | u32 val; |
1286 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1287 | bool locked = true; |
ea0760cf | 1288 | |
bedd4dba JN |
1289 | if (WARN_ON(HAS_DDI(dev))) |
1290 | return; | |
1291 | ||
1292 | if (HAS_PCH_SPLIT(dev)) { | |
1293 | u32 port_sel; | |
1294 | ||
ea0760cf | 1295 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1296 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1297 | ||
1298 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1299 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1300 | panel_pipe = PIPE_B; | |
1301 | /* XXX: else fix for eDP */ | |
666a4537 | 1302 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1303 | /* presumably write lock depends on pipe, not port select */ |
1304 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1305 | panel_pipe = pipe; | |
ea0760cf JB |
1306 | } else { |
1307 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1308 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1309 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1310 | } |
1311 | ||
1312 | val = I915_READ(pp_reg); | |
1313 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1314 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1315 | locked = false; |
1316 | ||
e2c719b7 | 1317 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1318 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1319 | pipe_name(pipe)); |
ea0760cf JB |
1320 | } |
1321 | ||
93ce0ba6 JN |
1322 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1323 | enum pipe pipe, bool state) | |
1324 | { | |
1325 | struct drm_device *dev = dev_priv->dev; | |
1326 | bool cur_state; | |
1327 | ||
d9d82081 | 1328 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1329 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1330 | else |
5efb3e28 | 1331 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1332 | |
e2c719b7 | 1333 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1334 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1335 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1336 | } |
1337 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1338 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1339 | ||
b840d907 JB |
1340 | void assert_pipe(struct drm_i915_private *dev_priv, |
1341 | enum pipe pipe, bool state) | |
b24e7179 | 1342 | { |
63d7bbe9 | 1343 | bool cur_state; |
702e7a56 PZ |
1344 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1345 | pipe); | |
b24e7179 | 1346 | |
b6b5d049 VS |
1347 | /* if we need the pipe quirk it must be always on */ |
1348 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1349 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1350 | state = true; |
1351 | ||
f458ebbc | 1352 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1353 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1354 | cur_state = false; |
1355 | } else { | |
649636ef | 1356 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 PZ |
1357 | cur_state = !!(val & PIPECONF_ENABLE); |
1358 | } | |
1359 | ||
e2c719b7 | 1360 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1361 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1362 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1363 | } |
1364 | ||
931872fc CW |
1365 | static void assert_plane(struct drm_i915_private *dev_priv, |
1366 | enum plane plane, bool state) | |
b24e7179 | 1367 | { |
b24e7179 | 1368 | u32 val; |
931872fc | 1369 | bool cur_state; |
b24e7179 | 1370 | |
649636ef | 1371 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1372 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1373 | I915_STATE_WARN(cur_state != state, |
931872fc | 1374 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1375 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1376 | } |
1377 | ||
931872fc CW |
1378 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1379 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1380 | ||
b24e7179 JB |
1381 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1382 | enum pipe pipe) | |
1383 | { | |
653e1026 | 1384 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1385 | int i; |
b24e7179 | 1386 | |
653e1026 VS |
1387 | /* Primary planes are fixed to pipes on gen4+ */ |
1388 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1389 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1390 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1391 | "plane %c assertion failure, should be disabled but not\n", |
1392 | plane_name(pipe)); | |
19ec1358 | 1393 | return; |
28c05794 | 1394 | } |
19ec1358 | 1395 | |
b24e7179 | 1396 | /* Need to check both planes against the pipe */ |
055e393f | 1397 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1398 | u32 val = I915_READ(DSPCNTR(i)); |
1399 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1400 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1401 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1402 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1403 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1404 | } |
1405 | } | |
1406 | ||
19332d7a JB |
1407 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1408 | enum pipe pipe) | |
1409 | { | |
20674eef | 1410 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1411 | int sprite; |
19332d7a | 1412 | |
7feb8b88 | 1413 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1414 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1415 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1416 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1417 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1418 | sprite, pipe_name(pipe)); | |
1419 | } | |
666a4537 | 1420 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1421 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1422 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1423 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1424 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1425 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1426 | } |
1427 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1428 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1429 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1430 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1431 | plane_name(pipe), pipe_name(pipe)); |
1432 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1433 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1434 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1435 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1436 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1437 | } |
1438 | } | |
1439 | ||
08c71e5e VS |
1440 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1441 | { | |
e2c719b7 | 1442 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1443 | drm_crtc_vblank_put(crtc); |
1444 | } | |
1445 | ||
89eff4be | 1446 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1447 | { |
1448 | u32 val; | |
1449 | bool enabled; | |
1450 | ||
e2c719b7 | 1451 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1452 | |
92f2584a JB |
1453 | val = I915_READ(PCH_DREF_CONTROL); |
1454 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1455 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1456 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1457 | } |
1458 | ||
ab9412ba DV |
1459 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1460 | enum pipe pipe) | |
92f2584a | 1461 | { |
92f2584a JB |
1462 | u32 val; |
1463 | bool enabled; | |
1464 | ||
649636ef | 1465 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1466 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1467 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1468 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1469 | pipe_name(pipe)); | |
92f2584a JB |
1470 | } |
1471 | ||
4e634389 KP |
1472 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1473 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1474 | { |
1475 | if ((val & DP_PORT_EN) == 0) | |
1476 | return false; | |
1477 | ||
1478 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
f0f59a00 | 1479 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1480 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1481 | return false; | |
44f37d1f CML |
1482 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1483 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1484 | return false; | |
f0575e92 KP |
1485 | } else { |
1486 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1487 | return false; | |
1488 | } | |
1489 | return true; | |
1490 | } | |
1491 | ||
1519b995 KP |
1492 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1493 | enum pipe pipe, u32 val) | |
1494 | { | |
dc0fa718 | 1495 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1496 | return false; |
1497 | ||
1498 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1499 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1500 | return false; |
44f37d1f CML |
1501 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1502 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1503 | return false; | |
1519b995 | 1504 | } else { |
dc0fa718 | 1505 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1506 | return false; |
1507 | } | |
1508 | return true; | |
1509 | } | |
1510 | ||
1511 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1512 | enum pipe pipe, u32 val) | |
1513 | { | |
1514 | if ((val & LVDS_PORT_EN) == 0) | |
1515 | return false; | |
1516 | ||
1517 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1518 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1519 | return false; | |
1520 | } else { | |
1521 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1522 | return false; | |
1523 | } | |
1524 | return true; | |
1525 | } | |
1526 | ||
1527 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1528 | enum pipe pipe, u32 val) | |
1529 | { | |
1530 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1531 | return false; | |
1532 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1533 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1534 | return false; | |
1535 | } else { | |
1536 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1537 | return false; | |
1538 | } | |
1539 | return true; | |
1540 | } | |
1541 | ||
291906f1 | 1542 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1543 | enum pipe pipe, i915_reg_t reg, |
1544 | u32 port_sel) | |
291906f1 | 1545 | { |
47a05eca | 1546 | u32 val = I915_READ(reg); |
e2c719b7 | 1547 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1548 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1549 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1550 | |
e2c719b7 | 1551 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1552 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1553 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1554 | } |
1555 | ||
1556 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1557 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1558 | { |
47a05eca | 1559 | u32 val = I915_READ(reg); |
e2c719b7 | 1560 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1561 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1562 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1563 | |
e2c719b7 | 1564 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1565 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1566 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1567 | } |
1568 | ||
1569 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1570 | enum pipe pipe) | |
1571 | { | |
291906f1 | 1572 | u32 val; |
291906f1 | 1573 | |
f0575e92 KP |
1574 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1575 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1576 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1577 | |
649636ef | 1578 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1579 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1580 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1581 | pipe_name(pipe)); |
291906f1 | 1582 | |
649636ef | 1583 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1584 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1585 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1586 | pipe_name(pipe)); |
291906f1 | 1587 | |
e2debe91 PZ |
1588 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1589 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1590 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1591 | } |
1592 | ||
d288f65f | 1593 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1594 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1595 | { |
426115cf DV |
1596 | struct drm_device *dev = crtc->base.dev; |
1597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1598 | i915_reg_t reg = DPLL(crtc->pipe); |
d288f65f | 1599 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1600 | |
426115cf | 1601 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 | 1602 | |
87442f73 | 1603 | /* PLL is protected by panel, make sure we can write it */ |
6a9e7363 | 1604 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1605 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1606 | |
426115cf DV |
1607 | I915_WRITE(reg, dpll); |
1608 | POSTING_READ(reg); | |
1609 | udelay(150); | |
1610 | ||
1611 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1612 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1613 | ||
d288f65f | 1614 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1615 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1616 | |
1617 | /* We do this three times for luck */ | |
426115cf | 1618 | I915_WRITE(reg, dpll); |
87442f73 DV |
1619 | POSTING_READ(reg); |
1620 | udelay(150); /* wait for warmup */ | |
426115cf | 1621 | I915_WRITE(reg, dpll); |
87442f73 DV |
1622 | POSTING_READ(reg); |
1623 | udelay(150); /* wait for warmup */ | |
426115cf | 1624 | I915_WRITE(reg, dpll); |
87442f73 DV |
1625 | POSTING_READ(reg); |
1626 | udelay(150); /* wait for warmup */ | |
1627 | } | |
1628 | ||
d288f65f | 1629 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1630 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1631 | { |
1632 | struct drm_device *dev = crtc->base.dev; | |
1633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1634 | int pipe = crtc->pipe; | |
1635 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1636 | u32 tmp; |
1637 | ||
1638 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1639 | ||
a580516d | 1640 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1641 | |
1642 | /* Enable back the 10bit clock to display controller */ | |
1643 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1644 | tmp |= DPIO_DCLKP_EN; | |
1645 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1646 | ||
54433e91 VS |
1647 | mutex_unlock(&dev_priv->sb_lock); |
1648 | ||
9d556c99 CML |
1649 | /* |
1650 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1651 | */ | |
1652 | udelay(1); | |
1653 | ||
1654 | /* Enable PLL */ | |
d288f65f | 1655 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1656 | |
1657 | /* Check PLL is locked */ | |
a11b0703 | 1658 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1659 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1660 | ||
a11b0703 | 1661 | /* not sure when this should be written */ |
d288f65f | 1662 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1663 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1664 | } |
1665 | ||
1c4e0274 VS |
1666 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1667 | { | |
1668 | struct intel_crtc *crtc; | |
1669 | int count = 0; | |
1670 | ||
1671 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1672 | count += crtc->base.state->active && |
409ee761 | 1673 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1674 | |
1675 | return count; | |
1676 | } | |
1677 | ||
66e3d5c0 | 1678 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1679 | { |
66e3d5c0 DV |
1680 | struct drm_device *dev = crtc->base.dev; |
1681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1682 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1683 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1684 | |
66e3d5c0 | 1685 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1686 | |
63d7bbe9 | 1687 | /* No really, not for ILK+ */ |
3d13ef2e | 1688 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1689 | |
1690 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1691 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1692 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1693 | |
1c4e0274 VS |
1694 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1695 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1696 | /* | |
1697 | * It appears to be important that we don't enable this | |
1698 | * for the current pipe before otherwise configuring the | |
1699 | * PLL. No idea how this should be handled if multiple | |
1700 | * DVO outputs are enabled simultaneosly. | |
1701 | */ | |
1702 | dpll |= DPLL_DVO_2X_MODE; | |
1703 | I915_WRITE(DPLL(!crtc->pipe), | |
1704 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1705 | } | |
66e3d5c0 | 1706 | |
c2b63374 VS |
1707 | /* |
1708 | * Apparently we need to have VGA mode enabled prior to changing | |
1709 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1710 | * dividers, even though the register value does change. | |
1711 | */ | |
1712 | I915_WRITE(reg, 0); | |
1713 | ||
8e7a65aa VS |
1714 | I915_WRITE(reg, dpll); |
1715 | ||
66e3d5c0 DV |
1716 | /* Wait for the clocks to stabilize. */ |
1717 | POSTING_READ(reg); | |
1718 | udelay(150); | |
1719 | ||
1720 | if (INTEL_INFO(dev)->gen >= 4) { | |
1721 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1722 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1723 | } else { |
1724 | /* The pixel multiplier can only be updated once the | |
1725 | * DPLL is enabled and the clocks are stable. | |
1726 | * | |
1727 | * So write it again. | |
1728 | */ | |
1729 | I915_WRITE(reg, dpll); | |
1730 | } | |
63d7bbe9 JB |
1731 | |
1732 | /* We do this three times for luck */ | |
66e3d5c0 | 1733 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1734 | POSTING_READ(reg); |
1735 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1736 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1737 | POSTING_READ(reg); |
1738 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1739 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1740 | POSTING_READ(reg); |
1741 | udelay(150); /* wait for warmup */ | |
1742 | } | |
1743 | ||
1744 | /** | |
50b44a44 | 1745 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1746 | * @dev_priv: i915 private structure |
1747 | * @pipe: pipe PLL to disable | |
1748 | * | |
1749 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1750 | * | |
1751 | * Note! This is for pre-ILK only. | |
1752 | */ | |
1c4e0274 | 1753 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1754 | { |
1c4e0274 VS |
1755 | struct drm_device *dev = crtc->base.dev; |
1756 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1757 | enum pipe pipe = crtc->pipe; | |
1758 | ||
1759 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1760 | if (IS_I830(dev) && | |
409ee761 | 1761 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1762 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1763 | I915_WRITE(DPLL(PIPE_B), |
1764 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1765 | I915_WRITE(DPLL(PIPE_A), | |
1766 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1767 | } | |
1768 | ||
b6b5d049 VS |
1769 | /* Don't disable pipe or pipe PLLs if needed */ |
1770 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1771 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1772 | return; |
1773 | ||
1774 | /* Make sure the pipe isn't still relying on us */ | |
1775 | assert_pipe_disabled(dev_priv, pipe); | |
1776 | ||
b8afb911 | 1777 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1778 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1779 | } |
1780 | ||
f6071166 JB |
1781 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1782 | { | |
b8afb911 | 1783 | u32 val; |
f6071166 JB |
1784 | |
1785 | /* Make sure the pipe isn't still relying on us */ | |
1786 | assert_pipe_disabled(dev_priv, pipe); | |
1787 | ||
e5cbfbfb ID |
1788 | /* |
1789 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1790 | * The latter is needed for VGA hotplug / manual detection. | |
1791 | */ | |
b8afb911 | 1792 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1793 | if (pipe == PIPE_B) |
60bfe44f | 1794 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1795 | I915_WRITE(DPLL(pipe), val); |
1796 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1797 | |
1798 | } | |
1799 | ||
1800 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1801 | { | |
d752048d | 1802 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1803 | u32 val; |
1804 | ||
a11b0703 VS |
1805 | /* Make sure the pipe isn't still relying on us */ |
1806 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1807 | |
a11b0703 | 1808 | /* Set PLL en = 0 */ |
60bfe44f VS |
1809 | val = DPLL_SSC_REF_CLK_CHV | |
1810 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1811 | if (pipe != PIPE_A) |
1812 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1813 | I915_WRITE(DPLL(pipe), val); | |
1814 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1815 | |
a580516d | 1816 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1817 | |
1818 | /* Disable 10bit clock to display controller */ | |
1819 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1820 | val &= ~DPIO_DCLKP_EN; | |
1821 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1822 | ||
a580516d | 1823 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1824 | } |
1825 | ||
e4607fcf | 1826 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1827 | struct intel_digital_port *dport, |
1828 | unsigned int expected_mask) | |
89b667f8 JB |
1829 | { |
1830 | u32 port_mask; | |
f0f59a00 | 1831 | i915_reg_t dpll_reg; |
89b667f8 | 1832 | |
e4607fcf CML |
1833 | switch (dport->port) { |
1834 | case PORT_B: | |
89b667f8 | 1835 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1836 | dpll_reg = DPLL(0); |
e4607fcf CML |
1837 | break; |
1838 | case PORT_C: | |
89b667f8 | 1839 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1840 | dpll_reg = DPLL(0); |
9b6de0a1 | 1841 | expected_mask <<= 4; |
00fc31b7 CML |
1842 | break; |
1843 | case PORT_D: | |
1844 | port_mask = DPLL_PORTD_READY_MASK; | |
1845 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1846 | break; |
1847 | default: | |
1848 | BUG(); | |
1849 | } | |
89b667f8 | 1850 | |
9b6de0a1 VS |
1851 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1852 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1853 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1854 | } |
1855 | ||
b14b1055 DV |
1856 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1857 | { | |
1858 | struct drm_device *dev = crtc->base.dev; | |
1859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1860 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1861 | ||
be19f0ff CW |
1862 | if (WARN_ON(pll == NULL)) |
1863 | return; | |
1864 | ||
3e369b76 | 1865 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1866 | if (pll->active == 0) { |
1867 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1868 | WARN_ON(pll->on); | |
1869 | assert_shared_dpll_disabled(dev_priv, pll); | |
1870 | ||
1871 | pll->mode_set(dev_priv, pll); | |
1872 | } | |
1873 | } | |
1874 | ||
92f2584a | 1875 | /** |
85b3894f | 1876 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1877 | * @dev_priv: i915 private structure |
1878 | * @pipe: pipe PLL to enable | |
1879 | * | |
1880 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1881 | * drives the transcoder clock. | |
1882 | */ | |
85b3894f | 1883 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1884 | { |
3d13ef2e DL |
1885 | struct drm_device *dev = crtc->base.dev; |
1886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1887 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1888 | |
87a875bb | 1889 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1890 | return; |
1891 | ||
3e369b76 | 1892 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1893 | return; |
ee7b9f93 | 1894 | |
74dd6928 | 1895 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1896 | pll->name, pll->active, pll->on, |
e2b78267 | 1897 | crtc->base.base.id); |
92f2584a | 1898 | |
cdbd2316 DV |
1899 | if (pll->active++) { |
1900 | WARN_ON(!pll->on); | |
e9d6944e | 1901 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1902 | return; |
1903 | } | |
f4a091c7 | 1904 | WARN_ON(pll->on); |
ee7b9f93 | 1905 | |
bd2bb1b9 PZ |
1906 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1907 | ||
46edb027 | 1908 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1909 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1910 | pll->on = true; |
92f2584a JB |
1911 | } |
1912 | ||
f6daaec2 | 1913 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1914 | { |
3d13ef2e DL |
1915 | struct drm_device *dev = crtc->base.dev; |
1916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1917 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1918 | |
92f2584a | 1919 | /* PCH only available on ILK+ */ |
80aa9312 JB |
1920 | if (INTEL_INFO(dev)->gen < 5) |
1921 | return; | |
1922 | ||
eddfcbcd ML |
1923 | if (pll == NULL) |
1924 | return; | |
92f2584a | 1925 | |
eddfcbcd | 1926 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1927 | return; |
7a419866 | 1928 | |
46edb027 DV |
1929 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1930 | pll->name, pll->active, pll->on, | |
e2b78267 | 1931 | crtc->base.base.id); |
7a419866 | 1932 | |
48da64a8 | 1933 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1934 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1935 | return; |
1936 | } | |
1937 | ||
e9d6944e | 1938 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1939 | WARN_ON(!pll->on); |
cdbd2316 | 1940 | if (--pll->active) |
7a419866 | 1941 | return; |
ee7b9f93 | 1942 | |
46edb027 | 1943 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1944 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1945 | pll->on = false; |
bd2bb1b9 PZ |
1946 | |
1947 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1948 | } |
1949 | ||
b8a4f404 PZ |
1950 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1951 | enum pipe pipe) | |
040484af | 1952 | { |
23670b32 | 1953 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1954 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1955 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1956 | i915_reg_t reg; |
1957 | uint32_t val, pipeconf_val; | |
040484af JB |
1958 | |
1959 | /* PCH only available on ILK+ */ | |
55522f37 | 1960 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1961 | |
1962 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1963 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1964 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1965 | |
1966 | /* FDI must be feeding us bits for PCH ports */ | |
1967 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1968 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1969 | ||
23670b32 DV |
1970 | if (HAS_PCH_CPT(dev)) { |
1971 | /* Workaround: Set the timing override bit before enabling the | |
1972 | * pch transcoder. */ | |
1973 | reg = TRANS_CHICKEN2(pipe); | |
1974 | val = I915_READ(reg); | |
1975 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1976 | I915_WRITE(reg, val); | |
59c859d6 | 1977 | } |
23670b32 | 1978 | |
ab9412ba | 1979 | reg = PCH_TRANSCONF(pipe); |
040484af | 1980 | val = I915_READ(reg); |
5f7f726d | 1981 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1982 | |
1983 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1984 | /* | |
c5de7c6f VS |
1985 | * Make the BPC in transcoder be consistent with |
1986 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1987 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1988 | */ |
dfd07d72 | 1989 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1990 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1991 | val |= PIPECONF_8BPC; | |
1992 | else | |
1993 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1994 | } |
5f7f726d PZ |
1995 | |
1996 | val &= ~TRANS_INTERLACE_MASK; | |
1997 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1998 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1999 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2000 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2001 | else | |
2002 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2003 | else |
2004 | val |= TRANS_PROGRESSIVE; | |
2005 | ||
040484af JB |
2006 | I915_WRITE(reg, val | TRANS_ENABLE); |
2007 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2008 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2009 | } |
2010 | ||
8fb033d7 | 2011 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2012 | enum transcoder cpu_transcoder) |
040484af | 2013 | { |
8fb033d7 | 2014 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2015 | |
2016 | /* PCH only available on ILK+ */ | |
55522f37 | 2017 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2018 | |
8fb033d7 | 2019 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2020 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2021 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2022 | |
223a6fdf | 2023 | /* Workaround: set timing override bit. */ |
36c0d0cf | 2024 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2025 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2026 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 2027 | |
25f3ef11 | 2028 | val = TRANS_ENABLE; |
937bb610 | 2029 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2030 | |
9a76b1c6 PZ |
2031 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2032 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2033 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2034 | else |
2035 | val |= TRANS_PROGRESSIVE; | |
2036 | ||
ab9412ba DV |
2037 | I915_WRITE(LPT_TRANSCONF, val); |
2038 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2039 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2040 | } |
2041 | ||
b8a4f404 PZ |
2042 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2043 | enum pipe pipe) | |
040484af | 2044 | { |
23670b32 | 2045 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
2046 | i915_reg_t reg; |
2047 | uint32_t val; | |
040484af JB |
2048 | |
2049 | /* FDI relies on the transcoder */ | |
2050 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2051 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2052 | ||
291906f1 JB |
2053 | /* Ports must be off as well */ |
2054 | assert_pch_ports_disabled(dev_priv, pipe); | |
2055 | ||
ab9412ba | 2056 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2057 | val = I915_READ(reg); |
2058 | val &= ~TRANS_ENABLE; | |
2059 | I915_WRITE(reg, val); | |
2060 | /* wait for PCH transcoder off, transcoder state */ | |
2061 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2062 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 2063 | |
c465613b | 2064 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
2065 | /* Workaround: Clear the timing override chicken bit again. */ |
2066 | reg = TRANS_CHICKEN2(pipe); | |
2067 | val = I915_READ(reg); | |
2068 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2069 | I915_WRITE(reg, val); | |
2070 | } | |
040484af JB |
2071 | } |
2072 | ||
ab4d966c | 2073 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2074 | { |
8fb033d7 PZ |
2075 | u32 val; |
2076 | ||
ab9412ba | 2077 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2078 | val &= ~TRANS_ENABLE; |
ab9412ba | 2079 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2080 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2081 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2082 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2083 | |
2084 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 2085 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2086 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2087 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
2088 | } |
2089 | ||
b24e7179 | 2090 | /** |
309cfea8 | 2091 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2092 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2093 | * |
0372264a | 2094 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2095 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2096 | */ |
e1fdc473 | 2097 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2098 | { |
0372264a PZ |
2099 | struct drm_device *dev = crtc->base.dev; |
2100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2101 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 2102 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 2103 | enum pipe pch_transcoder; |
f0f59a00 | 2104 | i915_reg_t reg; |
b24e7179 JB |
2105 | u32 val; |
2106 | ||
9e2ee2dd VS |
2107 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2108 | ||
58c6eaa2 | 2109 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2110 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2111 | assert_sprites_disabled(dev_priv, pipe); |
2112 | ||
681e5811 | 2113 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2114 | pch_transcoder = TRANSCODER_A; |
2115 | else | |
2116 | pch_transcoder = pipe; | |
2117 | ||
b24e7179 JB |
2118 | /* |
2119 | * A pipe without a PLL won't actually be able to drive bits from | |
2120 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2121 | * need the check. | |
2122 | */ | |
50360403 | 2123 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
a65347ba | 2124 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
2125 | assert_dsi_pll_enabled(dev_priv); |
2126 | else | |
2127 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2128 | else { |
6e3c9717 | 2129 | if (crtc->config->has_pch_encoder) { |
040484af | 2130 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2131 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2132 | assert_fdi_tx_pll_enabled(dev_priv, |
2133 | (enum pipe) cpu_transcoder); | |
040484af JB |
2134 | } |
2135 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2136 | } | |
b24e7179 | 2137 | |
702e7a56 | 2138 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2139 | val = I915_READ(reg); |
7ad25d48 | 2140 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2141 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2142 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2143 | return; |
7ad25d48 | 2144 | } |
00d70b15 CW |
2145 | |
2146 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2147 | POSTING_READ(reg); |
b7792d8b VS |
2148 | |
2149 | /* | |
2150 | * Until the pipe starts DSL will read as 0, which would cause | |
2151 | * an apparent vblank timestamp jump, which messes up also the | |
2152 | * frame count when it's derived from the timestamps. So let's | |
2153 | * wait for the pipe to start properly before we call | |
2154 | * drm_crtc_vblank_on() | |
2155 | */ | |
2156 | if (dev->max_vblank_count == 0 && | |
2157 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2158 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2159 | } |
2160 | ||
2161 | /** | |
309cfea8 | 2162 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2163 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2164 | * |
575f7ab7 VS |
2165 | * Disable the pipe of @crtc, making sure that various hardware |
2166 | * specific requirements are met, if applicable, e.g. plane | |
2167 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2168 | * |
2169 | * Will wait until the pipe has shut down before returning. | |
2170 | */ | |
575f7ab7 | 2171 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2172 | { |
575f7ab7 | 2173 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2174 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2175 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2176 | i915_reg_t reg; |
b24e7179 JB |
2177 | u32 val; |
2178 | ||
9e2ee2dd VS |
2179 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2180 | ||
b24e7179 JB |
2181 | /* |
2182 | * Make sure planes won't keep trying to pump pixels to us, | |
2183 | * or we might hang the display. | |
2184 | */ | |
2185 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2186 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2187 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2188 | |
702e7a56 | 2189 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2190 | val = I915_READ(reg); |
00d70b15 CW |
2191 | if ((val & PIPECONF_ENABLE) == 0) |
2192 | return; | |
2193 | ||
67adc644 VS |
2194 | /* |
2195 | * Double wide has implications for planes | |
2196 | * so best keep it disabled when not needed. | |
2197 | */ | |
6e3c9717 | 2198 | if (crtc->config->double_wide) |
67adc644 VS |
2199 | val &= ~PIPECONF_DOUBLE_WIDE; |
2200 | ||
2201 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2202 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2203 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2204 | val &= ~PIPECONF_ENABLE; |
2205 | ||
2206 | I915_WRITE(reg, val); | |
2207 | if ((val & PIPECONF_ENABLE) == 0) | |
2208 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2209 | } |
2210 | ||
693db184 CW |
2211 | static bool need_vtd_wa(struct drm_device *dev) |
2212 | { | |
2213 | #ifdef CONFIG_INTEL_IOMMU | |
2214 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2215 | return true; | |
2216 | #endif | |
2217 | return false; | |
2218 | } | |
2219 | ||
832be82f VS |
2220 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2221 | { | |
2222 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2223 | } | |
2224 | ||
7b49f948 VS |
2225 | static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv, |
2226 | uint64_t fb_modifier, unsigned int cpp) | |
2227 | { | |
2228 | switch (fb_modifier) { | |
2229 | case DRM_FORMAT_MOD_NONE: | |
2230 | return cpp; | |
2231 | case I915_FORMAT_MOD_X_TILED: | |
2232 | if (IS_GEN2(dev_priv)) | |
2233 | return 128; | |
2234 | else | |
2235 | return 512; | |
2236 | case I915_FORMAT_MOD_Y_TILED: | |
2237 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2238 | return 128; | |
2239 | else | |
2240 | return 512; | |
2241 | case I915_FORMAT_MOD_Yf_TILED: | |
2242 | switch (cpp) { | |
2243 | case 1: | |
2244 | return 64; | |
2245 | case 2: | |
2246 | case 4: | |
2247 | return 128; | |
2248 | case 8: | |
2249 | case 16: | |
2250 | return 256; | |
2251 | default: | |
2252 | MISSING_CASE(cpp); | |
2253 | return cpp; | |
2254 | } | |
2255 | break; | |
2256 | default: | |
2257 | MISSING_CASE(fb_modifier); | |
2258 | return cpp; | |
2259 | } | |
2260 | } | |
2261 | ||
832be82f VS |
2262 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2263 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2264 | { |
832be82f VS |
2265 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2266 | return 1; | |
2267 | else | |
2268 | return intel_tile_size(dev_priv) / | |
2269 | intel_tile_width(dev_priv, fb_modifier, cpp); | |
6761dd31 TU |
2270 | } |
2271 | ||
2272 | unsigned int | |
2273 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2274 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2275 | { |
832be82f VS |
2276 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2277 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2278 | ||
2279 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2280 | } |
2281 | ||
75c82a53 | 2282 | static void |
f64b98cd TU |
2283 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
2284 | const struct drm_plane_state *plane_state) | |
2285 | { | |
832be82f | 2286 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
7723f47d | 2287 | struct intel_rotation_info *info = &view->params.rotated; |
d9b3288e | 2288 | unsigned int tile_size, tile_width, tile_height, cpp; |
50470bb0 | 2289 | |
f64b98cd TU |
2290 | *view = i915_ggtt_view_normal; |
2291 | ||
50470bb0 | 2292 | if (!plane_state) |
75c82a53 | 2293 | return; |
50470bb0 | 2294 | |
121920fa | 2295 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
75c82a53 | 2296 | return; |
50470bb0 | 2297 | |
9abc4648 | 2298 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2299 | |
2300 | info->height = fb->height; | |
2301 | info->pixel_format = fb->pixel_format; | |
2302 | info->pitch = fb->pitches[0]; | |
89e3e142 | 2303 | info->uv_offset = fb->offsets[1]; |
50470bb0 TU |
2304 | info->fb_modifier = fb->modifier[0]; |
2305 | ||
d9b3288e VS |
2306 | tile_size = intel_tile_size(dev_priv); |
2307 | ||
2308 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
b16bb01f | 2309 | tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp); |
d9b3288e VS |
2310 | tile_height = tile_size / tile_width; |
2311 | ||
2312 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width); | |
84fe03f7 | 2313 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); |
d9b3288e | 2314 | info->size = info->width_pages * info->height_pages * tile_size; |
84fe03f7 | 2315 | |
89e3e142 | 2316 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2317 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
d9b3288e VS |
2318 | tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp); |
2319 | tile_height = tile_size / tile_width; | |
2320 | ||
2321 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width); | |
832be82f | 2322 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height); |
d9b3288e | 2323 | info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size; |
89e3e142 | 2324 | } |
f64b98cd TU |
2325 | } |
2326 | ||
603525d7 | 2327 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2328 | { |
2329 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2330 | return 256 * 1024; | |
985b8bb4 | 2331 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2332 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2333 | return 128 * 1024; |
2334 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2335 | return 4 * 1024; | |
2336 | else | |
44c5905e | 2337 | return 0; |
4e9a86b6 VS |
2338 | } |
2339 | ||
603525d7 VS |
2340 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2341 | uint64_t fb_modifier) | |
2342 | { | |
2343 | switch (fb_modifier) { | |
2344 | case DRM_FORMAT_MOD_NONE: | |
2345 | return intel_linear_alignment(dev_priv); | |
2346 | case I915_FORMAT_MOD_X_TILED: | |
2347 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2348 | return 256 * 1024; | |
2349 | return 0; | |
2350 | case I915_FORMAT_MOD_Y_TILED: | |
2351 | case I915_FORMAT_MOD_Yf_TILED: | |
2352 | return 1 * 1024 * 1024; | |
2353 | default: | |
2354 | MISSING_CASE(fb_modifier); | |
2355 | return 0; | |
2356 | } | |
2357 | } | |
2358 | ||
127bd2ac | 2359 | int |
850c4cdc TU |
2360 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2361 | struct drm_framebuffer *fb, | |
7580d774 | 2362 | const struct drm_plane_state *plane_state) |
6b95a207 | 2363 | { |
850c4cdc | 2364 | struct drm_device *dev = fb->dev; |
ce453d81 | 2365 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2366 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2367 | struct i915_ggtt_view view; |
6b95a207 KH |
2368 | u32 alignment; |
2369 | int ret; | |
2370 | ||
ebcdd39e MR |
2371 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2372 | ||
603525d7 | 2373 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2374 | |
75c82a53 | 2375 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2376 | |
693db184 CW |
2377 | /* Note that the w/a also requires 64 PTE of padding following the |
2378 | * bo. We currently fill all unused PTE with the shadow page and so | |
2379 | * we should always have valid PTE following the scanout preventing | |
2380 | * the VT-d warning. | |
2381 | */ | |
2382 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2383 | alignment = 256 * 1024; | |
2384 | ||
d6dd6843 PZ |
2385 | /* |
2386 | * Global gtt pte registers are special registers which actually forward | |
2387 | * writes to a chunk of system memory. Which means that there is no risk | |
2388 | * that the register values disappear as soon as we call | |
2389 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2390 | * pin/unpin/fence and not more. | |
2391 | */ | |
2392 | intel_runtime_pm_get(dev_priv); | |
2393 | ||
7580d774 ML |
2394 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2395 | &view); | |
48b956c5 | 2396 | if (ret) |
b26a6b35 | 2397 | goto err_pm; |
6b95a207 KH |
2398 | |
2399 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2400 | * fence, whereas 965+ only requires a fence if using | |
2401 | * framebuffer compression. For simplicity, we always install | |
2402 | * a fence as the cost is not that onerous. | |
2403 | */ | |
9807216f VK |
2404 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2405 | ret = i915_gem_object_get_fence(obj); | |
2406 | if (ret == -EDEADLK) { | |
2407 | /* | |
2408 | * -EDEADLK means there are no free fences | |
2409 | * no pending flips. | |
2410 | * | |
2411 | * This is propagated to atomic, but it uses | |
2412 | * -EDEADLK to force a locking recovery, so | |
2413 | * change the returned error to -EBUSY. | |
2414 | */ | |
2415 | ret = -EBUSY; | |
2416 | goto err_unpin; | |
2417 | } else if (ret) | |
2418 | goto err_unpin; | |
1690e1eb | 2419 | |
9807216f VK |
2420 | i915_gem_object_pin_fence(obj); |
2421 | } | |
6b95a207 | 2422 | |
d6dd6843 | 2423 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2424 | return 0; |
48b956c5 CW |
2425 | |
2426 | err_unpin: | |
f64b98cd | 2427 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2428 | err_pm: |
d6dd6843 | 2429 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2430 | return ret; |
6b95a207 KH |
2431 | } |
2432 | ||
82bc3b2d TU |
2433 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2434 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2435 | { |
82bc3b2d | 2436 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2437 | struct i915_ggtt_view view; |
82bc3b2d | 2438 | |
ebcdd39e MR |
2439 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2440 | ||
75c82a53 | 2441 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2442 | |
9807216f VK |
2443 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2444 | i915_gem_object_unpin_fence(obj); | |
2445 | ||
f64b98cd | 2446 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2447 | } |
2448 | ||
c2c75131 DV |
2449 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2450 | * is assumed to be a power-of-two. */ | |
54ea9da8 VS |
2451 | u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv, |
2452 | int *x, int *y, | |
2453 | uint64_t fb_modifier, | |
2454 | unsigned int cpp, | |
2455 | unsigned int pitch) | |
c2c75131 | 2456 | { |
b5c65338 | 2457 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
d843310d | 2458 | unsigned int tile_size, tile_width, tile_height; |
bc752862 | 2459 | unsigned int tile_rows, tiles; |
c2c75131 | 2460 | |
d843310d VS |
2461 | tile_size = intel_tile_size(dev_priv); |
2462 | tile_width = intel_tile_width(dev_priv, fb_modifier, cpp); | |
2463 | tile_height = tile_size / tile_width; | |
2464 | ||
2465 | tile_rows = *y / tile_height; | |
2466 | *y %= tile_height; | |
c2c75131 | 2467 | |
d843310d VS |
2468 | tiles = *x / (tile_width/cpp); |
2469 | *x %= tile_width/cpp; | |
bc752862 | 2470 | |
d843310d | 2471 | return tile_rows * pitch * tile_height + tiles * tile_size; |
bc752862 | 2472 | } else { |
4e9a86b6 | 2473 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
bc752862 CW |
2474 | unsigned int offset; |
2475 | ||
2476 | offset = *y * pitch + *x * cpp; | |
4e9a86b6 VS |
2477 | *y = (offset & alignment) / pitch; |
2478 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
2479 | return offset & ~alignment; | |
bc752862 | 2480 | } |
c2c75131 DV |
2481 | } |
2482 | ||
b35d63fa | 2483 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2484 | { |
2485 | switch (format) { | |
2486 | case DISPPLANE_8BPP: | |
2487 | return DRM_FORMAT_C8; | |
2488 | case DISPPLANE_BGRX555: | |
2489 | return DRM_FORMAT_XRGB1555; | |
2490 | case DISPPLANE_BGRX565: | |
2491 | return DRM_FORMAT_RGB565; | |
2492 | default: | |
2493 | case DISPPLANE_BGRX888: | |
2494 | return DRM_FORMAT_XRGB8888; | |
2495 | case DISPPLANE_RGBX888: | |
2496 | return DRM_FORMAT_XBGR8888; | |
2497 | case DISPPLANE_BGRX101010: | |
2498 | return DRM_FORMAT_XRGB2101010; | |
2499 | case DISPPLANE_RGBX101010: | |
2500 | return DRM_FORMAT_XBGR2101010; | |
2501 | } | |
2502 | } | |
2503 | ||
bc8d7dff DL |
2504 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2505 | { | |
2506 | switch (format) { | |
2507 | case PLANE_CTL_FORMAT_RGB_565: | |
2508 | return DRM_FORMAT_RGB565; | |
2509 | default: | |
2510 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2511 | if (rgb_order) { | |
2512 | if (alpha) | |
2513 | return DRM_FORMAT_ABGR8888; | |
2514 | else | |
2515 | return DRM_FORMAT_XBGR8888; | |
2516 | } else { | |
2517 | if (alpha) | |
2518 | return DRM_FORMAT_ARGB8888; | |
2519 | else | |
2520 | return DRM_FORMAT_XRGB8888; | |
2521 | } | |
2522 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2523 | if (rgb_order) | |
2524 | return DRM_FORMAT_XBGR2101010; | |
2525 | else | |
2526 | return DRM_FORMAT_XRGB2101010; | |
2527 | } | |
2528 | } | |
2529 | ||
5724dbd1 | 2530 | static bool |
f6936e29 DV |
2531 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2532 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2533 | { |
2534 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2535 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb JB |
2536 | struct drm_i915_gem_object *obj = NULL; |
2537 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2538 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2539 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2540 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2541 | PAGE_SIZE); | |
2542 | ||
2543 | size_aligned -= base_aligned; | |
46f297fb | 2544 | |
ff2652ea CW |
2545 | if (plane_config->size == 0) |
2546 | return false; | |
2547 | ||
3badb49f PZ |
2548 | /* If the FB is too big, just don't use it since fbdev is not very |
2549 | * important and we should probably use that space with FBC or other | |
2550 | * features. */ | |
2551 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) | |
2552 | return false; | |
2553 | ||
12c83d99 TU |
2554 | mutex_lock(&dev->struct_mutex); |
2555 | ||
f37b5c2b DV |
2556 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2557 | base_aligned, | |
2558 | base_aligned, | |
2559 | size_aligned); | |
12c83d99 TU |
2560 | if (!obj) { |
2561 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2562 | return false; |
12c83d99 | 2563 | } |
46f297fb | 2564 | |
49af449b DL |
2565 | obj->tiling_mode = plane_config->tiling; |
2566 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2567 | obj->stride = fb->pitches[0]; |
46f297fb | 2568 | |
6bf129df DL |
2569 | mode_cmd.pixel_format = fb->pixel_format; |
2570 | mode_cmd.width = fb->width; | |
2571 | mode_cmd.height = fb->height; | |
2572 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2573 | mode_cmd.modifier[0] = fb->modifier[0]; |
2574 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2575 | |
6bf129df | 2576 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2577 | &mode_cmd, obj)) { |
46f297fb JB |
2578 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2579 | goto out_unref_obj; | |
2580 | } | |
12c83d99 | 2581 | |
46f297fb | 2582 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2583 | |
f6936e29 | 2584 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2585 | return true; |
46f297fb JB |
2586 | |
2587 | out_unref_obj: | |
2588 | drm_gem_object_unreference(&obj->base); | |
2589 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2590 | return false; |
2591 | } | |
2592 | ||
afd65eb4 MR |
2593 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2594 | static void | |
2595 | update_state_fb(struct drm_plane *plane) | |
2596 | { | |
2597 | if (plane->fb == plane->state->fb) | |
2598 | return; | |
2599 | ||
2600 | if (plane->state->fb) | |
2601 | drm_framebuffer_unreference(plane->state->fb); | |
2602 | plane->state->fb = plane->fb; | |
2603 | if (plane->state->fb) | |
2604 | drm_framebuffer_reference(plane->state->fb); | |
2605 | } | |
2606 | ||
5724dbd1 | 2607 | static void |
f6936e29 DV |
2608 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2609 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2610 | { |
2611 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2612 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2613 | struct drm_crtc *c; |
2614 | struct intel_crtc *i; | |
2ff8fde1 | 2615 | struct drm_i915_gem_object *obj; |
88595ac9 | 2616 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2617 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2618 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2619 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2620 | struct intel_plane_state *intel_state = |
2621 | to_intel_plane_state(plane_state); | |
88595ac9 | 2622 | struct drm_framebuffer *fb; |
484b41dd | 2623 | |
2d14030b | 2624 | if (!plane_config->fb) |
484b41dd JB |
2625 | return; |
2626 | ||
f6936e29 | 2627 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2628 | fb = &plane_config->fb->base; |
2629 | goto valid_fb; | |
f55548b5 | 2630 | } |
484b41dd | 2631 | |
2d14030b | 2632 | kfree(plane_config->fb); |
484b41dd JB |
2633 | |
2634 | /* | |
2635 | * Failed to alloc the obj, check to see if we should share | |
2636 | * an fb with another CRTC instead | |
2637 | */ | |
70e1e0ec | 2638 | for_each_crtc(dev, c) { |
484b41dd JB |
2639 | i = to_intel_crtc(c); |
2640 | ||
2641 | if (c == &intel_crtc->base) | |
2642 | continue; | |
2643 | ||
2ff8fde1 MR |
2644 | if (!i->active) |
2645 | continue; | |
2646 | ||
88595ac9 DV |
2647 | fb = c->primary->fb; |
2648 | if (!fb) | |
484b41dd JB |
2649 | continue; |
2650 | ||
88595ac9 | 2651 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2652 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2653 | drm_framebuffer_reference(fb); |
2654 | goto valid_fb; | |
484b41dd JB |
2655 | } |
2656 | } | |
88595ac9 | 2657 | |
200757f5 MR |
2658 | /* |
2659 | * We've failed to reconstruct the BIOS FB. Current display state | |
2660 | * indicates that the primary plane is visible, but has a NULL FB, | |
2661 | * which will lead to problems later if we don't fix it up. The | |
2662 | * simplest solution is to just disable the primary plane now and | |
2663 | * pretend the BIOS never had it enabled. | |
2664 | */ | |
2665 | to_intel_plane_state(plane_state)->visible = false; | |
2666 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2667 | intel_pre_disable_primary(&intel_crtc->base); | |
2668 | intel_plane->disable_plane(primary, &intel_crtc->base); | |
2669 | ||
88595ac9 DV |
2670 | return; |
2671 | ||
2672 | valid_fb: | |
f44e2659 VS |
2673 | plane_state->src_x = 0; |
2674 | plane_state->src_y = 0; | |
be5651f2 ML |
2675 | plane_state->src_w = fb->width << 16; |
2676 | plane_state->src_h = fb->height << 16; | |
2677 | ||
f44e2659 VS |
2678 | plane_state->crtc_x = 0; |
2679 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2680 | plane_state->crtc_w = fb->width; |
2681 | plane_state->crtc_h = fb->height; | |
2682 | ||
0a8d8a86 MR |
2683 | intel_state->src.x1 = plane_state->src_x; |
2684 | intel_state->src.y1 = plane_state->src_y; | |
2685 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2686 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2687 | intel_state->dst.x1 = plane_state->crtc_x; | |
2688 | intel_state->dst.y1 = plane_state->crtc_y; | |
2689 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2690 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2691 | ||
88595ac9 DV |
2692 | obj = intel_fb_obj(fb); |
2693 | if (obj->tiling_mode != I915_TILING_NONE) | |
2694 | dev_priv->preserve_bios_swizzle = true; | |
2695 | ||
be5651f2 ML |
2696 | drm_framebuffer_reference(fb); |
2697 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2698 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2699 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2700 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2701 | } |
2702 | ||
a8d201af ML |
2703 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2704 | const struct intel_crtc_state *crtc_state, | |
2705 | const struct intel_plane_state *plane_state) | |
81255565 | 2706 | { |
a8d201af | 2707 | struct drm_device *dev = primary->dev; |
81255565 | 2708 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2709 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2710 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2711 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2712 | int plane = intel_crtc->plane; |
54ea9da8 | 2713 | u32 linear_offset; |
81255565 | 2714 | u32 dspcntr; |
f0f59a00 | 2715 | i915_reg_t reg = DSPCNTR(plane); |
ac484963 | 2716 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2717 | int x = plane_state->src.x1 >> 16; |
2718 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2719 | |
f45651ba VS |
2720 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2721 | ||
fdd508a6 | 2722 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2723 | |
2724 | if (INTEL_INFO(dev)->gen < 4) { | |
2725 | if (intel_crtc->pipe == PIPE_B) | |
2726 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2727 | ||
2728 | /* pipesrc and dspsize control the size that is scaled from, | |
2729 | * which should always be the user's requested size. | |
2730 | */ | |
2731 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2732 | ((crtc_state->pipe_src_h - 1) << 16) | |
2733 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2734 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2735 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2736 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2737 | ((crtc_state->pipe_src_h - 1) << 16) | |
2738 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2739 | I915_WRITE(PRIMPOS(plane), 0); |
2740 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2741 | } |
81255565 | 2742 | |
57779d06 VS |
2743 | switch (fb->pixel_format) { |
2744 | case DRM_FORMAT_C8: | |
81255565 JB |
2745 | dspcntr |= DISPPLANE_8BPP; |
2746 | break; | |
57779d06 | 2747 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2748 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2749 | break; |
57779d06 VS |
2750 | case DRM_FORMAT_RGB565: |
2751 | dspcntr |= DISPPLANE_BGRX565; | |
2752 | break; | |
2753 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2754 | dspcntr |= DISPPLANE_BGRX888; |
2755 | break; | |
2756 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2757 | dspcntr |= DISPPLANE_RGBX888; |
2758 | break; | |
2759 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2760 | dspcntr |= DISPPLANE_BGRX101010; |
2761 | break; | |
2762 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2763 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2764 | break; |
2765 | default: | |
baba133a | 2766 | BUG(); |
81255565 | 2767 | } |
57779d06 | 2768 | |
f45651ba VS |
2769 | if (INTEL_INFO(dev)->gen >= 4 && |
2770 | obj->tiling_mode != I915_TILING_NONE) | |
2771 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2772 | |
de1aa629 VS |
2773 | if (IS_G4X(dev)) |
2774 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2775 | ||
ac484963 | 2776 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2777 | |
c2c75131 DV |
2778 | if (INTEL_INFO(dev)->gen >= 4) { |
2779 | intel_crtc->dspaddr_offset = | |
ce1e5c14 | 2780 | intel_compute_tile_offset(dev_priv, &x, &y, |
ac484963 | 2781 | fb->modifier[0], cpp, |
ce1e5c14 | 2782 | fb->pitches[0]); |
c2c75131 DV |
2783 | linear_offset -= intel_crtc->dspaddr_offset; |
2784 | } else { | |
e506a0c6 | 2785 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2786 | } |
e506a0c6 | 2787 | |
a8d201af | 2788 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2789 | dspcntr |= DISPPLANE_ROTATE_180; |
2790 | ||
a8d201af ML |
2791 | x += (crtc_state->pipe_src_w - 1); |
2792 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2793 | |
2794 | /* Finding the last pixel of the last line of the display | |
2795 | data and adding to linear_offset*/ | |
2796 | linear_offset += | |
a8d201af | 2797 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2798 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2799 | } |
2800 | ||
2db3366b PZ |
2801 | intel_crtc->adjusted_x = x; |
2802 | intel_crtc->adjusted_y = y; | |
2803 | ||
48404c1e SJ |
2804 | I915_WRITE(reg, dspcntr); |
2805 | ||
01f2c773 | 2806 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2807 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2808 | I915_WRITE(DSPSURF(plane), |
2809 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2810 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2811 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2812 | } else |
f343c5f6 | 2813 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2814 | POSTING_READ(reg); |
17638cd6 JB |
2815 | } |
2816 | ||
a8d201af ML |
2817 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2818 | struct drm_crtc *crtc) | |
17638cd6 JB |
2819 | { |
2820 | struct drm_device *dev = crtc->dev; | |
2821 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2822 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
17638cd6 | 2823 | int plane = intel_crtc->plane; |
f45651ba | 2824 | |
a8d201af ML |
2825 | I915_WRITE(DSPCNTR(plane), 0); |
2826 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2827 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2828 | else |
2829 | I915_WRITE(DSPADDR(plane), 0); | |
2830 | POSTING_READ(DSPCNTR(plane)); | |
2831 | } | |
c9ba6fad | 2832 | |
a8d201af ML |
2833 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2834 | const struct intel_crtc_state *crtc_state, | |
2835 | const struct intel_plane_state *plane_state) | |
2836 | { | |
2837 | struct drm_device *dev = primary->dev; | |
2838 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2839 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2840 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2841 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2842 | int plane = intel_crtc->plane; | |
54ea9da8 | 2843 | u32 linear_offset; |
a8d201af ML |
2844 | u32 dspcntr; |
2845 | i915_reg_t reg = DSPCNTR(plane); | |
ac484963 | 2846 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2847 | int x = plane_state->src.x1 >> 16; |
2848 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2849 | |
f45651ba | 2850 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2851 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2852 | |
2853 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2854 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2855 | |
57779d06 VS |
2856 | switch (fb->pixel_format) { |
2857 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2858 | dspcntr |= DISPPLANE_8BPP; |
2859 | break; | |
57779d06 VS |
2860 | case DRM_FORMAT_RGB565: |
2861 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2862 | break; |
57779d06 | 2863 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2864 | dspcntr |= DISPPLANE_BGRX888; |
2865 | break; | |
2866 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2867 | dspcntr |= DISPPLANE_RGBX888; |
2868 | break; | |
2869 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2870 | dspcntr |= DISPPLANE_BGRX101010; |
2871 | break; | |
2872 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2873 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2874 | break; |
2875 | default: | |
baba133a | 2876 | BUG(); |
17638cd6 JB |
2877 | } |
2878 | ||
2879 | if (obj->tiling_mode != I915_TILING_NONE) | |
2880 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2881 | |
f45651ba | 2882 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2883 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2884 | |
ac484963 | 2885 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2886 | intel_crtc->dspaddr_offset = |
ce1e5c14 | 2887 | intel_compute_tile_offset(dev_priv, &x, &y, |
ac484963 | 2888 | fb->modifier[0], cpp, |
ce1e5c14 | 2889 | fb->pitches[0]); |
c2c75131 | 2890 | linear_offset -= intel_crtc->dspaddr_offset; |
a8d201af | 2891 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2892 | dspcntr |= DISPPLANE_ROTATE_180; |
2893 | ||
2894 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2895 | x += (crtc_state->pipe_src_w - 1); |
2896 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2897 | |
2898 | /* Finding the last pixel of the last line of the display | |
2899 | data and adding to linear_offset*/ | |
2900 | linear_offset += | |
a8d201af | 2901 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2902 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2903 | } |
2904 | } | |
2905 | ||
2db3366b PZ |
2906 | intel_crtc->adjusted_x = x; |
2907 | intel_crtc->adjusted_y = y; | |
2908 | ||
48404c1e | 2909 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2910 | |
01f2c773 | 2911 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2912 | I915_WRITE(DSPSURF(plane), |
2913 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2914 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2915 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2916 | } else { | |
2917 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2918 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2919 | } | |
17638cd6 | 2920 | POSTING_READ(reg); |
17638cd6 JB |
2921 | } |
2922 | ||
7b49f948 VS |
2923 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2924 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2925 | { |
7b49f948 | 2926 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2927 | return 64; |
7b49f948 VS |
2928 | } else { |
2929 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2930 | ||
2931 | return intel_tile_width(dev_priv, fb_modifier, cpp); | |
b321803d DL |
2932 | } |
2933 | } | |
2934 | ||
44eb0cb9 MK |
2935 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2936 | struct drm_i915_gem_object *obj, | |
2937 | unsigned int plane) | |
121920fa | 2938 | { |
ce7f1728 | 2939 | struct i915_ggtt_view view; |
dedf278c | 2940 | struct i915_vma *vma; |
44eb0cb9 | 2941 | u64 offset; |
121920fa | 2942 | |
e7941294 | 2943 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
ce7f1728 | 2944 | intel_plane->base.state); |
121920fa | 2945 | |
ce7f1728 | 2946 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2947 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2948 | view.type)) |
dedf278c TU |
2949 | return -1; |
2950 | ||
44eb0cb9 | 2951 | offset = vma->node.start; |
dedf278c TU |
2952 | |
2953 | if (plane == 1) { | |
7723f47d | 2954 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
2955 | PAGE_SIZE; |
2956 | } | |
2957 | ||
44eb0cb9 MK |
2958 | WARN_ON(upper_32_bits(offset)); |
2959 | ||
2960 | return lower_32_bits(offset); | |
121920fa TU |
2961 | } |
2962 | ||
e435d6e5 ML |
2963 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2964 | { | |
2965 | struct drm_device *dev = intel_crtc->base.dev; | |
2966 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2967 | ||
2968 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2969 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2970 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2971 | } |
2972 | ||
a1b2278e CK |
2973 | /* |
2974 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2975 | */ | |
0583236e | 2976 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2977 | { |
a1b2278e CK |
2978 | struct intel_crtc_scaler_state *scaler_state; |
2979 | int i; | |
2980 | ||
a1b2278e CK |
2981 | scaler_state = &intel_crtc->config->scaler_state; |
2982 | ||
2983 | /* loop through and disable scalers that aren't in use */ | |
2984 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2985 | if (!scaler_state->scalers[i].in_use) |
2986 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2987 | } |
2988 | } | |
2989 | ||
6156a456 | 2990 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2991 | { |
6156a456 | 2992 | switch (pixel_format) { |
d161cf7a | 2993 | case DRM_FORMAT_C8: |
c34ce3d1 | 2994 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2995 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2996 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2997 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2998 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2999 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3000 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3001 | /* |
3002 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3003 | * to be already pre-multiplied. We need to add a knob (or a different | |
3004 | * DRM_FORMAT) for user-space to configure that. | |
3005 | */ | |
f75fb42a | 3006 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3007 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3008 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3009 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3010 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3011 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3012 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3013 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3014 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3015 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3016 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3017 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3018 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3019 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3020 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3021 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3022 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3023 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3024 | default: |
4249eeef | 3025 | MISSING_CASE(pixel_format); |
70d21f0e | 3026 | } |
8cfcba41 | 3027 | |
c34ce3d1 | 3028 | return 0; |
6156a456 | 3029 | } |
70d21f0e | 3030 | |
6156a456 CK |
3031 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3032 | { | |
6156a456 | 3033 | switch (fb_modifier) { |
30af77c4 | 3034 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3035 | break; |
30af77c4 | 3036 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3037 | return PLANE_CTL_TILED_X; |
b321803d | 3038 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3039 | return PLANE_CTL_TILED_Y; |
b321803d | 3040 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3041 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3042 | default: |
6156a456 | 3043 | MISSING_CASE(fb_modifier); |
70d21f0e | 3044 | } |
8cfcba41 | 3045 | |
c34ce3d1 | 3046 | return 0; |
6156a456 | 3047 | } |
70d21f0e | 3048 | |
6156a456 CK |
3049 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3050 | { | |
3b7a5119 | 3051 | switch (rotation) { |
6156a456 CK |
3052 | case BIT(DRM_ROTATE_0): |
3053 | break; | |
1e8df167 SJ |
3054 | /* |
3055 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3056 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3057 | */ | |
3b7a5119 | 3058 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3059 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3060 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3061 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3062 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3063 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3064 | default: |
3065 | MISSING_CASE(rotation); | |
3066 | } | |
3067 | ||
c34ce3d1 | 3068 | return 0; |
6156a456 CK |
3069 | } |
3070 | ||
a8d201af ML |
3071 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3072 | const struct intel_crtc_state *crtc_state, | |
3073 | const struct intel_plane_state *plane_state) | |
6156a456 | 3074 | { |
a8d201af | 3075 | struct drm_device *dev = plane->dev; |
6156a456 | 3076 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
3077 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3078 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3079 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
3080 | int pipe = intel_crtc->pipe; |
3081 | u32 plane_ctl, stride_div, stride; | |
3082 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 3083 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 3084 | int x_offset, y_offset; |
44eb0cb9 | 3085 | u32 surf_addr; |
a8d201af ML |
3086 | int scaler_id = plane_state->scaler_id; |
3087 | int src_x = plane_state->src.x1 >> 16; | |
3088 | int src_y = plane_state->src.y1 >> 16; | |
3089 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3090 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3091 | int dst_x = plane_state->dst.x1; | |
3092 | int dst_y = plane_state->dst.y1; | |
3093 | int dst_w = drm_rect_width(&plane_state->dst); | |
3094 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3095 | |
6156a456 CK |
3096 | plane_ctl = PLANE_CTL_ENABLE | |
3097 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3098 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3099 | ||
3100 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3101 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3102 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3103 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3104 | ||
7b49f948 | 3105 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3106 | fb->pixel_format); |
dedf278c | 3107 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3108 | |
a42e5a23 PZ |
3109 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3110 | ||
3b7a5119 | 3111 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3112 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3113 | ||
3b7a5119 | 3114 | /* stride = Surface height in tiles */ |
832be82f | 3115 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3116 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3117 | x_offset = stride * tile_height - src_y - src_h; |
3118 | y_offset = src_x; | |
6156a456 | 3119 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3120 | } else { |
3121 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3122 | x_offset = src_x; |
3123 | y_offset = src_y; | |
6156a456 | 3124 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3125 | } |
3126 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3127 | |
2db3366b PZ |
3128 | intel_crtc->adjusted_x = x_offset; |
3129 | intel_crtc->adjusted_y = y_offset; | |
3130 | ||
70d21f0e | 3131 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3132 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3133 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3134 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3135 | |
3136 | if (scaler_id >= 0) { | |
3137 | uint32_t ps_ctrl = 0; | |
3138 | ||
3139 | WARN_ON(!dst_w || !dst_h); | |
3140 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3141 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3142 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3143 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3144 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3145 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3146 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3147 | } else { | |
3148 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3149 | } | |
3150 | ||
121920fa | 3151 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3152 | |
3153 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3154 | } | |
3155 | ||
a8d201af ML |
3156 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3157 | struct drm_crtc *crtc) | |
17638cd6 JB |
3158 | { |
3159 | struct drm_device *dev = crtc->dev; | |
3160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a8d201af | 3161 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3162 | |
a8d201af ML |
3163 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3164 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3165 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3166 | } | |
29b9bde6 | 3167 | |
a8d201af ML |
3168 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3169 | static int | |
3170 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3171 | int x, int y, enum mode_set_atomic state) | |
3172 | { | |
3173 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3174 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3175 | ||
3176 | return -ENODEV; | |
81255565 JB |
3177 | } |
3178 | ||
7514747d | 3179 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3180 | { |
96a02917 VS |
3181 | struct drm_crtc *crtc; |
3182 | ||
70e1e0ec | 3183 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3184 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3185 | enum plane plane = intel_crtc->plane; | |
3186 | ||
3187 | intel_prepare_page_flip(dev, plane); | |
3188 | intel_finish_page_flip_plane(dev, plane); | |
3189 | } | |
7514747d VS |
3190 | } |
3191 | ||
3192 | static void intel_update_primary_planes(struct drm_device *dev) | |
3193 | { | |
7514747d | 3194 | struct drm_crtc *crtc; |
96a02917 | 3195 | |
70e1e0ec | 3196 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3197 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3198 | struct intel_plane_state *plane_state; | |
96a02917 | 3199 | |
11c22da6 | 3200 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3201 | plane_state = to_intel_plane_state(plane->base.state); |
3202 | ||
a8d201af ML |
3203 | if (plane_state->visible) |
3204 | plane->update_plane(&plane->base, | |
3205 | to_intel_crtc_state(crtc->state), | |
3206 | plane_state); | |
11c22da6 ML |
3207 | |
3208 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3209 | } |
3210 | } | |
3211 | ||
7514747d VS |
3212 | void intel_prepare_reset(struct drm_device *dev) |
3213 | { | |
3214 | /* no reset support for gen2 */ | |
3215 | if (IS_GEN2(dev)) | |
3216 | return; | |
3217 | ||
3218 | /* reset doesn't touch the display */ | |
3219 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3220 | return; | |
3221 | ||
3222 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3223 | /* |
3224 | * Disabling the crtcs gracefully seems nicer. Also the | |
3225 | * g33 docs say we should at least disable all the planes. | |
3226 | */ | |
6b72d486 | 3227 | intel_display_suspend(dev); |
7514747d VS |
3228 | } |
3229 | ||
3230 | void intel_finish_reset(struct drm_device *dev) | |
3231 | { | |
3232 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3233 | ||
3234 | /* | |
3235 | * Flips in the rings will be nuked by the reset, | |
3236 | * so complete all pending flips so that user space | |
3237 | * will get its events and not get stuck. | |
3238 | */ | |
3239 | intel_complete_page_flips(dev); | |
3240 | ||
3241 | /* no reset support for gen2 */ | |
3242 | if (IS_GEN2(dev)) | |
3243 | return; | |
3244 | ||
3245 | /* reset doesn't touch the display */ | |
3246 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3247 | /* | |
3248 | * Flips in the rings have been nuked by the reset, | |
3249 | * so update the base address of all primary | |
3250 | * planes to the the last fb to make sure we're | |
3251 | * showing the correct fb after a reset. | |
11c22da6 ML |
3252 | * |
3253 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3254 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3255 | */ |
3256 | intel_update_primary_planes(dev); | |
3257 | return; | |
3258 | } | |
3259 | ||
3260 | /* | |
3261 | * The display has been reset as well, | |
3262 | * so need a full re-initialization. | |
3263 | */ | |
3264 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3265 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3266 | ||
3267 | intel_modeset_init_hw(dev); | |
3268 | ||
3269 | spin_lock_irq(&dev_priv->irq_lock); | |
3270 | if (dev_priv->display.hpd_irq_setup) | |
3271 | dev_priv->display.hpd_irq_setup(dev); | |
3272 | spin_unlock_irq(&dev_priv->irq_lock); | |
3273 | ||
043e9bda | 3274 | intel_display_resume(dev); |
7514747d VS |
3275 | |
3276 | intel_hpd_init(dev_priv); | |
3277 | ||
3278 | drm_modeset_unlock_all(dev); | |
3279 | } | |
3280 | ||
7d5e3799 CW |
3281 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3282 | { | |
3283 | struct drm_device *dev = crtc->dev; | |
3284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3285 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3286 | bool pending; |
3287 | ||
3288 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3289 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3290 | return false; | |
3291 | ||
5e2d7afc | 3292 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3293 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3294 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3295 | |
3296 | return pending; | |
3297 | } | |
3298 | ||
bfd16b2a ML |
3299 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3300 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3301 | { |
3302 | struct drm_device *dev = crtc->base.dev; | |
3303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3304 | struct intel_crtc_state *pipe_config = |
3305 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3306 | |
bfd16b2a ML |
3307 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3308 | crtc->base.mode = crtc->base.state->mode; | |
3309 | ||
3310 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3311 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3312 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3313 | |
44522d85 ML |
3314 | if (HAS_DDI(dev)) |
3315 | intel_set_pipe_csc(&crtc->base); | |
3316 | ||
e30e8f75 GP |
3317 | /* |
3318 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3319 | * that in compute_mode_changes we check the native mode (not the pfit | |
3320 | * mode) to see if we can flip rather than do a full mode set. In the | |
3321 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3322 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3323 | * sized surface. | |
e30e8f75 GP |
3324 | */ |
3325 | ||
e30e8f75 | 3326 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3327 | ((pipe_config->pipe_src_w - 1) << 16) | |
3328 | (pipe_config->pipe_src_h - 1)); | |
3329 | ||
3330 | /* on skylake this is done by detaching scalers */ | |
3331 | if (INTEL_INFO(dev)->gen >= 9) { | |
3332 | skl_detach_scalers(crtc); | |
3333 | ||
3334 | if (pipe_config->pch_pfit.enabled) | |
3335 | skylake_pfit_enable(crtc); | |
3336 | } else if (HAS_PCH_SPLIT(dev)) { | |
3337 | if (pipe_config->pch_pfit.enabled) | |
3338 | ironlake_pfit_enable(crtc); | |
3339 | else if (old_crtc_state->pch_pfit.enabled) | |
3340 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3341 | } |
e30e8f75 GP |
3342 | } |
3343 | ||
5e84e1a4 ZW |
3344 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3345 | { | |
3346 | struct drm_device *dev = crtc->dev; | |
3347 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3348 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3349 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3350 | i915_reg_t reg; |
3351 | u32 temp; | |
5e84e1a4 ZW |
3352 | |
3353 | /* enable normal train */ | |
3354 | reg = FDI_TX_CTL(pipe); | |
3355 | temp = I915_READ(reg); | |
61e499bf | 3356 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3357 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3358 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3359 | } else { |
3360 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3361 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3362 | } |
5e84e1a4 ZW |
3363 | I915_WRITE(reg, temp); |
3364 | ||
3365 | reg = FDI_RX_CTL(pipe); | |
3366 | temp = I915_READ(reg); | |
3367 | if (HAS_PCH_CPT(dev)) { | |
3368 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3369 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3370 | } else { | |
3371 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3372 | temp |= FDI_LINK_TRAIN_NONE; | |
3373 | } | |
3374 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3375 | ||
3376 | /* wait one idle pattern time */ | |
3377 | POSTING_READ(reg); | |
3378 | udelay(1000); | |
357555c0 JB |
3379 | |
3380 | /* IVB wants error correction enabled */ | |
3381 | if (IS_IVYBRIDGE(dev)) | |
3382 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3383 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3384 | } |
3385 | ||
8db9d77b ZW |
3386 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3387 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3388 | { | |
3389 | struct drm_device *dev = crtc->dev; | |
3390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3391 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3392 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3393 | i915_reg_t reg; |
3394 | u32 temp, tries; | |
8db9d77b | 3395 | |
1c8562f6 | 3396 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3397 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3398 | |
e1a44743 AJ |
3399 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3400 | for train result */ | |
5eddb70b CW |
3401 | reg = FDI_RX_IMR(pipe); |
3402 | temp = I915_READ(reg); | |
e1a44743 AJ |
3403 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3404 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3405 | I915_WRITE(reg, temp); |
3406 | I915_READ(reg); | |
e1a44743 AJ |
3407 | udelay(150); |
3408 | ||
8db9d77b | 3409 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3410 | reg = FDI_TX_CTL(pipe); |
3411 | temp = I915_READ(reg); | |
627eb5a3 | 3412 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3413 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3414 | temp &= ~FDI_LINK_TRAIN_NONE; |
3415 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3416 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3417 | |
5eddb70b CW |
3418 | reg = FDI_RX_CTL(pipe); |
3419 | temp = I915_READ(reg); | |
8db9d77b ZW |
3420 | temp &= ~FDI_LINK_TRAIN_NONE; |
3421 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3422 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3423 | ||
3424 | POSTING_READ(reg); | |
8db9d77b ZW |
3425 | udelay(150); |
3426 | ||
5b2adf89 | 3427 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3428 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3429 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3430 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3431 | |
5eddb70b | 3432 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3433 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3434 | temp = I915_READ(reg); |
8db9d77b ZW |
3435 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3436 | ||
3437 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3438 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3439 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3440 | break; |
3441 | } | |
8db9d77b | 3442 | } |
e1a44743 | 3443 | if (tries == 5) |
5eddb70b | 3444 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3445 | |
3446 | /* Train 2 */ | |
5eddb70b CW |
3447 | reg = FDI_TX_CTL(pipe); |
3448 | temp = I915_READ(reg); | |
8db9d77b ZW |
3449 | temp &= ~FDI_LINK_TRAIN_NONE; |
3450 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3451 | I915_WRITE(reg, temp); |
8db9d77b | 3452 | |
5eddb70b CW |
3453 | reg = FDI_RX_CTL(pipe); |
3454 | temp = I915_READ(reg); | |
8db9d77b ZW |
3455 | temp &= ~FDI_LINK_TRAIN_NONE; |
3456 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3457 | I915_WRITE(reg, temp); |
8db9d77b | 3458 | |
5eddb70b CW |
3459 | POSTING_READ(reg); |
3460 | udelay(150); | |
8db9d77b | 3461 | |
5eddb70b | 3462 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3463 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3464 | temp = I915_READ(reg); |
8db9d77b ZW |
3465 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3466 | ||
3467 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3468 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3469 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3470 | break; | |
3471 | } | |
8db9d77b | 3472 | } |
e1a44743 | 3473 | if (tries == 5) |
5eddb70b | 3474 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3475 | |
3476 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3477 | |
8db9d77b ZW |
3478 | } |
3479 | ||
0206e353 | 3480 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3481 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3482 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3483 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3484 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3485 | }; | |
3486 | ||
3487 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3488 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3489 | { | |
3490 | struct drm_device *dev = crtc->dev; | |
3491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3492 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3493 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3494 | i915_reg_t reg; |
3495 | u32 temp, i, retry; | |
8db9d77b | 3496 | |
e1a44743 AJ |
3497 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3498 | for train result */ | |
5eddb70b CW |
3499 | reg = FDI_RX_IMR(pipe); |
3500 | temp = I915_READ(reg); | |
e1a44743 AJ |
3501 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3502 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3503 | I915_WRITE(reg, temp); |
3504 | ||
3505 | POSTING_READ(reg); | |
e1a44743 AJ |
3506 | udelay(150); |
3507 | ||
8db9d77b | 3508 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3509 | reg = FDI_TX_CTL(pipe); |
3510 | temp = I915_READ(reg); | |
627eb5a3 | 3511 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3512 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3513 | temp &= ~FDI_LINK_TRAIN_NONE; |
3514 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3515 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3516 | /* SNB-B */ | |
3517 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3518 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3519 | |
d74cf324 DV |
3520 | I915_WRITE(FDI_RX_MISC(pipe), |
3521 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3522 | ||
5eddb70b CW |
3523 | reg = FDI_RX_CTL(pipe); |
3524 | temp = I915_READ(reg); | |
8db9d77b ZW |
3525 | if (HAS_PCH_CPT(dev)) { |
3526 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3527 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3528 | } else { | |
3529 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3530 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3531 | } | |
5eddb70b CW |
3532 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3533 | ||
3534 | POSTING_READ(reg); | |
8db9d77b ZW |
3535 | udelay(150); |
3536 | ||
0206e353 | 3537 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3538 | reg = FDI_TX_CTL(pipe); |
3539 | temp = I915_READ(reg); | |
8db9d77b ZW |
3540 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3541 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3542 | I915_WRITE(reg, temp); |
3543 | ||
3544 | POSTING_READ(reg); | |
8db9d77b ZW |
3545 | udelay(500); |
3546 | ||
fa37d39e SP |
3547 | for (retry = 0; retry < 5; retry++) { |
3548 | reg = FDI_RX_IIR(pipe); | |
3549 | temp = I915_READ(reg); | |
3550 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3551 | if (temp & FDI_RX_BIT_LOCK) { | |
3552 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3553 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3554 | break; | |
3555 | } | |
3556 | udelay(50); | |
8db9d77b | 3557 | } |
fa37d39e SP |
3558 | if (retry < 5) |
3559 | break; | |
8db9d77b ZW |
3560 | } |
3561 | if (i == 4) | |
5eddb70b | 3562 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3563 | |
3564 | /* Train 2 */ | |
5eddb70b CW |
3565 | reg = FDI_TX_CTL(pipe); |
3566 | temp = I915_READ(reg); | |
8db9d77b ZW |
3567 | temp &= ~FDI_LINK_TRAIN_NONE; |
3568 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3569 | if (IS_GEN6(dev)) { | |
3570 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3571 | /* SNB-B */ | |
3572 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3573 | } | |
5eddb70b | 3574 | I915_WRITE(reg, temp); |
8db9d77b | 3575 | |
5eddb70b CW |
3576 | reg = FDI_RX_CTL(pipe); |
3577 | temp = I915_READ(reg); | |
8db9d77b ZW |
3578 | if (HAS_PCH_CPT(dev)) { |
3579 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3580 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3581 | } else { | |
3582 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3583 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3584 | } | |
5eddb70b CW |
3585 | I915_WRITE(reg, temp); |
3586 | ||
3587 | POSTING_READ(reg); | |
8db9d77b ZW |
3588 | udelay(150); |
3589 | ||
0206e353 | 3590 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3591 | reg = FDI_TX_CTL(pipe); |
3592 | temp = I915_READ(reg); | |
8db9d77b ZW |
3593 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3594 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3595 | I915_WRITE(reg, temp); |
3596 | ||
3597 | POSTING_READ(reg); | |
8db9d77b ZW |
3598 | udelay(500); |
3599 | ||
fa37d39e SP |
3600 | for (retry = 0; retry < 5; retry++) { |
3601 | reg = FDI_RX_IIR(pipe); | |
3602 | temp = I915_READ(reg); | |
3603 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3604 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3605 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3606 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3607 | break; | |
3608 | } | |
3609 | udelay(50); | |
8db9d77b | 3610 | } |
fa37d39e SP |
3611 | if (retry < 5) |
3612 | break; | |
8db9d77b ZW |
3613 | } |
3614 | if (i == 4) | |
5eddb70b | 3615 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3616 | |
3617 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3618 | } | |
3619 | ||
357555c0 JB |
3620 | /* Manual link training for Ivy Bridge A0 parts */ |
3621 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3622 | { | |
3623 | struct drm_device *dev = crtc->dev; | |
3624 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3625 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3626 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3627 | i915_reg_t reg; |
3628 | u32 temp, i, j; | |
357555c0 JB |
3629 | |
3630 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3631 | for train result */ | |
3632 | reg = FDI_RX_IMR(pipe); | |
3633 | temp = I915_READ(reg); | |
3634 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3635 | temp &= ~FDI_RX_BIT_LOCK; | |
3636 | I915_WRITE(reg, temp); | |
3637 | ||
3638 | POSTING_READ(reg); | |
3639 | udelay(150); | |
3640 | ||
01a415fd DV |
3641 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3642 | I915_READ(FDI_RX_IIR(pipe))); | |
3643 | ||
139ccd3f JB |
3644 | /* Try each vswing and preemphasis setting twice before moving on */ |
3645 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3646 | /* disable first in case we need to retry */ | |
3647 | reg = FDI_TX_CTL(pipe); | |
3648 | temp = I915_READ(reg); | |
3649 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3650 | temp &= ~FDI_TX_ENABLE; | |
3651 | I915_WRITE(reg, temp); | |
357555c0 | 3652 | |
139ccd3f JB |
3653 | reg = FDI_RX_CTL(pipe); |
3654 | temp = I915_READ(reg); | |
3655 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3656 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3657 | temp &= ~FDI_RX_ENABLE; | |
3658 | I915_WRITE(reg, temp); | |
357555c0 | 3659 | |
139ccd3f | 3660 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3661 | reg = FDI_TX_CTL(pipe); |
3662 | temp = I915_READ(reg); | |
139ccd3f | 3663 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3664 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3665 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3666 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3667 | temp |= snb_b_fdi_train_param[j/2]; |
3668 | temp |= FDI_COMPOSITE_SYNC; | |
3669 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3670 | |
139ccd3f JB |
3671 | I915_WRITE(FDI_RX_MISC(pipe), |
3672 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3673 | |
139ccd3f | 3674 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3675 | temp = I915_READ(reg); |
139ccd3f JB |
3676 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3677 | temp |= FDI_COMPOSITE_SYNC; | |
3678 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3679 | |
139ccd3f JB |
3680 | POSTING_READ(reg); |
3681 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3682 | |
139ccd3f JB |
3683 | for (i = 0; i < 4; i++) { |
3684 | reg = FDI_RX_IIR(pipe); | |
3685 | temp = I915_READ(reg); | |
3686 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3687 | |
139ccd3f JB |
3688 | if (temp & FDI_RX_BIT_LOCK || |
3689 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3690 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3691 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3692 | i); | |
3693 | break; | |
3694 | } | |
3695 | udelay(1); /* should be 0.5us */ | |
3696 | } | |
3697 | if (i == 4) { | |
3698 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3699 | continue; | |
3700 | } | |
357555c0 | 3701 | |
139ccd3f | 3702 | /* Train 2 */ |
357555c0 JB |
3703 | reg = FDI_TX_CTL(pipe); |
3704 | temp = I915_READ(reg); | |
139ccd3f JB |
3705 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3706 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3707 | I915_WRITE(reg, temp); | |
3708 | ||
3709 | reg = FDI_RX_CTL(pipe); | |
3710 | temp = I915_READ(reg); | |
3711 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3712 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3713 | I915_WRITE(reg, temp); |
3714 | ||
3715 | POSTING_READ(reg); | |
139ccd3f | 3716 | udelay(2); /* should be 1.5us */ |
357555c0 | 3717 | |
139ccd3f JB |
3718 | for (i = 0; i < 4; i++) { |
3719 | reg = FDI_RX_IIR(pipe); | |
3720 | temp = I915_READ(reg); | |
3721 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3722 | |
139ccd3f JB |
3723 | if (temp & FDI_RX_SYMBOL_LOCK || |
3724 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3725 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3726 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3727 | i); | |
3728 | goto train_done; | |
3729 | } | |
3730 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3731 | } |
139ccd3f JB |
3732 | if (i == 4) |
3733 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3734 | } |
357555c0 | 3735 | |
139ccd3f | 3736 | train_done: |
357555c0 JB |
3737 | DRM_DEBUG_KMS("FDI train done.\n"); |
3738 | } | |
3739 | ||
88cefb6c | 3740 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3741 | { |
88cefb6c | 3742 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3743 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3744 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3745 | i915_reg_t reg; |
3746 | u32 temp; | |
c64e311e | 3747 | |
c98e9dcf | 3748 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3749 | reg = FDI_RX_CTL(pipe); |
3750 | temp = I915_READ(reg); | |
627eb5a3 | 3751 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3752 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3753 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3754 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3755 | ||
3756 | POSTING_READ(reg); | |
c98e9dcf JB |
3757 | udelay(200); |
3758 | ||
3759 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3760 | temp = I915_READ(reg); |
3761 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3762 | ||
3763 | POSTING_READ(reg); | |
c98e9dcf JB |
3764 | udelay(200); |
3765 | ||
20749730 PZ |
3766 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3767 | reg = FDI_TX_CTL(pipe); | |
3768 | temp = I915_READ(reg); | |
3769 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3770 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3771 | |
20749730 PZ |
3772 | POSTING_READ(reg); |
3773 | udelay(100); | |
6be4a607 | 3774 | } |
0e23b99d JB |
3775 | } |
3776 | ||
88cefb6c DV |
3777 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3778 | { | |
3779 | struct drm_device *dev = intel_crtc->base.dev; | |
3780 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3781 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3782 | i915_reg_t reg; |
3783 | u32 temp; | |
88cefb6c DV |
3784 | |
3785 | /* Switch from PCDclk to Rawclk */ | |
3786 | reg = FDI_RX_CTL(pipe); | |
3787 | temp = I915_READ(reg); | |
3788 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3789 | ||
3790 | /* Disable CPU FDI TX PLL */ | |
3791 | reg = FDI_TX_CTL(pipe); | |
3792 | temp = I915_READ(reg); | |
3793 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3794 | ||
3795 | POSTING_READ(reg); | |
3796 | udelay(100); | |
3797 | ||
3798 | reg = FDI_RX_CTL(pipe); | |
3799 | temp = I915_READ(reg); | |
3800 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3801 | ||
3802 | /* Wait for the clocks to turn off. */ | |
3803 | POSTING_READ(reg); | |
3804 | udelay(100); | |
3805 | } | |
3806 | ||
0fc932b8 JB |
3807 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3808 | { | |
3809 | struct drm_device *dev = crtc->dev; | |
3810 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3811 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3812 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3813 | i915_reg_t reg; |
3814 | u32 temp; | |
0fc932b8 JB |
3815 | |
3816 | /* disable CPU FDI tx and PCH FDI rx */ | |
3817 | reg = FDI_TX_CTL(pipe); | |
3818 | temp = I915_READ(reg); | |
3819 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3820 | POSTING_READ(reg); | |
3821 | ||
3822 | reg = FDI_RX_CTL(pipe); | |
3823 | temp = I915_READ(reg); | |
3824 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3825 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3826 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3827 | ||
3828 | POSTING_READ(reg); | |
3829 | udelay(100); | |
3830 | ||
3831 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3832 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3833 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3834 | |
3835 | /* still set train pattern 1 */ | |
3836 | reg = FDI_TX_CTL(pipe); | |
3837 | temp = I915_READ(reg); | |
3838 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3839 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3840 | I915_WRITE(reg, temp); | |
3841 | ||
3842 | reg = FDI_RX_CTL(pipe); | |
3843 | temp = I915_READ(reg); | |
3844 | if (HAS_PCH_CPT(dev)) { | |
3845 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3846 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3847 | } else { | |
3848 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3849 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3850 | } | |
3851 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3852 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3853 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3854 | I915_WRITE(reg, temp); |
3855 | ||
3856 | POSTING_READ(reg); | |
3857 | udelay(100); | |
3858 | } | |
3859 | ||
5dce5b93 CW |
3860 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3861 | { | |
3862 | struct intel_crtc *crtc; | |
3863 | ||
3864 | /* Note that we don't need to be called with mode_config.lock here | |
3865 | * as our list of CRTC objects is static for the lifetime of the | |
3866 | * device and so cannot disappear as we iterate. Similarly, we can | |
3867 | * happily treat the predicates as racy, atomic checks as userspace | |
3868 | * cannot claim and pin a new fb without at least acquring the | |
3869 | * struct_mutex and so serialising with us. | |
3870 | */ | |
d3fcc808 | 3871 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3872 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3873 | continue; | |
3874 | ||
3875 | if (crtc->unpin_work) | |
3876 | intel_wait_for_vblank(dev, crtc->pipe); | |
3877 | ||
3878 | return true; | |
3879 | } | |
3880 | ||
3881 | return false; | |
3882 | } | |
3883 | ||
d6bbafa1 CW |
3884 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3885 | { | |
3886 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3887 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3888 | ||
3889 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3890 | smp_rmb(); | |
3891 | intel_crtc->unpin_work = NULL; | |
3892 | ||
3893 | if (work->event) | |
3894 | drm_send_vblank_event(intel_crtc->base.dev, | |
3895 | intel_crtc->pipe, | |
3896 | work->event); | |
3897 | ||
3898 | drm_crtc_vblank_put(&intel_crtc->base); | |
3899 | ||
3900 | wake_up_all(&dev_priv->pending_flip_queue); | |
3901 | queue_work(dev_priv->wq, &work->work); | |
3902 | ||
3903 | trace_i915_flip_complete(intel_crtc->plane, | |
3904 | work->pending_flip_obj); | |
3905 | } | |
3906 | ||
5008e874 | 3907 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3908 | { |
0f91128d | 3909 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3910 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3911 | long ret; |
e6c3a2a6 | 3912 | |
2c10d571 | 3913 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3914 | |
3915 | ret = wait_event_interruptible_timeout( | |
3916 | dev_priv->pending_flip_queue, | |
3917 | !intel_crtc_has_pending_flip(crtc), | |
3918 | 60*HZ); | |
3919 | ||
3920 | if (ret < 0) | |
3921 | return ret; | |
3922 | ||
3923 | if (ret == 0) { | |
9c787942 | 3924 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3925 | |
5e2d7afc | 3926 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3927 | if (intel_crtc->unpin_work) { |
3928 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3929 | page_flip_completed(intel_crtc); | |
3930 | } | |
5e2d7afc | 3931 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3932 | } |
5bb61643 | 3933 | |
5008e874 | 3934 | return 0; |
e6c3a2a6 CW |
3935 | } |
3936 | ||
060f02d8 VS |
3937 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3938 | { | |
3939 | u32 temp; | |
3940 | ||
3941 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3942 | ||
3943 | mutex_lock(&dev_priv->sb_lock); | |
3944 | ||
3945 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3946 | temp |= SBI_SSCCTL_DISABLE; | |
3947 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3948 | ||
3949 | mutex_unlock(&dev_priv->sb_lock); | |
3950 | } | |
3951 | ||
e615efe4 ED |
3952 | /* Program iCLKIP clock to the desired frequency */ |
3953 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3954 | { | |
3955 | struct drm_device *dev = crtc->dev; | |
3956 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3957 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3958 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3959 | u32 temp; | |
3960 | ||
060f02d8 | 3961 | lpt_disable_iclkip(dev_priv); |
e615efe4 ED |
3962 | |
3963 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3964 | if (clock == 20000) { |
e615efe4 ED |
3965 | auxdiv = 1; |
3966 | divsel = 0x41; | |
3967 | phaseinc = 0x20; | |
3968 | } else { | |
3969 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3970 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3971 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3972 | * convert the virtual clock precision to KHz here for higher |
3973 | * precision. | |
3974 | */ | |
3975 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3976 | u32 iclk_pi_range = 64; | |
3977 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3978 | ||
a2572f5c | 3979 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock); |
e615efe4 ED |
3980 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3981 | pi_value = desired_divisor % iclk_pi_range; | |
3982 | ||
3983 | auxdiv = 0; | |
3984 | divsel = msb_divisor_value - 2; | |
3985 | phaseinc = pi_value; | |
3986 | } | |
3987 | ||
3988 | /* This should not happen with any sane values */ | |
3989 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3990 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3991 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3992 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3993 | ||
3994 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3995 | clock, |
e615efe4 ED |
3996 | auxdiv, |
3997 | divsel, | |
3998 | phasedir, | |
3999 | phaseinc); | |
4000 | ||
060f02d8 VS |
4001 | mutex_lock(&dev_priv->sb_lock); |
4002 | ||
e615efe4 | 4003 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4004 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4005 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4006 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4007 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4008 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4009 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4010 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4011 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4012 | |
4013 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4014 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4015 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4016 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4017 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4018 | |
4019 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4020 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4021 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4022 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4023 | |
060f02d8 VS |
4024 | mutex_unlock(&dev_priv->sb_lock); |
4025 | ||
e615efe4 ED |
4026 | /* Wait for initialization time */ |
4027 | udelay(24); | |
4028 | ||
4029 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4030 | } | |
4031 | ||
275f01b2 DV |
4032 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4033 | enum pipe pch_transcoder) | |
4034 | { | |
4035 | struct drm_device *dev = crtc->base.dev; | |
4036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4037 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4038 | |
4039 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4040 | I915_READ(HTOTAL(cpu_transcoder))); | |
4041 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4042 | I915_READ(HBLANK(cpu_transcoder))); | |
4043 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4044 | I915_READ(HSYNC(cpu_transcoder))); | |
4045 | ||
4046 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4047 | I915_READ(VTOTAL(cpu_transcoder))); | |
4048 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4049 | I915_READ(VBLANK(cpu_transcoder))); | |
4050 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4051 | I915_READ(VSYNC(cpu_transcoder))); | |
4052 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4053 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4054 | } | |
4055 | ||
003632d9 | 4056 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4057 | { |
4058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4059 | uint32_t temp; | |
4060 | ||
4061 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4062 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4063 | return; |
4064 | ||
4065 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4066 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4067 | ||
003632d9 ACO |
4068 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4069 | if (enable) | |
4070 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4071 | ||
4072 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4073 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4074 | POSTING_READ(SOUTH_CHICKEN1); | |
4075 | } | |
4076 | ||
4077 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4078 | { | |
4079 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4080 | |
4081 | switch (intel_crtc->pipe) { | |
4082 | case PIPE_A: | |
4083 | break; | |
4084 | case PIPE_B: | |
6e3c9717 | 4085 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4086 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4087 | else |
003632d9 | 4088 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4089 | |
4090 | break; | |
4091 | case PIPE_C: | |
003632d9 | 4092 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4093 | |
4094 | break; | |
4095 | default: | |
4096 | BUG(); | |
4097 | } | |
4098 | } | |
4099 | ||
c48b5305 VS |
4100 | /* Return which DP Port should be selected for Transcoder DP control */ |
4101 | static enum port | |
4102 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4103 | { | |
4104 | struct drm_device *dev = crtc->dev; | |
4105 | struct intel_encoder *encoder; | |
4106 | ||
4107 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4108 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4109 | encoder->type == INTEL_OUTPUT_EDP) | |
4110 | return enc_to_dig_port(&encoder->base)->port; | |
4111 | } | |
4112 | ||
4113 | return -1; | |
4114 | } | |
4115 | ||
f67a559d JB |
4116 | /* |
4117 | * Enable PCH resources required for PCH ports: | |
4118 | * - PCH PLLs | |
4119 | * - FDI training & RX/TX | |
4120 | * - update transcoder timings | |
4121 | * - DP transcoding bits | |
4122 | * - transcoder | |
4123 | */ | |
4124 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4125 | { |
4126 | struct drm_device *dev = crtc->dev; | |
4127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4128 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4129 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4130 | u32 temp; |
2c07245f | 4131 | |
ab9412ba | 4132 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4133 | |
1fbc0d78 DV |
4134 | if (IS_IVYBRIDGE(dev)) |
4135 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4136 | ||
cd986abb DV |
4137 | /* Write the TU size bits before fdi link training, so that error |
4138 | * detection works. */ | |
4139 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4140 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4141 | ||
3860b2ec VS |
4142 | /* |
4143 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4144 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4145 | */ | |
4146 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4147 | ||
c98e9dcf | 4148 | /* For PCH output, training FDI link */ |
674cf967 | 4149 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4150 | |
3ad8a208 DV |
4151 | /* We need to program the right clock selection before writing the pixel |
4152 | * mutliplier into the DPLL. */ | |
303b81e0 | 4153 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4154 | u32 sel; |
4b645f14 | 4155 | |
c98e9dcf | 4156 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4157 | temp |= TRANS_DPLL_ENABLE(pipe); |
4158 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4159 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4160 | temp |= sel; |
4161 | else | |
4162 | temp &= ~sel; | |
c98e9dcf | 4163 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4164 | } |
5eddb70b | 4165 | |
3ad8a208 DV |
4166 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4167 | * transcoder, and we actually should do this to not upset any PCH | |
4168 | * transcoder that already use the clock when we share it. | |
4169 | * | |
4170 | * Note that enable_shared_dpll tries to do the right thing, but | |
4171 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4172 | * the right LVDS enable sequence. */ | |
85b3894f | 4173 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4174 | |
d9b6cb56 JB |
4175 | /* set transcoder timing, panel must allow it */ |
4176 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4177 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4178 | |
303b81e0 | 4179 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4180 | |
3860b2ec VS |
4181 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4182 | ||
c98e9dcf | 4183 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4184 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4185 | const struct drm_display_mode *adjusted_mode = |
4186 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4187 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4188 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4189 | temp = I915_READ(reg); |
4190 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4191 | TRANS_DP_SYNC_MASK | |
4192 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4193 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4194 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4195 | |
9c4edaee | 4196 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4197 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4198 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4199 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4200 | |
4201 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4202 | case PORT_B: |
5eddb70b | 4203 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4204 | break; |
c48b5305 | 4205 | case PORT_C: |
5eddb70b | 4206 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4207 | break; |
c48b5305 | 4208 | case PORT_D: |
5eddb70b | 4209 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4210 | break; |
4211 | default: | |
e95d41e1 | 4212 | BUG(); |
32f9d658 | 4213 | } |
2c07245f | 4214 | |
5eddb70b | 4215 | I915_WRITE(reg, temp); |
6be4a607 | 4216 | } |
b52eb4dc | 4217 | |
b8a4f404 | 4218 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4219 | } |
4220 | ||
1507e5bd PZ |
4221 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4222 | { | |
4223 | struct drm_device *dev = crtc->dev; | |
4224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4225 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4226 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4227 | |
ab9412ba | 4228 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4229 | |
8c52b5e8 | 4230 | lpt_program_iclkip(crtc); |
1507e5bd | 4231 | |
0540e488 | 4232 | /* Set transcoder timing. */ |
275f01b2 | 4233 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4234 | |
937bb610 | 4235 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4236 | } |
4237 | ||
190f68c5 ACO |
4238 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4239 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4240 | { |
e2b78267 | 4241 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4242 | struct intel_shared_dpll *pll; |
de419ab6 | 4243 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4244 | enum intel_dpll_id i; |
00490c22 | 4245 | int max = dev_priv->num_shared_dpll; |
ee7b9f93 | 4246 | |
de419ab6 ML |
4247 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4248 | ||
98b6bd99 DV |
4249 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4250 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4251 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4252 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4253 | |
46edb027 DV |
4254 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4255 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4256 | |
de419ab6 | 4257 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4258 | |
98b6bd99 DV |
4259 | goto found; |
4260 | } | |
4261 | ||
bcddf610 S |
4262 | if (IS_BROXTON(dev_priv->dev)) { |
4263 | /* PLL is attached to port in bxt */ | |
4264 | struct intel_encoder *encoder; | |
4265 | struct intel_digital_port *intel_dig_port; | |
4266 | ||
4267 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4268 | if (WARN_ON(!encoder)) | |
4269 | return NULL; | |
4270 | ||
4271 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4272 | /* 1:1 mapping between ports and PLLs */ | |
4273 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4274 | pll = &dev_priv->shared_dplls[i]; | |
4275 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4276 | crtc->base.base.id, pll->name); | |
de419ab6 | 4277 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4278 | |
4279 | goto found; | |
00490c22 ML |
4280 | } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
4281 | /* Do not consider SPLL */ | |
4282 | max = 2; | |
bcddf610 | 4283 | |
00490c22 | 4284 | for (i = 0; i < max; i++) { |
e72f9fbf | 4285 | pll = &dev_priv->shared_dplls[i]; |
ee7b9f93 JB |
4286 | |
4287 | /* Only want to check enabled timings first */ | |
de419ab6 | 4288 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4289 | continue; |
4290 | ||
190f68c5 | 4291 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4292 | &shared_dpll[i].hw_state, |
4293 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4294 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4295 | crtc->base.base.id, pll->name, |
de419ab6 | 4296 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4297 | pll->active); |
ee7b9f93 JB |
4298 | goto found; |
4299 | } | |
4300 | } | |
4301 | ||
4302 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4303 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4304 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4305 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4306 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4307 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4308 | goto found; |
4309 | } | |
4310 | } | |
4311 | ||
4312 | return NULL; | |
4313 | ||
4314 | found: | |
de419ab6 ML |
4315 | if (shared_dpll[i].crtc_mask == 0) |
4316 | shared_dpll[i].hw_state = | |
4317 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4318 | |
190f68c5 | 4319 | crtc_state->shared_dpll = i; |
46edb027 DV |
4320 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4321 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4322 | |
de419ab6 | 4323 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4324 | |
ee7b9f93 JB |
4325 | return pll; |
4326 | } | |
4327 | ||
de419ab6 | 4328 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4329 | { |
de419ab6 ML |
4330 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4331 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4332 | struct intel_shared_dpll *pll; |
4333 | enum intel_dpll_id i; | |
4334 | ||
de419ab6 ML |
4335 | if (!to_intel_atomic_state(state)->dpll_set) |
4336 | return; | |
8bd31e67 | 4337 | |
de419ab6 | 4338 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4339 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4340 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4341 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4342 | } |
4343 | } | |
4344 | ||
a1520318 | 4345 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4346 | { |
4347 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4348 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4349 | u32 temp; |
4350 | ||
4351 | temp = I915_READ(dslreg); | |
4352 | udelay(500); | |
4353 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4354 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4355 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4356 | } |
4357 | } | |
4358 | ||
86adf9d7 ML |
4359 | static int |
4360 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4361 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4362 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4363 | { |
86adf9d7 ML |
4364 | struct intel_crtc_scaler_state *scaler_state = |
4365 | &crtc_state->scaler_state; | |
4366 | struct intel_crtc *intel_crtc = | |
4367 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4368 | int need_scaling; |
6156a456 CK |
4369 | |
4370 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4371 | (src_h != dst_w || src_w != dst_h): | |
4372 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4373 | |
4374 | /* | |
4375 | * if plane is being disabled or scaler is no more required or force detach | |
4376 | * - free scaler binded to this plane/crtc | |
4377 | * - in order to do this, update crtc->scaler_usage | |
4378 | * | |
4379 | * Here scaler state in crtc_state is set free so that | |
4380 | * scaler can be assigned to other user. Actual register | |
4381 | * update to free the scaler is done in plane/panel-fit programming. | |
4382 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4383 | */ | |
86adf9d7 | 4384 | if (force_detach || !need_scaling) { |
a1b2278e | 4385 | if (*scaler_id >= 0) { |
86adf9d7 | 4386 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4387 | scaler_state->scalers[*scaler_id].in_use = 0; |
4388 | ||
86adf9d7 ML |
4389 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4390 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4391 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4392 | scaler_state->scaler_users); |
4393 | *scaler_id = -1; | |
4394 | } | |
4395 | return 0; | |
4396 | } | |
4397 | ||
4398 | /* range checks */ | |
4399 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4400 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4401 | ||
4402 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4403 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4404 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4405 | "size is out of scaler range\n", |
86adf9d7 | 4406 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4407 | return -EINVAL; |
4408 | } | |
4409 | ||
86adf9d7 ML |
4410 | /* mark this plane as a scaler user in crtc_state */ |
4411 | scaler_state->scaler_users |= (1 << scaler_user); | |
4412 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4413 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4414 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4415 | scaler_state->scaler_users); | |
4416 | ||
4417 | return 0; | |
4418 | } | |
4419 | ||
4420 | /** | |
4421 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4422 | * | |
4423 | * @state: crtc's scaler state | |
86adf9d7 ML |
4424 | * |
4425 | * Return | |
4426 | * 0 - scaler_usage updated successfully | |
4427 | * error - requested scaling cannot be supported or other error condition | |
4428 | */ | |
e435d6e5 | 4429 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4430 | { |
4431 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4432 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4433 | |
4434 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4435 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4436 | ||
e435d6e5 | 4437 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4438 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4439 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4440 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4441 | } |
4442 | ||
4443 | /** | |
4444 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4445 | * | |
4446 | * @state: crtc's scaler state | |
86adf9d7 ML |
4447 | * @plane_state: atomic plane state to update |
4448 | * | |
4449 | * Return | |
4450 | * 0 - scaler_usage updated successfully | |
4451 | * error - requested scaling cannot be supported or other error condition | |
4452 | */ | |
da20eabd ML |
4453 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4454 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4455 | { |
4456 | ||
4457 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4458 | struct intel_plane *intel_plane = |
4459 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4460 | struct drm_framebuffer *fb = plane_state->base.fb; |
4461 | int ret; | |
4462 | ||
4463 | bool force_detach = !fb || !plane_state->visible; | |
4464 | ||
4465 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4466 | intel_plane->base.base.id, intel_crtc->pipe, | |
4467 | drm_plane_index(&intel_plane->base)); | |
4468 | ||
4469 | ret = skl_update_scaler(crtc_state, force_detach, | |
4470 | drm_plane_index(&intel_plane->base), | |
4471 | &plane_state->scaler_id, | |
4472 | plane_state->base.rotation, | |
4473 | drm_rect_width(&plane_state->src) >> 16, | |
4474 | drm_rect_height(&plane_state->src) >> 16, | |
4475 | drm_rect_width(&plane_state->dst), | |
4476 | drm_rect_height(&plane_state->dst)); | |
4477 | ||
4478 | if (ret || plane_state->scaler_id < 0) | |
4479 | return ret; | |
4480 | ||
a1b2278e | 4481 | /* check colorkey */ |
818ed961 | 4482 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4483 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4484 | intel_plane->base.base.id); |
a1b2278e CK |
4485 | return -EINVAL; |
4486 | } | |
4487 | ||
4488 | /* Check src format */ | |
86adf9d7 ML |
4489 | switch (fb->pixel_format) { |
4490 | case DRM_FORMAT_RGB565: | |
4491 | case DRM_FORMAT_XBGR8888: | |
4492 | case DRM_FORMAT_XRGB8888: | |
4493 | case DRM_FORMAT_ABGR8888: | |
4494 | case DRM_FORMAT_ARGB8888: | |
4495 | case DRM_FORMAT_XRGB2101010: | |
4496 | case DRM_FORMAT_XBGR2101010: | |
4497 | case DRM_FORMAT_YUYV: | |
4498 | case DRM_FORMAT_YVYU: | |
4499 | case DRM_FORMAT_UYVY: | |
4500 | case DRM_FORMAT_VYUY: | |
4501 | break; | |
4502 | default: | |
4503 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4504 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4505 | return -EINVAL; | |
a1b2278e CK |
4506 | } |
4507 | ||
a1b2278e CK |
4508 | return 0; |
4509 | } | |
4510 | ||
e435d6e5 ML |
4511 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4512 | { | |
4513 | int i; | |
4514 | ||
4515 | for (i = 0; i < crtc->num_scalers; i++) | |
4516 | skl_detach_scaler(crtc, i); | |
4517 | } | |
4518 | ||
4519 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4520 | { |
4521 | struct drm_device *dev = crtc->base.dev; | |
4522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4523 | int pipe = crtc->pipe; | |
a1b2278e CK |
4524 | struct intel_crtc_scaler_state *scaler_state = |
4525 | &crtc->config->scaler_state; | |
4526 | ||
4527 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4528 | ||
6e3c9717 | 4529 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4530 | int id; |
4531 | ||
4532 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4533 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4534 | return; | |
4535 | } | |
4536 | ||
4537 | id = scaler_state->scaler_id; | |
4538 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4539 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4540 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4541 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4542 | ||
4543 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4544 | } |
4545 | } | |
4546 | ||
b074cec8 JB |
4547 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4548 | { | |
4549 | struct drm_device *dev = crtc->base.dev; | |
4550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4551 | int pipe = crtc->pipe; | |
4552 | ||
6e3c9717 | 4553 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4554 | /* Force use of hard-coded filter coefficients |
4555 | * as some pre-programmed values are broken, | |
4556 | * e.g. x201. | |
4557 | */ | |
4558 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4559 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4560 | PF_PIPE_SEL_IVB(pipe)); | |
4561 | else | |
4562 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4563 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4564 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4565 | } |
4566 | } | |
4567 | ||
20bc8673 | 4568 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4569 | { |
cea165c3 VS |
4570 | struct drm_device *dev = crtc->base.dev; |
4571 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4572 | |
6e3c9717 | 4573 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4574 | return; |
4575 | ||
cea165c3 VS |
4576 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4577 | intel_wait_for_vblank(dev, crtc->pipe); | |
4578 | ||
d77e4531 | 4579 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4580 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4581 | mutex_lock(&dev_priv->rps.hw_lock); |
4582 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4583 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4584 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4585 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4586 | * mailbox." Moreover, the mailbox may return a bogus state, |
4587 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4588 | */ |
4589 | } else { | |
4590 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4591 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4592 | * is essentially intel_wait_for_vblank. If we don't have this | |
4593 | * and don't wait for vblanks until the end of crtc_enable, then | |
4594 | * the HW state readout code will complain that the expected | |
4595 | * IPS_CTL value is not the one we read. */ | |
4596 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4597 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4598 | } | |
d77e4531 PZ |
4599 | } |
4600 | ||
20bc8673 | 4601 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4602 | { |
4603 | struct drm_device *dev = crtc->base.dev; | |
4604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4605 | ||
6e3c9717 | 4606 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4607 | return; |
4608 | ||
4609 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4610 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4611 | mutex_lock(&dev_priv->rps.hw_lock); |
4612 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4613 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4614 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4615 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4616 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4617 | } else { |
2a114cc1 | 4618 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4619 | POSTING_READ(IPS_CTL); |
4620 | } | |
d77e4531 PZ |
4621 | |
4622 | /* We need to wait for a vblank before we can disable the plane. */ | |
4623 | intel_wait_for_vblank(dev, crtc->pipe); | |
4624 | } | |
4625 | ||
4626 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4627 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4628 | { | |
4629 | struct drm_device *dev = crtc->dev; | |
4630 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4631 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4632 | enum pipe pipe = intel_crtc->pipe; | |
d77e4531 PZ |
4633 | int i; |
4634 | bool reenable_ips = false; | |
4635 | ||
4636 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4637 | if (!crtc->state->active) |
d77e4531 PZ |
4638 | return; |
4639 | ||
50360403 | 4640 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
a65347ba | 4641 | if (intel_crtc->config->has_dsi_encoder) |
d77e4531 PZ |
4642 | assert_dsi_pll_enabled(dev_priv); |
4643 | else | |
4644 | assert_pll_enabled(dev_priv, pipe); | |
4645 | } | |
4646 | ||
d77e4531 PZ |
4647 | /* Workaround : Do not read or write the pipe palette/gamma data while |
4648 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4649 | */ | |
6e3c9717 | 4650 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4651 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4652 | GAMMA_MODE_MODE_SPLIT)) { | |
4653 | hsw_disable_ips(intel_crtc); | |
4654 | reenable_ips = true; | |
4655 | } | |
4656 | ||
4657 | for (i = 0; i < 256; i++) { | |
f0f59a00 | 4658 | i915_reg_t palreg; |
f65a9c5b VS |
4659 | |
4660 | if (HAS_GMCH_DISPLAY(dev)) | |
4661 | palreg = PALETTE(pipe, i); | |
4662 | else | |
4663 | palreg = LGC_PALETTE(pipe, i); | |
4664 | ||
4665 | I915_WRITE(palreg, | |
d77e4531 PZ |
4666 | (intel_crtc->lut_r[i] << 16) | |
4667 | (intel_crtc->lut_g[i] << 8) | | |
4668 | intel_crtc->lut_b[i]); | |
4669 | } | |
4670 | ||
4671 | if (reenable_ips) | |
4672 | hsw_enable_ips(intel_crtc); | |
4673 | } | |
4674 | ||
7cac945f | 4675 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4676 | { |
7cac945f | 4677 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4678 | struct drm_device *dev = intel_crtc->base.dev; |
4679 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4680 | ||
4681 | mutex_lock(&dev->struct_mutex); | |
4682 | dev_priv->mm.interruptible = false; | |
4683 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4684 | dev_priv->mm.interruptible = true; | |
4685 | mutex_unlock(&dev->struct_mutex); | |
4686 | } | |
4687 | ||
4688 | /* Let userspace switch the overlay on again. In most cases userspace | |
4689 | * has to recompute where to put it anyway. | |
4690 | */ | |
4691 | } | |
4692 | ||
87d4300a ML |
4693 | /** |
4694 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4695 | * @crtc: the CRTC whose primary plane was just enabled | |
4696 | * | |
4697 | * Performs potentially sleeping operations that must be done after the primary | |
4698 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4699 | * called due to an explicit primary plane update, or due to an implicit | |
4700 | * re-enable that is caused when a sprite plane is updated to no longer | |
4701 | * completely hide the primary plane. | |
4702 | */ | |
4703 | static void | |
4704 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4705 | { |
4706 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4707 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4708 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4709 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4710 | |
87d4300a ML |
4711 | /* |
4712 | * FIXME IPS should be fine as long as one plane is | |
4713 | * enabled, but in practice it seems to have problems | |
4714 | * when going from primary only to sprite only and vice | |
4715 | * versa. | |
4716 | */ | |
a5c4d7bc VS |
4717 | hsw_enable_ips(intel_crtc); |
4718 | ||
f99d7069 | 4719 | /* |
87d4300a ML |
4720 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4721 | * So don't enable underrun reporting before at least some planes | |
4722 | * are enabled. | |
4723 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4724 | * but leave the pipe running. | |
f99d7069 | 4725 | */ |
87d4300a ML |
4726 | if (IS_GEN2(dev)) |
4727 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4728 | ||
aca7b684 VS |
4729 | /* Underruns don't always raise interrupts, so check manually. */ |
4730 | intel_check_cpu_fifo_underruns(dev_priv); | |
4731 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4732 | } |
4733 | ||
87d4300a ML |
4734 | /** |
4735 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4736 | * @crtc: the CRTC whose primary plane is to be disabled | |
4737 | * | |
4738 | * Performs potentially sleeping operations that must be done before the | |
4739 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4740 | * be called due to an explicit primary plane update, or due to an implicit | |
4741 | * disable that is caused when a sprite plane completely hides the primary | |
4742 | * plane. | |
4743 | */ | |
4744 | static void | |
4745 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4746 | { |
4747 | struct drm_device *dev = crtc->dev; | |
4748 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4749 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4750 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4751 | |
87d4300a ML |
4752 | /* |
4753 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4754 | * So diasble underrun reporting before all the planes get disabled. | |
4755 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4756 | * but leave the pipe running. | |
4757 | */ | |
4758 | if (IS_GEN2(dev)) | |
4759 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4760 | |
87d4300a ML |
4761 | /* |
4762 | * Vblank time updates from the shadow to live plane control register | |
4763 | * are blocked if the memory self-refresh mode is active at that | |
4764 | * moment. So to make sure the plane gets truly disabled, disable | |
4765 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4766 | * will be checked/applied by the HW only at the next frame start | |
4767 | * event which is after the vblank start event, so we need to have a | |
4768 | * wait-for-vblank between disabling the plane and the pipe. | |
4769 | */ | |
262cd2e1 | 4770 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4771 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4772 | dev_priv->wm.vlv.cxsr = false; |
4773 | intel_wait_for_vblank(dev, pipe); | |
4774 | } | |
87d4300a | 4775 | |
87d4300a ML |
4776 | /* |
4777 | * FIXME IPS should be fine as long as one plane is | |
4778 | * enabled, but in practice it seems to have problems | |
4779 | * when going from primary only to sprite only and vice | |
4780 | * versa. | |
4781 | */ | |
a5c4d7bc | 4782 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4783 | } |
4784 | ||
ac21b225 ML |
4785 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4786 | { | |
4787 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
92826fcd ML |
4788 | struct intel_crtc_state *pipe_config = |
4789 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4790 | struct drm_device *dev = crtc->base.dev; |
ac21b225 ML |
4791 | |
4792 | if (atomic->wait_vblank) | |
4793 | intel_wait_for_vblank(dev, crtc->pipe); | |
4794 | ||
4795 | intel_frontbuffer_flip(dev, atomic->fb_bits); | |
4796 | ||
ab1d3a0e | 4797 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4798 | |
b9001114 | 4799 | if (pipe_config->wm_changed && pipe_config->base.active) |
f015c551 VS |
4800 | intel_update_watermarks(&crtc->base); |
4801 | ||
c80ac854 | 4802 | if (atomic->update_fbc) |
1eb52238 | 4803 | intel_fbc_post_update(crtc); |
ac21b225 ML |
4804 | |
4805 | if (atomic->post_enable_primary) | |
4806 | intel_post_enable_primary(&crtc->base); | |
4807 | ||
ac21b225 ML |
4808 | memset(atomic, 0, sizeof(*atomic)); |
4809 | } | |
4810 | ||
5c74cd73 | 4811 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4812 | { |
5c74cd73 | 4813 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4814 | struct drm_device *dev = crtc->base.dev; |
eddfcbcd | 4815 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 | 4816 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
ab1d3a0e ML |
4817 | struct intel_crtc_state *pipe_config = |
4818 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4819 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4820 | struct drm_plane *primary = crtc->base.primary; | |
4821 | struct drm_plane_state *old_pri_state = | |
4822 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4823 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4824 | |
1eb52238 PZ |
4825 | if (atomic->update_fbc) |
4826 | intel_fbc_pre_update(crtc); | |
ac21b225 | 4827 | |
5c74cd73 ML |
4828 | if (old_pri_state) { |
4829 | struct intel_plane_state *primary_state = | |
4830 | to_intel_plane_state(primary->state); | |
4831 | struct intel_plane_state *old_primary_state = | |
4832 | to_intel_plane_state(old_pri_state); | |
4833 | ||
4834 | if (old_primary_state->visible && | |
4835 | (modeset || !primary_state->visible)) | |
4836 | intel_pre_disable_primary(&crtc->base); | |
4837 | } | |
852eb00d | 4838 | |
ab1d3a0e | 4839 | if (pipe_config->disable_cxsr) { |
852eb00d | 4840 | crtc->wm.cxsr_allowed = false; |
2dfd178d ML |
4841 | |
4842 | if (old_crtc_state->base.active) | |
4843 | intel_set_memory_cxsr(dev_priv, false); | |
852eb00d | 4844 | } |
92826fcd | 4845 | |
bf220452 | 4846 | if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed) |
92826fcd | 4847 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4848 | } |
4849 | ||
d032ffa0 | 4850 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4851 | { |
4852 | struct drm_device *dev = crtc->dev; | |
4853 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4854 | struct drm_plane *p; |
87d4300a ML |
4855 | int pipe = intel_crtc->pipe; |
4856 | ||
7cac945f | 4857 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4858 | |
d032ffa0 ML |
4859 | drm_for_each_plane_mask(p, dev, plane_mask) |
4860 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4861 | |
f99d7069 DV |
4862 | /* |
4863 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4864 | * to compute the mask of flip planes precisely. For the time being | |
4865 | * consider this a flip to a NULL plane. | |
4866 | */ | |
4867 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4868 | } |
4869 | ||
f67a559d JB |
4870 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4871 | { | |
4872 | struct drm_device *dev = crtc->dev; | |
4873 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4874 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4875 | struct intel_encoder *encoder; |
f67a559d | 4876 | int pipe = intel_crtc->pipe; |
f67a559d | 4877 | |
53d9f4e9 | 4878 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4879 | return; |
4880 | ||
81b088ca VS |
4881 | if (intel_crtc->config->has_pch_encoder) |
4882 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4883 | ||
6e3c9717 | 4884 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4885 | intel_prepare_shared_dpll(intel_crtc); |
4886 | ||
6e3c9717 | 4887 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4888 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4889 | |
4890 | intel_set_pipe_timings(intel_crtc); | |
4891 | ||
6e3c9717 | 4892 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4893 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4894 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4895 | } |
4896 | ||
4897 | ironlake_set_pipeconf(crtc); | |
4898 | ||
f67a559d | 4899 | intel_crtc->active = true; |
8664281b | 4900 | |
a72e4c9f | 4901 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
8664281b | 4902 | |
f6736a1a | 4903 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4904 | if (encoder->pre_enable) |
4905 | encoder->pre_enable(encoder); | |
f67a559d | 4906 | |
6e3c9717 | 4907 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4908 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4909 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4910 | * enabling. */ | |
88cefb6c | 4911 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4912 | } else { |
4913 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4914 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4915 | } | |
f67a559d | 4916 | |
b074cec8 | 4917 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4918 | |
9c54c0dd JB |
4919 | /* |
4920 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4921 | * clocks enabled | |
4922 | */ | |
4923 | intel_crtc_load_lut(crtc); | |
4924 | ||
f37fcc2a | 4925 | intel_update_watermarks(crtc); |
e1fdc473 | 4926 | intel_enable_pipe(intel_crtc); |
f67a559d | 4927 | |
6e3c9717 | 4928 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4929 | ironlake_pch_enable(crtc); |
c98e9dcf | 4930 | |
f9b61ff6 DV |
4931 | assert_vblank_disabled(crtc); |
4932 | drm_crtc_vblank_on(crtc); | |
4933 | ||
fa5c73b1 DV |
4934 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4935 | encoder->enable(encoder); | |
61b77ddd DV |
4936 | |
4937 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4938 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4939 | |
4940 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4941 | if (intel_crtc->config->has_pch_encoder) | |
4942 | intel_wait_for_vblank(dev, pipe); | |
4943 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 JB |
4944 | } |
4945 | ||
42db64ef PZ |
4946 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4947 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4948 | { | |
f5adf94e | 4949 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4950 | } |
4951 | ||
4f771f10 PZ |
4952 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4953 | { | |
4954 | struct drm_device *dev = crtc->dev; | |
4955 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4956 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4957 | struct intel_encoder *encoder; | |
99d736a2 ML |
4958 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4959 | struct intel_crtc_state *pipe_config = | |
4960 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4961 | |
53d9f4e9 | 4962 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4963 | return; |
4964 | ||
81b088ca VS |
4965 | if (intel_crtc->config->has_pch_encoder) |
4966 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4967 | false); | |
4968 | ||
df8ad70c DV |
4969 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4970 | intel_enable_shared_dpll(intel_crtc); | |
4971 | ||
6e3c9717 | 4972 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4973 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4974 | |
4975 | intel_set_pipe_timings(intel_crtc); | |
4976 | ||
6e3c9717 ACO |
4977 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4978 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4979 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4980 | } |
4981 | ||
6e3c9717 | 4982 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4983 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4984 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4985 | } |
4986 | ||
4987 | haswell_set_pipeconf(crtc); | |
4988 | ||
4989 | intel_set_pipe_csc(crtc); | |
4990 | ||
4f771f10 | 4991 | intel_crtc->active = true; |
8664281b | 4992 | |
6b698516 DV |
4993 | if (intel_crtc->config->has_pch_encoder) |
4994 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4995 | else | |
4996 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4997 | ||
7d4aefd0 | 4998 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4999 | if (encoder->pre_enable) |
5000 | encoder->pre_enable(encoder); | |
7d4aefd0 | 5001 | } |
4f771f10 | 5002 | |
d2d65408 | 5003 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5004 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5005 | |
a65347ba | 5006 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5007 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5008 | |
1c132b44 | 5009 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5010 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5011 | else |
1c132b44 | 5012 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5013 | |
5014 | /* | |
5015 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5016 | * clocks enabled | |
5017 | */ | |
5018 | intel_crtc_load_lut(crtc); | |
5019 | ||
1f544388 | 5020 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 5021 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5022 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5023 | |
f37fcc2a | 5024 | intel_update_watermarks(crtc); |
e1fdc473 | 5025 | intel_enable_pipe(intel_crtc); |
42db64ef | 5026 | |
6e3c9717 | 5027 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5028 | lpt_pch_enable(crtc); |
4f771f10 | 5029 | |
a65347ba | 5030 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5031 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5032 | ||
f9b61ff6 DV |
5033 | assert_vblank_disabled(crtc); |
5034 | drm_crtc_vblank_on(crtc); | |
5035 | ||
8807e55b | 5036 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5037 | encoder->enable(encoder); |
8807e55b JN |
5038 | intel_opregion_notify_encoder(encoder, true); |
5039 | } | |
4f771f10 | 5040 | |
6b698516 DV |
5041 | if (intel_crtc->config->has_pch_encoder) { |
5042 | intel_wait_for_vblank(dev, pipe); | |
5043 | intel_wait_for_vblank(dev, pipe); | |
5044 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
5045 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5046 | true); | |
6b698516 | 5047 | } |
d2d65408 | 5048 | |
e4916946 PZ |
5049 | /* If we change the relative order between pipe/planes enabling, we need |
5050 | * to change the workaround. */ | |
99d736a2 ML |
5051 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5052 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5053 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5054 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5055 | } | |
4f771f10 PZ |
5056 | } |
5057 | ||
bfd16b2a | 5058 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5059 | { |
5060 | struct drm_device *dev = crtc->base.dev; | |
5061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5062 | int pipe = crtc->pipe; | |
5063 | ||
5064 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5065 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5066 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5067 | I915_WRITE(PF_CTL(pipe), 0); |
5068 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5069 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5070 | } | |
5071 | } | |
5072 | ||
6be4a607 JB |
5073 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5074 | { | |
5075 | struct drm_device *dev = crtc->dev; | |
5076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5077 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5078 | struct intel_encoder *encoder; |
6be4a607 | 5079 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5080 | |
37ca8d4c VS |
5081 | if (intel_crtc->config->has_pch_encoder) |
5082 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5083 | ||
ea9d758d DV |
5084 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5085 | encoder->disable(encoder); | |
5086 | ||
f9b61ff6 DV |
5087 | drm_crtc_vblank_off(crtc); |
5088 | assert_vblank_disabled(crtc); | |
5089 | ||
3860b2ec VS |
5090 | /* |
5091 | * Sometimes spurious CPU pipe underruns happen when the | |
5092 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5093 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5094 | */ | |
5095 | if (intel_crtc->config->has_pch_encoder) | |
5096 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5097 | ||
575f7ab7 | 5098 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5099 | |
bfd16b2a | 5100 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5101 | |
3860b2ec | 5102 | if (intel_crtc->config->has_pch_encoder) { |
5a74f70a | 5103 | ironlake_fdi_disable(crtc); |
3860b2ec VS |
5104 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5105 | } | |
5a74f70a | 5106 | |
bf49ec8c DV |
5107 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5108 | if (encoder->post_disable) | |
5109 | encoder->post_disable(encoder); | |
2c07245f | 5110 | |
6e3c9717 | 5111 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5112 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5113 | |
d925c59a | 5114 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5115 | i915_reg_t reg; |
5116 | u32 temp; | |
5117 | ||
d925c59a DV |
5118 | /* disable TRANS_DP_CTL */ |
5119 | reg = TRANS_DP_CTL(pipe); | |
5120 | temp = I915_READ(reg); | |
5121 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5122 | TRANS_DP_PORT_SEL_MASK); | |
5123 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5124 | I915_WRITE(reg, temp); | |
5125 | ||
5126 | /* disable DPLL_SEL */ | |
5127 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5128 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5129 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5130 | } |
e3421a18 | 5131 | |
d925c59a DV |
5132 | ironlake_fdi_pll_disable(intel_crtc); |
5133 | } | |
81b088ca VS |
5134 | |
5135 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 | 5136 | } |
1b3c7a47 | 5137 | |
4f771f10 | 5138 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5139 | { |
4f771f10 PZ |
5140 | struct drm_device *dev = crtc->dev; |
5141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5142 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5143 | struct intel_encoder *encoder; |
6e3c9717 | 5144 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5145 | |
d2d65408 VS |
5146 | if (intel_crtc->config->has_pch_encoder) |
5147 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5148 | false); | |
5149 | ||
8807e55b JN |
5150 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5151 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5152 | encoder->disable(encoder); |
8807e55b | 5153 | } |
4f771f10 | 5154 | |
f9b61ff6 DV |
5155 | drm_crtc_vblank_off(crtc); |
5156 | assert_vblank_disabled(crtc); | |
5157 | ||
575f7ab7 | 5158 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5159 | |
6e3c9717 | 5160 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5161 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5162 | ||
a65347ba | 5163 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5164 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5165 | |
1c132b44 | 5166 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5167 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5168 | else |
bfd16b2a | 5169 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5170 | |
a65347ba | 5171 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5172 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5173 | |
97b040aa ID |
5174 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5175 | if (encoder->post_disable) | |
5176 | encoder->post_disable(encoder); | |
81b088ca | 5177 | |
92966a37 VS |
5178 | if (intel_crtc->config->has_pch_encoder) { |
5179 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5180 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5181 | intel_ddi_fdi_disable(crtc); |
5182 | ||
81b088ca VS |
5183 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5184 | true); | |
92966a37 | 5185 | } |
4f771f10 PZ |
5186 | } |
5187 | ||
2dd24552 JB |
5188 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5189 | { | |
5190 | struct drm_device *dev = crtc->base.dev; | |
5191 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5192 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5193 | |
681a8504 | 5194 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5195 | return; |
5196 | ||
2dd24552 | 5197 | /* |
c0b03411 DV |
5198 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5199 | * according to register description and PRM. | |
2dd24552 | 5200 | */ |
c0b03411 DV |
5201 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5202 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5203 | |
b074cec8 JB |
5204 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5205 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5206 | |
5207 | /* Border color in case we don't scale up to the full screen. Black by | |
5208 | * default, change to something else for debugging. */ | |
5209 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5210 | } |
5211 | ||
d05410f9 DA |
5212 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5213 | { | |
5214 | switch (port) { | |
5215 | case PORT_A: | |
6331a704 | 5216 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5217 | case PORT_B: |
6331a704 | 5218 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5219 | case PORT_C: |
6331a704 | 5220 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5221 | case PORT_D: |
6331a704 | 5222 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5223 | case PORT_E: |
6331a704 | 5224 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5225 | default: |
b9fec167 | 5226 | MISSING_CASE(port); |
d05410f9 DA |
5227 | return POWER_DOMAIN_PORT_OTHER; |
5228 | } | |
5229 | } | |
5230 | ||
25f78f58 VS |
5231 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5232 | { | |
5233 | switch (port) { | |
5234 | case PORT_A: | |
5235 | return POWER_DOMAIN_AUX_A; | |
5236 | case PORT_B: | |
5237 | return POWER_DOMAIN_AUX_B; | |
5238 | case PORT_C: | |
5239 | return POWER_DOMAIN_AUX_C; | |
5240 | case PORT_D: | |
5241 | return POWER_DOMAIN_AUX_D; | |
5242 | case PORT_E: | |
5243 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5244 | return POWER_DOMAIN_AUX_D; | |
5245 | default: | |
b9fec167 | 5246 | MISSING_CASE(port); |
25f78f58 VS |
5247 | return POWER_DOMAIN_AUX_A; |
5248 | } | |
5249 | } | |
5250 | ||
319be8ae ID |
5251 | enum intel_display_power_domain |
5252 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5253 | { | |
5254 | struct drm_device *dev = intel_encoder->base.dev; | |
5255 | struct intel_digital_port *intel_dig_port; | |
5256 | ||
5257 | switch (intel_encoder->type) { | |
5258 | case INTEL_OUTPUT_UNKNOWN: | |
5259 | /* Only DDI platforms should ever use this output type */ | |
5260 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5261 | case INTEL_OUTPUT_DISPLAYPORT: | |
5262 | case INTEL_OUTPUT_HDMI: | |
5263 | case INTEL_OUTPUT_EDP: | |
5264 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5265 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5266 | case INTEL_OUTPUT_DP_MST: |
5267 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5268 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5269 | case INTEL_OUTPUT_ANALOG: |
5270 | return POWER_DOMAIN_PORT_CRT; | |
5271 | case INTEL_OUTPUT_DSI: | |
5272 | return POWER_DOMAIN_PORT_DSI; | |
5273 | default: | |
5274 | return POWER_DOMAIN_PORT_OTHER; | |
5275 | } | |
5276 | } | |
5277 | ||
25f78f58 VS |
5278 | enum intel_display_power_domain |
5279 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5280 | { | |
5281 | struct drm_device *dev = intel_encoder->base.dev; | |
5282 | struct intel_digital_port *intel_dig_port; | |
5283 | ||
5284 | switch (intel_encoder->type) { | |
5285 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5286 | case INTEL_OUTPUT_HDMI: |
5287 | /* | |
5288 | * Only DDI platforms should ever use these output types. | |
5289 | * We can get here after the HDMI detect code has already set | |
5290 | * the type of the shared encoder. Since we can't be sure | |
5291 | * what's the status of the given connectors, play safe and | |
5292 | * run the DP detection too. | |
5293 | */ | |
25f78f58 VS |
5294 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5295 | case INTEL_OUTPUT_DISPLAYPORT: | |
5296 | case INTEL_OUTPUT_EDP: | |
5297 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5298 | return port_to_aux_power_domain(intel_dig_port->port); | |
5299 | case INTEL_OUTPUT_DP_MST: | |
5300 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5301 | return port_to_aux_power_domain(intel_dig_port->port); | |
5302 | default: | |
b9fec167 | 5303 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5304 | return POWER_DOMAIN_AUX_A; |
5305 | } | |
5306 | } | |
5307 | ||
319be8ae | 5308 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5309 | { |
319be8ae ID |
5310 | struct drm_device *dev = crtc->dev; |
5311 | struct intel_encoder *intel_encoder; | |
5312 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5313 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5314 | unsigned long mask; |
1a70a728 | 5315 | enum transcoder transcoder = intel_crtc->config->cpu_transcoder; |
77d22dca | 5316 | |
292b990e ML |
5317 | if (!crtc->state->active) |
5318 | return 0; | |
5319 | ||
77d22dca ID |
5320 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5321 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5322 | if (intel_crtc->config->pch_pfit.enabled || |
5323 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5324 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5325 | ||
319be8ae ID |
5326 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5327 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5328 | ||
77d22dca ID |
5329 | return mask; |
5330 | } | |
5331 | ||
292b990e | 5332 | static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5333 | { |
292b990e ML |
5334 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5335 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5336 | enum intel_display_power_domain domain; | |
5337 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5338 | |
292b990e ML |
5339 | old_domains = intel_crtc->enabled_power_domains; |
5340 | intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); | |
77d22dca | 5341 | |
292b990e ML |
5342 | domains = new_domains & ~old_domains; |
5343 | ||
5344 | for_each_power_domain(domain, domains) | |
5345 | intel_display_power_get(dev_priv, domain); | |
5346 | ||
5347 | return old_domains & ~new_domains; | |
5348 | } | |
5349 | ||
5350 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5351 | unsigned long domains) | |
5352 | { | |
5353 | enum intel_display_power_domain domain; | |
5354 | ||
5355 | for_each_power_domain(domain, domains) | |
5356 | intel_display_power_put(dev_priv, domain); | |
5357 | } | |
77d22dca | 5358 | |
292b990e ML |
5359 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
5360 | { | |
1a617b77 | 5361 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
292b990e ML |
5362 | struct drm_device *dev = state->dev; |
5363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5364 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
5365 | struct drm_crtc_state *crtc_state; | |
5366 | struct drm_crtc *crtc; | |
5367 | int i; | |
77d22dca | 5368 | |
292b990e ML |
5369 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5370 | if (needs_modeset(crtc->state)) | |
5371 | put_domains[to_intel_crtc(crtc)->pipe] = | |
5372 | modeset_get_crtc_power_domains(crtc); | |
77d22dca ID |
5373 | } |
5374 | ||
1a617b77 ML |
5375 | if (dev_priv->display.modeset_commit_cdclk && |
5376 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
5377 | dev_priv->display.modeset_commit_cdclk(state); | |
50f6e502 | 5378 | |
292b990e ML |
5379 | for (i = 0; i < I915_MAX_PIPES; i++) |
5380 | if (put_domains[i]) | |
5381 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
77d22dca ID |
5382 | } |
5383 | ||
adafdc6f MK |
5384 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5385 | { | |
5386 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5387 | ||
5388 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5389 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5390 | return max_cdclk_freq; | |
5391 | else if (IS_CHERRYVIEW(dev_priv)) | |
5392 | return max_cdclk_freq*95/100; | |
5393 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5394 | return 2*max_cdclk_freq*90/100; | |
5395 | else | |
5396 | return max_cdclk_freq*90/100; | |
5397 | } | |
5398 | ||
560a7ae4 DL |
5399 | static void intel_update_max_cdclk(struct drm_device *dev) |
5400 | { | |
5401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5402 | ||
ef11bdb3 | 5403 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5404 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5405 | ||
5406 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5407 | dev_priv->max_cdclk_freq = 675000; | |
5408 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5409 | dev_priv->max_cdclk_freq = 540000; | |
5410 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5411 | dev_priv->max_cdclk_freq = 450000; | |
5412 | else | |
5413 | dev_priv->max_cdclk_freq = 337500; | |
5414 | } else if (IS_BROADWELL(dev)) { | |
5415 | /* | |
5416 | * FIXME with extra cooling we can allow | |
5417 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5418 | * How can we know if extra cooling is | |
5419 | * available? PCI ID, VTB, something else? | |
5420 | */ | |
5421 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5422 | dev_priv->max_cdclk_freq = 450000; | |
5423 | else if (IS_BDW_ULX(dev)) | |
5424 | dev_priv->max_cdclk_freq = 450000; | |
5425 | else if (IS_BDW_ULT(dev)) | |
5426 | dev_priv->max_cdclk_freq = 540000; | |
5427 | else | |
5428 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5429 | } else if (IS_CHERRYVIEW(dev)) { |
5430 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5431 | } else if (IS_VALLEYVIEW(dev)) { |
5432 | dev_priv->max_cdclk_freq = 400000; | |
5433 | } else { | |
5434 | /* otherwise assume cdclk is fixed */ | |
5435 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5436 | } | |
5437 | ||
adafdc6f MK |
5438 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5439 | ||
560a7ae4 DL |
5440 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5441 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5442 | |
5443 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5444 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5445 | } |
5446 | ||
5447 | static void intel_update_cdclk(struct drm_device *dev) | |
5448 | { | |
5449 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5450 | ||
5451 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5452 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5453 | dev_priv->cdclk_freq); | |
5454 | ||
5455 | /* | |
5456 | * Program the gmbus_freq based on the cdclk frequency. | |
5457 | * BSpec erroneously claims we should aim for 4MHz, but | |
5458 | * in fact 1MHz is the correct frequency. | |
5459 | */ | |
666a4537 | 5460 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
560a7ae4 DL |
5461 | /* |
5462 | * Program the gmbus_freq based on the cdclk frequency. | |
5463 | * BSpec erroneously claims we should aim for 4MHz, but | |
5464 | * in fact 1MHz is the correct frequency. | |
5465 | */ | |
5466 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5467 | } | |
5468 | ||
5469 | if (dev_priv->max_cdclk_freq == 0) | |
5470 | intel_update_max_cdclk(dev); | |
5471 | } | |
5472 | ||
70d0c574 | 5473 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5474 | { |
5475 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5476 | uint32_t divider; | |
5477 | uint32_t ratio; | |
5478 | uint32_t current_freq; | |
5479 | int ret; | |
5480 | ||
5481 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5482 | switch (frequency) { | |
5483 | case 144000: | |
5484 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5485 | ratio = BXT_DE_PLL_RATIO(60); | |
5486 | break; | |
5487 | case 288000: | |
5488 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5489 | ratio = BXT_DE_PLL_RATIO(60); | |
5490 | break; | |
5491 | case 384000: | |
5492 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5493 | ratio = BXT_DE_PLL_RATIO(60); | |
5494 | break; | |
5495 | case 576000: | |
5496 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5497 | ratio = BXT_DE_PLL_RATIO(60); | |
5498 | break; | |
5499 | case 624000: | |
5500 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5501 | ratio = BXT_DE_PLL_RATIO(65); | |
5502 | break; | |
5503 | case 19200: | |
5504 | /* | |
5505 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5506 | * to suppress GCC warning. | |
5507 | */ | |
5508 | ratio = 0; | |
5509 | divider = 0; | |
5510 | break; | |
5511 | default: | |
5512 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5513 | ||
5514 | return; | |
5515 | } | |
5516 | ||
5517 | mutex_lock(&dev_priv->rps.hw_lock); | |
5518 | /* Inform power controller of upcoming frequency change */ | |
5519 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5520 | 0x80000000); | |
5521 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5522 | ||
5523 | if (ret) { | |
5524 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5525 | ret, frequency); | |
5526 | return; | |
5527 | } | |
5528 | ||
5529 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5530 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5531 | current_freq = current_freq * 500 + 1000; | |
5532 | ||
5533 | /* | |
5534 | * DE PLL has to be disabled when | |
5535 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5536 | * - before setting to 624MHz (PLL needs toggling) | |
5537 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5538 | */ | |
5539 | if (frequency == 19200 || frequency == 624000 || | |
5540 | current_freq == 624000) { | |
5541 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5542 | /* Timeout 200us */ | |
5543 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5544 | 1)) | |
5545 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5546 | } | |
5547 | ||
5548 | if (frequency != 19200) { | |
5549 | uint32_t val; | |
5550 | ||
5551 | val = I915_READ(BXT_DE_PLL_CTL); | |
5552 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5553 | val |= ratio; | |
5554 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5555 | ||
5556 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5557 | /* Timeout 200us */ | |
5558 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5559 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5560 | ||
5561 | val = I915_READ(CDCLK_CTL); | |
5562 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5563 | val |= divider; | |
5564 | /* | |
5565 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5566 | * enable otherwise. | |
5567 | */ | |
5568 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5569 | if (frequency >= 500000) | |
5570 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5571 | ||
5572 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5573 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5574 | val |= (frequency - 1000) / 500; | |
5575 | I915_WRITE(CDCLK_CTL, val); | |
5576 | } | |
5577 | ||
5578 | mutex_lock(&dev_priv->rps.hw_lock); | |
5579 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5580 | DIV_ROUND_UP(frequency, 25000)); | |
5581 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5582 | ||
5583 | if (ret) { | |
5584 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5585 | ret, frequency); | |
5586 | return; | |
5587 | } | |
5588 | ||
a47871bd | 5589 | intel_update_cdclk(dev); |
f8437dd1 VK |
5590 | } |
5591 | ||
5592 | void broxton_init_cdclk(struct drm_device *dev) | |
5593 | { | |
5594 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5595 | uint32_t val; | |
5596 | ||
5597 | /* | |
5598 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5599 | * or else the reset will hang because there is no PCH to respond. | |
5600 | * Move the handshake programming to initialization sequence. | |
5601 | * Previously was left up to BIOS. | |
5602 | */ | |
5603 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5604 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5605 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5606 | ||
5607 | /* Enable PG1 for cdclk */ | |
5608 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5609 | ||
5610 | /* check if cd clock is enabled */ | |
5611 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5612 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5613 | return; | |
5614 | } | |
5615 | ||
5616 | /* | |
5617 | * FIXME: | |
5618 | * - The initial CDCLK needs to be read from VBT. | |
5619 | * Need to make this change after VBT has changes for BXT. | |
5620 | * - check if setting the max (or any) cdclk freq is really necessary | |
5621 | * here, it belongs to modeset time | |
5622 | */ | |
5623 | broxton_set_cdclk(dev, 624000); | |
5624 | ||
5625 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5626 | POSTING_READ(DBUF_CTL); |
5627 | ||
f8437dd1 VK |
5628 | udelay(10); |
5629 | ||
5630 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5631 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5632 | } | |
5633 | ||
5634 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5635 | { | |
5636 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5637 | ||
5638 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5639 | POSTING_READ(DBUF_CTL); |
5640 | ||
f8437dd1 VK |
5641 | udelay(10); |
5642 | ||
5643 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5644 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5645 | ||
5646 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5647 | broxton_set_cdclk(dev, 19200); | |
5648 | ||
5649 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5650 | } | |
5651 | ||
5d96d8af DL |
5652 | static const struct skl_cdclk_entry { |
5653 | unsigned int freq; | |
5654 | unsigned int vco; | |
5655 | } skl_cdclk_frequencies[] = { | |
5656 | { .freq = 308570, .vco = 8640 }, | |
5657 | { .freq = 337500, .vco = 8100 }, | |
5658 | { .freq = 432000, .vco = 8640 }, | |
5659 | { .freq = 450000, .vco = 8100 }, | |
5660 | { .freq = 540000, .vco = 8100 }, | |
5661 | { .freq = 617140, .vco = 8640 }, | |
5662 | { .freq = 675000, .vco = 8100 }, | |
5663 | }; | |
5664 | ||
5665 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5666 | { | |
5667 | return (freq - 1000) / 500; | |
5668 | } | |
5669 | ||
5670 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5671 | { | |
5672 | unsigned int i; | |
5673 | ||
5674 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5675 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5676 | ||
5677 | if (e->freq == freq) | |
5678 | return e->vco; | |
5679 | } | |
5680 | ||
5681 | return 8100; | |
5682 | } | |
5683 | ||
5684 | static void | |
5685 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5686 | { | |
5687 | unsigned int min_freq; | |
5688 | u32 val; | |
5689 | ||
5690 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5691 | val = I915_READ(CDCLK_CTL); | |
5692 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5693 | val |= CDCLK_FREQ_337_308; | |
5694 | ||
5695 | if (required_vco == 8640) | |
5696 | min_freq = 308570; | |
5697 | else | |
5698 | min_freq = 337500; | |
5699 | ||
5700 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5701 | ||
5702 | I915_WRITE(CDCLK_CTL, val); | |
5703 | POSTING_READ(CDCLK_CTL); | |
5704 | ||
5705 | /* | |
5706 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5707 | * taking into account the VCO required to operate the eDP panel at the | |
5708 | * desired frequency. The usual DP link rates operate with a VCO of | |
5709 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5710 | * The modeset code is responsible for the selection of the exact link | |
5711 | * rate later on, with the constraint of choosing a frequency that | |
5712 | * works with required_vco. | |
5713 | */ | |
5714 | val = I915_READ(DPLL_CTRL1); | |
5715 | ||
5716 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5717 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5718 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5719 | if (required_vco == 8640) | |
5720 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5721 | SKL_DPLL0); | |
5722 | else | |
5723 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5724 | SKL_DPLL0); | |
5725 | ||
5726 | I915_WRITE(DPLL_CTRL1, val); | |
5727 | POSTING_READ(DPLL_CTRL1); | |
5728 | ||
5729 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5730 | ||
5731 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5732 | DRM_ERROR("DPLL0 not locked\n"); | |
5733 | } | |
5734 | ||
5735 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5736 | { | |
5737 | int ret; | |
5738 | u32 val; | |
5739 | ||
5740 | /* inform PCU we want to change CDCLK */ | |
5741 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5742 | mutex_lock(&dev_priv->rps.hw_lock); | |
5743 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5744 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5745 | ||
5746 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5747 | } | |
5748 | ||
5749 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5750 | { | |
5751 | unsigned int i; | |
5752 | ||
5753 | for (i = 0; i < 15; i++) { | |
5754 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5755 | return true; | |
5756 | udelay(10); | |
5757 | } | |
5758 | ||
5759 | return false; | |
5760 | } | |
5761 | ||
5762 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5763 | { | |
560a7ae4 | 5764 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5765 | u32 freq_select, pcu_ack; |
5766 | ||
5767 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5768 | ||
5769 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5770 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5771 | return; | |
5772 | } | |
5773 | ||
5774 | /* set CDCLK_CTL */ | |
5775 | switch(freq) { | |
5776 | case 450000: | |
5777 | case 432000: | |
5778 | freq_select = CDCLK_FREQ_450_432; | |
5779 | pcu_ack = 1; | |
5780 | break; | |
5781 | case 540000: | |
5782 | freq_select = CDCLK_FREQ_540; | |
5783 | pcu_ack = 2; | |
5784 | break; | |
5785 | case 308570: | |
5786 | case 337500: | |
5787 | default: | |
5788 | freq_select = CDCLK_FREQ_337_308; | |
5789 | pcu_ack = 0; | |
5790 | break; | |
5791 | case 617140: | |
5792 | case 675000: | |
5793 | freq_select = CDCLK_FREQ_675_617; | |
5794 | pcu_ack = 3; | |
5795 | break; | |
5796 | } | |
5797 | ||
5798 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5799 | POSTING_READ(CDCLK_CTL); | |
5800 | ||
5801 | /* inform PCU of the change */ | |
5802 | mutex_lock(&dev_priv->rps.hw_lock); | |
5803 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5804 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5805 | |
5806 | intel_update_cdclk(dev); | |
5d96d8af DL |
5807 | } |
5808 | ||
5809 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5810 | { | |
5811 | /* disable DBUF power */ | |
5812 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5813 | POSTING_READ(DBUF_CTL); | |
5814 | ||
5815 | udelay(10); | |
5816 | ||
5817 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5818 | DRM_ERROR("DBuf power disable timeout\n"); | |
5819 | ||
ab96c1ee ID |
5820 | /* disable DPLL0 */ |
5821 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5822 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5823 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5824 | } |
5825 | ||
5826 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5827 | { | |
5d96d8af DL |
5828 | unsigned int required_vco; |
5829 | ||
39d9b85a GW |
5830 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5831 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5832 | /* enable DPLL0 */ | |
5833 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5834 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5835 | } |
5836 | ||
5d96d8af DL |
5837 | /* set CDCLK to the frequency the BIOS chose */ |
5838 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5839 | ||
5840 | /* enable DBUF power */ | |
5841 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5842 | POSTING_READ(DBUF_CTL); | |
5843 | ||
5844 | udelay(10); | |
5845 | ||
5846 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5847 | DRM_ERROR("DBuf power enable timeout\n"); | |
5848 | } | |
5849 | ||
c73666f3 SK |
5850 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5851 | { | |
5852 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5853 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5854 | int freq = dev_priv->skl_boot_cdclk; | |
5855 | ||
f1b391a5 SK |
5856 | /* |
5857 | * check if the pre-os intialized the display | |
5858 | * There is SWF18 scratchpad register defined which is set by the | |
5859 | * pre-os which can be used by the OS drivers to check the status | |
5860 | */ | |
5861 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5862 | goto sanitize; | |
5863 | ||
c73666f3 SK |
5864 | /* Is PLL enabled and locked ? */ |
5865 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5866 | goto sanitize; | |
5867 | ||
5868 | /* DPLL okay; verify the cdclock | |
5869 | * | |
5870 | * Noticed in some instances that the freq selection is correct but | |
5871 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5872 | * enable display. Verify the same as well. | |
5873 | */ | |
5874 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5875 | /* All well; nothing to sanitize */ | |
5876 | return false; | |
5877 | sanitize: | |
5878 | /* | |
5879 | * As of now initialize with max cdclk till | |
5880 | * we get dynamic cdclk support | |
5881 | * */ | |
5882 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5883 | skl_init_cdclk(dev_priv); | |
5884 | ||
5885 | /* we did have to sanitize */ | |
5886 | return true; | |
5887 | } | |
5888 | ||
30a970c6 JB |
5889 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5890 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5891 | { | |
5892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5893 | u32 val, cmd; | |
5894 | ||
164dfd28 VK |
5895 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5896 | != dev_priv->cdclk_freq); | |
d60c4473 | 5897 | |
dfcab17e | 5898 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5899 | cmd = 2; |
dfcab17e | 5900 | else if (cdclk == 266667) |
30a970c6 JB |
5901 | cmd = 1; |
5902 | else | |
5903 | cmd = 0; | |
5904 | ||
5905 | mutex_lock(&dev_priv->rps.hw_lock); | |
5906 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5907 | val &= ~DSPFREQGUAR_MASK; | |
5908 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5909 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5910 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5911 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5912 | 50)) { | |
5913 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5914 | } | |
5915 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5916 | ||
54433e91 VS |
5917 | mutex_lock(&dev_priv->sb_lock); |
5918 | ||
dfcab17e | 5919 | if (cdclk == 400000) { |
6bcda4f0 | 5920 | u32 divider; |
30a970c6 | 5921 | |
6bcda4f0 | 5922 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5923 | |
30a970c6 JB |
5924 | /* adjust cdclk divider */ |
5925 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5926 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5927 | val |= divider; |
5928 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5929 | |
5930 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5931 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5932 | 50)) |
5933 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5934 | } |
5935 | ||
30a970c6 JB |
5936 | /* adjust self-refresh exit latency value */ |
5937 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5938 | val &= ~0x7f; | |
5939 | ||
5940 | /* | |
5941 | * For high bandwidth configs, we set a higher latency in the bunit | |
5942 | * so that the core display fetch happens in time to avoid underruns. | |
5943 | */ | |
dfcab17e | 5944 | if (cdclk == 400000) |
30a970c6 JB |
5945 | val |= 4500 / 250; /* 4.5 usec */ |
5946 | else | |
5947 | val |= 3000 / 250; /* 3.0 usec */ | |
5948 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5949 | |
a580516d | 5950 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5951 | |
b6283055 | 5952 | intel_update_cdclk(dev); |
30a970c6 JB |
5953 | } |
5954 | ||
383c5a6a VS |
5955 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5956 | { | |
5957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5958 | u32 val, cmd; | |
5959 | ||
164dfd28 VK |
5960 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5961 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5962 | |
5963 | switch (cdclk) { | |
383c5a6a VS |
5964 | case 333333: |
5965 | case 320000: | |
383c5a6a | 5966 | case 266667: |
383c5a6a | 5967 | case 200000: |
383c5a6a VS |
5968 | break; |
5969 | default: | |
5f77eeb0 | 5970 | MISSING_CASE(cdclk); |
383c5a6a VS |
5971 | return; |
5972 | } | |
5973 | ||
9d0d3fda VS |
5974 | /* |
5975 | * Specs are full of misinformation, but testing on actual | |
5976 | * hardware has shown that we just need to write the desired | |
5977 | * CCK divider into the Punit register. | |
5978 | */ | |
5979 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5980 | ||
383c5a6a VS |
5981 | mutex_lock(&dev_priv->rps.hw_lock); |
5982 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5983 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5984 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5985 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5986 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5987 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5988 | 50)) { | |
5989 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5990 | } | |
5991 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5992 | ||
b6283055 | 5993 | intel_update_cdclk(dev); |
383c5a6a VS |
5994 | } |
5995 | ||
30a970c6 JB |
5996 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5997 | int max_pixclk) | |
5998 | { | |
6bcda4f0 | 5999 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6000 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6001 | |
30a970c6 JB |
6002 | /* |
6003 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6004 | * 200MHz | |
6005 | * 267MHz | |
29dc7ef3 | 6006 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6007 | * 400MHz (VLV only) |
6008 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6009 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6010 | * |
6011 | * We seem to get an unstable or solid color picture at 200MHz. | |
6012 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6013 | * are off. | |
30a970c6 | 6014 | */ |
6cca3195 VS |
6015 | if (!IS_CHERRYVIEW(dev_priv) && |
6016 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6017 | return 400000; |
6cca3195 | 6018 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6019 | return freq_320; |
e37c67a1 | 6020 | else if (max_pixclk > 0) |
dfcab17e | 6021 | return 266667; |
e37c67a1 VS |
6022 | else |
6023 | return 200000; | |
30a970c6 JB |
6024 | } |
6025 | ||
f8437dd1 VK |
6026 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
6027 | int max_pixclk) | |
6028 | { | |
6029 | /* | |
6030 | * FIXME: | |
6031 | * - remove the guardband, it's not needed on BXT | |
6032 | * - set 19.2MHz bypass frequency if there are no active pipes | |
6033 | */ | |
6034 | if (max_pixclk > 576000*9/10) | |
6035 | return 624000; | |
6036 | else if (max_pixclk > 384000*9/10) | |
6037 | return 576000; | |
6038 | else if (max_pixclk > 288000*9/10) | |
6039 | return 384000; | |
6040 | else if (max_pixclk > 144000*9/10) | |
6041 | return 288000; | |
6042 | else | |
6043 | return 144000; | |
6044 | } | |
6045 | ||
e8788cbc | 6046 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
6047 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6048 | struct drm_atomic_state *state) | |
30a970c6 | 6049 | { |
565602d7 ML |
6050 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
6051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6052 | struct drm_crtc *crtc; | |
6053 | struct drm_crtc_state *crtc_state; | |
6054 | unsigned max_pixclk = 0, i; | |
6055 | enum pipe pipe; | |
30a970c6 | 6056 | |
565602d7 ML |
6057 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6058 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6059 | |
565602d7 ML |
6060 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6061 | int pixclk = 0; | |
6062 | ||
6063 | if (crtc_state->enable) | |
6064 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6065 | |
565602d7 | 6066 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6067 | } |
6068 | ||
565602d7 ML |
6069 | for_each_pipe(dev_priv, pipe) |
6070 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6071 | ||
30a970c6 JB |
6072 | return max_pixclk; |
6073 | } | |
6074 | ||
27c329ed | 6075 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6076 | { |
27c329ed ML |
6077 | struct drm_device *dev = state->dev; |
6078 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6079 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6080 | struct intel_atomic_state *intel_state = |
6081 | to_intel_atomic_state(state); | |
30a970c6 | 6082 | |
304603f4 ACO |
6083 | if (max_pixclk < 0) |
6084 | return max_pixclk; | |
30a970c6 | 6085 | |
1a617b77 | 6086 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6087 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6088 | |
1a617b77 ML |
6089 | if (!intel_state->active_crtcs) |
6090 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6091 | ||
27c329ed ML |
6092 | return 0; |
6093 | } | |
304603f4 | 6094 | |
27c329ed ML |
6095 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
6096 | { | |
6097 | struct drm_device *dev = state->dev; | |
6098 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6099 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6100 | struct intel_atomic_state *intel_state = |
6101 | to_intel_atomic_state(state); | |
85a96e7a | 6102 | |
27c329ed ML |
6103 | if (max_pixclk < 0) |
6104 | return max_pixclk; | |
85a96e7a | 6105 | |
1a617b77 | 6106 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6107 | broxton_calc_cdclk(dev_priv, max_pixclk); |
85a96e7a | 6108 | |
1a617b77 ML |
6109 | if (!intel_state->active_crtcs) |
6110 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); | |
6111 | ||
27c329ed | 6112 | return 0; |
30a970c6 JB |
6113 | } |
6114 | ||
1e69cd74 VS |
6115 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6116 | { | |
6117 | unsigned int credits, default_credits; | |
6118 | ||
6119 | if (IS_CHERRYVIEW(dev_priv)) | |
6120 | default_credits = PFI_CREDIT(12); | |
6121 | else | |
6122 | default_credits = PFI_CREDIT(8); | |
6123 | ||
bfa7df01 | 6124 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6125 | /* CHV suggested value is 31 or 63 */ |
6126 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6127 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6128 | else |
6129 | credits = PFI_CREDIT(15); | |
6130 | } else { | |
6131 | credits = default_credits; | |
6132 | } | |
6133 | ||
6134 | /* | |
6135 | * WA - write default credits before re-programming | |
6136 | * FIXME: should we also set the resend bit here? | |
6137 | */ | |
6138 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6139 | default_credits); | |
6140 | ||
6141 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6142 | credits | PFI_CREDIT_RESEND); | |
6143 | ||
6144 | /* | |
6145 | * FIXME is this guaranteed to clear | |
6146 | * immediately or should we poll for it? | |
6147 | */ | |
6148 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6149 | } | |
6150 | ||
27c329ed | 6151 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6152 | { |
a821fc46 | 6153 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6154 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6155 | struct intel_atomic_state *old_intel_state = |
6156 | to_intel_atomic_state(old_state); | |
6157 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6158 | |
27c329ed ML |
6159 | /* |
6160 | * FIXME: We can end up here with all power domains off, yet | |
6161 | * with a CDCLK frequency other than the minimum. To account | |
6162 | * for this take the PIPE-A power domain, which covers the HW | |
6163 | * blocks needed for the following programming. This can be | |
6164 | * removed once it's guaranteed that we get here either with | |
6165 | * the minimum CDCLK set, or the required power domains | |
6166 | * enabled. | |
6167 | */ | |
6168 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6169 | |
27c329ed ML |
6170 | if (IS_CHERRYVIEW(dev)) |
6171 | cherryview_set_cdclk(dev, req_cdclk); | |
6172 | else | |
6173 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6174 | |
27c329ed | 6175 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6176 | |
27c329ed | 6177 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6178 | } |
6179 | ||
89b667f8 JB |
6180 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6181 | { | |
6182 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6183 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6184 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6185 | struct intel_encoder *encoder; | |
6186 | int pipe = intel_crtc->pipe; | |
89b667f8 | 6187 | |
53d9f4e9 | 6188 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6189 | return; |
6190 | ||
6e3c9717 | 6191 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6192 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6193 | |
6194 | intel_set_pipe_timings(intel_crtc); | |
6195 | ||
c14b0485 VS |
6196 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6198 | ||
6199 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6200 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6201 | } | |
6202 | ||
5b18e57c DV |
6203 | i9xx_set_pipeconf(intel_crtc); |
6204 | ||
89b667f8 | 6205 | intel_crtc->active = true; |
89b667f8 | 6206 | |
a72e4c9f | 6207 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6208 | |
89b667f8 JB |
6209 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6210 | if (encoder->pre_pll_enable) | |
6211 | encoder->pre_pll_enable(encoder); | |
6212 | ||
a65347ba | 6213 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6214 | if (IS_CHERRYVIEW(dev)) { |
6215 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6216 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6217 | } else { |
6218 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6219 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6220 | } |
9d556c99 | 6221 | } |
89b667f8 JB |
6222 | |
6223 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6224 | if (encoder->pre_enable) | |
6225 | encoder->pre_enable(encoder); | |
6226 | ||
2dd24552 JB |
6227 | i9xx_pfit_enable(intel_crtc); |
6228 | ||
63cbb074 VS |
6229 | intel_crtc_load_lut(crtc); |
6230 | ||
e1fdc473 | 6231 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6232 | |
4b3a9526 VS |
6233 | assert_vblank_disabled(crtc); |
6234 | drm_crtc_vblank_on(crtc); | |
6235 | ||
f9b61ff6 DV |
6236 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6237 | encoder->enable(encoder); | |
89b667f8 JB |
6238 | } |
6239 | ||
f13c2ef3 DV |
6240 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6241 | { | |
6242 | struct drm_device *dev = crtc->base.dev; | |
6243 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6244 | ||
6e3c9717 ACO |
6245 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6246 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6247 | } |
6248 | ||
0b8765c6 | 6249 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6250 | { |
6251 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6252 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6254 | struct intel_encoder *encoder; |
79e53945 | 6255 | int pipe = intel_crtc->pipe; |
79e53945 | 6256 | |
53d9f4e9 | 6257 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6258 | return; |
6259 | ||
f13c2ef3 DV |
6260 | i9xx_set_pll_dividers(intel_crtc); |
6261 | ||
6e3c9717 | 6262 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6263 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6264 | |
6265 | intel_set_pipe_timings(intel_crtc); | |
6266 | ||
5b18e57c DV |
6267 | i9xx_set_pipeconf(intel_crtc); |
6268 | ||
f7abfe8b | 6269 | intel_crtc->active = true; |
6b383a7f | 6270 | |
4a3436e8 | 6271 | if (!IS_GEN2(dev)) |
a72e4c9f | 6272 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6273 | |
9d6d9f19 MK |
6274 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6275 | if (encoder->pre_enable) | |
6276 | encoder->pre_enable(encoder); | |
6277 | ||
f6736a1a DV |
6278 | i9xx_enable_pll(intel_crtc); |
6279 | ||
2dd24552 JB |
6280 | i9xx_pfit_enable(intel_crtc); |
6281 | ||
63cbb074 VS |
6282 | intel_crtc_load_lut(crtc); |
6283 | ||
f37fcc2a | 6284 | intel_update_watermarks(crtc); |
e1fdc473 | 6285 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6286 | |
4b3a9526 VS |
6287 | assert_vblank_disabled(crtc); |
6288 | drm_crtc_vblank_on(crtc); | |
6289 | ||
f9b61ff6 DV |
6290 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6291 | encoder->enable(encoder); | |
0b8765c6 | 6292 | } |
79e53945 | 6293 | |
87476d63 DV |
6294 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6295 | { | |
6296 | struct drm_device *dev = crtc->base.dev; | |
6297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6298 | |
6e3c9717 | 6299 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6300 | return; |
87476d63 | 6301 | |
328d8e82 | 6302 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6303 | |
328d8e82 DV |
6304 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6305 | I915_READ(PFIT_CONTROL)); | |
6306 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6307 | } |
6308 | ||
0b8765c6 JB |
6309 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6310 | { | |
6311 | struct drm_device *dev = crtc->dev; | |
6312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6313 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6314 | struct intel_encoder *encoder; |
0b8765c6 | 6315 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6316 | |
6304cd91 VS |
6317 | /* |
6318 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6319 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6320 | * We also need to wait on all gmch platforms because of the |
6321 | * self-refresh mode constraint explained above. | |
6304cd91 | 6322 | */ |
564ed191 | 6323 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6324 | |
4b3a9526 VS |
6325 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6326 | encoder->disable(encoder); | |
6327 | ||
f9b61ff6 DV |
6328 | drm_crtc_vblank_off(crtc); |
6329 | assert_vblank_disabled(crtc); | |
6330 | ||
575f7ab7 | 6331 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6332 | |
87476d63 | 6333 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6334 | |
89b667f8 JB |
6335 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6336 | if (encoder->post_disable) | |
6337 | encoder->post_disable(encoder); | |
6338 | ||
a65347ba | 6339 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6340 | if (IS_CHERRYVIEW(dev)) |
6341 | chv_disable_pll(dev_priv, pipe); | |
6342 | else if (IS_VALLEYVIEW(dev)) | |
6343 | vlv_disable_pll(dev_priv, pipe); | |
6344 | else | |
1c4e0274 | 6345 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6346 | } |
0b8765c6 | 6347 | |
d6db995f VS |
6348 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6349 | if (encoder->post_pll_disable) | |
6350 | encoder->post_pll_disable(encoder); | |
6351 | ||
4a3436e8 | 6352 | if (!IS_GEN2(dev)) |
a72e4c9f | 6353 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6354 | } |
6355 | ||
b17d48e2 ML |
6356 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6357 | { | |
6358 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6359 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6360 | enum intel_display_power_domain domain; | |
6361 | unsigned long domains; | |
6362 | ||
6363 | if (!intel_crtc->active) | |
6364 | return; | |
6365 | ||
a539205a | 6366 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6367 | WARN_ON(intel_crtc->unpin_work); |
6368 | ||
a539205a | 6369 | intel_pre_disable_primary(crtc); |
54a41961 ML |
6370 | |
6371 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6372 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6373 | } |
6374 | ||
b17d48e2 | 6375 | dev_priv->display.crtc_disable(crtc); |
37d9078b | 6376 | intel_crtc->active = false; |
58f9c0bc | 6377 | intel_fbc_disable(intel_crtc); |
37d9078b | 6378 | intel_update_watermarks(crtc); |
1f7457b1 | 6379 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6380 | |
6381 | domains = intel_crtc->enabled_power_domains; | |
6382 | for_each_power_domain(domain, domains) | |
6383 | intel_display_power_put(dev_priv, domain); | |
6384 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6385 | |
6386 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6387 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6388 | } |
6389 | ||
6b72d486 ML |
6390 | /* |
6391 | * turn all crtc's off, but do not adjust state | |
6392 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6393 | */ | |
70e0bd74 | 6394 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6395 | { |
e2c8b870 | 6396 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6397 | struct drm_atomic_state *state; |
e2c8b870 | 6398 | int ret; |
70e0bd74 | 6399 | |
e2c8b870 ML |
6400 | state = drm_atomic_helper_suspend(dev); |
6401 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6402 | if (ret) |
6403 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6404 | else |
6405 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6406 | return ret; |
ee7b9f93 JB |
6407 | } |
6408 | ||
ea5b213a | 6409 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6410 | { |
4ef69c7a | 6411 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6412 | |
ea5b213a CW |
6413 | drm_encoder_cleanup(encoder); |
6414 | kfree(intel_encoder); | |
7e7d76c3 JB |
6415 | } |
6416 | ||
0a91ca29 DV |
6417 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6418 | * internal consistency). */ | |
b980514c | 6419 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6420 | { |
35dd3c64 ML |
6421 | struct drm_crtc *crtc = connector->base.state->crtc; |
6422 | ||
6423 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6424 | connector->base.base.id, | |
6425 | connector->base.name); | |
6426 | ||
0a91ca29 | 6427 | if (connector->get_hw_state(connector)) { |
e85376cb | 6428 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6429 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6430 | |
35dd3c64 ML |
6431 | I915_STATE_WARN(!crtc, |
6432 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6433 | |
35dd3c64 ML |
6434 | if (!crtc) |
6435 | return; | |
6436 | ||
6437 | I915_STATE_WARN(!crtc->state->active, | |
6438 | "connector is active, but attached crtc isn't\n"); | |
6439 | ||
e85376cb | 6440 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6441 | return; |
6442 | ||
e85376cb | 6443 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6444 | "atomic encoder doesn't match attached encoder\n"); |
6445 | ||
e85376cb | 6446 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6447 | "attached encoder crtc differs from connector crtc\n"); |
6448 | } else { | |
4d688a2a ML |
6449 | I915_STATE_WARN(crtc && crtc->state->active, |
6450 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6451 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6452 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6453 | } |
79e53945 JB |
6454 | } |
6455 | ||
08d9bc92 ACO |
6456 | int intel_connector_init(struct intel_connector *connector) |
6457 | { | |
5350a031 | 6458 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6459 | |
5350a031 | 6460 | if (!connector->base.state) |
08d9bc92 ACO |
6461 | return -ENOMEM; |
6462 | ||
08d9bc92 ACO |
6463 | return 0; |
6464 | } | |
6465 | ||
6466 | struct intel_connector *intel_connector_alloc(void) | |
6467 | { | |
6468 | struct intel_connector *connector; | |
6469 | ||
6470 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6471 | if (!connector) | |
6472 | return NULL; | |
6473 | ||
6474 | if (intel_connector_init(connector) < 0) { | |
6475 | kfree(connector); | |
6476 | return NULL; | |
6477 | } | |
6478 | ||
6479 | return connector; | |
6480 | } | |
6481 | ||
f0947c37 DV |
6482 | /* Simple connector->get_hw_state implementation for encoders that support only |
6483 | * one connector and no cloning and hence the encoder state determines the state | |
6484 | * of the connector. */ | |
6485 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6486 | { |
24929352 | 6487 | enum pipe pipe = 0; |
f0947c37 | 6488 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6489 | |
f0947c37 | 6490 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6491 | } |
6492 | ||
6d293983 | 6493 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6494 | { |
6d293983 ACO |
6495 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6496 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6497 | |
6498 | return 0; | |
6499 | } | |
6500 | ||
6d293983 | 6501 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6502 | struct intel_crtc_state *pipe_config) |
1857e1da | 6503 | { |
6d293983 ACO |
6504 | struct drm_atomic_state *state = pipe_config->base.state; |
6505 | struct intel_crtc *other_crtc; | |
6506 | struct intel_crtc_state *other_crtc_state; | |
6507 | ||
1857e1da DV |
6508 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6509 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6510 | if (pipe_config->fdi_lanes > 4) { | |
6511 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6512 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6513 | return -EINVAL; |
1857e1da DV |
6514 | } |
6515 | ||
bafb6553 | 6516 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6517 | if (pipe_config->fdi_lanes > 2) { |
6518 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6519 | pipe_config->fdi_lanes); | |
6d293983 | 6520 | return -EINVAL; |
1857e1da | 6521 | } else { |
6d293983 | 6522 | return 0; |
1857e1da DV |
6523 | } |
6524 | } | |
6525 | ||
6526 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6527 | return 0; |
1857e1da DV |
6528 | |
6529 | /* Ivybridge 3 pipe is really complicated */ | |
6530 | switch (pipe) { | |
6531 | case PIPE_A: | |
6d293983 | 6532 | return 0; |
1857e1da | 6533 | case PIPE_B: |
6d293983 ACO |
6534 | if (pipe_config->fdi_lanes <= 2) |
6535 | return 0; | |
6536 | ||
6537 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6538 | other_crtc_state = | |
6539 | intel_atomic_get_crtc_state(state, other_crtc); | |
6540 | if (IS_ERR(other_crtc_state)) | |
6541 | return PTR_ERR(other_crtc_state); | |
6542 | ||
6543 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6544 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6545 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6546 | return -EINVAL; |
1857e1da | 6547 | } |
6d293983 | 6548 | return 0; |
1857e1da | 6549 | case PIPE_C: |
251cc67c VS |
6550 | if (pipe_config->fdi_lanes > 2) { |
6551 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6552 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6553 | return -EINVAL; |
251cc67c | 6554 | } |
6d293983 ACO |
6555 | |
6556 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6557 | other_crtc_state = | |
6558 | intel_atomic_get_crtc_state(state, other_crtc); | |
6559 | if (IS_ERR(other_crtc_state)) | |
6560 | return PTR_ERR(other_crtc_state); | |
6561 | ||
6562 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6563 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6564 | return -EINVAL; |
1857e1da | 6565 | } |
6d293983 | 6566 | return 0; |
1857e1da DV |
6567 | default: |
6568 | BUG(); | |
6569 | } | |
6570 | } | |
6571 | ||
e29c22c0 DV |
6572 | #define RETRY 1 |
6573 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6574 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6575 | { |
1857e1da | 6576 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6577 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6578 | int lane, link_bw, fdi_dotclock, ret; |
6579 | bool needs_recompute = false; | |
877d48d5 | 6580 | |
e29c22c0 | 6581 | retry: |
877d48d5 DV |
6582 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6583 | * each output octet as 10 bits. The actual frequency | |
6584 | * is stored as a divider into a 100MHz clock, and the | |
6585 | * mode pixel clock is stored in units of 1KHz. | |
6586 | * Hence the bw of each lane in terms of the mode signal | |
6587 | * is: | |
6588 | */ | |
6589 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6590 | ||
241bfc38 | 6591 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6592 | |
2bd89a07 | 6593 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6594 | pipe_config->pipe_bpp); |
6595 | ||
6596 | pipe_config->fdi_lanes = lane; | |
6597 | ||
2bd89a07 | 6598 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6599 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6600 | |
6d293983 ACO |
6601 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6602 | intel_crtc->pipe, pipe_config); | |
6603 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6604 | pipe_config->pipe_bpp -= 2*3; |
6605 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6606 | pipe_config->pipe_bpp); | |
6607 | needs_recompute = true; | |
6608 | pipe_config->bw_constrained = true; | |
6609 | ||
6610 | goto retry; | |
6611 | } | |
6612 | ||
6613 | if (needs_recompute) | |
6614 | return RETRY; | |
6615 | ||
6d293983 | 6616 | return ret; |
877d48d5 DV |
6617 | } |
6618 | ||
8cfb3407 VS |
6619 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6620 | struct intel_crtc_state *pipe_config) | |
6621 | { | |
6622 | if (pipe_config->pipe_bpp > 24) | |
6623 | return false; | |
6624 | ||
6625 | /* HSW can handle pixel rate up to cdclk? */ | |
6626 | if (IS_HASWELL(dev_priv->dev)) | |
6627 | return true; | |
6628 | ||
6629 | /* | |
b432e5cf VS |
6630 | * We compare against max which means we must take |
6631 | * the increased cdclk requirement into account when | |
6632 | * calculating the new cdclk. | |
6633 | * | |
6634 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6635 | */ |
6636 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6637 | dev_priv->max_cdclk_freq * 95 / 100; | |
6638 | } | |
6639 | ||
42db64ef | 6640 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6641 | struct intel_crtc_state *pipe_config) |
42db64ef | 6642 | { |
8cfb3407 VS |
6643 | struct drm_device *dev = crtc->base.dev; |
6644 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6645 | ||
d330a953 | 6646 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6647 | hsw_crtc_supports_ips(crtc) && |
6648 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6649 | } |
6650 | ||
39acb4aa VS |
6651 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6652 | { | |
6653 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6654 | ||
6655 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6656 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6657 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6658 | } | |
6659 | ||
a43f6e0f | 6660 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6661 | struct intel_crtc_state *pipe_config) |
79e53945 | 6662 | { |
a43f6e0f | 6663 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6664 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6665 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6666 | |
ad3a4479 | 6667 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6668 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6669 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6670 | |
6671 | /* | |
39acb4aa | 6672 | * Enable double wide mode when the dot clock |
cf532bb2 | 6673 | * is > 90% of the (display) core speed. |
cf532bb2 | 6674 | */ |
39acb4aa VS |
6675 | if (intel_crtc_supports_double_wide(crtc) && |
6676 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6677 | clock_limit *= 2; |
cf532bb2 | 6678 | pipe_config->double_wide = true; |
ad3a4479 VS |
6679 | } |
6680 | ||
39acb4aa VS |
6681 | if (adjusted_mode->crtc_clock > clock_limit) { |
6682 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6683 | adjusted_mode->crtc_clock, clock_limit, | |
6684 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6685 | return -EINVAL; |
39acb4aa | 6686 | } |
2c07245f | 6687 | } |
89749350 | 6688 | |
1d1d0e27 VS |
6689 | /* |
6690 | * Pipe horizontal size must be even in: | |
6691 | * - DVO ganged mode | |
6692 | * - LVDS dual channel mode | |
6693 | * - Double wide pipe | |
6694 | */ | |
a93e255f | 6695 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6696 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6697 | pipe_config->pipe_src_w &= ~1; | |
6698 | ||
8693a824 DL |
6699 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6700 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6701 | */ |
6702 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6703 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6704 | return -EINVAL; |
44f46b42 | 6705 | |
f5adf94e | 6706 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6707 | hsw_compute_ips_config(crtc, pipe_config); |
6708 | ||
877d48d5 | 6709 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6710 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6711 | |
cf5a15be | 6712 | return 0; |
79e53945 JB |
6713 | } |
6714 | ||
1652d19e VS |
6715 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6716 | { | |
6717 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6718 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6719 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6720 | uint32_t linkrate; | |
6721 | ||
414355a7 | 6722 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6723 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6724 | |
6725 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6726 | return 540000; | |
6727 | ||
6728 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6729 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6730 | |
71cd8423 DL |
6731 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6732 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6733 | /* vco 8640 */ |
6734 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6735 | case CDCLK_FREQ_450_432: | |
6736 | return 432000; | |
6737 | case CDCLK_FREQ_337_308: | |
6738 | return 308570; | |
6739 | case CDCLK_FREQ_675_617: | |
6740 | return 617140; | |
6741 | default: | |
6742 | WARN(1, "Unknown cd freq selection\n"); | |
6743 | } | |
6744 | } else { | |
6745 | /* vco 8100 */ | |
6746 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6747 | case CDCLK_FREQ_450_432: | |
6748 | return 450000; | |
6749 | case CDCLK_FREQ_337_308: | |
6750 | return 337500; | |
6751 | case CDCLK_FREQ_675_617: | |
6752 | return 675000; | |
6753 | default: | |
6754 | WARN(1, "Unknown cd freq selection\n"); | |
6755 | } | |
6756 | } | |
6757 | ||
6758 | /* error case, do as if DPLL0 isn't enabled */ | |
6759 | return 24000; | |
6760 | } | |
6761 | ||
acd3f3d3 BP |
6762 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6763 | { | |
6764 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6765 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6766 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6767 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6768 | int cdclk; | |
6769 | ||
6770 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6771 | return 19200; | |
6772 | ||
6773 | cdclk = 19200 * pll_ratio / 2; | |
6774 | ||
6775 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6776 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6777 | return cdclk; /* 576MHz or 624MHz */ | |
6778 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6779 | return cdclk * 2 / 3; /* 384MHz */ | |
6780 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6781 | return cdclk / 2; /* 288MHz */ | |
6782 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6783 | return cdclk / 4; /* 144MHz */ | |
6784 | } | |
6785 | ||
6786 | /* error case, do as if DE PLL isn't enabled */ | |
6787 | return 19200; | |
6788 | } | |
6789 | ||
1652d19e VS |
6790 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6791 | { | |
6792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6793 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6794 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6795 | ||
6796 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6797 | return 800000; | |
6798 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6799 | return 450000; | |
6800 | else if (freq == LCPLL_CLK_FREQ_450) | |
6801 | return 450000; | |
6802 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6803 | return 540000; | |
6804 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6805 | return 337500; | |
6806 | else | |
6807 | return 675000; | |
6808 | } | |
6809 | ||
6810 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6811 | { | |
6812 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6813 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6814 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6815 | ||
6816 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6817 | return 800000; | |
6818 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6819 | return 450000; | |
6820 | else if (freq == LCPLL_CLK_FREQ_450) | |
6821 | return 450000; | |
6822 | else if (IS_HSW_ULT(dev)) | |
6823 | return 337500; | |
6824 | else | |
6825 | return 540000; | |
79e53945 JB |
6826 | } |
6827 | ||
25eb05fc JB |
6828 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6829 | { | |
bfa7df01 VS |
6830 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6831 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6832 | } |
6833 | ||
b37a6434 VS |
6834 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6835 | { | |
6836 | return 450000; | |
6837 | } | |
6838 | ||
e70236a8 JB |
6839 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6840 | { | |
6841 | return 400000; | |
6842 | } | |
79e53945 | 6843 | |
e70236a8 | 6844 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6845 | { |
e907f170 | 6846 | return 333333; |
e70236a8 | 6847 | } |
79e53945 | 6848 | |
e70236a8 JB |
6849 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6850 | { | |
6851 | return 200000; | |
6852 | } | |
79e53945 | 6853 | |
257a7ffc DV |
6854 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6855 | { | |
6856 | u16 gcfgc = 0; | |
6857 | ||
6858 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6859 | ||
6860 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6861 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6862 | return 266667; |
257a7ffc | 6863 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6864 | return 333333; |
257a7ffc | 6865 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6866 | return 444444; |
257a7ffc DV |
6867 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6868 | return 200000; | |
6869 | default: | |
6870 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6871 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6872 | return 133333; |
257a7ffc | 6873 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6874 | return 166667; |
257a7ffc DV |
6875 | } |
6876 | } | |
6877 | ||
e70236a8 JB |
6878 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6879 | { | |
6880 | u16 gcfgc = 0; | |
79e53945 | 6881 | |
e70236a8 JB |
6882 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6883 | ||
6884 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6885 | return 133333; |
e70236a8 JB |
6886 | else { |
6887 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6888 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6889 | return 333333; |
e70236a8 JB |
6890 | default: |
6891 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6892 | return 190000; | |
79e53945 | 6893 | } |
e70236a8 JB |
6894 | } |
6895 | } | |
6896 | ||
6897 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6898 | { | |
e907f170 | 6899 | return 266667; |
e70236a8 JB |
6900 | } |
6901 | ||
1b1d2716 | 6902 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6903 | { |
6904 | u16 hpllcc = 0; | |
1b1d2716 | 6905 | |
65cd2b3f VS |
6906 | /* |
6907 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6908 | * encoding is different :( | |
6909 | * FIXME is this the right way to detect 852GM/852GMV? | |
6910 | */ | |
6911 | if (dev->pdev->revision == 0x1) | |
6912 | return 133333; | |
6913 | ||
1b1d2716 VS |
6914 | pci_bus_read_config_word(dev->pdev->bus, |
6915 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6916 | ||
e70236a8 JB |
6917 | /* Assume that the hardware is in the high speed state. This |
6918 | * should be the default. | |
6919 | */ | |
6920 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6921 | case GC_CLOCK_133_200: | |
1b1d2716 | 6922 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6923 | case GC_CLOCK_100_200: |
6924 | return 200000; | |
6925 | case GC_CLOCK_166_250: | |
6926 | return 250000; | |
6927 | case GC_CLOCK_100_133: | |
e907f170 | 6928 | return 133333; |
1b1d2716 VS |
6929 | case GC_CLOCK_133_266: |
6930 | case GC_CLOCK_133_266_2: | |
6931 | case GC_CLOCK_166_266: | |
6932 | return 266667; | |
e70236a8 | 6933 | } |
79e53945 | 6934 | |
e70236a8 JB |
6935 | /* Shouldn't happen */ |
6936 | return 0; | |
6937 | } | |
79e53945 | 6938 | |
e70236a8 JB |
6939 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6940 | { | |
e907f170 | 6941 | return 133333; |
79e53945 JB |
6942 | } |
6943 | ||
34edce2f VS |
6944 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6945 | { | |
6946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6947 | static const unsigned int blb_vco[8] = { | |
6948 | [0] = 3200000, | |
6949 | [1] = 4000000, | |
6950 | [2] = 5333333, | |
6951 | [3] = 4800000, | |
6952 | [4] = 6400000, | |
6953 | }; | |
6954 | static const unsigned int pnv_vco[8] = { | |
6955 | [0] = 3200000, | |
6956 | [1] = 4000000, | |
6957 | [2] = 5333333, | |
6958 | [3] = 4800000, | |
6959 | [4] = 2666667, | |
6960 | }; | |
6961 | static const unsigned int cl_vco[8] = { | |
6962 | [0] = 3200000, | |
6963 | [1] = 4000000, | |
6964 | [2] = 5333333, | |
6965 | [3] = 6400000, | |
6966 | [4] = 3333333, | |
6967 | [5] = 3566667, | |
6968 | [6] = 4266667, | |
6969 | }; | |
6970 | static const unsigned int elk_vco[8] = { | |
6971 | [0] = 3200000, | |
6972 | [1] = 4000000, | |
6973 | [2] = 5333333, | |
6974 | [3] = 4800000, | |
6975 | }; | |
6976 | static const unsigned int ctg_vco[8] = { | |
6977 | [0] = 3200000, | |
6978 | [1] = 4000000, | |
6979 | [2] = 5333333, | |
6980 | [3] = 6400000, | |
6981 | [4] = 2666667, | |
6982 | [5] = 4266667, | |
6983 | }; | |
6984 | const unsigned int *vco_table; | |
6985 | unsigned int vco; | |
6986 | uint8_t tmp = 0; | |
6987 | ||
6988 | /* FIXME other chipsets? */ | |
6989 | if (IS_GM45(dev)) | |
6990 | vco_table = ctg_vco; | |
6991 | else if (IS_G4X(dev)) | |
6992 | vco_table = elk_vco; | |
6993 | else if (IS_CRESTLINE(dev)) | |
6994 | vco_table = cl_vco; | |
6995 | else if (IS_PINEVIEW(dev)) | |
6996 | vco_table = pnv_vco; | |
6997 | else if (IS_G33(dev)) | |
6998 | vco_table = blb_vco; | |
6999 | else | |
7000 | return 0; | |
7001 | ||
7002 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7003 | ||
7004 | vco = vco_table[tmp & 0x7]; | |
7005 | if (vco == 0) | |
7006 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7007 | else | |
7008 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7009 | ||
7010 | return vco; | |
7011 | } | |
7012 | ||
7013 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7014 | { | |
7015 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7016 | uint16_t tmp = 0; | |
7017 | ||
7018 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7019 | ||
7020 | cdclk_sel = (tmp >> 12) & 0x1; | |
7021 | ||
7022 | switch (vco) { | |
7023 | case 2666667: | |
7024 | case 4000000: | |
7025 | case 5333333: | |
7026 | return cdclk_sel ? 333333 : 222222; | |
7027 | case 3200000: | |
7028 | return cdclk_sel ? 320000 : 228571; | |
7029 | default: | |
7030 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7031 | return 222222; | |
7032 | } | |
7033 | } | |
7034 | ||
7035 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7036 | { | |
7037 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7038 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7039 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7040 | const uint8_t *div_table; | |
7041 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7042 | uint16_t tmp = 0; | |
7043 | ||
7044 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7045 | ||
7046 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7047 | ||
7048 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7049 | goto fail; | |
7050 | ||
7051 | switch (vco) { | |
7052 | case 3200000: | |
7053 | div_table = div_3200; | |
7054 | break; | |
7055 | case 4000000: | |
7056 | div_table = div_4000; | |
7057 | break; | |
7058 | case 5333333: | |
7059 | div_table = div_5333; | |
7060 | break; | |
7061 | default: | |
7062 | goto fail; | |
7063 | } | |
7064 | ||
7065 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7066 | ||
caf4e252 | 7067 | fail: |
34edce2f VS |
7068 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7069 | return 200000; | |
7070 | } | |
7071 | ||
7072 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7073 | { | |
7074 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7075 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7076 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7077 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7078 | const uint8_t *div_table; | |
7079 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7080 | uint16_t tmp = 0; | |
7081 | ||
7082 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7083 | ||
7084 | cdclk_sel = (tmp >> 4) & 0x7; | |
7085 | ||
7086 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7087 | goto fail; | |
7088 | ||
7089 | switch (vco) { | |
7090 | case 3200000: | |
7091 | div_table = div_3200; | |
7092 | break; | |
7093 | case 4000000: | |
7094 | div_table = div_4000; | |
7095 | break; | |
7096 | case 4800000: | |
7097 | div_table = div_4800; | |
7098 | break; | |
7099 | case 5333333: | |
7100 | div_table = div_5333; | |
7101 | break; | |
7102 | default: | |
7103 | goto fail; | |
7104 | } | |
7105 | ||
7106 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7107 | ||
caf4e252 | 7108 | fail: |
34edce2f VS |
7109 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7110 | return 190476; | |
7111 | } | |
7112 | ||
2c07245f | 7113 | static void |
a65851af | 7114 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7115 | { |
a65851af VS |
7116 | while (*num > DATA_LINK_M_N_MASK || |
7117 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7118 | *num >>= 1; |
7119 | *den >>= 1; | |
7120 | } | |
7121 | } | |
7122 | ||
a65851af VS |
7123 | static void compute_m_n(unsigned int m, unsigned int n, |
7124 | uint32_t *ret_m, uint32_t *ret_n) | |
7125 | { | |
7126 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7127 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7128 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7129 | } | |
7130 | ||
e69d0bc1 DV |
7131 | void |
7132 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7133 | int pixel_clock, int link_clock, | |
7134 | struct intel_link_m_n *m_n) | |
2c07245f | 7135 | { |
e69d0bc1 | 7136 | m_n->tu = 64; |
a65851af VS |
7137 | |
7138 | compute_m_n(bits_per_pixel * pixel_clock, | |
7139 | link_clock * nlanes * 8, | |
7140 | &m_n->gmch_m, &m_n->gmch_n); | |
7141 | ||
7142 | compute_m_n(pixel_clock, link_clock, | |
7143 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7144 | } |
7145 | ||
a7615030 CW |
7146 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7147 | { | |
d330a953 JN |
7148 | if (i915.panel_use_ssc >= 0) |
7149 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7150 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7151 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7152 | } |
7153 | ||
a93e255f ACO |
7154 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7155 | int num_connectors) | |
c65d77d8 | 7156 | { |
a93e255f | 7157 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7158 | struct drm_i915_private *dev_priv = dev->dev_private; |
7159 | int refclk; | |
7160 | ||
a93e255f ACO |
7161 | WARN_ON(!crtc_state->base.state); |
7162 | ||
666a4537 | 7163 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7164 | refclk = 100000; |
a93e255f | 7165 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7166 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7167 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7168 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7169 | } else if (!IS_GEN2(dev)) { |
7170 | refclk = 96000; | |
7171 | } else { | |
7172 | refclk = 48000; | |
7173 | } | |
7174 | ||
7175 | return refclk; | |
7176 | } | |
7177 | ||
7429e9d4 | 7178 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7179 | { |
7df00d7a | 7180 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7181 | } |
f47709a9 | 7182 | |
7429e9d4 DV |
7183 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7184 | { | |
7185 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7186 | } |
7187 | ||
f47709a9 | 7188 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7189 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7190 | intel_clock_t *reduced_clock) |
7191 | { | |
f47709a9 | 7192 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7193 | u32 fp, fp2 = 0; |
7194 | ||
7195 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7196 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7197 | if (reduced_clock) |
7429e9d4 | 7198 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7199 | } else { |
190f68c5 | 7200 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7201 | if (reduced_clock) |
7429e9d4 | 7202 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7203 | } |
7204 | ||
190f68c5 | 7205 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7206 | |
f47709a9 | 7207 | crtc->lowfreq_avail = false; |
a93e255f | 7208 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7209 | reduced_clock) { |
190f68c5 | 7210 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7211 | crtc->lowfreq_avail = true; |
a7516a05 | 7212 | } else { |
190f68c5 | 7213 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7214 | } |
7215 | } | |
7216 | ||
5e69f97f CML |
7217 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7218 | pipe) | |
89b667f8 JB |
7219 | { |
7220 | u32 reg_val; | |
7221 | ||
7222 | /* | |
7223 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7224 | * and set it to a reasonable value instead. | |
7225 | */ | |
ab3c759a | 7226 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7227 | reg_val &= 0xffffff00; |
7228 | reg_val |= 0x00000030; | |
ab3c759a | 7229 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7230 | |
ab3c759a | 7231 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7232 | reg_val &= 0x8cffffff; |
7233 | reg_val = 0x8c000000; | |
ab3c759a | 7234 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7235 | |
ab3c759a | 7236 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7237 | reg_val &= 0xffffff00; |
ab3c759a | 7238 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7239 | |
ab3c759a | 7240 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7241 | reg_val &= 0x00ffffff; |
7242 | reg_val |= 0xb0000000; | |
ab3c759a | 7243 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7244 | } |
7245 | ||
b551842d DV |
7246 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7247 | struct intel_link_m_n *m_n) | |
7248 | { | |
7249 | struct drm_device *dev = crtc->base.dev; | |
7250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7251 | int pipe = crtc->pipe; | |
7252 | ||
e3b95f1e DV |
7253 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7254 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7255 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7256 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7257 | } |
7258 | ||
7259 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7260 | struct intel_link_m_n *m_n, |
7261 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7262 | { |
7263 | struct drm_device *dev = crtc->base.dev; | |
7264 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7265 | int pipe = crtc->pipe; | |
6e3c9717 | 7266 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7267 | |
7268 | if (INTEL_INFO(dev)->gen >= 5) { | |
7269 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7270 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7271 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7272 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7273 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7274 | * for gen < 8) and if DRRS is supported (to make sure the | |
7275 | * registers are not unnecessarily accessed). | |
7276 | */ | |
44395bfe | 7277 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7278 | crtc->config->has_drrs) { |
f769cd24 VK |
7279 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7280 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7281 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7282 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7283 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7284 | } | |
b551842d | 7285 | } else { |
e3b95f1e DV |
7286 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7287 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7288 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7289 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7290 | } |
7291 | } | |
7292 | ||
fe3cd48d | 7293 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7294 | { |
fe3cd48d R |
7295 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7296 | ||
7297 | if (m_n == M1_N1) { | |
7298 | dp_m_n = &crtc->config->dp_m_n; | |
7299 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7300 | } else if (m_n == M2_N2) { | |
7301 | ||
7302 | /* | |
7303 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7304 | * needs to be programmed into M1_N1. | |
7305 | */ | |
7306 | dp_m_n = &crtc->config->dp_m2_n2; | |
7307 | } else { | |
7308 | DRM_ERROR("Unsupported divider value\n"); | |
7309 | return; | |
7310 | } | |
7311 | ||
6e3c9717 ACO |
7312 | if (crtc->config->has_pch_encoder) |
7313 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7314 | else |
fe3cd48d | 7315 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7316 | } |
7317 | ||
251ac862 DV |
7318 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7319 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7320 | { |
7321 | u32 dpll, dpll_md; | |
7322 | ||
7323 | /* | |
7324 | * Enable DPIO clock input. We should never disable the reference | |
7325 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7326 | * on it. | |
7327 | */ | |
60bfe44f VS |
7328 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7329 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7330 | /* We should never disable this, set it here for state tracking */ |
7331 | if (crtc->pipe == PIPE_B) | |
7332 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7333 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7334 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7335 | |
d288f65f | 7336 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7337 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7338 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7339 | } |
7340 | ||
d288f65f | 7341 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7342 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7343 | { |
f47709a9 | 7344 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7345 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7346 | int pipe = crtc->pipe; |
bdd4b6a6 | 7347 | u32 mdiv; |
a0c4da24 | 7348 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7349 | u32 coreclk, reg_val; |
a0c4da24 | 7350 | |
a580516d | 7351 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7352 | |
d288f65f VS |
7353 | bestn = pipe_config->dpll.n; |
7354 | bestm1 = pipe_config->dpll.m1; | |
7355 | bestm2 = pipe_config->dpll.m2; | |
7356 | bestp1 = pipe_config->dpll.p1; | |
7357 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7358 | |
89b667f8 JB |
7359 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7360 | ||
7361 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7362 | if (pipe == PIPE_B) |
5e69f97f | 7363 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7364 | |
7365 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7366 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7367 | |
7368 | /* Disable target IRef on PLL */ | |
ab3c759a | 7369 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7370 | reg_val &= 0x00ffffff; |
ab3c759a | 7371 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7372 | |
7373 | /* Disable fast lock */ | |
ab3c759a | 7374 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7375 | |
7376 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7377 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7378 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7379 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7380 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7381 | |
7382 | /* | |
7383 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7384 | * but we don't support that). | |
7385 | * Note: don't use the DAC post divider as it seems unstable. | |
7386 | */ | |
7387 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7388 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7389 | |
a0c4da24 | 7390 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7391 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7392 | |
89b667f8 | 7393 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7394 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7395 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7396 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7397 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7398 | 0x009f0003); |
89b667f8 | 7399 | else |
ab3c759a | 7400 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7401 | 0x00d0000f); |
7402 | ||
681a8504 | 7403 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7404 | /* Use SSC source */ |
bdd4b6a6 | 7405 | if (pipe == PIPE_A) |
ab3c759a | 7406 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7407 | 0x0df40000); |
7408 | else | |
ab3c759a | 7409 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7410 | 0x0df70000); |
7411 | } else { /* HDMI or VGA */ | |
7412 | /* Use bend source */ | |
bdd4b6a6 | 7413 | if (pipe == PIPE_A) |
ab3c759a | 7414 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7415 | 0x0df70000); |
7416 | else | |
ab3c759a | 7417 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7418 | 0x0df40000); |
7419 | } | |
a0c4da24 | 7420 | |
ab3c759a | 7421 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7422 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7423 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7424 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7425 | coreclk |= 0x01000000; |
ab3c759a | 7426 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7427 | |
ab3c759a | 7428 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7429 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7430 | } |
7431 | ||
251ac862 DV |
7432 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7433 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7434 | { |
60bfe44f VS |
7435 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7436 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7437 | DPLL_VCO_ENABLE; |
7438 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7439 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7440 | |
d288f65f VS |
7441 | pipe_config->dpll_hw_state.dpll_md = |
7442 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7443 | } |
7444 | ||
d288f65f | 7445 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7446 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7447 | { |
7448 | struct drm_device *dev = crtc->base.dev; | |
7449 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7450 | int pipe = crtc->pipe; | |
f0f59a00 | 7451 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7452 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7453 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7454 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7455 | u32 dpio_val; |
9cbe40c1 | 7456 | int vco; |
9d556c99 | 7457 | |
d288f65f VS |
7458 | bestn = pipe_config->dpll.n; |
7459 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7460 | bestm1 = pipe_config->dpll.m1; | |
7461 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7462 | bestp1 = pipe_config->dpll.p1; | |
7463 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7464 | vco = pipe_config->dpll.vco; |
a945ce7e | 7465 | dpio_val = 0; |
9cbe40c1 | 7466 | loopfilter = 0; |
9d556c99 CML |
7467 | |
7468 | /* | |
7469 | * Enable Refclk and SSC | |
7470 | */ | |
a11b0703 | 7471 | I915_WRITE(dpll_reg, |
d288f65f | 7472 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7473 | |
a580516d | 7474 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7475 | |
9d556c99 CML |
7476 | /* p1 and p2 divider */ |
7477 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7478 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7479 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7480 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7481 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7482 | ||
7483 | /* Feedback post-divider - m2 */ | |
7484 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7485 | ||
7486 | /* Feedback refclk divider - n and m1 */ | |
7487 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7488 | DPIO_CHV_M1_DIV_BY_2 | | |
7489 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7490 | ||
7491 | /* M2 fraction division */ | |
25a25dfc | 7492 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7493 | |
7494 | /* M2 fraction division enable */ | |
a945ce7e VP |
7495 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7496 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7497 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7498 | if (bestm2_frac) | |
7499 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7500 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7501 | |
de3a0fde VP |
7502 | /* Program digital lock detect threshold */ |
7503 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7504 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7505 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7506 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7507 | if (!bestm2_frac) | |
7508 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7509 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7510 | ||
9d556c99 | 7511 | /* Loop filter */ |
9cbe40c1 VP |
7512 | if (vco == 5400000) { |
7513 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7514 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7515 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7516 | tribuf_calcntr = 0x9; | |
7517 | } else if (vco <= 6200000) { | |
7518 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7519 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7520 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7521 | tribuf_calcntr = 0x9; | |
7522 | } else if (vco <= 6480000) { | |
7523 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7524 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7525 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7526 | tribuf_calcntr = 0x8; | |
7527 | } else { | |
7528 | /* Not supported. Apply the same limits as in the max case */ | |
7529 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7530 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7531 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7532 | tribuf_calcntr = 0; | |
7533 | } | |
9d556c99 CML |
7534 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7535 | ||
968040b2 | 7536 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7537 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7538 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7539 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7540 | ||
9d556c99 CML |
7541 | /* AFC Recal */ |
7542 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7543 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7544 | DPIO_AFC_RECAL); | |
7545 | ||
a580516d | 7546 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7547 | } |
7548 | ||
d288f65f VS |
7549 | /** |
7550 | * vlv_force_pll_on - forcibly enable just the PLL | |
7551 | * @dev_priv: i915 private structure | |
7552 | * @pipe: pipe PLL to enable | |
7553 | * @dpll: PLL configuration | |
7554 | * | |
7555 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7556 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7557 | * be enabled. | |
7558 | */ | |
3f36b937 TU |
7559 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7560 | const struct dpll *dpll) | |
d288f65f VS |
7561 | { |
7562 | struct intel_crtc *crtc = | |
7563 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7564 | struct intel_crtc_state *pipe_config; |
7565 | ||
7566 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7567 | if (!pipe_config) | |
7568 | return -ENOMEM; | |
7569 | ||
7570 | pipe_config->base.crtc = &crtc->base; | |
7571 | pipe_config->pixel_multiplier = 1; | |
7572 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7573 | |
7574 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7575 | chv_compute_dpll(crtc, pipe_config); |
7576 | chv_prepare_pll(crtc, pipe_config); | |
7577 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7578 | } else { |
3f36b937 TU |
7579 | vlv_compute_dpll(crtc, pipe_config); |
7580 | vlv_prepare_pll(crtc, pipe_config); | |
7581 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7582 | } |
3f36b937 TU |
7583 | |
7584 | kfree(pipe_config); | |
7585 | ||
7586 | return 0; | |
d288f65f VS |
7587 | } |
7588 | ||
7589 | /** | |
7590 | * vlv_force_pll_off - forcibly disable just the PLL | |
7591 | * @dev_priv: i915 private structure | |
7592 | * @pipe: pipe PLL to disable | |
7593 | * | |
7594 | * Disable the PLL for @pipe. To be used in cases where we need | |
7595 | * the PLL enabled even when @pipe is not going to be enabled. | |
7596 | */ | |
7597 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7598 | { | |
7599 | if (IS_CHERRYVIEW(dev)) | |
7600 | chv_disable_pll(to_i915(dev), pipe); | |
7601 | else | |
7602 | vlv_disable_pll(to_i915(dev), pipe); | |
7603 | } | |
7604 | ||
251ac862 DV |
7605 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7606 | struct intel_crtc_state *crtc_state, | |
7607 | intel_clock_t *reduced_clock, | |
7608 | int num_connectors) | |
eb1cbe48 | 7609 | { |
f47709a9 | 7610 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7611 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7612 | u32 dpll; |
7613 | bool is_sdvo; | |
190f68c5 | 7614 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7615 | |
190f68c5 | 7616 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7617 | |
a93e255f ACO |
7618 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7619 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7620 | |
7621 | dpll = DPLL_VGA_MODE_DIS; | |
7622 | ||
a93e255f | 7623 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7624 | dpll |= DPLLB_MODE_LVDS; |
7625 | else | |
7626 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7627 | |
ef1b460d | 7628 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7629 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7630 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7631 | } |
198a037f DV |
7632 | |
7633 | if (is_sdvo) | |
4a33e48d | 7634 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7635 | |
190f68c5 | 7636 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7637 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7638 | |
7639 | /* compute bitmask from p1 value */ | |
7640 | if (IS_PINEVIEW(dev)) | |
7641 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7642 | else { | |
7643 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7644 | if (IS_G4X(dev) && reduced_clock) | |
7645 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7646 | } | |
7647 | switch (clock->p2) { | |
7648 | case 5: | |
7649 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7650 | break; | |
7651 | case 7: | |
7652 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7653 | break; | |
7654 | case 10: | |
7655 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7656 | break; | |
7657 | case 14: | |
7658 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7659 | break; | |
7660 | } | |
7661 | if (INTEL_INFO(dev)->gen >= 4) | |
7662 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7663 | ||
190f68c5 | 7664 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7665 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7666 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7667 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7668 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7669 | else | |
7670 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7671 | ||
7672 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7673 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7674 | |
eb1cbe48 | 7675 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7676 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7677 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7678 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7679 | } |
7680 | } | |
7681 | ||
251ac862 DV |
7682 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7683 | struct intel_crtc_state *crtc_state, | |
7684 | intel_clock_t *reduced_clock, | |
7685 | int num_connectors) | |
eb1cbe48 | 7686 | { |
f47709a9 | 7687 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7688 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7689 | u32 dpll; |
190f68c5 | 7690 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7691 | |
190f68c5 | 7692 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7693 | |
eb1cbe48 DV |
7694 | dpll = DPLL_VGA_MODE_DIS; |
7695 | ||
a93e255f | 7696 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7697 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7698 | } else { | |
7699 | if (clock->p1 == 2) | |
7700 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7701 | else | |
7702 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7703 | if (clock->p2 == 4) | |
7704 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7705 | } | |
7706 | ||
a93e255f | 7707 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7708 | dpll |= DPLL_DVO_2X_MODE; |
7709 | ||
a93e255f | 7710 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7711 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7712 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7713 | else | |
7714 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7715 | ||
7716 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7717 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7718 | } |
7719 | ||
8a654f3b | 7720 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7721 | { |
7722 | struct drm_device *dev = intel_crtc->base.dev; | |
7723 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7724 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7725 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7726 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7727 | uint32_t crtc_vtotal, crtc_vblank_end; |
7728 | int vsyncshift = 0; | |
4d8a62ea DV |
7729 | |
7730 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7731 | * the hw state checker will get angry at the mismatch. */ | |
7732 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7733 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7734 | |
609aeaca | 7735 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7736 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7737 | crtc_vtotal -= 1; |
7738 | crtc_vblank_end -= 1; | |
609aeaca | 7739 | |
409ee761 | 7740 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7741 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7742 | else | |
7743 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7744 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7745 | if (vsyncshift < 0) |
7746 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7747 | } |
7748 | ||
7749 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7750 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7751 | |
fe2b8f9d | 7752 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7753 | (adjusted_mode->crtc_hdisplay - 1) | |
7754 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7755 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7756 | (adjusted_mode->crtc_hblank_start - 1) | |
7757 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7758 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7759 | (adjusted_mode->crtc_hsync_start - 1) | |
7760 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7761 | ||
fe2b8f9d | 7762 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7763 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7764 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7765 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7766 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7767 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7768 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7769 | (adjusted_mode->crtc_vsync_start - 1) | |
7770 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7771 | ||
b5e508d4 PZ |
7772 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7773 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7774 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7775 | * bits. */ | |
7776 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7777 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7778 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7779 | ||
b0e77b9c PZ |
7780 | /* pipesrc controls the size that is scaled from, which should |
7781 | * always be the user's requested size. | |
7782 | */ | |
7783 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7784 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7785 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7786 | } |
7787 | ||
1bd1bd80 | 7788 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7789 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7790 | { |
7791 | struct drm_device *dev = crtc->base.dev; | |
7792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7793 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7794 | uint32_t tmp; | |
7795 | ||
7796 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7797 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7798 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7799 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7800 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7801 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7802 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7803 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7804 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7805 | |
7806 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7807 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7808 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7809 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7810 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7811 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7812 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7813 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7814 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7815 | |
7816 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7817 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7818 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7819 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7820 | } |
7821 | ||
7822 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7823 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7824 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7825 | ||
2d112de7 ACO |
7826 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7827 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7828 | } |
7829 | ||
f6a83288 | 7830 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7831 | struct intel_crtc_state *pipe_config) |
babea61d | 7832 | { |
2d112de7 ACO |
7833 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7834 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7835 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7836 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7837 | |
2d112de7 ACO |
7838 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7839 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7840 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7841 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7842 | |
2d112de7 | 7843 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7844 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7845 | |
2d112de7 ACO |
7846 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7847 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7848 | |
7849 | mode->hsync = drm_mode_hsync(mode); | |
7850 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7851 | drm_mode_set_name(mode); | |
babea61d JB |
7852 | } |
7853 | ||
84b046f3 DV |
7854 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7855 | { | |
7856 | struct drm_device *dev = intel_crtc->base.dev; | |
7857 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7858 | uint32_t pipeconf; | |
7859 | ||
9f11a9e4 | 7860 | pipeconf = 0; |
84b046f3 | 7861 | |
b6b5d049 VS |
7862 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7863 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7864 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7865 | |
6e3c9717 | 7866 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7867 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7868 | |
ff9ce46e | 7869 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7870 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7871 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7872 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7873 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7874 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7875 | |
6e3c9717 | 7876 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7877 | case 18: |
7878 | pipeconf |= PIPECONF_6BPC; | |
7879 | break; | |
7880 | case 24: | |
7881 | pipeconf |= PIPECONF_8BPC; | |
7882 | break; | |
7883 | case 30: | |
7884 | pipeconf |= PIPECONF_10BPC; | |
7885 | break; | |
7886 | default: | |
7887 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7888 | BUG(); | |
84b046f3 DV |
7889 | } |
7890 | } | |
7891 | ||
7892 | if (HAS_PIPE_CXSR(dev)) { | |
7893 | if (intel_crtc->lowfreq_avail) { | |
7894 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7895 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7896 | } else { | |
7897 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7898 | } |
7899 | } | |
7900 | ||
6e3c9717 | 7901 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7902 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7903 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7904 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7905 | else | |
7906 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7907 | } else | |
84b046f3 DV |
7908 | pipeconf |= PIPECONF_PROGRESSIVE; |
7909 | ||
666a4537 WB |
7910 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7911 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7912 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7913 | |
84b046f3 DV |
7914 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7915 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7916 | } | |
7917 | ||
190f68c5 ACO |
7918 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7919 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7920 | { |
c7653199 | 7921 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7922 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7923 | int refclk, num_connectors = 0; |
c329a4ec DV |
7924 | intel_clock_t clock; |
7925 | bool ok; | |
d4906093 | 7926 | const intel_limit_t *limit; |
55bb9992 | 7927 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7928 | struct drm_connector *connector; |
55bb9992 ACO |
7929 | struct drm_connector_state *connector_state; |
7930 | int i; | |
79e53945 | 7931 | |
dd3cd74a ACO |
7932 | memset(&crtc_state->dpll_hw_state, 0, |
7933 | sizeof(crtc_state->dpll_hw_state)); | |
7934 | ||
a65347ba JN |
7935 | if (crtc_state->has_dsi_encoder) |
7936 | return 0; | |
43565a06 | 7937 | |
a65347ba JN |
7938 | for_each_connector_in_state(state, connector, connector_state, i) { |
7939 | if (connector_state->crtc == &crtc->base) | |
7940 | num_connectors++; | |
79e53945 JB |
7941 | } |
7942 | ||
190f68c5 | 7943 | if (!crtc_state->clock_set) { |
a93e255f | 7944 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7945 | |
e9fd1c02 JN |
7946 | /* |
7947 | * Returns a set of divisors for the desired target clock with | |
7948 | * the given refclk, or FALSE. The returned values represent | |
7949 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7950 | * 2) / p1 / p2. | |
7951 | */ | |
a93e255f ACO |
7952 | limit = intel_limit(crtc_state, refclk); |
7953 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7954 | crtc_state->port_clock, |
e9fd1c02 | 7955 | refclk, NULL, &clock); |
f2335330 | 7956 | if (!ok) { |
e9fd1c02 JN |
7957 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7958 | return -EINVAL; | |
7959 | } | |
79e53945 | 7960 | |
f2335330 | 7961 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7962 | crtc_state->dpll.n = clock.n; |
7963 | crtc_state->dpll.m1 = clock.m1; | |
7964 | crtc_state->dpll.m2 = clock.m2; | |
7965 | crtc_state->dpll.p1 = clock.p1; | |
7966 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7967 | } |
7026d4ac | 7968 | |
e9fd1c02 | 7969 | if (IS_GEN2(dev)) { |
c329a4ec | 7970 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7971 | num_connectors); |
9d556c99 | 7972 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 7973 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7974 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 7975 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7976 | } else { |
c329a4ec | 7977 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7978 | num_connectors); |
e9fd1c02 | 7979 | } |
79e53945 | 7980 | |
c8f7a0db | 7981 | return 0; |
f564048e EA |
7982 | } |
7983 | ||
2fa2fe9a | 7984 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7985 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7986 | { |
7987 | struct drm_device *dev = crtc->base.dev; | |
7988 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7989 | uint32_t tmp; | |
7990 | ||
dc9e7dec VS |
7991 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7992 | return; | |
7993 | ||
2fa2fe9a | 7994 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7995 | if (!(tmp & PFIT_ENABLE)) |
7996 | return; | |
2fa2fe9a | 7997 | |
06922821 | 7998 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7999 | if (INTEL_INFO(dev)->gen < 4) { |
8000 | if (crtc->pipe != PIPE_B) | |
8001 | return; | |
2fa2fe9a DV |
8002 | } else { |
8003 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8004 | return; | |
8005 | } | |
8006 | ||
06922821 | 8007 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
8008 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
8009 | if (INTEL_INFO(dev)->gen < 5) | |
8010 | pipe_config->gmch_pfit.lvds_border_bits = | |
8011 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
8012 | } | |
8013 | ||
acbec814 | 8014 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8015 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8016 | { |
8017 | struct drm_device *dev = crtc->base.dev; | |
8018 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8019 | int pipe = pipe_config->cpu_transcoder; | |
8020 | intel_clock_t clock; | |
8021 | u32 mdiv; | |
662c6ecb | 8022 | int refclk = 100000; |
acbec814 | 8023 | |
f573de5a SK |
8024 | /* In case of MIPI DPLL will not even be used */ |
8025 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
8026 | return; | |
8027 | ||
a580516d | 8028 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8029 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8030 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8031 | |
8032 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8033 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8034 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8035 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8036 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8037 | ||
dccbea3b | 8038 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8039 | } |
8040 | ||
5724dbd1 DL |
8041 | static void |
8042 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8043 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8044 | { |
8045 | struct drm_device *dev = crtc->base.dev; | |
8046 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8047 | u32 val, base, offset; | |
8048 | int pipe = crtc->pipe, plane = crtc->plane; | |
8049 | int fourcc, pixel_format; | |
6761dd31 | 8050 | unsigned int aligned_height; |
b113d5ee | 8051 | struct drm_framebuffer *fb; |
1b842c89 | 8052 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8053 | |
42a7b088 DL |
8054 | val = I915_READ(DSPCNTR(plane)); |
8055 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8056 | return; | |
8057 | ||
d9806c9f | 8058 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8059 | if (!intel_fb) { |
1ad292b5 JB |
8060 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8061 | return; | |
8062 | } | |
8063 | ||
1b842c89 DL |
8064 | fb = &intel_fb->base; |
8065 | ||
18c5247e DV |
8066 | if (INTEL_INFO(dev)->gen >= 4) { |
8067 | if (val & DISPPLANE_TILED) { | |
49af449b | 8068 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8069 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8070 | } | |
8071 | } | |
1ad292b5 JB |
8072 | |
8073 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8074 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8075 | fb->pixel_format = fourcc; |
8076 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8077 | |
8078 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8079 | if (plane_config->tiling) |
1ad292b5 JB |
8080 | offset = I915_READ(DSPTILEOFF(plane)); |
8081 | else | |
8082 | offset = I915_READ(DSPLINOFF(plane)); | |
8083 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8084 | } else { | |
8085 | base = I915_READ(DSPADDR(plane)); | |
8086 | } | |
8087 | plane_config->base = base; | |
8088 | ||
8089 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8090 | fb->width = ((val >> 16) & 0xfff) + 1; |
8091 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8092 | |
8093 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8094 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8095 | |
b113d5ee | 8096 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8097 | fb->pixel_format, |
8098 | fb->modifier[0]); | |
1ad292b5 | 8099 | |
f37b5c2b | 8100 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8101 | |
2844a921 DL |
8102 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8103 | pipe_name(pipe), plane, fb->width, fb->height, | |
8104 | fb->bits_per_pixel, base, fb->pitches[0], | |
8105 | plane_config->size); | |
1ad292b5 | 8106 | |
2d14030b | 8107 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8108 | } |
8109 | ||
70b23a98 | 8110 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8111 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8112 | { |
8113 | struct drm_device *dev = crtc->base.dev; | |
8114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8115 | int pipe = pipe_config->cpu_transcoder; | |
8116 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8117 | intel_clock_t clock; | |
0d7b6b11 | 8118 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8119 | int refclk = 100000; |
8120 | ||
a580516d | 8121 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8122 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8123 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8124 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8125 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8126 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8127 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8128 | |
8129 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8130 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8131 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8132 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8133 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8134 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8135 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8136 | ||
dccbea3b | 8137 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8138 | } |
8139 | ||
0e8ffe1b | 8140 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8141 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8142 | { |
8143 | struct drm_device *dev = crtc->base.dev; | |
8144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8145 | uint32_t tmp; | |
8146 | ||
f458ebbc DV |
8147 | if (!intel_display_power_is_enabled(dev_priv, |
8148 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
8149 | return false; |
8150 | ||
e143a21c | 8151 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8152 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8153 | |
0e8ffe1b DV |
8154 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8155 | if (!(tmp & PIPECONF_ENABLE)) | |
8156 | return false; | |
8157 | ||
666a4537 | 8158 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8159 | switch (tmp & PIPECONF_BPC_MASK) { |
8160 | case PIPECONF_6BPC: | |
8161 | pipe_config->pipe_bpp = 18; | |
8162 | break; | |
8163 | case PIPECONF_8BPC: | |
8164 | pipe_config->pipe_bpp = 24; | |
8165 | break; | |
8166 | case PIPECONF_10BPC: | |
8167 | pipe_config->pipe_bpp = 30; | |
8168 | break; | |
8169 | default: | |
8170 | break; | |
8171 | } | |
8172 | } | |
8173 | ||
666a4537 WB |
8174 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8175 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8176 | pipe_config->limited_color_range = true; |
8177 | ||
282740f7 VS |
8178 | if (INTEL_INFO(dev)->gen < 4) |
8179 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8180 | ||
1bd1bd80 DV |
8181 | intel_get_pipe_timings(crtc, pipe_config); |
8182 | ||
2fa2fe9a DV |
8183 | i9xx_get_pfit_config(crtc, pipe_config); |
8184 | ||
6c49f241 DV |
8185 | if (INTEL_INFO(dev)->gen >= 4) { |
8186 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8187 | pipe_config->pixel_multiplier = | |
8188 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8189 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8190 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8191 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8192 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8193 | pipe_config->pixel_multiplier = | |
8194 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8195 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8196 | } else { | |
8197 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8198 | * port and will be fixed up in the encoder->get_config | |
8199 | * function. */ | |
8200 | pipe_config->pixel_multiplier = 1; | |
8201 | } | |
8bcc2795 | 8202 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8203 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8204 | /* |
8205 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8206 | * on 830. Filter it out here so that we don't | |
8207 | * report errors due to that. | |
8208 | */ | |
8209 | if (IS_I830(dev)) | |
8210 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8211 | ||
8bcc2795 DV |
8212 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8213 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8214 | } else { |
8215 | /* Mask out read-only status bits. */ | |
8216 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8217 | DPLL_PORTC_READY_MASK | | |
8218 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8219 | } |
6c49f241 | 8220 | |
70b23a98 VS |
8221 | if (IS_CHERRYVIEW(dev)) |
8222 | chv_crtc_clock_get(crtc, pipe_config); | |
8223 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8224 | vlv_crtc_clock_get(crtc, pipe_config); |
8225 | else | |
8226 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8227 | |
0f64614d VS |
8228 | /* |
8229 | * Normally the dotclock is filled in by the encoder .get_config() | |
8230 | * but in case the pipe is enabled w/o any ports we need a sane | |
8231 | * default. | |
8232 | */ | |
8233 | pipe_config->base.adjusted_mode.crtc_clock = | |
8234 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8235 | ||
0e8ffe1b DV |
8236 | return true; |
8237 | } | |
8238 | ||
dde86e2d | 8239 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8240 | { |
8241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8242 | struct intel_encoder *encoder; |
74cfd7ac | 8243 | u32 val, final; |
13d83a67 | 8244 | bool has_lvds = false; |
199e5d79 | 8245 | bool has_cpu_edp = false; |
199e5d79 | 8246 | bool has_panel = false; |
99eb6a01 KP |
8247 | bool has_ck505 = false; |
8248 | bool can_ssc = false; | |
13d83a67 JB |
8249 | |
8250 | /* We need to take the global config into account */ | |
b2784e15 | 8251 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8252 | switch (encoder->type) { |
8253 | case INTEL_OUTPUT_LVDS: | |
8254 | has_panel = true; | |
8255 | has_lvds = true; | |
8256 | break; | |
8257 | case INTEL_OUTPUT_EDP: | |
8258 | has_panel = true; | |
2de6905f | 8259 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8260 | has_cpu_edp = true; |
8261 | break; | |
6847d71b PZ |
8262 | default: |
8263 | break; | |
13d83a67 JB |
8264 | } |
8265 | } | |
8266 | ||
99eb6a01 | 8267 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8268 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8269 | can_ssc = has_ck505; |
8270 | } else { | |
8271 | has_ck505 = false; | |
8272 | can_ssc = true; | |
8273 | } | |
8274 | ||
2de6905f ID |
8275 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8276 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8277 | |
8278 | /* Ironlake: try to setup display ref clock before DPLL | |
8279 | * enabling. This is only under driver's control after | |
8280 | * PCH B stepping, previous chipset stepping should be | |
8281 | * ignoring this setting. | |
8282 | */ | |
74cfd7ac CW |
8283 | val = I915_READ(PCH_DREF_CONTROL); |
8284 | ||
8285 | /* As we must carefully and slowly disable/enable each source in turn, | |
8286 | * compute the final state we want first and check if we need to | |
8287 | * make any changes at all. | |
8288 | */ | |
8289 | final = val; | |
8290 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8291 | if (has_ck505) | |
8292 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8293 | else | |
8294 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8295 | ||
8296 | final &= ~DREF_SSC_SOURCE_MASK; | |
8297 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8298 | final &= ~DREF_SSC1_ENABLE; | |
8299 | ||
8300 | if (has_panel) { | |
8301 | final |= DREF_SSC_SOURCE_ENABLE; | |
8302 | ||
8303 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8304 | final |= DREF_SSC1_ENABLE; | |
8305 | ||
8306 | if (has_cpu_edp) { | |
8307 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8308 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8309 | else | |
8310 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8311 | } else | |
8312 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8313 | } else { | |
8314 | final |= DREF_SSC_SOURCE_DISABLE; | |
8315 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8316 | } | |
8317 | ||
8318 | if (final == val) | |
8319 | return; | |
8320 | ||
13d83a67 | 8321 | /* Always enable nonspread source */ |
74cfd7ac | 8322 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8323 | |
99eb6a01 | 8324 | if (has_ck505) |
74cfd7ac | 8325 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8326 | else |
74cfd7ac | 8327 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8328 | |
199e5d79 | 8329 | if (has_panel) { |
74cfd7ac CW |
8330 | val &= ~DREF_SSC_SOURCE_MASK; |
8331 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8332 | |
199e5d79 | 8333 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8334 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8335 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8336 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8337 | } else |
74cfd7ac | 8338 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8339 | |
8340 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8341 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8342 | POSTING_READ(PCH_DREF_CONTROL); |
8343 | udelay(200); | |
8344 | ||
74cfd7ac | 8345 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8346 | |
8347 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8348 | if (has_cpu_edp) { |
99eb6a01 | 8349 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8350 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8351 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8352 | } else |
74cfd7ac | 8353 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8354 | } else |
74cfd7ac | 8355 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8356 | |
74cfd7ac | 8357 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8358 | POSTING_READ(PCH_DREF_CONTROL); |
8359 | udelay(200); | |
8360 | } else { | |
8361 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8362 | ||
74cfd7ac | 8363 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8364 | |
8365 | /* Turn off CPU output */ | |
74cfd7ac | 8366 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8367 | |
74cfd7ac | 8368 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8369 | POSTING_READ(PCH_DREF_CONTROL); |
8370 | udelay(200); | |
8371 | ||
8372 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8373 | val &= ~DREF_SSC_SOURCE_MASK; |
8374 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8375 | |
8376 | /* Turn off SSC1 */ | |
74cfd7ac | 8377 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8378 | |
74cfd7ac | 8379 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8380 | POSTING_READ(PCH_DREF_CONTROL); |
8381 | udelay(200); | |
8382 | } | |
74cfd7ac CW |
8383 | |
8384 | BUG_ON(val != final); | |
13d83a67 JB |
8385 | } |
8386 | ||
f31f2d55 | 8387 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8388 | { |
f31f2d55 | 8389 | uint32_t tmp; |
dde86e2d | 8390 | |
0ff066a9 PZ |
8391 | tmp = I915_READ(SOUTH_CHICKEN2); |
8392 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8393 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8394 | |
0ff066a9 PZ |
8395 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8396 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8397 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8398 | |
0ff066a9 PZ |
8399 | tmp = I915_READ(SOUTH_CHICKEN2); |
8400 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8401 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8402 | |
0ff066a9 PZ |
8403 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8404 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8405 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8406 | } |
8407 | ||
8408 | /* WaMPhyProgramming:hsw */ | |
8409 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8410 | { | |
8411 | uint32_t tmp; | |
dde86e2d PZ |
8412 | |
8413 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8414 | tmp &= ~(0xFF << 24); | |
8415 | tmp |= (0x12 << 24); | |
8416 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8417 | ||
dde86e2d PZ |
8418 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8419 | tmp |= (1 << 11); | |
8420 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8421 | ||
8422 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8423 | tmp |= (1 << 11); | |
8424 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8425 | ||
dde86e2d PZ |
8426 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8427 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8428 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8429 | ||
8430 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8431 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8432 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8433 | ||
0ff066a9 PZ |
8434 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8435 | tmp &= ~(7 << 13); | |
8436 | tmp |= (5 << 13); | |
8437 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8438 | |
0ff066a9 PZ |
8439 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8440 | tmp &= ~(7 << 13); | |
8441 | tmp |= (5 << 13); | |
8442 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8443 | |
8444 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8445 | tmp &= ~0xFF; | |
8446 | tmp |= 0x1C; | |
8447 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8448 | ||
8449 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8450 | tmp &= ~0xFF; | |
8451 | tmp |= 0x1C; | |
8452 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8453 | ||
8454 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8455 | tmp &= ~(0xFF << 16); | |
8456 | tmp |= (0x1C << 16); | |
8457 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8458 | ||
8459 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8460 | tmp &= ~(0xFF << 16); | |
8461 | tmp |= (0x1C << 16); | |
8462 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8463 | ||
0ff066a9 PZ |
8464 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8465 | tmp |= (1 << 27); | |
8466 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8467 | |
0ff066a9 PZ |
8468 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8469 | tmp |= (1 << 27); | |
8470 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8471 | |
0ff066a9 PZ |
8472 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8473 | tmp &= ~(0xF << 28); | |
8474 | tmp |= (4 << 28); | |
8475 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8476 | |
0ff066a9 PZ |
8477 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8478 | tmp &= ~(0xF << 28); | |
8479 | tmp |= (4 << 28); | |
8480 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8481 | } |
8482 | ||
2fa86a1f PZ |
8483 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8484 | * Programming" based on the parameters passed: | |
8485 | * - Sequence to enable CLKOUT_DP | |
8486 | * - Sequence to enable CLKOUT_DP without spread | |
8487 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8488 | */ | |
8489 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8490 | bool with_fdi) | |
f31f2d55 PZ |
8491 | { |
8492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8493 | uint32_t reg, tmp; |
8494 | ||
8495 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8496 | with_spread = true; | |
c2699524 | 8497 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8498 | with_fdi = false; |
f31f2d55 | 8499 | |
a580516d | 8500 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8501 | |
8502 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8503 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8504 | tmp |= SBI_SSCCTL_PATHALT; | |
8505 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8506 | ||
8507 | udelay(24); | |
8508 | ||
2fa86a1f PZ |
8509 | if (with_spread) { |
8510 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8511 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8512 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8513 | |
2fa86a1f PZ |
8514 | if (with_fdi) { |
8515 | lpt_reset_fdi_mphy(dev_priv); | |
8516 | lpt_program_fdi_mphy(dev_priv); | |
8517 | } | |
8518 | } | |
dde86e2d | 8519 | |
c2699524 | 8520 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8521 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8522 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8523 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8524 | |
a580516d | 8525 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8526 | } |
8527 | ||
47701c3b PZ |
8528 | /* Sequence to disable CLKOUT_DP */ |
8529 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8530 | { | |
8531 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8532 | uint32_t reg, tmp; | |
8533 | ||
a580516d | 8534 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8535 | |
c2699524 | 8536 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8537 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8538 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8539 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8540 | ||
8541 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8542 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8543 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8544 | tmp |= SBI_SSCCTL_PATHALT; | |
8545 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8546 | udelay(32); | |
8547 | } | |
8548 | tmp |= SBI_SSCCTL_DISABLE; | |
8549 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8550 | } | |
8551 | ||
a580516d | 8552 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8553 | } |
8554 | ||
f7be2c21 VS |
8555 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8556 | ||
8557 | static const uint16_t sscdivintphase[] = { | |
8558 | [BEND_IDX( 50)] = 0x3B23, | |
8559 | [BEND_IDX( 45)] = 0x3B23, | |
8560 | [BEND_IDX( 40)] = 0x3C23, | |
8561 | [BEND_IDX( 35)] = 0x3C23, | |
8562 | [BEND_IDX( 30)] = 0x3D23, | |
8563 | [BEND_IDX( 25)] = 0x3D23, | |
8564 | [BEND_IDX( 20)] = 0x3E23, | |
8565 | [BEND_IDX( 15)] = 0x3E23, | |
8566 | [BEND_IDX( 10)] = 0x3F23, | |
8567 | [BEND_IDX( 5)] = 0x3F23, | |
8568 | [BEND_IDX( 0)] = 0x0025, | |
8569 | [BEND_IDX( -5)] = 0x0025, | |
8570 | [BEND_IDX(-10)] = 0x0125, | |
8571 | [BEND_IDX(-15)] = 0x0125, | |
8572 | [BEND_IDX(-20)] = 0x0225, | |
8573 | [BEND_IDX(-25)] = 0x0225, | |
8574 | [BEND_IDX(-30)] = 0x0325, | |
8575 | [BEND_IDX(-35)] = 0x0325, | |
8576 | [BEND_IDX(-40)] = 0x0425, | |
8577 | [BEND_IDX(-45)] = 0x0425, | |
8578 | [BEND_IDX(-50)] = 0x0525, | |
8579 | }; | |
8580 | ||
8581 | /* | |
8582 | * Bend CLKOUT_DP | |
8583 | * steps -50 to 50 inclusive, in steps of 5 | |
8584 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8585 | * change in clock period = -(steps / 10) * 5.787 ps | |
8586 | */ | |
8587 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8588 | { | |
8589 | uint32_t tmp; | |
8590 | int idx = BEND_IDX(steps); | |
8591 | ||
8592 | if (WARN_ON(steps % 5 != 0)) | |
8593 | return; | |
8594 | ||
8595 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8596 | return; | |
8597 | ||
8598 | mutex_lock(&dev_priv->sb_lock); | |
8599 | ||
8600 | if (steps % 10 != 0) | |
8601 | tmp = 0xAAAAAAAB; | |
8602 | else | |
8603 | tmp = 0x00000000; | |
8604 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8605 | ||
8606 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8607 | tmp &= 0xffff0000; | |
8608 | tmp |= sscdivintphase[idx]; | |
8609 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8610 | ||
8611 | mutex_unlock(&dev_priv->sb_lock); | |
8612 | } | |
8613 | ||
8614 | #undef BEND_IDX | |
8615 | ||
bf8fa3d3 PZ |
8616 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8617 | { | |
bf8fa3d3 PZ |
8618 | struct intel_encoder *encoder; |
8619 | bool has_vga = false; | |
8620 | ||
b2784e15 | 8621 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8622 | switch (encoder->type) { |
8623 | case INTEL_OUTPUT_ANALOG: | |
8624 | has_vga = true; | |
8625 | break; | |
6847d71b PZ |
8626 | default: |
8627 | break; | |
bf8fa3d3 PZ |
8628 | } |
8629 | } | |
8630 | ||
f7be2c21 VS |
8631 | if (has_vga) { |
8632 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8633 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8634 | } else { |
47701c3b | 8635 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8636 | } |
bf8fa3d3 PZ |
8637 | } |
8638 | ||
dde86e2d PZ |
8639 | /* |
8640 | * Initialize reference clocks when the driver loads | |
8641 | */ | |
8642 | void intel_init_pch_refclk(struct drm_device *dev) | |
8643 | { | |
8644 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8645 | ironlake_init_pch_refclk(dev); | |
8646 | else if (HAS_PCH_LPT(dev)) | |
8647 | lpt_init_pch_refclk(dev); | |
8648 | } | |
8649 | ||
55bb9992 | 8650 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8651 | { |
55bb9992 | 8652 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8653 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8654 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8655 | struct drm_connector *connector; |
55bb9992 | 8656 | struct drm_connector_state *connector_state; |
d9d444cb | 8657 | struct intel_encoder *encoder; |
55bb9992 | 8658 | int num_connectors = 0, i; |
d9d444cb JB |
8659 | bool is_lvds = false; |
8660 | ||
da3ced29 | 8661 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8662 | if (connector_state->crtc != crtc_state->base.crtc) |
8663 | continue; | |
8664 | ||
8665 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8666 | ||
d9d444cb JB |
8667 | switch (encoder->type) { |
8668 | case INTEL_OUTPUT_LVDS: | |
8669 | is_lvds = true; | |
8670 | break; | |
6847d71b PZ |
8671 | default: |
8672 | break; | |
d9d444cb JB |
8673 | } |
8674 | num_connectors++; | |
8675 | } | |
8676 | ||
8677 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8678 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8679 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8680 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8681 | } |
8682 | ||
8683 | return 120000; | |
8684 | } | |
8685 | ||
6ff93609 | 8686 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8687 | { |
c8203565 | 8688 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8689 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8690 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8691 | uint32_t val; |
8692 | ||
78114071 | 8693 | val = 0; |
c8203565 | 8694 | |
6e3c9717 | 8695 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8696 | case 18: |
dfd07d72 | 8697 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8698 | break; |
8699 | case 24: | |
dfd07d72 | 8700 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8701 | break; |
8702 | case 30: | |
dfd07d72 | 8703 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8704 | break; |
8705 | case 36: | |
dfd07d72 | 8706 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8707 | break; |
8708 | default: | |
cc769b62 PZ |
8709 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8710 | BUG(); | |
c8203565 PZ |
8711 | } |
8712 | ||
6e3c9717 | 8713 | if (intel_crtc->config->dither) |
c8203565 PZ |
8714 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8715 | ||
6e3c9717 | 8716 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8717 | val |= PIPECONF_INTERLACED_ILK; |
8718 | else | |
8719 | val |= PIPECONF_PROGRESSIVE; | |
8720 | ||
6e3c9717 | 8721 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8722 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8723 | |
c8203565 PZ |
8724 | I915_WRITE(PIPECONF(pipe), val); |
8725 | POSTING_READ(PIPECONF(pipe)); | |
8726 | } | |
8727 | ||
86d3efce VS |
8728 | /* |
8729 | * Set up the pipe CSC unit. | |
8730 | * | |
8731 | * Currently only full range RGB to limited range RGB conversion | |
8732 | * is supported, but eventually this should handle various | |
8733 | * RGB<->YCbCr scenarios as well. | |
8734 | */ | |
50f3b016 | 8735 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8736 | { |
8737 | struct drm_device *dev = crtc->dev; | |
8738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8739 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8740 | int pipe = intel_crtc->pipe; | |
8741 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8742 | ||
8743 | /* | |
8744 | * TODO: Check what kind of values actually come out of the pipe | |
8745 | * with these coeff/postoff values and adjust to get the best | |
8746 | * accuracy. Perhaps we even need to take the bpc value into | |
8747 | * consideration. | |
8748 | */ | |
8749 | ||
6e3c9717 | 8750 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8751 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8752 | ||
8753 | /* | |
8754 | * GY/GU and RY/RU should be the other way around according | |
8755 | * to BSpec, but reality doesn't agree. Just set them up in | |
8756 | * a way that results in the correct picture. | |
8757 | */ | |
8758 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8759 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8760 | ||
8761 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8762 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8763 | ||
8764 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8765 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8766 | ||
8767 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8768 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8769 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8770 | ||
8771 | if (INTEL_INFO(dev)->gen > 6) { | |
8772 | uint16_t postoff = 0; | |
8773 | ||
6e3c9717 | 8774 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8775 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8776 | |
8777 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8778 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8779 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8780 | ||
8781 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8782 | } else { | |
8783 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8784 | ||
6e3c9717 | 8785 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8786 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8787 | ||
8788 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8789 | } | |
8790 | } | |
8791 | ||
6ff93609 | 8792 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8793 | { |
756f85cf PZ |
8794 | struct drm_device *dev = crtc->dev; |
8795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8796 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8797 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8798 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8799 | uint32_t val; |
8800 | ||
3eff4faa | 8801 | val = 0; |
ee2b0b38 | 8802 | |
6e3c9717 | 8803 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8804 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8805 | ||
6e3c9717 | 8806 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8807 | val |= PIPECONF_INTERLACED_ILK; |
8808 | else | |
8809 | val |= PIPECONF_PROGRESSIVE; | |
8810 | ||
702e7a56 PZ |
8811 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8812 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8813 | |
8814 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8815 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8816 | |
3cdf122c | 8817 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8818 | val = 0; |
8819 | ||
6e3c9717 | 8820 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8821 | case 18: |
8822 | val |= PIPEMISC_DITHER_6_BPC; | |
8823 | break; | |
8824 | case 24: | |
8825 | val |= PIPEMISC_DITHER_8_BPC; | |
8826 | break; | |
8827 | case 30: | |
8828 | val |= PIPEMISC_DITHER_10_BPC; | |
8829 | break; | |
8830 | case 36: | |
8831 | val |= PIPEMISC_DITHER_12_BPC; | |
8832 | break; | |
8833 | default: | |
8834 | /* Case prevented by pipe_config_set_bpp. */ | |
8835 | BUG(); | |
8836 | } | |
8837 | ||
6e3c9717 | 8838 | if (intel_crtc->config->dither) |
756f85cf PZ |
8839 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8840 | ||
8841 | I915_WRITE(PIPEMISC(pipe), val); | |
8842 | } | |
ee2b0b38 PZ |
8843 | } |
8844 | ||
6591c6e4 | 8845 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8846 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8847 | intel_clock_t *clock, |
8848 | bool *has_reduced_clock, | |
8849 | intel_clock_t *reduced_clock) | |
8850 | { | |
8851 | struct drm_device *dev = crtc->dev; | |
8852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8853 | int refclk; |
d4906093 | 8854 | const intel_limit_t *limit; |
c329a4ec | 8855 | bool ret; |
79e53945 | 8856 | |
55bb9992 | 8857 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8858 | |
d4906093 ML |
8859 | /* |
8860 | * Returns a set of divisors for the desired target clock with the given | |
8861 | * refclk, or FALSE. The returned values represent the clock equation: | |
8862 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8863 | */ | |
a93e255f ACO |
8864 | limit = intel_limit(crtc_state, refclk); |
8865 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8866 | crtc_state->port_clock, |
ee9300bb | 8867 | refclk, NULL, clock); |
6591c6e4 PZ |
8868 | if (!ret) |
8869 | return false; | |
cda4b7d3 | 8870 | |
6591c6e4 PZ |
8871 | return true; |
8872 | } | |
8873 | ||
d4b1931c PZ |
8874 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8875 | { | |
8876 | /* | |
8877 | * Account for spread spectrum to avoid | |
8878 | * oversubscribing the link. Max center spread | |
8879 | * is 2.5%; use 5% for safety's sake. | |
8880 | */ | |
8881 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8882 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8883 | } |
8884 | ||
7429e9d4 | 8885 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8886 | { |
7429e9d4 | 8887 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8888 | } |
8889 | ||
de13a2e3 | 8890 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8891 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8892 | u32 *fp, |
9a7c7890 | 8893 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8894 | { |
de13a2e3 | 8895 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8896 | struct drm_device *dev = crtc->dev; |
8897 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8898 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8899 | struct drm_connector *connector; |
55bb9992 ACO |
8900 | struct drm_connector_state *connector_state; |
8901 | struct intel_encoder *encoder; | |
de13a2e3 | 8902 | uint32_t dpll; |
55bb9992 | 8903 | int factor, num_connectors = 0, i; |
09ede541 | 8904 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8905 | |
da3ced29 | 8906 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8907 | if (connector_state->crtc != crtc_state->base.crtc) |
8908 | continue; | |
8909 | ||
8910 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8911 | ||
8912 | switch (encoder->type) { | |
79e53945 JB |
8913 | case INTEL_OUTPUT_LVDS: |
8914 | is_lvds = true; | |
8915 | break; | |
8916 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8917 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8918 | is_sdvo = true; |
79e53945 | 8919 | break; |
6847d71b PZ |
8920 | default: |
8921 | break; | |
79e53945 | 8922 | } |
43565a06 | 8923 | |
c751ce4f | 8924 | num_connectors++; |
79e53945 | 8925 | } |
79e53945 | 8926 | |
c1858123 | 8927 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8928 | factor = 21; |
8929 | if (is_lvds) { | |
8930 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8931 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8932 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8933 | factor = 25; |
190f68c5 | 8934 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8935 | factor = 20; |
c1858123 | 8936 | |
190f68c5 | 8937 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8938 | *fp |= FP_CB_TUNE; |
2c07245f | 8939 | |
9a7c7890 DV |
8940 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8941 | *fp2 |= FP_CB_TUNE; | |
8942 | ||
5eddb70b | 8943 | dpll = 0; |
2c07245f | 8944 | |
a07d6787 EA |
8945 | if (is_lvds) |
8946 | dpll |= DPLLB_MODE_LVDS; | |
8947 | else | |
8948 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8949 | |
190f68c5 | 8950 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8951 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8952 | |
8953 | if (is_sdvo) | |
4a33e48d | 8954 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8955 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8956 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8957 | |
a07d6787 | 8958 | /* compute bitmask from p1 value */ |
190f68c5 | 8959 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8960 | /* also FPA1 */ |
190f68c5 | 8961 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8962 | |
190f68c5 | 8963 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8964 | case 5: |
8965 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8966 | break; | |
8967 | case 7: | |
8968 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8969 | break; | |
8970 | case 10: | |
8971 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8972 | break; | |
8973 | case 14: | |
8974 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8975 | break; | |
79e53945 JB |
8976 | } |
8977 | ||
b4c09f3b | 8978 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8979 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8980 | else |
8981 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8982 | ||
959e16d6 | 8983 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8984 | } |
8985 | ||
190f68c5 ACO |
8986 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8987 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8988 | { |
c7653199 | 8989 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8990 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8991 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8992 | bool ok, has_reduced_clock = false; |
8b47047b | 8993 | bool is_lvds = false; |
e2b78267 | 8994 | struct intel_shared_dpll *pll; |
de13a2e3 | 8995 | |
dd3cd74a ACO |
8996 | memset(&crtc_state->dpll_hw_state, 0, |
8997 | sizeof(crtc_state->dpll_hw_state)); | |
8998 | ||
7905df29 | 8999 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 9000 | |
5dc5298b PZ |
9001 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
9002 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 9003 | |
190f68c5 | 9004 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 9005 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 9006 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
9007 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9008 | return -EINVAL; | |
79e53945 | 9009 | } |
f47709a9 | 9010 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
9011 | if (!crtc_state->clock_set) { |
9012 | crtc_state->dpll.n = clock.n; | |
9013 | crtc_state->dpll.m1 = clock.m1; | |
9014 | crtc_state->dpll.m2 = clock.m2; | |
9015 | crtc_state->dpll.p1 = clock.p1; | |
9016 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 9017 | } |
79e53945 | 9018 | |
5dc5298b | 9019 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
9020 | if (crtc_state->has_pch_encoder) { |
9021 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 9022 | if (has_reduced_clock) |
7429e9d4 | 9023 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 9024 | |
190f68c5 | 9025 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
9026 | &fp, &reduced_clock, |
9027 | has_reduced_clock ? &fp2 : NULL); | |
9028 | ||
190f68c5 ACO |
9029 | crtc_state->dpll_hw_state.dpll = dpll; |
9030 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 9031 | if (has_reduced_clock) |
190f68c5 | 9032 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 9033 | else |
190f68c5 | 9034 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 9035 | |
190f68c5 | 9036 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 9037 | if (pll == NULL) { |
84f44ce7 | 9038 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 9039 | pipe_name(crtc->pipe)); |
4b645f14 JB |
9040 | return -EINVAL; |
9041 | } | |
3fb37703 | 9042 | } |
79e53945 | 9043 | |
ab585dea | 9044 | if (is_lvds && has_reduced_clock) |
c7653199 | 9045 | crtc->lowfreq_avail = true; |
bcd644e0 | 9046 | else |
c7653199 | 9047 | crtc->lowfreq_avail = false; |
e2b78267 | 9048 | |
c8f7a0db | 9049 | return 0; |
79e53945 JB |
9050 | } |
9051 | ||
eb14cb74 VS |
9052 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9053 | struct intel_link_m_n *m_n) | |
9054 | { | |
9055 | struct drm_device *dev = crtc->base.dev; | |
9056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9057 | enum pipe pipe = crtc->pipe; | |
9058 | ||
9059 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9060 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9061 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9062 | & ~TU_SIZE_MASK; | |
9063 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9064 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9065 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9066 | } | |
9067 | ||
9068 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9069 | enum transcoder transcoder, | |
b95af8be VK |
9070 | struct intel_link_m_n *m_n, |
9071 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9072 | { |
9073 | struct drm_device *dev = crtc->base.dev; | |
9074 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 9075 | enum pipe pipe = crtc->pipe; |
72419203 | 9076 | |
eb14cb74 VS |
9077 | if (INTEL_INFO(dev)->gen >= 5) { |
9078 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9079 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9080 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9081 | & ~TU_SIZE_MASK; | |
9082 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9083 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9084 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9085 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9086 | * gen < 8) and if DRRS is supported (to make sure the | |
9087 | * registers are not unnecessarily read). | |
9088 | */ | |
9089 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9090 | crtc->config->has_drrs) { |
b95af8be VK |
9091 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9092 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9093 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9094 | & ~TU_SIZE_MASK; | |
9095 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9096 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9097 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9098 | } | |
eb14cb74 VS |
9099 | } else { |
9100 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9101 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9102 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9103 | & ~TU_SIZE_MASK; | |
9104 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9105 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9106 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9107 | } | |
9108 | } | |
9109 | ||
9110 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9111 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9112 | { |
681a8504 | 9113 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9114 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9115 | else | |
9116 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9117 | &pipe_config->dp_m_n, |
9118 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9119 | } |
72419203 | 9120 | |
eb14cb74 | 9121 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9122 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9123 | { |
9124 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9125 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9126 | } |
9127 | ||
bd2e244f | 9128 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9129 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9130 | { |
9131 | struct drm_device *dev = crtc->base.dev; | |
9132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9133 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9134 | uint32_t ps_ctrl = 0; | |
9135 | int id = -1; | |
9136 | int i; | |
bd2e244f | 9137 | |
a1b2278e CK |
9138 | /* find scaler attached to this pipe */ |
9139 | for (i = 0; i < crtc->num_scalers; i++) { | |
9140 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9141 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9142 | id = i; | |
9143 | pipe_config->pch_pfit.enabled = true; | |
9144 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9145 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9146 | break; | |
9147 | } | |
9148 | } | |
bd2e244f | 9149 | |
a1b2278e CK |
9150 | scaler_state->scaler_id = id; |
9151 | if (id >= 0) { | |
9152 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9153 | } else { | |
9154 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9155 | } |
9156 | } | |
9157 | ||
5724dbd1 DL |
9158 | static void |
9159 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9160 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9161 | { |
9162 | struct drm_device *dev = crtc->base.dev; | |
9163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9164 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9165 | int pipe = crtc->pipe; |
9166 | int fourcc, pixel_format; | |
6761dd31 | 9167 | unsigned int aligned_height; |
bc8d7dff | 9168 | struct drm_framebuffer *fb; |
1b842c89 | 9169 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9170 | |
d9806c9f | 9171 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9172 | if (!intel_fb) { |
bc8d7dff DL |
9173 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9174 | return; | |
9175 | } | |
9176 | ||
1b842c89 DL |
9177 | fb = &intel_fb->base; |
9178 | ||
bc8d7dff | 9179 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9180 | if (!(val & PLANE_CTL_ENABLE)) |
9181 | goto error; | |
9182 | ||
bc8d7dff DL |
9183 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9184 | fourcc = skl_format_to_fourcc(pixel_format, | |
9185 | val & PLANE_CTL_ORDER_RGBX, | |
9186 | val & PLANE_CTL_ALPHA_MASK); | |
9187 | fb->pixel_format = fourcc; | |
9188 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9189 | ||
40f46283 DL |
9190 | tiling = val & PLANE_CTL_TILED_MASK; |
9191 | switch (tiling) { | |
9192 | case PLANE_CTL_TILED_LINEAR: | |
9193 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9194 | break; | |
9195 | case PLANE_CTL_TILED_X: | |
9196 | plane_config->tiling = I915_TILING_X; | |
9197 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9198 | break; | |
9199 | case PLANE_CTL_TILED_Y: | |
9200 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9201 | break; | |
9202 | case PLANE_CTL_TILED_YF: | |
9203 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9204 | break; | |
9205 | default: | |
9206 | MISSING_CASE(tiling); | |
9207 | goto error; | |
9208 | } | |
9209 | ||
bc8d7dff DL |
9210 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9211 | plane_config->base = base; | |
9212 | ||
9213 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9214 | ||
9215 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9216 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9217 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9218 | ||
9219 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9220 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9221 | fb->pixel_format); |
bc8d7dff DL |
9222 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9223 | ||
9224 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9225 | fb->pixel_format, |
9226 | fb->modifier[0]); | |
bc8d7dff | 9227 | |
f37b5c2b | 9228 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9229 | |
9230 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9231 | pipe_name(pipe), fb->width, fb->height, | |
9232 | fb->bits_per_pixel, base, fb->pitches[0], | |
9233 | plane_config->size); | |
9234 | ||
2d14030b | 9235 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9236 | return; |
9237 | ||
9238 | error: | |
9239 | kfree(fb); | |
9240 | } | |
9241 | ||
2fa2fe9a | 9242 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9243 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9244 | { |
9245 | struct drm_device *dev = crtc->base.dev; | |
9246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9247 | uint32_t tmp; | |
9248 | ||
9249 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9250 | ||
9251 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9252 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9253 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9254 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9255 | |
9256 | /* We currently do not free assignements of panel fitters on | |
9257 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9258 | * differentiates them) so just WARN about this case for now. */ | |
9259 | if (IS_GEN7(dev)) { | |
9260 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9261 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9262 | } | |
2fa2fe9a | 9263 | } |
79e53945 JB |
9264 | } |
9265 | ||
5724dbd1 DL |
9266 | static void |
9267 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9268 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9269 | { |
9270 | struct drm_device *dev = crtc->base.dev; | |
9271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9272 | u32 val, base, offset; | |
aeee5a49 | 9273 | int pipe = crtc->pipe; |
4c6baa59 | 9274 | int fourcc, pixel_format; |
6761dd31 | 9275 | unsigned int aligned_height; |
b113d5ee | 9276 | struct drm_framebuffer *fb; |
1b842c89 | 9277 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9278 | |
42a7b088 DL |
9279 | val = I915_READ(DSPCNTR(pipe)); |
9280 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9281 | return; | |
9282 | ||
d9806c9f | 9283 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9284 | if (!intel_fb) { |
4c6baa59 JB |
9285 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9286 | return; | |
9287 | } | |
9288 | ||
1b842c89 DL |
9289 | fb = &intel_fb->base; |
9290 | ||
18c5247e DV |
9291 | if (INTEL_INFO(dev)->gen >= 4) { |
9292 | if (val & DISPPLANE_TILED) { | |
49af449b | 9293 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9294 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9295 | } | |
9296 | } | |
4c6baa59 JB |
9297 | |
9298 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9299 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9300 | fb->pixel_format = fourcc; |
9301 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9302 | |
aeee5a49 | 9303 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9304 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9305 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9306 | } else { |
49af449b | 9307 | if (plane_config->tiling) |
aeee5a49 | 9308 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9309 | else |
aeee5a49 | 9310 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9311 | } |
9312 | plane_config->base = base; | |
9313 | ||
9314 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9315 | fb->width = ((val >> 16) & 0xfff) + 1; |
9316 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9317 | |
9318 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9319 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9320 | |
b113d5ee | 9321 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9322 | fb->pixel_format, |
9323 | fb->modifier[0]); | |
4c6baa59 | 9324 | |
f37b5c2b | 9325 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9326 | |
2844a921 DL |
9327 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9328 | pipe_name(pipe), fb->width, fb->height, | |
9329 | fb->bits_per_pixel, base, fb->pitches[0], | |
9330 | plane_config->size); | |
b113d5ee | 9331 | |
2d14030b | 9332 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9333 | } |
9334 | ||
0e8ffe1b | 9335 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9336 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9337 | { |
9338 | struct drm_device *dev = crtc->base.dev; | |
9339 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9340 | uint32_t tmp; | |
9341 | ||
f458ebbc DV |
9342 | if (!intel_display_power_is_enabled(dev_priv, |
9343 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
9344 | return false; |
9345 | ||
e143a21c | 9346 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9347 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9348 | |
0e8ffe1b DV |
9349 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9350 | if (!(tmp & PIPECONF_ENABLE)) | |
9351 | return false; | |
9352 | ||
42571aef VS |
9353 | switch (tmp & PIPECONF_BPC_MASK) { |
9354 | case PIPECONF_6BPC: | |
9355 | pipe_config->pipe_bpp = 18; | |
9356 | break; | |
9357 | case PIPECONF_8BPC: | |
9358 | pipe_config->pipe_bpp = 24; | |
9359 | break; | |
9360 | case PIPECONF_10BPC: | |
9361 | pipe_config->pipe_bpp = 30; | |
9362 | break; | |
9363 | case PIPECONF_12BPC: | |
9364 | pipe_config->pipe_bpp = 36; | |
9365 | break; | |
9366 | default: | |
9367 | break; | |
9368 | } | |
9369 | ||
b5a9fa09 DV |
9370 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9371 | pipe_config->limited_color_range = true; | |
9372 | ||
ab9412ba | 9373 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9374 | struct intel_shared_dpll *pll; |
9375 | ||
88adfff1 DV |
9376 | pipe_config->has_pch_encoder = true; |
9377 | ||
627eb5a3 DV |
9378 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9379 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9380 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9381 | |
9382 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9383 | |
c0d43d62 | 9384 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9385 | pipe_config->shared_dpll = |
9386 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9387 | } else { |
9388 | tmp = I915_READ(PCH_DPLL_SEL); | |
9389 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9390 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9391 | else | |
9392 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9393 | } | |
66e985c0 DV |
9394 | |
9395 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9396 | ||
9397 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9398 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9399 | |
9400 | tmp = pipe_config->dpll_hw_state.dpll; | |
9401 | pipe_config->pixel_multiplier = | |
9402 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9403 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9404 | |
9405 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9406 | } else { |
9407 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9408 | } |
9409 | ||
1bd1bd80 DV |
9410 | intel_get_pipe_timings(crtc, pipe_config); |
9411 | ||
2fa2fe9a DV |
9412 | ironlake_get_pfit_config(crtc, pipe_config); |
9413 | ||
0e8ffe1b DV |
9414 | return true; |
9415 | } | |
9416 | ||
be256dc7 PZ |
9417 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9418 | { | |
9419 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9420 | struct intel_crtc *crtc; |
be256dc7 | 9421 | |
d3fcc808 | 9422 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9423 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9424 | pipe_name(crtc->pipe)); |
9425 | ||
e2c719b7 RC |
9426 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9427 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9428 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9429 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9430 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9431 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9432 | "CPU PWM1 enabled\n"); |
c5107b87 | 9433 | if (IS_HASWELL(dev)) |
e2c719b7 | 9434 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9435 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9436 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9437 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9438 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9439 | "Utility pin enabled\n"); |
e2c719b7 | 9440 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9441 | |
9926ada1 PZ |
9442 | /* |
9443 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9444 | * interrupts remain enabled. We used to check for that, but since it's | |
9445 | * gen-specific and since we only disable LCPLL after we fully disable | |
9446 | * the interrupts, the check below should be enough. | |
9447 | */ | |
e2c719b7 | 9448 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9449 | } |
9450 | ||
9ccd5aeb PZ |
9451 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9452 | { | |
9453 | struct drm_device *dev = dev_priv->dev; | |
9454 | ||
9455 | if (IS_HASWELL(dev)) | |
9456 | return I915_READ(D_COMP_HSW); | |
9457 | else | |
9458 | return I915_READ(D_COMP_BDW); | |
9459 | } | |
9460 | ||
3c4c9b81 PZ |
9461 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9462 | { | |
9463 | struct drm_device *dev = dev_priv->dev; | |
9464 | ||
9465 | if (IS_HASWELL(dev)) { | |
9466 | mutex_lock(&dev_priv->rps.hw_lock); | |
9467 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9468 | val)) | |
f475dadf | 9469 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9470 | mutex_unlock(&dev_priv->rps.hw_lock); |
9471 | } else { | |
9ccd5aeb PZ |
9472 | I915_WRITE(D_COMP_BDW, val); |
9473 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9474 | } |
be256dc7 PZ |
9475 | } |
9476 | ||
9477 | /* | |
9478 | * This function implements pieces of two sequences from BSpec: | |
9479 | * - Sequence for display software to disable LCPLL | |
9480 | * - Sequence for display software to allow package C8+ | |
9481 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9482 | * register. Callers should take care of disabling all the display engine | |
9483 | * functions, doing the mode unset, fixing interrupts, etc. | |
9484 | */ | |
6ff58d53 PZ |
9485 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9486 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9487 | { |
9488 | uint32_t val; | |
9489 | ||
9490 | assert_can_disable_lcpll(dev_priv); | |
9491 | ||
9492 | val = I915_READ(LCPLL_CTL); | |
9493 | ||
9494 | if (switch_to_fclk) { | |
9495 | val |= LCPLL_CD_SOURCE_FCLK; | |
9496 | I915_WRITE(LCPLL_CTL, val); | |
9497 | ||
9498 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9499 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9500 | DRM_ERROR("Switching to FCLK failed\n"); | |
9501 | ||
9502 | val = I915_READ(LCPLL_CTL); | |
9503 | } | |
9504 | ||
9505 | val |= LCPLL_PLL_DISABLE; | |
9506 | I915_WRITE(LCPLL_CTL, val); | |
9507 | POSTING_READ(LCPLL_CTL); | |
9508 | ||
9509 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9510 | DRM_ERROR("LCPLL still locked\n"); | |
9511 | ||
9ccd5aeb | 9512 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9513 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9514 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9515 | ndelay(100); |
9516 | ||
9ccd5aeb PZ |
9517 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9518 | 1)) | |
be256dc7 PZ |
9519 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9520 | ||
9521 | if (allow_power_down) { | |
9522 | val = I915_READ(LCPLL_CTL); | |
9523 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9524 | I915_WRITE(LCPLL_CTL, val); | |
9525 | POSTING_READ(LCPLL_CTL); | |
9526 | } | |
9527 | } | |
9528 | ||
9529 | /* | |
9530 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9531 | * source. | |
9532 | */ | |
6ff58d53 | 9533 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9534 | { |
9535 | uint32_t val; | |
9536 | ||
9537 | val = I915_READ(LCPLL_CTL); | |
9538 | ||
9539 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9540 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9541 | return; | |
9542 | ||
a8a8bd54 PZ |
9543 | /* |
9544 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9545 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9546 | */ |
59bad947 | 9547 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9548 | |
be256dc7 PZ |
9549 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9550 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9551 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9552 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9553 | } |
9554 | ||
9ccd5aeb | 9555 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9556 | val |= D_COMP_COMP_FORCE; |
9557 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9558 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9559 | |
9560 | val = I915_READ(LCPLL_CTL); | |
9561 | val &= ~LCPLL_PLL_DISABLE; | |
9562 | I915_WRITE(LCPLL_CTL, val); | |
9563 | ||
9564 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9565 | DRM_ERROR("LCPLL not locked yet\n"); | |
9566 | ||
9567 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9568 | val = I915_READ(LCPLL_CTL); | |
9569 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9570 | I915_WRITE(LCPLL_CTL, val); | |
9571 | ||
9572 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9573 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9574 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9575 | } | |
215733fa | 9576 | |
59bad947 | 9577 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9578 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9579 | } |
9580 | ||
765dab67 PZ |
9581 | /* |
9582 | * Package states C8 and deeper are really deep PC states that can only be | |
9583 | * reached when all the devices on the system allow it, so even if the graphics | |
9584 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9585 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9586 | * | |
9587 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9588 | * well is disabled and most interrupts are disabled, and these are also | |
9589 | * requirements for runtime PM. When these conditions are met, we manually do | |
9590 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9591 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9592 | * hang the machine. | |
9593 | * | |
9594 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9595 | * the state of some registers, so when we come back from PC8+ we need to | |
9596 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9597 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9598 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9599 | * because of the runtime PM support). | |
9600 | * | |
9601 | * For more, read "Display Sequences for Package C8" on the hardware | |
9602 | * documentation. | |
9603 | */ | |
a14cb6fc | 9604 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9605 | { |
c67a470b PZ |
9606 | struct drm_device *dev = dev_priv->dev; |
9607 | uint32_t val; | |
9608 | ||
c67a470b PZ |
9609 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9610 | ||
c2699524 | 9611 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9612 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9613 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9614 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9615 | } | |
9616 | ||
9617 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9618 | hsw_disable_lcpll(dev_priv, true, true); |
9619 | } | |
9620 | ||
a14cb6fc | 9621 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9622 | { |
9623 | struct drm_device *dev = dev_priv->dev; | |
9624 | uint32_t val; | |
9625 | ||
c67a470b PZ |
9626 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9627 | ||
9628 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9629 | lpt_init_pch_refclk(dev); |
9630 | ||
c2699524 | 9631 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9632 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9633 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9634 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9635 | } | |
c67a470b PZ |
9636 | } |
9637 | ||
27c329ed | 9638 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9639 | { |
a821fc46 | 9640 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9641 | struct intel_atomic_state *old_intel_state = |
9642 | to_intel_atomic_state(old_state); | |
9643 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9644 | |
27c329ed | 9645 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9646 | } |
9647 | ||
b432e5cf | 9648 | /* compute the max rate for new configuration */ |
27c329ed | 9649 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9650 | { |
565602d7 ML |
9651 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9652 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9653 | struct drm_crtc *crtc; | |
9654 | struct drm_crtc_state *cstate; | |
27c329ed | 9655 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9656 | unsigned max_pixel_rate = 0, i; |
9657 | enum pipe pipe; | |
b432e5cf | 9658 | |
565602d7 ML |
9659 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9660 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9661 | |
565602d7 ML |
9662 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9663 | int pixel_rate; | |
27c329ed | 9664 | |
565602d7 ML |
9665 | crtc_state = to_intel_crtc_state(cstate); |
9666 | if (!crtc_state->base.enable) { | |
9667 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9668 | continue; |
565602d7 | 9669 | } |
b432e5cf | 9670 | |
27c329ed | 9671 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9672 | |
9673 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9674 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9675 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9676 | ||
565602d7 | 9677 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9678 | } |
9679 | ||
565602d7 ML |
9680 | for_each_pipe(dev_priv, pipe) |
9681 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9682 | ||
b432e5cf VS |
9683 | return max_pixel_rate; |
9684 | } | |
9685 | ||
9686 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9687 | { | |
9688 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9689 | uint32_t val, data; | |
9690 | int ret; | |
9691 | ||
9692 | if (WARN((I915_READ(LCPLL_CTL) & | |
9693 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9694 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9695 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9696 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9697 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9698 | return; | |
9699 | ||
9700 | mutex_lock(&dev_priv->rps.hw_lock); | |
9701 | ret = sandybridge_pcode_write(dev_priv, | |
9702 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9703 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9704 | if (ret) { | |
9705 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9706 | return; | |
9707 | } | |
9708 | ||
9709 | val = I915_READ(LCPLL_CTL); | |
9710 | val |= LCPLL_CD_SOURCE_FCLK; | |
9711 | I915_WRITE(LCPLL_CTL, val); | |
9712 | ||
9713 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9714 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9715 | DRM_ERROR("Switching to FCLK failed\n"); | |
9716 | ||
9717 | val = I915_READ(LCPLL_CTL); | |
9718 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9719 | ||
9720 | switch (cdclk) { | |
9721 | case 450000: | |
9722 | val |= LCPLL_CLK_FREQ_450; | |
9723 | data = 0; | |
9724 | break; | |
9725 | case 540000: | |
9726 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9727 | data = 1; | |
9728 | break; | |
9729 | case 337500: | |
9730 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9731 | data = 2; | |
9732 | break; | |
9733 | case 675000: | |
9734 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9735 | data = 3; | |
9736 | break; | |
9737 | default: | |
9738 | WARN(1, "invalid cdclk frequency\n"); | |
9739 | return; | |
9740 | } | |
9741 | ||
9742 | I915_WRITE(LCPLL_CTL, val); | |
9743 | ||
9744 | val = I915_READ(LCPLL_CTL); | |
9745 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9746 | I915_WRITE(LCPLL_CTL, val); | |
9747 | ||
9748 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9749 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9750 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9751 | ||
9752 | mutex_lock(&dev_priv->rps.hw_lock); | |
9753 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9754 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9755 | ||
9756 | intel_update_cdclk(dev); | |
9757 | ||
9758 | WARN(cdclk != dev_priv->cdclk_freq, | |
9759 | "cdclk requested %d kHz but got %d kHz\n", | |
9760 | cdclk, dev_priv->cdclk_freq); | |
9761 | } | |
9762 | ||
27c329ed | 9763 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9764 | { |
27c329ed | 9765 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9766 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9767 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9768 | int cdclk; |
9769 | ||
9770 | /* | |
9771 | * FIXME should also account for plane ratio | |
9772 | * once 64bpp pixel formats are supported. | |
9773 | */ | |
27c329ed | 9774 | if (max_pixclk > 540000) |
b432e5cf | 9775 | cdclk = 675000; |
27c329ed | 9776 | else if (max_pixclk > 450000) |
b432e5cf | 9777 | cdclk = 540000; |
27c329ed | 9778 | else if (max_pixclk > 337500) |
b432e5cf VS |
9779 | cdclk = 450000; |
9780 | else | |
9781 | cdclk = 337500; | |
9782 | ||
b432e5cf | 9783 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9784 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9785 | cdclk, dev_priv->max_cdclk_freq); | |
9786 | return -EINVAL; | |
b432e5cf VS |
9787 | } |
9788 | ||
1a617b77 ML |
9789 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9790 | if (!intel_state->active_crtcs) | |
9791 | intel_state->dev_cdclk = 337500; | |
b432e5cf VS |
9792 | |
9793 | return 0; | |
9794 | } | |
9795 | ||
27c329ed | 9796 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9797 | { |
27c329ed | 9798 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9799 | struct intel_atomic_state *old_intel_state = |
9800 | to_intel_atomic_state(old_state); | |
9801 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9802 | |
27c329ed | 9803 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9804 | } |
9805 | ||
190f68c5 ACO |
9806 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9807 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9808 | { |
af3997b5 MK |
9809 | struct intel_encoder *intel_encoder = |
9810 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9811 | ||
9812 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | |
9813 | if (!intel_ddi_pll_select(crtc, crtc_state)) | |
9814 | return -EINVAL; | |
9815 | } | |
716c2e55 | 9816 | |
c7653199 | 9817 | crtc->lowfreq_avail = false; |
644cef34 | 9818 | |
c8f7a0db | 9819 | return 0; |
79e53945 JB |
9820 | } |
9821 | ||
3760b59c S |
9822 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9823 | enum port port, | |
9824 | struct intel_crtc_state *pipe_config) | |
9825 | { | |
9826 | switch (port) { | |
9827 | case PORT_A: | |
9828 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9829 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9830 | break; | |
9831 | case PORT_B: | |
9832 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9833 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9834 | break; | |
9835 | case PORT_C: | |
9836 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9837 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9838 | break; | |
9839 | default: | |
9840 | DRM_ERROR("Incorrect port type\n"); | |
9841 | } | |
9842 | } | |
9843 | ||
96b7dfb7 S |
9844 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9845 | enum port port, | |
5cec258b | 9846 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9847 | { |
3148ade7 | 9848 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9849 | |
9850 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9851 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9852 | ||
9853 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9854 | case SKL_DPLL0: |
9855 | /* | |
9856 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9857 | * of the shared DPLL framework and thus needs to be read out | |
9858 | * separately | |
9859 | */ | |
9860 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9861 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9862 | break; | |
96b7dfb7 S |
9863 | case SKL_DPLL1: |
9864 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9865 | break; | |
9866 | case SKL_DPLL2: | |
9867 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9868 | break; | |
9869 | case SKL_DPLL3: | |
9870 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9871 | break; | |
96b7dfb7 S |
9872 | } |
9873 | } | |
9874 | ||
7d2c8175 DL |
9875 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9876 | enum port port, | |
5cec258b | 9877 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9878 | { |
9879 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9880 | ||
9881 | switch (pipe_config->ddi_pll_sel) { | |
9882 | case PORT_CLK_SEL_WRPLL1: | |
9883 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9884 | break; | |
9885 | case PORT_CLK_SEL_WRPLL2: | |
9886 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9887 | break; | |
00490c22 ML |
9888 | case PORT_CLK_SEL_SPLL: |
9889 | pipe_config->shared_dpll = DPLL_ID_SPLL; | |
79bd23da | 9890 | break; |
7d2c8175 DL |
9891 | } |
9892 | } | |
9893 | ||
26804afd | 9894 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9895 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9896 | { |
9897 | struct drm_device *dev = crtc->base.dev; | |
9898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9899 | struct intel_shared_dpll *pll; |
26804afd DV |
9900 | enum port port; |
9901 | uint32_t tmp; | |
9902 | ||
9903 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9904 | ||
9905 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9906 | ||
ef11bdb3 | 9907 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9908 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9909 | else if (IS_BROXTON(dev)) |
9910 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9911 | else |
9912 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9913 | |
d452c5b6 DV |
9914 | if (pipe_config->shared_dpll >= 0) { |
9915 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9916 | ||
9917 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9918 | &pipe_config->dpll_hw_state)); | |
9919 | } | |
9920 | ||
26804afd DV |
9921 | /* |
9922 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9923 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9924 | * the PCH transcoder is on. | |
9925 | */ | |
ca370455 DL |
9926 | if (INTEL_INFO(dev)->gen < 9 && |
9927 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9928 | pipe_config->has_pch_encoder = true; |
9929 | ||
9930 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9931 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9932 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9933 | ||
9934 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9935 | } | |
9936 | } | |
9937 | ||
0e8ffe1b | 9938 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9939 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9940 | { |
9941 | struct drm_device *dev = crtc->base.dev; | |
9942 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9943 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9944 | uint32_t tmp; |
9945 | ||
f458ebbc | 9946 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9947 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9948 | return false; | |
9949 | ||
e143a21c | 9950 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9951 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9952 | ||
eccb140b DV |
9953 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9954 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9955 | enum pipe trans_edp_pipe; | |
9956 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9957 | default: | |
9958 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9959 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9960 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9961 | trans_edp_pipe = PIPE_A; | |
9962 | break; | |
9963 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9964 | trans_edp_pipe = PIPE_B; | |
9965 | break; | |
9966 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9967 | trans_edp_pipe = PIPE_C; | |
9968 | break; | |
9969 | } | |
9970 | ||
9971 | if (trans_edp_pipe == crtc->pipe) | |
9972 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9973 | } | |
9974 | ||
f458ebbc | 9975 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9976 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9977 | return false; |
9978 | ||
eccb140b | 9979 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9980 | if (!(tmp & PIPECONF_ENABLE)) |
9981 | return false; | |
9982 | ||
26804afd | 9983 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9984 | |
1bd1bd80 DV |
9985 | intel_get_pipe_timings(crtc, pipe_config); |
9986 | ||
a1b2278e CK |
9987 | if (INTEL_INFO(dev)->gen >= 9) { |
9988 | skl_init_scalers(dev, crtc, pipe_config); | |
9989 | } | |
9990 | ||
2fa2fe9a | 9991 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
9992 | |
9993 | if (INTEL_INFO(dev)->gen >= 9) { | |
9994 | pipe_config->scaler_state.scaler_id = -1; | |
9995 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9996 | } | |
9997 | ||
bd2e244f | 9998 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
1c132b44 | 9999 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10000 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10001 | else |
1c132b44 | 10002 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10003 | } |
88adfff1 | 10004 | |
e59150dc JB |
10005 | if (IS_HASWELL(dev)) |
10006 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10007 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10008 | |
ebb69c95 CT |
10009 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
10010 | pipe_config->pixel_multiplier = | |
10011 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10012 | } else { | |
10013 | pipe_config->pixel_multiplier = 1; | |
10014 | } | |
6c49f241 | 10015 | |
0e8ffe1b DV |
10016 | return true; |
10017 | } | |
10018 | ||
55a08b3f ML |
10019 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10020 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10021 | { |
10022 | struct drm_device *dev = crtc->dev; | |
10023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10024 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10025 | uint32_t cntl = 0, size = 0; |
560b85bb | 10026 | |
55a08b3f ML |
10027 | if (plane_state && plane_state->visible) { |
10028 | unsigned int width = plane_state->base.crtc_w; | |
10029 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10030 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10031 | ||
10032 | switch (stride) { | |
10033 | default: | |
10034 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10035 | width, stride); | |
10036 | stride = 256; | |
10037 | /* fallthrough */ | |
10038 | case 256: | |
10039 | case 512: | |
10040 | case 1024: | |
10041 | case 2048: | |
10042 | break; | |
4b0e333e CW |
10043 | } |
10044 | ||
dc41c154 VS |
10045 | cntl |= CURSOR_ENABLE | |
10046 | CURSOR_GAMMA_ENABLE | | |
10047 | CURSOR_FORMAT_ARGB | | |
10048 | CURSOR_STRIDE(stride); | |
10049 | ||
10050 | size = (height << 12) | width; | |
4b0e333e | 10051 | } |
560b85bb | 10052 | |
dc41c154 VS |
10053 | if (intel_crtc->cursor_cntl != 0 && |
10054 | (intel_crtc->cursor_base != base || | |
10055 | intel_crtc->cursor_size != size || | |
10056 | intel_crtc->cursor_cntl != cntl)) { | |
10057 | /* On these chipsets we can only modify the base/size/stride | |
10058 | * whilst the cursor is disabled. | |
10059 | */ | |
0b87c24e VS |
10060 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10061 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10062 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10063 | } |
560b85bb | 10064 | |
99d1f387 | 10065 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10066 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10067 | intel_crtc->cursor_base = base; |
10068 | } | |
4726e0b0 | 10069 | |
dc41c154 VS |
10070 | if (intel_crtc->cursor_size != size) { |
10071 | I915_WRITE(CURSIZE, size); | |
10072 | intel_crtc->cursor_size = size; | |
4b0e333e | 10073 | } |
560b85bb | 10074 | |
4b0e333e | 10075 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10076 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10077 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10078 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10079 | } |
560b85bb CW |
10080 | } |
10081 | ||
55a08b3f ML |
10082 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10083 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10084 | { |
10085 | struct drm_device *dev = crtc->dev; | |
10086 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10087 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10088 | int pipe = intel_crtc->pipe; | |
663f3122 | 10089 | uint32_t cntl = 0; |
4b0e333e | 10090 | |
55a08b3f | 10091 | if (plane_state && plane_state->visible) { |
4b0e333e | 10092 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10093 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10094 | case 64: |
10095 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10096 | break; | |
10097 | case 128: | |
10098 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10099 | break; | |
10100 | case 256: | |
10101 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10102 | break; | |
10103 | default: | |
55a08b3f | 10104 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10105 | return; |
65a21cd6 | 10106 | } |
4b0e333e | 10107 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10108 | |
fc6f93bc | 10109 | if (HAS_DDI(dev)) |
47bf17a7 | 10110 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10111 | |
55a08b3f ML |
10112 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10113 | cntl |= CURSOR_ROTATE_180; | |
10114 | } | |
4398ad45 | 10115 | |
4b0e333e CW |
10116 | if (intel_crtc->cursor_cntl != cntl) { |
10117 | I915_WRITE(CURCNTR(pipe), cntl); | |
10118 | POSTING_READ(CURCNTR(pipe)); | |
10119 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10120 | } |
4b0e333e | 10121 | |
65a21cd6 | 10122 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10123 | I915_WRITE(CURBASE(pipe), base); |
10124 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10125 | |
10126 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10127 | } |
10128 | ||
cda4b7d3 | 10129 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10130 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10131 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10132 | { |
10133 | struct drm_device *dev = crtc->dev; | |
10134 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10135 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10136 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10137 | u32 base = intel_crtc->cursor_addr; |
10138 | u32 pos = 0; | |
cda4b7d3 | 10139 | |
55a08b3f ML |
10140 | if (plane_state) { |
10141 | int x = plane_state->base.crtc_x; | |
10142 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10143 | |
55a08b3f ML |
10144 | if (x < 0) { |
10145 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10146 | x = -x; | |
10147 | } | |
10148 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10149 | |
55a08b3f ML |
10150 | if (y < 0) { |
10151 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10152 | y = -y; | |
10153 | } | |
10154 | pos |= y << CURSOR_Y_SHIFT; | |
10155 | ||
10156 | /* ILK+ do this automagically */ | |
10157 | if (HAS_GMCH_DISPLAY(dev) && | |
10158 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10159 | base += (plane_state->base.crtc_h * | |
10160 | plane_state->base.crtc_w - 1) * 4; | |
10161 | } | |
cda4b7d3 | 10162 | } |
cda4b7d3 | 10163 | |
5efb3e28 VS |
10164 | I915_WRITE(CURPOS(pipe), pos); |
10165 | ||
8ac54669 | 10166 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10167 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10168 | else |
55a08b3f | 10169 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10170 | } |
10171 | ||
dc41c154 VS |
10172 | static bool cursor_size_ok(struct drm_device *dev, |
10173 | uint32_t width, uint32_t height) | |
10174 | { | |
10175 | if (width == 0 || height == 0) | |
10176 | return false; | |
10177 | ||
10178 | /* | |
10179 | * 845g/865g are special in that they are only limited by | |
10180 | * the width of their cursors, the height is arbitrary up to | |
10181 | * the precision of the register. Everything else requires | |
10182 | * square cursors, limited to a few power-of-two sizes. | |
10183 | */ | |
10184 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10185 | if ((width & 63) != 0) | |
10186 | return false; | |
10187 | ||
10188 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10189 | return false; | |
10190 | ||
10191 | if (height > 1023) | |
10192 | return false; | |
10193 | } else { | |
10194 | switch (width | height) { | |
10195 | case 256: | |
10196 | case 128: | |
10197 | if (IS_GEN2(dev)) | |
10198 | return false; | |
10199 | case 64: | |
10200 | break; | |
10201 | default: | |
10202 | return false; | |
10203 | } | |
10204 | } | |
10205 | ||
10206 | return true; | |
10207 | } | |
10208 | ||
79e53945 | 10209 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10210 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10211 | { |
7203425a | 10212 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10213 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10214 | |
7203425a | 10215 | for (i = start; i < end; i++) { |
79e53945 JB |
10216 | intel_crtc->lut_r[i] = red[i] >> 8; |
10217 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10218 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10219 | } | |
10220 | ||
10221 | intel_crtc_load_lut(crtc); | |
10222 | } | |
10223 | ||
79e53945 JB |
10224 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10225 | static struct drm_display_mode load_detect_mode = { | |
10226 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10227 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10228 | }; | |
10229 | ||
a8bb6818 DV |
10230 | struct drm_framebuffer * |
10231 | __intel_framebuffer_create(struct drm_device *dev, | |
10232 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10233 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10234 | { |
10235 | struct intel_framebuffer *intel_fb; | |
10236 | int ret; | |
10237 | ||
10238 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10239 | if (!intel_fb) |
d2dff872 | 10240 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10241 | |
10242 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10243 | if (ret) |
10244 | goto err; | |
d2dff872 CW |
10245 | |
10246 | return &intel_fb->base; | |
dcb1394e | 10247 | |
dd4916c5 | 10248 | err: |
dd4916c5 | 10249 | kfree(intel_fb); |
dd4916c5 | 10250 | return ERR_PTR(ret); |
d2dff872 CW |
10251 | } |
10252 | ||
b5ea642a | 10253 | static struct drm_framebuffer * |
a8bb6818 DV |
10254 | intel_framebuffer_create(struct drm_device *dev, |
10255 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10256 | struct drm_i915_gem_object *obj) | |
10257 | { | |
10258 | struct drm_framebuffer *fb; | |
10259 | int ret; | |
10260 | ||
10261 | ret = i915_mutex_lock_interruptible(dev); | |
10262 | if (ret) | |
10263 | return ERR_PTR(ret); | |
10264 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10265 | mutex_unlock(&dev->struct_mutex); | |
10266 | ||
10267 | return fb; | |
10268 | } | |
10269 | ||
d2dff872 CW |
10270 | static u32 |
10271 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10272 | { | |
10273 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10274 | return ALIGN(pitch, 64); | |
10275 | } | |
10276 | ||
10277 | static u32 | |
10278 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10279 | { | |
10280 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10281 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10282 | } |
10283 | ||
10284 | static struct drm_framebuffer * | |
10285 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10286 | struct drm_display_mode *mode, | |
10287 | int depth, int bpp) | |
10288 | { | |
dcb1394e | 10289 | struct drm_framebuffer *fb; |
d2dff872 | 10290 | struct drm_i915_gem_object *obj; |
0fed39bd | 10291 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10292 | |
10293 | obj = i915_gem_alloc_object(dev, | |
10294 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10295 | if (obj == NULL) | |
10296 | return ERR_PTR(-ENOMEM); | |
10297 | ||
10298 | mode_cmd.width = mode->hdisplay; | |
10299 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10300 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10301 | bpp); | |
5ca0c34a | 10302 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10303 | |
dcb1394e LW |
10304 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10305 | if (IS_ERR(fb)) | |
10306 | drm_gem_object_unreference_unlocked(&obj->base); | |
10307 | ||
10308 | return fb; | |
d2dff872 CW |
10309 | } |
10310 | ||
10311 | static struct drm_framebuffer * | |
10312 | mode_fits_in_fbdev(struct drm_device *dev, | |
10313 | struct drm_display_mode *mode) | |
10314 | { | |
0695726e | 10315 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10316 | struct drm_i915_private *dev_priv = dev->dev_private; |
10317 | struct drm_i915_gem_object *obj; | |
10318 | struct drm_framebuffer *fb; | |
10319 | ||
4c0e5528 | 10320 | if (!dev_priv->fbdev) |
d2dff872 CW |
10321 | return NULL; |
10322 | ||
4c0e5528 | 10323 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10324 | return NULL; |
10325 | ||
4c0e5528 DV |
10326 | obj = dev_priv->fbdev->fb->obj; |
10327 | BUG_ON(!obj); | |
10328 | ||
8bcd4553 | 10329 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10330 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10331 | fb->bits_per_pixel)) | |
d2dff872 CW |
10332 | return NULL; |
10333 | ||
01f2c773 | 10334 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10335 | return NULL; |
10336 | ||
10337 | return fb; | |
4520f53a DV |
10338 | #else |
10339 | return NULL; | |
10340 | #endif | |
d2dff872 CW |
10341 | } |
10342 | ||
d3a40d1b ACO |
10343 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10344 | struct drm_crtc *crtc, | |
10345 | struct drm_display_mode *mode, | |
10346 | struct drm_framebuffer *fb, | |
10347 | int x, int y) | |
10348 | { | |
10349 | struct drm_plane_state *plane_state; | |
10350 | int hdisplay, vdisplay; | |
10351 | int ret; | |
10352 | ||
10353 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10354 | if (IS_ERR(plane_state)) | |
10355 | return PTR_ERR(plane_state); | |
10356 | ||
10357 | if (mode) | |
10358 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10359 | else | |
10360 | hdisplay = vdisplay = 0; | |
10361 | ||
10362 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10363 | if (ret) | |
10364 | return ret; | |
10365 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10366 | plane_state->crtc_x = 0; | |
10367 | plane_state->crtc_y = 0; | |
10368 | plane_state->crtc_w = hdisplay; | |
10369 | plane_state->crtc_h = vdisplay; | |
10370 | plane_state->src_x = x << 16; | |
10371 | plane_state->src_y = y << 16; | |
10372 | plane_state->src_w = hdisplay << 16; | |
10373 | plane_state->src_h = vdisplay << 16; | |
10374 | ||
10375 | return 0; | |
10376 | } | |
10377 | ||
d2434ab7 | 10378 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10379 | struct drm_display_mode *mode, |
51fd371b RC |
10380 | struct intel_load_detect_pipe *old, |
10381 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10382 | { |
10383 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10384 | struct intel_encoder *intel_encoder = |
10385 | intel_attached_encoder(connector); | |
79e53945 | 10386 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10387 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10388 | struct drm_crtc *crtc = NULL; |
10389 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10390 | struct drm_framebuffer *fb; |
51fd371b | 10391 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 10392 | struct drm_atomic_state *state = NULL; |
944b0c76 | 10393 | struct drm_connector_state *connector_state; |
4be07317 | 10394 | struct intel_crtc_state *crtc_state; |
51fd371b | 10395 | int ret, i = -1; |
79e53945 | 10396 | |
d2dff872 | 10397 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10398 | connector->base.id, connector->name, |
8e329a03 | 10399 | encoder->base.id, encoder->name); |
d2dff872 | 10400 | |
51fd371b RC |
10401 | retry: |
10402 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10403 | if (ret) | |
ad3c558f | 10404 | goto fail; |
6e9f798d | 10405 | |
79e53945 JB |
10406 | /* |
10407 | * Algorithm gets a little messy: | |
7a5e4805 | 10408 | * |
79e53945 JB |
10409 | * - if the connector already has an assigned crtc, use it (but make |
10410 | * sure it's on first) | |
7a5e4805 | 10411 | * |
79e53945 JB |
10412 | * - try to find the first unused crtc that can drive this connector, |
10413 | * and use that if we find one | |
79e53945 JB |
10414 | */ |
10415 | ||
10416 | /* See if we already have a CRTC for this connector */ | |
10417 | if (encoder->crtc) { | |
10418 | crtc = encoder->crtc; | |
8261b191 | 10419 | |
51fd371b | 10420 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10421 | if (ret) |
ad3c558f | 10422 | goto fail; |
4d02e2de | 10423 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
51fd371b | 10424 | if (ret) |
ad3c558f | 10425 | goto fail; |
7b24056b | 10426 | |
24218aac | 10427 | old->dpms_mode = connector->dpms; |
8261b191 CW |
10428 | old->load_detect_temp = false; |
10429 | ||
10430 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
10431 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10432 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 10433 | |
7173188d | 10434 | return true; |
79e53945 JB |
10435 | } |
10436 | ||
10437 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10438 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10439 | i++; |
10440 | if (!(encoder->possible_crtcs & (1 << i))) | |
10441 | continue; | |
83d65738 | 10442 | if (possible_crtc->state->enable) |
a459249c | 10443 | continue; |
a459249c VS |
10444 | |
10445 | crtc = possible_crtc; | |
10446 | break; | |
79e53945 JB |
10447 | } |
10448 | ||
10449 | /* | |
10450 | * If we didn't find an unused CRTC, don't use any. | |
10451 | */ | |
10452 | if (!crtc) { | |
7173188d | 10453 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10454 | goto fail; |
79e53945 JB |
10455 | } |
10456 | ||
51fd371b RC |
10457 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10458 | if (ret) | |
ad3c558f | 10459 | goto fail; |
4d02e2de DV |
10460 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10461 | if (ret) | |
ad3c558f | 10462 | goto fail; |
79e53945 JB |
10463 | |
10464 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 10465 | old->dpms_mode = connector->dpms; |
8261b191 | 10466 | old->load_detect_temp = true; |
d2dff872 | 10467 | old->release_fb = NULL; |
79e53945 | 10468 | |
83a57153 ACO |
10469 | state = drm_atomic_state_alloc(dev); |
10470 | if (!state) | |
10471 | return false; | |
10472 | ||
10473 | state->acquire_ctx = ctx; | |
10474 | ||
944b0c76 ACO |
10475 | connector_state = drm_atomic_get_connector_state(state, connector); |
10476 | if (IS_ERR(connector_state)) { | |
10477 | ret = PTR_ERR(connector_state); | |
10478 | goto fail; | |
10479 | } | |
10480 | ||
10481 | connector_state->crtc = crtc; | |
944b0c76 | 10482 | |
4be07317 ACO |
10483 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10484 | if (IS_ERR(crtc_state)) { | |
10485 | ret = PTR_ERR(crtc_state); | |
10486 | goto fail; | |
10487 | } | |
10488 | ||
49d6fa21 | 10489 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10490 | |
6492711d CW |
10491 | if (!mode) |
10492 | mode = &load_detect_mode; | |
79e53945 | 10493 | |
d2dff872 CW |
10494 | /* We need a framebuffer large enough to accommodate all accesses |
10495 | * that the plane may generate whilst we perform load detection. | |
10496 | * We can not rely on the fbcon either being present (we get called | |
10497 | * during its initialisation to detect all boot displays, or it may | |
10498 | * not even exist) or that it is large enough to satisfy the | |
10499 | * requested mode. | |
10500 | */ | |
94352cf9 DV |
10501 | fb = mode_fits_in_fbdev(dev, mode); |
10502 | if (fb == NULL) { | |
d2dff872 | 10503 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
10504 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10505 | old->release_fb = fb; | |
d2dff872 CW |
10506 | } else |
10507 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10508 | if (IS_ERR(fb)) { |
d2dff872 | 10509 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10510 | goto fail; |
79e53945 | 10511 | } |
79e53945 | 10512 | |
d3a40d1b ACO |
10513 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10514 | if (ret) | |
10515 | goto fail; | |
10516 | ||
8c7b5ccb ACO |
10517 | drm_mode_copy(&crtc_state->base.mode, mode); |
10518 | ||
74c090b1 | 10519 | if (drm_atomic_commit(state)) { |
6492711d | 10520 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
10521 | if (old->release_fb) |
10522 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 10523 | goto fail; |
79e53945 | 10524 | } |
9128b040 | 10525 | crtc->primary->crtc = crtc; |
7173188d | 10526 | |
79e53945 | 10527 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10528 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10529 | return true; |
412b61d8 | 10530 | |
ad3c558f | 10531 | fail: |
e5d958ef ACO |
10532 | drm_atomic_state_free(state); |
10533 | state = NULL; | |
83a57153 | 10534 | |
51fd371b RC |
10535 | if (ret == -EDEADLK) { |
10536 | drm_modeset_backoff(ctx); | |
10537 | goto retry; | |
10538 | } | |
10539 | ||
412b61d8 | 10540 | return false; |
79e53945 JB |
10541 | } |
10542 | ||
d2434ab7 | 10543 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10544 | struct intel_load_detect_pipe *old, |
10545 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10546 | { |
83a57153 | 10547 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
10548 | struct intel_encoder *intel_encoder = |
10549 | intel_attached_encoder(connector); | |
4ef69c7a | 10550 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 10551 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 10552 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 10553 | struct drm_atomic_state *state; |
944b0c76 | 10554 | struct drm_connector_state *connector_state; |
4be07317 | 10555 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 10556 | int ret; |
79e53945 | 10557 | |
d2dff872 | 10558 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10559 | connector->base.id, connector->name, |
8e329a03 | 10560 | encoder->base.id, encoder->name); |
d2dff872 | 10561 | |
8261b191 | 10562 | if (old->load_detect_temp) { |
83a57153 | 10563 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
10564 | if (!state) |
10565 | goto fail; | |
83a57153 ACO |
10566 | |
10567 | state->acquire_ctx = ctx; | |
10568 | ||
944b0c76 ACO |
10569 | connector_state = drm_atomic_get_connector_state(state, connector); |
10570 | if (IS_ERR(connector_state)) | |
10571 | goto fail; | |
10572 | ||
4be07317 ACO |
10573 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10574 | if (IS_ERR(crtc_state)) | |
10575 | goto fail; | |
10576 | ||
944b0c76 ACO |
10577 | connector_state->crtc = NULL; |
10578 | ||
49d6fa21 | 10579 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 10580 | |
d3a40d1b ACO |
10581 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
10582 | 0, 0); | |
10583 | if (ret) | |
10584 | goto fail; | |
10585 | ||
74c090b1 | 10586 | ret = drm_atomic_commit(state); |
2bfb4627 ACO |
10587 | if (ret) |
10588 | goto fail; | |
d2dff872 | 10589 | |
36206361 DV |
10590 | if (old->release_fb) { |
10591 | drm_framebuffer_unregister_private(old->release_fb); | |
10592 | drm_framebuffer_unreference(old->release_fb); | |
10593 | } | |
d2dff872 | 10594 | |
0622a53c | 10595 | return; |
79e53945 JB |
10596 | } |
10597 | ||
c751ce4f | 10598 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
10599 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
10600 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
10601 | |
10602 | return; | |
10603 | fail: | |
10604 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
10605 | drm_atomic_state_free(state); | |
79e53945 JB |
10606 | } |
10607 | ||
da4a1efa | 10608 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10609 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10610 | { |
10611 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10612 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10613 | ||
10614 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10615 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10616 | else if (HAS_PCH_SPLIT(dev)) |
10617 | return 120000; | |
10618 | else if (!IS_GEN2(dev)) | |
10619 | return 96000; | |
10620 | else | |
10621 | return 48000; | |
10622 | } | |
10623 | ||
79e53945 | 10624 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10625 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10626 | struct intel_crtc_state *pipe_config) |
79e53945 | 10627 | { |
f1f644dc | 10628 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10629 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10630 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10631 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10632 | u32 fp; |
10633 | intel_clock_t clock; | |
dccbea3b | 10634 | int port_clock; |
da4a1efa | 10635 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10636 | |
10637 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10638 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10639 | else |
293623f7 | 10640 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10641 | |
10642 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10643 | if (IS_PINEVIEW(dev)) { |
10644 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10645 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10646 | } else { |
10647 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10648 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10649 | } | |
10650 | ||
a6c45cf0 | 10651 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10652 | if (IS_PINEVIEW(dev)) |
10653 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10654 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10655 | else |
10656 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10657 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10658 | ||
10659 | switch (dpll & DPLL_MODE_MASK) { | |
10660 | case DPLLB_MODE_DAC_SERIAL: | |
10661 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10662 | 5 : 10; | |
10663 | break; | |
10664 | case DPLLB_MODE_LVDS: | |
10665 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10666 | 7 : 14; | |
10667 | break; | |
10668 | default: | |
28c97730 | 10669 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10670 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10671 | return; |
79e53945 JB |
10672 | } |
10673 | ||
ac58c3f0 | 10674 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10675 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10676 | else |
dccbea3b | 10677 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10678 | } else { |
0fb58223 | 10679 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10680 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10681 | |
10682 | if (is_lvds) { | |
10683 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10684 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10685 | |
10686 | if (lvds & LVDS_CLKB_POWER_UP) | |
10687 | clock.p2 = 7; | |
10688 | else | |
10689 | clock.p2 = 14; | |
79e53945 JB |
10690 | } else { |
10691 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10692 | clock.p1 = 2; | |
10693 | else { | |
10694 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10695 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10696 | } | |
10697 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10698 | clock.p2 = 4; | |
10699 | else | |
10700 | clock.p2 = 2; | |
79e53945 | 10701 | } |
da4a1efa | 10702 | |
dccbea3b | 10703 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10704 | } |
10705 | ||
18442d08 VS |
10706 | /* |
10707 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10708 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10709 | * encoder's get_config() function. |
10710 | */ | |
dccbea3b | 10711 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10712 | } |
10713 | ||
6878da05 VS |
10714 | int intel_dotclock_calculate(int link_freq, |
10715 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10716 | { |
f1f644dc JB |
10717 | /* |
10718 | * The calculation for the data clock is: | |
1041a02f | 10719 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10720 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10721 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10722 | * |
10723 | * and the link clock is simpler: | |
1041a02f | 10724 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10725 | */ |
10726 | ||
6878da05 VS |
10727 | if (!m_n->link_n) |
10728 | return 0; | |
f1f644dc | 10729 | |
6878da05 VS |
10730 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10731 | } | |
f1f644dc | 10732 | |
18442d08 | 10733 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10734 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10735 | { |
10736 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10737 | |
18442d08 VS |
10738 | /* read out port_clock from the DPLL */ |
10739 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10740 | |
f1f644dc | 10741 | /* |
18442d08 | 10742 | * This value does not include pixel_multiplier. |
241bfc38 | 10743 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10744 | * agree once we know their relationship in the encoder's |
10745 | * get_config() function. | |
79e53945 | 10746 | */ |
2d112de7 | 10747 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10748 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10749 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10750 | } |
10751 | ||
10752 | /** Returns the currently programmed mode of the given pipe. */ | |
10753 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10754 | struct drm_crtc *crtc) | |
10755 | { | |
548f245b | 10756 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10757 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10758 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10759 | struct drm_display_mode *mode; |
3f36b937 | 10760 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10761 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10762 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10763 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10764 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10765 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10766 | |
10767 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10768 | if (!mode) | |
10769 | return NULL; | |
10770 | ||
3f36b937 TU |
10771 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10772 | if (!pipe_config) { | |
10773 | kfree(mode); | |
10774 | return NULL; | |
10775 | } | |
10776 | ||
f1f644dc JB |
10777 | /* |
10778 | * Construct a pipe_config sufficient for getting the clock info | |
10779 | * back out of crtc_clock_get. | |
10780 | * | |
10781 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10782 | * to use a real value here instead. | |
10783 | */ | |
3f36b937 TU |
10784 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10785 | pipe_config->pixel_multiplier = 1; | |
10786 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10787 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10788 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10789 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10790 | ||
10791 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10792 | mode->hdisplay = (htot & 0xffff) + 1; |
10793 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10794 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10795 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10796 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10797 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10798 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10799 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10800 | ||
10801 | drm_mode_set_name(mode); | |
79e53945 | 10802 | |
3f36b937 TU |
10803 | kfree(pipe_config); |
10804 | ||
79e53945 JB |
10805 | return mode; |
10806 | } | |
10807 | ||
f047e395 CW |
10808 | void intel_mark_busy(struct drm_device *dev) |
10809 | { | |
c67a470b PZ |
10810 | struct drm_i915_private *dev_priv = dev->dev_private; |
10811 | ||
f62a0076 CW |
10812 | if (dev_priv->mm.busy) |
10813 | return; | |
10814 | ||
43694d69 | 10815 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10816 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10817 | if (INTEL_INFO(dev)->gen >= 6) |
10818 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10819 | dev_priv->mm.busy = true; |
f047e395 CW |
10820 | } |
10821 | ||
10822 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10823 | { |
c67a470b | 10824 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10825 | |
f62a0076 CW |
10826 | if (!dev_priv->mm.busy) |
10827 | return; | |
10828 | ||
10829 | dev_priv->mm.busy = false; | |
10830 | ||
3d13ef2e | 10831 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10832 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10833 | |
43694d69 | 10834 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10835 | } |
10836 | ||
79e53945 JB |
10837 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10838 | { | |
10839 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10840 | struct drm_device *dev = crtc->dev; |
10841 | struct intel_unpin_work *work; | |
67e77c5a | 10842 | |
5e2d7afc | 10843 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10844 | work = intel_crtc->unpin_work; |
10845 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10846 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10847 | |
10848 | if (work) { | |
10849 | cancel_work_sync(&work->work); | |
10850 | kfree(work); | |
10851 | } | |
79e53945 JB |
10852 | |
10853 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10854 | |
79e53945 JB |
10855 | kfree(intel_crtc); |
10856 | } | |
10857 | ||
6b95a207 KH |
10858 | static void intel_unpin_work_fn(struct work_struct *__work) |
10859 | { | |
10860 | struct intel_unpin_work *work = | |
10861 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10862 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10863 | struct drm_device *dev = crtc->base.dev; | |
10864 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10865 | |
b4a98e57 | 10866 | mutex_lock(&dev->struct_mutex); |
a9ff8714 | 10867 | intel_unpin_fb_obj(work->old_fb, primary->state); |
05394f39 | 10868 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10869 | |
f06cc1b9 | 10870 | if (work->flip_queued_req) |
146d84f0 | 10871 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10872 | mutex_unlock(&dev->struct_mutex); |
10873 | ||
a9ff8714 | 10874 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
1eb52238 | 10875 | intel_fbc_post_update(crtc); |
89ed88ba | 10876 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10877 | |
a9ff8714 VS |
10878 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10879 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10880 | |
6b95a207 KH |
10881 | kfree(work); |
10882 | } | |
10883 | ||
1afe3e9d | 10884 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10885 | struct drm_crtc *crtc) |
6b95a207 | 10886 | { |
6b95a207 KH |
10887 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10888 | struct intel_unpin_work *work; | |
6b95a207 KH |
10889 | unsigned long flags; |
10890 | ||
10891 | /* Ignore early vblank irqs */ | |
10892 | if (intel_crtc == NULL) | |
10893 | return; | |
10894 | ||
f326038a DV |
10895 | /* |
10896 | * This is called both by irq handlers and the reset code (to complete | |
10897 | * lost pageflips) so needs the full irqsave spinlocks. | |
10898 | */ | |
6b95a207 KH |
10899 | spin_lock_irqsave(&dev->event_lock, flags); |
10900 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10901 | |
10902 | /* Ensure we don't miss a work->pending update ... */ | |
10903 | smp_rmb(); | |
10904 | ||
10905 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10906 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10907 | return; | |
10908 | } | |
10909 | ||
d6bbafa1 | 10910 | page_flip_completed(intel_crtc); |
0af7e4df | 10911 | |
6b95a207 | 10912 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10913 | } |
10914 | ||
1afe3e9d JB |
10915 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10916 | { | |
fbee40df | 10917 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10918 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10919 | ||
49b14a5c | 10920 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10921 | } |
10922 | ||
10923 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10924 | { | |
fbee40df | 10925 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10926 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10927 | ||
49b14a5c | 10928 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10929 | } |
10930 | ||
75f7f3ec VS |
10931 | /* Is 'a' after or equal to 'b'? */ |
10932 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10933 | { | |
10934 | return !((a - b) & 0x80000000); | |
10935 | } | |
10936 | ||
10937 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10938 | { | |
10939 | struct drm_device *dev = crtc->base.dev; | |
10940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10941 | ||
bdfa7542 VS |
10942 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10943 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10944 | return true; | |
10945 | ||
75f7f3ec VS |
10946 | /* |
10947 | * The relevant registers doen't exist on pre-ctg. | |
10948 | * As the flip done interrupt doesn't trigger for mmio | |
10949 | * flips on gmch platforms, a flip count check isn't | |
10950 | * really needed there. But since ctg has the registers, | |
10951 | * include it in the check anyway. | |
10952 | */ | |
10953 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10954 | return true; | |
10955 | ||
10956 | /* | |
10957 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10958 | * used the same base address. In that case the mmio flip might | |
10959 | * have completed, but the CS hasn't even executed the flip yet. | |
10960 | * | |
10961 | * A flip count check isn't enough as the CS might have updated | |
10962 | * the base address just after start of vblank, but before we | |
10963 | * managed to process the interrupt. This means we'd complete the | |
10964 | * CS flip too soon. | |
10965 | * | |
10966 | * Combining both checks should get us a good enough result. It may | |
10967 | * still happen that the CS flip has been executed, but has not | |
10968 | * yet actually completed. But in case the base address is the same | |
10969 | * anyway, we don't really care. | |
10970 | */ | |
10971 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10972 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 10973 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
10974 | crtc->unpin_work->flip_count); |
10975 | } | |
10976 | ||
6b95a207 KH |
10977 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10978 | { | |
fbee40df | 10979 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10980 | struct intel_crtc *intel_crtc = |
10981 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10982 | unsigned long flags; | |
10983 | ||
f326038a DV |
10984 | |
10985 | /* | |
10986 | * This is called both by irq handlers and the reset code (to complete | |
10987 | * lost pageflips) so needs the full irqsave spinlocks. | |
10988 | * | |
10989 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10990 | * generate a page-flip completion irq, i.e. every modeset |
10991 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10992 | */ | |
6b95a207 | 10993 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10994 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10995 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10996 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10997 | } | |
10998 | ||
6042639c | 10999 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
11000 | { |
11001 | /* Ensure that the work item is consistent when activating it ... */ | |
11002 | smp_wmb(); | |
6042639c | 11003 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
11004 | /* and that it is marked active as soon as the irq could fire. */ |
11005 | smp_wmb(); | |
11006 | } | |
11007 | ||
8c9f3aaf JB |
11008 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11009 | struct drm_crtc *crtc, | |
11010 | struct drm_framebuffer *fb, | |
ed8d1975 | 11011 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11012 | struct drm_i915_gem_request *req, |
ed8d1975 | 11013 | uint32_t flags) |
8c9f3aaf | 11014 | { |
6258fbe2 | 11015 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11016 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11017 | u32 flip_mask; |
11018 | int ret; | |
11019 | ||
5fb9de1a | 11020 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11021 | if (ret) |
4fa62c89 | 11022 | return ret; |
8c9f3aaf JB |
11023 | |
11024 | /* Can't queue multiple flips, so wait for the previous | |
11025 | * one to finish before executing the next. | |
11026 | */ | |
11027 | if (intel_crtc->plane) | |
11028 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11029 | else | |
11030 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11031 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11032 | intel_ring_emit(ring, MI_NOOP); | |
11033 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
11034 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11035 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11036 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 11037 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca | 11038 | |
6042639c | 11039 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11040 | return 0; |
8c9f3aaf JB |
11041 | } |
11042 | ||
11043 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11044 | struct drm_crtc *crtc, | |
11045 | struct drm_framebuffer *fb, | |
ed8d1975 | 11046 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11047 | struct drm_i915_gem_request *req, |
ed8d1975 | 11048 | uint32_t flags) |
8c9f3aaf | 11049 | { |
6258fbe2 | 11050 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11051 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11052 | u32 flip_mask; |
11053 | int ret; | |
11054 | ||
5fb9de1a | 11055 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11056 | if (ret) |
4fa62c89 | 11057 | return ret; |
8c9f3aaf JB |
11058 | |
11059 | if (intel_crtc->plane) | |
11060 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11061 | else | |
11062 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11063 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11064 | intel_ring_emit(ring, MI_NOOP); | |
11065 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
11066 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11067 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11068 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
11069 | intel_ring_emit(ring, MI_NOOP); |
11070 | ||
6042639c | 11071 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11072 | return 0; |
8c9f3aaf JB |
11073 | } |
11074 | ||
11075 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11076 | struct drm_crtc *crtc, | |
11077 | struct drm_framebuffer *fb, | |
ed8d1975 | 11078 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11079 | struct drm_i915_gem_request *req, |
ed8d1975 | 11080 | uint32_t flags) |
8c9f3aaf | 11081 | { |
6258fbe2 | 11082 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11083 | struct drm_i915_private *dev_priv = dev->dev_private; |
11084 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11085 | uint32_t pf, pipesrc; | |
11086 | int ret; | |
11087 | ||
5fb9de1a | 11088 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11089 | if (ret) |
4fa62c89 | 11090 | return ret; |
8c9f3aaf JB |
11091 | |
11092 | /* i965+ uses the linear or tiled offsets from the | |
11093 | * Display Registers (which do not change across a page-flip) | |
11094 | * so we need only reprogram the base address. | |
11095 | */ | |
6d90c952 DV |
11096 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11097 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11098 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11099 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 11100 | obj->tiling_mode); |
8c9f3aaf JB |
11101 | |
11102 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11103 | * untested on non-native modes, so ignore it for now. | |
11104 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11105 | */ | |
11106 | pf = 0; | |
11107 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 11108 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11109 | |
6042639c | 11110 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11111 | return 0; |
8c9f3aaf JB |
11112 | } |
11113 | ||
11114 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11115 | struct drm_crtc *crtc, | |
11116 | struct drm_framebuffer *fb, | |
ed8d1975 | 11117 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11118 | struct drm_i915_gem_request *req, |
ed8d1975 | 11119 | uint32_t flags) |
8c9f3aaf | 11120 | { |
6258fbe2 | 11121 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11122 | struct drm_i915_private *dev_priv = dev->dev_private; |
11123 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11124 | uint32_t pf, pipesrc; | |
11125 | int ret; | |
11126 | ||
5fb9de1a | 11127 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11128 | if (ret) |
4fa62c89 | 11129 | return ret; |
8c9f3aaf | 11130 | |
6d90c952 DV |
11131 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11132 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11133 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 11134 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 11135 | |
dc257cf1 DV |
11136 | /* Contrary to the suggestions in the documentation, |
11137 | * "Enable Panel Fitter" does not seem to be required when page | |
11138 | * flipping with a non-native mode, and worse causes a normal | |
11139 | * modeset to fail. | |
11140 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11141 | */ | |
11142 | pf = 0; | |
8c9f3aaf | 11143 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 11144 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11145 | |
6042639c | 11146 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11147 | return 0; |
8c9f3aaf JB |
11148 | } |
11149 | ||
7c9017e5 JB |
11150 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11151 | struct drm_crtc *crtc, | |
11152 | struct drm_framebuffer *fb, | |
ed8d1975 | 11153 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11154 | struct drm_i915_gem_request *req, |
ed8d1975 | 11155 | uint32_t flags) |
7c9017e5 | 11156 | { |
6258fbe2 | 11157 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 11158 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11159 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11160 | int len, ret; |
11161 | ||
eba905b2 | 11162 | switch (intel_crtc->plane) { |
cb05d8de DV |
11163 | case PLANE_A: |
11164 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11165 | break; | |
11166 | case PLANE_B: | |
11167 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11168 | break; | |
11169 | case PLANE_C: | |
11170 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11171 | break; | |
11172 | default: | |
11173 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11174 | return -ENODEV; |
cb05d8de DV |
11175 | } |
11176 | ||
ffe74d75 | 11177 | len = 4; |
f476828a | 11178 | if (ring->id == RCS) { |
ffe74d75 | 11179 | len += 6; |
f476828a DL |
11180 | /* |
11181 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11182 | * 48bits addresses, and we need a NOOP for the batch size to | |
11183 | * stay even. | |
11184 | */ | |
11185 | if (IS_GEN8(dev)) | |
11186 | len += 2; | |
11187 | } | |
ffe74d75 | 11188 | |
f66fab8e VS |
11189 | /* |
11190 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11191 | * "The full packet must be contained within the same cache line." | |
11192 | * | |
11193 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11194 | * cacheline, if we ever start emitting more commands before | |
11195 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11196 | * then do the cacheline alignment, and finally emit the | |
11197 | * MI_DISPLAY_FLIP. | |
11198 | */ | |
bba09b12 | 11199 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11200 | if (ret) |
4fa62c89 | 11201 | return ret; |
f66fab8e | 11202 | |
5fb9de1a | 11203 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11204 | if (ret) |
4fa62c89 | 11205 | return ret; |
7c9017e5 | 11206 | |
ffe74d75 CW |
11207 | /* Unmask the flip-done completion message. Note that the bspec says that |
11208 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11209 | * more than one flip event at any time (or ensure that one flip message | |
11210 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11211 | * Experimentation says that BCS works despite DERRMR masking all | |
11212 | * flip-done completion events and that unmasking all planes at once | |
11213 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11214 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11215 | */ | |
11216 | if (ring->id == RCS) { | |
11217 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 11218 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 CW |
11219 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
11220 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11221 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11222 | if (IS_GEN8(dev)) |
f1afe24f | 11223 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11224 | MI_SRM_LRM_GLOBAL_GTT); |
11225 | else | |
f1afe24f | 11226 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
f476828a | 11227 | MI_SRM_LRM_GLOBAL_GTT); |
f92a9162 | 11228 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 | 11229 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
f476828a DL |
11230 | if (IS_GEN8(dev)) { |
11231 | intel_ring_emit(ring, 0); | |
11232 | intel_ring_emit(ring, MI_NOOP); | |
11233 | } | |
ffe74d75 CW |
11234 | } |
11235 | ||
cb05d8de | 11236 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11237 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11238 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11239 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca | 11240 | |
6042639c | 11241 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11242 | return 0; |
7c9017e5 JB |
11243 | } |
11244 | ||
84c33a64 SG |
11245 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11246 | struct drm_i915_gem_object *obj) | |
11247 | { | |
11248 | /* | |
11249 | * This is not being used for older platforms, because | |
11250 | * non-availability of flip done interrupt forces us to use | |
11251 | * CS flips. Older platforms derive flip done using some clever | |
11252 | * tricks involving the flip_pending status bits and vblank irqs. | |
11253 | * So using MMIO flips there would disrupt this mechanism. | |
11254 | */ | |
11255 | ||
8e09bf83 CW |
11256 | if (ring == NULL) |
11257 | return true; | |
11258 | ||
84c33a64 SG |
11259 | if (INTEL_INFO(ring->dev)->gen < 5) |
11260 | return false; | |
11261 | ||
11262 | if (i915.use_mmio_flip < 0) | |
11263 | return false; | |
11264 | else if (i915.use_mmio_flip > 0) | |
11265 | return true; | |
14bf993e OM |
11266 | else if (i915.enable_execlists) |
11267 | return true; | |
fd8e058a AG |
11268 | else if (obj->base.dma_buf && |
11269 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11270 | false)) | |
11271 | return true; | |
84c33a64 | 11272 | else |
b4716185 | 11273 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11274 | } |
11275 | ||
6042639c | 11276 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11277 | unsigned int rotation, |
6042639c | 11278 | struct intel_unpin_work *work) |
ff944564 DL |
11279 | { |
11280 | struct drm_device *dev = intel_crtc->base.dev; | |
11281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11282 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11283 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11284 | u32 ctl, stride, tile_height; |
ff944564 DL |
11285 | |
11286 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11287 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11288 | switch (fb->modifier[0]) { |
11289 | case DRM_FORMAT_MOD_NONE: | |
11290 | break; | |
11291 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11292 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11293 | break; |
11294 | case I915_FORMAT_MOD_Y_TILED: | |
11295 | ctl |= PLANE_CTL_TILED_Y; | |
11296 | break; | |
11297 | case I915_FORMAT_MOD_Yf_TILED: | |
11298 | ctl |= PLANE_CTL_TILED_YF; | |
11299 | break; | |
11300 | default: | |
11301 | MISSING_CASE(fb->modifier[0]); | |
11302 | } | |
ff944564 DL |
11303 | |
11304 | /* | |
11305 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11306 | * linear buffers or in number of tiles for tiled buffers. | |
11307 | */ | |
86efe24a TU |
11308 | if (intel_rotation_90_or_270(rotation)) { |
11309 | /* stride = Surface height in tiles */ | |
832be82f | 11310 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); |
86efe24a TU |
11311 | stride = DIV_ROUND_UP(fb->height, tile_height); |
11312 | } else { | |
11313 | stride = fb->pitches[0] / | |
7b49f948 VS |
11314 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
11315 | fb->pixel_format); | |
86efe24a | 11316 | } |
ff944564 DL |
11317 | |
11318 | /* | |
11319 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11320 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11321 | */ | |
11322 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11323 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11324 | ||
6042639c | 11325 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11326 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11327 | } | |
11328 | ||
6042639c CW |
11329 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11330 | struct intel_unpin_work *work) | |
84c33a64 SG |
11331 | { |
11332 | struct drm_device *dev = intel_crtc->base.dev; | |
11333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11334 | struct intel_framebuffer *intel_fb = | |
11335 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11336 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11337 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11338 | u32 dspcntr; |
84c33a64 | 11339 | |
84c33a64 SG |
11340 | dspcntr = I915_READ(reg); |
11341 | ||
c5d97472 DL |
11342 | if (obj->tiling_mode != I915_TILING_NONE) |
11343 | dspcntr |= DISPPLANE_TILED; | |
11344 | else | |
11345 | dspcntr &= ~DISPPLANE_TILED; | |
11346 | ||
84c33a64 SG |
11347 | I915_WRITE(reg, dspcntr); |
11348 | ||
6042639c | 11349 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11350 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11351 | } |
11352 | ||
11353 | /* | |
11354 | * XXX: This is the temporary way to update the plane registers until we get | |
11355 | * around to using the usual plane update functions for MMIO flips | |
11356 | */ | |
6042639c | 11357 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11358 | { |
6042639c CW |
11359 | struct intel_crtc *crtc = mmio_flip->crtc; |
11360 | struct intel_unpin_work *work; | |
11361 | ||
11362 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11363 | work = crtc->unpin_work; | |
11364 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11365 | if (work == NULL) | |
11366 | return; | |
ff944564 | 11367 | |
6042639c | 11368 | intel_mark_page_flip_active(work); |
ff944564 | 11369 | |
6042639c | 11370 | intel_pipe_update_start(crtc); |
ff944564 | 11371 | |
6042639c | 11372 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11373 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11374 | else |
11375 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11376 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11377 | |
6042639c | 11378 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11379 | } |
11380 | ||
9362c7c5 | 11381 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11382 | { |
b2cfe0ab CW |
11383 | struct intel_mmio_flip *mmio_flip = |
11384 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11385 | struct intel_framebuffer *intel_fb = |
11386 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11387 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11388 | |
6042639c | 11389 | if (mmio_flip->req) { |
eed29a5b | 11390 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11391 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11392 | false, NULL, |
11393 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11394 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11395 | } | |
84c33a64 | 11396 | |
fd8e058a AG |
11397 | /* For framebuffer backed by dmabuf, wait for fence */ |
11398 | if (obj->base.dma_buf) | |
11399 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11400 | false, false, | |
11401 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11402 | ||
6042639c | 11403 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11404 | kfree(mmio_flip); |
84c33a64 SG |
11405 | } |
11406 | ||
11407 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11408 | struct drm_crtc *crtc, | |
86efe24a | 11409 | struct drm_i915_gem_object *obj) |
84c33a64 | 11410 | { |
b2cfe0ab CW |
11411 | struct intel_mmio_flip *mmio_flip; |
11412 | ||
11413 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11414 | if (mmio_flip == NULL) | |
11415 | return -ENOMEM; | |
84c33a64 | 11416 | |
bcafc4e3 | 11417 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11418 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11419 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11420 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11421 | |
b2cfe0ab CW |
11422 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11423 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11424 | |
84c33a64 SG |
11425 | return 0; |
11426 | } | |
11427 | ||
8c9f3aaf JB |
11428 | static int intel_default_queue_flip(struct drm_device *dev, |
11429 | struct drm_crtc *crtc, | |
11430 | struct drm_framebuffer *fb, | |
ed8d1975 | 11431 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11432 | struct drm_i915_gem_request *req, |
ed8d1975 | 11433 | uint32_t flags) |
8c9f3aaf JB |
11434 | { |
11435 | return -ENODEV; | |
11436 | } | |
11437 | ||
d6bbafa1 CW |
11438 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11439 | struct drm_crtc *crtc) | |
11440 | { | |
11441 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11442 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11443 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11444 | u32 addr; | |
11445 | ||
11446 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11447 | return true; | |
11448 | ||
908565c2 CW |
11449 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11450 | return false; | |
11451 | ||
d6bbafa1 CW |
11452 | if (!work->enable_stall_check) |
11453 | return false; | |
11454 | ||
11455 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11456 | if (work->flip_queued_req && |
11457 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11458 | return false; |
11459 | ||
1e3feefd | 11460 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11461 | } |
11462 | ||
1e3feefd | 11463 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11464 | return false; |
11465 | ||
11466 | /* Potential stall - if we see that the flip has happened, | |
11467 | * assume a missed interrupt. */ | |
11468 | if (INTEL_INFO(dev)->gen >= 4) | |
11469 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11470 | else | |
11471 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11472 | ||
11473 | /* There is a potential issue here with a false positive after a flip | |
11474 | * to the same address. We could address this by checking for a | |
11475 | * non-incrementing frame counter. | |
11476 | */ | |
11477 | return addr == work->gtt_offset; | |
11478 | } | |
11479 | ||
11480 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11481 | { | |
11482 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11483 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11484 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11485 | struct intel_unpin_work *work; |
f326038a | 11486 | |
6c51d46f | 11487 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11488 | |
11489 | if (crtc == NULL) | |
11490 | return; | |
11491 | ||
f326038a | 11492 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11493 | work = intel_crtc->unpin_work; |
11494 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11495 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11496 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11497 | page_flip_completed(intel_crtc); |
6ad790c0 | 11498 | work = NULL; |
d6bbafa1 | 11499 | } |
6ad790c0 CW |
11500 | if (work != NULL && |
11501 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11502 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11503 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11504 | } |
11505 | ||
6b95a207 KH |
11506 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11507 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11508 | struct drm_pending_vblank_event *event, |
11509 | uint32_t page_flip_flags) | |
6b95a207 KH |
11510 | { |
11511 | struct drm_device *dev = crtc->dev; | |
11512 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11513 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11514 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11515 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11516 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11517 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11518 | struct intel_unpin_work *work; |
a4872ba6 | 11519 | struct intel_engine_cs *ring; |
cf5d8a46 | 11520 | bool mmio_flip; |
91af127f | 11521 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11522 | int ret; |
6b95a207 | 11523 | |
2ff8fde1 MR |
11524 | /* |
11525 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11526 | * check to be safe. In the future we may enable pageflipping from | |
11527 | * a disabled primary plane. | |
11528 | */ | |
11529 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11530 | return -EBUSY; | |
11531 | ||
e6a595d2 | 11532 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11533 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11534 | return -EINVAL; |
11535 | ||
11536 | /* | |
11537 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11538 | * Note that pitch changes could also affect these register. | |
11539 | */ | |
11540 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11541 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11542 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11543 | return -EINVAL; |
11544 | ||
f900db47 CW |
11545 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11546 | goto out_hang; | |
11547 | ||
b14c5679 | 11548 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11549 | if (work == NULL) |
11550 | return -ENOMEM; | |
11551 | ||
6b95a207 | 11552 | work->event = event; |
b4a98e57 | 11553 | work->crtc = crtc; |
ab8d6675 | 11554 | work->old_fb = old_fb; |
6b95a207 KH |
11555 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11556 | ||
87b6b101 | 11557 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11558 | if (ret) |
11559 | goto free_work; | |
11560 | ||
6b95a207 | 11561 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11562 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11563 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11564 | /* Before declaring the flip queue wedged, check if |
11565 | * the hardware completed the operation behind our backs. | |
11566 | */ | |
11567 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11568 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11569 | page_flip_completed(intel_crtc); | |
11570 | } else { | |
11571 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11572 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11573 | |
d6bbafa1 CW |
11574 | drm_crtc_vblank_put(crtc); |
11575 | kfree(work); | |
11576 | return -EBUSY; | |
11577 | } | |
6b95a207 KH |
11578 | } |
11579 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11580 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11581 | |
b4a98e57 CW |
11582 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11583 | flush_workqueue(dev_priv->wq); | |
11584 | ||
75dfca80 | 11585 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11586 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11587 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11588 | |
f4510a27 | 11589 | crtc->primary->fb = fb; |
afd65eb4 | 11590 | update_state_fb(crtc->primary); |
e8216e50 | 11591 | intel_fbc_pre_update(intel_crtc); |
1ed1f968 | 11592 | |
e1f99ce6 | 11593 | work->pending_flip_obj = obj; |
e1f99ce6 | 11594 | |
89ed88ba CW |
11595 | ret = i915_mutex_lock_interruptible(dev); |
11596 | if (ret) | |
11597 | goto cleanup; | |
11598 | ||
b4a98e57 | 11599 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11600 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11601 | |
75f7f3ec | 11602 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11603 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11604 | |
666a4537 | 11605 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4fa62c89 | 11606 | ring = &dev_priv->ring[BCS]; |
ab8d6675 | 11607 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11608 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11609 | ring = NULL; | |
48bf5b2d | 11610 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11611 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11612 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11613 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11614 | if (ring == NULL || ring->id != RCS) |
11615 | ring = &dev_priv->ring[BCS]; | |
11616 | } else { | |
11617 | ring = &dev_priv->ring[RCS]; | |
11618 | } | |
11619 | ||
cf5d8a46 CW |
11620 | mmio_flip = use_mmio_flip(ring, obj); |
11621 | ||
11622 | /* When using CS flips, we want to emit semaphores between rings. | |
11623 | * However, when using mmio flips we will create a task to do the | |
11624 | * synchronisation, so all we want here is to pin the framebuffer | |
11625 | * into the display plane and skip any waits. | |
11626 | */ | |
7580d774 ML |
11627 | if (!mmio_flip) { |
11628 | ret = i915_gem_object_sync(obj, ring, &request); | |
11629 | if (ret) | |
11630 | goto cleanup_pending; | |
11631 | } | |
11632 | ||
82bc3b2d | 11633 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
7580d774 | 11634 | crtc->primary->state); |
8c9f3aaf JB |
11635 | if (ret) |
11636 | goto cleanup_pending; | |
6b95a207 | 11637 | |
dedf278c TU |
11638 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11639 | obj, 0); | |
11640 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11641 | |
cf5d8a46 | 11642 | if (mmio_flip) { |
86efe24a | 11643 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11644 | if (ret) |
11645 | goto cleanup_unpin; | |
11646 | ||
f06cc1b9 JH |
11647 | i915_gem_request_assign(&work->flip_queued_req, |
11648 | obj->last_write_req); | |
d6bbafa1 | 11649 | } else { |
6258fbe2 | 11650 | if (!request) { |
26827088 DG |
11651 | request = i915_gem_request_alloc(ring, NULL); |
11652 | if (IS_ERR(request)) { | |
11653 | ret = PTR_ERR(request); | |
6258fbe2 | 11654 | goto cleanup_unpin; |
26827088 | 11655 | } |
6258fbe2 JH |
11656 | } |
11657 | ||
11658 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11659 | page_flip_flags); |
11660 | if (ret) | |
11661 | goto cleanup_unpin; | |
11662 | ||
6258fbe2 | 11663 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11664 | } |
11665 | ||
91af127f | 11666 | if (request) |
75289874 | 11667 | i915_add_request_no_flush(request); |
91af127f | 11668 | |
1e3feefd | 11669 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11670 | work->enable_stall_check = true; |
4fa62c89 | 11671 | |
ab8d6675 | 11672 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11673 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11674 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11675 | |
a9ff8714 VS |
11676 | intel_frontbuffer_flip_prepare(dev, |
11677 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11678 | |
e5510fac JB |
11679 | trace_i915_flip_request(intel_crtc->plane, obj); |
11680 | ||
6b95a207 | 11681 | return 0; |
96b099fd | 11682 | |
4fa62c89 | 11683 | cleanup_unpin: |
82bc3b2d | 11684 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11685 | cleanup_pending: |
0aa498d5 | 11686 | if (!IS_ERR_OR_NULL(request)) |
91af127f | 11687 | i915_gem_request_cancel(request); |
b4a98e57 | 11688 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11689 | mutex_unlock(&dev->struct_mutex); |
11690 | cleanup: | |
f4510a27 | 11691 | crtc->primary->fb = old_fb; |
afd65eb4 | 11692 | update_state_fb(crtc->primary); |
89ed88ba CW |
11693 | |
11694 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11695 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11696 | |
5e2d7afc | 11697 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11698 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11699 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11700 | |
87b6b101 | 11701 | drm_crtc_vblank_put(crtc); |
7317c75e | 11702 | free_work: |
96b099fd CW |
11703 | kfree(work); |
11704 | ||
f900db47 | 11705 | if (ret == -EIO) { |
02e0efb5 ML |
11706 | struct drm_atomic_state *state; |
11707 | struct drm_plane_state *plane_state; | |
11708 | ||
f900db47 | 11709 | out_hang: |
02e0efb5 ML |
11710 | state = drm_atomic_state_alloc(dev); |
11711 | if (!state) | |
11712 | return -ENOMEM; | |
11713 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11714 | ||
11715 | retry: | |
11716 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11717 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11718 | if (!ret) { | |
11719 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11720 | ||
11721 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11722 | if (!ret) | |
11723 | ret = drm_atomic_commit(state); | |
11724 | } | |
11725 | ||
11726 | if (ret == -EDEADLK) { | |
11727 | drm_modeset_backoff(state->acquire_ctx); | |
11728 | drm_atomic_state_clear(state); | |
11729 | goto retry; | |
11730 | } | |
11731 | ||
11732 | if (ret) | |
11733 | drm_atomic_state_free(state); | |
11734 | ||
f0d3dad3 | 11735 | if (ret == 0 && event) { |
5e2d7afc | 11736 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11737 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11738 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11739 | } |
f900db47 | 11740 | } |
96b099fd | 11741 | return ret; |
6b95a207 KH |
11742 | } |
11743 | ||
da20eabd ML |
11744 | |
11745 | /** | |
11746 | * intel_wm_need_update - Check whether watermarks need updating | |
11747 | * @plane: drm plane | |
11748 | * @state: new plane state | |
11749 | * | |
11750 | * Check current plane state versus the new one to determine whether | |
11751 | * watermarks need to be recalculated. | |
11752 | * | |
11753 | * Returns true or false. | |
11754 | */ | |
11755 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11756 | struct drm_plane_state *state) | |
11757 | { | |
d21fbe87 MR |
11758 | struct intel_plane_state *new = to_intel_plane_state(state); |
11759 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11760 | ||
11761 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11762 | if (new->visible != cur->visible) |
11763 | return true; | |
11764 | ||
11765 | if (!cur->base.fb || !new->base.fb) | |
11766 | return false; | |
11767 | ||
11768 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11769 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11770 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11771 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11772 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11773 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11774 | return true; |
7809e5ae | 11775 | |
2791a16c | 11776 | return false; |
7809e5ae MR |
11777 | } |
11778 | ||
d21fbe87 MR |
11779 | static bool needs_scaling(struct intel_plane_state *state) |
11780 | { | |
11781 | int src_w = drm_rect_width(&state->src) >> 16; | |
11782 | int src_h = drm_rect_height(&state->src) >> 16; | |
11783 | int dst_w = drm_rect_width(&state->dst); | |
11784 | int dst_h = drm_rect_height(&state->dst); | |
11785 | ||
11786 | return (src_w != dst_w || src_h != dst_h); | |
11787 | } | |
11788 | ||
da20eabd ML |
11789 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11790 | struct drm_plane_state *plane_state) | |
11791 | { | |
ab1d3a0e | 11792 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11793 | struct drm_crtc *crtc = crtc_state->crtc; |
11794 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11795 | struct drm_plane *plane = plane_state->plane; | |
11796 | struct drm_device *dev = crtc->dev; | |
da20eabd ML |
11797 | struct intel_plane_state *old_plane_state = |
11798 | to_intel_plane_state(plane->state); | |
11799 | int idx = intel_crtc->base.base.id, ret; | |
11800 | int i = drm_plane_index(plane); | |
11801 | bool mode_changed = needs_modeset(crtc_state); | |
11802 | bool was_crtc_enabled = crtc->state->active; | |
11803 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11804 | bool turn_off, turn_on, visible, was_visible; |
11805 | struct drm_framebuffer *fb = plane_state->fb; | |
11806 | ||
11807 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11808 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11809 | ret = skl_update_scaler_plane( | |
11810 | to_intel_crtc_state(crtc_state), | |
11811 | to_intel_plane_state(plane_state)); | |
11812 | if (ret) | |
11813 | return ret; | |
11814 | } | |
11815 | ||
da20eabd ML |
11816 | was_visible = old_plane_state->visible; |
11817 | visible = to_intel_plane_state(plane_state)->visible; | |
11818 | ||
11819 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11820 | was_visible = false; | |
11821 | ||
35c08f43 ML |
11822 | /* |
11823 | * Visibility is calculated as if the crtc was on, but | |
11824 | * after scaler setup everything depends on it being off | |
11825 | * when the crtc isn't active. | |
11826 | */ | |
11827 | if (!is_crtc_enabled) | |
11828 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11829 | |
11830 | if (!was_visible && !visible) | |
11831 | return 0; | |
11832 | ||
11833 | turn_off = was_visible && (!visible || mode_changed); | |
11834 | turn_on = visible && (!was_visible || mode_changed); | |
11835 | ||
11836 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11837 | plane->base.id, fb ? fb->base.id : -1); | |
11838 | ||
11839 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11840 | plane->base.id, was_visible, visible, | |
11841 | turn_off, turn_on, mode_changed); | |
11842 | ||
92826fcd ML |
11843 | if (turn_on || turn_off) { |
11844 | pipe_config->wm_changed = true; | |
11845 | ||
852eb00d VS |
11846 | /* must disable cxsr around plane enable/disable */ |
11847 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11848 | if (is_crtc_enabled) | |
11849 | intel_crtc->atomic.wait_vblank = true; | |
ab1d3a0e | 11850 | pipe_config->disable_cxsr = true; |
852eb00d VS |
11851 | } |
11852 | } else if (intel_wm_need_update(plane, plane_state)) { | |
92826fcd | 11853 | pipe_config->wm_changed = true; |
852eb00d | 11854 | } |
da20eabd | 11855 | |
8be6ca85 | 11856 | if (visible || was_visible) |
a9ff8714 VS |
11857 | intel_crtc->atomic.fb_bits |= |
11858 | to_intel_plane(plane)->frontbuffer_bit; | |
11859 | ||
da20eabd ML |
11860 | switch (plane->type) { |
11861 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd | 11862 | intel_crtc->atomic.post_enable_primary = turn_on; |
fcf38d13 | 11863 | intel_crtc->atomic.update_fbc = true; |
da20eabd | 11864 | |
da20eabd ML |
11865 | /* |
11866 | * BDW signals flip done immediately if the plane | |
11867 | * is disabled, even if the plane enable is already | |
11868 | * armed to occur at the next vblank :( | |
11869 | */ | |
11870 | if (turn_on && IS_BROADWELL(dev)) | |
11871 | intel_crtc->atomic.wait_vblank = true; | |
11872 | ||
da20eabd ML |
11873 | break; |
11874 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
11875 | break; |
11876 | case DRM_PLANE_TYPE_OVERLAY: | |
d21fbe87 MR |
11877 | /* |
11878 | * WaCxSRDisabledForSpriteScaling:ivb | |
11879 | * | |
11880 | * cstate->update_wm was already set above, so this flag will | |
11881 | * take effect when we commit and program watermarks. | |
11882 | */ | |
11883 | if (IS_IVYBRIDGE(dev) && | |
11884 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11885 | !needs_scaling(old_plane_state)) { | |
11886 | to_intel_crtc_state(crtc_state)->disable_lp_wm = true; | |
11887 | } else if (turn_off && !mode_changed) { | |
da20eabd ML |
11888 | intel_crtc->atomic.wait_vblank = true; |
11889 | intel_crtc->atomic.update_sprite_watermarks |= | |
11890 | 1 << i; | |
11891 | } | |
d21fbe87 MR |
11892 | |
11893 | break; | |
da20eabd ML |
11894 | } |
11895 | return 0; | |
11896 | } | |
11897 | ||
6d3a1ce7 ML |
11898 | static bool encoders_cloneable(const struct intel_encoder *a, |
11899 | const struct intel_encoder *b) | |
11900 | { | |
11901 | /* masks could be asymmetric, so check both ways */ | |
11902 | return a == b || (a->cloneable & (1 << b->type) && | |
11903 | b->cloneable & (1 << a->type)); | |
11904 | } | |
11905 | ||
11906 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11907 | struct intel_crtc *crtc, | |
11908 | struct intel_encoder *encoder) | |
11909 | { | |
11910 | struct intel_encoder *source_encoder; | |
11911 | struct drm_connector *connector; | |
11912 | struct drm_connector_state *connector_state; | |
11913 | int i; | |
11914 | ||
11915 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11916 | if (connector_state->crtc != &crtc->base) | |
11917 | continue; | |
11918 | ||
11919 | source_encoder = | |
11920 | to_intel_encoder(connector_state->best_encoder); | |
11921 | if (!encoders_cloneable(encoder, source_encoder)) | |
11922 | return false; | |
11923 | } | |
11924 | ||
11925 | return true; | |
11926 | } | |
11927 | ||
11928 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11929 | struct intel_crtc *crtc) | |
11930 | { | |
11931 | struct intel_encoder *encoder; | |
11932 | struct drm_connector *connector; | |
11933 | struct drm_connector_state *connector_state; | |
11934 | int i; | |
11935 | ||
11936 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11937 | if (connector_state->crtc != &crtc->base) | |
11938 | continue; | |
11939 | ||
11940 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11941 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11942 | return false; | |
11943 | } | |
11944 | ||
11945 | return true; | |
11946 | } | |
11947 | ||
11948 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11949 | struct drm_crtc_state *crtc_state) | |
11950 | { | |
cf5a15be | 11951 | struct drm_device *dev = crtc->dev; |
ad421372 | 11952 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11953 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11954 | struct intel_crtc_state *pipe_config = |
11955 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11956 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11957 | int ret; |
6d3a1ce7 ML |
11958 | bool mode_changed = needs_modeset(crtc_state); |
11959 | ||
11960 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11961 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11962 | return -EINVAL; | |
11963 | } | |
11964 | ||
852eb00d | 11965 | if (mode_changed && !crtc_state->active) |
92826fcd | 11966 | pipe_config->wm_changed = true; |
eddfcbcd | 11967 | |
ad421372 ML |
11968 | if (mode_changed && crtc_state->enable && |
11969 | dev_priv->display.crtc_compute_clock && | |
11970 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
11971 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
11972 | pipe_config); | |
11973 | if (ret) | |
11974 | return ret; | |
11975 | } | |
11976 | ||
e435d6e5 | 11977 | ret = 0; |
86c8bbbe MR |
11978 | if (dev_priv->display.compute_pipe_wm) { |
11979 | ret = dev_priv->display.compute_pipe_wm(intel_crtc, state); | |
bf220452 | 11980 | if (ret) |
86c8bbbe MR |
11981 | return ret; |
11982 | } | |
11983 | ||
e435d6e5 ML |
11984 | if (INTEL_INFO(dev)->gen >= 9) { |
11985 | if (mode_changed) | |
11986 | ret = skl_update_scaler_crtc(pipe_config); | |
11987 | ||
11988 | if (!ret) | |
11989 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
11990 | pipe_config); | |
11991 | } | |
11992 | ||
11993 | return ret; | |
6d3a1ce7 ML |
11994 | } |
11995 | ||
65b38e0d | 11996 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
11997 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
11998 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
11999 | .atomic_begin = intel_begin_crtc_commit, |
12000 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12001 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12002 | }; |
12003 | ||
d29b2f9d ACO |
12004 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12005 | { | |
12006 | struct intel_connector *connector; | |
12007 | ||
12008 | for_each_intel_connector(dev, connector) { | |
12009 | if (connector->base.encoder) { | |
12010 | connector->base.state->best_encoder = | |
12011 | connector->base.encoder; | |
12012 | connector->base.state->crtc = | |
12013 | connector->base.encoder->crtc; | |
12014 | } else { | |
12015 | connector->base.state->best_encoder = NULL; | |
12016 | connector->base.state->crtc = NULL; | |
12017 | } | |
12018 | } | |
12019 | } | |
12020 | ||
050f7aeb | 12021 | static void |
eba905b2 | 12022 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12023 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12024 | { |
12025 | int bpp = pipe_config->pipe_bpp; | |
12026 | ||
12027 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12028 | connector->base.base.id, | |
c23cc417 | 12029 | connector->base.name); |
050f7aeb DV |
12030 | |
12031 | /* Don't use an invalid EDID bpc value */ | |
12032 | if (connector->base.display_info.bpc && | |
12033 | connector->base.display_info.bpc * 3 < bpp) { | |
12034 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12035 | bpp, connector->base.display_info.bpc*3); | |
12036 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12037 | } | |
12038 | ||
013dd9e0 JN |
12039 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12040 | if (connector->base.display_info.bpc == 0) { | |
12041 | int type = connector->base.connector_type; | |
12042 | int clamp_bpp = 24; | |
12043 | ||
12044 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12045 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12046 | type == DRM_MODE_CONNECTOR_eDP) | |
12047 | clamp_bpp = 18; | |
12048 | ||
12049 | if (bpp > clamp_bpp) { | |
12050 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12051 | bpp, clamp_bpp); | |
12052 | pipe_config->pipe_bpp = clamp_bpp; | |
12053 | } | |
050f7aeb DV |
12054 | } |
12055 | } | |
12056 | ||
4e53c2e0 | 12057 | static int |
050f7aeb | 12058 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12059 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12060 | { |
050f7aeb | 12061 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12062 | struct drm_atomic_state *state; |
da3ced29 ACO |
12063 | struct drm_connector *connector; |
12064 | struct drm_connector_state *connector_state; | |
1486017f | 12065 | int bpp, i; |
4e53c2e0 | 12066 | |
666a4537 | 12067 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12068 | bpp = 10*3; |
d328c9d7 DV |
12069 | else if (INTEL_INFO(dev)->gen >= 5) |
12070 | bpp = 12*3; | |
12071 | else | |
12072 | bpp = 8*3; | |
12073 | ||
4e53c2e0 | 12074 | |
4e53c2e0 DV |
12075 | pipe_config->pipe_bpp = bpp; |
12076 | ||
1486017f ACO |
12077 | state = pipe_config->base.state; |
12078 | ||
4e53c2e0 | 12079 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12080 | for_each_connector_in_state(state, connector, connector_state, i) { |
12081 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12082 | continue; |
12083 | ||
da3ced29 ACO |
12084 | connected_sink_compute_bpp(to_intel_connector(connector), |
12085 | pipe_config); | |
4e53c2e0 DV |
12086 | } |
12087 | ||
12088 | return bpp; | |
12089 | } | |
12090 | ||
644db711 DV |
12091 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12092 | { | |
12093 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12094 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12095 | mode->crtc_clock, |
644db711 DV |
12096 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12097 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12098 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12099 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12100 | } | |
12101 | ||
c0b03411 | 12102 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12103 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12104 | const char *context) |
12105 | { | |
6a60cd87 CK |
12106 | struct drm_device *dev = crtc->base.dev; |
12107 | struct drm_plane *plane; | |
12108 | struct intel_plane *intel_plane; | |
12109 | struct intel_plane_state *state; | |
12110 | struct drm_framebuffer *fb; | |
12111 | ||
12112 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12113 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
12114 | |
12115 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
12116 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
12117 | pipe_config->pipe_bpp, pipe_config->dither); | |
12118 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12119 | pipe_config->has_pch_encoder, | |
12120 | pipe_config->fdi_lanes, | |
12121 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12122 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12123 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12124 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12125 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12126 | pipe_config->lane_count, |
eb14cb74 VS |
12127 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12128 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12129 | pipe_config->dp_m_n.tu); | |
b95af8be | 12130 | |
90a6b7b0 | 12131 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12132 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12133 | pipe_config->lane_count, |
b95af8be VK |
12134 | pipe_config->dp_m2_n2.gmch_m, |
12135 | pipe_config->dp_m2_n2.gmch_n, | |
12136 | pipe_config->dp_m2_n2.link_m, | |
12137 | pipe_config->dp_m2_n2.link_n, | |
12138 | pipe_config->dp_m2_n2.tu); | |
12139 | ||
55072d19 DV |
12140 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12141 | pipe_config->has_audio, | |
12142 | pipe_config->has_infoframe); | |
12143 | ||
c0b03411 | 12144 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12145 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12146 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12147 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12148 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12149 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12150 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12151 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12152 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12153 | crtc->num_scalers, | |
12154 | pipe_config->scaler_state.scaler_users, | |
12155 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12156 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12157 | pipe_config->gmch_pfit.control, | |
12158 | pipe_config->gmch_pfit.pgm_ratios, | |
12159 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12160 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12161 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12162 | pipe_config->pch_pfit.size, |
12163 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12164 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12165 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12166 | |
415ff0f6 | 12167 | if (IS_BROXTON(dev)) { |
05712c15 | 12168 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12169 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12170 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12171 | pipe_config->ddi_pll_sel, |
12172 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12173 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12174 | pipe_config->dpll_hw_state.pll0, |
12175 | pipe_config->dpll_hw_state.pll1, | |
12176 | pipe_config->dpll_hw_state.pll2, | |
12177 | pipe_config->dpll_hw_state.pll3, | |
12178 | pipe_config->dpll_hw_state.pll6, | |
12179 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12180 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12181 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12182 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12183 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12184 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12185 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12186 | pipe_config->ddi_pll_sel, | |
12187 | pipe_config->dpll_hw_state.ctrl1, | |
12188 | pipe_config->dpll_hw_state.cfgcr1, | |
12189 | pipe_config->dpll_hw_state.cfgcr2); | |
12190 | } else if (HAS_DDI(dev)) { | |
00490c22 | 12191 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12192 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12193 | pipe_config->dpll_hw_state.wrpll, |
12194 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12195 | } else { |
12196 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12197 | "fp0: 0x%x, fp1: 0x%x\n", | |
12198 | pipe_config->dpll_hw_state.dpll, | |
12199 | pipe_config->dpll_hw_state.dpll_md, | |
12200 | pipe_config->dpll_hw_state.fp0, | |
12201 | pipe_config->dpll_hw_state.fp1); | |
12202 | } | |
12203 | ||
6a60cd87 CK |
12204 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12205 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12206 | intel_plane = to_intel_plane(plane); | |
12207 | if (intel_plane->pipe != crtc->pipe) | |
12208 | continue; | |
12209 | ||
12210 | state = to_intel_plane_state(plane->state); | |
12211 | fb = state->base.fb; | |
12212 | if (!fb) { | |
12213 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12214 | "disabled, scaler_id = %d\n", | |
12215 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12216 | plane->base.id, intel_plane->pipe, | |
12217 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12218 | drm_plane_index(plane), state->scaler_id); | |
12219 | continue; | |
12220 | } | |
12221 | ||
12222 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12223 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12224 | plane->base.id, intel_plane->pipe, | |
12225 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12226 | drm_plane_index(plane)); | |
12227 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12228 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12229 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12230 | state->scaler_id, | |
12231 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12232 | drm_rect_width(&state->src) >> 16, | |
12233 | drm_rect_height(&state->src) >> 16, | |
12234 | state->dst.x1, state->dst.y1, | |
12235 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12236 | } | |
c0b03411 DV |
12237 | } |
12238 | ||
5448a00d | 12239 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12240 | { |
5448a00d | 12241 | struct drm_device *dev = state->dev; |
da3ced29 | 12242 | struct drm_connector *connector; |
00f0b378 VS |
12243 | unsigned int used_ports = 0; |
12244 | ||
12245 | /* | |
12246 | * Walk the connector list instead of the encoder | |
12247 | * list to detect the problem on ddi platforms | |
12248 | * where there's just one encoder per digital port. | |
12249 | */ | |
0bff4858 VS |
12250 | drm_for_each_connector(connector, dev) { |
12251 | struct drm_connector_state *connector_state; | |
12252 | struct intel_encoder *encoder; | |
12253 | ||
12254 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12255 | if (!connector_state) | |
12256 | connector_state = connector->state; | |
12257 | ||
5448a00d | 12258 | if (!connector_state->best_encoder) |
00f0b378 VS |
12259 | continue; |
12260 | ||
5448a00d ACO |
12261 | encoder = to_intel_encoder(connector_state->best_encoder); |
12262 | ||
12263 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12264 | |
12265 | switch (encoder->type) { | |
12266 | unsigned int port_mask; | |
12267 | case INTEL_OUTPUT_UNKNOWN: | |
12268 | if (WARN_ON(!HAS_DDI(dev))) | |
12269 | break; | |
12270 | case INTEL_OUTPUT_DISPLAYPORT: | |
12271 | case INTEL_OUTPUT_HDMI: | |
12272 | case INTEL_OUTPUT_EDP: | |
12273 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12274 | ||
12275 | /* the same port mustn't appear more than once */ | |
12276 | if (used_ports & port_mask) | |
12277 | return false; | |
12278 | ||
12279 | used_ports |= port_mask; | |
12280 | default: | |
12281 | break; | |
12282 | } | |
12283 | } | |
12284 | ||
12285 | return true; | |
12286 | } | |
12287 | ||
83a57153 ACO |
12288 | static void |
12289 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12290 | { | |
12291 | struct drm_crtc_state tmp_state; | |
663a3640 | 12292 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12293 | struct intel_dpll_hw_state dpll_hw_state; |
12294 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12295 | uint32_t ddi_pll_sel; |
c4e2d043 | 12296 | bool force_thru; |
83a57153 | 12297 | |
7546a384 ACO |
12298 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12299 | * kzalloc'd. Code that depends on any field being zero should be | |
12300 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12301 | * only fields that are know to not cause problems are preserved. */ | |
12302 | ||
83a57153 | 12303 | tmp_state = crtc_state->base; |
663a3640 | 12304 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12305 | shared_dpll = crtc_state->shared_dpll; |
12306 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12307 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12308 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12309 | |
83a57153 | 12310 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12311 | |
83a57153 | 12312 | crtc_state->base = tmp_state; |
663a3640 | 12313 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12314 | crtc_state->shared_dpll = shared_dpll; |
12315 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12316 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12317 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12318 | } |
12319 | ||
548ee15b | 12320 | static int |
b8cecdf5 | 12321 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12322 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12323 | { |
b359283a | 12324 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12325 | struct intel_encoder *encoder; |
da3ced29 | 12326 | struct drm_connector *connector; |
0b901879 | 12327 | struct drm_connector_state *connector_state; |
d328c9d7 | 12328 | int base_bpp, ret = -EINVAL; |
0b901879 | 12329 | int i; |
e29c22c0 | 12330 | bool retry = true; |
ee7b9f93 | 12331 | |
83a57153 | 12332 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12333 | |
e143a21c DV |
12334 | pipe_config->cpu_transcoder = |
12335 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12336 | |
2960bc9c ID |
12337 | /* |
12338 | * Sanitize sync polarity flags based on requested ones. If neither | |
12339 | * positive or negative polarity is requested, treat this as meaning | |
12340 | * negative polarity. | |
12341 | */ | |
2d112de7 | 12342 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12343 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12344 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12345 | |
2d112de7 | 12346 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12347 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12348 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12349 | |
d328c9d7 DV |
12350 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12351 | pipe_config); | |
12352 | if (base_bpp < 0) | |
4e53c2e0 DV |
12353 | goto fail; |
12354 | ||
e41a56be VS |
12355 | /* |
12356 | * Determine the real pipe dimensions. Note that stereo modes can | |
12357 | * increase the actual pipe size due to the frame doubling and | |
12358 | * insertion of additional space for blanks between the frame. This | |
12359 | * is stored in the crtc timings. We use the requested mode to do this | |
12360 | * computation to clearly distinguish it from the adjusted mode, which | |
12361 | * can be changed by the connectors in the below retry loop. | |
12362 | */ | |
2d112de7 | 12363 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12364 | &pipe_config->pipe_src_w, |
12365 | &pipe_config->pipe_src_h); | |
e41a56be | 12366 | |
e29c22c0 | 12367 | encoder_retry: |
ef1b460d | 12368 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12369 | pipe_config->port_clock = 0; |
ef1b460d | 12370 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12371 | |
135c81b8 | 12372 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12373 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12374 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12375 | |
7758a113 DV |
12376 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12377 | * adjust it according to limitations or connector properties, and also | |
12378 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12379 | */ |
da3ced29 | 12380 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12381 | if (connector_state->crtc != crtc) |
7758a113 | 12382 | continue; |
7ae89233 | 12383 | |
0b901879 ACO |
12384 | encoder = to_intel_encoder(connector_state->best_encoder); |
12385 | ||
efea6e8e DV |
12386 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12387 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12388 | goto fail; |
12389 | } | |
ee7b9f93 | 12390 | } |
47f1c6c9 | 12391 | |
ff9a6750 DV |
12392 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12393 | * done afterwards in case the encoder adjusts the mode. */ | |
12394 | if (!pipe_config->port_clock) | |
2d112de7 | 12395 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12396 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12397 | |
a43f6e0f | 12398 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12399 | if (ret < 0) { |
7758a113 DV |
12400 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12401 | goto fail; | |
ee7b9f93 | 12402 | } |
e29c22c0 DV |
12403 | |
12404 | if (ret == RETRY) { | |
12405 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12406 | ret = -EINVAL; | |
12407 | goto fail; | |
12408 | } | |
12409 | ||
12410 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12411 | retry = false; | |
12412 | goto encoder_retry; | |
12413 | } | |
12414 | ||
e8fa4270 DV |
12415 | /* Dithering seems to not pass-through bits correctly when it should, so |
12416 | * only enable it on 6bpc panels. */ | |
12417 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12418 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12419 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12420 | |
7758a113 | 12421 | fail: |
548ee15b | 12422 | return ret; |
ee7b9f93 | 12423 | } |
47f1c6c9 | 12424 | |
ea9d758d | 12425 | static void |
4740b0f2 | 12426 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12427 | { |
0a9ab303 ACO |
12428 | struct drm_crtc *crtc; |
12429 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12430 | int i; |
ea9d758d | 12431 | |
7668851f | 12432 | /* Double check state. */ |
8a75d157 | 12433 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12434 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12435 | |
12436 | /* Update hwmode for vblank functions */ | |
12437 | if (crtc->state->active) | |
12438 | crtc->hwmode = crtc->state->adjusted_mode; | |
12439 | else | |
12440 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12441 | |
12442 | /* | |
12443 | * Update legacy state to satisfy fbc code. This can | |
12444 | * be removed when fbc uses the atomic state. | |
12445 | */ | |
12446 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12447 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12448 | ||
12449 | crtc->primary->fb = plane_state->fb; | |
12450 | crtc->x = plane_state->src_x >> 16; | |
12451 | crtc->y = plane_state->src_y >> 16; | |
12452 | } | |
ea9d758d | 12453 | } |
ea9d758d DV |
12454 | } |
12455 | ||
3bd26263 | 12456 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12457 | { |
3bd26263 | 12458 | int diff; |
f1f644dc JB |
12459 | |
12460 | if (clock1 == clock2) | |
12461 | return true; | |
12462 | ||
12463 | if (!clock1 || !clock2) | |
12464 | return false; | |
12465 | ||
12466 | diff = abs(clock1 - clock2); | |
12467 | ||
12468 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12469 | return true; | |
12470 | ||
12471 | return false; | |
12472 | } | |
12473 | ||
25c5b266 DV |
12474 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12475 | list_for_each_entry((intel_crtc), \ | |
12476 | &(dev)->mode_config.crtc_list, \ | |
12477 | base.head) \ | |
95150bdf | 12478 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12479 | |
cfb23ed6 ML |
12480 | static bool |
12481 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12482 | unsigned int m2, unsigned int n2, | |
12483 | bool exact) | |
12484 | { | |
12485 | if (m == m2 && n == n2) | |
12486 | return true; | |
12487 | ||
12488 | if (exact || !m || !n || !m2 || !n2) | |
12489 | return false; | |
12490 | ||
12491 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12492 | ||
31d10b57 ML |
12493 | if (n > n2) { |
12494 | while (n > n2) { | |
cfb23ed6 ML |
12495 | m2 <<= 1; |
12496 | n2 <<= 1; | |
12497 | } | |
31d10b57 ML |
12498 | } else if (n < n2) { |
12499 | while (n < n2) { | |
cfb23ed6 ML |
12500 | m <<= 1; |
12501 | n <<= 1; | |
12502 | } | |
12503 | } | |
12504 | ||
31d10b57 ML |
12505 | if (n != n2) |
12506 | return false; | |
12507 | ||
12508 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12509 | } |
12510 | ||
12511 | static bool | |
12512 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12513 | struct intel_link_m_n *m2_n2, | |
12514 | bool adjust) | |
12515 | { | |
12516 | if (m_n->tu == m2_n2->tu && | |
12517 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12518 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12519 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12520 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12521 | if (adjust) | |
12522 | *m2_n2 = *m_n; | |
12523 | ||
12524 | return true; | |
12525 | } | |
12526 | ||
12527 | return false; | |
12528 | } | |
12529 | ||
0e8ffe1b | 12530 | static bool |
2fa2fe9a | 12531 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12532 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12533 | struct intel_crtc_state *pipe_config, |
12534 | bool adjust) | |
0e8ffe1b | 12535 | { |
cfb23ed6 ML |
12536 | bool ret = true; |
12537 | ||
12538 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12539 | do { \ | |
12540 | if (!adjust) \ | |
12541 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12542 | else \ | |
12543 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12544 | } while (0) | |
12545 | ||
66e985c0 DV |
12546 | #define PIPE_CONF_CHECK_X(name) \ |
12547 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12548 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12549 | "(expected 0x%08x, found 0x%08x)\n", \ |
12550 | current_config->name, \ | |
12551 | pipe_config->name); \ | |
cfb23ed6 | 12552 | ret = false; \ |
66e985c0 DV |
12553 | } |
12554 | ||
08a24034 DV |
12555 | #define PIPE_CONF_CHECK_I(name) \ |
12556 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12557 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12558 | "(expected %i, found %i)\n", \ |
12559 | current_config->name, \ | |
12560 | pipe_config->name); \ | |
cfb23ed6 ML |
12561 | ret = false; \ |
12562 | } | |
12563 | ||
12564 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12565 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12566 | &pipe_config->name,\ | |
12567 | adjust)) { \ | |
12568 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12569 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12570 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12571 | current_config->name.tu, \ | |
12572 | current_config->name.gmch_m, \ | |
12573 | current_config->name.gmch_n, \ | |
12574 | current_config->name.link_m, \ | |
12575 | current_config->name.link_n, \ | |
12576 | pipe_config->name.tu, \ | |
12577 | pipe_config->name.gmch_m, \ | |
12578 | pipe_config->name.gmch_n, \ | |
12579 | pipe_config->name.link_m, \ | |
12580 | pipe_config->name.link_n); \ | |
12581 | ret = false; \ | |
12582 | } | |
12583 | ||
12584 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12585 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12586 | &pipe_config->name, adjust) && \ | |
12587 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12588 | &pipe_config->name, adjust)) { \ | |
12589 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12590 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12591 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12592 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12593 | current_config->name.tu, \ | |
12594 | current_config->name.gmch_m, \ | |
12595 | current_config->name.gmch_n, \ | |
12596 | current_config->name.link_m, \ | |
12597 | current_config->name.link_n, \ | |
12598 | current_config->alt_name.tu, \ | |
12599 | current_config->alt_name.gmch_m, \ | |
12600 | current_config->alt_name.gmch_n, \ | |
12601 | current_config->alt_name.link_m, \ | |
12602 | current_config->alt_name.link_n, \ | |
12603 | pipe_config->name.tu, \ | |
12604 | pipe_config->name.gmch_m, \ | |
12605 | pipe_config->name.gmch_n, \ | |
12606 | pipe_config->name.link_m, \ | |
12607 | pipe_config->name.link_n); \ | |
12608 | ret = false; \ | |
88adfff1 DV |
12609 | } |
12610 | ||
b95af8be VK |
12611 | /* This is required for BDW+ where there is only one set of registers for |
12612 | * switching between high and low RR. | |
12613 | * This macro can be used whenever a comparison has to be made between one | |
12614 | * hw state and multiple sw state variables. | |
12615 | */ | |
12616 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12617 | if ((current_config->name != pipe_config->name) && \ | |
12618 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12619 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12620 | "(expected %i or %i, found %i)\n", \ |
12621 | current_config->name, \ | |
12622 | current_config->alt_name, \ | |
12623 | pipe_config->name); \ | |
cfb23ed6 | 12624 | ret = false; \ |
b95af8be VK |
12625 | } |
12626 | ||
1bd1bd80 DV |
12627 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12628 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12629 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12630 | "(expected %i, found %i)\n", \ |
12631 | current_config->name & (mask), \ | |
12632 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12633 | ret = false; \ |
1bd1bd80 DV |
12634 | } |
12635 | ||
5e550656 VS |
12636 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12637 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12638 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12639 | "(expected %i, found %i)\n", \ |
12640 | current_config->name, \ | |
12641 | pipe_config->name); \ | |
cfb23ed6 | 12642 | ret = false; \ |
5e550656 VS |
12643 | } |
12644 | ||
bb760063 DV |
12645 | #define PIPE_CONF_QUIRK(quirk) \ |
12646 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12647 | ||
eccb140b DV |
12648 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12649 | ||
08a24034 DV |
12650 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12651 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12652 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12653 | |
eb14cb74 | 12654 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12655 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12656 | |
12657 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12658 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12659 | ||
cfb23ed6 ML |
12660 | if (current_config->has_drrs) |
12661 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12662 | } else | |
12663 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12664 | |
a65347ba JN |
12665 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12666 | ||
2d112de7 ACO |
12667 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12668 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12669 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12670 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12671 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12672 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12673 | |
2d112de7 ACO |
12674 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12675 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12676 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12677 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12678 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12679 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12680 | |
c93f54cf | 12681 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12682 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12683 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12684 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12685 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12686 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12687 | |
9ed109a7 DV |
12688 | PIPE_CONF_CHECK_I(has_audio); |
12689 | ||
2d112de7 | 12690 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12691 | DRM_MODE_FLAG_INTERLACE); |
12692 | ||
bb760063 | 12693 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12694 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12695 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12696 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12697 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12698 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12699 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12700 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12701 | DRM_MODE_FLAG_NVSYNC); |
12702 | } | |
045ac3b5 | 12703 | |
333b8ca8 | 12704 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12705 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12706 | if (INTEL_INFO(dev)->gen < 4) | |
12707 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12708 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12709 | |
bfd16b2a ML |
12710 | if (!adjust) { |
12711 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12712 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12713 | ||
12714 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12715 | if (current_config->pch_pfit.enabled) { | |
12716 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12717 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12718 | } | |
2fa2fe9a | 12719 | |
7aefe2b5 ML |
12720 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12721 | } | |
a1b2278e | 12722 | |
e59150dc JB |
12723 | /* BDW+ don't expose a synchronous way to read the state */ |
12724 | if (IS_HASWELL(dev)) | |
12725 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12726 | |
282740f7 VS |
12727 | PIPE_CONF_CHECK_I(double_wide); |
12728 | ||
26804afd DV |
12729 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12730 | ||
c0d43d62 | 12731 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12732 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12733 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12734 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12735 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12736 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12737 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12738 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12739 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12740 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12741 | |
42571aef VS |
12742 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12743 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12744 | ||
2d112de7 | 12745 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12746 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12747 | |
66e985c0 | 12748 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12749 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12750 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12751 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12752 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12753 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12754 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12755 | |
cfb23ed6 | 12756 | return ret; |
0e8ffe1b DV |
12757 | } |
12758 | ||
08db6652 DL |
12759 | static void check_wm_state(struct drm_device *dev) |
12760 | { | |
12761 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12762 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12763 | struct intel_crtc *intel_crtc; | |
12764 | int plane; | |
12765 | ||
12766 | if (INTEL_INFO(dev)->gen < 9) | |
12767 | return; | |
12768 | ||
12769 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12770 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12771 | ||
12772 | for_each_intel_crtc(dev, intel_crtc) { | |
12773 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12774 | const enum pipe pipe = intel_crtc->pipe; | |
12775 | ||
12776 | if (!intel_crtc->active) | |
12777 | continue; | |
12778 | ||
12779 | /* planes */ | |
dd740780 | 12780 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12781 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12782 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12783 | ||
12784 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12785 | continue; | |
12786 | ||
12787 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12788 | "(expected (%u,%u), found (%u,%u))\n", | |
12789 | pipe_name(pipe), plane + 1, | |
12790 | sw_entry->start, sw_entry->end, | |
12791 | hw_entry->start, hw_entry->end); | |
12792 | } | |
12793 | ||
12794 | /* cursor */ | |
4969d33e MR |
12795 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12796 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12797 | |
12798 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12799 | continue; | |
12800 | ||
12801 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12802 | "(expected (%u,%u), found (%u,%u))\n", | |
12803 | pipe_name(pipe), | |
12804 | sw_entry->start, sw_entry->end, | |
12805 | hw_entry->start, hw_entry->end); | |
12806 | } | |
12807 | } | |
12808 | ||
91d1b4bd | 12809 | static void |
35dd3c64 ML |
12810 | check_connector_state(struct drm_device *dev, |
12811 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12812 | { |
35dd3c64 ML |
12813 | struct drm_connector_state *old_conn_state; |
12814 | struct drm_connector *connector; | |
12815 | int i; | |
8af6cf88 | 12816 | |
35dd3c64 ML |
12817 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12818 | struct drm_encoder *encoder = connector->encoder; | |
12819 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12820 | |
8af6cf88 DV |
12821 | /* This also checks the encoder/connector hw state with the |
12822 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12823 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12824 | |
ad3c558f | 12825 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12826 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12827 | } |
91d1b4bd DV |
12828 | } |
12829 | ||
12830 | static void | |
12831 | check_encoder_state(struct drm_device *dev) | |
12832 | { | |
12833 | struct intel_encoder *encoder; | |
12834 | struct intel_connector *connector; | |
8af6cf88 | 12835 | |
b2784e15 | 12836 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12837 | bool enabled = false; |
4d20cd86 | 12838 | enum pipe pipe; |
8af6cf88 DV |
12839 | |
12840 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12841 | encoder->base.base.id, | |
8e329a03 | 12842 | encoder->base.name); |
8af6cf88 | 12843 | |
3a3371ff | 12844 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12845 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12846 | continue; |
12847 | enabled = true; | |
ad3c558f ML |
12848 | |
12849 | I915_STATE_WARN(connector->base.state->crtc != | |
12850 | encoder->base.crtc, | |
12851 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12852 | } |
0e32b39c | 12853 | |
e2c719b7 | 12854 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12855 | "encoder's enabled state mismatch " |
12856 | "(expected %i, found %i)\n", | |
12857 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12858 | |
12859 | if (!encoder->base.crtc) { | |
4d20cd86 | 12860 | bool active; |
7c60d198 | 12861 | |
4d20cd86 ML |
12862 | active = encoder->get_hw_state(encoder, &pipe); |
12863 | I915_STATE_WARN(active, | |
12864 | "encoder detached but still enabled on pipe %c.\n", | |
12865 | pipe_name(pipe)); | |
7c60d198 | 12866 | } |
8af6cf88 | 12867 | } |
91d1b4bd DV |
12868 | } |
12869 | ||
12870 | static void | |
4d20cd86 | 12871 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12872 | { |
fbee40df | 12873 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12874 | struct intel_encoder *encoder; |
4d20cd86 ML |
12875 | struct drm_crtc_state *old_crtc_state; |
12876 | struct drm_crtc *crtc; | |
12877 | int i; | |
8af6cf88 | 12878 | |
4d20cd86 ML |
12879 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
12880 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12881 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 12882 | bool active; |
8af6cf88 | 12883 | |
bfd16b2a ML |
12884 | if (!needs_modeset(crtc->state) && |
12885 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 12886 | continue; |
045ac3b5 | 12887 | |
4d20cd86 ML |
12888 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
12889 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12890 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12891 | pipe_config->base.crtc = crtc; | |
12892 | pipe_config->base.state = old_state; | |
8af6cf88 | 12893 | |
4d20cd86 ML |
12894 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12895 | crtc->base.id); | |
8af6cf88 | 12896 | |
4d20cd86 ML |
12897 | active = dev_priv->display.get_pipe_config(intel_crtc, |
12898 | pipe_config); | |
d62cf62a | 12899 | |
b6b5d049 | 12900 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
12901 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
12902 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12903 | active = crtc->state->active; | |
6c49f241 | 12904 | |
4d20cd86 | 12905 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 12906 | "crtc active state doesn't match with hw state " |
4d20cd86 | 12907 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 12908 | |
4d20cd86 | 12909 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 12910 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
12911 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
12912 | ||
12913 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
12914 | enum pipe pipe; | |
12915 | ||
12916 | active = encoder->get_hw_state(encoder, &pipe); | |
12917 | I915_STATE_WARN(active != crtc->state->active, | |
12918 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12919 | encoder->base.base.id, active, crtc->state->active); | |
12920 | ||
12921 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
12922 | "Encoder connected to wrong pipe %c\n", | |
12923 | pipe_name(pipe)); | |
12924 | ||
12925 | if (active) | |
12926 | encoder->get_config(encoder, pipe_config); | |
12927 | } | |
53d9f4e9 | 12928 | |
4d20cd86 | 12929 | if (!crtc->state->active) |
cfb23ed6 ML |
12930 | continue; |
12931 | ||
4d20cd86 ML |
12932 | sw_config = to_intel_crtc_state(crtc->state); |
12933 | if (!intel_pipe_config_compare(dev, sw_config, | |
12934 | pipe_config, false)) { | |
e2c719b7 | 12935 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 12936 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 12937 | "[hw state]"); |
4d20cd86 | 12938 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
12939 | "[sw state]"); |
12940 | } | |
8af6cf88 DV |
12941 | } |
12942 | } | |
12943 | ||
91d1b4bd DV |
12944 | static void |
12945 | check_shared_dpll_state(struct drm_device *dev) | |
12946 | { | |
fbee40df | 12947 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12948 | struct intel_crtc *crtc; |
12949 | struct intel_dpll_hw_state dpll_hw_state; | |
12950 | int i; | |
5358901f DV |
12951 | |
12952 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12953 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12954 | int enabled_crtcs = 0, active_crtcs = 0; | |
12955 | bool active; | |
12956 | ||
12957 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12958 | ||
12959 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12960 | ||
12961 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12962 | ||
e2c719b7 | 12963 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12964 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12965 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12966 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12967 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12968 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12969 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12970 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12971 | "pll on state mismatch (expected %i, found %i)\n", |
12972 | pll->on, active); | |
12973 | ||
d3fcc808 | 12974 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12975 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
12976 | enabled_crtcs++; |
12977 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
12978 | active_crtcs++; | |
12979 | } | |
e2c719b7 | 12980 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
12981 | "pll active crtcs mismatch (expected %i, found %i)\n", |
12982 | pll->active, active_crtcs); | |
e2c719b7 | 12983 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 12984 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 12985 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 12986 | |
e2c719b7 | 12987 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12988 | sizeof(dpll_hw_state)), |
12989 | "pll hw state mismatch\n"); | |
5358901f | 12990 | } |
8af6cf88 DV |
12991 | } |
12992 | ||
ee165b1a ML |
12993 | static void |
12994 | intel_modeset_check_state(struct drm_device *dev, | |
12995 | struct drm_atomic_state *old_state) | |
91d1b4bd | 12996 | { |
08db6652 | 12997 | check_wm_state(dev); |
35dd3c64 | 12998 | check_connector_state(dev, old_state); |
91d1b4bd | 12999 | check_encoder_state(dev); |
4d20cd86 | 13000 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
13001 | check_shared_dpll_state(dev); |
13002 | } | |
13003 | ||
5cec258b | 13004 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
13005 | int dotclock) |
13006 | { | |
13007 | /* | |
13008 | * FDI already provided one idea for the dotclock. | |
13009 | * Yell if the encoder disagrees. | |
13010 | */ | |
2d112de7 | 13011 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 13012 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 13013 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
13014 | } |
13015 | ||
80715b2f VS |
13016 | static void update_scanline_offset(struct intel_crtc *crtc) |
13017 | { | |
13018 | struct drm_device *dev = crtc->base.dev; | |
13019 | ||
13020 | /* | |
13021 | * The scanline counter increments at the leading edge of hsync. | |
13022 | * | |
13023 | * On most platforms it starts counting from vtotal-1 on the | |
13024 | * first active line. That means the scanline counter value is | |
13025 | * always one less than what we would expect. Ie. just after | |
13026 | * start of vblank, which also occurs at start of hsync (on the | |
13027 | * last active line), the scanline counter will read vblank_start-1. | |
13028 | * | |
13029 | * On gen2 the scanline counter starts counting from 1 instead | |
13030 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13031 | * to keep the value positive), instead of adding one. | |
13032 | * | |
13033 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13034 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13035 | * there's an extra 1 line difference. So we need to add two instead of | |
13036 | * one to the value. | |
13037 | */ | |
13038 | if (IS_GEN2(dev)) { | |
124abe07 | 13039 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13040 | int vtotal; |
13041 | ||
124abe07 VS |
13042 | vtotal = adjusted_mode->crtc_vtotal; |
13043 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13044 | vtotal /= 2; |
13045 | ||
13046 | crtc->scanline_offset = vtotal - 1; | |
13047 | } else if (HAS_DDI(dev) && | |
409ee761 | 13048 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13049 | crtc->scanline_offset = 2; |
13050 | } else | |
13051 | crtc->scanline_offset = 1; | |
13052 | } | |
13053 | ||
ad421372 | 13054 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13055 | { |
225da59b | 13056 | struct drm_device *dev = state->dev; |
ed6739ef | 13057 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13058 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13059 | struct drm_crtc *crtc; |
13060 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13061 | int i; |
ed6739ef ACO |
13062 | |
13063 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13064 | return; |
ed6739ef | 13065 | |
0a9ab303 | 13066 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 ML |
13067 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13068 | int old_dpll = to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13069 | |
fb1a38a9 | 13070 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13071 | continue; |
13072 | ||
fb1a38a9 ML |
13073 | to_intel_crtc_state(crtc_state)->shared_dpll = DPLL_ID_PRIVATE; |
13074 | ||
13075 | if (old_dpll == DPLL_ID_PRIVATE) | |
13076 | continue; | |
0a9ab303 | 13077 | |
ad421372 ML |
13078 | if (!shared_dpll) |
13079 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13080 | |
fb1a38a9 | 13081 | shared_dpll[old_dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
ad421372 | 13082 | } |
ed6739ef ACO |
13083 | } |
13084 | ||
99d736a2 ML |
13085 | /* |
13086 | * This implements the workaround described in the "notes" section of the mode | |
13087 | * set sequence documentation. When going from no pipes or single pipe to | |
13088 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13089 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13090 | */ | |
13091 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13092 | { | |
13093 | struct drm_crtc_state *crtc_state; | |
13094 | struct intel_crtc *intel_crtc; | |
13095 | struct drm_crtc *crtc; | |
13096 | struct intel_crtc_state *first_crtc_state = NULL; | |
13097 | struct intel_crtc_state *other_crtc_state = NULL; | |
13098 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13099 | int i; | |
13100 | ||
13101 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13102 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13103 | intel_crtc = to_intel_crtc(crtc); | |
13104 | ||
13105 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13106 | continue; | |
13107 | ||
13108 | if (first_crtc_state) { | |
13109 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13110 | break; | |
13111 | } else { | |
13112 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13113 | first_pipe = intel_crtc->pipe; | |
13114 | } | |
13115 | } | |
13116 | ||
13117 | /* No workaround needed? */ | |
13118 | if (!first_crtc_state) | |
13119 | return 0; | |
13120 | ||
13121 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13122 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13123 | struct intel_crtc_state *pipe_config; | |
13124 | ||
13125 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13126 | if (IS_ERR(pipe_config)) | |
13127 | return PTR_ERR(pipe_config); | |
13128 | ||
13129 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13130 | ||
13131 | if (!pipe_config->base.active || | |
13132 | needs_modeset(&pipe_config->base)) | |
13133 | continue; | |
13134 | ||
13135 | /* 2 or more enabled crtcs means no need for w/a */ | |
13136 | if (enabled_pipe != INVALID_PIPE) | |
13137 | return 0; | |
13138 | ||
13139 | enabled_pipe = intel_crtc->pipe; | |
13140 | } | |
13141 | ||
13142 | if (enabled_pipe != INVALID_PIPE) | |
13143 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13144 | else if (other_crtc_state) | |
13145 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13146 | ||
13147 | return 0; | |
13148 | } | |
13149 | ||
27c329ed ML |
13150 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13151 | { | |
13152 | struct drm_crtc *crtc; | |
13153 | struct drm_crtc_state *crtc_state; | |
13154 | int ret = 0; | |
13155 | ||
13156 | /* add all active pipes to the state */ | |
13157 | for_each_crtc(state->dev, crtc) { | |
13158 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13159 | if (IS_ERR(crtc_state)) | |
13160 | return PTR_ERR(crtc_state); | |
13161 | ||
13162 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13163 | continue; | |
13164 | ||
13165 | crtc_state->mode_changed = true; | |
13166 | ||
13167 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13168 | if (ret) | |
13169 | break; | |
13170 | ||
13171 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13172 | if (ret) | |
13173 | break; | |
13174 | } | |
13175 | ||
13176 | return ret; | |
13177 | } | |
13178 | ||
c347a676 | 13179 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13180 | { |
565602d7 ML |
13181 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13182 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13183 | struct drm_crtc *crtc; | |
13184 | struct drm_crtc_state *crtc_state; | |
13185 | int ret = 0, i; | |
054518dd | 13186 | |
b359283a ML |
13187 | if (!check_digital_port_conflicts(state)) { |
13188 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13189 | return -EINVAL; | |
13190 | } | |
13191 | ||
565602d7 ML |
13192 | intel_state->modeset = true; |
13193 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13194 | ||
13195 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13196 | if (crtc_state->active) | |
13197 | intel_state->active_crtcs |= 1 << i; | |
13198 | else | |
13199 | intel_state->active_crtcs &= ~(1 << i); | |
13200 | } | |
13201 | ||
054518dd ACO |
13202 | /* |
13203 | * See if the config requires any additional preparation, e.g. | |
13204 | * to adjust global state with pipes off. We need to do this | |
13205 | * here so we can get the modeset_pipe updated config for the new | |
13206 | * mode set on this crtc. For other crtcs we need to use the | |
13207 | * adjusted_mode bits in the crtc directly. | |
13208 | */ | |
27c329ed | 13209 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed ML |
13210 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13211 | ||
1a617b77 | 13212 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
27c329ed ML |
13213 | ret = intel_modeset_all_pipes(state); |
13214 | ||
13215 | if (ret < 0) | |
054518dd | 13216 | return ret; |
e8788cbc ML |
13217 | |
13218 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13219 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13220 | } else |
1a617b77 | 13221 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13222 | |
ad421372 | 13223 | intel_modeset_clear_plls(state); |
054518dd | 13224 | |
565602d7 | 13225 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13226 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13227 | |
ad421372 | 13228 | return 0; |
c347a676 ACO |
13229 | } |
13230 | ||
aa363136 MR |
13231 | /* |
13232 | * Handle calculation of various watermark data at the end of the atomic check | |
13233 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13234 | * handlers to ensure that all derived state has been updated. | |
13235 | */ | |
13236 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13237 | { | |
13238 | struct drm_device *dev = state->dev; | |
13239 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13240 | struct drm_crtc *crtc; | |
13241 | struct drm_crtc_state *cstate; | |
13242 | struct drm_plane *plane; | |
13243 | struct drm_plane_state *pstate; | |
13244 | ||
13245 | /* | |
13246 | * Calculate watermark configuration details now that derived | |
13247 | * plane/crtc state is all properly updated. | |
13248 | */ | |
13249 | drm_for_each_crtc(crtc, dev) { | |
13250 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13251 | crtc->state; | |
13252 | ||
13253 | if (cstate->active) | |
13254 | intel_state->wm_config.num_pipes_active++; | |
13255 | } | |
13256 | drm_for_each_legacy_plane(plane, dev) { | |
13257 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13258 | plane->state; | |
13259 | ||
13260 | if (!to_intel_plane_state(pstate)->visible) | |
13261 | continue; | |
13262 | ||
13263 | intel_state->wm_config.sprites_enabled = true; | |
13264 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13265 | pstate->crtc_h != pstate->src_h >> 16) | |
13266 | intel_state->wm_config.sprites_scaled = true; | |
13267 | } | |
13268 | } | |
13269 | ||
74c090b1 ML |
13270 | /** |
13271 | * intel_atomic_check - validate state object | |
13272 | * @dev: drm device | |
13273 | * @state: state to validate | |
13274 | */ | |
13275 | static int intel_atomic_check(struct drm_device *dev, | |
13276 | struct drm_atomic_state *state) | |
c347a676 | 13277 | { |
dd8b3bdb | 13278 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13279 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13280 | struct drm_crtc *crtc; |
13281 | struct drm_crtc_state *crtc_state; | |
13282 | int ret, i; | |
61333b60 | 13283 | bool any_ms = false; |
c347a676 | 13284 | |
74c090b1 | 13285 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13286 | if (ret) |
13287 | return ret; | |
13288 | ||
c347a676 | 13289 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13290 | struct intel_crtc_state *pipe_config = |
13291 | to_intel_crtc_state(crtc_state); | |
1ed51de9 | 13292 | |
ba8af3e5 ML |
13293 | memset(&to_intel_crtc(crtc)->atomic, 0, |
13294 | sizeof(struct intel_crtc_atomic_commit)); | |
13295 | ||
1ed51de9 DV |
13296 | /* Catch I915_MODE_FLAG_INHERITED */ |
13297 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13298 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13299 | |
61333b60 ML |
13300 | if (!crtc_state->enable) { |
13301 | if (needs_modeset(crtc_state)) | |
13302 | any_ms = true; | |
c347a676 | 13303 | continue; |
61333b60 | 13304 | } |
c347a676 | 13305 | |
26495481 | 13306 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13307 | continue; |
13308 | ||
26495481 DV |
13309 | /* FIXME: For only active_changed we shouldn't need to do any |
13310 | * state recomputation at all. */ | |
13311 | ||
1ed51de9 DV |
13312 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13313 | if (ret) | |
13314 | return ret; | |
b359283a | 13315 | |
cfb23ed6 | 13316 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13317 | if (ret) |
13318 | return ret; | |
13319 | ||
73831236 | 13320 | if (i915.fastboot && |
dd8b3bdb | 13321 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13322 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13323 | pipe_config, true)) { |
26495481 | 13324 | crtc_state->mode_changed = false; |
bfd16b2a | 13325 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13326 | } |
13327 | ||
13328 | if (needs_modeset(crtc_state)) { | |
13329 | any_ms = true; | |
cfb23ed6 ML |
13330 | |
13331 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13332 | if (ret) | |
13333 | return ret; | |
13334 | } | |
61333b60 | 13335 | |
26495481 DV |
13336 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13337 | needs_modeset(crtc_state) ? | |
13338 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13339 | } |
13340 | ||
61333b60 ML |
13341 | if (any_ms) { |
13342 | ret = intel_modeset_checks(state); | |
13343 | ||
13344 | if (ret) | |
13345 | return ret; | |
27c329ed | 13346 | } else |
dd8b3bdb | 13347 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13348 | |
dd8b3bdb | 13349 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13350 | if (ret) |
13351 | return ret; | |
13352 | ||
f51be2e0 | 13353 | intel_fbc_choose_crtc(dev_priv, state); |
aa363136 MR |
13354 | calc_watermark_data(state); |
13355 | ||
13356 | return 0; | |
054518dd ACO |
13357 | } |
13358 | ||
5008e874 ML |
13359 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13360 | struct drm_atomic_state *state, | |
13361 | bool async) | |
13362 | { | |
7580d774 ML |
13363 | struct drm_i915_private *dev_priv = dev->dev_private; |
13364 | struct drm_plane_state *plane_state; | |
5008e874 | 13365 | struct drm_crtc_state *crtc_state; |
7580d774 | 13366 | struct drm_plane *plane; |
5008e874 ML |
13367 | struct drm_crtc *crtc; |
13368 | int i, ret; | |
13369 | ||
13370 | if (async) { | |
13371 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13372 | return -EINVAL; | |
13373 | } | |
13374 | ||
13375 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13376 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13377 | if (ret) | |
13378 | return ret; | |
7580d774 ML |
13379 | |
13380 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13381 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13382 | } |
13383 | ||
f935675f ML |
13384 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13385 | if (ret) | |
13386 | return ret; | |
13387 | ||
5008e874 | 13388 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13389 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13390 | u32 reset_counter; | |
13391 | ||
13392 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13393 | mutex_unlock(&dev->struct_mutex); | |
13394 | ||
13395 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13396 | struct intel_plane_state *intel_plane_state = | |
13397 | to_intel_plane_state(plane_state); | |
13398 | ||
13399 | if (!intel_plane_state->wait_req) | |
13400 | continue; | |
13401 | ||
13402 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13403 | reset_counter, true, | |
13404 | NULL, NULL); | |
13405 | ||
13406 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13407 | if (ret == -EIO) | |
13408 | ret = 0; | |
13409 | ||
13410 | if (ret) | |
13411 | break; | |
13412 | } | |
13413 | ||
13414 | if (!ret) | |
13415 | return 0; | |
13416 | ||
13417 | mutex_lock(&dev->struct_mutex); | |
13418 | drm_atomic_helper_cleanup_planes(dev, state); | |
13419 | } | |
5008e874 | 13420 | |
f935675f | 13421 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13422 | return ret; |
13423 | } | |
13424 | ||
74c090b1 ML |
13425 | /** |
13426 | * intel_atomic_commit - commit validated state object | |
13427 | * @dev: DRM device | |
13428 | * @state: the top-level driver state object | |
13429 | * @async: asynchronous commit | |
13430 | * | |
13431 | * This function commits a top-level state object that has been validated | |
13432 | * with drm_atomic_helper_check(). | |
13433 | * | |
13434 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13435 | * we can only handle plane-related operations and do not yet support | |
13436 | * asynchronous commit. | |
13437 | * | |
13438 | * RETURNS | |
13439 | * Zero for success or -errno. | |
13440 | */ | |
13441 | static int intel_atomic_commit(struct drm_device *dev, | |
13442 | struct drm_atomic_state *state, | |
13443 | bool async) | |
a6778b3c | 13444 | { |
565602d7 | 13445 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13446 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 | 13447 | struct drm_crtc_state *crtc_state; |
7580d774 | 13448 | struct drm_crtc *crtc; |
565602d7 ML |
13449 | int ret = 0, i; |
13450 | bool hw_check = intel_state->modeset; | |
a6778b3c | 13451 | |
5008e874 | 13452 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13453 | if (ret) { |
13454 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13455 | return ret; |
7580d774 | 13456 | } |
d4afb8cc | 13457 | |
1c5e19f8 | 13458 | drm_atomic_helper_swap_state(dev, state); |
aa363136 | 13459 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
1c5e19f8 | 13460 | |
565602d7 ML |
13461 | if (intel_state->modeset) { |
13462 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13463 | sizeof(intel_state->min_pixclk)); | |
13464 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13465 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
565602d7 ML |
13466 | } |
13467 | ||
0a9ab303 | 13468 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13469 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13470 | ||
61333b60 ML |
13471 | if (!needs_modeset(crtc->state)) |
13472 | continue; | |
13473 | ||
5c74cd73 | 13474 | intel_pre_plane_update(to_intel_crtc_state(crtc_state)); |
460da916 | 13475 | |
a539205a ML |
13476 | if (crtc_state->active) { |
13477 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13478 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd | 13479 | intel_crtc->active = false; |
58f9c0bc | 13480 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13481 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13482 | |
13483 | /* | |
13484 | * Underruns don't always raise | |
13485 | * interrupts, so check manually. | |
13486 | */ | |
13487 | intel_check_cpu_fifo_underruns(dev_priv); | |
13488 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13489 | |
13490 | if (!crtc->state->active) | |
13491 | intel_update_watermarks(crtc); | |
a539205a | 13492 | } |
b8cecdf5 | 13493 | } |
7758a113 | 13494 | |
ea9d758d DV |
13495 | /* Only after disabling all output pipelines that will be changed can we |
13496 | * update the the output configuration. */ | |
4740b0f2 | 13497 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13498 | |
565602d7 | 13499 | if (intel_state->modeset) { |
4740b0f2 ML |
13500 | intel_shared_dpll_commit(state); |
13501 | ||
13502 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
61333b60 | 13503 | modeset_update_crtc_power_domains(state); |
4740b0f2 | 13504 | } |
47fab737 | 13505 | |
a6778b3c | 13506 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13507 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
f6ac4b2a ML |
13508 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13509 | bool modeset = needs_modeset(crtc->state); | |
bfd16b2a ML |
13510 | bool update_pipe = !modeset && |
13511 | to_intel_crtc_state(crtc->state)->update_pipe; | |
13512 | unsigned long put_domains = 0; | |
f6ac4b2a | 13513 | |
9f836f90 PJ |
13514 | if (modeset) |
13515 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
13516 | ||
f6ac4b2a | 13517 | if (modeset && crtc->state->active) { |
a539205a ML |
13518 | update_scanline_offset(to_intel_crtc(crtc)); |
13519 | dev_priv->display.crtc_enable(crtc); | |
13520 | } | |
80715b2f | 13521 | |
bfd16b2a ML |
13522 | if (update_pipe) { |
13523 | put_domains = modeset_get_crtc_power_domains(crtc); | |
13524 | ||
13525 | /* make sure intel_modeset_check_state runs */ | |
565602d7 | 13526 | hw_check = true; |
bfd16b2a ML |
13527 | } |
13528 | ||
f6ac4b2a | 13529 | if (!modeset) |
5c74cd73 | 13530 | intel_pre_plane_update(to_intel_crtc_state(crtc_state)); |
f6ac4b2a | 13531 | |
49227c4a PZ |
13532 | if (crtc->state->active && intel_crtc->atomic.update_fbc) |
13533 | intel_fbc_enable(intel_crtc); | |
13534 | ||
6173ee28 ML |
13535 | if (crtc->state->active && |
13536 | (crtc->state->planes_changed || update_pipe)) | |
62852622 | 13537 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
bfd16b2a ML |
13538 | |
13539 | if (put_domains) | |
13540 | modeset_put_power_domains(dev_priv, put_domains); | |
13541 | ||
f6ac4b2a | 13542 | intel_post_plane_update(intel_crtc); |
9f836f90 PJ |
13543 | |
13544 | if (modeset) | |
13545 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
80715b2f | 13546 | } |
a6778b3c | 13547 | |
a6778b3c | 13548 | /* FIXME: add subpixel order */ |
83a57153 | 13549 | |
74c090b1 | 13550 | drm_atomic_helper_wait_for_vblanks(dev, state); |
f935675f ML |
13551 | |
13552 | mutex_lock(&dev->struct_mutex); | |
d4afb8cc | 13553 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13554 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13555 | |
565602d7 | 13556 | if (hw_check) |
ee165b1a ML |
13557 | intel_modeset_check_state(dev, state); |
13558 | ||
13559 | drm_atomic_state_free(state); | |
f30da187 | 13560 | |
75714940 MK |
13561 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13562 | * of triggering bugs in unclaimed access. After we finish | |
13563 | * modesetting, see if an error has been flagged, and if so | |
13564 | * enable debugging for the next modeset - and hope we catch | |
13565 | * the culprit. | |
13566 | * | |
13567 | * XXX note that we assume display power is on at this point. | |
13568 | * This might hold true now but we need to add pm helper to check | |
13569 | * unclaimed only when the hardware is on, as atomic commits | |
13570 | * can happen also when the device is completely off. | |
13571 | */ | |
13572 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
13573 | ||
74c090b1 | 13574 | return 0; |
7f27126e JB |
13575 | } |
13576 | ||
c0c36b94 CW |
13577 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13578 | { | |
83a57153 ACO |
13579 | struct drm_device *dev = crtc->dev; |
13580 | struct drm_atomic_state *state; | |
e694eb02 | 13581 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13582 | int ret; |
83a57153 ACO |
13583 | |
13584 | state = drm_atomic_state_alloc(dev); | |
13585 | if (!state) { | |
e694eb02 | 13586 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13587 | crtc->base.id); |
13588 | return; | |
13589 | } | |
13590 | ||
e694eb02 | 13591 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13592 | |
e694eb02 ML |
13593 | retry: |
13594 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13595 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13596 | if (!ret) { | |
13597 | if (!crtc_state->active) | |
13598 | goto out; | |
83a57153 | 13599 | |
e694eb02 | 13600 | crtc_state->mode_changed = true; |
74c090b1 | 13601 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13602 | } |
13603 | ||
e694eb02 ML |
13604 | if (ret == -EDEADLK) { |
13605 | drm_atomic_state_clear(state); | |
13606 | drm_modeset_backoff(state->acquire_ctx); | |
13607 | goto retry; | |
4ed9fb37 | 13608 | } |
4be07317 | 13609 | |
2bfb4627 | 13610 | if (ret) |
e694eb02 | 13611 | out: |
2bfb4627 | 13612 | drm_atomic_state_free(state); |
c0c36b94 CW |
13613 | } |
13614 | ||
25c5b266 DV |
13615 | #undef for_each_intel_crtc_masked |
13616 | ||
f6e5b160 | 13617 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 | 13618 | .gamma_set = intel_crtc_gamma_set, |
74c090b1 | 13619 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 CW |
13620 | .destroy = intel_crtc_destroy, |
13621 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13622 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13623 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13624 | }; |
13625 | ||
5358901f DV |
13626 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13627 | struct intel_shared_dpll *pll, | |
13628 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13629 | { |
5358901f | 13630 | uint32_t val; |
ee7b9f93 | 13631 | |
f458ebbc | 13632 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13633 | return false; |
13634 | ||
5358901f | 13635 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13636 | hw_state->dpll = val; |
13637 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13638 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13639 | |
13640 | return val & DPLL_VCO_ENABLE; | |
13641 | } | |
13642 | ||
15bdd4cf DV |
13643 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13644 | struct intel_shared_dpll *pll) | |
13645 | { | |
3e369b76 ACO |
13646 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13647 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13648 | } |
13649 | ||
e7b903d2 DV |
13650 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13651 | struct intel_shared_dpll *pll) | |
13652 | { | |
e7b903d2 | 13653 | /* PCH refclock must be enabled first */ |
89eff4be | 13654 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13655 | |
3e369b76 | 13656 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13657 | |
13658 | /* Wait for the clocks to stabilize. */ | |
13659 | POSTING_READ(PCH_DPLL(pll->id)); | |
13660 | udelay(150); | |
13661 | ||
13662 | /* The pixel multiplier can only be updated once the | |
13663 | * DPLL is enabled and the clocks are stable. | |
13664 | * | |
13665 | * So write it again. | |
13666 | */ | |
3e369b76 | 13667 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13668 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13669 | udelay(200); |
13670 | } | |
13671 | ||
13672 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13673 | struct intel_shared_dpll *pll) | |
13674 | { | |
13675 | struct drm_device *dev = dev_priv->dev; | |
13676 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13677 | |
13678 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13679 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13680 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13681 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13682 | } |
13683 | ||
15bdd4cf DV |
13684 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13685 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13686 | udelay(200); |
13687 | } | |
13688 | ||
46edb027 DV |
13689 | static char *ibx_pch_dpll_names[] = { |
13690 | "PCH DPLL A", | |
13691 | "PCH DPLL B", | |
13692 | }; | |
13693 | ||
7c74ade1 | 13694 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13695 | { |
e7b903d2 | 13696 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13697 | int i; |
13698 | ||
7c74ade1 | 13699 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13700 | |
e72f9fbf | 13701 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13702 | dev_priv->shared_dplls[i].id = i; |
13703 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13704 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13705 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13706 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13707 | dev_priv->shared_dplls[i].get_hw_state = |
13708 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13709 | } |
13710 | } | |
13711 | ||
7c74ade1 DV |
13712 | static void intel_shared_dpll_init(struct drm_device *dev) |
13713 | { | |
e7b903d2 | 13714 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13715 | |
9cd86933 DV |
13716 | if (HAS_DDI(dev)) |
13717 | intel_ddi_pll_init(dev); | |
13718 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13719 | ibx_pch_dpll_init(dev); |
13720 | else | |
13721 | dev_priv->num_shared_dpll = 0; | |
13722 | ||
13723 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13724 | } |
13725 | ||
6beb8c23 MR |
13726 | /** |
13727 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13728 | * @plane: drm plane to prepare for | |
13729 | * @fb: framebuffer to prepare for presentation | |
13730 | * | |
13731 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13732 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13733 | * bits. Some older platforms need special physical address handling for | |
13734 | * cursor planes. | |
13735 | * | |
f935675f ML |
13736 | * Must be called with struct_mutex held. |
13737 | * | |
6beb8c23 MR |
13738 | * Returns 0 on success, negative error code on failure. |
13739 | */ | |
13740 | int | |
13741 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13742 | const struct drm_plane_state *new_state) |
465c120c MR |
13743 | { |
13744 | struct drm_device *dev = plane->dev; | |
844f9111 | 13745 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13746 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13747 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13748 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13749 | int ret = 0; |
465c120c | 13750 | |
1ee49399 | 13751 | if (!obj && !old_obj) |
465c120c MR |
13752 | return 0; |
13753 | ||
5008e874 ML |
13754 | if (old_obj) { |
13755 | struct drm_crtc_state *crtc_state = | |
13756 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13757 | ||
13758 | /* Big Hammer, we also need to ensure that any pending | |
13759 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13760 | * current scanout is retired before unpinning the old | |
13761 | * framebuffer. Note that we rely on userspace rendering | |
13762 | * into the buffer attached to the pipe they are waiting | |
13763 | * on. If not, userspace generates a GPU hang with IPEHR | |
13764 | * point to the MI_WAIT_FOR_EVENT. | |
13765 | * | |
13766 | * This should only fail upon a hung GPU, in which case we | |
13767 | * can safely continue. | |
13768 | */ | |
13769 | if (needs_modeset(crtc_state)) | |
13770 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
13771 | ||
13772 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13773 | if (ret && ret != -EIO) | |
f935675f | 13774 | return ret; |
5008e874 ML |
13775 | } |
13776 | ||
3c28ff22 AG |
13777 | /* For framebuffer backed by dmabuf, wait for fence */ |
13778 | if (obj && obj->base.dma_buf) { | |
bcf8be27 ML |
13779 | long lret; |
13780 | ||
13781 | lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13782 | false, true, | |
13783 | MAX_SCHEDULE_TIMEOUT); | |
13784 | if (lret == -ERESTARTSYS) | |
13785 | return lret; | |
3c28ff22 | 13786 | |
bcf8be27 | 13787 | WARN(lret < 0, "waiting returns %li\n", lret); |
3c28ff22 AG |
13788 | } |
13789 | ||
1ee49399 ML |
13790 | if (!obj) { |
13791 | ret = 0; | |
13792 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13793 | INTEL_INFO(dev)->cursor_needs_physical) { |
13794 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13795 | ret = i915_gem_object_attach_phys(obj, align); | |
13796 | if (ret) | |
13797 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13798 | } else { | |
7580d774 | 13799 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state); |
6beb8c23 | 13800 | } |
465c120c | 13801 | |
7580d774 ML |
13802 | if (ret == 0) { |
13803 | if (obj) { | |
13804 | struct intel_plane_state *plane_state = | |
13805 | to_intel_plane_state(new_state); | |
13806 | ||
13807 | i915_gem_request_assign(&plane_state->wait_req, | |
13808 | obj->last_write_req); | |
13809 | } | |
13810 | ||
a9ff8714 | 13811 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13812 | } |
fdd508a6 | 13813 | |
6beb8c23 MR |
13814 | return ret; |
13815 | } | |
13816 | ||
38f3ce3a MR |
13817 | /** |
13818 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13819 | * @plane: drm plane to clean up for | |
13820 | * @fb: old framebuffer that was on plane | |
13821 | * | |
13822 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13823 | * |
13824 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13825 | */ |
13826 | void | |
13827 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13828 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13829 | { |
13830 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13831 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13832 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13833 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13834 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13835 | |
7580d774 ML |
13836 | old_intel_state = to_intel_plane_state(old_state); |
13837 | ||
1ee49399 | 13838 | if (!obj && !old_obj) |
38f3ce3a MR |
13839 | return; |
13840 | ||
1ee49399 ML |
13841 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13842 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
844f9111 | 13843 | intel_unpin_fb_obj(old_state->fb, old_state); |
1ee49399 ML |
13844 | |
13845 | /* prepare_fb aborted? */ | |
13846 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13847 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13848 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13849 | |
13850 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
13851 | ||
465c120c MR |
13852 | } |
13853 | ||
6156a456 CK |
13854 | int |
13855 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13856 | { | |
13857 | int max_scale; | |
13858 | struct drm_device *dev; | |
13859 | struct drm_i915_private *dev_priv; | |
13860 | int crtc_clock, cdclk; | |
13861 | ||
bf8a0af0 | 13862 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13863 | return DRM_PLANE_HELPER_NO_SCALING; |
13864 | ||
13865 | dev = intel_crtc->base.dev; | |
13866 | dev_priv = dev->dev_private; | |
13867 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13868 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13869 | |
54bf1ce6 | 13870 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
13871 | return DRM_PLANE_HELPER_NO_SCALING; |
13872 | ||
13873 | /* | |
13874 | * skl max scale is lower of: | |
13875 | * close to 3 but not 3, -1 is for that purpose | |
13876 | * or | |
13877 | * cdclk/crtc_clock | |
13878 | */ | |
13879 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13880 | ||
13881 | return max_scale; | |
13882 | } | |
13883 | ||
465c120c | 13884 | static int |
3c692a41 | 13885 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13886 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13887 | struct intel_plane_state *state) |
13888 | { | |
2b875c22 MR |
13889 | struct drm_crtc *crtc = state->base.crtc; |
13890 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13891 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13892 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13893 | bool can_position = false; | |
465c120c | 13894 | |
693bdc28 VS |
13895 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
13896 | /* use scaler when colorkey is not required */ | |
13897 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13898 | min_scale = 1; | |
13899 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13900 | } | |
d8106366 | 13901 | can_position = true; |
6156a456 | 13902 | } |
d8106366 | 13903 | |
061e4b8d ML |
13904 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13905 | &state->dst, &state->clip, | |
da20eabd ML |
13906 | min_scale, max_scale, |
13907 | can_position, true, | |
13908 | &state->visible); | |
14af293f GP |
13909 | } |
13910 | ||
613d2b27 ML |
13911 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13912 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13913 | { |
32b7eeec | 13914 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13915 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13916 | struct intel_crtc_state *old_intel_state = |
13917 | to_intel_crtc_state(old_crtc_state); | |
13918 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13919 | |
c34c9ee4 | 13920 | /* Perform vblank evasion around commit operation */ |
62852622 | 13921 | intel_pipe_update_start(intel_crtc); |
0583236e | 13922 | |
bfd16b2a ML |
13923 | if (modeset) |
13924 | return; | |
13925 | ||
13926 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
13927 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13928 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 13929 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
13930 | } |
13931 | ||
613d2b27 ML |
13932 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13933 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 13934 | { |
32b7eeec | 13935 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 13936 | |
62852622 | 13937 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
13938 | } |
13939 | ||
cf4c7c12 | 13940 | /** |
4a3b8769 MR |
13941 | * intel_plane_destroy - destroy a plane |
13942 | * @plane: plane to destroy | |
cf4c7c12 | 13943 | * |
4a3b8769 MR |
13944 | * Common destruction function for all types of planes (primary, cursor, |
13945 | * sprite). | |
cf4c7c12 | 13946 | */ |
4a3b8769 | 13947 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13948 | { |
13949 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13950 | drm_plane_cleanup(plane); | |
13951 | kfree(intel_plane); | |
13952 | } | |
13953 | ||
65a3fea0 | 13954 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13955 | .update_plane = drm_atomic_helper_update_plane, |
13956 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13957 | .destroy = intel_plane_destroy, |
c196e1d6 | 13958 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13959 | .atomic_get_property = intel_plane_atomic_get_property, |
13960 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13961 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13962 | .atomic_destroy_state = intel_plane_destroy_state, | |
13963 | ||
465c120c MR |
13964 | }; |
13965 | ||
13966 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13967 | int pipe) | |
13968 | { | |
13969 | struct intel_plane *primary; | |
8e7d688b | 13970 | struct intel_plane_state *state; |
465c120c | 13971 | const uint32_t *intel_primary_formats; |
45e3743a | 13972 | unsigned int num_formats; |
465c120c MR |
13973 | |
13974 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13975 | if (primary == NULL) | |
13976 | return NULL; | |
13977 | ||
8e7d688b MR |
13978 | state = intel_create_plane_state(&primary->base); |
13979 | if (!state) { | |
ea2c67bb MR |
13980 | kfree(primary); |
13981 | return NULL; | |
13982 | } | |
8e7d688b | 13983 | primary->base.state = &state->base; |
ea2c67bb | 13984 | |
465c120c MR |
13985 | primary->can_scale = false; |
13986 | primary->max_downscale = 1; | |
6156a456 CK |
13987 | if (INTEL_INFO(dev)->gen >= 9) { |
13988 | primary->can_scale = true; | |
af99ceda | 13989 | state->scaler_id = -1; |
6156a456 | 13990 | } |
465c120c MR |
13991 | primary->pipe = pipe; |
13992 | primary->plane = pipe; | |
a9ff8714 | 13993 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 13994 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
13995 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13996 | primary->plane = !pipe; | |
13997 | ||
6c0fd451 DL |
13998 | if (INTEL_INFO(dev)->gen >= 9) { |
13999 | intel_primary_formats = skl_primary_formats; | |
14000 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14001 | |
14002 | primary->update_plane = skylake_update_primary_plane; | |
14003 | primary->disable_plane = skylake_disable_primary_plane; | |
14004 | } else if (HAS_PCH_SPLIT(dev)) { | |
14005 | intel_primary_formats = i965_primary_formats; | |
14006 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14007 | ||
14008 | primary->update_plane = ironlake_update_primary_plane; | |
14009 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14010 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14011 | intel_primary_formats = i965_primary_formats; |
14012 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14013 | |
14014 | primary->update_plane = i9xx_update_primary_plane; | |
14015 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14016 | } else { |
14017 | intel_primary_formats = i8xx_primary_formats; | |
14018 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14019 | |
14020 | primary->update_plane = i9xx_update_primary_plane; | |
14021 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14022 | } |
14023 | ||
14024 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 14025 | &intel_plane_funcs, |
465c120c | 14026 | intel_primary_formats, num_formats, |
b0b3b795 | 14027 | DRM_PLANE_TYPE_PRIMARY, NULL); |
48404c1e | 14028 | |
3b7a5119 SJ |
14029 | if (INTEL_INFO(dev)->gen >= 4) |
14030 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14031 | |
ea2c67bb MR |
14032 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14033 | ||
465c120c MR |
14034 | return &primary->base; |
14035 | } | |
14036 | ||
3b7a5119 SJ |
14037 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14038 | { | |
14039 | if (!dev->mode_config.rotation_property) { | |
14040 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14041 | BIT(DRM_ROTATE_180); | |
14042 | ||
14043 | if (INTEL_INFO(dev)->gen >= 9) | |
14044 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14045 | ||
14046 | dev->mode_config.rotation_property = | |
14047 | drm_mode_create_rotation_property(dev, flags); | |
14048 | } | |
14049 | if (dev->mode_config.rotation_property) | |
14050 | drm_object_attach_property(&plane->base.base, | |
14051 | dev->mode_config.rotation_property, | |
14052 | plane->base.state->rotation); | |
14053 | } | |
14054 | ||
3d7d6510 | 14055 | static int |
852e787c | 14056 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14057 | struct intel_crtc_state *crtc_state, |
852e787c | 14058 | struct intel_plane_state *state) |
3d7d6510 | 14059 | { |
061e4b8d | 14060 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14061 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14062 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14063 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14064 | unsigned stride; |
14065 | int ret; | |
3d7d6510 | 14066 | |
061e4b8d ML |
14067 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14068 | &state->dst, &state->clip, | |
3d7d6510 MR |
14069 | DRM_PLANE_HELPER_NO_SCALING, |
14070 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14071 | true, true, &state->visible); |
757f9a3e GP |
14072 | if (ret) |
14073 | return ret; | |
14074 | ||
757f9a3e GP |
14075 | /* if we want to turn off the cursor ignore width and height */ |
14076 | if (!obj) | |
da20eabd | 14077 | return 0; |
757f9a3e | 14078 | |
757f9a3e | 14079 | /* Check for which cursor types we support */ |
061e4b8d | 14080 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14081 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14082 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14083 | return -EINVAL; |
14084 | } | |
14085 | ||
ea2c67bb MR |
14086 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14087 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14088 | DRM_DEBUG_KMS("buffer is too small\n"); |
14089 | return -ENOMEM; | |
14090 | } | |
14091 | ||
3a656b54 | 14092 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14093 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14094 | return -EINVAL; |
32b7eeec MR |
14095 | } |
14096 | ||
b29ec92c VS |
14097 | /* |
14098 | * There's something wrong with the cursor on CHV pipe C. | |
14099 | * If it straddles the left edge of the screen then | |
14100 | * moving it away from the edge or disabling it often | |
14101 | * results in a pipe underrun, and often that can lead to | |
14102 | * dead pipe (constant underrun reported, and it scans | |
14103 | * out just a solid color). To recover from that, the | |
14104 | * display power well must be turned off and on again. | |
14105 | * Refuse the put the cursor into that compromised position. | |
14106 | */ | |
14107 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14108 | state->visible && state->base.crtc_x < 0) { | |
14109 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14110 | return -EINVAL; | |
14111 | } | |
14112 | ||
da20eabd | 14113 | return 0; |
852e787c | 14114 | } |
3d7d6510 | 14115 | |
a8ad0d8e ML |
14116 | static void |
14117 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14118 | struct drm_crtc *crtc) |
a8ad0d8e | 14119 | { |
f2858021 ML |
14120 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14121 | ||
14122 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14123 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14124 | } |
14125 | ||
f4a2cf29 | 14126 | static void |
55a08b3f ML |
14127 | intel_update_cursor_plane(struct drm_plane *plane, |
14128 | const struct intel_crtc_state *crtc_state, | |
14129 | const struct intel_plane_state *state) | |
852e787c | 14130 | { |
55a08b3f ML |
14131 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14132 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14133 | struct drm_device *dev = plane->dev; |
2b875c22 | 14134 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14135 | uint32_t addr; |
852e787c | 14136 | |
f4a2cf29 | 14137 | if (!obj) |
a912f12f | 14138 | addr = 0; |
f4a2cf29 | 14139 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14140 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14141 | else |
a912f12f | 14142 | addr = obj->phys_handle->busaddr; |
852e787c | 14143 | |
a912f12f | 14144 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14145 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14146 | } |
14147 | ||
3d7d6510 MR |
14148 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14149 | int pipe) | |
14150 | { | |
14151 | struct intel_plane *cursor; | |
8e7d688b | 14152 | struct intel_plane_state *state; |
3d7d6510 MR |
14153 | |
14154 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14155 | if (cursor == NULL) | |
14156 | return NULL; | |
14157 | ||
8e7d688b MR |
14158 | state = intel_create_plane_state(&cursor->base); |
14159 | if (!state) { | |
ea2c67bb MR |
14160 | kfree(cursor); |
14161 | return NULL; | |
14162 | } | |
8e7d688b | 14163 | cursor->base.state = &state->base; |
ea2c67bb | 14164 | |
3d7d6510 MR |
14165 | cursor->can_scale = false; |
14166 | cursor->max_downscale = 1; | |
14167 | cursor->pipe = pipe; | |
14168 | cursor->plane = pipe; | |
a9ff8714 | 14169 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14170 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14171 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14172 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14173 | |
14174 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14175 | &intel_plane_funcs, |
3d7d6510 MR |
14176 | intel_cursor_formats, |
14177 | ARRAY_SIZE(intel_cursor_formats), | |
b0b3b795 | 14178 | DRM_PLANE_TYPE_CURSOR, NULL); |
4398ad45 VS |
14179 | |
14180 | if (INTEL_INFO(dev)->gen >= 4) { | |
14181 | if (!dev->mode_config.rotation_property) | |
14182 | dev->mode_config.rotation_property = | |
14183 | drm_mode_create_rotation_property(dev, | |
14184 | BIT(DRM_ROTATE_0) | | |
14185 | BIT(DRM_ROTATE_180)); | |
14186 | if (dev->mode_config.rotation_property) | |
14187 | drm_object_attach_property(&cursor->base.base, | |
14188 | dev->mode_config.rotation_property, | |
8e7d688b | 14189 | state->base.rotation); |
4398ad45 VS |
14190 | } |
14191 | ||
af99ceda CK |
14192 | if (INTEL_INFO(dev)->gen >=9) |
14193 | state->scaler_id = -1; | |
14194 | ||
ea2c67bb MR |
14195 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14196 | ||
3d7d6510 MR |
14197 | return &cursor->base; |
14198 | } | |
14199 | ||
549e2bfb CK |
14200 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14201 | struct intel_crtc_state *crtc_state) | |
14202 | { | |
14203 | int i; | |
14204 | struct intel_scaler *intel_scaler; | |
14205 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14206 | ||
14207 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14208 | intel_scaler = &scaler_state->scalers[i]; | |
14209 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14210 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14211 | } | |
14212 | ||
14213 | scaler_state->scaler_id = -1; | |
14214 | } | |
14215 | ||
b358d0a6 | 14216 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14217 | { |
fbee40df | 14218 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14219 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14220 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14221 | struct drm_plane *primary = NULL; |
14222 | struct drm_plane *cursor = NULL; | |
465c120c | 14223 | int i, ret; |
79e53945 | 14224 | |
955382f3 | 14225 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14226 | if (intel_crtc == NULL) |
14227 | return; | |
14228 | ||
f5de6e07 ACO |
14229 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14230 | if (!crtc_state) | |
14231 | goto fail; | |
550acefd ACO |
14232 | intel_crtc->config = crtc_state; |
14233 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14234 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14235 | |
549e2bfb CK |
14236 | /* initialize shared scalers */ |
14237 | if (INTEL_INFO(dev)->gen >= 9) { | |
14238 | if (pipe == PIPE_C) | |
14239 | intel_crtc->num_scalers = 1; | |
14240 | else | |
14241 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14242 | ||
14243 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14244 | } | |
14245 | ||
465c120c | 14246 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14247 | if (!primary) |
14248 | goto fail; | |
14249 | ||
14250 | cursor = intel_cursor_plane_create(dev, pipe); | |
14251 | if (!cursor) | |
14252 | goto fail; | |
14253 | ||
465c120c | 14254 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
f9882876 | 14255 | cursor, &intel_crtc_funcs, NULL); |
3d7d6510 MR |
14256 | if (ret) |
14257 | goto fail; | |
79e53945 JB |
14258 | |
14259 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
14260 | for (i = 0; i < 256; i++) { |
14261 | intel_crtc->lut_r[i] = i; | |
14262 | intel_crtc->lut_g[i] = i; | |
14263 | intel_crtc->lut_b[i] = i; | |
14264 | } | |
14265 | ||
1f1c2e24 VS |
14266 | /* |
14267 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14268 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14269 | */ |
80824003 JB |
14270 | intel_crtc->pipe = pipe; |
14271 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14272 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14273 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14274 | intel_crtc->plane = !pipe; |
80824003 JB |
14275 | } |
14276 | ||
4b0e333e CW |
14277 | intel_crtc->cursor_base = ~0; |
14278 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14279 | intel_crtc->cursor_size = ~0; |
8d7849db | 14280 | |
852eb00d VS |
14281 | intel_crtc->wm.cxsr_allowed = true; |
14282 | ||
22fd0fab JB |
14283 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14284 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14285 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14286 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14287 | ||
79e53945 | 14288 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
14289 | |
14290 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
14291 | return; |
14292 | ||
14293 | fail: | |
14294 | if (primary) | |
14295 | drm_plane_cleanup(primary); | |
14296 | if (cursor) | |
14297 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14298 | kfree(crtc_state); |
3d7d6510 | 14299 | kfree(intel_crtc); |
79e53945 JB |
14300 | } |
14301 | ||
752aa88a JB |
14302 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14303 | { | |
14304 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14305 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14306 | |
51fd371b | 14307 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14308 | |
d3babd3f | 14309 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14310 | return INVALID_PIPE; |
14311 | ||
14312 | return to_intel_crtc(encoder->crtc)->pipe; | |
14313 | } | |
14314 | ||
08d7b3d1 | 14315 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14316 | struct drm_file *file) |
08d7b3d1 | 14317 | { |
08d7b3d1 | 14318 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14319 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14320 | struct intel_crtc *crtc; |
08d7b3d1 | 14321 | |
7707e653 | 14322 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14323 | |
7707e653 | 14324 | if (!drmmode_crtc) { |
08d7b3d1 | 14325 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14326 | return -ENOENT; |
08d7b3d1 CW |
14327 | } |
14328 | ||
7707e653 | 14329 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14330 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14331 | |
c05422d5 | 14332 | return 0; |
08d7b3d1 CW |
14333 | } |
14334 | ||
66a9278e | 14335 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14336 | { |
66a9278e DV |
14337 | struct drm_device *dev = encoder->base.dev; |
14338 | struct intel_encoder *source_encoder; | |
79e53945 | 14339 | int index_mask = 0; |
79e53945 JB |
14340 | int entry = 0; |
14341 | ||
b2784e15 | 14342 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14343 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14344 | index_mask |= (1 << entry); |
14345 | ||
79e53945 JB |
14346 | entry++; |
14347 | } | |
4ef69c7a | 14348 | |
79e53945 JB |
14349 | return index_mask; |
14350 | } | |
14351 | ||
4d302442 CW |
14352 | static bool has_edp_a(struct drm_device *dev) |
14353 | { | |
14354 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14355 | ||
14356 | if (!IS_MOBILE(dev)) | |
14357 | return false; | |
14358 | ||
14359 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14360 | return false; | |
14361 | ||
e3589908 | 14362 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14363 | return false; |
14364 | ||
14365 | return true; | |
14366 | } | |
14367 | ||
84b4e042 JB |
14368 | static bool intel_crt_present(struct drm_device *dev) |
14369 | { | |
14370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14371 | ||
884497ed DL |
14372 | if (INTEL_INFO(dev)->gen >= 9) |
14373 | return false; | |
14374 | ||
cf404ce4 | 14375 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14376 | return false; |
14377 | ||
14378 | if (IS_CHERRYVIEW(dev)) | |
14379 | return false; | |
14380 | ||
65e472e4 VS |
14381 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14382 | return false; | |
14383 | ||
70ac54d0 VS |
14384 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14385 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14386 | return false; | |
14387 | ||
e4abb733 | 14388 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14389 | return false; |
14390 | ||
14391 | return true; | |
14392 | } | |
14393 | ||
79e53945 JB |
14394 | static void intel_setup_outputs(struct drm_device *dev) |
14395 | { | |
725e30ad | 14396 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14397 | struct intel_encoder *encoder; |
cb0953d7 | 14398 | bool dpd_is_edp = false; |
79e53945 | 14399 | |
c9093354 | 14400 | intel_lvds_init(dev); |
79e53945 | 14401 | |
84b4e042 | 14402 | if (intel_crt_present(dev)) |
79935fca | 14403 | intel_crt_init(dev); |
cb0953d7 | 14404 | |
c776eb2e VK |
14405 | if (IS_BROXTON(dev)) { |
14406 | /* | |
14407 | * FIXME: Broxton doesn't support port detection via the | |
14408 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14409 | * detect the ports. | |
14410 | */ | |
14411 | intel_ddi_init(dev, PORT_A); | |
14412 | intel_ddi_init(dev, PORT_B); | |
14413 | intel_ddi_init(dev, PORT_C); | |
14414 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14415 | int found; |
14416 | ||
de31facd JB |
14417 | /* |
14418 | * Haswell uses DDI functions to detect digital outputs. | |
14419 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14420 | * it's there. | |
14421 | */ | |
77179400 | 14422 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14423 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14424 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14425 | intel_ddi_init(dev, PORT_A); |
14426 | ||
14427 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14428 | * register */ | |
14429 | found = I915_READ(SFUSE_STRAP); | |
14430 | ||
14431 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14432 | intel_ddi_init(dev, PORT_B); | |
14433 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14434 | intel_ddi_init(dev, PORT_C); | |
14435 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14436 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14437 | /* |
14438 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14439 | */ | |
ef11bdb3 | 14440 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14441 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14442 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14443 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14444 | intel_ddi_init(dev, PORT_E); | |
14445 | ||
0e72a5b5 | 14446 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14447 | int found; |
5d8a7752 | 14448 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14449 | |
14450 | if (has_edp_a(dev)) | |
14451 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14452 | |
dc0fa718 | 14453 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14454 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14455 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14456 | if (!found) |
e2debe91 | 14457 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14458 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14459 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14460 | } |
14461 | ||
dc0fa718 | 14462 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14463 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14464 | |
dc0fa718 | 14465 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14466 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14467 | |
5eb08b69 | 14468 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14469 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14470 | |
270b3042 | 14471 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14472 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14473 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14474 | /* |
14475 | * The DP_DETECTED bit is the latched state of the DDC | |
14476 | * SDA pin at boot. However since eDP doesn't require DDC | |
14477 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14478 | * eDP ports may have been muxed to an alternate function. | |
14479 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14480 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14481 | * detect eDP ports. | |
14482 | */ | |
e66eb81d | 14483 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14484 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14485 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14486 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14487 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14488 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14489 | |
e66eb81d | 14490 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14491 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14492 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14493 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14494 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14495 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14496 | |
9418c1f1 | 14497 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14498 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14499 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14500 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14501 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14502 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14503 | } |
14504 | ||
3cfca973 | 14505 | intel_dsi_init(dev); |
09da55dc | 14506 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14507 | bool found = false; |
7d57382e | 14508 | |
e2debe91 | 14509 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14510 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14511 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14512 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14513 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14514 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14515 | } |
27185ae1 | 14516 | |
3fec3d2f | 14517 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14518 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14519 | } |
13520b05 KH |
14520 | |
14521 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14522 | |
e2debe91 | 14523 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14524 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14525 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14526 | } |
27185ae1 | 14527 | |
e2debe91 | 14528 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14529 | |
3fec3d2f | 14530 | if (IS_G4X(dev)) { |
b01f2c3a | 14531 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14532 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14533 | } |
3fec3d2f | 14534 | if (IS_G4X(dev)) |
ab9d7c30 | 14535 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14536 | } |
27185ae1 | 14537 | |
3fec3d2f | 14538 | if (IS_G4X(dev) && |
e7281eab | 14539 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14540 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14541 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14542 | intel_dvo_init(dev); |
14543 | ||
103a196f | 14544 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14545 | intel_tv_init(dev); |
14546 | ||
0bc12bcb | 14547 | intel_psr_init(dev); |
7c8f8a70 | 14548 | |
b2784e15 | 14549 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14550 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14551 | encoder->base.possible_clones = | |
66a9278e | 14552 | intel_encoder_clones(encoder); |
79e53945 | 14553 | } |
47356eb6 | 14554 | |
dde86e2d | 14555 | intel_init_pch_refclk(dev); |
270b3042 DV |
14556 | |
14557 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14558 | } |
14559 | ||
14560 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14561 | { | |
60a5ca01 | 14562 | struct drm_device *dev = fb->dev; |
79e53945 | 14563 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14564 | |
ef2d633e | 14565 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14566 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14567 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14568 | drm_gem_object_unreference(&intel_fb->obj->base); |
14569 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14570 | kfree(intel_fb); |
14571 | } | |
14572 | ||
14573 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14574 | struct drm_file *file, |
79e53945 JB |
14575 | unsigned int *handle) |
14576 | { | |
14577 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14578 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14579 | |
cc917ab4 CW |
14580 | if (obj->userptr.mm) { |
14581 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14582 | return -EINVAL; | |
14583 | } | |
14584 | ||
05394f39 | 14585 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14586 | } |
14587 | ||
86c98588 RV |
14588 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14589 | struct drm_file *file, | |
14590 | unsigned flags, unsigned color, | |
14591 | struct drm_clip_rect *clips, | |
14592 | unsigned num_clips) | |
14593 | { | |
14594 | struct drm_device *dev = fb->dev; | |
14595 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14596 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14597 | ||
14598 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14599 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14600 | mutex_unlock(&dev->struct_mutex); |
14601 | ||
14602 | return 0; | |
14603 | } | |
14604 | ||
79e53945 JB |
14605 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14606 | .destroy = intel_user_framebuffer_destroy, | |
14607 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14608 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14609 | }; |
14610 | ||
b321803d DL |
14611 | static |
14612 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14613 | uint32_t pixel_format) | |
14614 | { | |
14615 | u32 gen = INTEL_INFO(dev)->gen; | |
14616 | ||
14617 | if (gen >= 9) { | |
ac484963 VS |
14618 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14619 | ||
b321803d DL |
14620 | /* "The stride in bytes must not exceed the of the size of 8K |
14621 | * pixels and 32K bytes." | |
14622 | */ | |
ac484963 | 14623 | return min(8192 * cpp, 32768); |
666a4537 | 14624 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14625 | return 32*1024; |
14626 | } else if (gen >= 4) { | |
14627 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14628 | return 16*1024; | |
14629 | else | |
14630 | return 32*1024; | |
14631 | } else if (gen >= 3) { | |
14632 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14633 | return 8*1024; | |
14634 | else | |
14635 | return 16*1024; | |
14636 | } else { | |
14637 | /* XXX DSPC is limited to 4k tiled */ | |
14638 | return 8*1024; | |
14639 | } | |
14640 | } | |
14641 | ||
b5ea642a DV |
14642 | static int intel_framebuffer_init(struct drm_device *dev, |
14643 | struct intel_framebuffer *intel_fb, | |
14644 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14645 | struct drm_i915_gem_object *obj) | |
79e53945 | 14646 | { |
7b49f948 | 14647 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14648 | unsigned int aligned_height; |
79e53945 | 14649 | int ret; |
b321803d | 14650 | u32 pitch_limit, stride_alignment; |
79e53945 | 14651 | |
dd4916c5 DV |
14652 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14653 | ||
2a80eada DV |
14654 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14655 | /* Enforce that fb modifier and tiling mode match, but only for | |
14656 | * X-tiled. This is needed for FBC. */ | |
14657 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14658 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14659 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14660 | return -EINVAL; | |
14661 | } | |
14662 | } else { | |
14663 | if (obj->tiling_mode == I915_TILING_X) | |
14664 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14665 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14666 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14667 | return -EINVAL; | |
14668 | } | |
14669 | } | |
14670 | ||
9a8f0a12 TU |
14671 | /* Passed in modifier sanity checking. */ |
14672 | switch (mode_cmd->modifier[0]) { | |
14673 | case I915_FORMAT_MOD_Y_TILED: | |
14674 | case I915_FORMAT_MOD_Yf_TILED: | |
14675 | if (INTEL_INFO(dev)->gen < 9) { | |
14676 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14677 | mode_cmd->modifier[0]); | |
14678 | return -EINVAL; | |
14679 | } | |
14680 | case DRM_FORMAT_MOD_NONE: | |
14681 | case I915_FORMAT_MOD_X_TILED: | |
14682 | break; | |
14683 | default: | |
c0f40428 JB |
14684 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14685 | mode_cmd->modifier[0]); | |
57cd6508 | 14686 | return -EINVAL; |
c16ed4be | 14687 | } |
57cd6508 | 14688 | |
7b49f948 VS |
14689 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14690 | mode_cmd->modifier[0], | |
b321803d DL |
14691 | mode_cmd->pixel_format); |
14692 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14693 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14694 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14695 | return -EINVAL; |
c16ed4be | 14696 | } |
57cd6508 | 14697 | |
b321803d DL |
14698 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14699 | mode_cmd->pixel_format); | |
a35cdaa0 | 14700 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14701 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14702 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14703 | "tiled" : "linear", |
a35cdaa0 | 14704 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14705 | return -EINVAL; |
c16ed4be | 14706 | } |
5d7bd705 | 14707 | |
2a80eada | 14708 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14709 | mode_cmd->pitches[0] != obj->stride) { |
14710 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14711 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14712 | return -EINVAL; |
c16ed4be | 14713 | } |
5d7bd705 | 14714 | |
57779d06 | 14715 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14716 | switch (mode_cmd->pixel_format) { |
57779d06 | 14717 | case DRM_FORMAT_C8: |
04b3924d VS |
14718 | case DRM_FORMAT_RGB565: |
14719 | case DRM_FORMAT_XRGB8888: | |
14720 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14721 | break; |
14722 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14723 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14724 | DRM_DEBUG("unsupported pixel format: %s\n", |
14725 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14726 | return -EINVAL; |
c16ed4be | 14727 | } |
57779d06 | 14728 | break; |
57779d06 | 14729 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14730 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14731 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14732 | DRM_DEBUG("unsupported pixel format: %s\n", |
14733 | drm_get_format_name(mode_cmd->pixel_format)); | |
14734 | return -EINVAL; | |
14735 | } | |
14736 | break; | |
14737 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14738 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14739 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14740 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14741 | DRM_DEBUG("unsupported pixel format: %s\n", |
14742 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14743 | return -EINVAL; |
c16ed4be | 14744 | } |
b5626747 | 14745 | break; |
7531208b | 14746 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14747 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14748 | DRM_DEBUG("unsupported pixel format: %s\n", |
14749 | drm_get_format_name(mode_cmd->pixel_format)); | |
14750 | return -EINVAL; | |
14751 | } | |
14752 | break; | |
04b3924d VS |
14753 | case DRM_FORMAT_YUYV: |
14754 | case DRM_FORMAT_UYVY: | |
14755 | case DRM_FORMAT_YVYU: | |
14756 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14757 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14758 | DRM_DEBUG("unsupported pixel format: %s\n", |
14759 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14760 | return -EINVAL; |
c16ed4be | 14761 | } |
57cd6508 CW |
14762 | break; |
14763 | default: | |
4ee62c76 VS |
14764 | DRM_DEBUG("unsupported pixel format: %s\n", |
14765 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14766 | return -EINVAL; |
14767 | } | |
14768 | ||
90f9a336 VS |
14769 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14770 | if (mode_cmd->offsets[0] != 0) | |
14771 | return -EINVAL; | |
14772 | ||
ec2c981e | 14773 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14774 | mode_cmd->pixel_format, |
14775 | mode_cmd->modifier[0]); | |
53155c0a DV |
14776 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14777 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14778 | return -EINVAL; | |
14779 | ||
c7d73f6a DV |
14780 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14781 | intel_fb->obj = obj; | |
14782 | ||
79e53945 JB |
14783 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14784 | if (ret) { | |
14785 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14786 | return ret; | |
14787 | } | |
14788 | ||
0b05e1e0 VS |
14789 | intel_fb->obj->framebuffer_references++; |
14790 | ||
79e53945 JB |
14791 | return 0; |
14792 | } | |
14793 | ||
79e53945 JB |
14794 | static struct drm_framebuffer * |
14795 | intel_user_framebuffer_create(struct drm_device *dev, | |
14796 | struct drm_file *filp, | |
1eb83451 | 14797 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14798 | { |
dcb1394e | 14799 | struct drm_framebuffer *fb; |
05394f39 | 14800 | struct drm_i915_gem_object *obj; |
76dc3769 | 14801 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14802 | |
308e5bcb | 14803 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14804 | mode_cmd.handles[0])); |
c8725226 | 14805 | if (&obj->base == NULL) |
cce13ff7 | 14806 | return ERR_PTR(-ENOENT); |
79e53945 | 14807 | |
92907cbb | 14808 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14809 | if (IS_ERR(fb)) |
14810 | drm_gem_object_unreference_unlocked(&obj->base); | |
14811 | ||
14812 | return fb; | |
79e53945 JB |
14813 | } |
14814 | ||
0695726e | 14815 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14816 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14817 | { |
14818 | } | |
14819 | #endif | |
14820 | ||
79e53945 | 14821 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14822 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14823 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14824 | .atomic_check = intel_atomic_check, |
14825 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14826 | .atomic_state_alloc = intel_atomic_state_alloc, |
14827 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14828 | }; |
14829 | ||
e70236a8 JB |
14830 | /* Set up chip specific display functions */ |
14831 | static void intel_init_display(struct drm_device *dev) | |
14832 | { | |
14833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14834 | ||
ee9300bb DV |
14835 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14836 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14837 | else if (IS_CHERRYVIEW(dev)) |
14838 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14839 | else if (IS_VALLEYVIEW(dev)) |
14840 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14841 | else if (IS_PINEVIEW(dev)) | |
14842 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14843 | else | |
14844 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14845 | ||
bc8d7dff DL |
14846 | if (INTEL_INFO(dev)->gen >= 9) { |
14847 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14848 | dev_priv->display.get_initial_plane_config = |
14849 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14850 | dev_priv->display.crtc_compute_clock = |
14851 | haswell_crtc_compute_clock; | |
14852 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14853 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff | 14854 | } else if (HAS_DDI(dev)) { |
0e8ffe1b | 14855 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14856 | dev_priv->display.get_initial_plane_config = |
14857 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14858 | dev_priv->display.crtc_compute_clock = |
14859 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14860 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14861 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
09b4ddf9 | 14862 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14863 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14864 | dev_priv->display.get_initial_plane_config = |
14865 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14866 | dev_priv->display.crtc_compute_clock = |
14867 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14868 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14869 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
666a4537 | 14870 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
89b667f8 | 14871 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14872 | dev_priv->display.get_initial_plane_config = |
14873 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14874 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14875 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14876 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14877 | } else { |
0e8ffe1b | 14878 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14879 | dev_priv->display.get_initial_plane_config = |
14880 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14881 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14882 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14883 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14884 | } |
e70236a8 | 14885 | |
e70236a8 | 14886 | /* Returns the core display clock speed */ |
ef11bdb3 | 14887 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1652d19e VS |
14888 | dev_priv->display.get_display_clock_speed = |
14889 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
14890 | else if (IS_BROXTON(dev)) |
14891 | dev_priv->display.get_display_clock_speed = | |
14892 | broxton_get_display_clock_speed; | |
1652d19e VS |
14893 | else if (IS_BROADWELL(dev)) |
14894 | dev_priv->display.get_display_clock_speed = | |
14895 | broadwell_get_display_clock_speed; | |
14896 | else if (IS_HASWELL(dev)) | |
14897 | dev_priv->display.get_display_clock_speed = | |
14898 | haswell_get_display_clock_speed; | |
666a4537 | 14899 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
25eb05fc JB |
14900 | dev_priv->display.get_display_clock_speed = |
14901 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14902 | else if (IS_GEN5(dev)) |
14903 | dev_priv->display.get_display_clock_speed = | |
14904 | ilk_get_display_clock_speed; | |
a7c66cd8 | 14905 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 14906 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
14907 | dev_priv->display.get_display_clock_speed = |
14908 | i945_get_display_clock_speed; | |
34edce2f VS |
14909 | else if (IS_GM45(dev)) |
14910 | dev_priv->display.get_display_clock_speed = | |
14911 | gm45_get_display_clock_speed; | |
14912 | else if (IS_CRESTLINE(dev)) | |
14913 | dev_priv->display.get_display_clock_speed = | |
14914 | i965gm_get_display_clock_speed; | |
14915 | else if (IS_PINEVIEW(dev)) | |
14916 | dev_priv->display.get_display_clock_speed = | |
14917 | pnv_get_display_clock_speed; | |
14918 | else if (IS_G33(dev) || IS_G4X(dev)) | |
14919 | dev_priv->display.get_display_clock_speed = | |
14920 | g33_get_display_clock_speed; | |
e70236a8 JB |
14921 | else if (IS_I915G(dev)) |
14922 | dev_priv->display.get_display_clock_speed = | |
14923 | i915_get_display_clock_speed; | |
257a7ffc | 14924 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14925 | dev_priv->display.get_display_clock_speed = |
14926 | i9xx_misc_get_display_clock_speed; | |
14927 | else if (IS_I915GM(dev)) | |
14928 | dev_priv->display.get_display_clock_speed = | |
14929 | i915gm_get_display_clock_speed; | |
14930 | else if (IS_I865G(dev)) | |
14931 | dev_priv->display.get_display_clock_speed = | |
14932 | i865_get_display_clock_speed; | |
f0f8a9ce | 14933 | else if (IS_I85X(dev)) |
e70236a8 | 14934 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14935 | i85x_get_display_clock_speed; |
623e01e5 VS |
14936 | else { /* 830 */ |
14937 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
14938 | dev_priv->display.get_display_clock_speed = |
14939 | i830_get_display_clock_speed; | |
623e01e5 | 14940 | } |
e70236a8 | 14941 | |
7c10a2b5 | 14942 | if (IS_GEN5(dev)) { |
3bb11b53 | 14943 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14944 | } else if (IS_GEN6(dev)) { |
14945 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14946 | } else if (IS_IVYBRIDGE(dev)) { |
14947 | /* FIXME: detect B0+ stepping and use auto training */ | |
14948 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14949 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14950 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
14951 | if (IS_BROADWELL(dev)) { |
14952 | dev_priv->display.modeset_commit_cdclk = | |
14953 | broadwell_modeset_commit_cdclk; | |
14954 | dev_priv->display.modeset_calc_cdclk = | |
14955 | broadwell_modeset_calc_cdclk; | |
14956 | } | |
666a4537 | 14957 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
27c329ed ML |
14958 | dev_priv->display.modeset_commit_cdclk = |
14959 | valleyview_modeset_commit_cdclk; | |
14960 | dev_priv->display.modeset_calc_cdclk = | |
14961 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 14962 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
14963 | dev_priv->display.modeset_commit_cdclk = |
14964 | broxton_modeset_commit_cdclk; | |
14965 | dev_priv->display.modeset_calc_cdclk = | |
14966 | broxton_modeset_calc_cdclk; | |
e70236a8 | 14967 | } |
8c9f3aaf | 14968 | |
8c9f3aaf JB |
14969 | switch (INTEL_INFO(dev)->gen) { |
14970 | case 2: | |
14971 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14972 | break; | |
14973 | ||
14974 | case 3: | |
14975 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14976 | break; | |
14977 | ||
14978 | case 4: | |
14979 | case 5: | |
14980 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14981 | break; | |
14982 | ||
14983 | case 6: | |
14984 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14985 | break; | |
7c9017e5 | 14986 | case 7: |
4e0bbc31 | 14987 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14988 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14989 | break; | |
830c81db | 14990 | case 9: |
ba343e02 TU |
14991 | /* Drop through - unsupported since execlist only. */ |
14992 | default: | |
14993 | /* Default just returns -ENODEV to indicate unsupported */ | |
14994 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14995 | } |
7bd688cd | 14996 | |
e39b999a | 14997 | mutex_init(&dev_priv->pps_mutex); |
e70236a8 JB |
14998 | } |
14999 | ||
b690e96c JB |
15000 | /* |
15001 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15002 | * resume, or other times. This quirk makes sure that's the case for | |
15003 | * affected systems. | |
15004 | */ | |
0206e353 | 15005 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
15006 | { |
15007 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15008 | ||
15009 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15010 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15011 | } |
15012 | ||
b6b5d049 VS |
15013 | static void quirk_pipeb_force(struct drm_device *dev) |
15014 | { | |
15015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15016 | ||
15017 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15018 | DRM_INFO("applying pipe b force quirk\n"); | |
15019 | } | |
15020 | ||
435793df KP |
15021 | /* |
15022 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15023 | */ | |
15024 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15025 | { | |
15026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15027 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15028 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15029 | } |
15030 | ||
4dca20ef | 15031 | /* |
5a15ab5b CE |
15032 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15033 | * brightness value | |
4dca20ef CE |
15034 | */ |
15035 | static void quirk_invert_brightness(struct drm_device *dev) | |
15036 | { | |
15037 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15038 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15039 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15040 | } |
15041 | ||
9c72cc6f SD |
15042 | /* Some VBT's incorrectly indicate no backlight is present */ |
15043 | static void quirk_backlight_present(struct drm_device *dev) | |
15044 | { | |
15045 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15046 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15047 | DRM_INFO("applying backlight present quirk\n"); | |
15048 | } | |
15049 | ||
b690e96c JB |
15050 | struct intel_quirk { |
15051 | int device; | |
15052 | int subsystem_vendor; | |
15053 | int subsystem_device; | |
15054 | void (*hook)(struct drm_device *dev); | |
15055 | }; | |
15056 | ||
5f85f176 EE |
15057 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15058 | struct intel_dmi_quirk { | |
15059 | void (*hook)(struct drm_device *dev); | |
15060 | const struct dmi_system_id (*dmi_id_list)[]; | |
15061 | }; | |
15062 | ||
15063 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15064 | { | |
15065 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15066 | return 1; | |
15067 | } | |
15068 | ||
15069 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15070 | { | |
15071 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15072 | { | |
15073 | .callback = intel_dmi_reverse_brightness, | |
15074 | .ident = "NCR Corporation", | |
15075 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15076 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15077 | }, | |
15078 | }, | |
15079 | { } /* terminating entry */ | |
15080 | }, | |
15081 | .hook = quirk_invert_brightness, | |
15082 | }, | |
15083 | }; | |
15084 | ||
c43b5634 | 15085 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15086 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15087 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15088 | ||
b690e96c JB |
15089 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15090 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15091 | ||
5f080c0f VS |
15092 | /* 830 needs to leave pipe A & dpll A up */ |
15093 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15094 | ||
b6b5d049 VS |
15095 | /* 830 needs to leave pipe B & dpll B up */ |
15096 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15097 | ||
435793df KP |
15098 | /* Lenovo U160 cannot use SSC on LVDS */ |
15099 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15100 | |
15101 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15102 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15103 | |
be505f64 AH |
15104 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15105 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15106 | ||
15107 | /* Acer/eMachines G725 */ | |
15108 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15109 | ||
15110 | /* Acer/eMachines e725 */ | |
15111 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15112 | ||
15113 | /* Acer/Packard Bell NCL20 */ | |
15114 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15115 | ||
15116 | /* Acer Aspire 4736Z */ | |
15117 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15118 | |
15119 | /* Acer Aspire 5336 */ | |
15120 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15121 | |
15122 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15123 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15124 | |
dfb3d47b SD |
15125 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15126 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15127 | ||
b2a9601c | 15128 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15129 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15130 | ||
1b9448b0 JN |
15131 | /* Apple Macbook 4,1 */ |
15132 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15133 | ||
d4967d8c SD |
15134 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15135 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15136 | |
15137 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15138 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15139 | |
15140 | /* Dell Chromebook 11 */ | |
15141 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15142 | |
15143 | /* Dell Chromebook 11 (2015 version) */ | |
15144 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15145 | }; |
15146 | ||
15147 | static void intel_init_quirks(struct drm_device *dev) | |
15148 | { | |
15149 | struct pci_dev *d = dev->pdev; | |
15150 | int i; | |
15151 | ||
15152 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15153 | struct intel_quirk *q = &intel_quirks[i]; | |
15154 | ||
15155 | if (d->device == q->device && | |
15156 | (d->subsystem_vendor == q->subsystem_vendor || | |
15157 | q->subsystem_vendor == PCI_ANY_ID) && | |
15158 | (d->subsystem_device == q->subsystem_device || | |
15159 | q->subsystem_device == PCI_ANY_ID)) | |
15160 | q->hook(dev); | |
15161 | } | |
5f85f176 EE |
15162 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15163 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15164 | intel_dmi_quirks[i].hook(dev); | |
15165 | } | |
b690e96c JB |
15166 | } |
15167 | ||
9cce37f4 JB |
15168 | /* Disable the VGA plane that we never use */ |
15169 | static void i915_disable_vga(struct drm_device *dev) | |
15170 | { | |
15171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15172 | u8 sr1; | |
f0f59a00 | 15173 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15174 | |
2b37c616 | 15175 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15176 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15177 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15178 | sr1 = inb(VGA_SR_DATA); |
15179 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15180 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15181 | udelay(300); | |
15182 | ||
01f5a626 | 15183 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15184 | POSTING_READ(vga_reg); |
15185 | } | |
15186 | ||
f817586c DV |
15187 | void intel_modeset_init_hw(struct drm_device *dev) |
15188 | { | |
1a617b77 ML |
15189 | struct drm_i915_private *dev_priv = dev->dev_private; |
15190 | ||
b6283055 | 15191 | intel_update_cdclk(dev); |
1a617b77 ML |
15192 | |
15193 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15194 | ||
f817586c | 15195 | intel_init_clock_gating(dev); |
8090c6b9 | 15196 | intel_enable_gt_powersave(dev); |
f817586c DV |
15197 | } |
15198 | ||
d93c0372 MR |
15199 | /* |
15200 | * Calculate what we think the watermarks should be for the state we've read | |
15201 | * out of the hardware and then immediately program those watermarks so that | |
15202 | * we ensure the hardware settings match our internal state. | |
15203 | * | |
15204 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15205 | * current state (which was constructed during hardware readout) and running it | |
15206 | * through the atomic check code to calculate new watermark values in the | |
15207 | * state object. | |
15208 | */ | |
15209 | static void sanitize_watermarks(struct drm_device *dev) | |
15210 | { | |
15211 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15212 | struct drm_atomic_state *state; | |
15213 | struct drm_crtc *crtc; | |
15214 | struct drm_crtc_state *cstate; | |
15215 | struct drm_modeset_acquire_ctx ctx; | |
15216 | int ret; | |
15217 | int i; | |
15218 | ||
15219 | /* Only supported on platforms that use atomic watermark design */ | |
bf220452 | 15220 | if (!dev_priv->display.program_watermarks) |
d93c0372 MR |
15221 | return; |
15222 | ||
15223 | /* | |
15224 | * We need to hold connection_mutex before calling duplicate_state so | |
15225 | * that the connector loop is protected. | |
15226 | */ | |
15227 | drm_modeset_acquire_init(&ctx, 0); | |
15228 | retry: | |
0cd1262d | 15229 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15230 | if (ret == -EDEADLK) { |
15231 | drm_modeset_backoff(&ctx); | |
15232 | goto retry; | |
15233 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15234 | goto fail; |
d93c0372 MR |
15235 | } |
15236 | ||
15237 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15238 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15239 | goto fail; |
d93c0372 MR |
15240 | |
15241 | ret = intel_atomic_check(dev, state); | |
15242 | if (ret) { | |
15243 | /* | |
15244 | * If we fail here, it means that the hardware appears to be | |
15245 | * programmed in a way that shouldn't be possible, given our | |
15246 | * understanding of watermark requirements. This might mean a | |
15247 | * mistake in the hardware readout code or a mistake in the | |
15248 | * watermark calculations for a given platform. Raise a WARN | |
15249 | * so that this is noticeable. | |
15250 | * | |
15251 | * If this actually happens, we'll have to just leave the | |
15252 | * BIOS-programmed watermarks untouched and hope for the best. | |
15253 | */ | |
15254 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15255 | goto fail; |
d93c0372 MR |
15256 | } |
15257 | ||
15258 | /* Write calculated watermark values back */ | |
15259 | to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config; | |
15260 | for_each_crtc_in_state(state, crtc, cstate, i) { | |
15261 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15262 | ||
bf220452 | 15263 | dev_priv->display.program_watermarks(cs); |
d93c0372 MR |
15264 | } |
15265 | ||
15266 | drm_atomic_state_free(state); | |
0cd1262d | 15267 | fail: |
d93c0372 MR |
15268 | drm_modeset_drop_locks(&ctx); |
15269 | drm_modeset_acquire_fini(&ctx); | |
15270 | } | |
15271 | ||
79e53945 JB |
15272 | void intel_modeset_init(struct drm_device *dev) |
15273 | { | |
652c393a | 15274 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15275 | int sprite, ret; |
8cc87b75 | 15276 | enum pipe pipe; |
46f297fb | 15277 | struct intel_crtc *crtc; |
79e53945 JB |
15278 | |
15279 | drm_mode_config_init(dev); | |
15280 | ||
15281 | dev->mode_config.min_width = 0; | |
15282 | dev->mode_config.min_height = 0; | |
15283 | ||
019d96cb DA |
15284 | dev->mode_config.preferred_depth = 24; |
15285 | dev->mode_config.prefer_shadow = 1; | |
15286 | ||
25bab385 TU |
15287 | dev->mode_config.allow_fb_modifiers = true; |
15288 | ||
e6ecefaa | 15289 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15290 | |
b690e96c JB |
15291 | intel_init_quirks(dev); |
15292 | ||
1fa61106 ED |
15293 | intel_init_pm(dev); |
15294 | ||
e3c74757 BW |
15295 | if (INTEL_INFO(dev)->num_pipes == 0) |
15296 | return; | |
15297 | ||
69f92f67 LW |
15298 | /* |
15299 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15300 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15301 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15302 | * indicates as much. | |
15303 | */ | |
15304 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15305 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15306 | DREF_SSC1_ENABLE); | |
15307 | ||
15308 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15309 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15310 | bios_lvds_use_ssc ? "en" : "dis", | |
15311 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15312 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15313 | } | |
15314 | } | |
15315 | ||
e70236a8 | 15316 | intel_init_display(dev); |
7c10a2b5 | 15317 | intel_init_audio(dev); |
e70236a8 | 15318 | |
a6c45cf0 CW |
15319 | if (IS_GEN2(dev)) { |
15320 | dev->mode_config.max_width = 2048; | |
15321 | dev->mode_config.max_height = 2048; | |
15322 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15323 | dev->mode_config.max_width = 4096; |
15324 | dev->mode_config.max_height = 4096; | |
79e53945 | 15325 | } else { |
a6c45cf0 CW |
15326 | dev->mode_config.max_width = 8192; |
15327 | dev->mode_config.max_height = 8192; | |
79e53945 | 15328 | } |
068be561 | 15329 | |
dc41c154 VS |
15330 | if (IS_845G(dev) || IS_I865G(dev)) { |
15331 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15332 | dev->mode_config.cursor_height = 1023; | |
15333 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15334 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15335 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15336 | } else { | |
15337 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15338 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15339 | } | |
15340 | ||
5d4545ae | 15341 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 15342 | |
28c97730 | 15343 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15344 | INTEL_INFO(dev)->num_pipes, |
15345 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15346 | |
055e393f | 15347 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15348 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15349 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15350 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15351 | if (ret) |
06da8da2 | 15352 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15353 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15354 | } |
79e53945 JB |
15355 | } |
15356 | ||
bfa7df01 VS |
15357 | intel_update_czclk(dev_priv); |
15358 | intel_update_cdclk(dev); | |
15359 | ||
e72f9fbf | 15360 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15361 | |
9cce37f4 JB |
15362 | /* Just disable it once at startup */ |
15363 | i915_disable_vga(dev); | |
79e53945 | 15364 | intel_setup_outputs(dev); |
11be49eb | 15365 | |
6e9f798d | 15366 | drm_modeset_lock_all(dev); |
043e9bda | 15367 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15368 | drm_modeset_unlock_all(dev); |
46f297fb | 15369 | |
d3fcc808 | 15370 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15371 | struct intel_initial_plane_config plane_config = {}; |
15372 | ||
46f297fb JB |
15373 | if (!crtc->active) |
15374 | continue; | |
15375 | ||
46f297fb | 15376 | /* |
46f297fb JB |
15377 | * Note that reserving the BIOS fb up front prevents us |
15378 | * from stuffing other stolen allocations like the ring | |
15379 | * on top. This prevents some ugliness at boot time, and | |
15380 | * can even allow for smooth boot transitions if the BIOS | |
15381 | * fb is large enough for the active pipe configuration. | |
15382 | */ | |
eeebeac5 ML |
15383 | dev_priv->display.get_initial_plane_config(crtc, |
15384 | &plane_config); | |
15385 | ||
15386 | /* | |
15387 | * If the fb is shared between multiple heads, we'll | |
15388 | * just get the first one. | |
15389 | */ | |
15390 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15391 | } |
d93c0372 MR |
15392 | |
15393 | /* | |
15394 | * Make sure hardware watermarks really match the state we read out. | |
15395 | * Note that we need to do this after reconstructing the BIOS fb's | |
15396 | * since the watermark calculation done here will use pstate->fb. | |
15397 | */ | |
15398 | sanitize_watermarks(dev); | |
2c7111db CW |
15399 | } |
15400 | ||
7fad798e DV |
15401 | static void intel_enable_pipe_a(struct drm_device *dev) |
15402 | { | |
15403 | struct intel_connector *connector; | |
15404 | struct drm_connector *crt = NULL; | |
15405 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15406 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15407 | |
15408 | /* We can't just switch on the pipe A, we need to set things up with a | |
15409 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15410 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15411 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15412 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15413 | crt = &connector->base; | |
15414 | break; | |
15415 | } | |
15416 | } | |
15417 | ||
15418 | if (!crt) | |
15419 | return; | |
15420 | ||
208bf9fd | 15421 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15422 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15423 | } |
15424 | ||
fa555837 DV |
15425 | static bool |
15426 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15427 | { | |
7eb552ae BW |
15428 | struct drm_device *dev = crtc->base.dev; |
15429 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15430 | u32 val; |
fa555837 | 15431 | |
7eb552ae | 15432 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15433 | return true; |
15434 | ||
649636ef | 15435 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15436 | |
15437 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15438 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15439 | return false; | |
15440 | ||
15441 | return true; | |
15442 | } | |
15443 | ||
02e93c35 VS |
15444 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15445 | { | |
15446 | struct drm_device *dev = crtc->base.dev; | |
15447 | struct intel_encoder *encoder; | |
15448 | ||
15449 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15450 | return true; | |
15451 | ||
15452 | return false; | |
15453 | } | |
15454 | ||
24929352 DV |
15455 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15456 | { | |
15457 | struct drm_device *dev = crtc->base.dev; | |
15458 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15459 | i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 | 15460 | |
24929352 | 15461 | /* Clear any frame start delays used for debugging left by the BIOS */ |
24929352 DV |
15462 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15463 | ||
d3eaf884 | 15464 | /* restore vblank interrupts to correct state */ |
9625604c | 15465 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15466 | if (crtc->active) { |
f9cd7b88 VS |
15467 | struct intel_plane *plane; |
15468 | ||
9625604c | 15469 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15470 | |
15471 | /* Disable everything but the primary plane */ | |
15472 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15473 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15474 | continue; | |
15475 | ||
15476 | plane->disable_plane(&plane->base, &crtc->base); | |
15477 | } | |
9625604c | 15478 | } |
d3eaf884 | 15479 | |
24929352 | 15480 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15481 | * disable the crtc (and hence change the state) if it is wrong. Note |
15482 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15483 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15484 | bool plane; |
15485 | ||
24929352 DV |
15486 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15487 | crtc->base.base.id); | |
15488 | ||
15489 | /* Pipe has the wrong plane attached and the plane is active. | |
15490 | * Temporarily change the plane mapping and disable everything | |
15491 | * ... */ | |
15492 | plane = crtc->plane; | |
b70709a6 | 15493 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15494 | crtc->plane = !plane; |
b17d48e2 | 15495 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15496 | crtc->plane = plane; |
24929352 | 15497 | } |
24929352 | 15498 | |
7fad798e DV |
15499 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15500 | crtc->pipe == PIPE_A && !crtc->active) { | |
15501 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15502 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15503 | * call below we restore the pipe to the right state, but leave | |
15504 | * the required bits on. */ | |
15505 | intel_enable_pipe_a(dev); | |
15506 | } | |
15507 | ||
24929352 DV |
15508 | /* Adjust the state of the output pipe according to whether we |
15509 | * have active connectors/encoders. */ | |
02e93c35 | 15510 | if (!intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15511 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15512 | |
53d9f4e9 | 15513 | if (crtc->active != crtc->base.state->active) { |
02e93c35 | 15514 | struct intel_encoder *encoder; |
24929352 DV |
15515 | |
15516 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
15517 | * functions or because of calls to intel_crtc_disable_noatomic, |
15518 | * or because the pipe is force-enabled due to the | |
24929352 DV |
15519 | * pipe A quirk. */ |
15520 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15521 | crtc->base.base.id, | |
83d65738 | 15522 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15523 | crtc->active ? "enabled" : "disabled"); |
15524 | ||
4be40c98 | 15525 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 15526 | crtc->base.state->active = crtc->active; |
24929352 | 15527 | crtc->base.enabled = crtc->active; |
2aa974c9 | 15528 | crtc->base.state->connector_mask = 0; |
e87a52b3 | 15529 | crtc->base.state->encoder_mask = 0; |
24929352 DV |
15530 | |
15531 | /* Because we only establish the connector -> encoder -> | |
15532 | * crtc links if something is active, this means the | |
15533 | * crtc is now deactivated. Break the links. connector | |
15534 | * -> encoder links are only establish when things are | |
15535 | * actually up, hence no need to break them. */ | |
15536 | WARN_ON(crtc->active); | |
15537 | ||
2d406bb0 | 15538 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
24929352 | 15539 | encoder->base.crtc = NULL; |
24929352 | 15540 | } |
c5ab3bc0 | 15541 | |
a3ed6aad | 15542 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15543 | /* |
15544 | * We start out with underrun reporting disabled to avoid races. | |
15545 | * For correct bookkeeping mark this on active crtcs. | |
15546 | * | |
c5ab3bc0 DV |
15547 | * Also on gmch platforms we dont have any hardware bits to |
15548 | * disable the underrun reporting. Which means we need to start | |
15549 | * out with underrun reporting disabled also on inactive pipes, | |
15550 | * since otherwise we'll complain about the garbage we read when | |
15551 | * e.g. coming up after runtime pm. | |
15552 | * | |
4cc31489 DV |
15553 | * No protection against concurrent access is required - at |
15554 | * worst a fifo underrun happens which also sets this to false. | |
15555 | */ | |
15556 | crtc->cpu_fifo_underrun_disabled = true; | |
15557 | crtc->pch_fifo_underrun_disabled = true; | |
15558 | } | |
24929352 DV |
15559 | } |
15560 | ||
15561 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15562 | { | |
15563 | struct intel_connector *connector; | |
15564 | struct drm_device *dev = encoder->base.dev; | |
873ffe69 | 15565 | bool active = false; |
24929352 DV |
15566 | |
15567 | /* We need to check both for a crtc link (meaning that the | |
15568 | * encoder is active and trying to read from a pipe) and the | |
15569 | * pipe itself being active. */ | |
15570 | bool has_active_crtc = encoder->base.crtc && | |
15571 | to_intel_crtc(encoder->base.crtc)->active; | |
15572 | ||
873ffe69 ML |
15573 | for_each_intel_connector(dev, connector) { |
15574 | if (connector->base.encoder != &encoder->base) | |
15575 | continue; | |
15576 | ||
15577 | active = true; | |
15578 | break; | |
15579 | } | |
15580 | ||
15581 | if (active && !has_active_crtc) { | |
24929352 DV |
15582 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15583 | encoder->base.base.id, | |
8e329a03 | 15584 | encoder->base.name); |
24929352 DV |
15585 | |
15586 | /* Connector is active, but has no active pipe. This is | |
15587 | * fallout from our resume register restoring. Disable | |
15588 | * the encoder manually again. */ | |
15589 | if (encoder->base.crtc) { | |
15590 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15591 | encoder->base.base.id, | |
8e329a03 | 15592 | encoder->base.name); |
24929352 | 15593 | encoder->disable(encoder); |
a62d1497 VS |
15594 | if (encoder->post_disable) |
15595 | encoder->post_disable(encoder); | |
24929352 | 15596 | } |
7f1950fb | 15597 | encoder->base.crtc = NULL; |
24929352 DV |
15598 | |
15599 | /* Inconsistent output/port/pipe state happens presumably due to | |
15600 | * a bug in one of the get_hw_state functions. Or someplace else | |
15601 | * in our code, like the register restore mess on resume. Clamp | |
15602 | * things to off as a safer default. */ | |
3a3371ff | 15603 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15604 | if (connector->encoder != encoder) |
15605 | continue; | |
7f1950fb EE |
15606 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15607 | connector->base.encoder = NULL; | |
24929352 DV |
15608 | } |
15609 | } | |
15610 | /* Enabled encoders without active connectors will be fixed in | |
15611 | * the crtc fixup. */ | |
15612 | } | |
15613 | ||
04098753 | 15614 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15615 | { |
15616 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15617 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15618 | |
04098753 ID |
15619 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15620 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15621 | i915_disable_vga(dev); | |
15622 | } | |
15623 | } | |
15624 | ||
15625 | void i915_redisable_vga(struct drm_device *dev) | |
15626 | { | |
15627 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15628 | ||
8dc8a27c PZ |
15629 | /* This function can be called both from intel_modeset_setup_hw_state or |
15630 | * at a very early point in our resume sequence, where the power well | |
15631 | * structures are not yet restored. Since this function is at a very | |
15632 | * paranoid "someone might have enabled VGA while we were not looking" | |
15633 | * level, just check if the power well is enabled instead of trying to | |
15634 | * follow the "don't touch the power well if we don't need it" policy | |
15635 | * the rest of the driver uses. */ | |
f458ebbc | 15636 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15637 | return; |
15638 | ||
04098753 | 15639 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15640 | } |
15641 | ||
f9cd7b88 | 15642 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15643 | { |
f9cd7b88 | 15644 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15645 | |
f9cd7b88 | 15646 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15647 | } |
15648 | ||
f9cd7b88 VS |
15649 | /* FIXME read out full plane state for all planes */ |
15650 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15651 | { |
b26d3ea3 | 15652 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15653 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15654 | to_intel_plane_state(primary->state); |
d032ffa0 | 15655 | |
19b8d387 | 15656 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15657 | primary_get_hw_state(to_intel_plane(primary)); |
15658 | ||
15659 | if (plane_state->visible) | |
15660 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15661 | } |
15662 | ||
30e984df | 15663 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15664 | { |
15665 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15666 | enum pipe pipe; | |
24929352 DV |
15667 | struct intel_crtc *crtc; |
15668 | struct intel_encoder *encoder; | |
15669 | struct intel_connector *connector; | |
5358901f | 15670 | int i; |
24929352 | 15671 | |
565602d7 ML |
15672 | dev_priv->active_crtcs = 0; |
15673 | ||
d3fcc808 | 15674 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15675 | struct intel_crtc_state *crtc_state = crtc->config; |
15676 | int pixclk = 0; | |
3b117c8f | 15677 | |
565602d7 ML |
15678 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15679 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15680 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15681 | |
565602d7 ML |
15682 | crtc_state->base.active = crtc_state->base.enable = |
15683 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15684 | ||
15685 | crtc->base.enabled = crtc_state->base.enable; | |
15686 | crtc->active = crtc_state->base.active; | |
15687 | ||
15688 | if (crtc_state->base.active) { | |
15689 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15690 | ||
15691 | if (IS_BROADWELL(dev_priv)) { | |
15692 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15693 | ||
15694 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15695 | if (crtc_state->ips_enabled) | |
15696 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15697 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15698 | IS_CHERRYVIEW(dev_priv) || | |
15699 | IS_BROXTON(dev_priv)) | |
15700 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15701 | else | |
15702 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15703 | } | |
15704 | ||
15705 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15706 | |
f9cd7b88 | 15707 | readout_plane_state(crtc); |
24929352 DV |
15708 | |
15709 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15710 | crtc->base.base.id, | |
15711 | crtc->active ? "enabled" : "disabled"); | |
15712 | } | |
15713 | ||
5358901f DV |
15714 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15715 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15716 | ||
3e369b76 ACO |
15717 | pll->on = pll->get_hw_state(dev_priv, pll, |
15718 | &pll->config.hw_state); | |
5358901f | 15719 | pll->active = 0; |
3e369b76 | 15720 | pll->config.crtc_mask = 0; |
d3fcc808 | 15721 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15722 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15723 | pll->active++; |
3e369b76 | 15724 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15725 | } |
5358901f | 15726 | } |
5358901f | 15727 | |
1e6f2ddc | 15728 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15729 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15730 | |
3e369b76 | 15731 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15732 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15733 | } |
15734 | ||
b2784e15 | 15735 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15736 | pipe = 0; |
15737 | ||
15738 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15739 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15740 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15741 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15742 | } else { |
15743 | encoder->base.crtc = NULL; | |
15744 | } | |
15745 | ||
6f2bcceb | 15746 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15747 | encoder->base.base.id, |
8e329a03 | 15748 | encoder->base.name, |
24929352 | 15749 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15750 | pipe_name(pipe)); |
24929352 DV |
15751 | } |
15752 | ||
3a3371ff | 15753 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15754 | if (connector->get_hw_state(connector)) { |
15755 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15756 | |
15757 | encoder = connector->encoder; | |
15758 | connector->base.encoder = &encoder->base; | |
15759 | ||
15760 | if (encoder->base.crtc && | |
15761 | encoder->base.crtc->state->active) { | |
15762 | /* | |
15763 | * This has to be done during hardware readout | |
15764 | * because anything calling .crtc_disable may | |
15765 | * rely on the connector_mask being accurate. | |
15766 | */ | |
15767 | encoder->base.crtc->state->connector_mask |= | |
15768 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15769 | encoder->base.crtc->state->encoder_mask |= |
15770 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15771 | } |
15772 | ||
24929352 DV |
15773 | } else { |
15774 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15775 | connector->base.encoder = NULL; | |
15776 | } | |
15777 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15778 | connector->base.base.id, | |
c23cc417 | 15779 | connector->base.name, |
24929352 DV |
15780 | connector->base.encoder ? "enabled" : "disabled"); |
15781 | } | |
7f4c6284 VS |
15782 | |
15783 | for_each_intel_crtc(dev, crtc) { | |
15784 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15785 | ||
15786 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15787 | if (crtc->base.state->active) { | |
15788 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15789 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15790 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15791 | ||
15792 | /* | |
15793 | * The initial mode needs to be set in order to keep | |
15794 | * the atomic core happy. It wants a valid mode if the | |
15795 | * crtc's enabled, so we do the above call. | |
15796 | * | |
15797 | * At this point some state updated by the connectors | |
15798 | * in their ->detect() callback has not run yet, so | |
15799 | * no recalculation can be done yet. | |
15800 | * | |
15801 | * Even if we could do a recalculation and modeset | |
15802 | * right now it would cause a double modeset if | |
15803 | * fbdev or userspace chooses a different initial mode. | |
15804 | * | |
15805 | * If that happens, someone indicated they wanted a | |
15806 | * mode change, which means it's safe to do a full | |
15807 | * recalculation. | |
15808 | */ | |
15809 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15810 | |
15811 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15812 | update_scanline_offset(crtc); | |
7f4c6284 VS |
15813 | } |
15814 | } | |
30e984df DV |
15815 | } |
15816 | ||
043e9bda ML |
15817 | /* Scan out the current hw modeset state, |
15818 | * and sanitizes it to the current state | |
15819 | */ | |
15820 | static void | |
15821 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15822 | { |
15823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15824 | enum pipe pipe; | |
30e984df DV |
15825 | struct intel_crtc *crtc; |
15826 | struct intel_encoder *encoder; | |
35c95375 | 15827 | int i; |
30e984df DV |
15828 | |
15829 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15830 | |
15831 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15832 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15833 | intel_sanitize_encoder(encoder); |
15834 | } | |
15835 | ||
055e393f | 15836 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15837 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15838 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15839 | intel_dump_pipe_config(crtc, crtc->config, |
15840 | "[setup_hw_state]"); | |
24929352 | 15841 | } |
9a935856 | 15842 | |
d29b2f9d ACO |
15843 | intel_modeset_update_connector_atomic_state(dev); |
15844 | ||
35c95375 DV |
15845 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15846 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15847 | ||
15848 | if (!pll->on || pll->active) | |
15849 | continue; | |
15850 | ||
15851 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15852 | ||
15853 | pll->disable(dev_priv, pll); | |
15854 | pll->on = false; | |
15855 | } | |
15856 | ||
666a4537 | 15857 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
15858 | vlv_wm_get_hw_state(dev); |
15859 | else if (IS_GEN9(dev)) | |
3078999f PB |
15860 | skl_wm_get_hw_state(dev); |
15861 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15862 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15863 | |
15864 | for_each_intel_crtc(dev, crtc) { | |
15865 | unsigned long put_domains; | |
15866 | ||
15867 | put_domains = modeset_get_crtc_power_domains(&crtc->base); | |
15868 | if (WARN_ON(put_domains)) | |
15869 | modeset_put_power_domains(dev_priv, put_domains); | |
15870 | } | |
15871 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
15872 | |
15873 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 15874 | } |
7d0bc1ea | 15875 | |
043e9bda ML |
15876 | void intel_display_resume(struct drm_device *dev) |
15877 | { | |
e2c8b870 ML |
15878 | struct drm_i915_private *dev_priv = to_i915(dev); |
15879 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15880 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15881 | int ret; |
e2c8b870 | 15882 | bool setup = false; |
f30da187 | 15883 | |
e2c8b870 | 15884 | dev_priv->modeset_restore_state = NULL; |
043e9bda | 15885 | |
e2c8b870 | 15886 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15887 | |
e2c8b870 ML |
15888 | retry: |
15889 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
043e9bda | 15890 | |
e2c8b870 ML |
15891 | if (ret == 0 && !setup) { |
15892 | setup = true; | |
043e9bda | 15893 | |
e2c8b870 ML |
15894 | intel_modeset_setup_hw_state(dev); |
15895 | i915_redisable_vga(dev); | |
45e2b5f6 | 15896 | } |
8af6cf88 | 15897 | |
e2c8b870 ML |
15898 | if (ret == 0 && state) { |
15899 | struct drm_crtc_state *crtc_state; | |
15900 | struct drm_crtc *crtc; | |
15901 | int i; | |
043e9bda | 15902 | |
e2c8b870 ML |
15903 | state->acquire_ctx = &ctx; |
15904 | ||
15905 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
15906 | /* | |
15907 | * Force recalculation even if we restore | |
15908 | * current state. With fast modeset this may not result | |
15909 | * in a modeset when the state is compatible. | |
15910 | */ | |
15911 | crtc_state->mode_changed = true; | |
15912 | } | |
15913 | ||
15914 | ret = drm_atomic_commit(state); | |
043e9bda ML |
15915 | } |
15916 | ||
e2c8b870 ML |
15917 | if (ret == -EDEADLK) { |
15918 | drm_modeset_backoff(&ctx); | |
15919 | goto retry; | |
15920 | } | |
043e9bda | 15921 | |
e2c8b870 ML |
15922 | drm_modeset_drop_locks(&ctx); |
15923 | drm_modeset_acquire_fini(&ctx); | |
043e9bda | 15924 | |
e2c8b870 ML |
15925 | if (ret) { |
15926 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15927 | drm_atomic_state_free(state); | |
15928 | } | |
2c7111db CW |
15929 | } |
15930 | ||
15931 | void intel_modeset_gem_init(struct drm_device *dev) | |
15932 | { | |
484b41dd | 15933 | struct drm_crtc *c; |
2ff8fde1 | 15934 | struct drm_i915_gem_object *obj; |
e0d6149b | 15935 | int ret; |
484b41dd | 15936 | |
ae48434c | 15937 | intel_init_gt_powersave(dev); |
ae48434c | 15938 | |
1833b134 | 15939 | intel_modeset_init_hw(dev); |
02e792fb DV |
15940 | |
15941 | intel_setup_overlay(dev); | |
484b41dd JB |
15942 | |
15943 | /* | |
15944 | * Make sure any fbs we allocated at startup are properly | |
15945 | * pinned & fenced. When we do the allocation it's too early | |
15946 | * for this. | |
15947 | */ | |
70e1e0ec | 15948 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15949 | obj = intel_fb_obj(c->primary->fb); |
15950 | if (obj == NULL) | |
484b41dd JB |
15951 | continue; |
15952 | ||
e0d6149b TU |
15953 | mutex_lock(&dev->struct_mutex); |
15954 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
15955 | c->primary->fb, | |
7580d774 | 15956 | c->primary->state); |
e0d6149b TU |
15957 | mutex_unlock(&dev->struct_mutex); |
15958 | if (ret) { | |
484b41dd JB |
15959 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15960 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15961 | drm_framebuffer_unreference(c->primary->fb); |
15962 | c->primary->fb = NULL; | |
36750f28 | 15963 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 15964 | update_state_fb(c->primary); |
36750f28 | 15965 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
15966 | } |
15967 | } | |
0962c3c9 VS |
15968 | |
15969 | intel_backlight_register(dev); | |
79e53945 JB |
15970 | } |
15971 | ||
4932e2c3 ID |
15972 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15973 | { | |
15974 | struct drm_connector *connector = &intel_connector->base; | |
15975 | ||
15976 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15977 | drm_connector_unregister(connector); |
4932e2c3 ID |
15978 | } |
15979 | ||
79e53945 JB |
15980 | void intel_modeset_cleanup(struct drm_device *dev) |
15981 | { | |
652c393a | 15982 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 15983 | struct intel_connector *connector; |
652c393a | 15984 | |
2eb5252e ID |
15985 | intel_disable_gt_powersave(dev); |
15986 | ||
0962c3c9 VS |
15987 | intel_backlight_unregister(dev); |
15988 | ||
fd0c0642 DV |
15989 | /* |
15990 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15991 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15992 | * experience fancy races otherwise. |
15993 | */ | |
2aeb7d3a | 15994 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15995 | |
fd0c0642 DV |
15996 | /* |
15997 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15998 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15999 | */ | |
f87ea761 | 16000 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16001 | |
723bfd70 JB |
16002 | intel_unregister_dsm_handler(); |
16003 | ||
c937ab3e | 16004 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16005 | |
1630fe75 CW |
16006 | /* flush any delayed tasks or pending work */ |
16007 | flush_scheduled_work(); | |
16008 | ||
db31af1d | 16009 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
16010 | for_each_intel_connector(dev, connector) |
16011 | connector->unregister(connector); | |
d9255d57 | 16012 | |
79e53945 | 16013 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
16014 | |
16015 | intel_cleanup_overlay(dev); | |
ae48434c | 16016 | |
ae48434c | 16017 | intel_cleanup_gt_powersave(dev); |
f5949141 DV |
16018 | |
16019 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16020 | } |
16021 | ||
f1c79df3 ZW |
16022 | /* |
16023 | * Return which encoder is currently attached for connector. | |
16024 | */ | |
df0e9248 | 16025 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 16026 | { |
df0e9248 CW |
16027 | return &intel_attached_encoder(connector)->base; |
16028 | } | |
f1c79df3 | 16029 | |
df0e9248 CW |
16030 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16031 | struct intel_encoder *encoder) | |
16032 | { | |
16033 | connector->encoder = encoder; | |
16034 | drm_mode_connector_attach_encoder(&connector->base, | |
16035 | &encoder->base); | |
79e53945 | 16036 | } |
28d52043 DA |
16037 | |
16038 | /* | |
16039 | * set vga decode state - true == enable VGA decode | |
16040 | */ | |
16041 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16042 | { | |
16043 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 16044 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16045 | u16 gmch_ctrl; |
16046 | ||
75fa041d CW |
16047 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16048 | DRM_ERROR("failed to read control word\n"); | |
16049 | return -EIO; | |
16050 | } | |
16051 | ||
c0cc8a55 CW |
16052 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16053 | return 0; | |
16054 | ||
28d52043 DA |
16055 | if (state) |
16056 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16057 | else | |
16058 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16059 | |
16060 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16061 | DRM_ERROR("failed to write control word\n"); | |
16062 | return -EIO; | |
16063 | } | |
16064 | ||
28d52043 DA |
16065 | return 0; |
16066 | } | |
c4a1d9e4 | 16067 | |
c4a1d9e4 | 16068 | struct intel_display_error_state { |
ff57f1b0 PZ |
16069 | |
16070 | u32 power_well_driver; | |
16071 | ||
63b66e5b CW |
16072 | int num_transcoders; |
16073 | ||
c4a1d9e4 CW |
16074 | struct intel_cursor_error_state { |
16075 | u32 control; | |
16076 | u32 position; | |
16077 | u32 base; | |
16078 | u32 size; | |
52331309 | 16079 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16080 | |
16081 | struct intel_pipe_error_state { | |
ddf9c536 | 16082 | bool power_domain_on; |
c4a1d9e4 | 16083 | u32 source; |
f301b1e1 | 16084 | u32 stat; |
52331309 | 16085 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16086 | |
16087 | struct intel_plane_error_state { | |
16088 | u32 control; | |
16089 | u32 stride; | |
16090 | u32 size; | |
16091 | u32 pos; | |
16092 | u32 addr; | |
16093 | u32 surface; | |
16094 | u32 tile_offset; | |
52331309 | 16095 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16096 | |
16097 | struct intel_transcoder_error_state { | |
ddf9c536 | 16098 | bool power_domain_on; |
63b66e5b CW |
16099 | enum transcoder cpu_transcoder; |
16100 | ||
16101 | u32 conf; | |
16102 | ||
16103 | u32 htotal; | |
16104 | u32 hblank; | |
16105 | u32 hsync; | |
16106 | u32 vtotal; | |
16107 | u32 vblank; | |
16108 | u32 vsync; | |
16109 | } transcoder[4]; | |
c4a1d9e4 CW |
16110 | }; |
16111 | ||
16112 | struct intel_display_error_state * | |
16113 | intel_display_capture_error_state(struct drm_device *dev) | |
16114 | { | |
fbee40df | 16115 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 16116 | struct intel_display_error_state *error; |
63b66e5b CW |
16117 | int transcoders[] = { |
16118 | TRANSCODER_A, | |
16119 | TRANSCODER_B, | |
16120 | TRANSCODER_C, | |
16121 | TRANSCODER_EDP, | |
16122 | }; | |
c4a1d9e4 CW |
16123 | int i; |
16124 | ||
63b66e5b CW |
16125 | if (INTEL_INFO(dev)->num_pipes == 0) |
16126 | return NULL; | |
16127 | ||
9d1cb914 | 16128 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16129 | if (error == NULL) |
16130 | return NULL; | |
16131 | ||
190be112 | 16132 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
16133 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16134 | ||
055e393f | 16135 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16136 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16137 | __intel_display_power_is_enabled(dev_priv, |
16138 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16139 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16140 | continue; |
16141 | ||
5efb3e28 VS |
16142 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16143 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16144 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16145 | |
16146 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16147 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 16148 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 16149 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16150 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16151 | } | |
ca291363 PZ |
16152 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
16153 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
16154 | if (INTEL_INFO(dev)->gen >= 4) { |
16155 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16156 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16157 | } | |
16158 | ||
c4a1d9e4 | 16159 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16160 | |
3abfce77 | 16161 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 16162 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16163 | } |
16164 | ||
16165 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
16166 | if (HAS_DDI(dev_priv->dev)) | |
16167 | error->num_transcoders++; /* Account for eDP. */ | |
16168 | ||
16169 | for (i = 0; i < error->num_transcoders; i++) { | |
16170 | enum transcoder cpu_transcoder = transcoders[i]; | |
16171 | ||
ddf9c536 | 16172 | error->transcoder[i].power_domain_on = |
f458ebbc | 16173 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16174 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16175 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16176 | continue; |
16177 | ||
63b66e5b CW |
16178 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16179 | ||
16180 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16181 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16182 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16183 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16184 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16185 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16186 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16187 | } |
16188 | ||
16189 | return error; | |
16190 | } | |
16191 | ||
edc3d884 MK |
16192 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16193 | ||
c4a1d9e4 | 16194 | void |
edc3d884 | 16195 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16196 | struct drm_device *dev, |
16197 | struct intel_display_error_state *error) | |
16198 | { | |
055e393f | 16199 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16200 | int i; |
16201 | ||
63b66e5b CW |
16202 | if (!error) |
16203 | return; | |
16204 | ||
edc3d884 | 16205 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16206 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16207 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16208 | error->power_well_driver); |
055e393f | 16209 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16210 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16211 | err_printf(m, " Power: %s\n", |
87ad3212 | 16212 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16213 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16214 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16215 | |
16216 | err_printf(m, "Plane [%d]:\n", i); | |
16217 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16218 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16219 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16220 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16221 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16222 | } |
4b71a570 | 16223 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16224 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16225 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16226 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16227 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16228 | } |
16229 | ||
edc3d884 MK |
16230 | err_printf(m, "Cursor [%d]:\n", i); |
16231 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16232 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16233 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16234 | } |
63b66e5b CW |
16235 | |
16236 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 16237 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 16238 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16239 | err_printf(m, " Power: %s\n", |
87ad3212 | 16240 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16241 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16242 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16243 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16244 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16245 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16246 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16247 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16248 | } | |
c4a1d9e4 | 16249 | } |