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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
c37efb99 | 39 | #include "i915_gem_dmabuf.h" |
db18b6a6 | 40 | #include "intel_dsi.h" |
e5510fac | 41 | #include "i915_trace.h" |
319c1d42 | 42 | #include <drm/drm_atomic.h> |
c196e1d6 | 43 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
44 | #include <drm/drm_dp_helper.h> |
45 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
46 | #include <drm/drm_plane_helper.h> |
47 | #include <drm/drm_rect.h> | |
c0f372b3 | 48 | #include <linux/dma_remapping.h> |
fd8e058a | 49 | #include <linux/reservation.h> |
79e53945 | 50 | |
5a21b665 DV |
51 | static bool is_mmio_work(struct intel_flip_work *work) |
52 | { | |
53 | return work->mmio_work.func; | |
54 | } | |
55 | ||
465c120c | 56 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 57 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
58 | DRM_FORMAT_C8, |
59 | DRM_FORMAT_RGB565, | |
465c120c | 60 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 61 | DRM_FORMAT_XRGB8888, |
465c120c MR |
62 | }; |
63 | ||
64 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 65 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
66 | DRM_FORMAT_C8, |
67 | DRM_FORMAT_RGB565, | |
68 | DRM_FORMAT_XRGB8888, | |
69 | DRM_FORMAT_XBGR8888, | |
70 | DRM_FORMAT_XRGB2101010, | |
71 | DRM_FORMAT_XBGR2101010, | |
72 | }; | |
73 | ||
74 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
75 | DRM_FORMAT_C8, |
76 | DRM_FORMAT_RGB565, | |
77 | DRM_FORMAT_XRGB8888, | |
465c120c | 78 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 79 | DRM_FORMAT_ARGB8888, |
465c120c MR |
80 | DRM_FORMAT_ABGR8888, |
81 | DRM_FORMAT_XRGB2101010, | |
465c120c | 82 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
83 | DRM_FORMAT_YUYV, |
84 | DRM_FORMAT_YVYU, | |
85 | DRM_FORMAT_UYVY, | |
86 | DRM_FORMAT_VYUY, | |
465c120c MR |
87 | }; |
88 | ||
3d7d6510 MR |
89 | /* Cursor formats */ |
90 | static const uint32_t intel_cursor_formats[] = { | |
91 | DRM_FORMAT_ARGB8888, | |
92 | }; | |
93 | ||
f1f644dc | 94 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 95 | struct intel_crtc_state *pipe_config); |
18442d08 | 96 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 97 | struct intel_crtc_state *pipe_config); |
f1f644dc | 98 | |
eb1bfe80 JB |
99 | static int intel_framebuffer_init(struct drm_device *dev, |
100 | struct intel_framebuffer *ifb, | |
101 | struct drm_mode_fb_cmd2 *mode_cmd, | |
102 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
103 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
104 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 105 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 106 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
107 | struct intel_link_m_n *m_n, |
108 | struct intel_link_m_n *m2_n2); | |
29407aab | 109 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 110 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 111 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 112 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 113 | const struct intel_crtc_state *pipe_config); |
d288f65f | 114 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 115 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
116 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
117 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
118 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
119 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
120 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
121 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
122 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 123 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 124 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
4e5ca60f | 125 | static int ilk_max_pixel_rate(struct drm_atomic_state *state); |
324513c0 | 126 | static int bxt_calc_cdclk(int max_pixclk); |
e7457a9a | 127 | |
d4906093 | 128 | struct intel_limit { |
4c5def93 ACO |
129 | struct { |
130 | int min, max; | |
131 | } dot, vco, n, m, m1, m2, p, p1; | |
132 | ||
133 | struct { | |
134 | int dot_limit; | |
135 | int p2_slow, p2_fast; | |
136 | } p2; | |
d4906093 | 137 | }; |
79e53945 | 138 | |
bfa7df01 VS |
139 | /* returns HPLL frequency in kHz */ |
140 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
141 | { | |
142 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
143 | ||
144 | /* Obtain SKU information */ | |
145 | mutex_lock(&dev_priv->sb_lock); | |
146 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
147 | CCK_FUSE_HPLL_FREQ_MASK; | |
148 | mutex_unlock(&dev_priv->sb_lock); | |
149 | ||
150 | return vco_freq[hpll_freq] * 1000; | |
151 | } | |
152 | ||
c30fec65 VS |
153 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
154 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
155 | { |
156 | u32 val; | |
157 | int divider; | |
158 | ||
bfa7df01 VS |
159 | mutex_lock(&dev_priv->sb_lock); |
160 | val = vlv_cck_read(dev_priv, reg); | |
161 | mutex_unlock(&dev_priv->sb_lock); | |
162 | ||
163 | divider = val & CCK_FREQUENCY_VALUES; | |
164 | ||
165 | WARN((val & CCK_FREQUENCY_STATUS) != | |
166 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
167 | "%s change in progress\n", name); | |
168 | ||
c30fec65 VS |
169 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
170 | } | |
171 | ||
172 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
173 | const char *name, u32 reg) | |
174 | { | |
175 | if (dev_priv->hpll_freq == 0) | |
176 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
177 | ||
178 | return vlv_get_cck_clock(dev_priv, name, reg, | |
179 | dev_priv->hpll_freq); | |
bfa7df01 VS |
180 | } |
181 | ||
e7dc33f3 VS |
182 | static int |
183 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 184 | { |
e7dc33f3 VS |
185 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
186 | } | |
d2acd215 | 187 | |
e7dc33f3 VS |
188 | static int |
189 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
190 | { | |
19ab4ed3 | 191 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
35d38d1f VS |
192 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
193 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
194 | } |
195 | ||
e7dc33f3 VS |
196 | static int |
197 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 198 | { |
79e50a4f JN |
199 | uint32_t clkcfg; |
200 | ||
e7dc33f3 | 201 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
202 | clkcfg = I915_READ(CLKCFG); |
203 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
204 | case CLKCFG_FSB_400: | |
e7dc33f3 | 205 | return 100000; |
79e50a4f | 206 | case CLKCFG_FSB_533: |
e7dc33f3 | 207 | return 133333; |
79e50a4f | 208 | case CLKCFG_FSB_667: |
e7dc33f3 | 209 | return 166667; |
79e50a4f | 210 | case CLKCFG_FSB_800: |
e7dc33f3 | 211 | return 200000; |
79e50a4f | 212 | case CLKCFG_FSB_1067: |
e7dc33f3 | 213 | return 266667; |
79e50a4f | 214 | case CLKCFG_FSB_1333: |
e7dc33f3 | 215 | return 333333; |
79e50a4f JN |
216 | /* these two are just a guess; one of them might be right */ |
217 | case CLKCFG_FSB_1600: | |
218 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 219 | return 400000; |
79e50a4f | 220 | default: |
e7dc33f3 | 221 | return 133333; |
79e50a4f JN |
222 | } |
223 | } | |
224 | ||
19ab4ed3 | 225 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
e7dc33f3 VS |
226 | { |
227 | if (HAS_PCH_SPLIT(dev_priv)) | |
228 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
229 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
230 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
231 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
232 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
233 | else | |
234 | return; /* no rawclk on other platforms, or no need to know it */ | |
235 | ||
236 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
237 | } | |
238 | ||
bfa7df01 VS |
239 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
240 | { | |
666a4537 | 241 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
242 | return; |
243 | ||
244 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
245 | CCK_CZ_CLOCK_CONTROL); | |
246 | ||
247 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
248 | } | |
249 | ||
021357ac | 250 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
251 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
252 | const struct intel_crtc_state *pipe_config) | |
021357ac | 253 | { |
21a727b3 VS |
254 | if (HAS_DDI(dev_priv)) |
255 | return pipe_config->port_clock; /* SPLL */ | |
256 | else if (IS_GEN5(dev_priv)) | |
257 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 258 | else |
21a727b3 | 259 | return 270000; |
021357ac CW |
260 | } |
261 | ||
1b6f4958 | 262 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 263 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 264 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 265 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
266 | .m = { .min = 96, .max = 140 }, |
267 | .m1 = { .min = 18, .max = 26 }, | |
268 | .m2 = { .min = 6, .max = 16 }, | |
269 | .p = { .min = 4, .max = 128 }, | |
270 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
271 | .p2 = { .dot_limit = 165000, |
272 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
273 | }; |
274 | ||
1b6f4958 | 275 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 276 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 277 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 278 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
279 | .m = { .min = 96, .max = 140 }, |
280 | .m1 = { .min = 18, .max = 26 }, | |
281 | .m2 = { .min = 6, .max = 16 }, | |
282 | .p = { .min = 4, .max = 128 }, | |
283 | .p1 = { .min = 2, .max = 33 }, | |
284 | .p2 = { .dot_limit = 165000, | |
285 | .p2_slow = 4, .p2_fast = 4 }, | |
286 | }; | |
287 | ||
1b6f4958 | 288 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 289 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 290 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 291 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
292 | .m = { .min = 96, .max = 140 }, |
293 | .m1 = { .min = 18, .max = 26 }, | |
294 | .m2 = { .min = 6, .max = 16 }, | |
295 | .p = { .min = 4, .max = 128 }, | |
296 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
297 | .p2 = { .dot_limit = 165000, |
298 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 299 | }; |
273e27ca | 300 | |
1b6f4958 | 301 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
302 | .dot = { .min = 20000, .max = 400000 }, |
303 | .vco = { .min = 1400000, .max = 2800000 }, | |
304 | .n = { .min = 1, .max = 6 }, | |
305 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
306 | .m1 = { .min = 8, .max = 18 }, |
307 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
308 | .p = { .min = 5, .max = 80 }, |
309 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
310 | .p2 = { .dot_limit = 200000, |
311 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
312 | }; |
313 | ||
1b6f4958 | 314 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
315 | .dot = { .min = 20000, .max = 400000 }, |
316 | .vco = { .min = 1400000, .max = 2800000 }, | |
317 | .n = { .min = 1, .max = 6 }, | |
318 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
319 | .m1 = { .min = 8, .max = 18 }, |
320 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
321 | .p = { .min = 7, .max = 98 }, |
322 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
323 | .p2 = { .dot_limit = 112000, |
324 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
325 | }; |
326 | ||
273e27ca | 327 | |
1b6f4958 | 328 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
329 | .dot = { .min = 25000, .max = 270000 }, |
330 | .vco = { .min = 1750000, .max = 3500000}, | |
331 | .n = { .min = 1, .max = 4 }, | |
332 | .m = { .min = 104, .max = 138 }, | |
333 | .m1 = { .min = 17, .max = 23 }, | |
334 | .m2 = { .min = 5, .max = 11 }, | |
335 | .p = { .min = 10, .max = 30 }, | |
336 | .p1 = { .min = 1, .max = 3}, | |
337 | .p2 = { .dot_limit = 270000, | |
338 | .p2_slow = 10, | |
339 | .p2_fast = 10 | |
044c7c41 | 340 | }, |
e4b36699 KP |
341 | }; |
342 | ||
1b6f4958 | 343 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
344 | .dot = { .min = 22000, .max = 400000 }, |
345 | .vco = { .min = 1750000, .max = 3500000}, | |
346 | .n = { .min = 1, .max = 4 }, | |
347 | .m = { .min = 104, .max = 138 }, | |
348 | .m1 = { .min = 16, .max = 23 }, | |
349 | .m2 = { .min = 5, .max = 11 }, | |
350 | .p = { .min = 5, .max = 80 }, | |
351 | .p1 = { .min = 1, .max = 8}, | |
352 | .p2 = { .dot_limit = 165000, | |
353 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
354 | }; |
355 | ||
1b6f4958 | 356 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
357 | .dot = { .min = 20000, .max = 115000 }, |
358 | .vco = { .min = 1750000, .max = 3500000 }, | |
359 | .n = { .min = 1, .max = 3 }, | |
360 | .m = { .min = 104, .max = 138 }, | |
361 | .m1 = { .min = 17, .max = 23 }, | |
362 | .m2 = { .min = 5, .max = 11 }, | |
363 | .p = { .min = 28, .max = 112 }, | |
364 | .p1 = { .min = 2, .max = 8 }, | |
365 | .p2 = { .dot_limit = 0, | |
366 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 367 | }, |
e4b36699 KP |
368 | }; |
369 | ||
1b6f4958 | 370 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
371 | .dot = { .min = 80000, .max = 224000 }, |
372 | .vco = { .min = 1750000, .max = 3500000 }, | |
373 | .n = { .min = 1, .max = 3 }, | |
374 | .m = { .min = 104, .max = 138 }, | |
375 | .m1 = { .min = 17, .max = 23 }, | |
376 | .m2 = { .min = 5, .max = 11 }, | |
377 | .p = { .min = 14, .max = 42 }, | |
378 | .p1 = { .min = 2, .max = 6 }, | |
379 | .p2 = { .dot_limit = 0, | |
380 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 381 | }, |
e4b36699 KP |
382 | }; |
383 | ||
1b6f4958 | 384 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
385 | .dot = { .min = 20000, .max = 400000}, |
386 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 387 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
388 | .n = { .min = 3, .max = 6 }, |
389 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 390 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
391 | .m1 = { .min = 0, .max = 0 }, |
392 | .m2 = { .min = 0, .max = 254 }, | |
393 | .p = { .min = 5, .max = 80 }, | |
394 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
395 | .p2 = { .dot_limit = 200000, |
396 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
397 | }; |
398 | ||
1b6f4958 | 399 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
400 | .dot = { .min = 20000, .max = 400000 }, |
401 | .vco = { .min = 1700000, .max = 3500000 }, | |
402 | .n = { .min = 3, .max = 6 }, | |
403 | .m = { .min = 2, .max = 256 }, | |
404 | .m1 = { .min = 0, .max = 0 }, | |
405 | .m2 = { .min = 0, .max = 254 }, | |
406 | .p = { .min = 7, .max = 112 }, | |
407 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
408 | .p2 = { .dot_limit = 112000, |
409 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
410 | }; |
411 | ||
273e27ca EA |
412 | /* Ironlake / Sandybridge |
413 | * | |
414 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
415 | * the range value for them is (actual_value - 2). | |
416 | */ | |
1b6f4958 | 417 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
418 | .dot = { .min = 25000, .max = 350000 }, |
419 | .vco = { .min = 1760000, .max = 3510000 }, | |
420 | .n = { .min = 1, .max = 5 }, | |
421 | .m = { .min = 79, .max = 127 }, | |
422 | .m1 = { .min = 12, .max = 22 }, | |
423 | .m2 = { .min = 5, .max = 9 }, | |
424 | .p = { .min = 5, .max = 80 }, | |
425 | .p1 = { .min = 1, .max = 8 }, | |
426 | .p2 = { .dot_limit = 225000, | |
427 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
428 | }; |
429 | ||
1b6f4958 | 430 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
431 | .dot = { .min = 25000, .max = 350000 }, |
432 | .vco = { .min = 1760000, .max = 3510000 }, | |
433 | .n = { .min = 1, .max = 3 }, | |
434 | .m = { .min = 79, .max = 118 }, | |
435 | .m1 = { .min = 12, .max = 22 }, | |
436 | .m2 = { .min = 5, .max = 9 }, | |
437 | .p = { .min = 28, .max = 112 }, | |
438 | .p1 = { .min = 2, .max = 8 }, | |
439 | .p2 = { .dot_limit = 225000, | |
440 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
441 | }; |
442 | ||
1b6f4958 | 443 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
444 | .dot = { .min = 25000, .max = 350000 }, |
445 | .vco = { .min = 1760000, .max = 3510000 }, | |
446 | .n = { .min = 1, .max = 3 }, | |
447 | .m = { .min = 79, .max = 127 }, | |
448 | .m1 = { .min = 12, .max = 22 }, | |
449 | .m2 = { .min = 5, .max = 9 }, | |
450 | .p = { .min = 14, .max = 56 }, | |
451 | .p1 = { .min = 2, .max = 8 }, | |
452 | .p2 = { .dot_limit = 225000, | |
453 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
454 | }; |
455 | ||
273e27ca | 456 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 457 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
458 | .dot = { .min = 25000, .max = 350000 }, |
459 | .vco = { .min = 1760000, .max = 3510000 }, | |
460 | .n = { .min = 1, .max = 2 }, | |
461 | .m = { .min = 79, .max = 126 }, | |
462 | .m1 = { .min = 12, .max = 22 }, | |
463 | .m2 = { .min = 5, .max = 9 }, | |
464 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 465 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
466 | .p2 = { .dot_limit = 225000, |
467 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
468 | }; |
469 | ||
1b6f4958 | 470 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
471 | .dot = { .min = 25000, .max = 350000 }, |
472 | .vco = { .min = 1760000, .max = 3510000 }, | |
473 | .n = { .min = 1, .max = 3 }, | |
474 | .m = { .min = 79, .max = 126 }, | |
475 | .m1 = { .min = 12, .max = 22 }, | |
476 | .m2 = { .min = 5, .max = 9 }, | |
477 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 478 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
479 | .p2 = { .dot_limit = 225000, |
480 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
481 | }; |
482 | ||
1b6f4958 | 483 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
484 | /* |
485 | * These are the data rate limits (measured in fast clocks) | |
486 | * since those are the strictest limits we have. The fast | |
487 | * clock and actual rate limits are more relaxed, so checking | |
488 | * them would make no difference. | |
489 | */ | |
490 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 491 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 492 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
493 | .m1 = { .min = 2, .max = 3 }, |
494 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 495 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 496 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
497 | }; |
498 | ||
1b6f4958 | 499 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
500 | /* |
501 | * These are the data rate limits (measured in fast clocks) | |
502 | * since those are the strictest limits we have. The fast | |
503 | * clock and actual rate limits are more relaxed, so checking | |
504 | * them would make no difference. | |
505 | */ | |
506 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 507 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
508 | .n = { .min = 1, .max = 1 }, |
509 | .m1 = { .min = 2, .max = 2 }, | |
510 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
511 | .p1 = { .min = 2, .max = 4 }, | |
512 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
513 | }; | |
514 | ||
1b6f4958 | 515 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
516 | /* FIXME: find real dot limits */ |
517 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 518 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
519 | .n = { .min = 1, .max = 1 }, |
520 | .m1 = { .min = 2, .max = 2 }, | |
521 | /* FIXME: find real m2 limits */ | |
522 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
523 | .p1 = { .min = 2, .max = 4 }, | |
524 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
525 | }; | |
526 | ||
cdba954e ACO |
527 | static bool |
528 | needs_modeset(struct drm_crtc_state *state) | |
529 | { | |
fc596660 | 530 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
531 | } |
532 | ||
dccbea3b ID |
533 | /* |
534 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
535 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
536 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
537 | * The helpers' return value is the rate of the clock that is fed to the | |
538 | * display engine's pipe which can be the above fast dot clock rate or a | |
539 | * divided-down version of it. | |
540 | */ | |
f2b115e6 | 541 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 542 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 543 | { |
2177832f SL |
544 | clock->m = clock->m2 + 2; |
545 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 546 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 547 | return 0; |
fb03ac01 VS |
548 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
549 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
550 | |
551 | return clock->dot; | |
2177832f SL |
552 | } |
553 | ||
7429e9d4 DV |
554 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
555 | { | |
556 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
557 | } | |
558 | ||
9e2c8475 | 559 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 560 | { |
7429e9d4 | 561 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 562 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 563 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 564 | return 0; |
fb03ac01 VS |
565 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
566 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
567 | |
568 | return clock->dot; | |
79e53945 JB |
569 | } |
570 | ||
9e2c8475 | 571 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
572 | { |
573 | clock->m = clock->m1 * clock->m2; | |
574 | clock->p = clock->p1 * clock->p2; | |
575 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 576 | return 0; |
589eca67 ID |
577 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
578 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
579 | |
580 | return clock->dot / 5; | |
589eca67 ID |
581 | } |
582 | ||
9e2c8475 | 583 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
584 | { |
585 | clock->m = clock->m1 * clock->m2; | |
586 | clock->p = clock->p1 * clock->p2; | |
587 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 588 | return 0; |
ef9348c8 CML |
589 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
590 | clock->n << 22); | |
591 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
592 | |
593 | return clock->dot / 5; | |
ef9348c8 CML |
594 | } |
595 | ||
7c04d1d9 | 596 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
597 | /** |
598 | * Returns whether the given set of divisors are valid for a given refclk with | |
599 | * the given connectors. | |
600 | */ | |
601 | ||
1b894b59 | 602 | static bool intel_PLL_is_valid(struct drm_device *dev, |
1b6f4958 | 603 | const struct intel_limit *limit, |
9e2c8475 | 604 | const struct dpll *clock) |
79e53945 | 605 | { |
f01b7962 VS |
606 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
607 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 608 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 609 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 610 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 611 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 612 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 613 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 614 | |
666a4537 WB |
615 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
616 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
617 | if (clock->m1 <= clock->m2) |
618 | INTELPllInvalid("m1 <= m2\n"); | |
619 | ||
666a4537 | 620 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
621 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
622 | INTELPllInvalid("p out of range\n"); | |
623 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
624 | INTELPllInvalid("m out of range\n"); | |
625 | } | |
626 | ||
79e53945 | 627 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 628 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
629 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
630 | * connector, etc., rather than just a single range. | |
631 | */ | |
632 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 633 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
634 | |
635 | return true; | |
636 | } | |
637 | ||
3b1429d9 | 638 | static int |
1b6f4958 | 639 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
640 | const struct intel_crtc_state *crtc_state, |
641 | int target) | |
79e53945 | 642 | { |
3b1429d9 | 643 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 644 | |
2d84d2b3 | 645 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 646 | /* |
a210b028 DV |
647 | * For LVDS just rely on its current settings for dual-channel. |
648 | * We haven't figured out how to reliably set up different | |
649 | * single/dual channel state, if we even can. | |
79e53945 | 650 | */ |
1974cad0 | 651 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 652 | return limit->p2.p2_fast; |
79e53945 | 653 | else |
3b1429d9 | 654 | return limit->p2.p2_slow; |
79e53945 JB |
655 | } else { |
656 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 657 | return limit->p2.p2_slow; |
79e53945 | 658 | else |
3b1429d9 | 659 | return limit->p2.p2_fast; |
79e53945 | 660 | } |
3b1429d9 VS |
661 | } |
662 | ||
70e8aa21 ACO |
663 | /* |
664 | * Returns a set of divisors for the desired target clock with the given | |
665 | * refclk, or FALSE. The returned values represent the clock equation: | |
666 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
667 | * | |
668 | * Target and reference clocks are specified in kHz. | |
669 | * | |
670 | * If match_clock is provided, then best_clock P divider must match the P | |
671 | * divider from @match_clock used for LVDS downclocking. | |
672 | */ | |
3b1429d9 | 673 | static bool |
1b6f4958 | 674 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 675 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
676 | int target, int refclk, struct dpll *match_clock, |
677 | struct dpll *best_clock) | |
3b1429d9 VS |
678 | { |
679 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 680 | struct dpll clock; |
3b1429d9 | 681 | int err = target; |
79e53945 | 682 | |
0206e353 | 683 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 684 | |
3b1429d9 VS |
685 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
686 | ||
42158660 ZY |
687 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
688 | clock.m1++) { | |
689 | for (clock.m2 = limit->m2.min; | |
690 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 691 | if (clock.m2 >= clock.m1) |
42158660 ZY |
692 | break; |
693 | for (clock.n = limit->n.min; | |
694 | clock.n <= limit->n.max; clock.n++) { | |
695 | for (clock.p1 = limit->p1.min; | |
696 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
697 | int this_err; |
698 | ||
dccbea3b | 699 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
700 | if (!intel_PLL_is_valid(dev, limit, |
701 | &clock)) | |
702 | continue; | |
703 | if (match_clock && | |
704 | clock.p != match_clock->p) | |
705 | continue; | |
706 | ||
707 | this_err = abs(clock.dot - target); | |
708 | if (this_err < err) { | |
709 | *best_clock = clock; | |
710 | err = this_err; | |
711 | } | |
712 | } | |
713 | } | |
714 | } | |
715 | } | |
716 | ||
717 | return (err != target); | |
718 | } | |
719 | ||
70e8aa21 ACO |
720 | /* |
721 | * Returns a set of divisors for the desired target clock with the given | |
722 | * refclk, or FALSE. The returned values represent the clock equation: | |
723 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
724 | * | |
725 | * Target and reference clocks are specified in kHz. | |
726 | * | |
727 | * If match_clock is provided, then best_clock P divider must match the P | |
728 | * divider from @match_clock used for LVDS downclocking. | |
729 | */ | |
ac58c3f0 | 730 | static bool |
1b6f4958 | 731 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 732 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
733 | int target, int refclk, struct dpll *match_clock, |
734 | struct dpll *best_clock) | |
79e53945 | 735 | { |
3b1429d9 | 736 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 737 | struct dpll clock; |
79e53945 JB |
738 | int err = target; |
739 | ||
0206e353 | 740 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 741 | |
3b1429d9 VS |
742 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
743 | ||
42158660 ZY |
744 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
745 | clock.m1++) { | |
746 | for (clock.m2 = limit->m2.min; | |
747 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
748 | for (clock.n = limit->n.min; |
749 | clock.n <= limit->n.max; clock.n++) { | |
750 | for (clock.p1 = limit->p1.min; | |
751 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
752 | int this_err; |
753 | ||
dccbea3b | 754 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
755 | if (!intel_PLL_is_valid(dev, limit, |
756 | &clock)) | |
79e53945 | 757 | continue; |
cec2f356 SP |
758 | if (match_clock && |
759 | clock.p != match_clock->p) | |
760 | continue; | |
79e53945 JB |
761 | |
762 | this_err = abs(clock.dot - target); | |
763 | if (this_err < err) { | |
764 | *best_clock = clock; | |
765 | err = this_err; | |
766 | } | |
767 | } | |
768 | } | |
769 | } | |
770 | } | |
771 | ||
772 | return (err != target); | |
773 | } | |
774 | ||
997c030c ACO |
775 | /* |
776 | * Returns a set of divisors for the desired target clock with the given | |
777 | * refclk, or FALSE. The returned values represent the clock equation: | |
778 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
779 | * |
780 | * Target and reference clocks are specified in kHz. | |
781 | * | |
782 | * If match_clock is provided, then best_clock P divider must match the P | |
783 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 784 | */ |
d4906093 | 785 | static bool |
1b6f4958 | 786 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 787 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
788 | int target, int refclk, struct dpll *match_clock, |
789 | struct dpll *best_clock) | |
d4906093 | 790 | { |
3b1429d9 | 791 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 792 | struct dpll clock; |
d4906093 | 793 | int max_n; |
3b1429d9 | 794 | bool found = false; |
6ba770dc AJ |
795 | /* approximately equals target * 0.00585 */ |
796 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
797 | |
798 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
799 | |
800 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
801 | ||
d4906093 | 802 | max_n = limit->n.max; |
f77f13e2 | 803 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 804 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 805 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
806 | for (clock.m1 = limit->m1.max; |
807 | clock.m1 >= limit->m1.min; clock.m1--) { | |
808 | for (clock.m2 = limit->m2.max; | |
809 | clock.m2 >= limit->m2.min; clock.m2--) { | |
810 | for (clock.p1 = limit->p1.max; | |
811 | clock.p1 >= limit->p1.min; clock.p1--) { | |
812 | int this_err; | |
813 | ||
dccbea3b | 814 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
815 | if (!intel_PLL_is_valid(dev, limit, |
816 | &clock)) | |
d4906093 | 817 | continue; |
1b894b59 CW |
818 | |
819 | this_err = abs(clock.dot - target); | |
d4906093 ML |
820 | if (this_err < err_most) { |
821 | *best_clock = clock; | |
822 | err_most = this_err; | |
823 | max_n = clock.n; | |
824 | found = true; | |
825 | } | |
826 | } | |
827 | } | |
828 | } | |
829 | } | |
2c07245f ZW |
830 | return found; |
831 | } | |
832 | ||
d5dd62bd ID |
833 | /* |
834 | * Check if the calculated PLL configuration is more optimal compared to the | |
835 | * best configuration and error found so far. Return the calculated error. | |
836 | */ | |
837 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
838 | const struct dpll *calculated_clock, |
839 | const struct dpll *best_clock, | |
d5dd62bd ID |
840 | unsigned int best_error_ppm, |
841 | unsigned int *error_ppm) | |
842 | { | |
9ca3ba01 ID |
843 | /* |
844 | * For CHV ignore the error and consider only the P value. | |
845 | * Prefer a bigger P value based on HW requirements. | |
846 | */ | |
847 | if (IS_CHERRYVIEW(dev)) { | |
848 | *error_ppm = 0; | |
849 | ||
850 | return calculated_clock->p > best_clock->p; | |
851 | } | |
852 | ||
24be4e46 ID |
853 | if (WARN_ON_ONCE(!target_freq)) |
854 | return false; | |
855 | ||
d5dd62bd ID |
856 | *error_ppm = div_u64(1000000ULL * |
857 | abs(target_freq - calculated_clock->dot), | |
858 | target_freq); | |
859 | /* | |
860 | * Prefer a better P value over a better (smaller) error if the error | |
861 | * is small. Ensure this preference for future configurations too by | |
862 | * setting the error to 0. | |
863 | */ | |
864 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
865 | *error_ppm = 0; | |
866 | ||
867 | return true; | |
868 | } | |
869 | ||
870 | return *error_ppm + 10 < best_error_ppm; | |
871 | } | |
872 | ||
65b3d6a9 ACO |
873 | /* |
874 | * Returns a set of divisors for the desired target clock with the given | |
875 | * refclk, or FALSE. The returned values represent the clock equation: | |
876 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
877 | */ | |
a0c4da24 | 878 | static bool |
1b6f4958 | 879 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 880 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
881 | int target, int refclk, struct dpll *match_clock, |
882 | struct dpll *best_clock) | |
a0c4da24 | 883 | { |
a93e255f | 884 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 885 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 886 | struct dpll clock; |
69e4f900 | 887 | unsigned int bestppm = 1000000; |
27e639bf VS |
888 | /* min update 19.2 MHz */ |
889 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 890 | bool found = false; |
a0c4da24 | 891 | |
6b4bf1c4 VS |
892 | target *= 5; /* fast clock */ |
893 | ||
894 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
895 | |
896 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 897 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 898 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 899 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 900 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 901 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 902 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 903 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 904 | unsigned int ppm; |
69e4f900 | 905 | |
6b4bf1c4 VS |
906 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
907 | refclk * clock.m1); | |
908 | ||
dccbea3b | 909 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 910 | |
f01b7962 VS |
911 | if (!intel_PLL_is_valid(dev, limit, |
912 | &clock)) | |
43b0ac53 VS |
913 | continue; |
914 | ||
d5dd62bd ID |
915 | if (!vlv_PLL_is_optimal(dev, target, |
916 | &clock, | |
917 | best_clock, | |
918 | bestppm, &ppm)) | |
919 | continue; | |
6b4bf1c4 | 920 | |
d5dd62bd ID |
921 | *best_clock = clock; |
922 | bestppm = ppm; | |
923 | found = true; | |
a0c4da24 JB |
924 | } |
925 | } | |
926 | } | |
927 | } | |
a0c4da24 | 928 | |
49e497ef | 929 | return found; |
a0c4da24 | 930 | } |
a4fc5ed6 | 931 | |
65b3d6a9 ACO |
932 | /* |
933 | * Returns a set of divisors for the desired target clock with the given | |
934 | * refclk, or FALSE. The returned values represent the clock equation: | |
935 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
936 | */ | |
ef9348c8 | 937 | static bool |
1b6f4958 | 938 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 939 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
940 | int target, int refclk, struct dpll *match_clock, |
941 | struct dpll *best_clock) | |
ef9348c8 | 942 | { |
a93e255f | 943 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 944 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 945 | unsigned int best_error_ppm; |
9e2c8475 | 946 | struct dpll clock; |
ef9348c8 CML |
947 | uint64_t m2; |
948 | int found = false; | |
949 | ||
950 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 951 | best_error_ppm = 1000000; |
ef9348c8 CML |
952 | |
953 | /* | |
954 | * Based on hardware doc, the n always set to 1, and m1 always | |
955 | * set to 2. If requires to support 200Mhz refclk, we need to | |
956 | * revisit this because n may not 1 anymore. | |
957 | */ | |
958 | clock.n = 1, clock.m1 = 2; | |
959 | target *= 5; /* fast clock */ | |
960 | ||
961 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
962 | for (clock.p2 = limit->p2.p2_fast; | |
963 | clock.p2 >= limit->p2.p2_slow; | |
964 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 965 | unsigned int error_ppm; |
ef9348c8 CML |
966 | |
967 | clock.p = clock.p1 * clock.p2; | |
968 | ||
969 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
970 | clock.n) << 22, refclk * clock.m1); | |
971 | ||
972 | if (m2 > INT_MAX/clock.m1) | |
973 | continue; | |
974 | ||
975 | clock.m2 = m2; | |
976 | ||
dccbea3b | 977 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
978 | |
979 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
980 | continue; | |
981 | ||
9ca3ba01 ID |
982 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
983 | best_error_ppm, &error_ppm)) | |
984 | continue; | |
985 | ||
986 | *best_clock = clock; | |
987 | best_error_ppm = error_ppm; | |
988 | found = true; | |
ef9348c8 CML |
989 | } |
990 | } | |
991 | ||
992 | return found; | |
993 | } | |
994 | ||
5ab7b0b7 | 995 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 996 | struct dpll *best_clock) |
5ab7b0b7 | 997 | { |
65b3d6a9 | 998 | int refclk = 100000; |
1b6f4958 | 999 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1000 | |
65b3d6a9 | 1001 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
1002 | target_clock, refclk, NULL, best_clock); |
1003 | } | |
1004 | ||
20ddf665 VS |
1005 | bool intel_crtc_active(struct drm_crtc *crtc) |
1006 | { | |
1007 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1008 | ||
1009 | /* Be paranoid as we can arrive here with only partial | |
1010 | * state retrieved from the hardware during setup. | |
1011 | * | |
241bfc38 | 1012 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1013 | * as Haswell has gained clock readout/fastboot support. |
1014 | * | |
66e514c1 | 1015 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1016 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1017 | * |
1018 | * FIXME: The intel_crtc->active here should be switched to | |
1019 | * crtc->state->active once we have proper CRTC states wired up | |
1020 | * for atomic. | |
20ddf665 | 1021 | */ |
c3d1f436 | 1022 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1023 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1024 | } |
1025 | ||
a5c961d1 PZ |
1026 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1027 | enum pipe pipe) | |
1028 | { | |
1029 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1030 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1031 | ||
6e3c9717 | 1032 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1033 | } |
1034 | ||
fbf49ea2 VS |
1035 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1036 | { | |
fac5e23e | 1037 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1038 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1039 | u32 line1, line2; |
1040 | u32 line_mask; | |
1041 | ||
1042 | if (IS_GEN2(dev)) | |
1043 | line_mask = DSL_LINEMASK_GEN2; | |
1044 | else | |
1045 | line_mask = DSL_LINEMASK_GEN3; | |
1046 | ||
1047 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1048 | msleep(5); |
fbf49ea2 VS |
1049 | line2 = I915_READ(reg) & line_mask; |
1050 | ||
1051 | return line1 == line2; | |
1052 | } | |
1053 | ||
ab7ad7f6 KP |
1054 | /* |
1055 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1056 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1057 | * |
1058 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1059 | * spinning on the vblank interrupt status bit, since we won't actually | |
1060 | * see an interrupt when the pipe is disabled. | |
1061 | * | |
ab7ad7f6 KP |
1062 | * On Gen4 and above: |
1063 | * wait for the pipe register state bit to turn off | |
1064 | * | |
1065 | * Otherwise: | |
1066 | * wait for the display line value to settle (it usually | |
1067 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1068 | * |
9d0498a2 | 1069 | */ |
575f7ab7 | 1070 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1071 | { |
575f7ab7 | 1072 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1073 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 1074 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1075 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1076 | |
1077 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1078 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1079 | |
1080 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1081 | if (intel_wait_for_register(dev_priv, |
1082 | reg, I965_PIPECONF_ACTIVE, 0, | |
1083 | 100)) | |
284637d9 | 1084 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1085 | } else { |
ab7ad7f6 | 1086 | /* Wait for the display line to settle */ |
fbf49ea2 | 1087 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1088 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1089 | } |
79e53945 JB |
1090 | } |
1091 | ||
b24e7179 | 1092 | /* Only for pre-ILK configs */ |
55607e8a DV |
1093 | void assert_pll(struct drm_i915_private *dev_priv, |
1094 | enum pipe pipe, bool state) | |
b24e7179 | 1095 | { |
b24e7179 JB |
1096 | u32 val; |
1097 | bool cur_state; | |
1098 | ||
649636ef | 1099 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1100 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1101 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1102 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1103 | onoff(state), onoff(cur_state)); |
b24e7179 | 1104 | } |
b24e7179 | 1105 | |
23538ef1 | 1106 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1107 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1108 | { |
1109 | u32 val; | |
1110 | bool cur_state; | |
1111 | ||
a580516d | 1112 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1113 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1114 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1115 | |
1116 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1117 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1118 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1119 | onoff(state), onoff(cur_state)); |
23538ef1 | 1120 | } |
23538ef1 | 1121 | |
040484af JB |
1122 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1123 | enum pipe pipe, bool state) | |
1124 | { | |
040484af | 1125 | bool cur_state; |
ad80a810 PZ |
1126 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1127 | pipe); | |
040484af | 1128 | |
2d1fe073 | 1129 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1130 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1131 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1132 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1133 | } else { |
649636ef | 1134 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1135 | cur_state = !!(val & FDI_TX_ENABLE); |
1136 | } | |
e2c719b7 | 1137 | I915_STATE_WARN(cur_state != state, |
040484af | 1138 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1139 | onoff(state), onoff(cur_state)); |
040484af JB |
1140 | } |
1141 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1142 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1143 | ||
1144 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1145 | enum pipe pipe, bool state) | |
1146 | { | |
040484af JB |
1147 | u32 val; |
1148 | bool cur_state; | |
1149 | ||
649636ef | 1150 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1151 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1152 | I915_STATE_WARN(cur_state != state, |
040484af | 1153 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1154 | onoff(state), onoff(cur_state)); |
040484af JB |
1155 | } |
1156 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1157 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1158 | ||
1159 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1160 | enum pipe pipe) | |
1161 | { | |
040484af JB |
1162 | u32 val; |
1163 | ||
1164 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1165 | if (IS_GEN5(dev_priv)) |
040484af JB |
1166 | return; |
1167 | ||
bf507ef7 | 1168 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1169 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1170 | return; |
1171 | ||
649636ef | 1172 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1173 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1174 | } |
1175 | ||
55607e8a DV |
1176 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1177 | enum pipe pipe, bool state) | |
040484af | 1178 | { |
040484af | 1179 | u32 val; |
55607e8a | 1180 | bool cur_state; |
040484af | 1181 | |
649636ef | 1182 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1183 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1184 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1185 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1186 | onoff(state), onoff(cur_state)); |
040484af JB |
1187 | } |
1188 | ||
b680c37a DV |
1189 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1190 | enum pipe pipe) | |
ea0760cf | 1191 | { |
91c8a326 | 1192 | struct drm_device *dev = &dev_priv->drm; |
f0f59a00 | 1193 | i915_reg_t pp_reg; |
ea0760cf JB |
1194 | u32 val; |
1195 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1196 | bool locked = true; |
ea0760cf | 1197 | |
bedd4dba JN |
1198 | if (WARN_ON(HAS_DDI(dev))) |
1199 | return; | |
1200 | ||
1201 | if (HAS_PCH_SPLIT(dev)) { | |
1202 | u32 port_sel; | |
1203 | ||
ea0760cf | 1204 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1205 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1206 | ||
1207 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1208 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1209 | panel_pipe = PIPE_B; | |
1210 | /* XXX: else fix for eDP */ | |
666a4537 | 1211 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1212 | /* presumably write lock depends on pipe, not port select */ |
1213 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1214 | panel_pipe = pipe; | |
ea0760cf JB |
1215 | } else { |
1216 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1217 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1218 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1219 | } |
1220 | ||
1221 | val = I915_READ(pp_reg); | |
1222 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1223 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1224 | locked = false; |
1225 | ||
e2c719b7 | 1226 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1227 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1228 | pipe_name(pipe)); |
ea0760cf JB |
1229 | } |
1230 | ||
93ce0ba6 JN |
1231 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1232 | enum pipe pipe, bool state) | |
1233 | { | |
91c8a326 | 1234 | struct drm_device *dev = &dev_priv->drm; |
93ce0ba6 JN |
1235 | bool cur_state; |
1236 | ||
d9d82081 | 1237 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1238 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1239 | else |
5efb3e28 | 1240 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1241 | |
e2c719b7 | 1242 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1243 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1244 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1245 | } |
1246 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1247 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1248 | ||
b840d907 JB |
1249 | void assert_pipe(struct drm_i915_private *dev_priv, |
1250 | enum pipe pipe, bool state) | |
b24e7179 | 1251 | { |
63d7bbe9 | 1252 | bool cur_state; |
702e7a56 PZ |
1253 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1254 | pipe); | |
4feed0eb | 1255 | enum intel_display_power_domain power_domain; |
b24e7179 | 1256 | |
b6b5d049 VS |
1257 | /* if we need the pipe quirk it must be always on */ |
1258 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1259 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1260 | state = true; |
1261 | ||
4feed0eb ID |
1262 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1263 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1264 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1265 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1266 | |
1267 | intel_display_power_put(dev_priv, power_domain); | |
1268 | } else { | |
1269 | cur_state = false; | |
69310161 PZ |
1270 | } |
1271 | ||
e2c719b7 | 1272 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1273 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1274 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1275 | } |
1276 | ||
931872fc CW |
1277 | static void assert_plane(struct drm_i915_private *dev_priv, |
1278 | enum plane plane, bool state) | |
b24e7179 | 1279 | { |
b24e7179 | 1280 | u32 val; |
931872fc | 1281 | bool cur_state; |
b24e7179 | 1282 | |
649636ef | 1283 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1284 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1285 | I915_STATE_WARN(cur_state != state, |
931872fc | 1286 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1287 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1288 | } |
1289 | ||
931872fc CW |
1290 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1291 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1292 | ||
b24e7179 JB |
1293 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1294 | enum pipe pipe) | |
1295 | { | |
91c8a326 | 1296 | struct drm_device *dev = &dev_priv->drm; |
649636ef | 1297 | int i; |
b24e7179 | 1298 | |
653e1026 VS |
1299 | /* Primary planes are fixed to pipes on gen4+ */ |
1300 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1301 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1302 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1303 | "plane %c assertion failure, should be disabled but not\n", |
1304 | plane_name(pipe)); | |
19ec1358 | 1305 | return; |
28c05794 | 1306 | } |
19ec1358 | 1307 | |
b24e7179 | 1308 | /* Need to check both planes against the pipe */ |
055e393f | 1309 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1310 | u32 val = I915_READ(DSPCNTR(i)); |
1311 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1312 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1313 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1314 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1315 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1316 | } |
1317 | } | |
1318 | ||
19332d7a JB |
1319 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1320 | enum pipe pipe) | |
1321 | { | |
91c8a326 | 1322 | struct drm_device *dev = &dev_priv->drm; |
649636ef | 1323 | int sprite; |
19332d7a | 1324 | |
7feb8b88 | 1325 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1326 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1327 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1328 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1329 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1330 | sprite, pipe_name(pipe)); | |
1331 | } | |
666a4537 | 1332 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1333 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1334 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1335 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1336 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1337 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1338 | } |
1339 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1340 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1341 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1342 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1343 | plane_name(pipe), pipe_name(pipe)); |
1344 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1345 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1346 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1347 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1348 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1349 | } |
1350 | } | |
1351 | ||
08c71e5e VS |
1352 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1353 | { | |
e2c719b7 | 1354 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1355 | drm_crtc_vblank_put(crtc); |
1356 | } | |
1357 | ||
7abd4b35 ACO |
1358 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1359 | enum pipe pipe) | |
92f2584a | 1360 | { |
92f2584a JB |
1361 | u32 val; |
1362 | bool enabled; | |
1363 | ||
649636ef | 1364 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1365 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1366 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1367 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1368 | pipe_name(pipe)); | |
92f2584a JB |
1369 | } |
1370 | ||
4e634389 KP |
1371 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1372 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1373 | { |
1374 | if ((val & DP_PORT_EN) == 0) | |
1375 | return false; | |
1376 | ||
2d1fe073 | 1377 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1378 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1379 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1380 | return false; | |
2d1fe073 | 1381 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1382 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1383 | return false; | |
f0575e92 KP |
1384 | } else { |
1385 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1386 | return false; | |
1387 | } | |
1388 | return true; | |
1389 | } | |
1390 | ||
1519b995 KP |
1391 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1392 | enum pipe pipe, u32 val) | |
1393 | { | |
dc0fa718 | 1394 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1395 | return false; |
1396 | ||
2d1fe073 | 1397 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1398 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1399 | return false; |
2d1fe073 | 1400 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1401 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1402 | return false; | |
1519b995 | 1403 | } else { |
dc0fa718 | 1404 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1405 | return false; |
1406 | } | |
1407 | return true; | |
1408 | } | |
1409 | ||
1410 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1411 | enum pipe pipe, u32 val) | |
1412 | { | |
1413 | if ((val & LVDS_PORT_EN) == 0) | |
1414 | return false; | |
1415 | ||
2d1fe073 | 1416 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1417 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1418 | return false; | |
1419 | } else { | |
1420 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1421 | return false; | |
1422 | } | |
1423 | return true; | |
1424 | } | |
1425 | ||
1426 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1427 | enum pipe pipe, u32 val) | |
1428 | { | |
1429 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1430 | return false; | |
2d1fe073 | 1431 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1432 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1433 | return false; | |
1434 | } else { | |
1435 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1436 | return false; | |
1437 | } | |
1438 | return true; | |
1439 | } | |
1440 | ||
291906f1 | 1441 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1442 | enum pipe pipe, i915_reg_t reg, |
1443 | u32 port_sel) | |
291906f1 | 1444 | { |
47a05eca | 1445 | u32 val = I915_READ(reg); |
e2c719b7 | 1446 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1447 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1448 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1449 | |
2d1fe073 | 1450 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1451 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1452 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1453 | } |
1454 | ||
1455 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1456 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1457 | { |
47a05eca | 1458 | u32 val = I915_READ(reg); |
e2c719b7 | 1459 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1460 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1461 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1462 | |
2d1fe073 | 1463 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1464 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1465 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1466 | } |
1467 | ||
1468 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1469 | enum pipe pipe) | |
1470 | { | |
291906f1 | 1471 | u32 val; |
291906f1 | 1472 | |
f0575e92 KP |
1473 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1474 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1475 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1476 | |
649636ef | 1477 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1478 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1479 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1480 | pipe_name(pipe)); |
291906f1 | 1481 | |
649636ef | 1482 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1483 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1484 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1485 | pipe_name(pipe)); |
291906f1 | 1486 | |
e2debe91 PZ |
1487 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1488 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1489 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1490 | } |
1491 | ||
cd2d34d9 VS |
1492 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1493 | const struct intel_crtc_state *pipe_config) | |
1494 | { | |
1495 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1496 | enum pipe pipe = crtc->pipe; | |
1497 | ||
1498 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1499 | POSTING_READ(DPLL(pipe)); | |
1500 | udelay(150); | |
1501 | ||
2c30b43b CW |
1502 | if (intel_wait_for_register(dev_priv, |
1503 | DPLL(pipe), | |
1504 | DPLL_LOCK_VLV, | |
1505 | DPLL_LOCK_VLV, | |
1506 | 1)) | |
cd2d34d9 VS |
1507 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1508 | } | |
1509 | ||
d288f65f | 1510 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1511 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1512 | { |
cd2d34d9 | 1513 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1514 | enum pipe pipe = crtc->pipe; |
87442f73 | 1515 | |
8bd3f301 | 1516 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1517 | |
87442f73 | 1518 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1519 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1520 | |
cd2d34d9 VS |
1521 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1522 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1523 | |
8bd3f301 VS |
1524 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1525 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1526 | } |
1527 | ||
cd2d34d9 VS |
1528 | |
1529 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1530 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1531 | { |
cd2d34d9 | 1532 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1533 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1534 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1535 | u32 tmp; |
1536 | ||
a580516d | 1537 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1538 | |
1539 | /* Enable back the 10bit clock to display controller */ | |
1540 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1541 | tmp |= DPIO_DCLKP_EN; | |
1542 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1543 | ||
54433e91 VS |
1544 | mutex_unlock(&dev_priv->sb_lock); |
1545 | ||
9d556c99 CML |
1546 | /* |
1547 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1548 | */ | |
1549 | udelay(1); | |
1550 | ||
1551 | /* Enable PLL */ | |
d288f65f | 1552 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1553 | |
1554 | /* Check PLL is locked */ | |
6b18826a CW |
1555 | if (intel_wait_for_register(dev_priv, |
1556 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1557 | 1)) | |
9d556c99 | 1558 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1559 | } |
1560 | ||
1561 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1562 | const struct intel_crtc_state *pipe_config) | |
1563 | { | |
1564 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1565 | enum pipe pipe = crtc->pipe; | |
1566 | ||
1567 | assert_pipe_disabled(dev_priv, pipe); | |
1568 | ||
1569 | /* PLL is protected by panel, make sure we can write it */ | |
1570 | assert_panel_unlocked(dev_priv, pipe); | |
1571 | ||
1572 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1573 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1574 | |
c231775c VS |
1575 | if (pipe != PIPE_A) { |
1576 | /* | |
1577 | * WaPixelRepeatModeFixForC0:chv | |
1578 | * | |
1579 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1580 | * the value from DPLLBMD to either pipe B or C. | |
1581 | */ | |
1582 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1583 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1584 | I915_WRITE(CBR4_VLV, 0); | |
1585 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1586 | ||
1587 | /* | |
1588 | * DPLLB VGA mode also seems to cause problems. | |
1589 | * We should always have it disabled. | |
1590 | */ | |
1591 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1592 | } else { | |
1593 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1594 | POSTING_READ(DPLL_MD(pipe)); | |
1595 | } | |
9d556c99 CML |
1596 | } |
1597 | ||
1c4e0274 VS |
1598 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1599 | { | |
1600 | struct intel_crtc *crtc; | |
1601 | int count = 0; | |
1602 | ||
2d84d2b3 | 1603 | for_each_intel_crtc(dev, crtc) { |
3538b9df | 1604 | count += crtc->base.state->active && |
2d84d2b3 VS |
1605 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1606 | } | |
1c4e0274 VS |
1607 | |
1608 | return count; | |
1609 | } | |
1610 | ||
66e3d5c0 | 1611 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1612 | { |
66e3d5c0 | 1613 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1614 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1615 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1616 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1617 | |
66e3d5c0 | 1618 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1619 | |
63d7bbe9 | 1620 | /* PLL is protected by panel, make sure we can write it */ |
66e3d5c0 DV |
1621 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1622 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1623 | |
1c4e0274 VS |
1624 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1625 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1626 | /* | |
1627 | * It appears to be important that we don't enable this | |
1628 | * for the current pipe before otherwise configuring the | |
1629 | * PLL. No idea how this should be handled if multiple | |
1630 | * DVO outputs are enabled simultaneosly. | |
1631 | */ | |
1632 | dpll |= DPLL_DVO_2X_MODE; | |
1633 | I915_WRITE(DPLL(!crtc->pipe), | |
1634 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1635 | } | |
66e3d5c0 | 1636 | |
c2b63374 VS |
1637 | /* |
1638 | * Apparently we need to have VGA mode enabled prior to changing | |
1639 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1640 | * dividers, even though the register value does change. | |
1641 | */ | |
1642 | I915_WRITE(reg, 0); | |
1643 | ||
8e7a65aa VS |
1644 | I915_WRITE(reg, dpll); |
1645 | ||
66e3d5c0 DV |
1646 | /* Wait for the clocks to stabilize. */ |
1647 | POSTING_READ(reg); | |
1648 | udelay(150); | |
1649 | ||
1650 | if (INTEL_INFO(dev)->gen >= 4) { | |
1651 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1652 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1653 | } else { |
1654 | /* The pixel multiplier can only be updated once the | |
1655 | * DPLL is enabled and the clocks are stable. | |
1656 | * | |
1657 | * So write it again. | |
1658 | */ | |
1659 | I915_WRITE(reg, dpll); | |
1660 | } | |
63d7bbe9 JB |
1661 | |
1662 | /* We do this three times for luck */ | |
66e3d5c0 | 1663 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1664 | POSTING_READ(reg); |
1665 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1666 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1667 | POSTING_READ(reg); |
1668 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1669 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1670 | POSTING_READ(reg); |
1671 | udelay(150); /* wait for warmup */ | |
1672 | } | |
1673 | ||
1674 | /** | |
50b44a44 | 1675 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1676 | * @dev_priv: i915 private structure |
1677 | * @pipe: pipe PLL to disable | |
1678 | * | |
1679 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1680 | * | |
1681 | * Note! This is for pre-ILK only. | |
1682 | */ | |
1c4e0274 | 1683 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1684 | { |
1c4e0274 | 1685 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1686 | struct drm_i915_private *dev_priv = to_i915(dev); |
1c4e0274 VS |
1687 | enum pipe pipe = crtc->pipe; |
1688 | ||
1689 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1690 | if (IS_I830(dev) && | |
2d84d2b3 | 1691 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
3538b9df | 1692 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1693 | I915_WRITE(DPLL(PIPE_B), |
1694 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1695 | I915_WRITE(DPLL(PIPE_A), | |
1696 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1697 | } | |
1698 | ||
b6b5d049 VS |
1699 | /* Don't disable pipe or pipe PLLs if needed */ |
1700 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1701 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1702 | return; |
1703 | ||
1704 | /* Make sure the pipe isn't still relying on us */ | |
1705 | assert_pipe_disabled(dev_priv, pipe); | |
1706 | ||
b8afb911 | 1707 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1708 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1709 | } |
1710 | ||
f6071166 JB |
1711 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1712 | { | |
b8afb911 | 1713 | u32 val; |
f6071166 JB |
1714 | |
1715 | /* Make sure the pipe isn't still relying on us */ | |
1716 | assert_pipe_disabled(dev_priv, pipe); | |
1717 | ||
03ed5cbf VS |
1718 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1719 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1720 | if (pipe != PIPE_A) | |
1721 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1722 | ||
f6071166 JB |
1723 | I915_WRITE(DPLL(pipe), val); |
1724 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1725 | } |
1726 | ||
1727 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1728 | { | |
d752048d | 1729 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1730 | u32 val; |
1731 | ||
a11b0703 VS |
1732 | /* Make sure the pipe isn't still relying on us */ |
1733 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1734 | |
60bfe44f VS |
1735 | val = DPLL_SSC_REF_CLK_CHV | |
1736 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1737 | if (pipe != PIPE_A) |
1738 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1739 | |
a11b0703 VS |
1740 | I915_WRITE(DPLL(pipe), val); |
1741 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1742 | |
a580516d | 1743 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1744 | |
1745 | /* Disable 10bit clock to display controller */ | |
1746 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1747 | val &= ~DPIO_DCLKP_EN; | |
1748 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1749 | ||
a580516d | 1750 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1751 | } |
1752 | ||
e4607fcf | 1753 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1754 | struct intel_digital_port *dport, |
1755 | unsigned int expected_mask) | |
89b667f8 JB |
1756 | { |
1757 | u32 port_mask; | |
f0f59a00 | 1758 | i915_reg_t dpll_reg; |
89b667f8 | 1759 | |
e4607fcf CML |
1760 | switch (dport->port) { |
1761 | case PORT_B: | |
89b667f8 | 1762 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1763 | dpll_reg = DPLL(0); |
e4607fcf CML |
1764 | break; |
1765 | case PORT_C: | |
89b667f8 | 1766 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1767 | dpll_reg = DPLL(0); |
9b6de0a1 | 1768 | expected_mask <<= 4; |
00fc31b7 CML |
1769 | break; |
1770 | case PORT_D: | |
1771 | port_mask = DPLL_PORTD_READY_MASK; | |
1772 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1773 | break; |
1774 | default: | |
1775 | BUG(); | |
1776 | } | |
89b667f8 | 1777 | |
370004d3 CW |
1778 | if (intel_wait_for_register(dev_priv, |
1779 | dpll_reg, port_mask, expected_mask, | |
1780 | 1000)) | |
9b6de0a1 VS |
1781 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1782 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1783 | } |
1784 | ||
b8a4f404 PZ |
1785 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1786 | enum pipe pipe) | |
040484af | 1787 | { |
91c8a326 | 1788 | struct drm_device *dev = &dev_priv->drm; |
7c26e5c6 | 1789 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1790 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1791 | i915_reg_t reg; |
1792 | uint32_t val, pipeconf_val; | |
040484af | 1793 | |
040484af | 1794 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1795 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1796 | |
1797 | /* FDI must be feeding us bits for PCH ports */ | |
1798 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1799 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1800 | ||
23670b32 DV |
1801 | if (HAS_PCH_CPT(dev)) { |
1802 | /* Workaround: Set the timing override bit before enabling the | |
1803 | * pch transcoder. */ | |
1804 | reg = TRANS_CHICKEN2(pipe); | |
1805 | val = I915_READ(reg); | |
1806 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1807 | I915_WRITE(reg, val); | |
59c859d6 | 1808 | } |
23670b32 | 1809 | |
ab9412ba | 1810 | reg = PCH_TRANSCONF(pipe); |
040484af | 1811 | val = I915_READ(reg); |
5f7f726d | 1812 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1813 | |
2d1fe073 | 1814 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1815 | /* |
c5de7c6f VS |
1816 | * Make the BPC in transcoder be consistent with |
1817 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1818 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1819 | */ |
dfd07d72 | 1820 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1821 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1822 | val |= PIPECONF_8BPC; |
1823 | else | |
1824 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1825 | } |
5f7f726d PZ |
1826 | |
1827 | val &= ~TRANS_INTERLACE_MASK; | |
1828 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1829 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1830 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1831 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1832 | else | |
1833 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1834 | else |
1835 | val |= TRANS_PROGRESSIVE; | |
1836 | ||
040484af | 1837 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1838 | if (intel_wait_for_register(dev_priv, |
1839 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1840 | 100)) | |
4bb6f1f3 | 1841 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1842 | } |
1843 | ||
8fb033d7 | 1844 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1845 | enum transcoder cpu_transcoder) |
040484af | 1846 | { |
8fb033d7 | 1847 | u32 val, pipeconf_val; |
8fb033d7 | 1848 | |
8fb033d7 | 1849 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1850 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1851 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1852 | |
223a6fdf | 1853 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1854 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1855 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1856 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1857 | |
25f3ef11 | 1858 | val = TRANS_ENABLE; |
937bb610 | 1859 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1860 | |
9a76b1c6 PZ |
1861 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1862 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1863 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1864 | else |
1865 | val |= TRANS_PROGRESSIVE; | |
1866 | ||
ab9412ba | 1867 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1868 | if (intel_wait_for_register(dev_priv, |
1869 | LPT_TRANSCONF, | |
1870 | TRANS_STATE_ENABLE, | |
1871 | TRANS_STATE_ENABLE, | |
1872 | 100)) | |
937bb610 | 1873 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1874 | } |
1875 | ||
b8a4f404 PZ |
1876 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1877 | enum pipe pipe) | |
040484af | 1878 | { |
91c8a326 | 1879 | struct drm_device *dev = &dev_priv->drm; |
f0f59a00 VS |
1880 | i915_reg_t reg; |
1881 | uint32_t val; | |
040484af JB |
1882 | |
1883 | /* FDI relies on the transcoder */ | |
1884 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1885 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1886 | ||
291906f1 JB |
1887 | /* Ports must be off as well */ |
1888 | assert_pch_ports_disabled(dev_priv, pipe); | |
1889 | ||
ab9412ba | 1890 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1891 | val = I915_READ(reg); |
1892 | val &= ~TRANS_ENABLE; | |
1893 | I915_WRITE(reg, val); | |
1894 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1895 | if (intel_wait_for_register(dev_priv, |
1896 | reg, TRANS_STATE_ENABLE, 0, | |
1897 | 50)) | |
4bb6f1f3 | 1898 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1899 | |
c465613b | 1900 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
1901 | /* Workaround: Clear the timing override chicken bit again. */ |
1902 | reg = TRANS_CHICKEN2(pipe); | |
1903 | val = I915_READ(reg); | |
1904 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1905 | I915_WRITE(reg, val); | |
1906 | } | |
040484af JB |
1907 | } |
1908 | ||
ab4d966c | 1909 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1910 | { |
8fb033d7 PZ |
1911 | u32 val; |
1912 | ||
ab9412ba | 1913 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1914 | val &= ~TRANS_ENABLE; |
ab9412ba | 1915 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1916 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1917 | if (intel_wait_for_register(dev_priv, |
1918 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1919 | 50)) | |
8a52fd9f | 1920 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1921 | |
1922 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1923 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1924 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1925 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1926 | } |
1927 | ||
b24e7179 | 1928 | /** |
309cfea8 | 1929 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1930 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1931 | * |
0372264a | 1932 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1933 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1934 | */ |
e1fdc473 | 1935 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1936 | { |
0372264a | 1937 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1938 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1939 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1940 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 1941 | enum pipe pch_transcoder; |
f0f59a00 | 1942 | i915_reg_t reg; |
b24e7179 JB |
1943 | u32 val; |
1944 | ||
9e2ee2dd VS |
1945 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1946 | ||
58c6eaa2 | 1947 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1948 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1949 | assert_sprites_disabled(dev_priv, pipe); |
1950 | ||
2d1fe073 | 1951 | if (HAS_PCH_LPT(dev_priv)) |
cc391bbb PZ |
1952 | pch_transcoder = TRANSCODER_A; |
1953 | else | |
1954 | pch_transcoder = pipe; | |
1955 | ||
b24e7179 JB |
1956 | /* |
1957 | * A pipe without a PLL won't actually be able to drive bits from | |
1958 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1959 | * need the check. | |
1960 | */ | |
2d1fe073 | 1961 | if (HAS_GMCH_DISPLAY(dev_priv)) |
d7edc4e5 | 1962 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1963 | assert_dsi_pll_enabled(dev_priv); |
1964 | else | |
1965 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 1966 | else { |
6e3c9717 | 1967 | if (crtc->config->has_pch_encoder) { |
040484af | 1968 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 1969 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1970 | assert_fdi_tx_pll_enabled(dev_priv, |
1971 | (enum pipe) cpu_transcoder); | |
040484af JB |
1972 | } |
1973 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1974 | } | |
b24e7179 | 1975 | |
702e7a56 | 1976 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1977 | val = I915_READ(reg); |
7ad25d48 | 1978 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1979 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1980 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1981 | return; |
7ad25d48 | 1982 | } |
00d70b15 CW |
1983 | |
1984 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1985 | POSTING_READ(reg); |
b7792d8b VS |
1986 | |
1987 | /* | |
1988 | * Until the pipe starts DSL will read as 0, which would cause | |
1989 | * an apparent vblank timestamp jump, which messes up also the | |
1990 | * frame count when it's derived from the timestamps. So let's | |
1991 | * wait for the pipe to start properly before we call | |
1992 | * drm_crtc_vblank_on() | |
1993 | */ | |
1994 | if (dev->max_vblank_count == 0 && | |
1995 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1996 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1997 | } |
1998 | ||
1999 | /** | |
309cfea8 | 2000 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2001 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2002 | * |
575f7ab7 VS |
2003 | * Disable the pipe of @crtc, making sure that various hardware |
2004 | * specific requirements are met, if applicable, e.g. plane | |
2005 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2006 | * |
2007 | * Will wait until the pipe has shut down before returning. | |
2008 | */ | |
575f7ab7 | 2009 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2010 | { |
fac5e23e | 2011 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 2012 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2013 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2014 | i915_reg_t reg; |
b24e7179 JB |
2015 | u32 val; |
2016 | ||
9e2ee2dd VS |
2017 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2018 | ||
b24e7179 JB |
2019 | /* |
2020 | * Make sure planes won't keep trying to pump pixels to us, | |
2021 | * or we might hang the display. | |
2022 | */ | |
2023 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2024 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2025 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2026 | |
702e7a56 | 2027 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2028 | val = I915_READ(reg); |
00d70b15 CW |
2029 | if ((val & PIPECONF_ENABLE) == 0) |
2030 | return; | |
2031 | ||
67adc644 VS |
2032 | /* |
2033 | * Double wide has implications for planes | |
2034 | * so best keep it disabled when not needed. | |
2035 | */ | |
6e3c9717 | 2036 | if (crtc->config->double_wide) |
67adc644 VS |
2037 | val &= ~PIPECONF_DOUBLE_WIDE; |
2038 | ||
2039 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2040 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2041 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2042 | val &= ~PIPECONF_ENABLE; |
2043 | ||
2044 | I915_WRITE(reg, val); | |
2045 | if ((val & PIPECONF_ENABLE) == 0) | |
2046 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2047 | } |
2048 | ||
832be82f VS |
2049 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2050 | { | |
2051 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2052 | } | |
2053 | ||
27ba3910 VS |
2054 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2055 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2056 | { |
2057 | switch (fb_modifier) { | |
2058 | case DRM_FORMAT_MOD_NONE: | |
2059 | return cpp; | |
2060 | case I915_FORMAT_MOD_X_TILED: | |
2061 | if (IS_GEN2(dev_priv)) | |
2062 | return 128; | |
2063 | else | |
2064 | return 512; | |
2065 | case I915_FORMAT_MOD_Y_TILED: | |
2066 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2067 | return 128; | |
2068 | else | |
2069 | return 512; | |
2070 | case I915_FORMAT_MOD_Yf_TILED: | |
2071 | switch (cpp) { | |
2072 | case 1: | |
2073 | return 64; | |
2074 | case 2: | |
2075 | case 4: | |
2076 | return 128; | |
2077 | case 8: | |
2078 | case 16: | |
2079 | return 256; | |
2080 | default: | |
2081 | MISSING_CASE(cpp); | |
2082 | return cpp; | |
2083 | } | |
2084 | break; | |
2085 | default: | |
2086 | MISSING_CASE(fb_modifier); | |
2087 | return cpp; | |
2088 | } | |
2089 | } | |
2090 | ||
832be82f VS |
2091 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2092 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2093 | { |
832be82f VS |
2094 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2095 | return 1; | |
2096 | else | |
2097 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2098 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2099 | } |
2100 | ||
8d0deca8 VS |
2101 | /* Return the tile dimensions in pixel units */ |
2102 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2103 | unsigned int *tile_width, | |
2104 | unsigned int *tile_height, | |
2105 | uint64_t fb_modifier, | |
2106 | unsigned int cpp) | |
2107 | { | |
2108 | unsigned int tile_width_bytes = | |
2109 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2110 | ||
2111 | *tile_width = tile_width_bytes / cpp; | |
2112 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2113 | } | |
2114 | ||
6761dd31 TU |
2115 | unsigned int |
2116 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2117 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2118 | { |
832be82f VS |
2119 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2120 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2121 | ||
2122 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2123 | } |
2124 | ||
1663b9d6 VS |
2125 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2126 | { | |
2127 | unsigned int size = 0; | |
2128 | int i; | |
2129 | ||
2130 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2131 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2132 | ||
2133 | return size; | |
2134 | } | |
2135 | ||
75c82a53 | 2136 | static void |
3465c580 VS |
2137 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2138 | const struct drm_framebuffer *fb, | |
2139 | unsigned int rotation) | |
f64b98cd | 2140 | { |
2d7a215f VS |
2141 | if (intel_rotation_90_or_270(rotation)) { |
2142 | *view = i915_ggtt_view_rotated; | |
2143 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2144 | } else { | |
2145 | *view = i915_ggtt_view_normal; | |
2146 | } | |
2147 | } | |
50470bb0 | 2148 | |
2d7a215f VS |
2149 | static void |
2150 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2151 | struct drm_framebuffer *fb) | |
2152 | { | |
2153 | struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info; | |
2154 | unsigned int tile_size, tile_width, tile_height, cpp; | |
50470bb0 | 2155 | |
d9b3288e VS |
2156 | tile_size = intel_tile_size(dev_priv); |
2157 | ||
2158 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
8d0deca8 VS |
2159 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2160 | fb->modifier[0], cpp); | |
d9b3288e | 2161 | |
1663b9d6 VS |
2162 | info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp); |
2163 | info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height); | |
84fe03f7 | 2164 | |
89e3e142 | 2165 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2166 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
8d0deca8 VS |
2167 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2168 | fb->modifier[1], cpp); | |
d9b3288e | 2169 | |
2d7a215f | 2170 | info->uv_offset = fb->offsets[1]; |
1663b9d6 VS |
2171 | info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp); |
2172 | info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height); | |
89e3e142 | 2173 | } |
f64b98cd TU |
2174 | } |
2175 | ||
603525d7 | 2176 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2177 | { |
2178 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2179 | return 256 * 1024; | |
985b8bb4 | 2180 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2181 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2182 | return 128 * 1024; |
2183 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2184 | return 4 * 1024; | |
2185 | else | |
44c5905e | 2186 | return 0; |
4e9a86b6 VS |
2187 | } |
2188 | ||
603525d7 VS |
2189 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2190 | uint64_t fb_modifier) | |
2191 | { | |
2192 | switch (fb_modifier) { | |
2193 | case DRM_FORMAT_MOD_NONE: | |
2194 | return intel_linear_alignment(dev_priv); | |
2195 | case I915_FORMAT_MOD_X_TILED: | |
2196 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2197 | return 256 * 1024; | |
2198 | return 0; | |
2199 | case I915_FORMAT_MOD_Y_TILED: | |
2200 | case I915_FORMAT_MOD_Yf_TILED: | |
2201 | return 1 * 1024 * 1024; | |
2202 | default: | |
2203 | MISSING_CASE(fb_modifier); | |
2204 | return 0; | |
2205 | } | |
2206 | } | |
2207 | ||
127bd2ac | 2208 | int |
3465c580 VS |
2209 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
2210 | unsigned int rotation) | |
6b95a207 | 2211 | { |
850c4cdc | 2212 | struct drm_device *dev = fb->dev; |
fac5e23e | 2213 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2214 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2215 | struct i915_ggtt_view view; |
6b95a207 KH |
2216 | u32 alignment; |
2217 | int ret; | |
2218 | ||
ebcdd39e MR |
2219 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2220 | ||
603525d7 | 2221 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2222 | |
3465c580 | 2223 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2224 | |
693db184 CW |
2225 | /* Note that the w/a also requires 64 PTE of padding following the |
2226 | * bo. We currently fill all unused PTE with the shadow page and so | |
2227 | * we should always have valid PTE following the scanout preventing | |
2228 | * the VT-d warning. | |
2229 | */ | |
48f112fe | 2230 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2231 | alignment = 256 * 1024; |
2232 | ||
d6dd6843 PZ |
2233 | /* |
2234 | * Global gtt pte registers are special registers which actually forward | |
2235 | * writes to a chunk of system memory. Which means that there is no risk | |
2236 | * that the register values disappear as soon as we call | |
2237 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2238 | * pin/unpin/fence and not more. | |
2239 | */ | |
2240 | intel_runtime_pm_get(dev_priv); | |
2241 | ||
7580d774 ML |
2242 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2243 | &view); | |
48b956c5 | 2244 | if (ret) |
b26a6b35 | 2245 | goto err_pm; |
6b95a207 KH |
2246 | |
2247 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2248 | * fence, whereas 965+ only requires a fence if using | |
2249 | * framebuffer compression. For simplicity, we always install | |
2250 | * a fence as the cost is not that onerous. | |
2251 | */ | |
9807216f VK |
2252 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2253 | ret = i915_gem_object_get_fence(obj); | |
2254 | if (ret == -EDEADLK) { | |
2255 | /* | |
2256 | * -EDEADLK means there are no free fences | |
2257 | * no pending flips. | |
2258 | * | |
2259 | * This is propagated to atomic, but it uses | |
2260 | * -EDEADLK to force a locking recovery, so | |
2261 | * change the returned error to -EBUSY. | |
2262 | */ | |
2263 | ret = -EBUSY; | |
2264 | goto err_unpin; | |
2265 | } else if (ret) | |
2266 | goto err_unpin; | |
1690e1eb | 2267 | |
9807216f VK |
2268 | i915_gem_object_pin_fence(obj); |
2269 | } | |
6b95a207 | 2270 | |
d6dd6843 | 2271 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2272 | return 0; |
48b956c5 CW |
2273 | |
2274 | err_unpin: | |
f64b98cd | 2275 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2276 | err_pm: |
d6dd6843 | 2277 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2278 | return ret; |
6b95a207 KH |
2279 | } |
2280 | ||
fb4b8ce1 | 2281 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2282 | { |
82bc3b2d | 2283 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2284 | struct i915_ggtt_view view; |
82bc3b2d | 2285 | |
ebcdd39e MR |
2286 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2287 | ||
3465c580 | 2288 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2289 | |
9807216f VK |
2290 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2291 | i915_gem_object_unpin_fence(obj); | |
2292 | ||
f64b98cd | 2293 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2294 | } |
2295 | ||
29cf9491 VS |
2296 | /* |
2297 | * Adjust the tile offset by moving the difference into | |
2298 | * the x/y offsets. | |
2299 | * | |
2300 | * Input tile dimensions and pitch must already be | |
2301 | * rotated to match x and y, and in pixel units. | |
2302 | */ | |
2303 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2304 | unsigned int tile_width, | |
2305 | unsigned int tile_height, | |
2306 | unsigned int tile_size, | |
2307 | unsigned int pitch_tiles, | |
2308 | u32 old_offset, | |
2309 | u32 new_offset) | |
2310 | { | |
2311 | unsigned int tiles; | |
2312 | ||
2313 | WARN_ON(old_offset & (tile_size - 1)); | |
2314 | WARN_ON(new_offset & (tile_size - 1)); | |
2315 | WARN_ON(new_offset > old_offset); | |
2316 | ||
2317 | tiles = (old_offset - new_offset) / tile_size; | |
2318 | ||
2319 | *y += tiles / pitch_tiles * tile_height; | |
2320 | *x += tiles % pitch_tiles * tile_width; | |
2321 | ||
2322 | return new_offset; | |
2323 | } | |
2324 | ||
8d0deca8 VS |
2325 | /* |
2326 | * Computes the linear offset to the base tile and adjusts | |
2327 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2328 | * | |
2329 | * In the 90/270 rotated case, x and y are assumed | |
2330 | * to be already rotated to match the rotated GTT view, and | |
2331 | * pitch is the tile_height aligned framebuffer height. | |
2332 | */ | |
4f2d9934 VS |
2333 | u32 intel_compute_tile_offset(int *x, int *y, |
2334 | const struct drm_framebuffer *fb, int plane, | |
8d0deca8 VS |
2335 | unsigned int pitch, |
2336 | unsigned int rotation) | |
c2c75131 | 2337 | { |
4f2d9934 VS |
2338 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2339 | uint64_t fb_modifier = fb->modifier[plane]; | |
2340 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
29cf9491 VS |
2341 | u32 offset, offset_aligned, alignment; |
2342 | ||
2343 | alignment = intel_surf_alignment(dev_priv, fb_modifier); | |
2344 | if (alignment) | |
2345 | alignment--; | |
2346 | ||
b5c65338 | 2347 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2348 | unsigned int tile_size, tile_width, tile_height; |
2349 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2350 | |
d843310d | 2351 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2352 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2353 | fb_modifier, cpp); | |
2354 | ||
2355 | if (intel_rotation_90_or_270(rotation)) { | |
2356 | pitch_tiles = pitch / tile_height; | |
2357 | swap(tile_width, tile_height); | |
2358 | } else { | |
2359 | pitch_tiles = pitch / (tile_width * cpp); | |
2360 | } | |
d843310d VS |
2361 | |
2362 | tile_rows = *y / tile_height; | |
2363 | *y %= tile_height; | |
c2c75131 | 2364 | |
8d0deca8 VS |
2365 | tiles = *x / tile_width; |
2366 | *x %= tile_width; | |
bc752862 | 2367 | |
29cf9491 VS |
2368 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2369 | offset_aligned = offset & ~alignment; | |
bc752862 | 2370 | |
29cf9491 VS |
2371 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2372 | tile_size, pitch_tiles, | |
2373 | offset, offset_aligned); | |
2374 | } else { | |
bc752862 | 2375 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2376 | offset_aligned = offset & ~alignment; |
2377 | ||
4e9a86b6 VS |
2378 | *y = (offset & alignment) / pitch; |
2379 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2380 | } |
29cf9491 VS |
2381 | |
2382 | return offset_aligned; | |
c2c75131 DV |
2383 | } |
2384 | ||
b35d63fa | 2385 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2386 | { |
2387 | switch (format) { | |
2388 | case DISPPLANE_8BPP: | |
2389 | return DRM_FORMAT_C8; | |
2390 | case DISPPLANE_BGRX555: | |
2391 | return DRM_FORMAT_XRGB1555; | |
2392 | case DISPPLANE_BGRX565: | |
2393 | return DRM_FORMAT_RGB565; | |
2394 | default: | |
2395 | case DISPPLANE_BGRX888: | |
2396 | return DRM_FORMAT_XRGB8888; | |
2397 | case DISPPLANE_RGBX888: | |
2398 | return DRM_FORMAT_XBGR8888; | |
2399 | case DISPPLANE_BGRX101010: | |
2400 | return DRM_FORMAT_XRGB2101010; | |
2401 | case DISPPLANE_RGBX101010: | |
2402 | return DRM_FORMAT_XBGR2101010; | |
2403 | } | |
2404 | } | |
2405 | ||
bc8d7dff DL |
2406 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2407 | { | |
2408 | switch (format) { | |
2409 | case PLANE_CTL_FORMAT_RGB_565: | |
2410 | return DRM_FORMAT_RGB565; | |
2411 | default: | |
2412 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2413 | if (rgb_order) { | |
2414 | if (alpha) | |
2415 | return DRM_FORMAT_ABGR8888; | |
2416 | else | |
2417 | return DRM_FORMAT_XBGR8888; | |
2418 | } else { | |
2419 | if (alpha) | |
2420 | return DRM_FORMAT_ARGB8888; | |
2421 | else | |
2422 | return DRM_FORMAT_XRGB8888; | |
2423 | } | |
2424 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2425 | if (rgb_order) | |
2426 | return DRM_FORMAT_XBGR2101010; | |
2427 | else | |
2428 | return DRM_FORMAT_XRGB2101010; | |
2429 | } | |
2430 | } | |
2431 | ||
5724dbd1 | 2432 | static bool |
f6936e29 DV |
2433 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2434 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2435 | { |
2436 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2437 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2438 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2439 | struct drm_i915_gem_object *obj = NULL; |
2440 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2441 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2442 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2443 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2444 | PAGE_SIZE); | |
2445 | ||
2446 | size_aligned -= base_aligned; | |
46f297fb | 2447 | |
ff2652ea CW |
2448 | if (plane_config->size == 0) |
2449 | return false; | |
2450 | ||
3badb49f PZ |
2451 | /* If the FB is too big, just don't use it since fbdev is not very |
2452 | * important and we should probably use that space with FBC or other | |
2453 | * features. */ | |
72e96d64 | 2454 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2455 | return false; |
2456 | ||
12c83d99 TU |
2457 | mutex_lock(&dev->struct_mutex); |
2458 | ||
f37b5c2b DV |
2459 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2460 | base_aligned, | |
2461 | base_aligned, | |
2462 | size_aligned); | |
12c83d99 TU |
2463 | if (!obj) { |
2464 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2465 | return false; |
12c83d99 | 2466 | } |
46f297fb | 2467 | |
49af449b DL |
2468 | obj->tiling_mode = plane_config->tiling; |
2469 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2470 | obj->stride = fb->pitches[0]; |
46f297fb | 2471 | |
6bf129df DL |
2472 | mode_cmd.pixel_format = fb->pixel_format; |
2473 | mode_cmd.width = fb->width; | |
2474 | mode_cmd.height = fb->height; | |
2475 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2476 | mode_cmd.modifier[0] = fb->modifier[0]; |
2477 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2478 | |
6bf129df | 2479 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2480 | &mode_cmd, obj)) { |
46f297fb JB |
2481 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2482 | goto out_unref_obj; | |
2483 | } | |
12c83d99 | 2484 | |
46f297fb | 2485 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2486 | |
f6936e29 | 2487 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2488 | return true; |
46f297fb JB |
2489 | |
2490 | out_unref_obj: | |
f8c417cd | 2491 | i915_gem_object_put(obj); |
46f297fb | 2492 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2493 | return false; |
2494 | } | |
2495 | ||
5a21b665 DV |
2496 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2497 | static void | |
2498 | update_state_fb(struct drm_plane *plane) | |
2499 | { | |
2500 | if (plane->fb == plane->state->fb) | |
2501 | return; | |
2502 | ||
2503 | if (plane->state->fb) | |
2504 | drm_framebuffer_unreference(plane->state->fb); | |
2505 | plane->state->fb = plane->fb; | |
2506 | if (plane->state->fb) | |
2507 | drm_framebuffer_reference(plane->state->fb); | |
2508 | } | |
2509 | ||
5724dbd1 | 2510 | static void |
f6936e29 DV |
2511 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2512 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2513 | { |
2514 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2515 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd JB |
2516 | struct drm_crtc *c; |
2517 | struct intel_crtc *i; | |
2ff8fde1 | 2518 | struct drm_i915_gem_object *obj; |
88595ac9 | 2519 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2520 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2521 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2522 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2523 | struct intel_plane_state *intel_state = |
2524 | to_intel_plane_state(plane_state); | |
88595ac9 | 2525 | struct drm_framebuffer *fb; |
484b41dd | 2526 | |
2d14030b | 2527 | if (!plane_config->fb) |
484b41dd JB |
2528 | return; |
2529 | ||
f6936e29 | 2530 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2531 | fb = &plane_config->fb->base; |
2532 | goto valid_fb; | |
f55548b5 | 2533 | } |
484b41dd | 2534 | |
2d14030b | 2535 | kfree(plane_config->fb); |
484b41dd JB |
2536 | |
2537 | /* | |
2538 | * Failed to alloc the obj, check to see if we should share | |
2539 | * an fb with another CRTC instead | |
2540 | */ | |
70e1e0ec | 2541 | for_each_crtc(dev, c) { |
484b41dd JB |
2542 | i = to_intel_crtc(c); |
2543 | ||
2544 | if (c == &intel_crtc->base) | |
2545 | continue; | |
2546 | ||
2ff8fde1 MR |
2547 | if (!i->active) |
2548 | continue; | |
2549 | ||
88595ac9 DV |
2550 | fb = c->primary->fb; |
2551 | if (!fb) | |
484b41dd JB |
2552 | continue; |
2553 | ||
88595ac9 | 2554 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2555 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2556 | drm_framebuffer_reference(fb); |
2557 | goto valid_fb; | |
484b41dd JB |
2558 | } |
2559 | } | |
88595ac9 | 2560 | |
200757f5 MR |
2561 | /* |
2562 | * We've failed to reconstruct the BIOS FB. Current display state | |
2563 | * indicates that the primary plane is visible, but has a NULL FB, | |
2564 | * which will lead to problems later if we don't fix it up. The | |
2565 | * simplest solution is to just disable the primary plane now and | |
2566 | * pretend the BIOS never had it enabled. | |
2567 | */ | |
2568 | to_intel_plane_state(plane_state)->visible = false; | |
2569 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2622a081 | 2570 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2571 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2572 | ||
88595ac9 DV |
2573 | return; |
2574 | ||
2575 | valid_fb: | |
f44e2659 VS |
2576 | plane_state->src_x = 0; |
2577 | plane_state->src_y = 0; | |
be5651f2 ML |
2578 | plane_state->src_w = fb->width << 16; |
2579 | plane_state->src_h = fb->height << 16; | |
2580 | ||
f44e2659 VS |
2581 | plane_state->crtc_x = 0; |
2582 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2583 | plane_state->crtc_w = fb->width; |
2584 | plane_state->crtc_h = fb->height; | |
2585 | ||
0a8d8a86 MR |
2586 | intel_state->src.x1 = plane_state->src_x; |
2587 | intel_state->src.y1 = plane_state->src_y; | |
2588 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2589 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2590 | intel_state->dst.x1 = plane_state->crtc_x; | |
2591 | intel_state->dst.y1 = plane_state->crtc_y; | |
2592 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2593 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2594 | ||
88595ac9 DV |
2595 | obj = intel_fb_obj(fb); |
2596 | if (obj->tiling_mode != I915_TILING_NONE) | |
2597 | dev_priv->preserve_bios_swizzle = true; | |
2598 | ||
be5651f2 ML |
2599 | drm_framebuffer_reference(fb); |
2600 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2601 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2602 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2603 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2604 | } |
2605 | ||
a8d201af ML |
2606 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2607 | const struct intel_crtc_state *crtc_state, | |
2608 | const struct intel_plane_state *plane_state) | |
81255565 | 2609 | { |
a8d201af | 2610 | struct drm_device *dev = primary->dev; |
fac5e23e | 2611 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
2612 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2613 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2614 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2615 | int plane = intel_crtc->plane; |
54ea9da8 | 2616 | u32 linear_offset; |
81255565 | 2617 | u32 dspcntr; |
f0f59a00 | 2618 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2619 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2620 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2621 | int x = plane_state->src.x1 >> 16; |
2622 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2623 | |
f45651ba VS |
2624 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2625 | ||
fdd508a6 | 2626 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2627 | |
2628 | if (INTEL_INFO(dev)->gen < 4) { | |
2629 | if (intel_crtc->pipe == PIPE_B) | |
2630 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2631 | ||
2632 | /* pipesrc and dspsize control the size that is scaled from, | |
2633 | * which should always be the user's requested size. | |
2634 | */ | |
2635 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2636 | ((crtc_state->pipe_src_h - 1) << 16) | |
2637 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2638 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2639 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2640 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2641 | ((crtc_state->pipe_src_h - 1) << 16) | |
2642 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2643 | I915_WRITE(PRIMPOS(plane), 0); |
2644 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2645 | } |
81255565 | 2646 | |
57779d06 VS |
2647 | switch (fb->pixel_format) { |
2648 | case DRM_FORMAT_C8: | |
81255565 JB |
2649 | dspcntr |= DISPPLANE_8BPP; |
2650 | break; | |
57779d06 | 2651 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2652 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2653 | break; |
57779d06 VS |
2654 | case DRM_FORMAT_RGB565: |
2655 | dspcntr |= DISPPLANE_BGRX565; | |
2656 | break; | |
2657 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2658 | dspcntr |= DISPPLANE_BGRX888; |
2659 | break; | |
2660 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2661 | dspcntr |= DISPPLANE_RGBX888; |
2662 | break; | |
2663 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2664 | dspcntr |= DISPPLANE_BGRX101010; |
2665 | break; | |
2666 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2667 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2668 | break; |
2669 | default: | |
baba133a | 2670 | BUG(); |
81255565 | 2671 | } |
57779d06 | 2672 | |
f45651ba VS |
2673 | if (INTEL_INFO(dev)->gen >= 4 && |
2674 | obj->tiling_mode != I915_TILING_NONE) | |
2675 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2676 | |
de1aa629 VS |
2677 | if (IS_G4X(dev)) |
2678 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2679 | ||
ac484963 | 2680 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2681 | |
c2c75131 DV |
2682 | if (INTEL_INFO(dev)->gen >= 4) { |
2683 | intel_crtc->dspaddr_offset = | |
4f2d9934 | 2684 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2685 | fb->pitches[0], rotation); |
c2c75131 DV |
2686 | linear_offset -= intel_crtc->dspaddr_offset; |
2687 | } else { | |
e506a0c6 | 2688 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2689 | } |
e506a0c6 | 2690 | |
8d0deca8 | 2691 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2692 | dspcntr |= DISPPLANE_ROTATE_180; |
2693 | ||
a8d201af ML |
2694 | x += (crtc_state->pipe_src_w - 1); |
2695 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2696 | |
2697 | /* Finding the last pixel of the last line of the display | |
2698 | data and adding to linear_offset*/ | |
2699 | linear_offset += | |
a8d201af | 2700 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2701 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2702 | } |
2703 | ||
2db3366b PZ |
2704 | intel_crtc->adjusted_x = x; |
2705 | intel_crtc->adjusted_y = y; | |
2706 | ||
48404c1e SJ |
2707 | I915_WRITE(reg, dspcntr); |
2708 | ||
01f2c773 | 2709 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2710 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2711 | I915_WRITE(DSPSURF(plane), |
2712 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2713 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2714 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2715 | } else |
f343c5f6 | 2716 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2717 | POSTING_READ(reg); |
17638cd6 JB |
2718 | } |
2719 | ||
a8d201af ML |
2720 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2721 | struct drm_crtc *crtc) | |
17638cd6 JB |
2722 | { |
2723 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 2724 | struct drm_i915_private *dev_priv = to_i915(dev); |
17638cd6 | 2725 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
17638cd6 | 2726 | int plane = intel_crtc->plane; |
f45651ba | 2727 | |
a8d201af ML |
2728 | I915_WRITE(DSPCNTR(plane), 0); |
2729 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2730 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2731 | else |
2732 | I915_WRITE(DSPADDR(plane), 0); | |
2733 | POSTING_READ(DSPCNTR(plane)); | |
2734 | } | |
c9ba6fad | 2735 | |
a8d201af ML |
2736 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2737 | const struct intel_crtc_state *crtc_state, | |
2738 | const struct intel_plane_state *plane_state) | |
2739 | { | |
2740 | struct drm_device *dev = primary->dev; | |
fac5e23e | 2741 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
2742 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2743 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2744 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2745 | int plane = intel_crtc->plane; | |
54ea9da8 | 2746 | u32 linear_offset; |
a8d201af ML |
2747 | u32 dspcntr; |
2748 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 2749 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2750 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2751 | int x = plane_state->src.x1 >> 16; |
2752 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2753 | |
f45651ba | 2754 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2755 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2756 | |
2757 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2758 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2759 | |
57779d06 VS |
2760 | switch (fb->pixel_format) { |
2761 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2762 | dspcntr |= DISPPLANE_8BPP; |
2763 | break; | |
57779d06 VS |
2764 | case DRM_FORMAT_RGB565: |
2765 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2766 | break; |
57779d06 | 2767 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2768 | dspcntr |= DISPPLANE_BGRX888; |
2769 | break; | |
2770 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2771 | dspcntr |= DISPPLANE_RGBX888; |
2772 | break; | |
2773 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2774 | dspcntr |= DISPPLANE_BGRX101010; |
2775 | break; | |
2776 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2777 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2778 | break; |
2779 | default: | |
baba133a | 2780 | BUG(); |
17638cd6 JB |
2781 | } |
2782 | ||
2783 | if (obj->tiling_mode != I915_TILING_NONE) | |
2784 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2785 | |
f45651ba | 2786 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2787 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2788 | |
ac484963 | 2789 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2790 | intel_crtc->dspaddr_offset = |
4f2d9934 | 2791 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2792 | fb->pitches[0], rotation); |
c2c75131 | 2793 | linear_offset -= intel_crtc->dspaddr_offset; |
8d0deca8 | 2794 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2795 | dspcntr |= DISPPLANE_ROTATE_180; |
2796 | ||
2797 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2798 | x += (crtc_state->pipe_src_w - 1); |
2799 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2800 | |
2801 | /* Finding the last pixel of the last line of the display | |
2802 | data and adding to linear_offset*/ | |
2803 | linear_offset += | |
a8d201af | 2804 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2805 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2806 | } |
2807 | } | |
2808 | ||
2db3366b PZ |
2809 | intel_crtc->adjusted_x = x; |
2810 | intel_crtc->adjusted_y = y; | |
2811 | ||
48404c1e | 2812 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2813 | |
01f2c773 | 2814 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2815 | I915_WRITE(DSPSURF(plane), |
2816 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2817 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2818 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2819 | } else { | |
2820 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2821 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2822 | } | |
17638cd6 | 2823 | POSTING_READ(reg); |
17638cd6 JB |
2824 | } |
2825 | ||
7b49f948 VS |
2826 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2827 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2828 | { |
7b49f948 | 2829 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2830 | return 64; |
7b49f948 VS |
2831 | } else { |
2832 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2833 | ||
27ba3910 | 2834 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
2835 | } |
2836 | } | |
2837 | ||
44eb0cb9 MK |
2838 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2839 | struct drm_i915_gem_object *obj, | |
2840 | unsigned int plane) | |
121920fa | 2841 | { |
ce7f1728 | 2842 | struct i915_ggtt_view view; |
dedf278c | 2843 | struct i915_vma *vma; |
44eb0cb9 | 2844 | u64 offset; |
121920fa | 2845 | |
e7941294 | 2846 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
3465c580 | 2847 | intel_plane->base.state->rotation); |
121920fa | 2848 | |
ce7f1728 | 2849 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2850 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2851 | view.type)) |
dedf278c TU |
2852 | return -1; |
2853 | ||
44eb0cb9 | 2854 | offset = vma->node.start; |
dedf278c TU |
2855 | |
2856 | if (plane == 1) { | |
7723f47d | 2857 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
2858 | PAGE_SIZE; |
2859 | } | |
2860 | ||
44eb0cb9 MK |
2861 | WARN_ON(upper_32_bits(offset)); |
2862 | ||
2863 | return lower_32_bits(offset); | |
121920fa TU |
2864 | } |
2865 | ||
e435d6e5 ML |
2866 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2867 | { | |
2868 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2869 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
2870 | |
2871 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2872 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2873 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2874 | } |
2875 | ||
a1b2278e CK |
2876 | /* |
2877 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2878 | */ | |
0583236e | 2879 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2880 | { |
a1b2278e CK |
2881 | struct intel_crtc_scaler_state *scaler_state; |
2882 | int i; | |
2883 | ||
a1b2278e CK |
2884 | scaler_state = &intel_crtc->config->scaler_state; |
2885 | ||
2886 | /* loop through and disable scalers that aren't in use */ | |
2887 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2888 | if (!scaler_state->scalers[i].in_use) |
2889 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2890 | } |
2891 | } | |
2892 | ||
6156a456 | 2893 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2894 | { |
6156a456 | 2895 | switch (pixel_format) { |
d161cf7a | 2896 | case DRM_FORMAT_C8: |
c34ce3d1 | 2897 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2898 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2899 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2900 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2901 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2902 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2903 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2904 | /* |
2905 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2906 | * to be already pre-multiplied. We need to add a knob (or a different | |
2907 | * DRM_FORMAT) for user-space to configure that. | |
2908 | */ | |
f75fb42a | 2909 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2910 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2911 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2912 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2913 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2914 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2915 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2916 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2917 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2918 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2919 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2920 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2921 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2922 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2923 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2924 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2925 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2926 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2927 | default: |
4249eeef | 2928 | MISSING_CASE(pixel_format); |
70d21f0e | 2929 | } |
8cfcba41 | 2930 | |
c34ce3d1 | 2931 | return 0; |
6156a456 | 2932 | } |
70d21f0e | 2933 | |
6156a456 CK |
2934 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2935 | { | |
6156a456 | 2936 | switch (fb_modifier) { |
30af77c4 | 2937 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2938 | break; |
30af77c4 | 2939 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2940 | return PLANE_CTL_TILED_X; |
b321803d | 2941 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 2942 | return PLANE_CTL_TILED_Y; |
b321803d | 2943 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 2944 | return PLANE_CTL_TILED_YF; |
70d21f0e | 2945 | default: |
6156a456 | 2946 | MISSING_CASE(fb_modifier); |
70d21f0e | 2947 | } |
8cfcba41 | 2948 | |
c34ce3d1 | 2949 | return 0; |
6156a456 | 2950 | } |
70d21f0e | 2951 | |
6156a456 CK |
2952 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
2953 | { | |
3b7a5119 | 2954 | switch (rotation) { |
6156a456 CK |
2955 | case BIT(DRM_ROTATE_0): |
2956 | break; | |
1e8df167 SJ |
2957 | /* |
2958 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
2959 | * while i915 HW rotation is clockwise, thats why this swapping. | |
2960 | */ | |
3b7a5119 | 2961 | case BIT(DRM_ROTATE_90): |
1e8df167 | 2962 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 2963 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 2964 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 2965 | case BIT(DRM_ROTATE_270): |
1e8df167 | 2966 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
2967 | default: |
2968 | MISSING_CASE(rotation); | |
2969 | } | |
2970 | ||
c34ce3d1 | 2971 | return 0; |
6156a456 CK |
2972 | } |
2973 | ||
a8d201af ML |
2974 | static void skylake_update_primary_plane(struct drm_plane *plane, |
2975 | const struct intel_crtc_state *crtc_state, | |
2976 | const struct intel_plane_state *plane_state) | |
6156a456 | 2977 | { |
a8d201af | 2978 | struct drm_device *dev = plane->dev; |
fac5e23e | 2979 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
2980 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2981 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2982 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
2983 | int pipe = intel_crtc->pipe; |
2984 | u32 plane_ctl, stride_div, stride; | |
2985 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 2986 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 2987 | int x_offset, y_offset; |
44eb0cb9 | 2988 | u32 surf_addr; |
a8d201af ML |
2989 | int scaler_id = plane_state->scaler_id; |
2990 | int src_x = plane_state->src.x1 >> 16; | |
2991 | int src_y = plane_state->src.y1 >> 16; | |
2992 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
2993 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
2994 | int dst_x = plane_state->dst.x1; | |
2995 | int dst_y = plane_state->dst.y1; | |
2996 | int dst_w = drm_rect_width(&plane_state->dst); | |
2997 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 2998 | |
6156a456 CK |
2999 | plane_ctl = PLANE_CTL_ENABLE | |
3000 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3001 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3002 | ||
3003 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3004 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3005 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3006 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3007 | ||
7b49f948 | 3008 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3009 | fb->pixel_format); |
dedf278c | 3010 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3011 | |
a42e5a23 PZ |
3012 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3013 | ||
3b7a5119 | 3014 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3015 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3016 | ||
3b7a5119 | 3017 | /* stride = Surface height in tiles */ |
832be82f | 3018 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3019 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3020 | x_offset = stride * tile_height - src_y - src_h; |
3021 | y_offset = src_x; | |
6156a456 | 3022 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3023 | } else { |
3024 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3025 | x_offset = src_x; |
3026 | y_offset = src_y; | |
6156a456 | 3027 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3028 | } |
3029 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3030 | |
2db3366b PZ |
3031 | intel_crtc->adjusted_x = x_offset; |
3032 | intel_crtc->adjusted_y = y_offset; | |
3033 | ||
70d21f0e | 3034 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3035 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3036 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3037 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3038 | |
3039 | if (scaler_id >= 0) { | |
3040 | uint32_t ps_ctrl = 0; | |
3041 | ||
3042 | WARN_ON(!dst_w || !dst_h); | |
3043 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3044 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3045 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3046 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3047 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3048 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3049 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3050 | } else { | |
3051 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3052 | } | |
3053 | ||
121920fa | 3054 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3055 | |
3056 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3057 | } | |
3058 | ||
a8d201af ML |
3059 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3060 | struct drm_crtc *crtc) | |
17638cd6 JB |
3061 | { |
3062 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3063 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af | 3064 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3065 | |
a8d201af ML |
3066 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3067 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3068 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3069 | } | |
29b9bde6 | 3070 | |
a8d201af ML |
3071 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3072 | static int | |
3073 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3074 | int x, int y, enum mode_set_atomic state) | |
3075 | { | |
3076 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3077 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3078 | ||
3079 | return -ENODEV; | |
81255565 JB |
3080 | } |
3081 | ||
5a21b665 DV |
3082 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3083 | { | |
3084 | struct intel_crtc *crtc; | |
3085 | ||
91c8a326 | 3086 | for_each_intel_crtc(&dev_priv->drm, crtc) |
5a21b665 DV |
3087 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
3088 | } | |
3089 | ||
7514747d VS |
3090 | static void intel_update_primary_planes(struct drm_device *dev) |
3091 | { | |
7514747d | 3092 | struct drm_crtc *crtc; |
96a02917 | 3093 | |
70e1e0ec | 3094 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3095 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3096 | struct intel_plane_state *plane_state; | |
96a02917 | 3097 | |
11c22da6 | 3098 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3099 | plane_state = to_intel_plane_state(plane->base.state); |
3100 | ||
a8d201af ML |
3101 | if (plane_state->visible) |
3102 | plane->update_plane(&plane->base, | |
3103 | to_intel_crtc_state(crtc->state), | |
3104 | plane_state); | |
11c22da6 ML |
3105 | |
3106 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3107 | } |
3108 | } | |
3109 | ||
c033666a | 3110 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d VS |
3111 | { |
3112 | /* no reset support for gen2 */ | |
c033666a | 3113 | if (IS_GEN2(dev_priv)) |
7514747d VS |
3114 | return; |
3115 | ||
3116 | /* reset doesn't touch the display */ | |
c033666a | 3117 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
7514747d VS |
3118 | return; |
3119 | ||
91c8a326 | 3120 | drm_modeset_lock_all(&dev_priv->drm); |
f98ce92f VS |
3121 | /* |
3122 | * Disabling the crtcs gracefully seems nicer. Also the | |
3123 | * g33 docs say we should at least disable all the planes. | |
3124 | */ | |
91c8a326 | 3125 | intel_display_suspend(&dev_priv->drm); |
7514747d VS |
3126 | } |
3127 | ||
c033666a | 3128 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3129 | { |
5a21b665 DV |
3130 | /* |
3131 | * Flips in the rings will be nuked by the reset, | |
3132 | * so complete all pending flips so that user space | |
3133 | * will get its events and not get stuck. | |
3134 | */ | |
3135 | intel_complete_page_flips(dev_priv); | |
3136 | ||
7514747d | 3137 | /* no reset support for gen2 */ |
c033666a | 3138 | if (IS_GEN2(dev_priv)) |
7514747d VS |
3139 | return; |
3140 | ||
3141 | /* reset doesn't touch the display */ | |
c033666a | 3142 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
7514747d VS |
3143 | /* |
3144 | * Flips in the rings have been nuked by the reset, | |
3145 | * so update the base address of all primary | |
3146 | * planes to the the last fb to make sure we're | |
3147 | * showing the correct fb after a reset. | |
11c22da6 ML |
3148 | * |
3149 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3150 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d | 3151 | */ |
91c8a326 | 3152 | intel_update_primary_planes(&dev_priv->drm); |
7514747d VS |
3153 | return; |
3154 | } | |
3155 | ||
3156 | /* | |
3157 | * The display has been reset as well, | |
3158 | * so need a full re-initialization. | |
3159 | */ | |
3160 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3161 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3162 | ||
91c8a326 | 3163 | intel_modeset_init_hw(&dev_priv->drm); |
7514747d VS |
3164 | |
3165 | spin_lock_irq(&dev_priv->irq_lock); | |
3166 | if (dev_priv->display.hpd_irq_setup) | |
91d14251 | 3167 | dev_priv->display.hpd_irq_setup(dev_priv); |
7514747d VS |
3168 | spin_unlock_irq(&dev_priv->irq_lock); |
3169 | ||
91c8a326 | 3170 | intel_display_resume(&dev_priv->drm); |
7514747d VS |
3171 | |
3172 | intel_hpd_init(dev_priv); | |
3173 | ||
91c8a326 | 3174 | drm_modeset_unlock_all(&dev_priv->drm); |
7514747d VS |
3175 | } |
3176 | ||
7d5e3799 CW |
3177 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3178 | { | |
5a21b665 DV |
3179 | struct drm_device *dev = crtc->dev; |
3180 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3181 | unsigned reset_counter; | |
3182 | bool pending; | |
3183 | ||
3184 | reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error); | |
3185 | if (intel_crtc->reset_counter != reset_counter) | |
3186 | return false; | |
3187 | ||
3188 | spin_lock_irq(&dev->event_lock); | |
3189 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3190 | spin_unlock_irq(&dev->event_lock); | |
3191 | ||
3192 | return pending; | |
7d5e3799 CW |
3193 | } |
3194 | ||
bfd16b2a ML |
3195 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3196 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3197 | { |
3198 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 3199 | struct drm_i915_private *dev_priv = to_i915(dev); |
bfd16b2a ML |
3200 | struct intel_crtc_state *pipe_config = |
3201 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3202 | |
bfd16b2a ML |
3203 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3204 | crtc->base.mode = crtc->base.state->mode; | |
3205 | ||
3206 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3207 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3208 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3209 | |
3210 | /* | |
3211 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3212 | * that in compute_mode_changes we check the native mode (not the pfit | |
3213 | * mode) to see if we can flip rather than do a full mode set. In the | |
3214 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3215 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3216 | * sized surface. | |
e30e8f75 GP |
3217 | */ |
3218 | ||
e30e8f75 | 3219 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3220 | ((pipe_config->pipe_src_w - 1) << 16) | |
3221 | (pipe_config->pipe_src_h - 1)); | |
3222 | ||
3223 | /* on skylake this is done by detaching scalers */ | |
3224 | if (INTEL_INFO(dev)->gen >= 9) { | |
3225 | skl_detach_scalers(crtc); | |
3226 | ||
3227 | if (pipe_config->pch_pfit.enabled) | |
3228 | skylake_pfit_enable(crtc); | |
3229 | } else if (HAS_PCH_SPLIT(dev)) { | |
3230 | if (pipe_config->pch_pfit.enabled) | |
3231 | ironlake_pfit_enable(crtc); | |
3232 | else if (old_crtc_state->pch_pfit.enabled) | |
3233 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3234 | } |
e30e8f75 GP |
3235 | } |
3236 | ||
5e84e1a4 ZW |
3237 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3238 | { | |
3239 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3240 | struct drm_i915_private *dev_priv = to_i915(dev); |
5e84e1a4 ZW |
3241 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3242 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3243 | i915_reg_t reg; |
3244 | u32 temp; | |
5e84e1a4 ZW |
3245 | |
3246 | /* enable normal train */ | |
3247 | reg = FDI_TX_CTL(pipe); | |
3248 | temp = I915_READ(reg); | |
61e499bf | 3249 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3250 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3251 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3252 | } else { |
3253 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3254 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3255 | } |
5e84e1a4 ZW |
3256 | I915_WRITE(reg, temp); |
3257 | ||
3258 | reg = FDI_RX_CTL(pipe); | |
3259 | temp = I915_READ(reg); | |
3260 | if (HAS_PCH_CPT(dev)) { | |
3261 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3262 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3263 | } else { | |
3264 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3265 | temp |= FDI_LINK_TRAIN_NONE; | |
3266 | } | |
3267 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3268 | ||
3269 | /* wait one idle pattern time */ | |
3270 | POSTING_READ(reg); | |
3271 | udelay(1000); | |
357555c0 JB |
3272 | |
3273 | /* IVB wants error correction enabled */ | |
3274 | if (IS_IVYBRIDGE(dev)) | |
3275 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3276 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3277 | } |
3278 | ||
8db9d77b ZW |
3279 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3280 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3281 | { | |
3282 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3283 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3284 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3285 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3286 | i915_reg_t reg; |
3287 | u32 temp, tries; | |
8db9d77b | 3288 | |
1c8562f6 | 3289 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3290 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3291 | |
e1a44743 AJ |
3292 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3293 | for train result */ | |
5eddb70b CW |
3294 | reg = FDI_RX_IMR(pipe); |
3295 | temp = I915_READ(reg); | |
e1a44743 AJ |
3296 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3297 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3298 | I915_WRITE(reg, temp); |
3299 | I915_READ(reg); | |
e1a44743 AJ |
3300 | udelay(150); |
3301 | ||
8db9d77b | 3302 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3303 | reg = FDI_TX_CTL(pipe); |
3304 | temp = I915_READ(reg); | |
627eb5a3 | 3305 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3306 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3307 | temp &= ~FDI_LINK_TRAIN_NONE; |
3308 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3309 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3310 | |
5eddb70b CW |
3311 | reg = FDI_RX_CTL(pipe); |
3312 | temp = I915_READ(reg); | |
8db9d77b ZW |
3313 | temp &= ~FDI_LINK_TRAIN_NONE; |
3314 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3315 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3316 | ||
3317 | POSTING_READ(reg); | |
8db9d77b ZW |
3318 | udelay(150); |
3319 | ||
5b2adf89 | 3320 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3321 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3322 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3323 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3324 | |
5eddb70b | 3325 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3326 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3327 | temp = I915_READ(reg); |
8db9d77b ZW |
3328 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3329 | ||
3330 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3331 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3332 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3333 | break; |
3334 | } | |
8db9d77b | 3335 | } |
e1a44743 | 3336 | if (tries == 5) |
5eddb70b | 3337 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3338 | |
3339 | /* Train 2 */ | |
5eddb70b CW |
3340 | reg = FDI_TX_CTL(pipe); |
3341 | temp = I915_READ(reg); | |
8db9d77b ZW |
3342 | temp &= ~FDI_LINK_TRAIN_NONE; |
3343 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3344 | I915_WRITE(reg, temp); |
8db9d77b | 3345 | |
5eddb70b CW |
3346 | reg = FDI_RX_CTL(pipe); |
3347 | temp = I915_READ(reg); | |
8db9d77b ZW |
3348 | temp &= ~FDI_LINK_TRAIN_NONE; |
3349 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3350 | I915_WRITE(reg, temp); |
8db9d77b | 3351 | |
5eddb70b CW |
3352 | POSTING_READ(reg); |
3353 | udelay(150); | |
8db9d77b | 3354 | |
5eddb70b | 3355 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3356 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3357 | temp = I915_READ(reg); |
8db9d77b ZW |
3358 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3359 | ||
3360 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3361 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3362 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3363 | break; | |
3364 | } | |
8db9d77b | 3365 | } |
e1a44743 | 3366 | if (tries == 5) |
5eddb70b | 3367 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3368 | |
3369 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3370 | |
8db9d77b ZW |
3371 | } |
3372 | ||
0206e353 | 3373 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3374 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3375 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3376 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3377 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3378 | }; | |
3379 | ||
3380 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3381 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3382 | { | |
3383 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3384 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3385 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3386 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3387 | i915_reg_t reg; |
3388 | u32 temp, i, retry; | |
8db9d77b | 3389 | |
e1a44743 AJ |
3390 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3391 | for train result */ | |
5eddb70b CW |
3392 | reg = FDI_RX_IMR(pipe); |
3393 | temp = I915_READ(reg); | |
e1a44743 AJ |
3394 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3395 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3396 | I915_WRITE(reg, temp); |
3397 | ||
3398 | POSTING_READ(reg); | |
e1a44743 AJ |
3399 | udelay(150); |
3400 | ||
8db9d77b | 3401 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3402 | reg = FDI_TX_CTL(pipe); |
3403 | temp = I915_READ(reg); | |
627eb5a3 | 3404 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3405 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3406 | temp &= ~FDI_LINK_TRAIN_NONE; |
3407 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3408 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3409 | /* SNB-B */ | |
3410 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3411 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3412 | |
d74cf324 DV |
3413 | I915_WRITE(FDI_RX_MISC(pipe), |
3414 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3415 | ||
5eddb70b CW |
3416 | reg = FDI_RX_CTL(pipe); |
3417 | temp = I915_READ(reg); | |
8db9d77b ZW |
3418 | if (HAS_PCH_CPT(dev)) { |
3419 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3420 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3421 | } else { | |
3422 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3423 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3424 | } | |
5eddb70b CW |
3425 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3426 | ||
3427 | POSTING_READ(reg); | |
8db9d77b ZW |
3428 | udelay(150); |
3429 | ||
0206e353 | 3430 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3431 | reg = FDI_TX_CTL(pipe); |
3432 | temp = I915_READ(reg); | |
8db9d77b ZW |
3433 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3434 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3435 | I915_WRITE(reg, temp); |
3436 | ||
3437 | POSTING_READ(reg); | |
8db9d77b ZW |
3438 | udelay(500); |
3439 | ||
fa37d39e SP |
3440 | for (retry = 0; retry < 5; retry++) { |
3441 | reg = FDI_RX_IIR(pipe); | |
3442 | temp = I915_READ(reg); | |
3443 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3444 | if (temp & FDI_RX_BIT_LOCK) { | |
3445 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3446 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3447 | break; | |
3448 | } | |
3449 | udelay(50); | |
8db9d77b | 3450 | } |
fa37d39e SP |
3451 | if (retry < 5) |
3452 | break; | |
8db9d77b ZW |
3453 | } |
3454 | if (i == 4) | |
5eddb70b | 3455 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3456 | |
3457 | /* Train 2 */ | |
5eddb70b CW |
3458 | reg = FDI_TX_CTL(pipe); |
3459 | temp = I915_READ(reg); | |
8db9d77b ZW |
3460 | temp &= ~FDI_LINK_TRAIN_NONE; |
3461 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3462 | if (IS_GEN6(dev)) { | |
3463 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3464 | /* SNB-B */ | |
3465 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3466 | } | |
5eddb70b | 3467 | I915_WRITE(reg, temp); |
8db9d77b | 3468 | |
5eddb70b CW |
3469 | reg = FDI_RX_CTL(pipe); |
3470 | temp = I915_READ(reg); | |
8db9d77b ZW |
3471 | if (HAS_PCH_CPT(dev)) { |
3472 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3473 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3474 | } else { | |
3475 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3476 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3477 | } | |
5eddb70b CW |
3478 | I915_WRITE(reg, temp); |
3479 | ||
3480 | POSTING_READ(reg); | |
8db9d77b ZW |
3481 | udelay(150); |
3482 | ||
0206e353 | 3483 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3484 | reg = FDI_TX_CTL(pipe); |
3485 | temp = I915_READ(reg); | |
8db9d77b ZW |
3486 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3487 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3488 | I915_WRITE(reg, temp); |
3489 | ||
3490 | POSTING_READ(reg); | |
8db9d77b ZW |
3491 | udelay(500); |
3492 | ||
fa37d39e SP |
3493 | for (retry = 0; retry < 5; retry++) { |
3494 | reg = FDI_RX_IIR(pipe); | |
3495 | temp = I915_READ(reg); | |
3496 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3497 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3498 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3499 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3500 | break; | |
3501 | } | |
3502 | udelay(50); | |
8db9d77b | 3503 | } |
fa37d39e SP |
3504 | if (retry < 5) |
3505 | break; | |
8db9d77b ZW |
3506 | } |
3507 | if (i == 4) | |
5eddb70b | 3508 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3509 | |
3510 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3511 | } | |
3512 | ||
357555c0 JB |
3513 | /* Manual link training for Ivy Bridge A0 parts */ |
3514 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3515 | { | |
3516 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3517 | struct drm_i915_private *dev_priv = to_i915(dev); |
357555c0 JB |
3518 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3519 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3520 | i915_reg_t reg; |
3521 | u32 temp, i, j; | |
357555c0 JB |
3522 | |
3523 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3524 | for train result */ | |
3525 | reg = FDI_RX_IMR(pipe); | |
3526 | temp = I915_READ(reg); | |
3527 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3528 | temp &= ~FDI_RX_BIT_LOCK; | |
3529 | I915_WRITE(reg, temp); | |
3530 | ||
3531 | POSTING_READ(reg); | |
3532 | udelay(150); | |
3533 | ||
01a415fd DV |
3534 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3535 | I915_READ(FDI_RX_IIR(pipe))); | |
3536 | ||
139ccd3f JB |
3537 | /* Try each vswing and preemphasis setting twice before moving on */ |
3538 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3539 | /* disable first in case we need to retry */ | |
3540 | reg = FDI_TX_CTL(pipe); | |
3541 | temp = I915_READ(reg); | |
3542 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3543 | temp &= ~FDI_TX_ENABLE; | |
3544 | I915_WRITE(reg, temp); | |
357555c0 | 3545 | |
139ccd3f JB |
3546 | reg = FDI_RX_CTL(pipe); |
3547 | temp = I915_READ(reg); | |
3548 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3549 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3550 | temp &= ~FDI_RX_ENABLE; | |
3551 | I915_WRITE(reg, temp); | |
357555c0 | 3552 | |
139ccd3f | 3553 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3554 | reg = FDI_TX_CTL(pipe); |
3555 | temp = I915_READ(reg); | |
139ccd3f | 3556 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3557 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3558 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3559 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3560 | temp |= snb_b_fdi_train_param[j/2]; |
3561 | temp |= FDI_COMPOSITE_SYNC; | |
3562 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3563 | |
139ccd3f JB |
3564 | I915_WRITE(FDI_RX_MISC(pipe), |
3565 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3566 | |
139ccd3f | 3567 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3568 | temp = I915_READ(reg); |
139ccd3f JB |
3569 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3570 | temp |= FDI_COMPOSITE_SYNC; | |
3571 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3572 | |
139ccd3f JB |
3573 | POSTING_READ(reg); |
3574 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3575 | |
139ccd3f JB |
3576 | for (i = 0; i < 4; i++) { |
3577 | reg = FDI_RX_IIR(pipe); | |
3578 | temp = I915_READ(reg); | |
3579 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3580 | |
139ccd3f JB |
3581 | if (temp & FDI_RX_BIT_LOCK || |
3582 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3583 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3584 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3585 | i); | |
3586 | break; | |
3587 | } | |
3588 | udelay(1); /* should be 0.5us */ | |
3589 | } | |
3590 | if (i == 4) { | |
3591 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3592 | continue; | |
3593 | } | |
357555c0 | 3594 | |
139ccd3f | 3595 | /* Train 2 */ |
357555c0 JB |
3596 | reg = FDI_TX_CTL(pipe); |
3597 | temp = I915_READ(reg); | |
139ccd3f JB |
3598 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3599 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3600 | I915_WRITE(reg, temp); | |
3601 | ||
3602 | reg = FDI_RX_CTL(pipe); | |
3603 | temp = I915_READ(reg); | |
3604 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3605 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3606 | I915_WRITE(reg, temp); |
3607 | ||
3608 | POSTING_READ(reg); | |
139ccd3f | 3609 | udelay(2); /* should be 1.5us */ |
357555c0 | 3610 | |
139ccd3f JB |
3611 | for (i = 0; i < 4; i++) { |
3612 | reg = FDI_RX_IIR(pipe); | |
3613 | temp = I915_READ(reg); | |
3614 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3615 | |
139ccd3f JB |
3616 | if (temp & FDI_RX_SYMBOL_LOCK || |
3617 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3618 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3619 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3620 | i); | |
3621 | goto train_done; | |
3622 | } | |
3623 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3624 | } |
139ccd3f JB |
3625 | if (i == 4) |
3626 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3627 | } |
357555c0 | 3628 | |
139ccd3f | 3629 | train_done: |
357555c0 JB |
3630 | DRM_DEBUG_KMS("FDI train done.\n"); |
3631 | } | |
3632 | ||
88cefb6c | 3633 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3634 | { |
88cefb6c | 3635 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 3636 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 3637 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3638 | i915_reg_t reg; |
3639 | u32 temp; | |
c64e311e | 3640 | |
c98e9dcf | 3641 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3642 | reg = FDI_RX_CTL(pipe); |
3643 | temp = I915_READ(reg); | |
627eb5a3 | 3644 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3645 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3646 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3647 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3648 | ||
3649 | POSTING_READ(reg); | |
c98e9dcf JB |
3650 | udelay(200); |
3651 | ||
3652 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3653 | temp = I915_READ(reg); |
3654 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3655 | ||
3656 | POSTING_READ(reg); | |
c98e9dcf JB |
3657 | udelay(200); |
3658 | ||
20749730 PZ |
3659 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3660 | reg = FDI_TX_CTL(pipe); | |
3661 | temp = I915_READ(reg); | |
3662 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3663 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3664 | |
20749730 PZ |
3665 | POSTING_READ(reg); |
3666 | udelay(100); | |
6be4a607 | 3667 | } |
0e23b99d JB |
3668 | } |
3669 | ||
88cefb6c DV |
3670 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3671 | { | |
3672 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3673 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 3674 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3675 | i915_reg_t reg; |
3676 | u32 temp; | |
88cefb6c DV |
3677 | |
3678 | /* Switch from PCDclk to Rawclk */ | |
3679 | reg = FDI_RX_CTL(pipe); | |
3680 | temp = I915_READ(reg); | |
3681 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3682 | ||
3683 | /* Disable CPU FDI TX PLL */ | |
3684 | reg = FDI_TX_CTL(pipe); | |
3685 | temp = I915_READ(reg); | |
3686 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3687 | ||
3688 | POSTING_READ(reg); | |
3689 | udelay(100); | |
3690 | ||
3691 | reg = FDI_RX_CTL(pipe); | |
3692 | temp = I915_READ(reg); | |
3693 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3694 | ||
3695 | /* Wait for the clocks to turn off. */ | |
3696 | POSTING_READ(reg); | |
3697 | udelay(100); | |
3698 | } | |
3699 | ||
0fc932b8 JB |
3700 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3701 | { | |
3702 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3703 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
3704 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3705 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3706 | i915_reg_t reg; |
3707 | u32 temp; | |
0fc932b8 JB |
3708 | |
3709 | /* disable CPU FDI tx and PCH FDI rx */ | |
3710 | reg = FDI_TX_CTL(pipe); | |
3711 | temp = I915_READ(reg); | |
3712 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3713 | POSTING_READ(reg); | |
3714 | ||
3715 | reg = FDI_RX_CTL(pipe); | |
3716 | temp = I915_READ(reg); | |
3717 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3718 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3719 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3720 | ||
3721 | POSTING_READ(reg); | |
3722 | udelay(100); | |
3723 | ||
3724 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3725 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3726 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3727 | |
3728 | /* still set train pattern 1 */ | |
3729 | reg = FDI_TX_CTL(pipe); | |
3730 | temp = I915_READ(reg); | |
3731 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3732 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3733 | I915_WRITE(reg, temp); | |
3734 | ||
3735 | reg = FDI_RX_CTL(pipe); | |
3736 | temp = I915_READ(reg); | |
3737 | if (HAS_PCH_CPT(dev)) { | |
3738 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3739 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3740 | } else { | |
3741 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3742 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3743 | } | |
3744 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3745 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3746 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3747 | I915_WRITE(reg, temp); |
3748 | ||
3749 | POSTING_READ(reg); | |
3750 | udelay(100); | |
3751 | } | |
3752 | ||
5dce5b93 CW |
3753 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3754 | { | |
3755 | struct intel_crtc *crtc; | |
3756 | ||
3757 | /* Note that we don't need to be called with mode_config.lock here | |
3758 | * as our list of CRTC objects is static for the lifetime of the | |
3759 | * device and so cannot disappear as we iterate. Similarly, we can | |
3760 | * happily treat the predicates as racy, atomic checks as userspace | |
3761 | * cannot claim and pin a new fb without at least acquring the | |
3762 | * struct_mutex and so serialising with us. | |
3763 | */ | |
d3fcc808 | 3764 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3765 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3766 | continue; | |
3767 | ||
5a21b665 | 3768 | if (crtc->flip_work) |
5dce5b93 CW |
3769 | intel_wait_for_vblank(dev, crtc->pipe); |
3770 | ||
3771 | return true; | |
3772 | } | |
3773 | ||
3774 | return false; | |
3775 | } | |
3776 | ||
5a21b665 | 3777 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
3778 | { |
3779 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
3780 | struct intel_flip_work *work = intel_crtc->flip_work; |
3781 | ||
3782 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
3783 | |
3784 | if (work->event) | |
560ce1dc | 3785 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
3786 | |
3787 | drm_crtc_vblank_put(&intel_crtc->base); | |
3788 | ||
5a21b665 | 3789 | wake_up_all(&dev_priv->pending_flip_queue); |
143f73b3 | 3790 | queue_work(dev_priv->wq, &work->unpin_work); |
5a21b665 DV |
3791 | |
3792 | trace_i915_flip_complete(intel_crtc->plane, | |
3793 | work->pending_flip_obj); | |
d6bbafa1 CW |
3794 | } |
3795 | ||
5008e874 | 3796 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3797 | { |
0f91128d | 3798 | struct drm_device *dev = crtc->dev; |
fac5e23e | 3799 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 | 3800 | long ret; |
e6c3a2a6 | 3801 | |
2c10d571 | 3802 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3803 | |
3804 | ret = wait_event_interruptible_timeout( | |
3805 | dev_priv->pending_flip_queue, | |
3806 | !intel_crtc_has_pending_flip(crtc), | |
3807 | 60*HZ); | |
3808 | ||
3809 | if (ret < 0) | |
3810 | return ret; | |
3811 | ||
5a21b665 DV |
3812 | if (ret == 0) { |
3813 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3814 | struct intel_flip_work *work; | |
3815 | ||
3816 | spin_lock_irq(&dev->event_lock); | |
3817 | work = intel_crtc->flip_work; | |
3818 | if (work && !is_mmio_work(work)) { | |
3819 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3820 | page_flip_completed(intel_crtc); | |
3821 | } | |
3822 | spin_unlock_irq(&dev->event_lock); | |
3823 | } | |
5bb61643 | 3824 | |
5008e874 | 3825 | return 0; |
e6c3a2a6 CW |
3826 | } |
3827 | ||
060f02d8 VS |
3828 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3829 | { | |
3830 | u32 temp; | |
3831 | ||
3832 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3833 | ||
3834 | mutex_lock(&dev_priv->sb_lock); | |
3835 | ||
3836 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3837 | temp |= SBI_SSCCTL_DISABLE; | |
3838 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3839 | ||
3840 | mutex_unlock(&dev_priv->sb_lock); | |
3841 | } | |
3842 | ||
e615efe4 ED |
3843 | /* Program iCLKIP clock to the desired frequency */ |
3844 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3845 | { | |
64b46a06 | 3846 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 3847 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3848 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3849 | u32 temp; | |
3850 | ||
060f02d8 | 3851 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 3852 | |
64b46a06 VS |
3853 | /* The iCLK virtual clock root frequency is in MHz, |
3854 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
3855 | * divisors, it is necessary to divide one by another, so we | |
3856 | * convert the virtual clock precision to KHz here for higher | |
3857 | * precision. | |
3858 | */ | |
3859 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
3860 | u32 iclk_virtual_root_freq = 172800 * 1000; |
3861 | u32 iclk_pi_range = 64; | |
64b46a06 | 3862 | u32 desired_divisor; |
e615efe4 | 3863 | |
64b46a06 VS |
3864 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
3865 | clock << auxdiv); | |
3866 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
3867 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 3868 | |
64b46a06 VS |
3869 | /* |
3870 | * Near 20MHz is a corner case which is | |
3871 | * out of range for the 7-bit divisor | |
3872 | */ | |
3873 | if (divsel <= 0x7f) | |
3874 | break; | |
e615efe4 ED |
3875 | } |
3876 | ||
3877 | /* This should not happen with any sane values */ | |
3878 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3879 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3880 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3881 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3882 | ||
3883 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3884 | clock, |
e615efe4 ED |
3885 | auxdiv, |
3886 | divsel, | |
3887 | phasedir, | |
3888 | phaseinc); | |
3889 | ||
060f02d8 VS |
3890 | mutex_lock(&dev_priv->sb_lock); |
3891 | ||
e615efe4 | 3892 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 3893 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3894 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3895 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3896 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3897 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3898 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3899 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3900 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3901 | |
3902 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3903 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3904 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3905 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3906 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3907 | |
3908 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3909 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3910 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3911 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 3912 | |
060f02d8 VS |
3913 | mutex_unlock(&dev_priv->sb_lock); |
3914 | ||
e615efe4 ED |
3915 | /* Wait for initialization time */ |
3916 | udelay(24); | |
3917 | ||
3918 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
3919 | } | |
3920 | ||
8802e5b6 VS |
3921 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
3922 | { | |
3923 | u32 divsel, phaseinc, auxdiv; | |
3924 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3925 | u32 iclk_pi_range = 64; | |
3926 | u32 desired_divisor; | |
3927 | u32 temp; | |
3928 | ||
3929 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
3930 | return 0; | |
3931 | ||
3932 | mutex_lock(&dev_priv->sb_lock); | |
3933 | ||
3934 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3935 | if (temp & SBI_SSCCTL_DISABLE) { | |
3936 | mutex_unlock(&dev_priv->sb_lock); | |
3937 | return 0; | |
3938 | } | |
3939 | ||
3940 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
3941 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
3942 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
3943 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
3944 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
3945 | ||
3946 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
3947 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
3948 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
3949 | ||
3950 | mutex_unlock(&dev_priv->sb_lock); | |
3951 | ||
3952 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
3953 | ||
3954 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
3955 | desired_divisor << auxdiv); | |
3956 | } | |
3957 | ||
275f01b2 DV |
3958 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3959 | enum pipe pch_transcoder) | |
3960 | { | |
3961 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 3962 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 3963 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
3964 | |
3965 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3966 | I915_READ(HTOTAL(cpu_transcoder))); | |
3967 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3968 | I915_READ(HBLANK(cpu_transcoder))); | |
3969 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3970 | I915_READ(HSYNC(cpu_transcoder))); | |
3971 | ||
3972 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3973 | I915_READ(VTOTAL(cpu_transcoder))); | |
3974 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3975 | I915_READ(VBLANK(cpu_transcoder))); | |
3976 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3977 | I915_READ(VSYNC(cpu_transcoder))); | |
3978 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3979 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3980 | } | |
3981 | ||
003632d9 | 3982 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 3983 | { |
fac5e23e | 3984 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
3985 | uint32_t temp; |
3986 | ||
3987 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 3988 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
3989 | return; |
3990 | ||
3991 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3992 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3993 | ||
003632d9 ACO |
3994 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
3995 | if (enable) | |
3996 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3997 | ||
3998 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
3999 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4000 | POSTING_READ(SOUTH_CHICKEN1); | |
4001 | } | |
4002 | ||
4003 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4004 | { | |
4005 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4006 | |
4007 | switch (intel_crtc->pipe) { | |
4008 | case PIPE_A: | |
4009 | break; | |
4010 | case PIPE_B: | |
6e3c9717 | 4011 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4012 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4013 | else |
003632d9 | 4014 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4015 | |
4016 | break; | |
4017 | case PIPE_C: | |
003632d9 | 4018 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4019 | |
4020 | break; | |
4021 | default: | |
4022 | BUG(); | |
4023 | } | |
4024 | } | |
4025 | ||
c48b5305 VS |
4026 | /* Return which DP Port should be selected for Transcoder DP control */ |
4027 | static enum port | |
4028 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4029 | { | |
4030 | struct drm_device *dev = crtc->dev; | |
4031 | struct intel_encoder *encoder; | |
4032 | ||
4033 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
cca0502b | 4034 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4035 | encoder->type == INTEL_OUTPUT_EDP) |
4036 | return enc_to_dig_port(&encoder->base)->port; | |
4037 | } | |
4038 | ||
4039 | return -1; | |
4040 | } | |
4041 | ||
f67a559d JB |
4042 | /* |
4043 | * Enable PCH resources required for PCH ports: | |
4044 | * - PCH PLLs | |
4045 | * - FDI training & RX/TX | |
4046 | * - update transcoder timings | |
4047 | * - DP transcoding bits | |
4048 | * - transcoder | |
4049 | */ | |
4050 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4051 | { |
4052 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4053 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e23b99d JB |
4054 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4055 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4056 | u32 temp; |
2c07245f | 4057 | |
ab9412ba | 4058 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4059 | |
1fbc0d78 DV |
4060 | if (IS_IVYBRIDGE(dev)) |
4061 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4062 | ||
cd986abb DV |
4063 | /* Write the TU size bits before fdi link training, so that error |
4064 | * detection works. */ | |
4065 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4066 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4067 | ||
c98e9dcf | 4068 | /* For PCH output, training FDI link */ |
674cf967 | 4069 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4070 | |
3ad8a208 DV |
4071 | /* We need to program the right clock selection before writing the pixel |
4072 | * mutliplier into the DPLL. */ | |
303b81e0 | 4073 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4074 | u32 sel; |
4b645f14 | 4075 | |
c98e9dcf | 4076 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4077 | temp |= TRANS_DPLL_ENABLE(pipe); |
4078 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4079 | if (intel_crtc->config->shared_dpll == |
4080 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4081 | temp |= sel; |
4082 | else | |
4083 | temp &= ~sel; | |
c98e9dcf | 4084 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4085 | } |
5eddb70b | 4086 | |
3ad8a208 DV |
4087 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4088 | * transcoder, and we actually should do this to not upset any PCH | |
4089 | * transcoder that already use the clock when we share it. | |
4090 | * | |
4091 | * Note that enable_shared_dpll tries to do the right thing, but | |
4092 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4093 | * the right LVDS enable sequence. */ | |
85b3894f | 4094 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4095 | |
d9b6cb56 JB |
4096 | /* set transcoder timing, panel must allow it */ |
4097 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4098 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4099 | |
303b81e0 | 4100 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4101 | |
c98e9dcf | 4102 | /* For PCH DP, enable TRANS_DP_CTL */ |
37a5650b | 4103 | if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) { |
9c4edaee VS |
4104 | const struct drm_display_mode *adjusted_mode = |
4105 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4106 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4107 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4108 | temp = I915_READ(reg); |
4109 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4110 | TRANS_DP_SYNC_MASK | |
4111 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4112 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4113 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4114 | |
9c4edaee | 4115 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4116 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4117 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4118 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4119 | |
4120 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4121 | case PORT_B: |
5eddb70b | 4122 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4123 | break; |
c48b5305 | 4124 | case PORT_C: |
5eddb70b | 4125 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4126 | break; |
c48b5305 | 4127 | case PORT_D: |
5eddb70b | 4128 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4129 | break; |
4130 | default: | |
e95d41e1 | 4131 | BUG(); |
32f9d658 | 4132 | } |
2c07245f | 4133 | |
5eddb70b | 4134 | I915_WRITE(reg, temp); |
6be4a607 | 4135 | } |
b52eb4dc | 4136 | |
b8a4f404 | 4137 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4138 | } |
4139 | ||
1507e5bd PZ |
4140 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4141 | { | |
4142 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4143 | struct drm_i915_private *dev_priv = to_i915(dev); |
1507e5bd | 4144 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 4145 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4146 | |
ab9412ba | 4147 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4148 | |
8c52b5e8 | 4149 | lpt_program_iclkip(crtc); |
1507e5bd | 4150 | |
0540e488 | 4151 | /* Set transcoder timing. */ |
275f01b2 | 4152 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4153 | |
937bb610 | 4154 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4155 | } |
4156 | ||
a1520318 | 4157 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4158 | { |
fac5e23e | 4159 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4160 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4161 | u32 temp; |
4162 | ||
4163 | temp = I915_READ(dslreg); | |
4164 | udelay(500); | |
4165 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4166 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4167 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4168 | } |
4169 | } | |
4170 | ||
86adf9d7 ML |
4171 | static int |
4172 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4173 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4174 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4175 | { |
86adf9d7 ML |
4176 | struct intel_crtc_scaler_state *scaler_state = |
4177 | &crtc_state->scaler_state; | |
4178 | struct intel_crtc *intel_crtc = | |
4179 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4180 | int need_scaling; |
6156a456 CK |
4181 | |
4182 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4183 | (src_h != dst_w || src_w != dst_h): | |
4184 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4185 | |
4186 | /* | |
4187 | * if plane is being disabled or scaler is no more required or force detach | |
4188 | * - free scaler binded to this plane/crtc | |
4189 | * - in order to do this, update crtc->scaler_usage | |
4190 | * | |
4191 | * Here scaler state in crtc_state is set free so that | |
4192 | * scaler can be assigned to other user. Actual register | |
4193 | * update to free the scaler is done in plane/panel-fit programming. | |
4194 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4195 | */ | |
86adf9d7 | 4196 | if (force_detach || !need_scaling) { |
a1b2278e | 4197 | if (*scaler_id >= 0) { |
86adf9d7 | 4198 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4199 | scaler_state->scalers[*scaler_id].in_use = 0; |
4200 | ||
86adf9d7 ML |
4201 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4202 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4203 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4204 | scaler_state->scaler_users); |
4205 | *scaler_id = -1; | |
4206 | } | |
4207 | return 0; | |
4208 | } | |
4209 | ||
4210 | /* range checks */ | |
4211 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4212 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4213 | ||
4214 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4215 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4216 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4217 | "size is out of scaler range\n", |
86adf9d7 | 4218 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4219 | return -EINVAL; |
4220 | } | |
4221 | ||
86adf9d7 ML |
4222 | /* mark this plane as a scaler user in crtc_state */ |
4223 | scaler_state->scaler_users |= (1 << scaler_user); | |
4224 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4225 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4226 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4227 | scaler_state->scaler_users); | |
4228 | ||
4229 | return 0; | |
4230 | } | |
4231 | ||
4232 | /** | |
4233 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4234 | * | |
4235 | * @state: crtc's scaler state | |
86adf9d7 ML |
4236 | * |
4237 | * Return | |
4238 | * 0 - scaler_usage updated successfully | |
4239 | * error - requested scaling cannot be supported or other error condition | |
4240 | */ | |
e435d6e5 | 4241 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4242 | { |
4243 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4244 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4245 | |
78108b7c VS |
4246 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n", |
4247 | intel_crtc->base.base.id, intel_crtc->base.name, | |
4248 | intel_crtc->pipe, SKL_CRTC_INDEX); | |
86adf9d7 | 4249 | |
e435d6e5 | 4250 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4251 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4252 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4253 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4254 | } |
4255 | ||
4256 | /** | |
4257 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4258 | * | |
4259 | * @state: crtc's scaler state | |
86adf9d7 ML |
4260 | * @plane_state: atomic plane state to update |
4261 | * | |
4262 | * Return | |
4263 | * 0 - scaler_usage updated successfully | |
4264 | * error - requested scaling cannot be supported or other error condition | |
4265 | */ | |
da20eabd ML |
4266 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4267 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4268 | { |
4269 | ||
4270 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4271 | struct intel_plane *intel_plane = |
4272 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4273 | struct drm_framebuffer *fb = plane_state->base.fb; |
4274 | int ret; | |
4275 | ||
4276 | bool force_detach = !fb || !plane_state->visible; | |
4277 | ||
72660ce0 VS |
4278 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n", |
4279 | intel_plane->base.base.id, intel_plane->base.name, | |
4280 | intel_crtc->pipe, drm_plane_index(&intel_plane->base)); | |
86adf9d7 ML |
4281 | |
4282 | ret = skl_update_scaler(crtc_state, force_detach, | |
4283 | drm_plane_index(&intel_plane->base), | |
4284 | &plane_state->scaler_id, | |
4285 | plane_state->base.rotation, | |
4286 | drm_rect_width(&plane_state->src) >> 16, | |
4287 | drm_rect_height(&plane_state->src) >> 16, | |
4288 | drm_rect_width(&plane_state->dst), | |
4289 | drm_rect_height(&plane_state->dst)); | |
4290 | ||
4291 | if (ret || plane_state->scaler_id < 0) | |
4292 | return ret; | |
4293 | ||
a1b2278e | 4294 | /* check colorkey */ |
818ed961 | 4295 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4296 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4297 | intel_plane->base.base.id, | |
4298 | intel_plane->base.name); | |
a1b2278e CK |
4299 | return -EINVAL; |
4300 | } | |
4301 | ||
4302 | /* Check src format */ | |
86adf9d7 ML |
4303 | switch (fb->pixel_format) { |
4304 | case DRM_FORMAT_RGB565: | |
4305 | case DRM_FORMAT_XBGR8888: | |
4306 | case DRM_FORMAT_XRGB8888: | |
4307 | case DRM_FORMAT_ABGR8888: | |
4308 | case DRM_FORMAT_ARGB8888: | |
4309 | case DRM_FORMAT_XRGB2101010: | |
4310 | case DRM_FORMAT_XBGR2101010: | |
4311 | case DRM_FORMAT_YUYV: | |
4312 | case DRM_FORMAT_YVYU: | |
4313 | case DRM_FORMAT_UYVY: | |
4314 | case DRM_FORMAT_VYUY: | |
4315 | break; | |
4316 | default: | |
72660ce0 VS |
4317 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4318 | intel_plane->base.base.id, intel_plane->base.name, | |
4319 | fb->base.id, fb->pixel_format); | |
86adf9d7 | 4320 | return -EINVAL; |
a1b2278e CK |
4321 | } |
4322 | ||
a1b2278e CK |
4323 | return 0; |
4324 | } | |
4325 | ||
e435d6e5 ML |
4326 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4327 | { | |
4328 | int i; | |
4329 | ||
4330 | for (i = 0; i < crtc->num_scalers; i++) | |
4331 | skl_detach_scaler(crtc, i); | |
4332 | } | |
4333 | ||
4334 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4335 | { |
4336 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4337 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4338 | int pipe = crtc->pipe; |
a1b2278e CK |
4339 | struct intel_crtc_scaler_state *scaler_state = |
4340 | &crtc->config->scaler_state; | |
4341 | ||
4342 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4343 | ||
6e3c9717 | 4344 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4345 | int id; |
4346 | ||
4347 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4348 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4349 | return; | |
4350 | } | |
4351 | ||
4352 | id = scaler_state->scaler_id; | |
4353 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4354 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4355 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4356 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4357 | ||
4358 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4359 | } |
4360 | } | |
4361 | ||
b074cec8 JB |
4362 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4363 | { | |
4364 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4365 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4366 | int pipe = crtc->pipe; |
4367 | ||
6e3c9717 | 4368 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4369 | /* Force use of hard-coded filter coefficients |
4370 | * as some pre-programmed values are broken, | |
4371 | * e.g. x201. | |
4372 | */ | |
4373 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4374 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4375 | PF_PIPE_SEL_IVB(pipe)); | |
4376 | else | |
4377 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4378 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4379 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4380 | } |
4381 | } | |
4382 | ||
20bc8673 | 4383 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4384 | { |
cea165c3 | 4385 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4386 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4387 | |
6e3c9717 | 4388 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4389 | return; |
4390 | ||
307e4498 ML |
4391 | /* |
4392 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4393 | * This function is called from post_plane_update, which is run after | |
4394 | * a vblank wait. | |
4395 | */ | |
cea165c3 | 4396 | |
d77e4531 | 4397 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4398 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4399 | mutex_lock(&dev_priv->rps.hw_lock); |
4400 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4401 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4402 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4403 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4404 | * mailbox." Moreover, the mailbox may return a bogus state, |
4405 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4406 | */ |
4407 | } else { | |
4408 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4409 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4410 | * is essentially intel_wait_for_vblank. If we don't have this | |
4411 | * and don't wait for vblanks until the end of crtc_enable, then | |
4412 | * the HW state readout code will complain that the expected | |
4413 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4414 | if (intel_wait_for_register(dev_priv, |
4415 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4416 | 50)) | |
2a114cc1 BW |
4417 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4418 | } | |
d77e4531 PZ |
4419 | } |
4420 | ||
20bc8673 | 4421 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4422 | { |
4423 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4424 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4425 | |
6e3c9717 | 4426 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4427 | return; |
4428 | ||
4429 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4430 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4431 | mutex_lock(&dev_priv->rps.hw_lock); |
4432 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4433 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4434 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4435 | if (intel_wait_for_register(dev_priv, |
4436 | IPS_CTL, IPS_ENABLE, 0, | |
4437 | 42)) | |
23d0b130 | 4438 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4439 | } else { |
2a114cc1 | 4440 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4441 | POSTING_READ(IPS_CTL); |
4442 | } | |
d77e4531 PZ |
4443 | |
4444 | /* We need to wait for a vblank before we can disable the plane. */ | |
4445 | intel_wait_for_vblank(dev, crtc->pipe); | |
4446 | } | |
4447 | ||
7cac945f | 4448 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4449 | { |
7cac945f | 4450 | if (intel_crtc->overlay) { |
d3eedb1a | 4451 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4452 | struct drm_i915_private *dev_priv = to_i915(dev); |
d3eedb1a VS |
4453 | |
4454 | mutex_lock(&dev->struct_mutex); | |
4455 | dev_priv->mm.interruptible = false; | |
4456 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4457 | dev_priv->mm.interruptible = true; | |
4458 | mutex_unlock(&dev->struct_mutex); | |
4459 | } | |
4460 | ||
4461 | /* Let userspace switch the overlay on again. In most cases userspace | |
4462 | * has to recompute where to put it anyway. | |
4463 | */ | |
4464 | } | |
4465 | ||
87d4300a ML |
4466 | /** |
4467 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4468 | * @crtc: the CRTC whose primary plane was just enabled | |
4469 | * | |
4470 | * Performs potentially sleeping operations that must be done after the primary | |
4471 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4472 | * called due to an explicit primary plane update, or due to an implicit | |
4473 | * re-enable that is caused when a sprite plane is updated to no longer | |
4474 | * completely hide the primary plane. | |
4475 | */ | |
4476 | static void | |
4477 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4478 | { |
4479 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4480 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4481 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4482 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4483 | |
87d4300a ML |
4484 | /* |
4485 | * FIXME IPS should be fine as long as one plane is | |
4486 | * enabled, but in practice it seems to have problems | |
4487 | * when going from primary only to sprite only and vice | |
4488 | * versa. | |
4489 | */ | |
a5c4d7bc VS |
4490 | hsw_enable_ips(intel_crtc); |
4491 | ||
f99d7069 | 4492 | /* |
87d4300a ML |
4493 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4494 | * So don't enable underrun reporting before at least some planes | |
4495 | * are enabled. | |
4496 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4497 | * but leave the pipe running. | |
f99d7069 | 4498 | */ |
87d4300a ML |
4499 | if (IS_GEN2(dev)) |
4500 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4501 | ||
aca7b684 VS |
4502 | /* Underruns don't always raise interrupts, so check manually. */ |
4503 | intel_check_cpu_fifo_underruns(dev_priv); | |
4504 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4505 | } |
4506 | ||
2622a081 | 4507 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4508 | static void |
4509 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4510 | { |
4511 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4512 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4513 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4514 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4515 | |
87d4300a ML |
4516 | /* |
4517 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4518 | * So diasble underrun reporting before all the planes get disabled. | |
4519 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4520 | * but leave the pipe running. | |
4521 | */ | |
4522 | if (IS_GEN2(dev)) | |
4523 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4524 | |
2622a081 VS |
4525 | /* |
4526 | * FIXME IPS should be fine as long as one plane is | |
4527 | * enabled, but in practice it seems to have problems | |
4528 | * when going from primary only to sprite only and vice | |
4529 | * versa. | |
4530 | */ | |
4531 | hsw_disable_ips(intel_crtc); | |
4532 | } | |
4533 | ||
4534 | /* FIXME get rid of this and use pre_plane_update */ | |
4535 | static void | |
4536 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4537 | { | |
4538 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4539 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
4540 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4541 | int pipe = intel_crtc->pipe; | |
4542 | ||
4543 | intel_pre_disable_primary(crtc); | |
4544 | ||
87d4300a ML |
4545 | /* |
4546 | * Vblank time updates from the shadow to live plane control register | |
4547 | * are blocked if the memory self-refresh mode is active at that | |
4548 | * moment. So to make sure the plane gets truly disabled, disable | |
4549 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4550 | * will be checked/applied by the HW only at the next frame start | |
4551 | * event which is after the vblank start event, so we need to have a | |
4552 | * wait-for-vblank between disabling the plane and the pipe. | |
4553 | */ | |
262cd2e1 | 4554 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4555 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4556 | dev_priv->wm.vlv.cxsr = false; |
4557 | intel_wait_for_vblank(dev, pipe); | |
4558 | } | |
87d4300a ML |
4559 | } |
4560 | ||
5a21b665 DV |
4561 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
4562 | { | |
4563 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
4564 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
4565 | struct intel_crtc_state *pipe_config = | |
4566 | to_intel_crtc_state(crtc->base.state); | |
4567 | struct drm_device *dev = crtc->base.dev; | |
4568 | struct drm_plane *primary = crtc->base.primary; | |
4569 | struct drm_plane_state *old_pri_state = | |
4570 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4571 | ||
4572 | intel_frontbuffer_flip(dev, pipe_config->fb_bits); | |
4573 | ||
4574 | crtc->wm.cxsr_allowed = true; | |
4575 | ||
4576 | if (pipe_config->update_wm_post && pipe_config->base.active) | |
4577 | intel_update_watermarks(&crtc->base); | |
4578 | ||
4579 | if (old_pri_state) { | |
4580 | struct intel_plane_state *primary_state = | |
4581 | to_intel_plane_state(primary->state); | |
4582 | struct intel_plane_state *old_primary_state = | |
4583 | to_intel_plane_state(old_pri_state); | |
4584 | ||
4585 | intel_fbc_post_update(crtc); | |
4586 | ||
4587 | if (primary_state->visible && | |
4588 | (needs_modeset(&pipe_config->base) || | |
4589 | !old_primary_state->visible)) | |
4590 | intel_post_enable_primary(&crtc->base); | |
4591 | } | |
4592 | } | |
4593 | ||
5c74cd73 | 4594 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4595 | { |
5c74cd73 | 4596 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4597 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4598 | struct drm_i915_private *dev_priv = to_i915(dev); |
ab1d3a0e ML |
4599 | struct intel_crtc_state *pipe_config = |
4600 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4601 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4602 | struct drm_plane *primary = crtc->base.primary; | |
4603 | struct drm_plane_state *old_pri_state = | |
4604 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4605 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4606 | |
5c74cd73 ML |
4607 | if (old_pri_state) { |
4608 | struct intel_plane_state *primary_state = | |
4609 | to_intel_plane_state(primary->state); | |
4610 | struct intel_plane_state *old_primary_state = | |
4611 | to_intel_plane_state(old_pri_state); | |
4612 | ||
faf68d92 | 4613 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 4614 | |
5c74cd73 ML |
4615 | if (old_primary_state->visible && |
4616 | (modeset || !primary_state->visible)) | |
4617 | intel_pre_disable_primary(&crtc->base); | |
4618 | } | |
852eb00d | 4619 | |
a4015f9a | 4620 | if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) { |
852eb00d | 4621 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 4622 | |
2622a081 VS |
4623 | /* |
4624 | * Vblank time updates from the shadow to live plane control register | |
4625 | * are blocked if the memory self-refresh mode is active at that | |
4626 | * moment. So to make sure the plane gets truly disabled, disable | |
4627 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4628 | * will be checked/applied by the HW only at the next frame start | |
4629 | * event which is after the vblank start event, so we need to have a | |
4630 | * wait-for-vblank between disabling the plane and the pipe. | |
4631 | */ | |
4632 | if (old_crtc_state->base.active) { | |
2dfd178d | 4633 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 VS |
4634 | dev_priv->wm.vlv.cxsr = false; |
4635 | intel_wait_for_vblank(dev, crtc->pipe); | |
4636 | } | |
852eb00d | 4637 | } |
92826fcd | 4638 | |
ed4a6a7c MR |
4639 | /* |
4640 | * IVB workaround: must disable low power watermarks for at least | |
4641 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4642 | * when scaling is disabled. | |
4643 | * | |
4644 | * WaCxSRDisabledForSpriteScaling:ivb | |
4645 | */ | |
4646 | if (pipe_config->disable_lp_wm) { | |
4647 | ilk_disable_lp_wm(dev); | |
4648 | intel_wait_for_vblank(dev, crtc->pipe); | |
4649 | } | |
4650 | ||
4651 | /* | |
4652 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4653 | * watermark programming here. | |
4654 | */ | |
4655 | if (needs_modeset(&pipe_config->base)) | |
4656 | return; | |
4657 | ||
4658 | /* | |
4659 | * For platforms that support atomic watermarks, program the | |
4660 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4661 | * will be the intermediate values that are safe for both pre- and | |
4662 | * post- vblank; when vblank happens, the 'active' values will be set | |
4663 | * to the final 'target' values and we'll do this again to get the | |
4664 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4665 | * will be the final target values which will get automatically latched | |
4666 | * at vblank time; no further programming will be necessary. | |
4667 | * | |
4668 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4669 | * we'll continue to update watermarks the old way, if flags tell | |
4670 | * us to. | |
4671 | */ | |
4672 | if (dev_priv->display.initial_watermarks != NULL) | |
4673 | dev_priv->display.initial_watermarks(pipe_config); | |
caed361d | 4674 | else if (pipe_config->update_wm_pre) |
92826fcd | 4675 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4676 | } |
4677 | ||
d032ffa0 | 4678 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4679 | { |
4680 | struct drm_device *dev = crtc->dev; | |
4681 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4682 | struct drm_plane *p; |
87d4300a ML |
4683 | int pipe = intel_crtc->pipe; |
4684 | ||
7cac945f | 4685 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4686 | |
d032ffa0 ML |
4687 | drm_for_each_plane_mask(p, dev, plane_mask) |
4688 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4689 | |
f99d7069 DV |
4690 | /* |
4691 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4692 | * to compute the mask of flip planes precisely. For the time being | |
4693 | * consider this a flip to a NULL plane. | |
4694 | */ | |
4695 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4696 | } |
4697 | ||
f67a559d JB |
4698 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4699 | { | |
4700 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4701 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d | 4702 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4703 | struct intel_encoder *encoder; |
f67a559d | 4704 | int pipe = intel_crtc->pipe; |
b95c5321 ML |
4705 | struct intel_crtc_state *pipe_config = |
4706 | to_intel_crtc_state(crtc->state); | |
f67a559d | 4707 | |
53d9f4e9 | 4708 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4709 | return; |
4710 | ||
b2c0593a VS |
4711 | /* |
4712 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4713 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4714 | * | |
4715 | * On ILK we get an occasional spurious CPU pipe underruns | |
4716 | * between eDP port A enable and vdd enable. Also PCH port | |
4717 | * enable seems to result in the occasional CPU pipe underrun. | |
4718 | * | |
4719 | * Spurious PCH underruns also occur during PCH enabling. | |
4720 | */ | |
4721 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
4722 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
4723 | if (intel_crtc->config->has_pch_encoder) |
4724 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4725 | ||
6e3c9717 | 4726 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4727 | intel_prepare_shared_dpll(intel_crtc); |
4728 | ||
37a5650b | 4729 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 4730 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4731 | |
4732 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 4733 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 4734 | |
6e3c9717 | 4735 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4736 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4737 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4738 | } |
4739 | ||
4740 | ironlake_set_pipeconf(crtc); | |
4741 | ||
f67a559d | 4742 | intel_crtc->active = true; |
8664281b | 4743 | |
f6736a1a | 4744 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4745 | if (encoder->pre_enable) |
4746 | encoder->pre_enable(encoder); | |
f67a559d | 4747 | |
6e3c9717 | 4748 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4749 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4750 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4751 | * enabling. */ | |
88cefb6c | 4752 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4753 | } else { |
4754 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4755 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4756 | } | |
f67a559d | 4757 | |
b074cec8 | 4758 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4759 | |
9c54c0dd JB |
4760 | /* |
4761 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4762 | * clocks enabled | |
4763 | */ | |
b95c5321 | 4764 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 4765 | |
1d5bf5d9 ID |
4766 | if (dev_priv->display.initial_watermarks != NULL) |
4767 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 4768 | intel_enable_pipe(intel_crtc); |
f67a559d | 4769 | |
6e3c9717 | 4770 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4771 | ironlake_pch_enable(crtc); |
c98e9dcf | 4772 | |
f9b61ff6 DV |
4773 | assert_vblank_disabled(crtc); |
4774 | drm_crtc_vblank_on(crtc); | |
4775 | ||
fa5c73b1 DV |
4776 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4777 | encoder->enable(encoder); | |
61b77ddd DV |
4778 | |
4779 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4780 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4781 | |
4782 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4783 | if (intel_crtc->config->has_pch_encoder) | |
4784 | intel_wait_for_vblank(dev, pipe); | |
b2c0593a | 4785 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 4786 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
4787 | } |
4788 | ||
42db64ef PZ |
4789 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4790 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4791 | { | |
f5adf94e | 4792 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4793 | } |
4794 | ||
4f771f10 PZ |
4795 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4796 | { | |
4797 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4798 | struct drm_i915_private *dev_priv = to_i915(dev); |
4f771f10 PZ |
4799 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4800 | struct intel_encoder *encoder; | |
99d736a2 | 4801 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 4802 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
99d736a2 ML |
4803 | struct intel_crtc_state *pipe_config = |
4804 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4805 | |
53d9f4e9 | 4806 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4807 | return; |
4808 | ||
81b088ca VS |
4809 | if (intel_crtc->config->has_pch_encoder) |
4810 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4811 | false); | |
4812 | ||
95a7a2ae ID |
4813 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4814 | if (encoder->pre_pll_enable) | |
4815 | encoder->pre_pll_enable(encoder); | |
4816 | ||
8106ddbd | 4817 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
4818 | intel_enable_shared_dpll(intel_crtc); |
4819 | ||
37a5650b | 4820 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 4821 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 4822 | |
d7edc4e5 | 4823 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
4824 | intel_set_pipe_timings(intel_crtc); |
4825 | ||
bc58be60 | 4826 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 4827 | |
4d1de975 JN |
4828 | if (cpu_transcoder != TRANSCODER_EDP && |
4829 | !transcoder_is_dsi(cpu_transcoder)) { | |
4830 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 4831 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
4832 | } |
4833 | ||
6e3c9717 | 4834 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4835 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4836 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4837 | } |
4838 | ||
d7edc4e5 | 4839 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
4840 | haswell_set_pipeconf(crtc); |
4841 | ||
391bf048 | 4842 | haswell_set_pipemisc(crtc); |
229fca97 | 4843 | |
b95c5321 | 4844 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 4845 | |
4f771f10 | 4846 | intel_crtc->active = true; |
8664281b | 4847 | |
6b698516 DV |
4848 | if (intel_crtc->config->has_pch_encoder) |
4849 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4850 | else | |
4851 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4852 | ||
7d4aefd0 | 4853 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4854 | if (encoder->pre_enable) |
4855 | encoder->pre_enable(encoder); | |
7d4aefd0 | 4856 | } |
4f771f10 | 4857 | |
d2d65408 | 4858 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 4859 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 4860 | |
d7edc4e5 | 4861 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 4862 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4863 | |
1c132b44 | 4864 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 4865 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 4866 | else |
1c132b44 | 4867 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4868 | |
4869 | /* | |
4870 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4871 | * clocks enabled | |
4872 | */ | |
b95c5321 | 4873 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 4874 | |
1f544388 | 4875 | intel_ddi_set_pipe_settings(crtc); |
d7edc4e5 | 4876 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 4877 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4878 | |
1d5bf5d9 ID |
4879 | if (dev_priv->display.initial_watermarks != NULL) |
4880 | dev_priv->display.initial_watermarks(pipe_config); | |
4881 | else | |
4882 | intel_update_watermarks(crtc); | |
4d1de975 JN |
4883 | |
4884 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 4885 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 4886 | intel_enable_pipe(intel_crtc); |
42db64ef | 4887 | |
6e3c9717 | 4888 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4889 | lpt_pch_enable(crtc); |
4f771f10 | 4890 | |
a65347ba | 4891 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4892 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4893 | ||
f9b61ff6 DV |
4894 | assert_vblank_disabled(crtc); |
4895 | drm_crtc_vblank_on(crtc); | |
4896 | ||
8807e55b | 4897 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4898 | encoder->enable(encoder); |
8807e55b JN |
4899 | intel_opregion_notify_encoder(encoder, true); |
4900 | } | |
4f771f10 | 4901 | |
6b698516 DV |
4902 | if (intel_crtc->config->has_pch_encoder) { |
4903 | intel_wait_for_vblank(dev, pipe); | |
4904 | intel_wait_for_vblank(dev, pipe); | |
4905 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
4906 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4907 | true); | |
6b698516 | 4908 | } |
d2d65408 | 4909 | |
e4916946 PZ |
4910 | /* If we change the relative order between pipe/planes enabling, we need |
4911 | * to change the workaround. */ | |
99d736a2 ML |
4912 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
4913 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
4914 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4915 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4916 | } | |
4f771f10 PZ |
4917 | } |
4918 | ||
bfd16b2a | 4919 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
4920 | { |
4921 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4922 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
4923 | int pipe = crtc->pipe; |
4924 | ||
4925 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4926 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 4927 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4928 | I915_WRITE(PF_CTL(pipe), 0); |
4929 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4930 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4931 | } | |
4932 | } | |
4933 | ||
6be4a607 JB |
4934 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4935 | { | |
4936 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4937 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 | 4938 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4939 | struct intel_encoder *encoder; |
6be4a607 | 4940 | int pipe = intel_crtc->pipe; |
b52eb4dc | 4941 | |
b2c0593a VS |
4942 | /* |
4943 | * Sometimes spurious CPU pipe underruns happen when the | |
4944 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
4945 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
4946 | */ | |
4947 | if (intel_crtc->config->has_pch_encoder) { | |
4948 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 4949 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 4950 | } |
37ca8d4c | 4951 | |
ea9d758d DV |
4952 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4953 | encoder->disable(encoder); | |
4954 | ||
f9b61ff6 DV |
4955 | drm_crtc_vblank_off(crtc); |
4956 | assert_vblank_disabled(crtc); | |
4957 | ||
575f7ab7 | 4958 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4959 | |
bfd16b2a | 4960 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 4961 | |
b2c0593a | 4962 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
4963 | ironlake_fdi_disable(crtc); |
4964 | ||
bf49ec8c DV |
4965 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4966 | if (encoder->post_disable) | |
4967 | encoder->post_disable(encoder); | |
2c07245f | 4968 | |
6e3c9717 | 4969 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 4970 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 4971 | |
d925c59a | 4972 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
4973 | i915_reg_t reg; |
4974 | u32 temp; | |
4975 | ||
d925c59a DV |
4976 | /* disable TRANS_DP_CTL */ |
4977 | reg = TRANS_DP_CTL(pipe); | |
4978 | temp = I915_READ(reg); | |
4979 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4980 | TRANS_DP_PORT_SEL_MASK); | |
4981 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4982 | I915_WRITE(reg, temp); | |
4983 | ||
4984 | /* disable DPLL_SEL */ | |
4985 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4986 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4987 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4988 | } |
e3421a18 | 4989 | |
d925c59a DV |
4990 | ironlake_fdi_pll_disable(intel_crtc); |
4991 | } | |
81b088ca | 4992 | |
b2c0593a | 4993 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 4994 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 4995 | } |
1b3c7a47 | 4996 | |
4f771f10 | 4997 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4998 | { |
4f771f10 | 4999 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5000 | struct drm_i915_private *dev_priv = to_i915(dev); |
ee7b9f93 | 5001 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5002 | struct intel_encoder *encoder; |
6e3c9717 | 5003 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5004 | |
d2d65408 VS |
5005 | if (intel_crtc->config->has_pch_encoder) |
5006 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5007 | false); | |
5008 | ||
8807e55b JN |
5009 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5010 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5011 | encoder->disable(encoder); |
8807e55b | 5012 | } |
4f771f10 | 5013 | |
f9b61ff6 DV |
5014 | drm_crtc_vblank_off(crtc); |
5015 | assert_vblank_disabled(crtc); | |
5016 | ||
4d1de975 | 5017 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5018 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5019 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5020 | |
6e3c9717 | 5021 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5022 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5023 | ||
d7edc4e5 | 5024 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5025 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5026 | |
1c132b44 | 5027 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5028 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5029 | else |
bfd16b2a | 5030 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5031 | |
d7edc4e5 | 5032 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5033 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5034 | |
97b040aa ID |
5035 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5036 | if (encoder->post_disable) | |
5037 | encoder->post_disable(encoder); | |
81b088ca | 5038 | |
92966a37 VS |
5039 | if (intel_crtc->config->has_pch_encoder) { |
5040 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5041 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5042 | intel_ddi_fdi_disable(crtc); |
5043 | ||
81b088ca VS |
5044 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5045 | true); | |
92966a37 | 5046 | } |
4f771f10 PZ |
5047 | } |
5048 | ||
2dd24552 JB |
5049 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5050 | { | |
5051 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5052 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5053 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5054 | |
681a8504 | 5055 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5056 | return; |
5057 | ||
2dd24552 | 5058 | /* |
c0b03411 DV |
5059 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5060 | * according to register description and PRM. | |
2dd24552 | 5061 | */ |
c0b03411 DV |
5062 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5063 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5064 | |
b074cec8 JB |
5065 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5066 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5067 | |
5068 | /* Border color in case we don't scale up to the full screen. Black by | |
5069 | * default, change to something else for debugging. */ | |
5070 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5071 | } |
5072 | ||
d05410f9 DA |
5073 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5074 | { | |
5075 | switch (port) { | |
5076 | case PORT_A: | |
6331a704 | 5077 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5078 | case PORT_B: |
6331a704 | 5079 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5080 | case PORT_C: |
6331a704 | 5081 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5082 | case PORT_D: |
6331a704 | 5083 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5084 | case PORT_E: |
6331a704 | 5085 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5086 | default: |
b9fec167 | 5087 | MISSING_CASE(port); |
d05410f9 DA |
5088 | return POWER_DOMAIN_PORT_OTHER; |
5089 | } | |
5090 | } | |
5091 | ||
25f78f58 VS |
5092 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5093 | { | |
5094 | switch (port) { | |
5095 | case PORT_A: | |
5096 | return POWER_DOMAIN_AUX_A; | |
5097 | case PORT_B: | |
5098 | return POWER_DOMAIN_AUX_B; | |
5099 | case PORT_C: | |
5100 | return POWER_DOMAIN_AUX_C; | |
5101 | case PORT_D: | |
5102 | return POWER_DOMAIN_AUX_D; | |
5103 | case PORT_E: | |
5104 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5105 | return POWER_DOMAIN_AUX_D; | |
5106 | default: | |
b9fec167 | 5107 | MISSING_CASE(port); |
25f78f58 VS |
5108 | return POWER_DOMAIN_AUX_A; |
5109 | } | |
5110 | } | |
5111 | ||
319be8ae ID |
5112 | enum intel_display_power_domain |
5113 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5114 | { | |
5115 | struct drm_device *dev = intel_encoder->base.dev; | |
5116 | struct intel_digital_port *intel_dig_port; | |
5117 | ||
5118 | switch (intel_encoder->type) { | |
5119 | case INTEL_OUTPUT_UNKNOWN: | |
5120 | /* Only DDI platforms should ever use this output type */ | |
5121 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
cca0502b | 5122 | case INTEL_OUTPUT_DP: |
319be8ae ID |
5123 | case INTEL_OUTPUT_HDMI: |
5124 | case INTEL_OUTPUT_EDP: | |
5125 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5126 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5127 | case INTEL_OUTPUT_DP_MST: |
5128 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5129 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5130 | case INTEL_OUTPUT_ANALOG: |
5131 | return POWER_DOMAIN_PORT_CRT; | |
5132 | case INTEL_OUTPUT_DSI: | |
5133 | return POWER_DOMAIN_PORT_DSI; | |
5134 | default: | |
5135 | return POWER_DOMAIN_PORT_OTHER; | |
5136 | } | |
5137 | } | |
5138 | ||
25f78f58 VS |
5139 | enum intel_display_power_domain |
5140 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5141 | { | |
5142 | struct drm_device *dev = intel_encoder->base.dev; | |
5143 | struct intel_digital_port *intel_dig_port; | |
5144 | ||
5145 | switch (intel_encoder->type) { | |
5146 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5147 | case INTEL_OUTPUT_HDMI: |
5148 | /* | |
5149 | * Only DDI platforms should ever use these output types. | |
5150 | * We can get here after the HDMI detect code has already set | |
5151 | * the type of the shared encoder. Since we can't be sure | |
5152 | * what's the status of the given connectors, play safe and | |
5153 | * run the DP detection too. | |
5154 | */ | |
25f78f58 | 5155 | WARN_ON_ONCE(!HAS_DDI(dev)); |
cca0502b | 5156 | case INTEL_OUTPUT_DP: |
25f78f58 VS |
5157 | case INTEL_OUTPUT_EDP: |
5158 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5159 | return port_to_aux_power_domain(intel_dig_port->port); | |
5160 | case INTEL_OUTPUT_DP_MST: | |
5161 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5162 | return port_to_aux_power_domain(intel_dig_port->port); | |
5163 | default: | |
b9fec167 | 5164 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5165 | return POWER_DOMAIN_AUX_A; |
5166 | } | |
5167 | } | |
5168 | ||
74bff5f9 ML |
5169 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5170 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5171 | { |
319be8ae | 5172 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5173 | struct drm_encoder *encoder; |
319be8ae ID |
5174 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5175 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5176 | unsigned long mask; |
74bff5f9 | 5177 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5178 | |
74bff5f9 | 5179 | if (!crtc_state->base.active) |
292b990e ML |
5180 | return 0; |
5181 | ||
77d22dca ID |
5182 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5183 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5184 | if (crtc_state->pch_pfit.enabled || |
5185 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5186 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5187 | ||
74bff5f9 ML |
5188 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5189 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5190 | ||
319be8ae | 5191 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5192 | } |
319be8ae | 5193 | |
15e7ec29 ML |
5194 | if (crtc_state->shared_dpll) |
5195 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5196 | ||
77d22dca ID |
5197 | return mask; |
5198 | } | |
5199 | ||
74bff5f9 ML |
5200 | static unsigned long |
5201 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5202 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5203 | { |
fac5e23e | 5204 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5205 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5206 | enum intel_display_power_domain domain; | |
5a21b665 | 5207 | unsigned long domains, new_domains, old_domains; |
77d22dca | 5208 | |
292b990e | 5209 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5210 | intel_crtc->enabled_power_domains = new_domains = |
5211 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5212 | |
5a21b665 | 5213 | domains = new_domains & ~old_domains; |
292b990e ML |
5214 | |
5215 | for_each_power_domain(domain, domains) | |
5216 | intel_display_power_get(dev_priv, domain); | |
5217 | ||
5a21b665 | 5218 | return old_domains & ~new_domains; |
292b990e ML |
5219 | } |
5220 | ||
5221 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5222 | unsigned long domains) | |
5223 | { | |
5224 | enum intel_display_power_domain domain; | |
5225 | ||
5226 | for_each_power_domain(domain, domains) | |
5227 | intel_display_power_put(dev_priv, domain); | |
5228 | } | |
77d22dca | 5229 | |
adafdc6f MK |
5230 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5231 | { | |
5232 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5233 | ||
5234 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5235 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5236 | return max_cdclk_freq; | |
5237 | else if (IS_CHERRYVIEW(dev_priv)) | |
5238 | return max_cdclk_freq*95/100; | |
5239 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5240 | return 2*max_cdclk_freq*90/100; | |
5241 | else | |
5242 | return max_cdclk_freq*90/100; | |
5243 | } | |
5244 | ||
b2045352 VS |
5245 | static int skl_calc_cdclk(int max_pixclk, int vco); |
5246 | ||
560a7ae4 DL |
5247 | static void intel_update_max_cdclk(struct drm_device *dev) |
5248 | { | |
fac5e23e | 5249 | struct drm_i915_private *dev_priv = to_i915(dev); |
560a7ae4 | 5250 | |
ef11bdb3 | 5251 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 | 5252 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
b2045352 VS |
5253 | int max_cdclk, vco; |
5254 | ||
5255 | vco = dev_priv->skl_preferred_vco_freq; | |
63911d72 | 5256 | WARN_ON(vco != 8100000 && vco != 8640000); |
560a7ae4 | 5257 | |
b2045352 VS |
5258 | /* |
5259 | * Use the lower (vco 8640) cdclk values as a | |
5260 | * first guess. skl_calc_cdclk() will correct it | |
5261 | * if the preferred vco is 8100 instead. | |
5262 | */ | |
560a7ae4 | 5263 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
487ed2e4 | 5264 | max_cdclk = 617143; |
560a7ae4 | 5265 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
b2045352 | 5266 | max_cdclk = 540000; |
560a7ae4 | 5267 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
b2045352 | 5268 | max_cdclk = 432000; |
560a7ae4 | 5269 | else |
487ed2e4 | 5270 | max_cdclk = 308571; |
b2045352 VS |
5271 | |
5272 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
281c114f MR |
5273 | } else if (IS_BROXTON(dev)) { |
5274 | dev_priv->max_cdclk_freq = 624000; | |
560a7ae4 DL |
5275 | } else if (IS_BROADWELL(dev)) { |
5276 | /* | |
5277 | * FIXME with extra cooling we can allow | |
5278 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5279 | * How can we know if extra cooling is | |
5280 | * available? PCI ID, VTB, something else? | |
5281 | */ | |
5282 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5283 | dev_priv->max_cdclk_freq = 450000; | |
5284 | else if (IS_BDW_ULX(dev)) | |
5285 | dev_priv->max_cdclk_freq = 450000; | |
5286 | else if (IS_BDW_ULT(dev)) | |
5287 | dev_priv->max_cdclk_freq = 540000; | |
5288 | else | |
5289 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5290 | } else if (IS_CHERRYVIEW(dev)) { |
5291 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5292 | } else if (IS_VALLEYVIEW(dev)) { |
5293 | dev_priv->max_cdclk_freq = 400000; | |
5294 | } else { | |
5295 | /* otherwise assume cdclk is fixed */ | |
5296 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5297 | } | |
5298 | ||
adafdc6f MK |
5299 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5300 | ||
560a7ae4 DL |
5301 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5302 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5303 | |
5304 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5305 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5306 | } |
5307 | ||
5308 | static void intel_update_cdclk(struct drm_device *dev) | |
5309 | { | |
fac5e23e | 5310 | struct drm_i915_private *dev_priv = to_i915(dev); |
560a7ae4 DL |
5311 | |
5312 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
2f2a121a | 5313 | |
83d7c81f | 5314 | if (INTEL_GEN(dev_priv) >= 9) |
709e05c3 VS |
5315 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
5316 | dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, | |
5317 | dev_priv->cdclk_pll.ref); | |
2f2a121a VS |
5318 | else |
5319 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5320 | dev_priv->cdclk_freq); | |
560a7ae4 DL |
5321 | |
5322 | /* | |
b5d99ff9 VS |
5323 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
5324 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
5325 | * of cdclk that generates 4MHz reference clock freq which is used to | |
5326 | * generate GMBus clock. This will vary with the cdclk freq. | |
560a7ae4 | 5327 | */ |
b5d99ff9 | 5328 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
560a7ae4 | 5329 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
560a7ae4 DL |
5330 | } |
5331 | ||
92891e45 VS |
5332 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
5333 | static int skl_cdclk_decimal(int cdclk) | |
5334 | { | |
5335 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
5336 | } | |
5337 | ||
5f199dfa VS |
5338 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
5339 | { | |
5340 | int ratio; | |
5341 | ||
5342 | if (cdclk == dev_priv->cdclk_pll.ref) | |
5343 | return 0; | |
5344 | ||
5345 | switch (cdclk) { | |
5346 | default: | |
5347 | MISSING_CASE(cdclk); | |
5348 | case 144000: | |
5349 | case 288000: | |
5350 | case 384000: | |
5351 | case 576000: | |
5352 | ratio = 60; | |
5353 | break; | |
5354 | case 624000: | |
5355 | ratio = 65; | |
5356 | break; | |
5357 | } | |
5358 | ||
5359 | return dev_priv->cdclk_pll.ref * ratio; | |
5360 | } | |
5361 | ||
2b73001e VS |
5362 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) |
5363 | { | |
5364 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
5365 | ||
5366 | /* Timeout 200us */ | |
95cac283 CW |
5367 | if (intel_wait_for_register(dev_priv, |
5368 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, | |
5369 | 1)) | |
2b73001e | 5370 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); |
83d7c81f VS |
5371 | |
5372 | dev_priv->cdclk_pll.vco = 0; | |
2b73001e VS |
5373 | } |
5374 | ||
5f199dfa | 5375 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) |
2b73001e | 5376 | { |
5f199dfa | 5377 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref); |
2b73001e VS |
5378 | u32 val; |
5379 | ||
5380 | val = I915_READ(BXT_DE_PLL_CTL); | |
5381 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5f199dfa | 5382 | val |= BXT_DE_PLL_RATIO(ratio); |
2b73001e VS |
5383 | I915_WRITE(BXT_DE_PLL_CTL, val); |
5384 | ||
5385 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5386 | ||
5387 | /* Timeout 200us */ | |
e084e1b9 CW |
5388 | if (intel_wait_for_register(dev_priv, |
5389 | BXT_DE_PLL_ENABLE, | |
5390 | BXT_DE_PLL_LOCK, | |
5391 | BXT_DE_PLL_LOCK, | |
5392 | 1)) | |
2b73001e | 5393 | DRM_ERROR("timeout waiting for DE PLL lock\n"); |
83d7c81f | 5394 | |
5f199dfa | 5395 | dev_priv->cdclk_pll.vco = vco; |
2b73001e VS |
5396 | } |
5397 | ||
324513c0 | 5398 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) |
f8437dd1 | 5399 | { |
5f199dfa VS |
5400 | u32 val, divider; |
5401 | int vco, ret; | |
f8437dd1 | 5402 | |
5f199dfa VS |
5403 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
5404 | ||
5405 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); | |
5406 | ||
5407 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ | |
5408 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
5409 | case 8: | |
f8437dd1 | 5410 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
f8437dd1 | 5411 | break; |
5f199dfa | 5412 | case 4: |
f8437dd1 | 5413 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
f8437dd1 | 5414 | break; |
5f199dfa | 5415 | case 3: |
f8437dd1 | 5416 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
f8437dd1 | 5417 | break; |
5f199dfa | 5418 | case 2: |
f8437dd1 | 5419 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
f8437dd1 VK |
5420 | break; |
5421 | default: | |
5f199dfa VS |
5422 | WARN_ON(cdclk != dev_priv->cdclk_pll.ref); |
5423 | WARN_ON(vco != 0); | |
f8437dd1 | 5424 | |
5f199dfa VS |
5425 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
5426 | break; | |
f8437dd1 VK |
5427 | } |
5428 | ||
f8437dd1 | 5429 | /* Inform power controller of upcoming frequency change */ |
5f199dfa | 5430 | mutex_lock(&dev_priv->rps.hw_lock); |
f8437dd1 VK |
5431 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
5432 | 0x80000000); | |
5433 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5434 | ||
5435 | if (ret) { | |
5436 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
9ef56154 | 5437 | ret, cdclk); |
f8437dd1 VK |
5438 | return; |
5439 | } | |
5440 | ||
5f199dfa VS |
5441 | if (dev_priv->cdclk_pll.vco != 0 && |
5442 | dev_priv->cdclk_pll.vco != vco) | |
2b73001e | 5443 | bxt_de_pll_disable(dev_priv); |
f8437dd1 | 5444 | |
5f199dfa VS |
5445 | if (dev_priv->cdclk_pll.vco != vco) |
5446 | bxt_de_pll_enable(dev_priv, vco); | |
f8437dd1 | 5447 | |
5f199dfa VS |
5448 | val = divider | skl_cdclk_decimal(cdclk); |
5449 | /* | |
5450 | * FIXME if only the cd2x divider needs changing, it could be done | |
5451 | * without shutting off the pipe (if only one pipe is active). | |
5452 | */ | |
5453 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
5454 | /* | |
5455 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5456 | * enable otherwise. | |
5457 | */ | |
5458 | if (cdclk >= 500000) | |
5459 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5460 | I915_WRITE(CDCLK_CTL, val); | |
f8437dd1 VK |
5461 | |
5462 | mutex_lock(&dev_priv->rps.hw_lock); | |
5463 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
9ef56154 | 5464 | DIV_ROUND_UP(cdclk, 25000)); |
f8437dd1 VK |
5465 | mutex_unlock(&dev_priv->rps.hw_lock); |
5466 | ||
5467 | if (ret) { | |
5468 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
9ef56154 | 5469 | ret, cdclk); |
f8437dd1 VK |
5470 | return; |
5471 | } | |
5472 | ||
91c8a326 | 5473 | intel_update_cdclk(&dev_priv->drm); |
f8437dd1 VK |
5474 | } |
5475 | ||
d66a2194 | 5476 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5477 | { |
d66a2194 ID |
5478 | u32 cdctl, expected; |
5479 | ||
91c8a326 | 5480 | intel_update_cdclk(&dev_priv->drm); |
f8437dd1 | 5481 | |
d66a2194 ID |
5482 | if (dev_priv->cdclk_pll.vco == 0 || |
5483 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
5484 | goto sanitize; | |
5485 | ||
5486 | /* DPLL okay; verify the cdclock | |
5487 | * | |
5488 | * Some BIOS versions leave an incorrect decimal frequency value and | |
5489 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
5490 | * so sanitize this register. | |
5491 | */ | |
5492 | cdctl = I915_READ(CDCLK_CTL); | |
5493 | /* | |
5494 | * Let's ignore the pipe field, since BIOS could have configured the | |
5495 | * dividers both synching to an active pipe, or asynchronously | |
5496 | * (PIPE_NONE). | |
5497 | */ | |
5498 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
5499 | ||
5500 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
5501 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
5502 | /* | |
5503 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5504 | * enable otherwise. | |
5505 | */ | |
5506 | if (dev_priv->cdclk_freq >= 500000) | |
5507 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5508 | ||
5509 | if (cdctl == expected) | |
5510 | /* All well; nothing to sanitize */ | |
5511 | return; | |
5512 | ||
5513 | sanitize: | |
5514 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
5515 | ||
5516 | /* force cdclk programming */ | |
5517 | dev_priv->cdclk_freq = 0; | |
5518 | ||
5519 | /* force full PLL disable + enable */ | |
5520 | dev_priv->cdclk_pll.vco = -1; | |
5521 | } | |
5522 | ||
324513c0 | 5523 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) |
d66a2194 ID |
5524 | { |
5525 | bxt_sanitize_cdclk(dev_priv); | |
5526 | ||
5527 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) | |
089c6fd5 | 5528 | return; |
c2e001ef | 5529 | |
f8437dd1 VK |
5530 | /* |
5531 | * FIXME: | |
5532 | * - The initial CDCLK needs to be read from VBT. | |
5533 | * Need to make this change after VBT has changes for BXT. | |
f8437dd1 | 5534 | */ |
324513c0 | 5535 | bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0)); |
f8437dd1 VK |
5536 | } |
5537 | ||
324513c0 | 5538 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5539 | { |
324513c0 | 5540 | bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref); |
f8437dd1 VK |
5541 | } |
5542 | ||
a8ca4934 VS |
5543 | static int skl_calc_cdclk(int max_pixclk, int vco) |
5544 | { | |
63911d72 | 5545 | if (vco == 8640000) { |
a8ca4934 | 5546 | if (max_pixclk > 540000) |
487ed2e4 | 5547 | return 617143; |
a8ca4934 VS |
5548 | else if (max_pixclk > 432000) |
5549 | return 540000; | |
487ed2e4 | 5550 | else if (max_pixclk > 308571) |
a8ca4934 VS |
5551 | return 432000; |
5552 | else | |
487ed2e4 | 5553 | return 308571; |
a8ca4934 | 5554 | } else { |
a8ca4934 VS |
5555 | if (max_pixclk > 540000) |
5556 | return 675000; | |
5557 | else if (max_pixclk > 450000) | |
5558 | return 540000; | |
5559 | else if (max_pixclk > 337500) | |
5560 | return 450000; | |
5561 | else | |
5562 | return 337500; | |
5563 | } | |
5564 | } | |
5565 | ||
ea61791e VS |
5566 | static void |
5567 | skl_dpll0_update(struct drm_i915_private *dev_priv) | |
5d96d8af | 5568 | { |
ea61791e | 5569 | u32 val; |
5d96d8af | 5570 | |
709e05c3 | 5571 | dev_priv->cdclk_pll.ref = 24000; |
1c3f7700 | 5572 | dev_priv->cdclk_pll.vco = 0; |
709e05c3 | 5573 | |
ea61791e | 5574 | val = I915_READ(LCPLL1_CTL); |
1c3f7700 | 5575 | if ((val & LCPLL_PLL_ENABLE) == 0) |
ea61791e | 5576 | return; |
5d96d8af | 5577 | |
1c3f7700 ID |
5578 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) |
5579 | return; | |
9f7eb31a | 5580 | |
ea61791e VS |
5581 | val = I915_READ(DPLL_CTRL1); |
5582 | ||
1c3f7700 ID |
5583 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | |
5584 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5585 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
5586 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
5587 | return; | |
9f7eb31a | 5588 | |
ea61791e VS |
5589 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { |
5590 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
5591 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
5592 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
5593 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
63911d72 | 5594 | dev_priv->cdclk_pll.vco = 8100000; |
ea61791e VS |
5595 | break; |
5596 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
5597 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
63911d72 | 5598 | dev_priv->cdclk_pll.vco = 8640000; |
ea61791e VS |
5599 | break; |
5600 | default: | |
5601 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
ea61791e VS |
5602 | break; |
5603 | } | |
5d96d8af DL |
5604 | } |
5605 | ||
b2045352 VS |
5606 | void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) |
5607 | { | |
5608 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
5609 | ||
5610 | dev_priv->skl_preferred_vco_freq = vco; | |
5611 | ||
5612 | if (changed) | |
91c8a326 | 5613 | intel_update_max_cdclk(&dev_priv->drm); |
b2045352 VS |
5614 | } |
5615 | ||
5d96d8af | 5616 | static void |
3861fc60 | 5617 | skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) |
5d96d8af | 5618 | { |
a8ca4934 | 5619 | int min_cdclk = skl_calc_cdclk(0, vco); |
5d96d8af DL |
5620 | u32 val; |
5621 | ||
63911d72 | 5622 | WARN_ON(vco != 8100000 && vco != 8640000); |
b2045352 | 5623 | |
5d96d8af | 5624 | /* select the minimum CDCLK before enabling DPLL 0 */ |
9ef56154 | 5625 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); |
5d96d8af DL |
5626 | I915_WRITE(CDCLK_CTL, val); |
5627 | POSTING_READ(CDCLK_CTL); | |
5628 | ||
5629 | /* | |
5630 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5631 | * taking into account the VCO required to operate the eDP panel at the | |
5632 | * desired frequency. The usual DP link rates operate with a VCO of | |
5633 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5634 | * The modeset code is responsible for the selection of the exact link | |
5635 | * rate later on, with the constraint of choosing a frequency that | |
a8ca4934 | 5636 | * works with vco. |
5d96d8af DL |
5637 | */ |
5638 | val = I915_READ(DPLL_CTRL1); | |
5639 | ||
5640 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5641 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5642 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
63911d72 | 5643 | if (vco == 8640000) |
5d96d8af DL |
5644 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
5645 | SKL_DPLL0); | |
5646 | else | |
5647 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5648 | SKL_DPLL0); | |
5649 | ||
5650 | I915_WRITE(DPLL_CTRL1, val); | |
5651 | POSTING_READ(DPLL_CTRL1); | |
5652 | ||
5653 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5654 | ||
e24ca054 CW |
5655 | if (intel_wait_for_register(dev_priv, |
5656 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
5657 | 5)) | |
5d96d8af | 5658 | DRM_ERROR("DPLL0 not locked\n"); |
1cd593e0 | 5659 | |
63911d72 | 5660 | dev_priv->cdclk_pll.vco = vco; |
b2045352 VS |
5661 | |
5662 | /* We'll want to keep using the current vco from now on. */ | |
5663 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
5d96d8af DL |
5664 | } |
5665 | ||
430e05de VS |
5666 | static void |
5667 | skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
5668 | { | |
5669 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
8ad32a05 CW |
5670 | if (intel_wait_for_register(dev_priv, |
5671 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, | |
5672 | 1)) | |
430e05de | 5673 | DRM_ERROR("Couldn't disable DPLL0\n"); |
1cd593e0 | 5674 | |
63911d72 | 5675 | dev_priv->cdclk_pll.vco = 0; |
430e05de VS |
5676 | } |
5677 | ||
5d96d8af DL |
5678 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
5679 | { | |
5680 | int ret; | |
5681 | u32 val; | |
5682 | ||
5683 | /* inform PCU we want to change CDCLK */ | |
5684 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5685 | mutex_lock(&dev_priv->rps.hw_lock); | |
5686 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5687 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5688 | ||
5689 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5690 | } | |
5691 | ||
5692 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5693 | { | |
848496e5 | 5694 | return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0; |
5d96d8af DL |
5695 | } |
5696 | ||
1cd593e0 | 5697 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) |
5d96d8af | 5698 | { |
91c8a326 | 5699 | struct drm_device *dev = &dev_priv->drm; |
5d96d8af DL |
5700 | u32 freq_select, pcu_ack; |
5701 | ||
1cd593e0 VS |
5702 | WARN_ON((cdclk == 24000) != (vco == 0)); |
5703 | ||
63911d72 | 5704 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); |
5d96d8af DL |
5705 | |
5706 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5707 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5708 | return; | |
5709 | } | |
5710 | ||
5711 | /* set CDCLK_CTL */ | |
9ef56154 | 5712 | switch (cdclk) { |
5d96d8af DL |
5713 | case 450000: |
5714 | case 432000: | |
5715 | freq_select = CDCLK_FREQ_450_432; | |
5716 | pcu_ack = 1; | |
5717 | break; | |
5718 | case 540000: | |
5719 | freq_select = CDCLK_FREQ_540; | |
5720 | pcu_ack = 2; | |
5721 | break; | |
487ed2e4 | 5722 | case 308571: |
5d96d8af DL |
5723 | case 337500: |
5724 | default: | |
5725 | freq_select = CDCLK_FREQ_337_308; | |
5726 | pcu_ack = 0; | |
5727 | break; | |
487ed2e4 | 5728 | case 617143: |
5d96d8af DL |
5729 | case 675000: |
5730 | freq_select = CDCLK_FREQ_675_617; | |
5731 | pcu_ack = 3; | |
5732 | break; | |
5733 | } | |
5734 | ||
63911d72 VS |
5735 | if (dev_priv->cdclk_pll.vco != 0 && |
5736 | dev_priv->cdclk_pll.vco != vco) | |
1cd593e0 VS |
5737 | skl_dpll0_disable(dev_priv); |
5738 | ||
63911d72 | 5739 | if (dev_priv->cdclk_pll.vco != vco) |
1cd593e0 VS |
5740 | skl_dpll0_enable(dev_priv, vco); |
5741 | ||
9ef56154 | 5742 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); |
5d96d8af DL |
5743 | POSTING_READ(CDCLK_CTL); |
5744 | ||
5745 | /* inform PCU of the change */ | |
5746 | mutex_lock(&dev_priv->rps.hw_lock); | |
5747 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5748 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5749 | |
5750 | intel_update_cdclk(dev); | |
5d96d8af DL |
5751 | } |
5752 | ||
9f7eb31a VS |
5753 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
5754 | ||
5d96d8af DL |
5755 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
5756 | { | |
709e05c3 | 5757 | skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); |
5d96d8af DL |
5758 | } |
5759 | ||
5760 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5761 | { | |
9f7eb31a VS |
5762 | int cdclk, vco; |
5763 | ||
5764 | skl_sanitize_cdclk(dev_priv); | |
5d96d8af | 5765 | |
63911d72 | 5766 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) { |
9f7eb31a VS |
5767 | /* |
5768 | * Use the current vco as our initial | |
5769 | * guess as to what the preferred vco is. | |
5770 | */ | |
5771 | if (dev_priv->skl_preferred_vco_freq == 0) | |
5772 | skl_set_preferred_cdclk_vco(dev_priv, | |
63911d72 | 5773 | dev_priv->cdclk_pll.vco); |
70c2c184 | 5774 | return; |
1cd593e0 | 5775 | } |
5d96d8af | 5776 | |
70c2c184 VS |
5777 | vco = dev_priv->skl_preferred_vco_freq; |
5778 | if (vco == 0) | |
63911d72 | 5779 | vco = 8100000; |
70c2c184 | 5780 | cdclk = skl_calc_cdclk(0, vco); |
5d96d8af | 5781 | |
70c2c184 | 5782 | skl_set_cdclk(dev_priv, cdclk, vco); |
5d96d8af DL |
5783 | } |
5784 | ||
9f7eb31a | 5785 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
c73666f3 | 5786 | { |
09492498 | 5787 | uint32_t cdctl, expected; |
c73666f3 | 5788 | |
f1b391a5 SK |
5789 | /* |
5790 | * check if the pre-os intialized the display | |
5791 | * There is SWF18 scratchpad register defined which is set by the | |
5792 | * pre-os which can be used by the OS drivers to check the status | |
5793 | */ | |
5794 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5795 | goto sanitize; | |
5796 | ||
91c8a326 | 5797 | intel_update_cdclk(&dev_priv->drm); |
c73666f3 | 5798 | /* Is PLL enabled and locked ? */ |
1c3f7700 ID |
5799 | if (dev_priv->cdclk_pll.vco == 0 || |
5800 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
c73666f3 SK |
5801 | goto sanitize; |
5802 | ||
5803 | /* DPLL okay; verify the cdclock | |
5804 | * | |
5805 | * Noticed in some instances that the freq selection is correct but | |
5806 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5807 | * enable display. Verify the same as well. | |
5808 | */ | |
09492498 VS |
5809 | cdctl = I915_READ(CDCLK_CTL); |
5810 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
5811 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
5812 | if (cdctl == expected) | |
c73666f3 | 5813 | /* All well; nothing to sanitize */ |
9f7eb31a | 5814 | return; |
c89e39f3 | 5815 | |
9f7eb31a VS |
5816 | sanitize: |
5817 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
c73666f3 | 5818 | |
9f7eb31a VS |
5819 | /* force cdclk programming */ |
5820 | dev_priv->cdclk_freq = 0; | |
5821 | /* force full PLL disable + enable */ | |
63911d72 | 5822 | dev_priv->cdclk_pll.vco = -1; |
c73666f3 SK |
5823 | } |
5824 | ||
30a970c6 JB |
5825 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5826 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5827 | { | |
fac5e23e | 5828 | struct drm_i915_private *dev_priv = to_i915(dev); |
30a970c6 JB |
5829 | u32 val, cmd; |
5830 | ||
164dfd28 VK |
5831 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5832 | != dev_priv->cdclk_freq); | |
d60c4473 | 5833 | |
dfcab17e | 5834 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5835 | cmd = 2; |
dfcab17e | 5836 | else if (cdclk == 266667) |
30a970c6 JB |
5837 | cmd = 1; |
5838 | else | |
5839 | cmd = 0; | |
5840 | ||
5841 | mutex_lock(&dev_priv->rps.hw_lock); | |
5842 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5843 | val &= ~DSPFREQGUAR_MASK; | |
5844 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5845 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5846 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5847 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5848 | 50)) { | |
5849 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5850 | } | |
5851 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5852 | ||
54433e91 VS |
5853 | mutex_lock(&dev_priv->sb_lock); |
5854 | ||
dfcab17e | 5855 | if (cdclk == 400000) { |
6bcda4f0 | 5856 | u32 divider; |
30a970c6 | 5857 | |
6bcda4f0 | 5858 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5859 | |
30a970c6 JB |
5860 | /* adjust cdclk divider */ |
5861 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5862 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5863 | val |= divider; |
5864 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5865 | |
5866 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5867 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5868 | 50)) |
5869 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5870 | } |
5871 | ||
30a970c6 JB |
5872 | /* adjust self-refresh exit latency value */ |
5873 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5874 | val &= ~0x7f; | |
5875 | ||
5876 | /* | |
5877 | * For high bandwidth configs, we set a higher latency in the bunit | |
5878 | * so that the core display fetch happens in time to avoid underruns. | |
5879 | */ | |
dfcab17e | 5880 | if (cdclk == 400000) |
30a970c6 JB |
5881 | val |= 4500 / 250; /* 4.5 usec */ |
5882 | else | |
5883 | val |= 3000 / 250; /* 3.0 usec */ | |
5884 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5885 | |
a580516d | 5886 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5887 | |
b6283055 | 5888 | intel_update_cdclk(dev); |
30a970c6 JB |
5889 | } |
5890 | ||
383c5a6a VS |
5891 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5892 | { | |
fac5e23e | 5893 | struct drm_i915_private *dev_priv = to_i915(dev); |
383c5a6a VS |
5894 | u32 val, cmd; |
5895 | ||
164dfd28 VK |
5896 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5897 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5898 | |
5899 | switch (cdclk) { | |
383c5a6a VS |
5900 | case 333333: |
5901 | case 320000: | |
383c5a6a | 5902 | case 266667: |
383c5a6a | 5903 | case 200000: |
383c5a6a VS |
5904 | break; |
5905 | default: | |
5f77eeb0 | 5906 | MISSING_CASE(cdclk); |
383c5a6a VS |
5907 | return; |
5908 | } | |
5909 | ||
9d0d3fda VS |
5910 | /* |
5911 | * Specs are full of misinformation, but testing on actual | |
5912 | * hardware has shown that we just need to write the desired | |
5913 | * CCK divider into the Punit register. | |
5914 | */ | |
5915 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5916 | ||
383c5a6a VS |
5917 | mutex_lock(&dev_priv->rps.hw_lock); |
5918 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5919 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5920 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5921 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5922 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5923 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5924 | 50)) { | |
5925 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5926 | } | |
5927 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5928 | ||
b6283055 | 5929 | intel_update_cdclk(dev); |
383c5a6a VS |
5930 | } |
5931 | ||
30a970c6 JB |
5932 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5933 | int max_pixclk) | |
5934 | { | |
6bcda4f0 | 5935 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5936 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5937 | |
30a970c6 JB |
5938 | /* |
5939 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5940 | * 200MHz | |
5941 | * 267MHz | |
29dc7ef3 | 5942 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5943 | * 400MHz (VLV only) |
5944 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5945 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5946 | * |
5947 | * We seem to get an unstable or solid color picture at 200MHz. | |
5948 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5949 | * are off. | |
30a970c6 | 5950 | */ |
6cca3195 VS |
5951 | if (!IS_CHERRYVIEW(dev_priv) && |
5952 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5953 | return 400000; |
6cca3195 | 5954 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5955 | return freq_320; |
e37c67a1 | 5956 | else if (max_pixclk > 0) |
dfcab17e | 5957 | return 266667; |
e37c67a1 VS |
5958 | else |
5959 | return 200000; | |
30a970c6 JB |
5960 | } |
5961 | ||
324513c0 | 5962 | static int bxt_calc_cdclk(int max_pixclk) |
f8437dd1 | 5963 | { |
760e1477 | 5964 | if (max_pixclk > 576000) |
f8437dd1 | 5965 | return 624000; |
760e1477 | 5966 | else if (max_pixclk > 384000) |
f8437dd1 | 5967 | return 576000; |
760e1477 | 5968 | else if (max_pixclk > 288000) |
f8437dd1 | 5969 | return 384000; |
760e1477 | 5970 | else if (max_pixclk > 144000) |
f8437dd1 VK |
5971 | return 288000; |
5972 | else | |
5973 | return 144000; | |
5974 | } | |
5975 | ||
e8788cbc | 5976 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
5977 | static int intel_mode_max_pixclk(struct drm_device *dev, |
5978 | struct drm_atomic_state *state) | |
30a970c6 | 5979 | { |
565602d7 | 5980 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 5981 | struct drm_i915_private *dev_priv = to_i915(dev); |
565602d7 ML |
5982 | struct drm_crtc *crtc; |
5983 | struct drm_crtc_state *crtc_state; | |
5984 | unsigned max_pixclk = 0, i; | |
5985 | enum pipe pipe; | |
30a970c6 | 5986 | |
565602d7 ML |
5987 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
5988 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 5989 | |
565602d7 ML |
5990 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5991 | int pixclk = 0; | |
5992 | ||
5993 | if (crtc_state->enable) | |
5994 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 5995 | |
565602d7 | 5996 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
5997 | } |
5998 | ||
565602d7 ML |
5999 | for_each_pipe(dev_priv, pipe) |
6000 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6001 | ||
30a970c6 JB |
6002 | return max_pixclk; |
6003 | } | |
6004 | ||
27c329ed | 6005 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6006 | { |
27c329ed | 6007 | struct drm_device *dev = state->dev; |
fac5e23e | 6008 | struct drm_i915_private *dev_priv = to_i915(dev); |
27c329ed | 6009 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
1a617b77 ML |
6010 | struct intel_atomic_state *intel_state = |
6011 | to_intel_atomic_state(state); | |
30a970c6 | 6012 | |
1a617b77 | 6013 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6014 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6015 | |
1a617b77 ML |
6016 | if (!intel_state->active_crtcs) |
6017 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6018 | ||
27c329ed ML |
6019 | return 0; |
6020 | } | |
304603f4 | 6021 | |
324513c0 | 6022 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
27c329ed | 6023 | { |
4e5ca60f | 6024 | int max_pixclk = ilk_max_pixel_rate(state); |
1a617b77 ML |
6025 | struct intel_atomic_state *intel_state = |
6026 | to_intel_atomic_state(state); | |
85a96e7a | 6027 | |
1a617b77 | 6028 | intel_state->cdclk = intel_state->dev_cdclk = |
324513c0 | 6029 | bxt_calc_cdclk(max_pixclk); |
85a96e7a | 6030 | |
1a617b77 | 6031 | if (!intel_state->active_crtcs) |
324513c0 | 6032 | intel_state->dev_cdclk = bxt_calc_cdclk(0); |
1a617b77 | 6033 | |
27c329ed | 6034 | return 0; |
30a970c6 JB |
6035 | } |
6036 | ||
1e69cd74 VS |
6037 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6038 | { | |
6039 | unsigned int credits, default_credits; | |
6040 | ||
6041 | if (IS_CHERRYVIEW(dev_priv)) | |
6042 | default_credits = PFI_CREDIT(12); | |
6043 | else | |
6044 | default_credits = PFI_CREDIT(8); | |
6045 | ||
bfa7df01 | 6046 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6047 | /* CHV suggested value is 31 or 63 */ |
6048 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6049 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6050 | else |
6051 | credits = PFI_CREDIT(15); | |
6052 | } else { | |
6053 | credits = default_credits; | |
6054 | } | |
6055 | ||
6056 | /* | |
6057 | * WA - write default credits before re-programming | |
6058 | * FIXME: should we also set the resend bit here? | |
6059 | */ | |
6060 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6061 | default_credits); | |
6062 | ||
6063 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6064 | credits | PFI_CREDIT_RESEND); | |
6065 | ||
6066 | /* | |
6067 | * FIXME is this guaranteed to clear | |
6068 | * immediately or should we poll for it? | |
6069 | */ | |
6070 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6071 | } | |
6072 | ||
27c329ed | 6073 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6074 | { |
a821fc46 | 6075 | struct drm_device *dev = old_state->dev; |
fac5e23e | 6076 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 ML |
6077 | struct intel_atomic_state *old_intel_state = |
6078 | to_intel_atomic_state(old_state); | |
6079 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6080 | |
27c329ed ML |
6081 | /* |
6082 | * FIXME: We can end up here with all power domains off, yet | |
6083 | * with a CDCLK frequency other than the minimum. To account | |
6084 | * for this take the PIPE-A power domain, which covers the HW | |
6085 | * blocks needed for the following programming. This can be | |
6086 | * removed once it's guaranteed that we get here either with | |
6087 | * the minimum CDCLK set, or the required power domains | |
6088 | * enabled. | |
6089 | */ | |
6090 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6091 | |
27c329ed ML |
6092 | if (IS_CHERRYVIEW(dev)) |
6093 | cherryview_set_cdclk(dev, req_cdclk); | |
6094 | else | |
6095 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6096 | |
27c329ed | 6097 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6098 | |
27c329ed | 6099 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6100 | } |
6101 | ||
89b667f8 JB |
6102 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6103 | { | |
6104 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6105 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6106 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6107 | struct intel_encoder *encoder; | |
b95c5321 ML |
6108 | struct intel_crtc_state *pipe_config = |
6109 | to_intel_crtc_state(crtc->state); | |
89b667f8 | 6110 | int pipe = intel_crtc->pipe; |
89b667f8 | 6111 | |
53d9f4e9 | 6112 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6113 | return; |
6114 | ||
37a5650b | 6115 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6116 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6117 | |
6118 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6119 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6120 | |
c14b0485 | 6121 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
fac5e23e | 6122 | struct drm_i915_private *dev_priv = to_i915(dev); |
c14b0485 VS |
6123 | |
6124 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6125 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6126 | } | |
6127 | ||
5b18e57c DV |
6128 | i9xx_set_pipeconf(intel_crtc); |
6129 | ||
89b667f8 | 6130 | intel_crtc->active = true; |
89b667f8 | 6131 | |
a72e4c9f | 6132 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6133 | |
89b667f8 JB |
6134 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6135 | if (encoder->pre_pll_enable) | |
6136 | encoder->pre_pll_enable(encoder); | |
6137 | ||
cd2d34d9 VS |
6138 | if (IS_CHERRYVIEW(dev)) { |
6139 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6140 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
6141 | } else { | |
6142 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6143 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
9d556c99 | 6144 | } |
89b667f8 JB |
6145 | |
6146 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6147 | if (encoder->pre_enable) | |
6148 | encoder->pre_enable(encoder); | |
6149 | ||
2dd24552 JB |
6150 | i9xx_pfit_enable(intel_crtc); |
6151 | ||
b95c5321 | 6152 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6153 | |
caed361d | 6154 | intel_update_watermarks(crtc); |
e1fdc473 | 6155 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6156 | |
4b3a9526 VS |
6157 | assert_vblank_disabled(crtc); |
6158 | drm_crtc_vblank_on(crtc); | |
6159 | ||
f9b61ff6 DV |
6160 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6161 | encoder->enable(encoder); | |
89b667f8 JB |
6162 | } |
6163 | ||
f13c2ef3 DV |
6164 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6165 | { | |
6166 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6167 | struct drm_i915_private *dev_priv = to_i915(dev); |
f13c2ef3 | 6168 | |
6e3c9717 ACO |
6169 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6170 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6171 | } |
6172 | ||
0b8765c6 | 6173 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6174 | { |
6175 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6176 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6177 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6178 | struct intel_encoder *encoder; |
b95c5321 ML |
6179 | struct intel_crtc_state *pipe_config = |
6180 | to_intel_crtc_state(crtc->state); | |
cd2d34d9 | 6181 | enum pipe pipe = intel_crtc->pipe; |
79e53945 | 6182 | |
53d9f4e9 | 6183 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6184 | return; |
6185 | ||
f13c2ef3 DV |
6186 | i9xx_set_pll_dividers(intel_crtc); |
6187 | ||
37a5650b | 6188 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6189 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6190 | |
6191 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6192 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6193 | |
5b18e57c DV |
6194 | i9xx_set_pipeconf(intel_crtc); |
6195 | ||
f7abfe8b | 6196 | intel_crtc->active = true; |
6b383a7f | 6197 | |
4a3436e8 | 6198 | if (!IS_GEN2(dev)) |
a72e4c9f | 6199 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6200 | |
9d6d9f19 MK |
6201 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6202 | if (encoder->pre_enable) | |
6203 | encoder->pre_enable(encoder); | |
6204 | ||
f6736a1a DV |
6205 | i9xx_enable_pll(intel_crtc); |
6206 | ||
2dd24552 JB |
6207 | i9xx_pfit_enable(intel_crtc); |
6208 | ||
b95c5321 | 6209 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6210 | |
f37fcc2a | 6211 | intel_update_watermarks(crtc); |
e1fdc473 | 6212 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6213 | |
4b3a9526 VS |
6214 | assert_vblank_disabled(crtc); |
6215 | drm_crtc_vblank_on(crtc); | |
6216 | ||
f9b61ff6 DV |
6217 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6218 | encoder->enable(encoder); | |
0b8765c6 | 6219 | } |
79e53945 | 6220 | |
87476d63 DV |
6221 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6222 | { | |
6223 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6224 | struct drm_i915_private *dev_priv = to_i915(dev); |
87476d63 | 6225 | |
6e3c9717 | 6226 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6227 | return; |
87476d63 | 6228 | |
328d8e82 | 6229 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6230 | |
328d8e82 DV |
6231 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6232 | I915_READ(PFIT_CONTROL)); | |
6233 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6234 | } |
6235 | ||
0b8765c6 JB |
6236 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6237 | { | |
6238 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 6239 | struct drm_i915_private *dev_priv = to_i915(dev); |
0b8765c6 | 6240 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6241 | struct intel_encoder *encoder; |
0b8765c6 | 6242 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6243 | |
6304cd91 VS |
6244 | /* |
6245 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6246 | * wait for planes to fully turn off before disabling the pipe. | |
6247 | */ | |
90e83e53 ACO |
6248 | if (IS_GEN2(dev)) |
6249 | intel_wait_for_vblank(dev, pipe); | |
6304cd91 | 6250 | |
4b3a9526 VS |
6251 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6252 | encoder->disable(encoder); | |
6253 | ||
f9b61ff6 DV |
6254 | drm_crtc_vblank_off(crtc); |
6255 | assert_vblank_disabled(crtc); | |
6256 | ||
575f7ab7 | 6257 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6258 | |
87476d63 | 6259 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6260 | |
89b667f8 JB |
6261 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6262 | if (encoder->post_disable) | |
6263 | encoder->post_disable(encoder); | |
6264 | ||
d7edc4e5 | 6265 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
6266 | if (IS_CHERRYVIEW(dev)) |
6267 | chv_disable_pll(dev_priv, pipe); | |
6268 | else if (IS_VALLEYVIEW(dev)) | |
6269 | vlv_disable_pll(dev_priv, pipe); | |
6270 | else | |
1c4e0274 | 6271 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6272 | } |
0b8765c6 | 6273 | |
d6db995f VS |
6274 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6275 | if (encoder->post_pll_disable) | |
6276 | encoder->post_pll_disable(encoder); | |
6277 | ||
4a3436e8 | 6278 | if (!IS_GEN2(dev)) |
a72e4c9f | 6279 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6280 | } |
6281 | ||
b17d48e2 ML |
6282 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6283 | { | |
842e0307 | 6284 | struct intel_encoder *encoder; |
b17d48e2 ML |
6285 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6286 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6287 | enum intel_display_power_domain domain; | |
6288 | unsigned long domains; | |
6289 | ||
6290 | if (!intel_crtc->active) | |
6291 | return; | |
6292 | ||
a539205a | 6293 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
5a21b665 | 6294 | WARN_ON(intel_crtc->flip_work); |
fc32b1fd | 6295 | |
2622a081 | 6296 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6297 | |
6298 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6299 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6300 | } |
6301 | ||
b17d48e2 | 6302 | dev_priv->display.crtc_disable(crtc); |
842e0307 | 6303 | |
78108b7c VS |
6304 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
6305 | crtc->base.id, crtc->name); | |
842e0307 ML |
6306 | |
6307 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6308 | crtc->state->active = false; | |
37d9078b | 6309 | intel_crtc->active = false; |
842e0307 ML |
6310 | crtc->enabled = false; |
6311 | crtc->state->connector_mask = 0; | |
6312 | crtc->state->encoder_mask = 0; | |
6313 | ||
6314 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6315 | encoder->base.crtc = NULL; | |
6316 | ||
58f9c0bc | 6317 | intel_fbc_disable(intel_crtc); |
37d9078b | 6318 | intel_update_watermarks(crtc); |
1f7457b1 | 6319 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6320 | |
6321 | domains = intel_crtc->enabled_power_domains; | |
6322 | for_each_power_domain(domain, domains) | |
6323 | intel_display_power_put(dev_priv, domain); | |
6324 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6325 | |
6326 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6327 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6328 | } |
6329 | ||
6b72d486 ML |
6330 | /* |
6331 | * turn all crtc's off, but do not adjust state | |
6332 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6333 | */ | |
70e0bd74 | 6334 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6335 | { |
e2c8b870 | 6336 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6337 | struct drm_atomic_state *state; |
e2c8b870 | 6338 | int ret; |
70e0bd74 | 6339 | |
e2c8b870 ML |
6340 | state = drm_atomic_helper_suspend(dev); |
6341 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6342 | if (ret) |
6343 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6344 | else |
6345 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6346 | return ret; |
ee7b9f93 JB |
6347 | } |
6348 | ||
ea5b213a | 6349 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6350 | { |
4ef69c7a | 6351 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6352 | |
ea5b213a CW |
6353 | drm_encoder_cleanup(encoder); |
6354 | kfree(intel_encoder); | |
7e7d76c3 JB |
6355 | } |
6356 | ||
0a91ca29 DV |
6357 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6358 | * internal consistency). */ | |
5a21b665 | 6359 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 6360 | { |
5a21b665 | 6361 | struct drm_crtc *crtc = connector->base.state->crtc; |
35dd3c64 ML |
6362 | |
6363 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6364 | connector->base.base.id, | |
6365 | connector->base.name); | |
6366 | ||
0a91ca29 | 6367 | if (connector->get_hw_state(connector)) { |
e85376cb | 6368 | struct intel_encoder *encoder = connector->encoder; |
5a21b665 | 6369 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6370 | |
35dd3c64 ML |
6371 | I915_STATE_WARN(!crtc, |
6372 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6373 | |
35dd3c64 ML |
6374 | if (!crtc) |
6375 | return; | |
6376 | ||
6377 | I915_STATE_WARN(!crtc->state->active, | |
6378 | "connector is active, but attached crtc isn't\n"); | |
6379 | ||
e85376cb | 6380 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6381 | return; |
6382 | ||
e85376cb | 6383 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6384 | "atomic encoder doesn't match attached encoder\n"); |
6385 | ||
e85376cb | 6386 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6387 | "attached encoder crtc differs from connector crtc\n"); |
6388 | } else { | |
4d688a2a ML |
6389 | I915_STATE_WARN(crtc && crtc->state->active, |
6390 | "attached crtc is active, but connector isn't\n"); | |
5a21b665 | 6391 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
35dd3c64 | 6392 | "best encoder set without crtc!\n"); |
0a91ca29 | 6393 | } |
79e53945 JB |
6394 | } |
6395 | ||
08d9bc92 ACO |
6396 | int intel_connector_init(struct intel_connector *connector) |
6397 | { | |
5350a031 | 6398 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6399 | |
5350a031 | 6400 | if (!connector->base.state) |
08d9bc92 ACO |
6401 | return -ENOMEM; |
6402 | ||
08d9bc92 ACO |
6403 | return 0; |
6404 | } | |
6405 | ||
6406 | struct intel_connector *intel_connector_alloc(void) | |
6407 | { | |
6408 | struct intel_connector *connector; | |
6409 | ||
6410 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6411 | if (!connector) | |
6412 | return NULL; | |
6413 | ||
6414 | if (intel_connector_init(connector) < 0) { | |
6415 | kfree(connector); | |
6416 | return NULL; | |
6417 | } | |
6418 | ||
6419 | return connector; | |
6420 | } | |
6421 | ||
f0947c37 DV |
6422 | /* Simple connector->get_hw_state implementation for encoders that support only |
6423 | * one connector and no cloning and hence the encoder state determines the state | |
6424 | * of the connector. */ | |
6425 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6426 | { |
24929352 | 6427 | enum pipe pipe = 0; |
f0947c37 | 6428 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6429 | |
f0947c37 | 6430 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6431 | } |
6432 | ||
6d293983 | 6433 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6434 | { |
6d293983 ACO |
6435 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6436 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6437 | |
6438 | return 0; | |
6439 | } | |
6440 | ||
6d293983 | 6441 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6442 | struct intel_crtc_state *pipe_config) |
1857e1da | 6443 | { |
6d293983 ACO |
6444 | struct drm_atomic_state *state = pipe_config->base.state; |
6445 | struct intel_crtc *other_crtc; | |
6446 | struct intel_crtc_state *other_crtc_state; | |
6447 | ||
1857e1da DV |
6448 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6449 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6450 | if (pipe_config->fdi_lanes > 4) { | |
6451 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6452 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6453 | return -EINVAL; |
1857e1da DV |
6454 | } |
6455 | ||
bafb6553 | 6456 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6457 | if (pipe_config->fdi_lanes > 2) { |
6458 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6459 | pipe_config->fdi_lanes); | |
6d293983 | 6460 | return -EINVAL; |
1857e1da | 6461 | } else { |
6d293983 | 6462 | return 0; |
1857e1da DV |
6463 | } |
6464 | } | |
6465 | ||
6466 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6467 | return 0; |
1857e1da DV |
6468 | |
6469 | /* Ivybridge 3 pipe is really complicated */ | |
6470 | switch (pipe) { | |
6471 | case PIPE_A: | |
6d293983 | 6472 | return 0; |
1857e1da | 6473 | case PIPE_B: |
6d293983 ACO |
6474 | if (pipe_config->fdi_lanes <= 2) |
6475 | return 0; | |
6476 | ||
6477 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6478 | other_crtc_state = | |
6479 | intel_atomic_get_crtc_state(state, other_crtc); | |
6480 | if (IS_ERR(other_crtc_state)) | |
6481 | return PTR_ERR(other_crtc_state); | |
6482 | ||
6483 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6484 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6485 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6486 | return -EINVAL; |
1857e1da | 6487 | } |
6d293983 | 6488 | return 0; |
1857e1da | 6489 | case PIPE_C: |
251cc67c VS |
6490 | if (pipe_config->fdi_lanes > 2) { |
6491 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6492 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6493 | return -EINVAL; |
251cc67c | 6494 | } |
6d293983 ACO |
6495 | |
6496 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6497 | other_crtc_state = | |
6498 | intel_atomic_get_crtc_state(state, other_crtc); | |
6499 | if (IS_ERR(other_crtc_state)) | |
6500 | return PTR_ERR(other_crtc_state); | |
6501 | ||
6502 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6503 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6504 | return -EINVAL; |
1857e1da | 6505 | } |
6d293983 | 6506 | return 0; |
1857e1da DV |
6507 | default: |
6508 | BUG(); | |
6509 | } | |
6510 | } | |
6511 | ||
e29c22c0 DV |
6512 | #define RETRY 1 |
6513 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6514 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6515 | { |
1857e1da | 6516 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6517 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6518 | int lane, link_bw, fdi_dotclock, ret; |
6519 | bool needs_recompute = false; | |
877d48d5 | 6520 | |
e29c22c0 | 6521 | retry: |
877d48d5 DV |
6522 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6523 | * each output octet as 10 bits. The actual frequency | |
6524 | * is stored as a divider into a 100MHz clock, and the | |
6525 | * mode pixel clock is stored in units of 1KHz. | |
6526 | * Hence the bw of each lane in terms of the mode signal | |
6527 | * is: | |
6528 | */ | |
21a727b3 | 6529 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6530 | |
241bfc38 | 6531 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6532 | |
2bd89a07 | 6533 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6534 | pipe_config->pipe_bpp); |
6535 | ||
6536 | pipe_config->fdi_lanes = lane; | |
6537 | ||
2bd89a07 | 6538 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6539 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6540 | |
e3b247da | 6541 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6542 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
6543 | pipe_config->pipe_bpp -= 2*3; |
6544 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6545 | pipe_config->pipe_bpp); | |
6546 | needs_recompute = true; | |
6547 | pipe_config->bw_constrained = true; | |
6548 | ||
6549 | goto retry; | |
6550 | } | |
6551 | ||
6552 | if (needs_recompute) | |
6553 | return RETRY; | |
6554 | ||
6d293983 | 6555 | return ret; |
877d48d5 DV |
6556 | } |
6557 | ||
8cfb3407 VS |
6558 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6559 | struct intel_crtc_state *pipe_config) | |
6560 | { | |
6561 | if (pipe_config->pipe_bpp > 24) | |
6562 | return false; | |
6563 | ||
6564 | /* HSW can handle pixel rate up to cdclk? */ | |
2d1fe073 | 6565 | if (IS_HASWELL(dev_priv)) |
8cfb3407 VS |
6566 | return true; |
6567 | ||
6568 | /* | |
b432e5cf VS |
6569 | * We compare against max which means we must take |
6570 | * the increased cdclk requirement into account when | |
6571 | * calculating the new cdclk. | |
6572 | * | |
6573 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6574 | */ |
6575 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6576 | dev_priv->max_cdclk_freq * 95 / 100; | |
6577 | } | |
6578 | ||
42db64ef | 6579 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6580 | struct intel_crtc_state *pipe_config) |
42db64ef | 6581 | { |
8cfb3407 | 6582 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6583 | struct drm_i915_private *dev_priv = to_i915(dev); |
8cfb3407 | 6584 | |
d330a953 | 6585 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6586 | hsw_crtc_supports_ips(crtc) && |
6587 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6588 | } |
6589 | ||
39acb4aa VS |
6590 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6591 | { | |
6592 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6593 | ||
6594 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6595 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6596 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6597 | } | |
6598 | ||
a43f6e0f | 6599 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6600 | struct intel_crtc_state *pipe_config) |
79e53945 | 6601 | { |
a43f6e0f | 6602 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6603 | struct drm_i915_private *dev_priv = to_i915(dev); |
7c5f93b0 | 6604 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
f3261156 | 6605 | int clock_limit = dev_priv->max_dotclk_freq; |
89749350 | 6606 | |
cf532bb2 | 6607 | if (INTEL_INFO(dev)->gen < 4) { |
f3261156 | 6608 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6609 | |
6610 | /* | |
39acb4aa | 6611 | * Enable double wide mode when the dot clock |
cf532bb2 | 6612 | * is > 90% of the (display) core speed. |
cf532bb2 | 6613 | */ |
39acb4aa VS |
6614 | if (intel_crtc_supports_double_wide(crtc) && |
6615 | adjusted_mode->crtc_clock > clock_limit) { | |
f3261156 | 6616 | clock_limit = dev_priv->max_dotclk_freq; |
cf532bb2 | 6617 | pipe_config->double_wide = true; |
ad3a4479 | 6618 | } |
f3261156 | 6619 | } |
ad3a4479 | 6620 | |
f3261156 VS |
6621 | if (adjusted_mode->crtc_clock > clock_limit) { |
6622 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6623 | adjusted_mode->crtc_clock, clock_limit, | |
6624 | yesno(pipe_config->double_wide)); | |
6625 | return -EINVAL; | |
2c07245f | 6626 | } |
89749350 | 6627 | |
1d1d0e27 VS |
6628 | /* |
6629 | * Pipe horizontal size must be even in: | |
6630 | * - DVO ganged mode | |
6631 | * - LVDS dual channel mode | |
6632 | * - Double wide pipe | |
6633 | */ | |
2d84d2b3 | 6634 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6635 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6636 | pipe_config->pipe_src_w &= ~1; | |
6637 | ||
8693a824 DL |
6638 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6639 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6640 | */ |
6641 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6642 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6643 | return -EINVAL; |
44f46b42 | 6644 | |
f5adf94e | 6645 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6646 | hsw_compute_ips_config(crtc, pipe_config); |
6647 | ||
877d48d5 | 6648 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6649 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6650 | |
cf5a15be | 6651 | return 0; |
79e53945 JB |
6652 | } |
6653 | ||
1652d19e VS |
6654 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6655 | { | |
6656 | struct drm_i915_private *dev_priv = to_i915(dev); | |
ea61791e | 6657 | uint32_t cdctl; |
1652d19e | 6658 | |
ea61791e | 6659 | skl_dpll0_update(dev_priv); |
1652d19e | 6660 | |
63911d72 | 6661 | if (dev_priv->cdclk_pll.vco == 0) |
709e05c3 | 6662 | return dev_priv->cdclk_pll.ref; |
1652d19e | 6663 | |
ea61791e | 6664 | cdctl = I915_READ(CDCLK_CTL); |
1652d19e | 6665 | |
63911d72 | 6666 | if (dev_priv->cdclk_pll.vco == 8640000) { |
1652d19e VS |
6667 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
6668 | case CDCLK_FREQ_450_432: | |
6669 | return 432000; | |
6670 | case CDCLK_FREQ_337_308: | |
487ed2e4 | 6671 | return 308571; |
ea61791e VS |
6672 | case CDCLK_FREQ_540: |
6673 | return 540000; | |
1652d19e | 6674 | case CDCLK_FREQ_675_617: |
487ed2e4 | 6675 | return 617143; |
1652d19e | 6676 | default: |
ea61791e | 6677 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
6678 | } |
6679 | } else { | |
1652d19e VS |
6680 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
6681 | case CDCLK_FREQ_450_432: | |
6682 | return 450000; | |
6683 | case CDCLK_FREQ_337_308: | |
6684 | return 337500; | |
ea61791e VS |
6685 | case CDCLK_FREQ_540: |
6686 | return 540000; | |
1652d19e VS |
6687 | case CDCLK_FREQ_675_617: |
6688 | return 675000; | |
6689 | default: | |
ea61791e | 6690 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
6691 | } |
6692 | } | |
6693 | ||
709e05c3 | 6694 | return dev_priv->cdclk_pll.ref; |
1652d19e VS |
6695 | } |
6696 | ||
83d7c81f VS |
6697 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv) |
6698 | { | |
6699 | u32 val; | |
6700 | ||
6701 | dev_priv->cdclk_pll.ref = 19200; | |
1c3f7700 | 6702 | dev_priv->cdclk_pll.vco = 0; |
83d7c81f VS |
6703 | |
6704 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1c3f7700 | 6705 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) |
83d7c81f | 6706 | return; |
83d7c81f | 6707 | |
1c3f7700 ID |
6708 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) |
6709 | return; | |
83d7c81f VS |
6710 | |
6711 | val = I915_READ(BXT_DE_PLL_CTL); | |
6712 | dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * | |
6713 | dev_priv->cdclk_pll.ref; | |
6714 | } | |
6715 | ||
acd3f3d3 BP |
6716 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6717 | { | |
6718 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f5986242 VS |
6719 | u32 divider; |
6720 | int div, vco; | |
acd3f3d3 | 6721 | |
83d7c81f VS |
6722 | bxt_de_pll_update(dev_priv); |
6723 | ||
f5986242 VS |
6724 | vco = dev_priv->cdclk_pll.vco; |
6725 | if (vco == 0) | |
6726 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 | 6727 | |
f5986242 | 6728 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; |
acd3f3d3 | 6729 | |
f5986242 | 6730 | switch (divider) { |
acd3f3d3 | 6731 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
f5986242 VS |
6732 | div = 2; |
6733 | break; | |
acd3f3d3 | 6734 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
f5986242 VS |
6735 | div = 3; |
6736 | break; | |
acd3f3d3 | 6737 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
f5986242 VS |
6738 | div = 4; |
6739 | break; | |
acd3f3d3 | 6740 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
f5986242 VS |
6741 | div = 8; |
6742 | break; | |
6743 | default: | |
6744 | MISSING_CASE(divider); | |
6745 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 BP |
6746 | } |
6747 | ||
f5986242 | 6748 | return DIV_ROUND_CLOSEST(vco, div); |
acd3f3d3 BP |
6749 | } |
6750 | ||
1652d19e VS |
6751 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6752 | { | |
fac5e23e | 6753 | struct drm_i915_private *dev_priv = to_i915(dev); |
1652d19e VS |
6754 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
6755 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6756 | ||
6757 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6758 | return 800000; | |
6759 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6760 | return 450000; | |
6761 | else if (freq == LCPLL_CLK_FREQ_450) | |
6762 | return 450000; | |
6763 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6764 | return 540000; | |
6765 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6766 | return 337500; | |
6767 | else | |
6768 | return 675000; | |
6769 | } | |
6770 | ||
6771 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6772 | { | |
fac5e23e | 6773 | struct drm_i915_private *dev_priv = to_i915(dev); |
1652d19e VS |
6774 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
6775 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6776 | ||
6777 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6778 | return 800000; | |
6779 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6780 | return 450000; | |
6781 | else if (freq == LCPLL_CLK_FREQ_450) | |
6782 | return 450000; | |
6783 | else if (IS_HSW_ULT(dev)) | |
6784 | return 337500; | |
6785 | else | |
6786 | return 540000; | |
79e53945 JB |
6787 | } |
6788 | ||
25eb05fc JB |
6789 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6790 | { | |
bfa7df01 VS |
6791 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6792 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6793 | } |
6794 | ||
b37a6434 VS |
6795 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6796 | { | |
6797 | return 450000; | |
6798 | } | |
6799 | ||
e70236a8 JB |
6800 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6801 | { | |
6802 | return 400000; | |
6803 | } | |
79e53945 | 6804 | |
e70236a8 | 6805 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6806 | { |
e907f170 | 6807 | return 333333; |
e70236a8 | 6808 | } |
79e53945 | 6809 | |
e70236a8 JB |
6810 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6811 | { | |
6812 | return 200000; | |
6813 | } | |
79e53945 | 6814 | |
257a7ffc DV |
6815 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6816 | { | |
6817 | u16 gcfgc = 0; | |
6818 | ||
6819 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6820 | ||
6821 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6822 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6823 | return 266667; |
257a7ffc | 6824 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6825 | return 333333; |
257a7ffc | 6826 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6827 | return 444444; |
257a7ffc DV |
6828 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6829 | return 200000; | |
6830 | default: | |
6831 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6832 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6833 | return 133333; |
257a7ffc | 6834 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6835 | return 166667; |
257a7ffc DV |
6836 | } |
6837 | } | |
6838 | ||
e70236a8 JB |
6839 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6840 | { | |
6841 | u16 gcfgc = 0; | |
79e53945 | 6842 | |
e70236a8 JB |
6843 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6844 | ||
6845 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6846 | return 133333; |
e70236a8 JB |
6847 | else { |
6848 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6849 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6850 | return 333333; |
e70236a8 JB |
6851 | default: |
6852 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6853 | return 190000; | |
79e53945 | 6854 | } |
e70236a8 JB |
6855 | } |
6856 | } | |
6857 | ||
6858 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6859 | { | |
e907f170 | 6860 | return 266667; |
e70236a8 JB |
6861 | } |
6862 | ||
1b1d2716 | 6863 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6864 | { |
6865 | u16 hpllcc = 0; | |
1b1d2716 | 6866 | |
65cd2b3f VS |
6867 | /* |
6868 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6869 | * encoding is different :( | |
6870 | * FIXME is this the right way to detect 852GM/852GMV? | |
6871 | */ | |
6872 | if (dev->pdev->revision == 0x1) | |
6873 | return 133333; | |
6874 | ||
1b1d2716 VS |
6875 | pci_bus_read_config_word(dev->pdev->bus, |
6876 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6877 | ||
e70236a8 JB |
6878 | /* Assume that the hardware is in the high speed state. This |
6879 | * should be the default. | |
6880 | */ | |
6881 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6882 | case GC_CLOCK_133_200: | |
1b1d2716 | 6883 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6884 | case GC_CLOCK_100_200: |
6885 | return 200000; | |
6886 | case GC_CLOCK_166_250: | |
6887 | return 250000; | |
6888 | case GC_CLOCK_100_133: | |
e907f170 | 6889 | return 133333; |
1b1d2716 VS |
6890 | case GC_CLOCK_133_266: |
6891 | case GC_CLOCK_133_266_2: | |
6892 | case GC_CLOCK_166_266: | |
6893 | return 266667; | |
e70236a8 | 6894 | } |
79e53945 | 6895 | |
e70236a8 JB |
6896 | /* Shouldn't happen */ |
6897 | return 0; | |
6898 | } | |
79e53945 | 6899 | |
e70236a8 JB |
6900 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6901 | { | |
e907f170 | 6902 | return 133333; |
79e53945 JB |
6903 | } |
6904 | ||
34edce2f VS |
6905 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6906 | { | |
fac5e23e | 6907 | struct drm_i915_private *dev_priv = to_i915(dev); |
34edce2f VS |
6908 | static const unsigned int blb_vco[8] = { |
6909 | [0] = 3200000, | |
6910 | [1] = 4000000, | |
6911 | [2] = 5333333, | |
6912 | [3] = 4800000, | |
6913 | [4] = 6400000, | |
6914 | }; | |
6915 | static const unsigned int pnv_vco[8] = { | |
6916 | [0] = 3200000, | |
6917 | [1] = 4000000, | |
6918 | [2] = 5333333, | |
6919 | [3] = 4800000, | |
6920 | [4] = 2666667, | |
6921 | }; | |
6922 | static const unsigned int cl_vco[8] = { | |
6923 | [0] = 3200000, | |
6924 | [1] = 4000000, | |
6925 | [2] = 5333333, | |
6926 | [3] = 6400000, | |
6927 | [4] = 3333333, | |
6928 | [5] = 3566667, | |
6929 | [6] = 4266667, | |
6930 | }; | |
6931 | static const unsigned int elk_vco[8] = { | |
6932 | [0] = 3200000, | |
6933 | [1] = 4000000, | |
6934 | [2] = 5333333, | |
6935 | [3] = 4800000, | |
6936 | }; | |
6937 | static const unsigned int ctg_vco[8] = { | |
6938 | [0] = 3200000, | |
6939 | [1] = 4000000, | |
6940 | [2] = 5333333, | |
6941 | [3] = 6400000, | |
6942 | [4] = 2666667, | |
6943 | [5] = 4266667, | |
6944 | }; | |
6945 | const unsigned int *vco_table; | |
6946 | unsigned int vco; | |
6947 | uint8_t tmp = 0; | |
6948 | ||
6949 | /* FIXME other chipsets? */ | |
6950 | if (IS_GM45(dev)) | |
6951 | vco_table = ctg_vco; | |
6952 | else if (IS_G4X(dev)) | |
6953 | vco_table = elk_vco; | |
6954 | else if (IS_CRESTLINE(dev)) | |
6955 | vco_table = cl_vco; | |
6956 | else if (IS_PINEVIEW(dev)) | |
6957 | vco_table = pnv_vco; | |
6958 | else if (IS_G33(dev)) | |
6959 | vco_table = blb_vco; | |
6960 | else | |
6961 | return 0; | |
6962 | ||
6963 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
6964 | ||
6965 | vco = vco_table[tmp & 0x7]; | |
6966 | if (vco == 0) | |
6967 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
6968 | else | |
6969 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
6970 | ||
6971 | return vco; | |
6972 | } | |
6973 | ||
6974 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
6975 | { | |
6976 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6977 | uint16_t tmp = 0; | |
6978 | ||
6979 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6980 | ||
6981 | cdclk_sel = (tmp >> 12) & 0x1; | |
6982 | ||
6983 | switch (vco) { | |
6984 | case 2666667: | |
6985 | case 4000000: | |
6986 | case 5333333: | |
6987 | return cdclk_sel ? 333333 : 222222; | |
6988 | case 3200000: | |
6989 | return cdclk_sel ? 320000 : 228571; | |
6990 | default: | |
6991 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
6992 | return 222222; | |
6993 | } | |
6994 | } | |
6995 | ||
6996 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
6997 | { | |
6998 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
6999 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7000 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7001 | const uint8_t *div_table; | |
7002 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7003 | uint16_t tmp = 0; | |
7004 | ||
7005 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7006 | ||
7007 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7008 | ||
7009 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7010 | goto fail; | |
7011 | ||
7012 | switch (vco) { | |
7013 | case 3200000: | |
7014 | div_table = div_3200; | |
7015 | break; | |
7016 | case 4000000: | |
7017 | div_table = div_4000; | |
7018 | break; | |
7019 | case 5333333: | |
7020 | div_table = div_5333; | |
7021 | break; | |
7022 | default: | |
7023 | goto fail; | |
7024 | } | |
7025 | ||
7026 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7027 | ||
caf4e252 | 7028 | fail: |
34edce2f VS |
7029 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7030 | return 200000; | |
7031 | } | |
7032 | ||
7033 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7034 | { | |
7035 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7036 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7037 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7038 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7039 | const uint8_t *div_table; | |
7040 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7041 | uint16_t tmp = 0; | |
7042 | ||
7043 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7044 | ||
7045 | cdclk_sel = (tmp >> 4) & 0x7; | |
7046 | ||
7047 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7048 | goto fail; | |
7049 | ||
7050 | switch (vco) { | |
7051 | case 3200000: | |
7052 | div_table = div_3200; | |
7053 | break; | |
7054 | case 4000000: | |
7055 | div_table = div_4000; | |
7056 | break; | |
7057 | case 4800000: | |
7058 | div_table = div_4800; | |
7059 | break; | |
7060 | case 5333333: | |
7061 | div_table = div_5333; | |
7062 | break; | |
7063 | default: | |
7064 | goto fail; | |
7065 | } | |
7066 | ||
7067 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7068 | ||
caf4e252 | 7069 | fail: |
34edce2f VS |
7070 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7071 | return 190476; | |
7072 | } | |
7073 | ||
2c07245f | 7074 | static void |
a65851af | 7075 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7076 | { |
a65851af VS |
7077 | while (*num > DATA_LINK_M_N_MASK || |
7078 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7079 | *num >>= 1; |
7080 | *den >>= 1; | |
7081 | } | |
7082 | } | |
7083 | ||
a65851af VS |
7084 | static void compute_m_n(unsigned int m, unsigned int n, |
7085 | uint32_t *ret_m, uint32_t *ret_n) | |
7086 | { | |
7087 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7088 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7089 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7090 | } | |
7091 | ||
e69d0bc1 DV |
7092 | void |
7093 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7094 | int pixel_clock, int link_clock, | |
7095 | struct intel_link_m_n *m_n) | |
2c07245f | 7096 | { |
e69d0bc1 | 7097 | m_n->tu = 64; |
a65851af VS |
7098 | |
7099 | compute_m_n(bits_per_pixel * pixel_clock, | |
7100 | link_clock * nlanes * 8, | |
7101 | &m_n->gmch_m, &m_n->gmch_n); | |
7102 | ||
7103 | compute_m_n(pixel_clock, link_clock, | |
7104 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7105 | } |
7106 | ||
a7615030 CW |
7107 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7108 | { | |
d330a953 JN |
7109 | if (i915.panel_use_ssc >= 0) |
7110 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7111 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7112 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7113 | } |
7114 | ||
7429e9d4 | 7115 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7116 | { |
7df00d7a | 7117 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7118 | } |
f47709a9 | 7119 | |
7429e9d4 DV |
7120 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7121 | { | |
7122 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7123 | } |
7124 | ||
f47709a9 | 7125 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7126 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 7127 | struct dpll *reduced_clock) |
a7516a05 | 7128 | { |
f47709a9 | 7129 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7130 | u32 fp, fp2 = 0; |
7131 | ||
7132 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7133 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7134 | if (reduced_clock) |
7429e9d4 | 7135 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7136 | } else { |
190f68c5 | 7137 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7138 | if (reduced_clock) |
7429e9d4 | 7139 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7140 | } |
7141 | ||
190f68c5 | 7142 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7143 | |
f47709a9 | 7144 | crtc->lowfreq_avail = false; |
2d84d2b3 | 7145 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7146 | reduced_clock) { |
190f68c5 | 7147 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7148 | crtc->lowfreq_avail = true; |
a7516a05 | 7149 | } else { |
190f68c5 | 7150 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7151 | } |
7152 | } | |
7153 | ||
5e69f97f CML |
7154 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7155 | pipe) | |
89b667f8 JB |
7156 | { |
7157 | u32 reg_val; | |
7158 | ||
7159 | /* | |
7160 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7161 | * and set it to a reasonable value instead. | |
7162 | */ | |
ab3c759a | 7163 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7164 | reg_val &= 0xffffff00; |
7165 | reg_val |= 0x00000030; | |
ab3c759a | 7166 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7167 | |
ab3c759a | 7168 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7169 | reg_val &= 0x8cffffff; |
7170 | reg_val = 0x8c000000; | |
ab3c759a | 7171 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7172 | |
ab3c759a | 7173 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7174 | reg_val &= 0xffffff00; |
ab3c759a | 7175 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7176 | |
ab3c759a | 7177 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7178 | reg_val &= 0x00ffffff; |
7179 | reg_val |= 0xb0000000; | |
ab3c759a | 7180 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7181 | } |
7182 | ||
b551842d DV |
7183 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7184 | struct intel_link_m_n *m_n) | |
7185 | { | |
7186 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7187 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
7188 | int pipe = crtc->pipe; |
7189 | ||
e3b95f1e DV |
7190 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7191 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7192 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7193 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7194 | } |
7195 | ||
7196 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7197 | struct intel_link_m_n *m_n, |
7198 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7199 | { |
7200 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7201 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d | 7202 | int pipe = crtc->pipe; |
6e3c9717 | 7203 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7204 | |
7205 | if (INTEL_INFO(dev)->gen >= 5) { | |
7206 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7207 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7208 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7209 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7210 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7211 | * for gen < 8) and if DRRS is supported (to make sure the | |
7212 | * registers are not unnecessarily accessed). | |
7213 | */ | |
44395bfe | 7214 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7215 | crtc->config->has_drrs) { |
f769cd24 VK |
7216 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7217 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7218 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7219 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7220 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7221 | } | |
b551842d | 7222 | } else { |
e3b95f1e DV |
7223 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7224 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7225 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7226 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7227 | } |
7228 | } | |
7229 | ||
fe3cd48d | 7230 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7231 | { |
fe3cd48d R |
7232 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7233 | ||
7234 | if (m_n == M1_N1) { | |
7235 | dp_m_n = &crtc->config->dp_m_n; | |
7236 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7237 | } else if (m_n == M2_N2) { | |
7238 | ||
7239 | /* | |
7240 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7241 | * needs to be programmed into M1_N1. | |
7242 | */ | |
7243 | dp_m_n = &crtc->config->dp_m2_n2; | |
7244 | } else { | |
7245 | DRM_ERROR("Unsupported divider value\n"); | |
7246 | return; | |
7247 | } | |
7248 | ||
6e3c9717 ACO |
7249 | if (crtc->config->has_pch_encoder) |
7250 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7251 | else |
fe3cd48d | 7252 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7253 | } |
7254 | ||
251ac862 DV |
7255 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7256 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 7257 | { |
03ed5cbf | 7258 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 7259 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7260 | if (crtc->pipe != PIPE_A) |
7261 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 7262 | |
cd2d34d9 | 7263 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7264 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7265 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
7266 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7267 | ||
03ed5cbf VS |
7268 | pipe_config->dpll_hw_state.dpll_md = |
7269 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7270 | } | |
bdd4b6a6 | 7271 | |
03ed5cbf VS |
7272 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7273 | struct intel_crtc_state *pipe_config) | |
7274 | { | |
7275 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 7276 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7277 | if (crtc->pipe != PIPE_A) |
7278 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7279 | ||
cd2d34d9 | 7280 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7281 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7282 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
7283 | ||
03ed5cbf VS |
7284 | pipe_config->dpll_hw_state.dpll_md = |
7285 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
7286 | } |
7287 | ||
d288f65f | 7288 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7289 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7290 | { |
f47709a9 | 7291 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7292 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7293 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 7294 | u32 mdiv; |
a0c4da24 | 7295 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7296 | u32 coreclk, reg_val; |
a0c4da24 | 7297 | |
cd2d34d9 VS |
7298 | /* Enable Refclk */ |
7299 | I915_WRITE(DPLL(pipe), | |
7300 | pipe_config->dpll_hw_state.dpll & | |
7301 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
7302 | ||
7303 | /* No need to actually set up the DPLL with DSI */ | |
7304 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7305 | return; | |
7306 | ||
a580516d | 7307 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7308 | |
d288f65f VS |
7309 | bestn = pipe_config->dpll.n; |
7310 | bestm1 = pipe_config->dpll.m1; | |
7311 | bestm2 = pipe_config->dpll.m2; | |
7312 | bestp1 = pipe_config->dpll.p1; | |
7313 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7314 | |
89b667f8 JB |
7315 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7316 | ||
7317 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7318 | if (pipe == PIPE_B) |
5e69f97f | 7319 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7320 | |
7321 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7322 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7323 | |
7324 | /* Disable target IRef on PLL */ | |
ab3c759a | 7325 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7326 | reg_val &= 0x00ffffff; |
ab3c759a | 7327 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7328 | |
7329 | /* Disable fast lock */ | |
ab3c759a | 7330 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7331 | |
7332 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7333 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7334 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7335 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7336 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7337 | |
7338 | /* | |
7339 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7340 | * but we don't support that). | |
7341 | * Note: don't use the DAC post divider as it seems unstable. | |
7342 | */ | |
7343 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7344 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7345 | |
a0c4da24 | 7346 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7347 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7348 | |
89b667f8 | 7349 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7350 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
7351 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
7352 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7353 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7354 | 0x009f0003); |
89b667f8 | 7355 | else |
ab3c759a | 7356 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7357 | 0x00d0000f); |
7358 | ||
37a5650b | 7359 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 7360 | /* Use SSC source */ |
bdd4b6a6 | 7361 | if (pipe == PIPE_A) |
ab3c759a | 7362 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7363 | 0x0df40000); |
7364 | else | |
ab3c759a | 7365 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7366 | 0x0df70000); |
7367 | } else { /* HDMI or VGA */ | |
7368 | /* Use bend source */ | |
bdd4b6a6 | 7369 | if (pipe == PIPE_A) |
ab3c759a | 7370 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7371 | 0x0df70000); |
7372 | else | |
ab3c759a | 7373 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7374 | 0x0df40000); |
7375 | } | |
a0c4da24 | 7376 | |
ab3c759a | 7377 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7378 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 7379 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 7380 | coreclk |= 0x01000000; |
ab3c759a | 7381 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7382 | |
ab3c759a | 7383 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7384 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7385 | } |
7386 | ||
d288f65f | 7387 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7388 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7389 | { |
7390 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7391 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7392 | enum pipe pipe = crtc->pipe; |
9d556c99 | 7393 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7394 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7395 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7396 | u32 dpio_val; |
9cbe40c1 | 7397 | int vco; |
9d556c99 | 7398 | |
cd2d34d9 VS |
7399 | /* Enable Refclk and SSC */ |
7400 | I915_WRITE(DPLL(pipe), | |
7401 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
7402 | ||
7403 | /* No need to actually set up the DPLL with DSI */ | |
7404 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7405 | return; | |
7406 | ||
d288f65f VS |
7407 | bestn = pipe_config->dpll.n; |
7408 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7409 | bestm1 = pipe_config->dpll.m1; | |
7410 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7411 | bestp1 = pipe_config->dpll.p1; | |
7412 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7413 | vco = pipe_config->dpll.vco; |
a945ce7e | 7414 | dpio_val = 0; |
9cbe40c1 | 7415 | loopfilter = 0; |
9d556c99 | 7416 | |
a580516d | 7417 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7418 | |
9d556c99 CML |
7419 | /* p1 and p2 divider */ |
7420 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7421 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7422 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7423 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7424 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7425 | ||
7426 | /* Feedback post-divider - m2 */ | |
7427 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7428 | ||
7429 | /* Feedback refclk divider - n and m1 */ | |
7430 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7431 | DPIO_CHV_M1_DIV_BY_2 | | |
7432 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7433 | ||
7434 | /* M2 fraction division */ | |
25a25dfc | 7435 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7436 | |
7437 | /* M2 fraction division enable */ | |
a945ce7e VP |
7438 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7439 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7440 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7441 | if (bestm2_frac) | |
7442 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7443 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7444 | |
de3a0fde VP |
7445 | /* Program digital lock detect threshold */ |
7446 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7447 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7448 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7449 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7450 | if (!bestm2_frac) | |
7451 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7452 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7453 | ||
9d556c99 | 7454 | /* Loop filter */ |
9cbe40c1 VP |
7455 | if (vco == 5400000) { |
7456 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7457 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7458 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7459 | tribuf_calcntr = 0x9; | |
7460 | } else if (vco <= 6200000) { | |
7461 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7462 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7463 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7464 | tribuf_calcntr = 0x9; | |
7465 | } else if (vco <= 6480000) { | |
7466 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7467 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7468 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7469 | tribuf_calcntr = 0x8; | |
7470 | } else { | |
7471 | /* Not supported. Apply the same limits as in the max case */ | |
7472 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7473 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7474 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7475 | tribuf_calcntr = 0; | |
7476 | } | |
9d556c99 CML |
7477 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7478 | ||
968040b2 | 7479 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7480 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7481 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7482 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7483 | ||
9d556c99 CML |
7484 | /* AFC Recal */ |
7485 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7486 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7487 | DPIO_AFC_RECAL); | |
7488 | ||
a580516d | 7489 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7490 | } |
7491 | ||
d288f65f VS |
7492 | /** |
7493 | * vlv_force_pll_on - forcibly enable just the PLL | |
7494 | * @dev_priv: i915 private structure | |
7495 | * @pipe: pipe PLL to enable | |
7496 | * @dpll: PLL configuration | |
7497 | * | |
7498 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7499 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7500 | * be enabled. | |
7501 | */ | |
3f36b937 TU |
7502 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7503 | const struct dpll *dpll) | |
d288f65f VS |
7504 | { |
7505 | struct intel_crtc *crtc = | |
7506 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7507 | struct intel_crtc_state *pipe_config; |
7508 | ||
7509 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7510 | if (!pipe_config) | |
7511 | return -ENOMEM; | |
7512 | ||
7513 | pipe_config->base.crtc = &crtc->base; | |
7514 | pipe_config->pixel_multiplier = 1; | |
7515 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7516 | |
7517 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7518 | chv_compute_dpll(crtc, pipe_config); |
7519 | chv_prepare_pll(crtc, pipe_config); | |
7520 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7521 | } else { |
3f36b937 TU |
7522 | vlv_compute_dpll(crtc, pipe_config); |
7523 | vlv_prepare_pll(crtc, pipe_config); | |
7524 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7525 | } |
3f36b937 TU |
7526 | |
7527 | kfree(pipe_config); | |
7528 | ||
7529 | return 0; | |
d288f65f VS |
7530 | } |
7531 | ||
7532 | /** | |
7533 | * vlv_force_pll_off - forcibly disable just the PLL | |
7534 | * @dev_priv: i915 private structure | |
7535 | * @pipe: pipe PLL to disable | |
7536 | * | |
7537 | * Disable the PLL for @pipe. To be used in cases where we need | |
7538 | * the PLL enabled even when @pipe is not going to be enabled. | |
7539 | */ | |
7540 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7541 | { | |
7542 | if (IS_CHERRYVIEW(dev)) | |
7543 | chv_disable_pll(to_i915(dev), pipe); | |
7544 | else | |
7545 | vlv_disable_pll(to_i915(dev), pipe); | |
7546 | } | |
7547 | ||
251ac862 DV |
7548 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7549 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7550 | struct dpll *reduced_clock) |
eb1cbe48 | 7551 | { |
f47709a9 | 7552 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7553 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 7554 | u32 dpll; |
190f68c5 | 7555 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7556 | |
190f68c5 | 7557 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7558 | |
eb1cbe48 DV |
7559 | dpll = DPLL_VGA_MODE_DIS; |
7560 | ||
2d84d2b3 | 7561 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7562 | dpll |= DPLLB_MODE_LVDS; |
7563 | else | |
7564 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7565 | |
ef1b460d | 7566 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7567 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7568 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7569 | } |
198a037f | 7570 | |
3d6e9ee0 VS |
7571 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7572 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 7573 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7574 | |
37a5650b | 7575 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 7576 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7577 | |
7578 | /* compute bitmask from p1 value */ | |
7579 | if (IS_PINEVIEW(dev)) | |
7580 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7581 | else { | |
7582 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7583 | if (IS_G4X(dev) && reduced_clock) | |
7584 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7585 | } | |
7586 | switch (clock->p2) { | |
7587 | case 5: | |
7588 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7589 | break; | |
7590 | case 7: | |
7591 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7592 | break; | |
7593 | case 10: | |
7594 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7595 | break; | |
7596 | case 14: | |
7597 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7598 | break; | |
7599 | } | |
7600 | if (INTEL_INFO(dev)->gen >= 4) | |
7601 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7602 | ||
190f68c5 | 7603 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7604 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 7605 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7606 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7607 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7608 | else | |
7609 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7610 | ||
7611 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7612 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7613 | |
eb1cbe48 | 7614 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7615 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7616 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7617 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7618 | } |
7619 | } | |
7620 | ||
251ac862 DV |
7621 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7622 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7623 | struct dpll *reduced_clock) |
eb1cbe48 | 7624 | { |
f47709a9 | 7625 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7626 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 7627 | u32 dpll; |
190f68c5 | 7628 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7629 | |
190f68c5 | 7630 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7631 | |
eb1cbe48 DV |
7632 | dpll = DPLL_VGA_MODE_DIS; |
7633 | ||
2d84d2b3 | 7634 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7635 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7636 | } else { | |
7637 | if (clock->p1 == 2) | |
7638 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7639 | else | |
7640 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7641 | if (clock->p2 == 4) | |
7642 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7643 | } | |
7644 | ||
2d84d2b3 | 7645 | if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7646 | dpll |= DPLL_DVO_2X_MODE; |
7647 | ||
2d84d2b3 | 7648 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7649 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7650 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7651 | else | |
7652 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7653 | ||
7654 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7655 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7656 | } |
7657 | ||
8a654f3b | 7658 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7659 | { |
7660 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7661 | struct drm_i915_private *dev_priv = to_i915(dev); |
b0e77b9c | 7662 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 7663 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7664 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7665 | uint32_t crtc_vtotal, crtc_vblank_end; |
7666 | int vsyncshift = 0; | |
4d8a62ea DV |
7667 | |
7668 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7669 | * the hw state checker will get angry at the mismatch. */ | |
7670 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7671 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7672 | |
609aeaca | 7673 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7674 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7675 | crtc_vtotal -= 1; |
7676 | crtc_vblank_end -= 1; | |
609aeaca | 7677 | |
2d84d2b3 | 7678 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7679 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7680 | else | |
7681 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7682 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7683 | if (vsyncshift < 0) |
7684 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7685 | } |
7686 | ||
7687 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7688 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7689 | |
fe2b8f9d | 7690 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7691 | (adjusted_mode->crtc_hdisplay - 1) | |
7692 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7693 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7694 | (adjusted_mode->crtc_hblank_start - 1) | |
7695 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7696 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7697 | (adjusted_mode->crtc_hsync_start - 1) | |
7698 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7699 | ||
fe2b8f9d | 7700 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7701 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7702 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7703 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7704 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7705 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7706 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7707 | (adjusted_mode->crtc_vsync_start - 1) | |
7708 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7709 | ||
b5e508d4 PZ |
7710 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7711 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7712 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7713 | * bits. */ | |
7714 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7715 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7716 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7717 | ||
bc58be60 JN |
7718 | } |
7719 | ||
7720 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7721 | { | |
7722 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7723 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
7724 | enum pipe pipe = intel_crtc->pipe; |
7725 | ||
b0e77b9c PZ |
7726 | /* pipesrc controls the size that is scaled from, which should |
7727 | * always be the user's requested size. | |
7728 | */ | |
7729 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7730 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7731 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7732 | } |
7733 | ||
1bd1bd80 | 7734 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7735 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7736 | { |
7737 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7738 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
7739 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
7740 | uint32_t tmp; | |
7741 | ||
7742 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7743 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7744 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7745 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7746 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7747 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7748 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7749 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7750 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7751 | |
7752 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7753 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7754 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7755 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7756 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7757 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7758 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7759 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7760 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7761 | |
7762 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7763 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7764 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7765 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7766 | } |
bc58be60 JN |
7767 | } |
7768 | ||
7769 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7770 | struct intel_crtc_state *pipe_config) | |
7771 | { | |
7772 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7773 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 7774 | u32 tmp; |
1bd1bd80 DV |
7775 | |
7776 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7777 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7778 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7779 | ||
2d112de7 ACO |
7780 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7781 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7782 | } |
7783 | ||
f6a83288 | 7784 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7785 | struct intel_crtc_state *pipe_config) |
babea61d | 7786 | { |
2d112de7 ACO |
7787 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7788 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7789 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7790 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7791 | |
2d112de7 ACO |
7792 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7793 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7794 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7795 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7796 | |
2d112de7 | 7797 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7798 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7799 | |
2d112de7 ACO |
7800 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7801 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7802 | |
7803 | mode->hsync = drm_mode_hsync(mode); | |
7804 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7805 | drm_mode_set_name(mode); | |
babea61d JB |
7806 | } |
7807 | ||
84b046f3 DV |
7808 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7809 | { | |
7810 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7811 | struct drm_i915_private *dev_priv = to_i915(dev); |
84b046f3 DV |
7812 | uint32_t pipeconf; |
7813 | ||
9f11a9e4 | 7814 | pipeconf = 0; |
84b046f3 | 7815 | |
b6b5d049 VS |
7816 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7817 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7818 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7819 | |
6e3c9717 | 7820 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7821 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7822 | |
ff9ce46e | 7823 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7824 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7825 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7826 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7827 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7828 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7829 | |
6e3c9717 | 7830 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7831 | case 18: |
7832 | pipeconf |= PIPECONF_6BPC; | |
7833 | break; | |
7834 | case 24: | |
7835 | pipeconf |= PIPECONF_8BPC; | |
7836 | break; | |
7837 | case 30: | |
7838 | pipeconf |= PIPECONF_10BPC; | |
7839 | break; | |
7840 | default: | |
7841 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7842 | BUG(); | |
84b046f3 DV |
7843 | } |
7844 | } | |
7845 | ||
7846 | if (HAS_PIPE_CXSR(dev)) { | |
7847 | if (intel_crtc->lowfreq_avail) { | |
7848 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7849 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7850 | } else { | |
7851 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7852 | } |
7853 | } | |
7854 | ||
6e3c9717 | 7855 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7856 | if (INTEL_INFO(dev)->gen < 4 || |
2d84d2b3 | 7857 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7858 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7859 | else | |
7860 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7861 | } else | |
84b046f3 DV |
7862 | pipeconf |= PIPECONF_PROGRESSIVE; |
7863 | ||
666a4537 WB |
7864 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7865 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7866 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7867 | |
84b046f3 DV |
7868 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7869 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7870 | } | |
7871 | ||
81c97f52 ACO |
7872 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7873 | struct intel_crtc_state *crtc_state) | |
7874 | { | |
7875 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7876 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7877 | const struct intel_limit *limit; |
81c97f52 ACO |
7878 | int refclk = 48000; |
7879 | ||
7880 | memset(&crtc_state->dpll_hw_state, 0, | |
7881 | sizeof(crtc_state->dpll_hw_state)); | |
7882 | ||
2d84d2b3 | 7883 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
7884 | if (intel_panel_use_ssc(dev_priv)) { |
7885 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7886 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7887 | } | |
7888 | ||
7889 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 7890 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
7891 | limit = &intel_limits_i8xx_dvo; |
7892 | } else { | |
7893 | limit = &intel_limits_i8xx_dac; | |
7894 | } | |
7895 | ||
7896 | if (!crtc_state->clock_set && | |
7897 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7898 | refclk, NULL, &crtc_state->dpll)) { | |
7899 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7900 | return -EINVAL; | |
7901 | } | |
7902 | ||
7903 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7904 | ||
7905 | return 0; | |
7906 | } | |
7907 | ||
19ec6693 ACO |
7908 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7909 | struct intel_crtc_state *crtc_state) | |
7910 | { | |
7911 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7912 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7913 | const struct intel_limit *limit; |
19ec6693 ACO |
7914 | int refclk = 96000; |
7915 | ||
7916 | memset(&crtc_state->dpll_hw_state, 0, | |
7917 | sizeof(crtc_state->dpll_hw_state)); | |
7918 | ||
2d84d2b3 | 7919 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
7920 | if (intel_panel_use_ssc(dev_priv)) { |
7921 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7922 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7923 | } | |
7924 | ||
7925 | if (intel_is_dual_link_lvds(dev)) | |
7926 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7927 | else | |
7928 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
7929 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
7930 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 7931 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 7932 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
7933 | limit = &intel_limits_g4x_sdvo; |
7934 | } else { | |
7935 | /* The option is for other outputs */ | |
7936 | limit = &intel_limits_i9xx_sdvo; | |
7937 | } | |
7938 | ||
7939 | if (!crtc_state->clock_set && | |
7940 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7941 | refclk, NULL, &crtc_state->dpll)) { | |
7942 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7943 | return -EINVAL; | |
7944 | } | |
7945 | ||
7946 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7947 | ||
7948 | return 0; | |
7949 | } | |
7950 | ||
70e8aa21 ACO |
7951 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7952 | struct intel_crtc_state *crtc_state) | |
7953 | { | |
7954 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7955 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7956 | const struct intel_limit *limit; |
70e8aa21 ACO |
7957 | int refclk = 96000; |
7958 | ||
7959 | memset(&crtc_state->dpll_hw_state, 0, | |
7960 | sizeof(crtc_state->dpll_hw_state)); | |
7961 | ||
2d84d2b3 | 7962 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7963 | if (intel_panel_use_ssc(dev_priv)) { |
7964 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7965 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7966 | } | |
7967 | ||
7968 | limit = &intel_limits_pineview_lvds; | |
7969 | } else { | |
7970 | limit = &intel_limits_pineview_sdvo; | |
7971 | } | |
7972 | ||
7973 | if (!crtc_state->clock_set && | |
7974 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7975 | refclk, NULL, &crtc_state->dpll)) { | |
7976 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7977 | return -EINVAL; | |
7978 | } | |
7979 | ||
7980 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7981 | ||
7982 | return 0; | |
7983 | } | |
7984 | ||
190f68c5 ACO |
7985 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7986 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7987 | { |
c7653199 | 7988 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7989 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7990 | const struct intel_limit *limit; |
81c97f52 | 7991 | int refclk = 96000; |
79e53945 | 7992 | |
dd3cd74a ACO |
7993 | memset(&crtc_state->dpll_hw_state, 0, |
7994 | sizeof(crtc_state->dpll_hw_state)); | |
7995 | ||
2d84d2b3 | 7996 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7997 | if (intel_panel_use_ssc(dev_priv)) { |
7998 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7999 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8000 | } | |
43565a06 | 8001 | |
70e8aa21 ACO |
8002 | limit = &intel_limits_i9xx_lvds; |
8003 | } else { | |
8004 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 8005 | } |
79e53945 | 8006 | |
70e8aa21 ACO |
8007 | if (!crtc_state->clock_set && |
8008 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8009 | refclk, NULL, &crtc_state->dpll)) { | |
8010 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8011 | return -EINVAL; | |
f47709a9 | 8012 | } |
7026d4ac | 8013 | |
81c97f52 | 8014 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 8015 | |
c8f7a0db | 8016 | return 0; |
f564048e EA |
8017 | } |
8018 | ||
65b3d6a9 ACO |
8019 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
8020 | struct intel_crtc_state *crtc_state) | |
8021 | { | |
8022 | int refclk = 100000; | |
1b6f4958 | 8023 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
8024 | |
8025 | memset(&crtc_state->dpll_hw_state, 0, | |
8026 | sizeof(crtc_state->dpll_hw_state)); | |
8027 | ||
65b3d6a9 ACO |
8028 | if (!crtc_state->clock_set && |
8029 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8030 | refclk, NULL, &crtc_state->dpll)) { | |
8031 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8032 | return -EINVAL; | |
8033 | } | |
8034 | ||
8035 | chv_compute_dpll(crtc, crtc_state); | |
8036 | ||
8037 | return 0; | |
8038 | } | |
8039 | ||
8040 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
8041 | struct intel_crtc_state *crtc_state) | |
8042 | { | |
8043 | int refclk = 100000; | |
1b6f4958 | 8044 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
8045 | |
8046 | memset(&crtc_state->dpll_hw_state, 0, | |
8047 | sizeof(crtc_state->dpll_hw_state)); | |
8048 | ||
65b3d6a9 ACO |
8049 | if (!crtc_state->clock_set && |
8050 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8051 | refclk, NULL, &crtc_state->dpll)) { | |
8052 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8053 | return -EINVAL; | |
8054 | } | |
8055 | ||
8056 | vlv_compute_dpll(crtc, crtc_state); | |
8057 | ||
8058 | return 0; | |
8059 | } | |
8060 | ||
2fa2fe9a | 8061 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8062 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8063 | { |
8064 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8065 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8066 | uint32_t tmp; |
8067 | ||
dc9e7dec VS |
8068 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8069 | return; | |
8070 | ||
2fa2fe9a | 8071 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8072 | if (!(tmp & PFIT_ENABLE)) |
8073 | return; | |
2fa2fe9a | 8074 | |
06922821 | 8075 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8076 | if (INTEL_INFO(dev)->gen < 4) { |
8077 | if (crtc->pipe != PIPE_B) | |
8078 | return; | |
2fa2fe9a DV |
8079 | } else { |
8080 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8081 | return; | |
8082 | } | |
8083 | ||
06922821 | 8084 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 8085 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
8086 | } |
8087 | ||
acbec814 | 8088 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8089 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8090 | { |
8091 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8092 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 8093 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 8094 | struct dpll clock; |
acbec814 | 8095 | u32 mdiv; |
662c6ecb | 8096 | int refclk = 100000; |
acbec814 | 8097 | |
b521973b VS |
8098 | /* In case of DSI, DPLL will not be used */ |
8099 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
8100 | return; |
8101 | ||
a580516d | 8102 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8103 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8104 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8105 | |
8106 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8107 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8108 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8109 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8110 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8111 | ||
dccbea3b | 8112 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8113 | } |
8114 | ||
5724dbd1 DL |
8115 | static void |
8116 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8117 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8118 | { |
8119 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8120 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
8121 | u32 val, base, offset; |
8122 | int pipe = crtc->pipe, plane = crtc->plane; | |
8123 | int fourcc, pixel_format; | |
6761dd31 | 8124 | unsigned int aligned_height; |
b113d5ee | 8125 | struct drm_framebuffer *fb; |
1b842c89 | 8126 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8127 | |
42a7b088 DL |
8128 | val = I915_READ(DSPCNTR(plane)); |
8129 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8130 | return; | |
8131 | ||
d9806c9f | 8132 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8133 | if (!intel_fb) { |
1ad292b5 JB |
8134 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8135 | return; | |
8136 | } | |
8137 | ||
1b842c89 DL |
8138 | fb = &intel_fb->base; |
8139 | ||
18c5247e DV |
8140 | if (INTEL_INFO(dev)->gen >= 4) { |
8141 | if (val & DISPPLANE_TILED) { | |
49af449b | 8142 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8143 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8144 | } | |
8145 | } | |
1ad292b5 JB |
8146 | |
8147 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8148 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8149 | fb->pixel_format = fourcc; |
8150 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8151 | |
8152 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8153 | if (plane_config->tiling) |
1ad292b5 JB |
8154 | offset = I915_READ(DSPTILEOFF(plane)); |
8155 | else | |
8156 | offset = I915_READ(DSPLINOFF(plane)); | |
8157 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8158 | } else { | |
8159 | base = I915_READ(DSPADDR(plane)); | |
8160 | } | |
8161 | plane_config->base = base; | |
8162 | ||
8163 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8164 | fb->width = ((val >> 16) & 0xfff) + 1; |
8165 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8166 | |
8167 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8168 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8169 | |
b113d5ee | 8170 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8171 | fb->pixel_format, |
8172 | fb->modifier[0]); | |
1ad292b5 | 8173 | |
f37b5c2b | 8174 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8175 | |
2844a921 DL |
8176 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8177 | pipe_name(pipe), plane, fb->width, fb->height, | |
8178 | fb->bits_per_pixel, base, fb->pitches[0], | |
8179 | plane_config->size); | |
1ad292b5 | 8180 | |
2d14030b | 8181 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8182 | } |
8183 | ||
70b23a98 | 8184 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8185 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8186 | { |
8187 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8188 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
8189 | int pipe = pipe_config->cpu_transcoder; |
8190 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 8191 | struct dpll clock; |
0d7b6b11 | 8192 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8193 | int refclk = 100000; |
8194 | ||
b521973b VS |
8195 | /* In case of DSI, DPLL will not be used */ |
8196 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8197 | return; | |
8198 | ||
a580516d | 8199 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8200 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8201 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8202 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8203 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8204 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8205 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8206 | |
8207 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8208 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8209 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8210 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8211 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8212 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8213 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8214 | ||
dccbea3b | 8215 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8216 | } |
8217 | ||
0e8ffe1b | 8218 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8219 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8220 | { |
8221 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8222 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8223 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8224 | uint32_t tmp; |
1729050e | 8225 | bool ret; |
0e8ffe1b | 8226 | |
1729050e ID |
8227 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8228 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8229 | return false; |
8230 | ||
e143a21c | 8231 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8232 | pipe_config->shared_dpll = NULL; |
eccb140b | 8233 | |
1729050e ID |
8234 | ret = false; |
8235 | ||
0e8ffe1b DV |
8236 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8237 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8238 | goto out; |
0e8ffe1b | 8239 | |
666a4537 | 8240 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8241 | switch (tmp & PIPECONF_BPC_MASK) { |
8242 | case PIPECONF_6BPC: | |
8243 | pipe_config->pipe_bpp = 18; | |
8244 | break; | |
8245 | case PIPECONF_8BPC: | |
8246 | pipe_config->pipe_bpp = 24; | |
8247 | break; | |
8248 | case PIPECONF_10BPC: | |
8249 | pipe_config->pipe_bpp = 30; | |
8250 | break; | |
8251 | default: | |
8252 | break; | |
8253 | } | |
8254 | } | |
8255 | ||
666a4537 WB |
8256 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8257 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8258 | pipe_config->limited_color_range = true; |
8259 | ||
282740f7 VS |
8260 | if (INTEL_INFO(dev)->gen < 4) |
8261 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8262 | ||
1bd1bd80 | 8263 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8264 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8265 | |
2fa2fe9a DV |
8266 | i9xx_get_pfit_config(crtc, pipe_config); |
8267 | ||
6c49f241 | 8268 | if (INTEL_INFO(dev)->gen >= 4) { |
c231775c VS |
8269 | /* No way to read it out on pipes B and C */ |
8270 | if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) | |
8271 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; | |
8272 | else | |
8273 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
8274 | pipe_config->pixel_multiplier = |
8275 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8276 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8277 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8278 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8279 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8280 | pipe_config->pixel_multiplier = | |
8281 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8282 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8283 | } else { | |
8284 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8285 | * port and will be fixed up in the encoder->get_config | |
8286 | * function. */ | |
8287 | pipe_config->pixel_multiplier = 1; | |
8288 | } | |
8bcc2795 | 8289 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8290 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8291 | /* |
8292 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8293 | * on 830. Filter it out here so that we don't | |
8294 | * report errors due to that. | |
8295 | */ | |
8296 | if (IS_I830(dev)) | |
8297 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8298 | ||
8bcc2795 DV |
8299 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8300 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8301 | } else { |
8302 | /* Mask out read-only status bits. */ | |
8303 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8304 | DPLL_PORTC_READY_MASK | | |
8305 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8306 | } |
6c49f241 | 8307 | |
70b23a98 VS |
8308 | if (IS_CHERRYVIEW(dev)) |
8309 | chv_crtc_clock_get(crtc, pipe_config); | |
8310 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8311 | vlv_crtc_clock_get(crtc, pipe_config); |
8312 | else | |
8313 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8314 | |
0f64614d VS |
8315 | /* |
8316 | * Normally the dotclock is filled in by the encoder .get_config() | |
8317 | * but in case the pipe is enabled w/o any ports we need a sane | |
8318 | * default. | |
8319 | */ | |
8320 | pipe_config->base.adjusted_mode.crtc_clock = | |
8321 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8322 | ||
1729050e ID |
8323 | ret = true; |
8324 | ||
8325 | out: | |
8326 | intel_display_power_put(dev_priv, power_domain); | |
8327 | ||
8328 | return ret; | |
0e8ffe1b DV |
8329 | } |
8330 | ||
dde86e2d | 8331 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 | 8332 | { |
fac5e23e | 8333 | struct drm_i915_private *dev_priv = to_i915(dev); |
13d83a67 | 8334 | struct intel_encoder *encoder; |
1c1a24d2 | 8335 | int i; |
74cfd7ac | 8336 | u32 val, final; |
13d83a67 | 8337 | bool has_lvds = false; |
199e5d79 | 8338 | bool has_cpu_edp = false; |
199e5d79 | 8339 | bool has_panel = false; |
99eb6a01 KP |
8340 | bool has_ck505 = false; |
8341 | bool can_ssc = false; | |
1c1a24d2 | 8342 | bool using_ssc_source = false; |
13d83a67 JB |
8343 | |
8344 | /* We need to take the global config into account */ | |
b2784e15 | 8345 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8346 | switch (encoder->type) { |
8347 | case INTEL_OUTPUT_LVDS: | |
8348 | has_panel = true; | |
8349 | has_lvds = true; | |
8350 | break; | |
8351 | case INTEL_OUTPUT_EDP: | |
8352 | has_panel = true; | |
2de6905f | 8353 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8354 | has_cpu_edp = true; |
8355 | break; | |
6847d71b PZ |
8356 | default: |
8357 | break; | |
13d83a67 JB |
8358 | } |
8359 | } | |
8360 | ||
99eb6a01 | 8361 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8362 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8363 | can_ssc = has_ck505; |
8364 | } else { | |
8365 | has_ck505 = false; | |
8366 | can_ssc = true; | |
8367 | } | |
8368 | ||
1c1a24d2 L |
8369 | /* Check if any DPLLs are using the SSC source */ |
8370 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8371 | u32 temp = I915_READ(PCH_DPLL(i)); | |
8372 | ||
8373 | if (!(temp & DPLL_VCO_ENABLE)) | |
8374 | continue; | |
8375 | ||
8376 | if ((temp & PLL_REF_INPUT_MASK) == | |
8377 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
8378 | using_ssc_source = true; | |
8379 | break; | |
8380 | } | |
8381 | } | |
8382 | ||
8383 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
8384 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
8385 | |
8386 | /* Ironlake: try to setup display ref clock before DPLL | |
8387 | * enabling. This is only under driver's control after | |
8388 | * PCH B stepping, previous chipset stepping should be | |
8389 | * ignoring this setting. | |
8390 | */ | |
74cfd7ac CW |
8391 | val = I915_READ(PCH_DREF_CONTROL); |
8392 | ||
8393 | /* As we must carefully and slowly disable/enable each source in turn, | |
8394 | * compute the final state we want first and check if we need to | |
8395 | * make any changes at all. | |
8396 | */ | |
8397 | final = val; | |
8398 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8399 | if (has_ck505) | |
8400 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8401 | else | |
8402 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8403 | ||
8c07eb68 | 8404 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 8405 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 8406 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
8407 | |
8408 | if (has_panel) { | |
8409 | final |= DREF_SSC_SOURCE_ENABLE; | |
8410 | ||
8411 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8412 | final |= DREF_SSC1_ENABLE; | |
8413 | ||
8414 | if (has_cpu_edp) { | |
8415 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8416 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8417 | else | |
8418 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8419 | } else | |
8420 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
8421 | } else if (using_ssc_source) { |
8422 | final |= DREF_SSC_SOURCE_ENABLE; | |
8423 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
8424 | } |
8425 | ||
8426 | if (final == val) | |
8427 | return; | |
8428 | ||
13d83a67 | 8429 | /* Always enable nonspread source */ |
74cfd7ac | 8430 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8431 | |
99eb6a01 | 8432 | if (has_ck505) |
74cfd7ac | 8433 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8434 | else |
74cfd7ac | 8435 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8436 | |
199e5d79 | 8437 | if (has_panel) { |
74cfd7ac CW |
8438 | val &= ~DREF_SSC_SOURCE_MASK; |
8439 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8440 | |
199e5d79 | 8441 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8442 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8443 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8444 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8445 | } else |
74cfd7ac | 8446 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8447 | |
8448 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8449 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8450 | POSTING_READ(PCH_DREF_CONTROL); |
8451 | udelay(200); | |
8452 | ||
74cfd7ac | 8453 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8454 | |
8455 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8456 | if (has_cpu_edp) { |
99eb6a01 | 8457 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8458 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8459 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8460 | } else |
74cfd7ac | 8461 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8462 | } else |
74cfd7ac | 8463 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8464 | |
74cfd7ac | 8465 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8466 | POSTING_READ(PCH_DREF_CONTROL); |
8467 | udelay(200); | |
8468 | } else { | |
1c1a24d2 | 8469 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 8470 | |
74cfd7ac | 8471 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8472 | |
8473 | /* Turn off CPU output */ | |
74cfd7ac | 8474 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8475 | |
74cfd7ac | 8476 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8477 | POSTING_READ(PCH_DREF_CONTROL); |
8478 | udelay(200); | |
8479 | ||
1c1a24d2 L |
8480 | if (!using_ssc_source) { |
8481 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 8482 | |
1c1a24d2 L |
8483 | /* Turn off the SSC source */ |
8484 | val &= ~DREF_SSC_SOURCE_MASK; | |
8485 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 8486 | |
1c1a24d2 L |
8487 | /* Turn off SSC1 */ |
8488 | val &= ~DREF_SSC1_ENABLE; | |
8489 | ||
8490 | I915_WRITE(PCH_DREF_CONTROL, val); | |
8491 | POSTING_READ(PCH_DREF_CONTROL); | |
8492 | udelay(200); | |
8493 | } | |
13d83a67 | 8494 | } |
74cfd7ac CW |
8495 | |
8496 | BUG_ON(val != final); | |
13d83a67 JB |
8497 | } |
8498 | ||
f31f2d55 | 8499 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8500 | { |
f31f2d55 | 8501 | uint32_t tmp; |
dde86e2d | 8502 | |
0ff066a9 PZ |
8503 | tmp = I915_READ(SOUTH_CHICKEN2); |
8504 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8505 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8506 | |
cf3598c2 ID |
8507 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
8508 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 8509 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 8510 | |
0ff066a9 PZ |
8511 | tmp = I915_READ(SOUTH_CHICKEN2); |
8512 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8513 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8514 | |
cf3598c2 ID |
8515 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
8516 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 8517 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
8518 | } |
8519 | ||
8520 | /* WaMPhyProgramming:hsw */ | |
8521 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8522 | { | |
8523 | uint32_t tmp; | |
dde86e2d PZ |
8524 | |
8525 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8526 | tmp &= ~(0xFF << 24); | |
8527 | tmp |= (0x12 << 24); | |
8528 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8529 | ||
dde86e2d PZ |
8530 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8531 | tmp |= (1 << 11); | |
8532 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8533 | ||
8534 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8535 | tmp |= (1 << 11); | |
8536 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8537 | ||
dde86e2d PZ |
8538 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8539 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8540 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8541 | ||
8542 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8543 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8544 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8545 | ||
0ff066a9 PZ |
8546 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8547 | tmp &= ~(7 << 13); | |
8548 | tmp |= (5 << 13); | |
8549 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8550 | |
0ff066a9 PZ |
8551 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8552 | tmp &= ~(7 << 13); | |
8553 | tmp |= (5 << 13); | |
8554 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8555 | |
8556 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8557 | tmp &= ~0xFF; | |
8558 | tmp |= 0x1C; | |
8559 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8560 | ||
8561 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8562 | tmp &= ~0xFF; | |
8563 | tmp |= 0x1C; | |
8564 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8565 | ||
8566 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8567 | tmp &= ~(0xFF << 16); | |
8568 | tmp |= (0x1C << 16); | |
8569 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8570 | ||
8571 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8572 | tmp &= ~(0xFF << 16); | |
8573 | tmp |= (0x1C << 16); | |
8574 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8575 | ||
0ff066a9 PZ |
8576 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8577 | tmp |= (1 << 27); | |
8578 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8579 | |
0ff066a9 PZ |
8580 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8581 | tmp |= (1 << 27); | |
8582 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8583 | |
0ff066a9 PZ |
8584 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8585 | tmp &= ~(0xF << 28); | |
8586 | tmp |= (4 << 28); | |
8587 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8588 | |
0ff066a9 PZ |
8589 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8590 | tmp &= ~(0xF << 28); | |
8591 | tmp |= (4 << 28); | |
8592 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8593 | } |
8594 | ||
2fa86a1f PZ |
8595 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8596 | * Programming" based on the parameters passed: | |
8597 | * - Sequence to enable CLKOUT_DP | |
8598 | * - Sequence to enable CLKOUT_DP without spread | |
8599 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8600 | */ | |
8601 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8602 | bool with_fdi) | |
f31f2d55 | 8603 | { |
fac5e23e | 8604 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa86a1f PZ |
8605 | uint32_t reg, tmp; |
8606 | ||
8607 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8608 | with_spread = true; | |
c2699524 | 8609 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8610 | with_fdi = false; |
f31f2d55 | 8611 | |
a580516d | 8612 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8613 | |
8614 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8615 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8616 | tmp |= SBI_SSCCTL_PATHALT; | |
8617 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8618 | ||
8619 | udelay(24); | |
8620 | ||
2fa86a1f PZ |
8621 | if (with_spread) { |
8622 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8623 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8624 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8625 | |
2fa86a1f PZ |
8626 | if (with_fdi) { |
8627 | lpt_reset_fdi_mphy(dev_priv); | |
8628 | lpt_program_fdi_mphy(dev_priv); | |
8629 | } | |
8630 | } | |
dde86e2d | 8631 | |
c2699524 | 8632 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8633 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8634 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8635 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8636 | |
a580516d | 8637 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8638 | } |
8639 | ||
47701c3b PZ |
8640 | /* Sequence to disable CLKOUT_DP */ |
8641 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8642 | { | |
fac5e23e | 8643 | struct drm_i915_private *dev_priv = to_i915(dev); |
47701c3b PZ |
8644 | uint32_t reg, tmp; |
8645 | ||
a580516d | 8646 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8647 | |
c2699524 | 8648 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8649 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8650 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8651 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8652 | ||
8653 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8654 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8655 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8656 | tmp |= SBI_SSCCTL_PATHALT; | |
8657 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8658 | udelay(32); | |
8659 | } | |
8660 | tmp |= SBI_SSCCTL_DISABLE; | |
8661 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8662 | } | |
8663 | ||
a580516d | 8664 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8665 | } |
8666 | ||
f7be2c21 VS |
8667 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8668 | ||
8669 | static const uint16_t sscdivintphase[] = { | |
8670 | [BEND_IDX( 50)] = 0x3B23, | |
8671 | [BEND_IDX( 45)] = 0x3B23, | |
8672 | [BEND_IDX( 40)] = 0x3C23, | |
8673 | [BEND_IDX( 35)] = 0x3C23, | |
8674 | [BEND_IDX( 30)] = 0x3D23, | |
8675 | [BEND_IDX( 25)] = 0x3D23, | |
8676 | [BEND_IDX( 20)] = 0x3E23, | |
8677 | [BEND_IDX( 15)] = 0x3E23, | |
8678 | [BEND_IDX( 10)] = 0x3F23, | |
8679 | [BEND_IDX( 5)] = 0x3F23, | |
8680 | [BEND_IDX( 0)] = 0x0025, | |
8681 | [BEND_IDX( -5)] = 0x0025, | |
8682 | [BEND_IDX(-10)] = 0x0125, | |
8683 | [BEND_IDX(-15)] = 0x0125, | |
8684 | [BEND_IDX(-20)] = 0x0225, | |
8685 | [BEND_IDX(-25)] = 0x0225, | |
8686 | [BEND_IDX(-30)] = 0x0325, | |
8687 | [BEND_IDX(-35)] = 0x0325, | |
8688 | [BEND_IDX(-40)] = 0x0425, | |
8689 | [BEND_IDX(-45)] = 0x0425, | |
8690 | [BEND_IDX(-50)] = 0x0525, | |
8691 | }; | |
8692 | ||
8693 | /* | |
8694 | * Bend CLKOUT_DP | |
8695 | * steps -50 to 50 inclusive, in steps of 5 | |
8696 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8697 | * change in clock period = -(steps / 10) * 5.787 ps | |
8698 | */ | |
8699 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8700 | { | |
8701 | uint32_t tmp; | |
8702 | int idx = BEND_IDX(steps); | |
8703 | ||
8704 | if (WARN_ON(steps % 5 != 0)) | |
8705 | return; | |
8706 | ||
8707 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8708 | return; | |
8709 | ||
8710 | mutex_lock(&dev_priv->sb_lock); | |
8711 | ||
8712 | if (steps % 10 != 0) | |
8713 | tmp = 0xAAAAAAAB; | |
8714 | else | |
8715 | tmp = 0x00000000; | |
8716 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8717 | ||
8718 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8719 | tmp &= 0xffff0000; | |
8720 | tmp |= sscdivintphase[idx]; | |
8721 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8722 | ||
8723 | mutex_unlock(&dev_priv->sb_lock); | |
8724 | } | |
8725 | ||
8726 | #undef BEND_IDX | |
8727 | ||
bf8fa3d3 PZ |
8728 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8729 | { | |
bf8fa3d3 PZ |
8730 | struct intel_encoder *encoder; |
8731 | bool has_vga = false; | |
8732 | ||
b2784e15 | 8733 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8734 | switch (encoder->type) { |
8735 | case INTEL_OUTPUT_ANALOG: | |
8736 | has_vga = true; | |
8737 | break; | |
6847d71b PZ |
8738 | default: |
8739 | break; | |
bf8fa3d3 PZ |
8740 | } |
8741 | } | |
8742 | ||
f7be2c21 VS |
8743 | if (has_vga) { |
8744 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8745 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8746 | } else { |
47701c3b | 8747 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8748 | } |
bf8fa3d3 PZ |
8749 | } |
8750 | ||
dde86e2d PZ |
8751 | /* |
8752 | * Initialize reference clocks when the driver loads | |
8753 | */ | |
8754 | void intel_init_pch_refclk(struct drm_device *dev) | |
8755 | { | |
8756 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8757 | ironlake_init_pch_refclk(dev); | |
8758 | else if (HAS_PCH_LPT(dev)) | |
8759 | lpt_init_pch_refclk(dev); | |
8760 | } | |
8761 | ||
6ff93609 | 8762 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8763 | { |
fac5e23e | 8764 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
8765 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8766 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8767 | uint32_t val; |
8768 | ||
78114071 | 8769 | val = 0; |
c8203565 | 8770 | |
6e3c9717 | 8771 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8772 | case 18: |
dfd07d72 | 8773 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8774 | break; |
8775 | case 24: | |
dfd07d72 | 8776 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8777 | break; |
8778 | case 30: | |
dfd07d72 | 8779 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8780 | break; |
8781 | case 36: | |
dfd07d72 | 8782 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8783 | break; |
8784 | default: | |
cc769b62 PZ |
8785 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8786 | BUG(); | |
c8203565 PZ |
8787 | } |
8788 | ||
6e3c9717 | 8789 | if (intel_crtc->config->dither) |
c8203565 PZ |
8790 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8791 | ||
6e3c9717 | 8792 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8793 | val |= PIPECONF_INTERLACED_ILK; |
8794 | else | |
8795 | val |= PIPECONF_PROGRESSIVE; | |
8796 | ||
6e3c9717 | 8797 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8798 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8799 | |
c8203565 PZ |
8800 | I915_WRITE(PIPECONF(pipe), val); |
8801 | POSTING_READ(PIPECONF(pipe)); | |
8802 | } | |
8803 | ||
6ff93609 | 8804 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8805 | { |
fac5e23e | 8806 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 8807 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8808 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8809 | u32 val = 0; |
ee2b0b38 | 8810 | |
391bf048 | 8811 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8812 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8813 | ||
6e3c9717 | 8814 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8815 | val |= PIPECONF_INTERLACED_ILK; |
8816 | else | |
8817 | val |= PIPECONF_PROGRESSIVE; | |
8818 | ||
702e7a56 PZ |
8819 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8820 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8821 | } |
8822 | ||
391bf048 JN |
8823 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8824 | { | |
fac5e23e | 8825 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 8826 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8827 | |
391bf048 JN |
8828 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8829 | u32 val = 0; | |
756f85cf | 8830 | |
6e3c9717 | 8831 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8832 | case 18: |
8833 | val |= PIPEMISC_DITHER_6_BPC; | |
8834 | break; | |
8835 | case 24: | |
8836 | val |= PIPEMISC_DITHER_8_BPC; | |
8837 | break; | |
8838 | case 30: | |
8839 | val |= PIPEMISC_DITHER_10_BPC; | |
8840 | break; | |
8841 | case 36: | |
8842 | val |= PIPEMISC_DITHER_12_BPC; | |
8843 | break; | |
8844 | default: | |
8845 | /* Case prevented by pipe_config_set_bpp. */ | |
8846 | BUG(); | |
8847 | } | |
8848 | ||
6e3c9717 | 8849 | if (intel_crtc->config->dither) |
756f85cf PZ |
8850 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8851 | ||
391bf048 | 8852 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8853 | } |
ee2b0b38 PZ |
8854 | } |
8855 | ||
d4b1931c PZ |
8856 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8857 | { | |
8858 | /* | |
8859 | * Account for spread spectrum to avoid | |
8860 | * oversubscribing the link. Max center spread | |
8861 | * is 2.5%; use 5% for safety's sake. | |
8862 | */ | |
8863 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8864 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8865 | } |
8866 | ||
7429e9d4 | 8867 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8868 | { |
7429e9d4 | 8869 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8870 | } |
8871 | ||
b75ca6f6 ACO |
8872 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8873 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8874 | struct dpll *reduced_clock) |
79e53945 | 8875 | { |
de13a2e3 | 8876 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 8877 | struct drm_device *dev = crtc->dev; |
fac5e23e | 8878 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 8879 | u32 dpll, fp, fp2; |
3d6e9ee0 | 8880 | int factor; |
79e53945 | 8881 | |
c1858123 | 8882 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 8883 | factor = 21; |
3d6e9ee0 | 8884 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 8885 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 8886 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8887 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8888 | factor = 25; |
190f68c5 | 8889 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8890 | factor = 20; |
c1858123 | 8891 | |
b75ca6f6 ACO |
8892 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8893 | ||
190f68c5 | 8894 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8895 | fp |= FP_CB_TUNE; |
8896 | ||
8897 | if (reduced_clock) { | |
8898 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8899 | |
b75ca6f6 ACO |
8900 | if (reduced_clock->m < factor * reduced_clock->n) |
8901 | fp2 |= FP_CB_TUNE; | |
8902 | } else { | |
8903 | fp2 = fp; | |
8904 | } | |
9a7c7890 | 8905 | |
5eddb70b | 8906 | dpll = 0; |
2c07245f | 8907 | |
3d6e9ee0 | 8908 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
8909 | dpll |= DPLLB_MODE_LVDS; |
8910 | else | |
8911 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8912 | |
190f68c5 | 8913 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8914 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 8915 | |
3d6e9ee0 VS |
8916 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8917 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8918 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 8919 | |
37a5650b | 8920 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8921 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8922 | |
a07d6787 | 8923 | /* compute bitmask from p1 value */ |
190f68c5 | 8924 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8925 | /* also FPA1 */ |
190f68c5 | 8926 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8927 | |
190f68c5 | 8928 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8929 | case 5: |
8930 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8931 | break; | |
8932 | case 7: | |
8933 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8934 | break; | |
8935 | case 10: | |
8936 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8937 | break; | |
8938 | case 14: | |
8939 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8940 | break; | |
79e53945 JB |
8941 | } |
8942 | ||
3d6e9ee0 VS |
8943 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8944 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 8945 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8946 | else |
8947 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8948 | ||
b75ca6f6 ACO |
8949 | dpll |= DPLL_VCO_ENABLE; |
8950 | ||
8951 | crtc_state->dpll_hw_state.dpll = dpll; | |
8952 | crtc_state->dpll_hw_state.fp0 = fp; | |
8953 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8954 | } |
8955 | ||
190f68c5 ACO |
8956 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8957 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8958 | { |
997c030c | 8959 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8960 | struct drm_i915_private *dev_priv = to_i915(dev); |
9e2c8475 | 8961 | struct dpll reduced_clock; |
7ed9f894 | 8962 | bool has_reduced_clock = false; |
e2b78267 | 8963 | struct intel_shared_dpll *pll; |
1b6f4958 | 8964 | const struct intel_limit *limit; |
997c030c | 8965 | int refclk = 120000; |
de13a2e3 | 8966 | |
dd3cd74a ACO |
8967 | memset(&crtc_state->dpll_hw_state, 0, |
8968 | sizeof(crtc_state->dpll_hw_state)); | |
8969 | ||
ded220e2 ACO |
8970 | crtc->lowfreq_avail = false; |
8971 | ||
8972 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8973 | if (!crtc_state->has_pch_encoder) | |
8974 | return 0; | |
79e53945 | 8975 | |
2d84d2b3 | 8976 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
8977 | if (intel_panel_use_ssc(dev_priv)) { |
8978 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8979 | dev_priv->vbt.lvds_ssc_freq); | |
8980 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8981 | } | |
8982 | ||
8983 | if (intel_is_dual_link_lvds(dev)) { | |
8984 | if (refclk == 100000) | |
8985 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8986 | else | |
8987 | limit = &intel_limits_ironlake_dual_lvds; | |
8988 | } else { | |
8989 | if (refclk == 100000) | |
8990 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8991 | else | |
8992 | limit = &intel_limits_ironlake_single_lvds; | |
8993 | } | |
8994 | } else { | |
8995 | limit = &intel_limits_ironlake_dac; | |
8996 | } | |
8997 | ||
364ee29d | 8998 | if (!crtc_state->clock_set && |
997c030c ACO |
8999 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
9000 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
9001 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9002 | return -EINVAL; | |
f47709a9 | 9003 | } |
79e53945 | 9004 | |
b75ca6f6 ACO |
9005 | ironlake_compute_dpll(crtc, crtc_state, |
9006 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 9007 | |
ded220e2 ACO |
9008 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
9009 | if (pll == NULL) { | |
9010 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
9011 | pipe_name(crtc->pipe)); | |
9012 | return -EINVAL; | |
3fb37703 | 9013 | } |
79e53945 | 9014 | |
2d84d2b3 | 9015 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ded220e2 | 9016 | has_reduced_clock) |
c7653199 | 9017 | crtc->lowfreq_avail = true; |
e2b78267 | 9018 | |
c8f7a0db | 9019 | return 0; |
79e53945 JB |
9020 | } |
9021 | ||
eb14cb74 VS |
9022 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9023 | struct intel_link_m_n *m_n) | |
9024 | { | |
9025 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9026 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
9027 | enum pipe pipe = crtc->pipe; |
9028 | ||
9029 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9030 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9031 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9032 | & ~TU_SIZE_MASK; | |
9033 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9034 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9035 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9036 | } | |
9037 | ||
9038 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9039 | enum transcoder transcoder, | |
b95af8be VK |
9040 | struct intel_link_m_n *m_n, |
9041 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9042 | { |
9043 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9044 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 | 9045 | enum pipe pipe = crtc->pipe; |
72419203 | 9046 | |
eb14cb74 VS |
9047 | if (INTEL_INFO(dev)->gen >= 5) { |
9048 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9049 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9050 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9051 | & ~TU_SIZE_MASK; | |
9052 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9053 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9054 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9055 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9056 | * gen < 8) and if DRRS is supported (to make sure the | |
9057 | * registers are not unnecessarily read). | |
9058 | */ | |
9059 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9060 | crtc->config->has_drrs) { |
b95af8be VK |
9061 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9062 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9063 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9064 | & ~TU_SIZE_MASK; | |
9065 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9066 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9067 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9068 | } | |
eb14cb74 VS |
9069 | } else { |
9070 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9071 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9072 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9073 | & ~TU_SIZE_MASK; | |
9074 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9075 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9076 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9077 | } | |
9078 | } | |
9079 | ||
9080 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9081 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9082 | { |
681a8504 | 9083 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9084 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9085 | else | |
9086 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9087 | &pipe_config->dp_m_n, |
9088 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9089 | } |
72419203 | 9090 | |
eb14cb74 | 9091 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9092 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9093 | { |
9094 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9095 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9096 | } |
9097 | ||
bd2e244f | 9098 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9099 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9100 | { |
9101 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9102 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
9103 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9104 | uint32_t ps_ctrl = 0; | |
9105 | int id = -1; | |
9106 | int i; | |
bd2e244f | 9107 | |
a1b2278e CK |
9108 | /* find scaler attached to this pipe */ |
9109 | for (i = 0; i < crtc->num_scalers; i++) { | |
9110 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9111 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9112 | id = i; | |
9113 | pipe_config->pch_pfit.enabled = true; | |
9114 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9115 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9116 | break; | |
9117 | } | |
9118 | } | |
bd2e244f | 9119 | |
a1b2278e CK |
9120 | scaler_state->scaler_id = id; |
9121 | if (id >= 0) { | |
9122 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9123 | } else { | |
9124 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9125 | } |
9126 | } | |
9127 | ||
5724dbd1 DL |
9128 | static void |
9129 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9130 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9131 | { |
9132 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9133 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 9134 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9135 | int pipe = crtc->pipe; |
9136 | int fourcc, pixel_format; | |
6761dd31 | 9137 | unsigned int aligned_height; |
bc8d7dff | 9138 | struct drm_framebuffer *fb; |
1b842c89 | 9139 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9140 | |
d9806c9f | 9141 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9142 | if (!intel_fb) { |
bc8d7dff DL |
9143 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9144 | return; | |
9145 | } | |
9146 | ||
1b842c89 DL |
9147 | fb = &intel_fb->base; |
9148 | ||
bc8d7dff | 9149 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9150 | if (!(val & PLANE_CTL_ENABLE)) |
9151 | goto error; | |
9152 | ||
bc8d7dff DL |
9153 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9154 | fourcc = skl_format_to_fourcc(pixel_format, | |
9155 | val & PLANE_CTL_ORDER_RGBX, | |
9156 | val & PLANE_CTL_ALPHA_MASK); | |
9157 | fb->pixel_format = fourcc; | |
9158 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9159 | ||
40f46283 DL |
9160 | tiling = val & PLANE_CTL_TILED_MASK; |
9161 | switch (tiling) { | |
9162 | case PLANE_CTL_TILED_LINEAR: | |
9163 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9164 | break; | |
9165 | case PLANE_CTL_TILED_X: | |
9166 | plane_config->tiling = I915_TILING_X; | |
9167 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9168 | break; | |
9169 | case PLANE_CTL_TILED_Y: | |
9170 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9171 | break; | |
9172 | case PLANE_CTL_TILED_YF: | |
9173 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9174 | break; | |
9175 | default: | |
9176 | MISSING_CASE(tiling); | |
9177 | goto error; | |
9178 | } | |
9179 | ||
bc8d7dff DL |
9180 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9181 | plane_config->base = base; | |
9182 | ||
9183 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9184 | ||
9185 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9186 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9187 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9188 | ||
9189 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9190 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9191 | fb->pixel_format); |
bc8d7dff DL |
9192 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9193 | ||
9194 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9195 | fb->pixel_format, |
9196 | fb->modifier[0]); | |
bc8d7dff | 9197 | |
f37b5c2b | 9198 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9199 | |
9200 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9201 | pipe_name(pipe), fb->width, fb->height, | |
9202 | fb->bits_per_pixel, base, fb->pitches[0], | |
9203 | plane_config->size); | |
9204 | ||
2d14030b | 9205 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9206 | return; |
9207 | ||
9208 | error: | |
9209 | kfree(fb); | |
9210 | } | |
9211 | ||
2fa2fe9a | 9212 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9213 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9214 | { |
9215 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9216 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
9217 | uint32_t tmp; |
9218 | ||
9219 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9220 | ||
9221 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9222 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9223 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9224 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9225 | |
9226 | /* We currently do not free assignements of panel fitters on | |
9227 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9228 | * differentiates them) so just WARN about this case for now. */ | |
9229 | if (IS_GEN7(dev)) { | |
9230 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9231 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9232 | } | |
2fa2fe9a | 9233 | } |
79e53945 JB |
9234 | } |
9235 | ||
5724dbd1 DL |
9236 | static void |
9237 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9238 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9239 | { |
9240 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9241 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 9242 | u32 val, base, offset; |
aeee5a49 | 9243 | int pipe = crtc->pipe; |
4c6baa59 | 9244 | int fourcc, pixel_format; |
6761dd31 | 9245 | unsigned int aligned_height; |
b113d5ee | 9246 | struct drm_framebuffer *fb; |
1b842c89 | 9247 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9248 | |
42a7b088 DL |
9249 | val = I915_READ(DSPCNTR(pipe)); |
9250 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9251 | return; | |
9252 | ||
d9806c9f | 9253 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9254 | if (!intel_fb) { |
4c6baa59 JB |
9255 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9256 | return; | |
9257 | } | |
9258 | ||
1b842c89 DL |
9259 | fb = &intel_fb->base; |
9260 | ||
18c5247e DV |
9261 | if (INTEL_INFO(dev)->gen >= 4) { |
9262 | if (val & DISPPLANE_TILED) { | |
49af449b | 9263 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9264 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9265 | } | |
9266 | } | |
4c6baa59 JB |
9267 | |
9268 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9269 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9270 | fb->pixel_format = fourcc; |
9271 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9272 | |
aeee5a49 | 9273 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9274 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9275 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9276 | } else { |
49af449b | 9277 | if (plane_config->tiling) |
aeee5a49 | 9278 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9279 | else |
aeee5a49 | 9280 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9281 | } |
9282 | plane_config->base = base; | |
9283 | ||
9284 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9285 | fb->width = ((val >> 16) & 0xfff) + 1; |
9286 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9287 | |
9288 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9289 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9290 | |
b113d5ee | 9291 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9292 | fb->pixel_format, |
9293 | fb->modifier[0]); | |
4c6baa59 | 9294 | |
f37b5c2b | 9295 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9296 | |
2844a921 DL |
9297 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9298 | pipe_name(pipe), fb->width, fb->height, | |
9299 | fb->bits_per_pixel, base, fb->pitches[0], | |
9300 | plane_config->size); | |
b113d5ee | 9301 | |
2d14030b | 9302 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9303 | } |
9304 | ||
0e8ffe1b | 9305 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9306 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9307 | { |
9308 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9309 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 9310 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9311 | uint32_t tmp; |
1729050e | 9312 | bool ret; |
0e8ffe1b | 9313 | |
1729050e ID |
9314 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9315 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9316 | return false; |
9317 | ||
e143a21c | 9318 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9319 | pipe_config->shared_dpll = NULL; |
eccb140b | 9320 | |
1729050e | 9321 | ret = false; |
0e8ffe1b DV |
9322 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9323 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9324 | goto out; |
0e8ffe1b | 9325 | |
42571aef VS |
9326 | switch (tmp & PIPECONF_BPC_MASK) { |
9327 | case PIPECONF_6BPC: | |
9328 | pipe_config->pipe_bpp = 18; | |
9329 | break; | |
9330 | case PIPECONF_8BPC: | |
9331 | pipe_config->pipe_bpp = 24; | |
9332 | break; | |
9333 | case PIPECONF_10BPC: | |
9334 | pipe_config->pipe_bpp = 30; | |
9335 | break; | |
9336 | case PIPECONF_12BPC: | |
9337 | pipe_config->pipe_bpp = 36; | |
9338 | break; | |
9339 | default: | |
9340 | break; | |
9341 | } | |
9342 | ||
b5a9fa09 DV |
9343 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9344 | pipe_config->limited_color_range = true; | |
9345 | ||
ab9412ba | 9346 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9347 | struct intel_shared_dpll *pll; |
8106ddbd | 9348 | enum intel_dpll_id pll_id; |
66e985c0 | 9349 | |
88adfff1 DV |
9350 | pipe_config->has_pch_encoder = true; |
9351 | ||
627eb5a3 DV |
9352 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9353 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9354 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9355 | |
9356 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9357 | |
2d1fe073 | 9358 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
9359 | /* |
9360 | * The pipe->pch transcoder and pch transcoder->pll | |
9361 | * mapping is fixed. | |
9362 | */ | |
8106ddbd | 9363 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9364 | } else { |
9365 | tmp = I915_READ(PCH_DPLL_SEL); | |
9366 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9367 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9368 | else |
8106ddbd | 9369 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9370 | } |
66e985c0 | 9371 | |
8106ddbd ACO |
9372 | pipe_config->shared_dpll = |
9373 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9374 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9375 | |
2edd6443 ACO |
9376 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9377 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9378 | |
9379 | tmp = pipe_config->dpll_hw_state.dpll; | |
9380 | pipe_config->pixel_multiplier = | |
9381 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9382 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9383 | |
9384 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9385 | } else { |
9386 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9387 | } |
9388 | ||
1bd1bd80 | 9389 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 9390 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9391 | |
2fa2fe9a DV |
9392 | ironlake_get_pfit_config(crtc, pipe_config); |
9393 | ||
1729050e ID |
9394 | ret = true; |
9395 | ||
9396 | out: | |
9397 | intel_display_power_put(dev_priv, power_domain); | |
9398 | ||
9399 | return ret; | |
0e8ffe1b DV |
9400 | } |
9401 | ||
be256dc7 PZ |
9402 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9403 | { | |
91c8a326 | 9404 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 9405 | struct intel_crtc *crtc; |
be256dc7 | 9406 | |
d3fcc808 | 9407 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9408 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9409 | pipe_name(crtc->pipe)); |
9410 | ||
e2c719b7 RC |
9411 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9412 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9413 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9414 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9415 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9416 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9417 | "CPU PWM1 enabled\n"); |
c5107b87 | 9418 | if (IS_HASWELL(dev)) |
e2c719b7 | 9419 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9420 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9421 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9422 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9423 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9424 | "Utility pin enabled\n"); |
e2c719b7 | 9425 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9426 | |
9926ada1 PZ |
9427 | /* |
9428 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9429 | * interrupts remain enabled. We used to check for that, but since it's | |
9430 | * gen-specific and since we only disable LCPLL after we fully disable | |
9431 | * the interrupts, the check below should be enough. | |
9432 | */ | |
e2c719b7 | 9433 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9434 | } |
9435 | ||
9ccd5aeb PZ |
9436 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9437 | { | |
91c8a326 | 9438 | struct drm_device *dev = &dev_priv->drm; |
9ccd5aeb PZ |
9439 | |
9440 | if (IS_HASWELL(dev)) | |
9441 | return I915_READ(D_COMP_HSW); | |
9442 | else | |
9443 | return I915_READ(D_COMP_BDW); | |
9444 | } | |
9445 | ||
3c4c9b81 PZ |
9446 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9447 | { | |
91c8a326 | 9448 | struct drm_device *dev = &dev_priv->drm; |
3c4c9b81 PZ |
9449 | |
9450 | if (IS_HASWELL(dev)) { | |
9451 | mutex_lock(&dev_priv->rps.hw_lock); | |
9452 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9453 | val)) | |
f475dadf | 9454 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9455 | mutex_unlock(&dev_priv->rps.hw_lock); |
9456 | } else { | |
9ccd5aeb PZ |
9457 | I915_WRITE(D_COMP_BDW, val); |
9458 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9459 | } |
be256dc7 PZ |
9460 | } |
9461 | ||
9462 | /* | |
9463 | * This function implements pieces of two sequences from BSpec: | |
9464 | * - Sequence for display software to disable LCPLL | |
9465 | * - Sequence for display software to allow package C8+ | |
9466 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9467 | * register. Callers should take care of disabling all the display engine | |
9468 | * functions, doing the mode unset, fixing interrupts, etc. | |
9469 | */ | |
6ff58d53 PZ |
9470 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9471 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9472 | { |
9473 | uint32_t val; | |
9474 | ||
9475 | assert_can_disable_lcpll(dev_priv); | |
9476 | ||
9477 | val = I915_READ(LCPLL_CTL); | |
9478 | ||
9479 | if (switch_to_fclk) { | |
9480 | val |= LCPLL_CD_SOURCE_FCLK; | |
9481 | I915_WRITE(LCPLL_CTL, val); | |
9482 | ||
f53dd63f ID |
9483 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9484 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
9485 | DRM_ERROR("Switching to FCLK failed\n"); |
9486 | ||
9487 | val = I915_READ(LCPLL_CTL); | |
9488 | } | |
9489 | ||
9490 | val |= LCPLL_PLL_DISABLE; | |
9491 | I915_WRITE(LCPLL_CTL, val); | |
9492 | POSTING_READ(LCPLL_CTL); | |
9493 | ||
24d8441d | 9494 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
9495 | DRM_ERROR("LCPLL still locked\n"); |
9496 | ||
9ccd5aeb | 9497 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9498 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9499 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9500 | ndelay(100); |
9501 | ||
9ccd5aeb PZ |
9502 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9503 | 1)) | |
be256dc7 PZ |
9504 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9505 | ||
9506 | if (allow_power_down) { | |
9507 | val = I915_READ(LCPLL_CTL); | |
9508 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9509 | I915_WRITE(LCPLL_CTL, val); | |
9510 | POSTING_READ(LCPLL_CTL); | |
9511 | } | |
9512 | } | |
9513 | ||
9514 | /* | |
9515 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9516 | * source. | |
9517 | */ | |
6ff58d53 | 9518 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9519 | { |
9520 | uint32_t val; | |
9521 | ||
9522 | val = I915_READ(LCPLL_CTL); | |
9523 | ||
9524 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9525 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9526 | return; | |
9527 | ||
a8a8bd54 PZ |
9528 | /* |
9529 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9530 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9531 | */ |
59bad947 | 9532 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9533 | |
be256dc7 PZ |
9534 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9535 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9536 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9537 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9538 | } |
9539 | ||
9ccd5aeb | 9540 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9541 | val |= D_COMP_COMP_FORCE; |
9542 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9543 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9544 | |
9545 | val = I915_READ(LCPLL_CTL); | |
9546 | val &= ~LCPLL_PLL_DISABLE; | |
9547 | I915_WRITE(LCPLL_CTL, val); | |
9548 | ||
93220c08 CW |
9549 | if (intel_wait_for_register(dev_priv, |
9550 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
9551 | 5)) | |
be256dc7 PZ |
9552 | DRM_ERROR("LCPLL not locked yet\n"); |
9553 | ||
9554 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9555 | val = I915_READ(LCPLL_CTL); | |
9556 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9557 | I915_WRITE(LCPLL_CTL, val); | |
9558 | ||
f53dd63f ID |
9559 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9560 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
9561 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9562 | } | |
215733fa | 9563 | |
59bad947 | 9564 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
91c8a326 | 9565 | intel_update_cdclk(&dev_priv->drm); |
be256dc7 PZ |
9566 | } |
9567 | ||
765dab67 PZ |
9568 | /* |
9569 | * Package states C8 and deeper are really deep PC states that can only be | |
9570 | * reached when all the devices on the system allow it, so even if the graphics | |
9571 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9572 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9573 | * | |
9574 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9575 | * well is disabled and most interrupts are disabled, and these are also | |
9576 | * requirements for runtime PM. When these conditions are met, we manually do | |
9577 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9578 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9579 | * hang the machine. | |
9580 | * | |
9581 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9582 | * the state of some registers, so when we come back from PC8+ we need to | |
9583 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9584 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9585 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9586 | * because of the runtime PM support). | |
9587 | * | |
9588 | * For more, read "Display Sequences for Package C8" on the hardware | |
9589 | * documentation. | |
9590 | */ | |
a14cb6fc | 9591 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9592 | { |
91c8a326 | 9593 | struct drm_device *dev = &dev_priv->drm; |
c67a470b PZ |
9594 | uint32_t val; |
9595 | ||
c67a470b PZ |
9596 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9597 | ||
c2699524 | 9598 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9599 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9600 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9601 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9602 | } | |
9603 | ||
9604 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9605 | hsw_disable_lcpll(dev_priv, true, true); |
9606 | } | |
9607 | ||
a14cb6fc | 9608 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9609 | { |
91c8a326 | 9610 | struct drm_device *dev = &dev_priv->drm; |
c67a470b PZ |
9611 | uint32_t val; |
9612 | ||
c67a470b PZ |
9613 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9614 | ||
9615 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9616 | lpt_init_pch_refclk(dev); |
9617 | ||
c2699524 | 9618 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9619 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9620 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9621 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9622 | } | |
c67a470b PZ |
9623 | } |
9624 | ||
324513c0 | 9625 | static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9626 | { |
a821fc46 | 9627 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9628 | struct intel_atomic_state *old_intel_state = |
9629 | to_intel_atomic_state(old_state); | |
9630 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9631 | |
324513c0 | 9632 | bxt_set_cdclk(to_i915(dev), req_cdclk); |
f8437dd1 VK |
9633 | } |
9634 | ||
b432e5cf | 9635 | /* compute the max rate for new configuration */ |
27c329ed | 9636 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9637 | { |
565602d7 | 9638 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 9639 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
9640 | struct drm_crtc *crtc; |
9641 | struct drm_crtc_state *cstate; | |
27c329ed | 9642 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9643 | unsigned max_pixel_rate = 0, i; |
9644 | enum pipe pipe; | |
b432e5cf | 9645 | |
565602d7 ML |
9646 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9647 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9648 | |
565602d7 ML |
9649 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9650 | int pixel_rate; | |
27c329ed | 9651 | |
565602d7 ML |
9652 | crtc_state = to_intel_crtc_state(cstate); |
9653 | if (!crtc_state->base.enable) { | |
9654 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9655 | continue; |
565602d7 | 9656 | } |
b432e5cf | 9657 | |
27c329ed | 9658 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9659 | |
9660 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9661 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9662 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9663 | ||
565602d7 | 9664 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9665 | } |
9666 | ||
565602d7 ML |
9667 | for_each_pipe(dev_priv, pipe) |
9668 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9669 | ||
b432e5cf VS |
9670 | return max_pixel_rate; |
9671 | } | |
9672 | ||
9673 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9674 | { | |
fac5e23e | 9675 | struct drm_i915_private *dev_priv = to_i915(dev); |
b432e5cf VS |
9676 | uint32_t val, data; |
9677 | int ret; | |
9678 | ||
9679 | if (WARN((I915_READ(LCPLL_CTL) & | |
9680 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9681 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9682 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9683 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9684 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9685 | return; | |
9686 | ||
9687 | mutex_lock(&dev_priv->rps.hw_lock); | |
9688 | ret = sandybridge_pcode_write(dev_priv, | |
9689 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9690 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9691 | if (ret) { | |
9692 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9693 | return; | |
9694 | } | |
9695 | ||
9696 | val = I915_READ(LCPLL_CTL); | |
9697 | val |= LCPLL_CD_SOURCE_FCLK; | |
9698 | I915_WRITE(LCPLL_CTL, val); | |
9699 | ||
5ba00178 TU |
9700 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9701 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
9702 | DRM_ERROR("Switching to FCLK failed\n"); |
9703 | ||
9704 | val = I915_READ(LCPLL_CTL); | |
9705 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9706 | ||
9707 | switch (cdclk) { | |
9708 | case 450000: | |
9709 | val |= LCPLL_CLK_FREQ_450; | |
9710 | data = 0; | |
9711 | break; | |
9712 | case 540000: | |
9713 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9714 | data = 1; | |
9715 | break; | |
9716 | case 337500: | |
9717 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9718 | data = 2; | |
9719 | break; | |
9720 | case 675000: | |
9721 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9722 | data = 3; | |
9723 | break; | |
9724 | default: | |
9725 | WARN(1, "invalid cdclk frequency\n"); | |
9726 | return; | |
9727 | } | |
9728 | ||
9729 | I915_WRITE(LCPLL_CTL, val); | |
9730 | ||
9731 | val = I915_READ(LCPLL_CTL); | |
9732 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9733 | I915_WRITE(LCPLL_CTL, val); | |
9734 | ||
5ba00178 TU |
9735 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9736 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
9737 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9738 | ||
9739 | mutex_lock(&dev_priv->rps.hw_lock); | |
9740 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9741 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9742 | ||
7f1052a8 VS |
9743 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
9744 | ||
b432e5cf VS |
9745 | intel_update_cdclk(dev); |
9746 | ||
9747 | WARN(cdclk != dev_priv->cdclk_freq, | |
9748 | "cdclk requested %d kHz but got %d kHz\n", | |
9749 | cdclk, dev_priv->cdclk_freq); | |
9750 | } | |
9751 | ||
587c7914 VS |
9752 | static int broadwell_calc_cdclk(int max_pixclk) |
9753 | { | |
9754 | if (max_pixclk > 540000) | |
9755 | return 675000; | |
9756 | else if (max_pixclk > 450000) | |
9757 | return 540000; | |
9758 | else if (max_pixclk > 337500) | |
9759 | return 450000; | |
9760 | else | |
9761 | return 337500; | |
9762 | } | |
9763 | ||
27c329ed | 9764 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9765 | { |
27c329ed | 9766 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9767 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9768 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9769 | int cdclk; |
9770 | ||
9771 | /* | |
9772 | * FIXME should also account for plane ratio | |
9773 | * once 64bpp pixel formats are supported. | |
9774 | */ | |
587c7914 | 9775 | cdclk = broadwell_calc_cdclk(max_pixclk); |
b432e5cf | 9776 | |
b432e5cf | 9777 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9778 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9779 | cdclk, dev_priv->max_cdclk_freq); | |
9780 | return -EINVAL; | |
b432e5cf VS |
9781 | } |
9782 | ||
1a617b77 ML |
9783 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9784 | if (!intel_state->active_crtcs) | |
587c7914 | 9785 | intel_state->dev_cdclk = broadwell_calc_cdclk(0); |
b432e5cf VS |
9786 | |
9787 | return 0; | |
9788 | } | |
9789 | ||
27c329ed | 9790 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9791 | { |
27c329ed | 9792 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9793 | struct intel_atomic_state *old_intel_state = |
9794 | to_intel_atomic_state(old_state); | |
9795 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9796 | |
27c329ed | 9797 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9798 | } |
9799 | ||
c89e39f3 CT |
9800 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
9801 | { | |
9802 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
9803 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
9804 | const int max_pixclk = ilk_max_pixel_rate(state); | |
a8ca4934 | 9805 | int vco = intel_state->cdclk_pll_vco; |
c89e39f3 CT |
9806 | int cdclk; |
9807 | ||
9808 | /* | |
9809 | * FIXME should also account for plane ratio | |
9810 | * once 64bpp pixel formats are supported. | |
9811 | */ | |
a8ca4934 | 9812 | cdclk = skl_calc_cdclk(max_pixclk, vco); |
c89e39f3 CT |
9813 | |
9814 | /* | |
9815 | * FIXME move the cdclk caclulation to | |
9816 | * compute_config() so we can fail gracegully. | |
9817 | */ | |
9818 | if (cdclk > dev_priv->max_cdclk_freq) { | |
9819 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
9820 | cdclk, dev_priv->max_cdclk_freq); | |
9821 | cdclk = dev_priv->max_cdclk_freq; | |
9822 | } | |
9823 | ||
9824 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; | |
9825 | if (!intel_state->active_crtcs) | |
a8ca4934 | 9826 | intel_state->dev_cdclk = skl_calc_cdclk(0, vco); |
c89e39f3 CT |
9827 | |
9828 | return 0; | |
9829 | } | |
9830 | ||
9831 | static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
9832 | { | |
1cd593e0 VS |
9833 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
9834 | struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state); | |
9835 | unsigned int req_cdclk = intel_state->dev_cdclk; | |
9836 | unsigned int req_vco = intel_state->cdclk_pll_vco; | |
c89e39f3 | 9837 | |
1cd593e0 | 9838 | skl_set_cdclk(dev_priv, req_cdclk, req_vco); |
c89e39f3 CT |
9839 | } |
9840 | ||
190f68c5 ACO |
9841 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9842 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9843 | { |
d7edc4e5 | 9844 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
af3997b5 MK |
9845 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
9846 | return -EINVAL; | |
9847 | } | |
716c2e55 | 9848 | |
c7653199 | 9849 | crtc->lowfreq_avail = false; |
644cef34 | 9850 | |
c8f7a0db | 9851 | return 0; |
79e53945 JB |
9852 | } |
9853 | ||
3760b59c S |
9854 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9855 | enum port port, | |
9856 | struct intel_crtc_state *pipe_config) | |
9857 | { | |
8106ddbd ACO |
9858 | enum intel_dpll_id id; |
9859 | ||
3760b59c S |
9860 | switch (port) { |
9861 | case PORT_A: | |
9862 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
08250c4b | 9863 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
9864 | break; |
9865 | case PORT_B: | |
9866 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
08250c4b | 9867 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
9868 | break; |
9869 | case PORT_C: | |
9870 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
08250c4b | 9871 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
9872 | break; |
9873 | default: | |
9874 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 9875 | return; |
3760b59c | 9876 | } |
8106ddbd ACO |
9877 | |
9878 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
9879 | } |
9880 | ||
96b7dfb7 S |
9881 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9882 | enum port port, | |
5cec258b | 9883 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9884 | { |
8106ddbd | 9885 | enum intel_dpll_id id; |
a3c988ea | 9886 | u32 temp; |
96b7dfb7 S |
9887 | |
9888 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9889 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9890 | ||
9891 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 | 9892 | case SKL_DPLL0: |
a3c988ea ACO |
9893 | id = DPLL_ID_SKL_DPLL0; |
9894 | break; | |
96b7dfb7 | 9895 | case SKL_DPLL1: |
8106ddbd | 9896 | id = DPLL_ID_SKL_DPLL1; |
96b7dfb7 S |
9897 | break; |
9898 | case SKL_DPLL2: | |
8106ddbd | 9899 | id = DPLL_ID_SKL_DPLL2; |
96b7dfb7 S |
9900 | break; |
9901 | case SKL_DPLL3: | |
8106ddbd | 9902 | id = DPLL_ID_SKL_DPLL3; |
96b7dfb7 | 9903 | break; |
8106ddbd ACO |
9904 | default: |
9905 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9906 | return; | |
96b7dfb7 | 9907 | } |
8106ddbd ACO |
9908 | |
9909 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
9910 | } |
9911 | ||
7d2c8175 DL |
9912 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9913 | enum port port, | |
5cec258b | 9914 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 9915 | { |
8106ddbd ACO |
9916 | enum intel_dpll_id id; |
9917 | ||
7d2c8175 DL |
9918 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
9919 | ||
9920 | switch (pipe_config->ddi_pll_sel) { | |
9921 | case PORT_CLK_SEL_WRPLL1: | |
8106ddbd | 9922 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
9923 | break; |
9924 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 9925 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 9926 | break; |
00490c22 | 9927 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 9928 | id = DPLL_ID_SPLL; |
79bd23da | 9929 | break; |
9d16da65 ACO |
9930 | case PORT_CLK_SEL_LCPLL_810: |
9931 | id = DPLL_ID_LCPLL_810; | |
9932 | break; | |
9933 | case PORT_CLK_SEL_LCPLL_1350: | |
9934 | id = DPLL_ID_LCPLL_1350; | |
9935 | break; | |
9936 | case PORT_CLK_SEL_LCPLL_2700: | |
9937 | id = DPLL_ID_LCPLL_2700; | |
9938 | break; | |
8106ddbd ACO |
9939 | default: |
9940 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9941 | /* fall through */ | |
9942 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 9943 | return; |
7d2c8175 | 9944 | } |
8106ddbd ACO |
9945 | |
9946 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
9947 | } |
9948 | ||
cf30429e JN |
9949 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
9950 | struct intel_crtc_state *pipe_config, | |
9951 | unsigned long *power_domain_mask) | |
9952 | { | |
9953 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9954 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
9955 | enum intel_display_power_domain power_domain; |
9956 | u32 tmp; | |
9957 | ||
d9a7bc67 ID |
9958 | /* |
9959 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
9960 | * transcoder handled below. | |
9961 | */ | |
cf30429e JN |
9962 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
9963 | ||
9964 | /* | |
9965 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
9966 | * consistency and less surprising code; it's in always on power). | |
9967 | */ | |
9968 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
9969 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9970 | enum pipe trans_edp_pipe; | |
9971 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9972 | default: | |
9973 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9974 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9975 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9976 | trans_edp_pipe = PIPE_A; | |
9977 | break; | |
9978 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9979 | trans_edp_pipe = PIPE_B; | |
9980 | break; | |
9981 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9982 | trans_edp_pipe = PIPE_C; | |
9983 | break; | |
9984 | } | |
9985 | ||
9986 | if (trans_edp_pipe == crtc->pipe) | |
9987 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9988 | } | |
9989 | ||
9990 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
9991 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9992 | return false; | |
9993 | *power_domain_mask |= BIT(power_domain); | |
9994 | ||
9995 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
9996 | ||
9997 | return tmp & PIPECONF_ENABLE; | |
9998 | } | |
9999 | ||
4d1de975 JN |
10000 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
10001 | struct intel_crtc_state *pipe_config, | |
10002 | unsigned long *power_domain_mask) | |
10003 | { | |
10004 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10005 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
10006 | enum intel_display_power_domain power_domain; |
10007 | enum port port; | |
10008 | enum transcoder cpu_transcoder; | |
10009 | u32 tmp; | |
10010 | ||
4d1de975 JN |
10011 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
10012 | if (port == PORT_A) | |
10013 | cpu_transcoder = TRANSCODER_DSI_A; | |
10014 | else | |
10015 | cpu_transcoder = TRANSCODER_DSI_C; | |
10016 | ||
10017 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
10018 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10019 | continue; | |
10020 | *power_domain_mask |= BIT(power_domain); | |
10021 | ||
db18b6a6 ID |
10022 | /* |
10023 | * The PLL needs to be enabled with a valid divider | |
10024 | * configuration, otherwise accessing DSI registers will hang | |
10025 | * the machine. See BSpec North Display Engine | |
10026 | * registers/MIPI[BXT]. We can break out here early, since we | |
10027 | * need the same DSI PLL to be enabled for both DSI ports. | |
10028 | */ | |
10029 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
10030 | break; | |
10031 | ||
4d1de975 JN |
10032 | /* XXX: this works for video mode only */ |
10033 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
10034 | if (!(tmp & DPI_ENABLE)) | |
10035 | continue; | |
10036 | ||
10037 | tmp = I915_READ(MIPI_CTRL(port)); | |
10038 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
10039 | continue; | |
10040 | ||
10041 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
10042 | break; |
10043 | } | |
10044 | ||
d7edc4e5 | 10045 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
10046 | } |
10047 | ||
26804afd | 10048 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 10049 | struct intel_crtc_state *pipe_config) |
26804afd DV |
10050 | { |
10051 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10052 | struct drm_i915_private *dev_priv = to_i915(dev); |
d452c5b6 | 10053 | struct intel_shared_dpll *pll; |
26804afd DV |
10054 | enum port port; |
10055 | uint32_t tmp; | |
10056 | ||
10057 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
10058 | ||
10059 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
10060 | ||
ef11bdb3 | 10061 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 10062 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
10063 | else if (IS_BROXTON(dev)) |
10064 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
10065 | else |
10066 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 10067 | |
8106ddbd ACO |
10068 | pll = pipe_config->shared_dpll; |
10069 | if (pll) { | |
2edd6443 ACO |
10070 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
10071 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
10072 | } |
10073 | ||
26804afd DV |
10074 | /* |
10075 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
10076 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
10077 | * the PCH transcoder is on. | |
10078 | */ | |
ca370455 DL |
10079 | if (INTEL_INFO(dev)->gen < 9 && |
10080 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
10081 | pipe_config->has_pch_encoder = true; |
10082 | ||
10083 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
10084 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
10085 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
10086 | ||
10087 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
10088 | } | |
10089 | } | |
10090 | ||
0e8ffe1b | 10091 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10092 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
10093 | { |
10094 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10095 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e ID |
10096 | enum intel_display_power_domain power_domain; |
10097 | unsigned long power_domain_mask; | |
cf30429e | 10098 | bool active; |
0e8ffe1b | 10099 | |
1729050e ID |
10100 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
10101 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 10102 | return false; |
1729050e ID |
10103 | power_domain_mask = BIT(power_domain); |
10104 | ||
8106ddbd | 10105 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 10106 | |
cf30429e | 10107 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 10108 | |
d7edc4e5 VS |
10109 | if (IS_BROXTON(dev_priv) && |
10110 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { | |
10111 | WARN_ON(active); | |
10112 | active = true; | |
4d1de975 JN |
10113 | } |
10114 | ||
cf30429e | 10115 | if (!active) |
1729050e | 10116 | goto out; |
0e8ffe1b | 10117 | |
d7edc4e5 | 10118 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
10119 | haswell_get_ddi_port_state(crtc, pipe_config); |
10120 | intel_get_pipe_timings(crtc, pipe_config); | |
10121 | } | |
627eb5a3 | 10122 | |
bc58be60 | 10123 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10124 | |
05dc698c LL |
10125 | pipe_config->gamma_mode = |
10126 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
10127 | ||
a1b2278e CK |
10128 | if (INTEL_INFO(dev)->gen >= 9) { |
10129 | skl_init_scalers(dev, crtc, pipe_config); | |
10130 | } | |
10131 | ||
af99ceda CK |
10132 | if (INTEL_INFO(dev)->gen >= 9) { |
10133 | pipe_config->scaler_state.scaler_id = -1; | |
10134 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10135 | } | |
10136 | ||
1729050e ID |
10137 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10138 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10139 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10140 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10141 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10142 | else |
1c132b44 | 10143 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10144 | } |
88adfff1 | 10145 | |
e59150dc JB |
10146 | if (IS_HASWELL(dev)) |
10147 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10148 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10149 | |
4d1de975 JN |
10150 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
10151 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
10152 | pipe_config->pixel_multiplier = |
10153 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10154 | } else { | |
10155 | pipe_config->pixel_multiplier = 1; | |
10156 | } | |
6c49f241 | 10157 | |
1729050e ID |
10158 | out: |
10159 | for_each_power_domain(power_domain, power_domain_mask) | |
10160 | intel_display_power_put(dev_priv, power_domain); | |
10161 | ||
cf30429e | 10162 | return active; |
0e8ffe1b DV |
10163 | } |
10164 | ||
55a08b3f ML |
10165 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10166 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10167 | { |
10168 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10169 | struct drm_i915_private *dev_priv = to_i915(dev); |
560b85bb | 10170 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
dc41c154 | 10171 | uint32_t cntl = 0, size = 0; |
560b85bb | 10172 | |
55a08b3f ML |
10173 | if (plane_state && plane_state->visible) { |
10174 | unsigned int width = plane_state->base.crtc_w; | |
10175 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10176 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10177 | ||
10178 | switch (stride) { | |
10179 | default: | |
10180 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10181 | width, stride); | |
10182 | stride = 256; | |
10183 | /* fallthrough */ | |
10184 | case 256: | |
10185 | case 512: | |
10186 | case 1024: | |
10187 | case 2048: | |
10188 | break; | |
4b0e333e CW |
10189 | } |
10190 | ||
dc41c154 VS |
10191 | cntl |= CURSOR_ENABLE | |
10192 | CURSOR_GAMMA_ENABLE | | |
10193 | CURSOR_FORMAT_ARGB | | |
10194 | CURSOR_STRIDE(stride); | |
10195 | ||
10196 | size = (height << 12) | width; | |
4b0e333e | 10197 | } |
560b85bb | 10198 | |
dc41c154 VS |
10199 | if (intel_crtc->cursor_cntl != 0 && |
10200 | (intel_crtc->cursor_base != base || | |
10201 | intel_crtc->cursor_size != size || | |
10202 | intel_crtc->cursor_cntl != cntl)) { | |
10203 | /* On these chipsets we can only modify the base/size/stride | |
10204 | * whilst the cursor is disabled. | |
10205 | */ | |
0b87c24e VS |
10206 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10207 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10208 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10209 | } |
560b85bb | 10210 | |
99d1f387 | 10211 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10212 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10213 | intel_crtc->cursor_base = base; |
10214 | } | |
4726e0b0 | 10215 | |
dc41c154 VS |
10216 | if (intel_crtc->cursor_size != size) { |
10217 | I915_WRITE(CURSIZE, size); | |
10218 | intel_crtc->cursor_size = size; | |
4b0e333e | 10219 | } |
560b85bb | 10220 | |
4b0e333e | 10221 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10222 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10223 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10224 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10225 | } |
560b85bb CW |
10226 | } |
10227 | ||
55a08b3f ML |
10228 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10229 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10230 | { |
10231 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10232 | struct drm_i915_private *dev_priv = to_i915(dev); |
65a21cd6 JB |
10233 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10234 | int pipe = intel_crtc->pipe; | |
663f3122 | 10235 | uint32_t cntl = 0; |
4b0e333e | 10236 | |
55a08b3f | 10237 | if (plane_state && plane_state->visible) { |
4b0e333e | 10238 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10239 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10240 | case 64: |
10241 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10242 | break; | |
10243 | case 128: | |
10244 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10245 | break; | |
10246 | case 256: | |
10247 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10248 | break; | |
10249 | default: | |
55a08b3f | 10250 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10251 | return; |
65a21cd6 | 10252 | } |
4b0e333e | 10253 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10254 | |
fc6f93bc | 10255 | if (HAS_DDI(dev)) |
47bf17a7 | 10256 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10257 | |
55a08b3f ML |
10258 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10259 | cntl |= CURSOR_ROTATE_180; | |
10260 | } | |
4398ad45 | 10261 | |
4b0e333e CW |
10262 | if (intel_crtc->cursor_cntl != cntl) { |
10263 | I915_WRITE(CURCNTR(pipe), cntl); | |
10264 | POSTING_READ(CURCNTR(pipe)); | |
10265 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10266 | } |
4b0e333e | 10267 | |
65a21cd6 | 10268 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10269 | I915_WRITE(CURBASE(pipe), base); |
10270 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10271 | |
10272 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10273 | } |
10274 | ||
cda4b7d3 | 10275 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10276 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10277 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10278 | { |
10279 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10280 | struct drm_i915_private *dev_priv = to_i915(dev); |
cda4b7d3 CW |
10281 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10282 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10283 | u32 base = intel_crtc->cursor_addr; |
10284 | u32 pos = 0; | |
cda4b7d3 | 10285 | |
55a08b3f ML |
10286 | if (plane_state) { |
10287 | int x = plane_state->base.crtc_x; | |
10288 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10289 | |
55a08b3f ML |
10290 | if (x < 0) { |
10291 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10292 | x = -x; | |
10293 | } | |
10294 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10295 | |
55a08b3f ML |
10296 | if (y < 0) { |
10297 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10298 | y = -y; | |
10299 | } | |
10300 | pos |= y << CURSOR_Y_SHIFT; | |
10301 | ||
10302 | /* ILK+ do this automagically */ | |
10303 | if (HAS_GMCH_DISPLAY(dev) && | |
10304 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10305 | base += (plane_state->base.crtc_h * | |
10306 | plane_state->base.crtc_w - 1) * 4; | |
10307 | } | |
cda4b7d3 | 10308 | } |
cda4b7d3 | 10309 | |
5efb3e28 VS |
10310 | I915_WRITE(CURPOS(pipe), pos); |
10311 | ||
8ac54669 | 10312 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10313 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10314 | else |
55a08b3f | 10315 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10316 | } |
10317 | ||
dc41c154 VS |
10318 | static bool cursor_size_ok(struct drm_device *dev, |
10319 | uint32_t width, uint32_t height) | |
10320 | { | |
10321 | if (width == 0 || height == 0) | |
10322 | return false; | |
10323 | ||
10324 | /* | |
10325 | * 845g/865g are special in that they are only limited by | |
10326 | * the width of their cursors, the height is arbitrary up to | |
10327 | * the precision of the register. Everything else requires | |
10328 | * square cursors, limited to a few power-of-two sizes. | |
10329 | */ | |
10330 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10331 | if ((width & 63) != 0) | |
10332 | return false; | |
10333 | ||
10334 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10335 | return false; | |
10336 | ||
10337 | if (height > 1023) | |
10338 | return false; | |
10339 | } else { | |
10340 | switch (width | height) { | |
10341 | case 256: | |
10342 | case 128: | |
10343 | if (IS_GEN2(dev)) | |
10344 | return false; | |
10345 | case 64: | |
10346 | break; | |
10347 | default: | |
10348 | return false; | |
10349 | } | |
10350 | } | |
10351 | ||
10352 | return true; | |
10353 | } | |
10354 | ||
79e53945 JB |
10355 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10356 | static struct drm_display_mode load_detect_mode = { | |
10357 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10358 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10359 | }; | |
10360 | ||
a8bb6818 DV |
10361 | struct drm_framebuffer * |
10362 | __intel_framebuffer_create(struct drm_device *dev, | |
10363 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10364 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10365 | { |
10366 | struct intel_framebuffer *intel_fb; | |
10367 | int ret; | |
10368 | ||
10369 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10370 | if (!intel_fb) |
d2dff872 | 10371 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10372 | |
10373 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10374 | if (ret) |
10375 | goto err; | |
d2dff872 CW |
10376 | |
10377 | return &intel_fb->base; | |
dcb1394e | 10378 | |
dd4916c5 | 10379 | err: |
dd4916c5 | 10380 | kfree(intel_fb); |
dd4916c5 | 10381 | return ERR_PTR(ret); |
d2dff872 CW |
10382 | } |
10383 | ||
b5ea642a | 10384 | static struct drm_framebuffer * |
a8bb6818 DV |
10385 | intel_framebuffer_create(struct drm_device *dev, |
10386 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10387 | struct drm_i915_gem_object *obj) | |
10388 | { | |
10389 | struct drm_framebuffer *fb; | |
10390 | int ret; | |
10391 | ||
10392 | ret = i915_mutex_lock_interruptible(dev); | |
10393 | if (ret) | |
10394 | return ERR_PTR(ret); | |
10395 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10396 | mutex_unlock(&dev->struct_mutex); | |
10397 | ||
10398 | return fb; | |
10399 | } | |
10400 | ||
d2dff872 CW |
10401 | static u32 |
10402 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10403 | { | |
10404 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10405 | return ALIGN(pitch, 64); | |
10406 | } | |
10407 | ||
10408 | static u32 | |
10409 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10410 | { | |
10411 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10412 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10413 | } |
10414 | ||
10415 | static struct drm_framebuffer * | |
10416 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10417 | struct drm_display_mode *mode, | |
10418 | int depth, int bpp) | |
10419 | { | |
dcb1394e | 10420 | struct drm_framebuffer *fb; |
d2dff872 | 10421 | struct drm_i915_gem_object *obj; |
0fed39bd | 10422 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 10423 | |
d37cd8a8 | 10424 | obj = i915_gem_object_create(dev, |
d2dff872 | 10425 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
10426 | if (IS_ERR(obj)) |
10427 | return ERR_CAST(obj); | |
d2dff872 CW |
10428 | |
10429 | mode_cmd.width = mode->hdisplay; | |
10430 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10431 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10432 | bpp); | |
5ca0c34a | 10433 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10434 | |
dcb1394e LW |
10435 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10436 | if (IS_ERR(fb)) | |
34911fd3 | 10437 | i915_gem_object_put_unlocked(obj); |
dcb1394e LW |
10438 | |
10439 | return fb; | |
d2dff872 CW |
10440 | } |
10441 | ||
10442 | static struct drm_framebuffer * | |
10443 | mode_fits_in_fbdev(struct drm_device *dev, | |
10444 | struct drm_display_mode *mode) | |
10445 | { | |
0695726e | 10446 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 10447 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
10448 | struct drm_i915_gem_object *obj; |
10449 | struct drm_framebuffer *fb; | |
10450 | ||
4c0e5528 | 10451 | if (!dev_priv->fbdev) |
d2dff872 CW |
10452 | return NULL; |
10453 | ||
4c0e5528 | 10454 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10455 | return NULL; |
10456 | ||
4c0e5528 DV |
10457 | obj = dev_priv->fbdev->fb->obj; |
10458 | BUG_ON(!obj); | |
10459 | ||
8bcd4553 | 10460 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10461 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10462 | fb->bits_per_pixel)) | |
d2dff872 CW |
10463 | return NULL; |
10464 | ||
01f2c773 | 10465 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10466 | return NULL; |
10467 | ||
edde3617 | 10468 | drm_framebuffer_reference(fb); |
d2dff872 | 10469 | return fb; |
4520f53a DV |
10470 | #else |
10471 | return NULL; | |
10472 | #endif | |
d2dff872 CW |
10473 | } |
10474 | ||
d3a40d1b ACO |
10475 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10476 | struct drm_crtc *crtc, | |
10477 | struct drm_display_mode *mode, | |
10478 | struct drm_framebuffer *fb, | |
10479 | int x, int y) | |
10480 | { | |
10481 | struct drm_plane_state *plane_state; | |
10482 | int hdisplay, vdisplay; | |
10483 | int ret; | |
10484 | ||
10485 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10486 | if (IS_ERR(plane_state)) | |
10487 | return PTR_ERR(plane_state); | |
10488 | ||
10489 | if (mode) | |
10490 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10491 | else | |
10492 | hdisplay = vdisplay = 0; | |
10493 | ||
10494 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10495 | if (ret) | |
10496 | return ret; | |
10497 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10498 | plane_state->crtc_x = 0; | |
10499 | plane_state->crtc_y = 0; | |
10500 | plane_state->crtc_w = hdisplay; | |
10501 | plane_state->crtc_h = vdisplay; | |
10502 | plane_state->src_x = x << 16; | |
10503 | plane_state->src_y = y << 16; | |
10504 | plane_state->src_w = hdisplay << 16; | |
10505 | plane_state->src_h = vdisplay << 16; | |
10506 | ||
10507 | return 0; | |
10508 | } | |
10509 | ||
d2434ab7 | 10510 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10511 | struct drm_display_mode *mode, |
51fd371b RC |
10512 | struct intel_load_detect_pipe *old, |
10513 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10514 | { |
10515 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10516 | struct intel_encoder *intel_encoder = |
10517 | intel_attached_encoder(connector); | |
79e53945 | 10518 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10519 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10520 | struct drm_crtc *crtc = NULL; |
10521 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10522 | struct drm_framebuffer *fb; |
51fd371b | 10523 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10524 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10525 | struct drm_connector_state *connector_state; |
4be07317 | 10526 | struct intel_crtc_state *crtc_state; |
51fd371b | 10527 | int ret, i = -1; |
79e53945 | 10528 | |
d2dff872 | 10529 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10530 | connector->base.id, connector->name, |
8e329a03 | 10531 | encoder->base.id, encoder->name); |
d2dff872 | 10532 | |
edde3617 ML |
10533 | old->restore_state = NULL; |
10534 | ||
51fd371b RC |
10535 | retry: |
10536 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10537 | if (ret) | |
ad3c558f | 10538 | goto fail; |
6e9f798d | 10539 | |
79e53945 JB |
10540 | /* |
10541 | * Algorithm gets a little messy: | |
7a5e4805 | 10542 | * |
79e53945 JB |
10543 | * - if the connector already has an assigned crtc, use it (but make |
10544 | * sure it's on first) | |
7a5e4805 | 10545 | * |
79e53945 JB |
10546 | * - try to find the first unused crtc that can drive this connector, |
10547 | * and use that if we find one | |
79e53945 JB |
10548 | */ |
10549 | ||
10550 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10551 | if (connector->state->crtc) { |
10552 | crtc = connector->state->crtc; | |
8261b191 | 10553 | |
51fd371b | 10554 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10555 | if (ret) |
ad3c558f | 10556 | goto fail; |
8261b191 CW |
10557 | |
10558 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10559 | goto found; |
79e53945 JB |
10560 | } |
10561 | ||
10562 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10563 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10564 | i++; |
10565 | if (!(encoder->possible_crtcs & (1 << i))) | |
10566 | continue; | |
edde3617 ML |
10567 | |
10568 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10569 | if (ret) | |
10570 | goto fail; | |
10571 | ||
10572 | if (possible_crtc->state->enable) { | |
10573 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10574 | continue; |
edde3617 | 10575 | } |
a459249c VS |
10576 | |
10577 | crtc = possible_crtc; | |
10578 | break; | |
79e53945 JB |
10579 | } |
10580 | ||
10581 | /* | |
10582 | * If we didn't find an unused CRTC, don't use any. | |
10583 | */ | |
10584 | if (!crtc) { | |
7173188d | 10585 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10586 | goto fail; |
79e53945 JB |
10587 | } |
10588 | ||
edde3617 ML |
10589 | found: |
10590 | intel_crtc = to_intel_crtc(crtc); | |
10591 | ||
4d02e2de DV |
10592 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10593 | if (ret) | |
ad3c558f | 10594 | goto fail; |
79e53945 | 10595 | |
83a57153 | 10596 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10597 | restore_state = drm_atomic_state_alloc(dev); |
10598 | if (!state || !restore_state) { | |
10599 | ret = -ENOMEM; | |
10600 | goto fail; | |
10601 | } | |
83a57153 ACO |
10602 | |
10603 | state->acquire_ctx = ctx; | |
edde3617 | 10604 | restore_state->acquire_ctx = ctx; |
83a57153 | 10605 | |
944b0c76 ACO |
10606 | connector_state = drm_atomic_get_connector_state(state, connector); |
10607 | if (IS_ERR(connector_state)) { | |
10608 | ret = PTR_ERR(connector_state); | |
10609 | goto fail; | |
10610 | } | |
10611 | ||
edde3617 ML |
10612 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10613 | if (ret) | |
10614 | goto fail; | |
944b0c76 | 10615 | |
4be07317 ACO |
10616 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10617 | if (IS_ERR(crtc_state)) { | |
10618 | ret = PTR_ERR(crtc_state); | |
10619 | goto fail; | |
10620 | } | |
10621 | ||
49d6fa21 | 10622 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10623 | |
6492711d CW |
10624 | if (!mode) |
10625 | mode = &load_detect_mode; | |
79e53945 | 10626 | |
d2dff872 CW |
10627 | /* We need a framebuffer large enough to accommodate all accesses |
10628 | * that the plane may generate whilst we perform load detection. | |
10629 | * We can not rely on the fbcon either being present (we get called | |
10630 | * during its initialisation to detect all boot displays, or it may | |
10631 | * not even exist) or that it is large enough to satisfy the | |
10632 | * requested mode. | |
10633 | */ | |
94352cf9 DV |
10634 | fb = mode_fits_in_fbdev(dev, mode); |
10635 | if (fb == NULL) { | |
d2dff872 | 10636 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10637 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10638 | } else |
10639 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10640 | if (IS_ERR(fb)) { |
d2dff872 | 10641 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10642 | goto fail; |
79e53945 | 10643 | } |
79e53945 | 10644 | |
d3a40d1b ACO |
10645 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10646 | if (ret) | |
10647 | goto fail; | |
10648 | ||
edde3617 ML |
10649 | drm_framebuffer_unreference(fb); |
10650 | ||
10651 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10652 | if (ret) | |
10653 | goto fail; | |
10654 | ||
10655 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10656 | if (!ret) | |
10657 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10658 | if (!ret) | |
10659 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10660 | if (ret) { | |
10661 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10662 | goto fail; | |
10663 | } | |
8c7b5ccb | 10664 | |
3ba86073 ML |
10665 | ret = drm_atomic_commit(state); |
10666 | if (ret) { | |
6492711d | 10667 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10668 | goto fail; |
79e53945 | 10669 | } |
edde3617 ML |
10670 | |
10671 | old->restore_state = restore_state; | |
7173188d | 10672 | |
79e53945 | 10673 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10674 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10675 | return true; |
412b61d8 | 10676 | |
ad3c558f | 10677 | fail: |
e5d958ef | 10678 | drm_atomic_state_free(state); |
edde3617 ML |
10679 | drm_atomic_state_free(restore_state); |
10680 | restore_state = state = NULL; | |
83a57153 | 10681 | |
51fd371b RC |
10682 | if (ret == -EDEADLK) { |
10683 | drm_modeset_backoff(ctx); | |
10684 | goto retry; | |
10685 | } | |
10686 | ||
412b61d8 | 10687 | return false; |
79e53945 JB |
10688 | } |
10689 | ||
d2434ab7 | 10690 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10691 | struct intel_load_detect_pipe *old, |
10692 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10693 | { |
d2434ab7 DV |
10694 | struct intel_encoder *intel_encoder = |
10695 | intel_attached_encoder(connector); | |
4ef69c7a | 10696 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10697 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10698 | int ret; |
79e53945 | 10699 | |
d2dff872 | 10700 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10701 | connector->base.id, connector->name, |
8e329a03 | 10702 | encoder->base.id, encoder->name); |
d2dff872 | 10703 | |
edde3617 | 10704 | if (!state) |
0622a53c | 10705 | return; |
79e53945 | 10706 | |
edde3617 ML |
10707 | ret = drm_atomic_commit(state); |
10708 | if (ret) { | |
10709 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10710 | drm_atomic_state_free(state); | |
10711 | } | |
79e53945 JB |
10712 | } |
10713 | ||
da4a1efa | 10714 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10715 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 10716 | { |
fac5e23e | 10717 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
10718 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
10719 | ||
10720 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10721 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10722 | else if (HAS_PCH_SPLIT(dev)) |
10723 | return 120000; | |
10724 | else if (!IS_GEN2(dev)) | |
10725 | return 96000; | |
10726 | else | |
10727 | return 48000; | |
10728 | } | |
10729 | ||
79e53945 | 10730 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10731 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10732 | struct intel_crtc_state *pipe_config) |
79e53945 | 10733 | { |
f1f644dc | 10734 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 10735 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 10736 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10737 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 10738 | u32 fp; |
9e2c8475 | 10739 | struct dpll clock; |
dccbea3b | 10740 | int port_clock; |
da4a1efa | 10741 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10742 | |
10743 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10744 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10745 | else |
293623f7 | 10746 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10747 | |
10748 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10749 | if (IS_PINEVIEW(dev)) { |
10750 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10751 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10752 | } else { |
10753 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10754 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10755 | } | |
10756 | ||
a6c45cf0 | 10757 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10758 | if (IS_PINEVIEW(dev)) |
10759 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10760 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10761 | else |
10762 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10763 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10764 | ||
10765 | switch (dpll & DPLL_MODE_MASK) { | |
10766 | case DPLLB_MODE_DAC_SERIAL: | |
10767 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10768 | 5 : 10; | |
10769 | break; | |
10770 | case DPLLB_MODE_LVDS: | |
10771 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10772 | 7 : 14; | |
10773 | break; | |
10774 | default: | |
28c97730 | 10775 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10776 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10777 | return; |
79e53945 JB |
10778 | } |
10779 | ||
ac58c3f0 | 10780 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10781 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10782 | else |
dccbea3b | 10783 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10784 | } else { |
0fb58223 | 10785 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10786 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10787 | |
10788 | if (is_lvds) { | |
10789 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10790 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10791 | |
10792 | if (lvds & LVDS_CLKB_POWER_UP) | |
10793 | clock.p2 = 7; | |
10794 | else | |
10795 | clock.p2 = 14; | |
79e53945 JB |
10796 | } else { |
10797 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10798 | clock.p1 = 2; | |
10799 | else { | |
10800 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10801 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10802 | } | |
10803 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10804 | clock.p2 = 4; | |
10805 | else | |
10806 | clock.p2 = 2; | |
79e53945 | 10807 | } |
da4a1efa | 10808 | |
dccbea3b | 10809 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10810 | } |
10811 | ||
18442d08 VS |
10812 | /* |
10813 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10814 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10815 | * encoder's get_config() function. |
10816 | */ | |
dccbea3b | 10817 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10818 | } |
10819 | ||
6878da05 VS |
10820 | int intel_dotclock_calculate(int link_freq, |
10821 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10822 | { |
f1f644dc JB |
10823 | /* |
10824 | * The calculation for the data clock is: | |
1041a02f | 10825 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10826 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10827 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10828 | * |
10829 | * and the link clock is simpler: | |
1041a02f | 10830 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10831 | */ |
10832 | ||
6878da05 VS |
10833 | if (!m_n->link_n) |
10834 | return 0; | |
f1f644dc | 10835 | |
6878da05 VS |
10836 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10837 | } | |
f1f644dc | 10838 | |
18442d08 | 10839 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10840 | struct intel_crtc_state *pipe_config) |
6878da05 | 10841 | { |
e3b247da | 10842 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10843 | |
18442d08 VS |
10844 | /* read out port_clock from the DPLL */ |
10845 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10846 | |
f1f644dc | 10847 | /* |
e3b247da VS |
10848 | * In case there is an active pipe without active ports, |
10849 | * we may need some idea for the dotclock anyway. | |
10850 | * Calculate one based on the FDI configuration. | |
79e53945 | 10851 | */ |
2d112de7 | 10852 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10853 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10854 | &pipe_config->fdi_m_n); |
79e53945 JB |
10855 | } |
10856 | ||
10857 | /** Returns the currently programmed mode of the given pipe. */ | |
10858 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10859 | struct drm_crtc *crtc) | |
10860 | { | |
fac5e23e | 10861 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 10862 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10863 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10864 | struct drm_display_mode *mode; |
3f36b937 | 10865 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10866 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10867 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10868 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10869 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10870 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10871 | |
10872 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10873 | if (!mode) | |
10874 | return NULL; | |
10875 | ||
3f36b937 TU |
10876 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10877 | if (!pipe_config) { | |
10878 | kfree(mode); | |
10879 | return NULL; | |
10880 | } | |
10881 | ||
f1f644dc JB |
10882 | /* |
10883 | * Construct a pipe_config sufficient for getting the clock info | |
10884 | * back out of crtc_clock_get. | |
10885 | * | |
10886 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10887 | * to use a real value here instead. | |
10888 | */ | |
3f36b937 TU |
10889 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10890 | pipe_config->pixel_multiplier = 1; | |
10891 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10892 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10893 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10894 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10895 | ||
10896 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10897 | mode->hdisplay = (htot & 0xffff) + 1; |
10898 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10899 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10900 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10901 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10902 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10903 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10904 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10905 | ||
10906 | drm_mode_set_name(mode); | |
79e53945 | 10907 | |
3f36b937 TU |
10908 | kfree(pipe_config); |
10909 | ||
79e53945 JB |
10910 | return mode; |
10911 | } | |
10912 | ||
10913 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
10914 | { | |
10915 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 10916 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 10917 | struct intel_flip_work *work; |
67e77c5a | 10918 | |
5e2d7afc | 10919 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
10920 | work = intel_crtc->flip_work; |
10921 | intel_crtc->flip_work = NULL; | |
10922 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 10923 | |
5a21b665 | 10924 | if (work) { |
51cbaf01 ML |
10925 | cancel_work_sync(&work->mmio_work); |
10926 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 10927 | kfree(work); |
67e77c5a | 10928 | } |
79e53945 JB |
10929 | |
10930 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10931 | |
79e53945 JB |
10932 | kfree(intel_crtc); |
10933 | } | |
10934 | ||
6b95a207 KH |
10935 | static void intel_unpin_work_fn(struct work_struct *__work) |
10936 | { | |
51cbaf01 ML |
10937 | struct intel_flip_work *work = |
10938 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
10939 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10940 | struct drm_device *dev = crtc->base.dev; | |
10941 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 10942 | |
5a21b665 DV |
10943 | if (is_mmio_work(work)) |
10944 | flush_work(&work->mmio_work); | |
03f476e1 | 10945 | |
5a21b665 DV |
10946 | mutex_lock(&dev->struct_mutex); |
10947 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); | |
f8c417cd | 10948 | i915_gem_object_put(work->pending_flip_obj); |
5a21b665 | 10949 | mutex_unlock(&dev->struct_mutex); |
143f73b3 | 10950 | |
e8a261ea CW |
10951 | i915_gem_request_put(work->flip_queued_req); |
10952 | ||
5a21b665 DV |
10953 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
10954 | intel_fbc_post_update(crtc); | |
10955 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 10956 | |
5a21b665 DV |
10957 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10958 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 10959 | |
5a21b665 DV |
10960 | kfree(work); |
10961 | } | |
d9e86c0e | 10962 | |
5a21b665 DV |
10963 | /* Is 'a' after or equal to 'b'? */ |
10964 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10965 | { | |
10966 | return !((a - b) & 0x80000000); | |
10967 | } | |
143f73b3 | 10968 | |
5a21b665 DV |
10969 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
10970 | struct intel_flip_work *work) | |
10971 | { | |
10972 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10973 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 10974 | unsigned reset_counter; |
143f73b3 | 10975 | |
5a21b665 DV |
10976 | reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
10977 | if (crtc->reset_counter != reset_counter) | |
10978 | return true; | |
143f73b3 | 10979 | |
5a21b665 DV |
10980 | /* |
10981 | * The relevant registers doen't exist on pre-ctg. | |
10982 | * As the flip done interrupt doesn't trigger for mmio | |
10983 | * flips on gmch platforms, a flip count check isn't | |
10984 | * really needed there. But since ctg has the registers, | |
10985 | * include it in the check anyway. | |
10986 | */ | |
10987 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10988 | return true; | |
b4a98e57 | 10989 | |
5a21b665 DV |
10990 | /* |
10991 | * BDW signals flip done immediately if the plane | |
10992 | * is disabled, even if the plane enable is already | |
10993 | * armed to occur at the next vblank :( | |
10994 | */ | |
f99d7069 | 10995 | |
5a21b665 DV |
10996 | /* |
10997 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10998 | * used the same base address. In that case the mmio flip might | |
10999 | * have completed, but the CS hasn't even executed the flip yet. | |
11000 | * | |
11001 | * A flip count check isn't enough as the CS might have updated | |
11002 | * the base address just after start of vblank, but before we | |
11003 | * managed to process the interrupt. This means we'd complete the | |
11004 | * CS flip too soon. | |
11005 | * | |
11006 | * Combining both checks should get us a good enough result. It may | |
11007 | * still happen that the CS flip has been executed, but has not | |
11008 | * yet actually completed. But in case the base address is the same | |
11009 | * anyway, we don't really care. | |
11010 | */ | |
11011 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11012 | crtc->flip_work->gtt_offset && | |
11013 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
11014 | crtc->flip_work->flip_count); | |
11015 | } | |
b4a98e57 | 11016 | |
5a21b665 DV |
11017 | static bool |
11018 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
11019 | struct intel_flip_work *work) | |
11020 | { | |
11021 | /* | |
11022 | * MMIO work completes when vblank is different from | |
11023 | * flip_queued_vblank. | |
11024 | * | |
11025 | * Reset counter value doesn't matter, this is handled by | |
11026 | * i915_wait_request finishing early, so no need to handle | |
11027 | * reset here. | |
11028 | */ | |
11029 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
11030 | } |
11031 | ||
51cbaf01 ML |
11032 | |
11033 | static bool pageflip_finished(struct intel_crtc *crtc, | |
11034 | struct intel_flip_work *work) | |
11035 | { | |
11036 | if (!atomic_read(&work->pending)) | |
11037 | return false; | |
11038 | ||
11039 | smp_rmb(); | |
11040 | ||
5a21b665 DV |
11041 | if (is_mmio_work(work)) |
11042 | return __pageflip_finished_mmio(crtc, work); | |
11043 | else | |
11044 | return __pageflip_finished_cs(crtc, work); | |
11045 | } | |
11046 | ||
11047 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
11048 | { | |
91c8a326 | 11049 | struct drm_device *dev = &dev_priv->drm; |
5a21b665 DV |
11050 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11051 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11052 | struct intel_flip_work *work; | |
11053 | unsigned long flags; | |
11054 | ||
11055 | /* Ignore early vblank irqs */ | |
11056 | if (!crtc) | |
11057 | return; | |
11058 | ||
51cbaf01 | 11059 | /* |
5a21b665 DV |
11060 | * This is called both by irq handlers and the reset code (to complete |
11061 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 11062 | */ |
5a21b665 DV |
11063 | spin_lock_irqsave(&dev->event_lock, flags); |
11064 | work = intel_crtc->flip_work; | |
11065 | ||
11066 | if (work != NULL && | |
11067 | !is_mmio_work(work) && | |
11068 | pageflip_finished(intel_crtc, work)) | |
11069 | page_flip_completed(intel_crtc); | |
11070 | ||
11071 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
11072 | } |
11073 | ||
51cbaf01 | 11074 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 11075 | { |
91c8a326 | 11076 | struct drm_device *dev = &dev_priv->drm; |
5251f04e ML |
11077 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11078 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
51cbaf01 | 11079 | struct intel_flip_work *work; |
6b95a207 KH |
11080 | unsigned long flags; |
11081 | ||
5251f04e ML |
11082 | /* Ignore early vblank irqs */ |
11083 | if (!crtc) | |
11084 | return; | |
f326038a DV |
11085 | |
11086 | /* | |
11087 | * This is called both by irq handlers and the reset code (to complete | |
11088 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 11089 | */ |
6b95a207 | 11090 | spin_lock_irqsave(&dev->event_lock, flags); |
5a21b665 | 11091 | work = intel_crtc->flip_work; |
5251f04e | 11092 | |
5a21b665 DV |
11093 | if (work != NULL && |
11094 | is_mmio_work(work) && | |
11095 | pageflip_finished(intel_crtc, work)) | |
11096 | page_flip_completed(intel_crtc); | |
5251f04e | 11097 | |
6b95a207 KH |
11098 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11099 | } | |
11100 | ||
5a21b665 DV |
11101 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
11102 | struct intel_flip_work *work) | |
84c33a64 | 11103 | { |
5a21b665 | 11104 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 11105 | |
5a21b665 DV |
11106 | /* Ensure that the work item is consistent when activating it ... */ |
11107 | smp_mb__before_atomic(); | |
11108 | atomic_set(&work->pending, 1); | |
11109 | } | |
a6747b73 | 11110 | |
5a21b665 DV |
11111 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11112 | struct drm_crtc *crtc, | |
11113 | struct drm_framebuffer *fb, | |
11114 | struct drm_i915_gem_object *obj, | |
11115 | struct drm_i915_gem_request *req, | |
11116 | uint32_t flags) | |
11117 | { | |
11118 | struct intel_engine_cs *engine = req->engine; | |
11119 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11120 | u32 flip_mask; | |
11121 | int ret; | |
143f73b3 | 11122 | |
5a21b665 DV |
11123 | ret = intel_ring_begin(req, 6); |
11124 | if (ret) | |
11125 | return ret; | |
143f73b3 | 11126 | |
5a21b665 DV |
11127 | /* Can't queue multiple flips, so wait for the previous |
11128 | * one to finish before executing the next. | |
11129 | */ | |
11130 | if (intel_crtc->plane) | |
11131 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11132 | else | |
11133 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
11134 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); | |
11135 | intel_ring_emit(engine, MI_NOOP); | |
11136 | intel_ring_emit(engine, MI_DISPLAY_FLIP | | |
11137 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11138 | intel_ring_emit(engine, fb->pitches[0]); | |
11139 | intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset); | |
11140 | intel_ring_emit(engine, 0); /* aux display base address, unused */ | |
143f73b3 | 11141 | |
5a21b665 DV |
11142 | return 0; |
11143 | } | |
84c33a64 | 11144 | |
5a21b665 DV |
11145 | static int intel_gen3_queue_flip(struct drm_device *dev, |
11146 | struct drm_crtc *crtc, | |
11147 | struct drm_framebuffer *fb, | |
11148 | struct drm_i915_gem_object *obj, | |
11149 | struct drm_i915_gem_request *req, | |
11150 | uint32_t flags) | |
11151 | { | |
11152 | struct intel_engine_cs *engine = req->engine; | |
11153 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11154 | u32 flip_mask; | |
11155 | int ret; | |
d55dbd06 | 11156 | |
5a21b665 DV |
11157 | ret = intel_ring_begin(req, 6); |
11158 | if (ret) | |
11159 | return ret; | |
d55dbd06 | 11160 | |
5a21b665 DV |
11161 | if (intel_crtc->plane) |
11162 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11163 | else | |
11164 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
11165 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); | |
11166 | intel_ring_emit(engine, MI_NOOP); | |
11167 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | | |
11168 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11169 | intel_ring_emit(engine, fb->pitches[0]); | |
11170 | intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset); | |
11171 | intel_ring_emit(engine, MI_NOOP); | |
fd8e058a | 11172 | |
5a21b665 DV |
11173 | return 0; |
11174 | } | |
84c33a64 | 11175 | |
5a21b665 DV |
11176 | static int intel_gen4_queue_flip(struct drm_device *dev, |
11177 | struct drm_crtc *crtc, | |
11178 | struct drm_framebuffer *fb, | |
11179 | struct drm_i915_gem_object *obj, | |
11180 | struct drm_i915_gem_request *req, | |
11181 | uint32_t flags) | |
11182 | { | |
11183 | struct intel_engine_cs *engine = req->engine; | |
fac5e23e | 11184 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11185 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11186 | uint32_t pf, pipesrc; | |
11187 | int ret; | |
143f73b3 | 11188 | |
5a21b665 DV |
11189 | ret = intel_ring_begin(req, 4); |
11190 | if (ret) | |
11191 | return ret; | |
143f73b3 | 11192 | |
5a21b665 DV |
11193 | /* i965+ uses the linear or tiled offsets from the |
11194 | * Display Registers (which do not change across a page-flip) | |
11195 | * so we need only reprogram the base address. | |
11196 | */ | |
11197 | intel_ring_emit(engine, MI_DISPLAY_FLIP | | |
11198 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11199 | intel_ring_emit(engine, fb->pitches[0]); | |
11200 | intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset | | |
11201 | obj->tiling_mode); | |
11202 | ||
11203 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11204 | * untested on non-native modes, so ignore it for now. | |
11205 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11206 | */ | |
11207 | pf = 0; | |
11208 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
11209 | intel_ring_emit(engine, pf | pipesrc); | |
143f73b3 | 11210 | |
5a21b665 | 11211 | return 0; |
8c9f3aaf JB |
11212 | } |
11213 | ||
5a21b665 DV |
11214 | static int intel_gen6_queue_flip(struct drm_device *dev, |
11215 | struct drm_crtc *crtc, | |
11216 | struct drm_framebuffer *fb, | |
11217 | struct drm_i915_gem_object *obj, | |
11218 | struct drm_i915_gem_request *req, | |
11219 | uint32_t flags) | |
da20eabd | 11220 | { |
5a21b665 | 11221 | struct intel_engine_cs *engine = req->engine; |
fac5e23e | 11222 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11223 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11224 | uint32_t pf, pipesrc; | |
11225 | int ret; | |
d21fbe87 | 11226 | |
5a21b665 DV |
11227 | ret = intel_ring_begin(req, 4); |
11228 | if (ret) | |
11229 | return ret; | |
92826fcd | 11230 | |
5a21b665 DV |
11231 | intel_ring_emit(engine, MI_DISPLAY_FLIP | |
11232 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11233 | intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode); | |
11234 | intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset); | |
92826fcd | 11235 | |
5a21b665 DV |
11236 | /* Contrary to the suggestions in the documentation, |
11237 | * "Enable Panel Fitter" does not seem to be required when page | |
11238 | * flipping with a non-native mode, and worse causes a normal | |
11239 | * modeset to fail. | |
11240 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11241 | */ | |
11242 | pf = 0; | |
11243 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
11244 | intel_ring_emit(engine, pf | pipesrc); | |
7809e5ae | 11245 | |
5a21b665 | 11246 | return 0; |
7809e5ae MR |
11247 | } |
11248 | ||
5a21b665 DV |
11249 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11250 | struct drm_crtc *crtc, | |
11251 | struct drm_framebuffer *fb, | |
11252 | struct drm_i915_gem_object *obj, | |
11253 | struct drm_i915_gem_request *req, | |
11254 | uint32_t flags) | |
d21fbe87 | 11255 | { |
5a21b665 DV |
11256 | struct intel_engine_cs *engine = req->engine; |
11257 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11258 | uint32_t plane_bit = 0; | |
11259 | int len, ret; | |
d21fbe87 | 11260 | |
5a21b665 DV |
11261 | switch (intel_crtc->plane) { |
11262 | case PLANE_A: | |
11263 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11264 | break; | |
11265 | case PLANE_B: | |
11266 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11267 | break; | |
11268 | case PLANE_C: | |
11269 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11270 | break; | |
11271 | default: | |
11272 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
11273 | return -ENODEV; | |
11274 | } | |
11275 | ||
11276 | len = 4; | |
11277 | if (engine->id == RCS) { | |
11278 | len += 6; | |
11279 | /* | |
11280 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11281 | * 48bits addresses, and we need a NOOP for the batch size to | |
11282 | * stay even. | |
11283 | */ | |
11284 | if (IS_GEN8(dev)) | |
11285 | len += 2; | |
11286 | } | |
11287 | ||
11288 | /* | |
11289 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11290 | * "The full packet must be contained within the same cache line." | |
11291 | * | |
11292 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11293 | * cacheline, if we ever start emitting more commands before | |
11294 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11295 | * then do the cacheline alignment, and finally emit the | |
11296 | * MI_DISPLAY_FLIP. | |
11297 | */ | |
11298 | ret = intel_ring_cacheline_align(req); | |
11299 | if (ret) | |
11300 | return ret; | |
11301 | ||
11302 | ret = intel_ring_begin(req, len); | |
11303 | if (ret) | |
11304 | return ret; | |
11305 | ||
11306 | /* Unmask the flip-done completion message. Note that the bspec says that | |
11307 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11308 | * more than one flip event at any time (or ensure that one flip message | |
11309 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11310 | * Experimentation says that BCS works despite DERRMR masking all | |
11311 | * flip-done completion events and that unmasking all planes at once | |
11312 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11313 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11314 | */ | |
11315 | if (engine->id == RCS) { | |
11316 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); | |
11317 | intel_ring_emit_reg(engine, DERRMR); | |
11318 | intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
11319 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11320 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
11321 | if (IS_GEN8(dev)) | |
11322 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 | | |
11323 | MI_SRM_LRM_GLOBAL_GTT); | |
11324 | else | |
11325 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM | | |
11326 | MI_SRM_LRM_GLOBAL_GTT); | |
11327 | intel_ring_emit_reg(engine, DERRMR); | |
11328 | intel_ring_emit(engine, engine->scratch.gtt_offset + 256); | |
11329 | if (IS_GEN8(dev)) { | |
11330 | intel_ring_emit(engine, 0); | |
11331 | intel_ring_emit(engine, MI_NOOP); | |
11332 | } | |
11333 | } | |
11334 | ||
11335 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit); | |
11336 | intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode)); | |
11337 | intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset); | |
11338 | intel_ring_emit(engine, (MI_NOOP)); | |
11339 | ||
11340 | return 0; | |
11341 | } | |
11342 | ||
11343 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
11344 | struct drm_i915_gem_object *obj) | |
11345 | { | |
c37efb99 CW |
11346 | struct reservation_object *resv; |
11347 | ||
5a21b665 DV |
11348 | /* |
11349 | * This is not being used for older platforms, because | |
11350 | * non-availability of flip done interrupt forces us to use | |
11351 | * CS flips. Older platforms derive flip done using some clever | |
11352 | * tricks involving the flip_pending status bits and vblank irqs. | |
11353 | * So using MMIO flips there would disrupt this mechanism. | |
11354 | */ | |
11355 | ||
11356 | if (engine == NULL) | |
11357 | return true; | |
11358 | ||
11359 | if (INTEL_GEN(engine->i915) < 5) | |
11360 | return false; | |
11361 | ||
11362 | if (i915.use_mmio_flip < 0) | |
11363 | return false; | |
11364 | else if (i915.use_mmio_flip > 0) | |
11365 | return true; | |
11366 | else if (i915.enable_execlists) | |
11367 | return true; | |
c37efb99 CW |
11368 | |
11369 | resv = i915_gem_object_get_dmabuf_resv(obj); | |
11370 | if (resv && !reservation_object_test_signaled_rcu(resv, false)) | |
5a21b665 | 11371 | return true; |
c37efb99 CW |
11372 | |
11373 | return engine != i915_gem_request_get_engine(obj->last_write_req); | |
5a21b665 DV |
11374 | } |
11375 | ||
11376 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11377 | unsigned int rotation, | |
11378 | struct intel_flip_work *work) | |
11379 | { | |
11380 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11381 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11382 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
11383 | const enum pipe pipe = intel_crtc->pipe; | |
11384 | u32 ctl, stride, tile_height; | |
11385 | ||
11386 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11387 | ctl &= ~PLANE_CTL_TILED_MASK; | |
11388 | switch (fb->modifier[0]) { | |
11389 | case DRM_FORMAT_MOD_NONE: | |
11390 | break; | |
11391 | case I915_FORMAT_MOD_X_TILED: | |
11392 | ctl |= PLANE_CTL_TILED_X; | |
11393 | break; | |
11394 | case I915_FORMAT_MOD_Y_TILED: | |
11395 | ctl |= PLANE_CTL_TILED_Y; | |
11396 | break; | |
11397 | case I915_FORMAT_MOD_Yf_TILED: | |
11398 | ctl |= PLANE_CTL_TILED_YF; | |
11399 | break; | |
11400 | default: | |
11401 | MISSING_CASE(fb->modifier[0]); | |
11402 | } | |
11403 | ||
11404 | /* | |
11405 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11406 | * linear buffers or in number of tiles for tiled buffers. | |
11407 | */ | |
11408 | if (intel_rotation_90_or_270(rotation)) { | |
11409 | /* stride = Surface height in tiles */ | |
11410 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); | |
11411 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
11412 | } else { | |
11413 | stride = fb->pitches[0] / | |
11414 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], | |
11415 | fb->pixel_format); | |
11416 | } | |
11417 | ||
11418 | /* | |
11419 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11420 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11421 | */ | |
11422 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11423 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11424 | ||
11425 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
11426 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
11427 | } | |
11428 | ||
11429 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11430 | struct intel_flip_work *work) | |
11431 | { | |
11432 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11433 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11434 | struct intel_framebuffer *intel_fb = |
11435 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11436 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11437 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); | |
11438 | u32 dspcntr; | |
11439 | ||
11440 | dspcntr = I915_READ(reg); | |
11441 | ||
11442 | if (obj->tiling_mode != I915_TILING_NONE) | |
11443 | dspcntr |= DISPPLANE_TILED; | |
11444 | else | |
11445 | dspcntr &= ~DISPPLANE_TILED; | |
11446 | ||
11447 | I915_WRITE(reg, dspcntr); | |
11448 | ||
11449 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
11450 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
11451 | } | |
11452 | ||
11453 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
11454 | { | |
11455 | struct intel_flip_work *work = | |
11456 | container_of(w, struct intel_flip_work, mmio_work); | |
11457 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
11458 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
11459 | struct intel_framebuffer *intel_fb = | |
11460 | to_intel_framebuffer(crtc->base.primary->fb); | |
11461 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
c37efb99 | 11462 | struct reservation_object *resv; |
5a21b665 DV |
11463 | |
11464 | if (work->flip_queued_req) | |
11465 | WARN_ON(__i915_wait_request(work->flip_queued_req, | |
11466 | false, NULL, | |
197be2ae | 11467 | NO_WAITBOOST)); |
5a21b665 DV |
11468 | |
11469 | /* For framebuffer backed by dmabuf, wait for fence */ | |
c37efb99 CW |
11470 | resv = i915_gem_object_get_dmabuf_resv(obj); |
11471 | if (resv) | |
11472 | WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false, | |
5a21b665 DV |
11473 | MAX_SCHEDULE_TIMEOUT) < 0); |
11474 | ||
11475 | intel_pipe_update_start(crtc); | |
11476 | ||
11477 | if (INTEL_GEN(dev_priv) >= 9) | |
11478 | skl_do_mmio_flip(crtc, work->rotation, work); | |
11479 | else | |
11480 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
11481 | ilk_do_mmio_flip(crtc, work); | |
11482 | ||
11483 | intel_pipe_update_end(crtc, work); | |
11484 | } | |
11485 | ||
11486 | static int intel_default_queue_flip(struct drm_device *dev, | |
11487 | struct drm_crtc *crtc, | |
11488 | struct drm_framebuffer *fb, | |
11489 | struct drm_i915_gem_object *obj, | |
11490 | struct drm_i915_gem_request *req, | |
11491 | uint32_t flags) | |
11492 | { | |
11493 | return -ENODEV; | |
11494 | } | |
11495 | ||
11496 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
11497 | struct intel_crtc *intel_crtc, | |
11498 | struct intel_flip_work *work) | |
11499 | { | |
11500 | u32 addr, vblank; | |
11501 | ||
11502 | if (!atomic_read(&work->pending)) | |
11503 | return false; | |
11504 | ||
11505 | smp_rmb(); | |
11506 | ||
11507 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
11508 | if (work->flip_ready_vblank == 0) { | |
11509 | if (work->flip_queued_req && | |
f69a02c9 | 11510 | !i915_gem_request_completed(work->flip_queued_req)) |
5a21b665 DV |
11511 | return false; |
11512 | ||
11513 | work->flip_ready_vblank = vblank; | |
11514 | } | |
11515 | ||
11516 | if (vblank - work->flip_ready_vblank < 3) | |
11517 | return false; | |
11518 | ||
11519 | /* Potential stall - if we see that the flip has happened, | |
11520 | * assume a missed interrupt. */ | |
11521 | if (INTEL_GEN(dev_priv) >= 4) | |
11522 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11523 | else | |
11524 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11525 | ||
11526 | /* There is a potential issue here with a false positive after a flip | |
11527 | * to the same address. We could address this by checking for a | |
11528 | * non-incrementing frame counter. | |
11529 | */ | |
11530 | return addr == work->gtt_offset; | |
11531 | } | |
11532 | ||
11533 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
11534 | { | |
91c8a326 | 11535 | struct drm_device *dev = &dev_priv->drm; |
5a21b665 DV |
11536 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11537 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11538 | struct intel_flip_work *work; | |
11539 | ||
11540 | WARN_ON(!in_interrupt()); | |
11541 | ||
11542 | if (crtc == NULL) | |
11543 | return; | |
11544 | ||
11545 | spin_lock(&dev->event_lock); | |
11546 | work = intel_crtc->flip_work; | |
11547 | ||
11548 | if (work != NULL && !is_mmio_work(work) && | |
11549 | __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) { | |
11550 | WARN_ONCE(1, | |
11551 | "Kicking stuck page flip: queued at %d, now %d\n", | |
11552 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc)); | |
11553 | page_flip_completed(intel_crtc); | |
11554 | work = NULL; | |
11555 | } | |
11556 | ||
11557 | if (work != NULL && !is_mmio_work(work) && | |
11558 | intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1) | |
11559 | intel_queue_rps_boost_for_request(work->flip_queued_req); | |
11560 | spin_unlock(&dev->event_lock); | |
11561 | } | |
11562 | ||
11563 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
11564 | struct drm_framebuffer *fb, | |
11565 | struct drm_pending_vblank_event *event, | |
11566 | uint32_t page_flip_flags) | |
11567 | { | |
11568 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 11569 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11570 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
11571 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
11572 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11573 | struct drm_plane *primary = crtc->primary; | |
11574 | enum pipe pipe = intel_crtc->pipe; | |
11575 | struct intel_flip_work *work; | |
11576 | struct intel_engine_cs *engine; | |
11577 | bool mmio_flip; | |
11578 | struct drm_i915_gem_request *request = NULL; | |
11579 | int ret; | |
11580 | ||
11581 | /* | |
11582 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11583 | * check to be safe. In the future we may enable pageflipping from | |
11584 | * a disabled primary plane. | |
11585 | */ | |
11586 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11587 | return -EBUSY; | |
11588 | ||
11589 | /* Can't change pixel format via MI display flips. */ | |
11590 | if (fb->pixel_format != crtc->primary->fb->pixel_format) | |
11591 | return -EINVAL; | |
11592 | ||
11593 | /* | |
11594 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11595 | * Note that pitch changes could also affect these register. | |
11596 | */ | |
11597 | if (INTEL_INFO(dev)->gen > 3 && | |
11598 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || | |
11599 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
11600 | return -EINVAL; | |
11601 | ||
11602 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
11603 | goto out_hang; | |
11604 | ||
11605 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
11606 | if (work == NULL) | |
11607 | return -ENOMEM; | |
11608 | ||
11609 | work->event = event; | |
11610 | work->crtc = crtc; | |
11611 | work->old_fb = old_fb; | |
11612 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
11613 | ||
11614 | ret = drm_crtc_vblank_get(crtc); | |
11615 | if (ret) | |
11616 | goto free_work; | |
11617 | ||
11618 | /* We borrow the event spin lock for protecting flip_work */ | |
11619 | spin_lock_irq(&dev->event_lock); | |
11620 | if (intel_crtc->flip_work) { | |
11621 | /* Before declaring the flip queue wedged, check if | |
11622 | * the hardware completed the operation behind our backs. | |
11623 | */ | |
11624 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
11625 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11626 | page_flip_completed(intel_crtc); | |
11627 | } else { | |
11628 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
11629 | spin_unlock_irq(&dev->event_lock); | |
11630 | ||
11631 | drm_crtc_vblank_put(crtc); | |
11632 | kfree(work); | |
11633 | return -EBUSY; | |
11634 | } | |
11635 | } | |
11636 | intel_crtc->flip_work = work; | |
11637 | spin_unlock_irq(&dev->event_lock); | |
11638 | ||
11639 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
11640 | flush_workqueue(dev_priv->wq); | |
11641 | ||
11642 | /* Reference the objects for the scheduled work. */ | |
11643 | drm_framebuffer_reference(work->old_fb); | |
5a21b665 DV |
11644 | |
11645 | crtc->primary->fb = fb; | |
11646 | update_state_fb(crtc->primary); | |
faf68d92 ML |
11647 | |
11648 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
11649 | to_intel_plane_state(primary->state)); | |
5a21b665 | 11650 | |
25dc556a | 11651 | work->pending_flip_obj = i915_gem_object_get(obj); |
5a21b665 DV |
11652 | |
11653 | ret = i915_mutex_lock_interruptible(dev); | |
11654 | if (ret) | |
11655 | goto cleanup; | |
11656 | ||
11657 | intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error); | |
11658 | if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) { | |
11659 | ret = -EIO; | |
11660 | goto cleanup; | |
11661 | } | |
11662 | ||
11663 | atomic_inc(&intel_crtc->unpin_work_count); | |
11664 | ||
11665 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
11666 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; | |
11667 | ||
11668 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { | |
11669 | engine = &dev_priv->engine[BCS]; | |
11670 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) | |
11671 | /* vlv: DISPLAY_FLIP fails to change tiling */ | |
11672 | engine = NULL; | |
11673 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { | |
11674 | engine = &dev_priv->engine[BCS]; | |
11675 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
11676 | engine = i915_gem_request_get_engine(obj->last_write_req); | |
11677 | if (engine == NULL || engine->id != RCS) | |
11678 | engine = &dev_priv->engine[BCS]; | |
11679 | } else { | |
11680 | engine = &dev_priv->engine[RCS]; | |
11681 | } | |
11682 | ||
11683 | mmio_flip = use_mmio_flip(engine, obj); | |
11684 | ||
11685 | /* When using CS flips, we want to emit semaphores between rings. | |
11686 | * However, when using mmio flips we will create a task to do the | |
11687 | * synchronisation, so all we want here is to pin the framebuffer | |
11688 | * into the display plane and skip any waits. | |
11689 | */ | |
11690 | if (!mmio_flip) { | |
11691 | ret = i915_gem_object_sync(obj, engine, &request); | |
11692 | if (!ret && !request) { | |
11693 | request = i915_gem_request_alloc(engine, NULL); | |
11694 | ret = PTR_ERR_OR_ZERO(request); | |
11695 | } | |
11696 | ||
11697 | if (ret) | |
11698 | goto cleanup_pending; | |
11699 | } | |
11700 | ||
11701 | ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); | |
11702 | if (ret) | |
11703 | goto cleanup_pending; | |
11704 | ||
11705 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), | |
11706 | obj, 0); | |
11707 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
11708 | work->rotation = crtc->primary->state->rotation; | |
11709 | ||
11710 | if (mmio_flip) { | |
11711 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
11712 | ||
11713 | i915_gem_request_assign(&work->flip_queued_req, | |
11714 | obj->last_write_req); | |
11715 | ||
11716 | schedule_work(&work->mmio_work); | |
11717 | } else { | |
11718 | i915_gem_request_assign(&work->flip_queued_req, request); | |
11719 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
11720 | page_flip_flags); | |
11721 | if (ret) | |
11722 | goto cleanup_unpin; | |
11723 | ||
11724 | intel_mark_page_flip_active(intel_crtc, work); | |
11725 | ||
11726 | i915_add_request_no_flush(request); | |
11727 | } | |
11728 | ||
11729 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, | |
11730 | to_intel_plane(primary)->frontbuffer_bit); | |
11731 | mutex_unlock(&dev->struct_mutex); | |
11732 | ||
11733 | intel_frontbuffer_flip_prepare(dev, | |
11734 | to_intel_plane(primary)->frontbuffer_bit); | |
11735 | ||
11736 | trace_i915_flip_request(intel_crtc->plane, obj); | |
11737 | ||
11738 | return 0; | |
11739 | ||
11740 | cleanup_unpin: | |
11741 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); | |
11742 | cleanup_pending: | |
11743 | if (!IS_ERR_OR_NULL(request)) | |
11744 | i915_add_request_no_flush(request); | |
11745 | atomic_dec(&intel_crtc->unpin_work_count); | |
11746 | mutex_unlock(&dev->struct_mutex); | |
11747 | cleanup: | |
11748 | crtc->primary->fb = old_fb; | |
11749 | update_state_fb(crtc->primary); | |
11750 | ||
34911fd3 | 11751 | i915_gem_object_put_unlocked(obj); |
5a21b665 DV |
11752 | drm_framebuffer_unreference(work->old_fb); |
11753 | ||
11754 | spin_lock_irq(&dev->event_lock); | |
11755 | intel_crtc->flip_work = NULL; | |
11756 | spin_unlock_irq(&dev->event_lock); | |
11757 | ||
11758 | drm_crtc_vblank_put(crtc); | |
11759 | free_work: | |
11760 | kfree(work); | |
11761 | ||
11762 | if (ret == -EIO) { | |
11763 | struct drm_atomic_state *state; | |
11764 | struct drm_plane_state *plane_state; | |
11765 | ||
11766 | out_hang: | |
11767 | state = drm_atomic_state_alloc(dev); | |
11768 | if (!state) | |
11769 | return -ENOMEM; | |
11770 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11771 | ||
11772 | retry: | |
11773 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11774 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11775 | if (!ret) { | |
11776 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11777 | ||
11778 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11779 | if (!ret) | |
11780 | ret = drm_atomic_commit(state); | |
11781 | } | |
11782 | ||
11783 | if (ret == -EDEADLK) { | |
11784 | drm_modeset_backoff(state->acquire_ctx); | |
11785 | drm_atomic_state_clear(state); | |
11786 | goto retry; | |
11787 | } | |
11788 | ||
11789 | if (ret) | |
11790 | drm_atomic_state_free(state); | |
11791 | ||
11792 | if (ret == 0 && event) { | |
11793 | spin_lock_irq(&dev->event_lock); | |
11794 | drm_crtc_send_vblank_event(crtc, event); | |
11795 | spin_unlock_irq(&dev->event_lock); | |
11796 | } | |
11797 | } | |
11798 | return ret; | |
11799 | } | |
11800 | ||
11801 | ||
11802 | /** | |
11803 | * intel_wm_need_update - Check whether watermarks need updating | |
11804 | * @plane: drm plane | |
11805 | * @state: new plane state | |
11806 | * | |
11807 | * Check current plane state versus the new one to determine whether | |
11808 | * watermarks need to be recalculated. | |
11809 | * | |
11810 | * Returns true or false. | |
11811 | */ | |
11812 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11813 | struct drm_plane_state *state) | |
11814 | { | |
11815 | struct intel_plane_state *new = to_intel_plane_state(state); | |
11816 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11817 | ||
11818 | /* Update watermarks on tiling or size changes. */ | |
11819 | if (new->visible != cur->visible) | |
11820 | return true; | |
11821 | ||
11822 | if (!cur->base.fb || !new->base.fb) | |
11823 | return false; | |
11824 | ||
11825 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11826 | cur->base.rotation != new->base.rotation || | |
11827 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || | |
11828 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11829 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11830 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
11831 | return true; | |
11832 | ||
11833 | return false; | |
11834 | } | |
11835 | ||
11836 | static bool needs_scaling(struct intel_plane_state *state) | |
11837 | { | |
11838 | int src_w = drm_rect_width(&state->src) >> 16; | |
11839 | int src_h = drm_rect_height(&state->src) >> 16; | |
11840 | int dst_w = drm_rect_width(&state->dst); | |
11841 | int dst_h = drm_rect_height(&state->dst); | |
11842 | ||
11843 | return (src_w != dst_w || src_h != dst_h); | |
11844 | } | |
d21fbe87 | 11845 | |
da20eabd ML |
11846 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11847 | struct drm_plane_state *plane_state) | |
11848 | { | |
ab1d3a0e | 11849 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11850 | struct drm_crtc *crtc = crtc_state->crtc; |
11851 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11852 | struct drm_plane *plane = plane_state->plane; | |
11853 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 11854 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
11855 | struct intel_plane_state *old_plane_state = |
11856 | to_intel_plane_state(plane->state); | |
da20eabd ML |
11857 | bool mode_changed = needs_modeset(crtc_state); |
11858 | bool was_crtc_enabled = crtc->state->active; | |
11859 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11860 | bool turn_off, turn_on, visible, was_visible; |
11861 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 11862 | int ret; |
da20eabd | 11863 | |
84114990 | 11864 | if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { |
da20eabd ML |
11865 | ret = skl_update_scaler_plane( |
11866 | to_intel_crtc_state(crtc_state), | |
11867 | to_intel_plane_state(plane_state)); | |
11868 | if (ret) | |
11869 | return ret; | |
11870 | } | |
11871 | ||
da20eabd ML |
11872 | was_visible = old_plane_state->visible; |
11873 | visible = to_intel_plane_state(plane_state)->visible; | |
11874 | ||
11875 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11876 | was_visible = false; | |
11877 | ||
35c08f43 ML |
11878 | /* |
11879 | * Visibility is calculated as if the crtc was on, but | |
11880 | * after scaler setup everything depends on it being off | |
11881 | * when the crtc isn't active. | |
f818ffea VS |
11882 | * |
11883 | * FIXME this is wrong for watermarks. Watermarks should also | |
11884 | * be computed as if the pipe would be active. Perhaps move | |
11885 | * per-plane wm computation to the .check_plane() hook, and | |
11886 | * only combine the results from all planes in the current place? | |
35c08f43 ML |
11887 | */ |
11888 | if (!is_crtc_enabled) | |
11889 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11890 | |
11891 | if (!was_visible && !visible) | |
11892 | return 0; | |
11893 | ||
e8861675 ML |
11894 | if (fb != old_plane_state->base.fb) |
11895 | pipe_config->fb_changed = true; | |
11896 | ||
da20eabd ML |
11897 | turn_off = was_visible && (!visible || mode_changed); |
11898 | turn_on = visible && (!was_visible || mode_changed); | |
11899 | ||
72660ce0 | 11900 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
78108b7c VS |
11901 | intel_crtc->base.base.id, |
11902 | intel_crtc->base.name, | |
72660ce0 VS |
11903 | plane->base.id, plane->name, |
11904 | fb ? fb->base.id : -1); | |
da20eabd | 11905 | |
72660ce0 VS |
11906 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
11907 | plane->base.id, plane->name, | |
11908 | was_visible, visible, | |
da20eabd ML |
11909 | turn_off, turn_on, mode_changed); |
11910 | ||
caed361d VS |
11911 | if (turn_on) { |
11912 | pipe_config->update_wm_pre = true; | |
11913 | ||
11914 | /* must disable cxsr around plane enable/disable */ | |
11915 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
11916 | pipe_config->disable_cxsr = true; | |
11917 | } else if (turn_off) { | |
11918 | pipe_config->update_wm_post = true; | |
92826fcd | 11919 | |
852eb00d | 11920 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 11921 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 11922 | pipe_config->disable_cxsr = true; |
852eb00d | 11923 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
11924 | /* FIXME bollocks */ |
11925 | pipe_config->update_wm_pre = true; | |
11926 | pipe_config->update_wm_post = true; | |
852eb00d | 11927 | } |
da20eabd | 11928 | |
ed4a6a7c | 11929 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d VS |
11930 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
11931 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
ed4a6a7c MR |
11932 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
11933 | ||
8be6ca85 | 11934 | if (visible || was_visible) |
cd202f69 | 11935 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 11936 | |
31ae71fc ML |
11937 | /* |
11938 | * WaCxSRDisabledForSpriteScaling:ivb | |
11939 | * | |
11940 | * cstate->update_wm was already set above, so this flag will | |
11941 | * take effect when we commit and program watermarks. | |
11942 | */ | |
11943 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && | |
11944 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11945 | !needs_scaling(old_plane_state)) | |
11946 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 11947 | |
da20eabd ML |
11948 | return 0; |
11949 | } | |
11950 | ||
6d3a1ce7 ML |
11951 | static bool encoders_cloneable(const struct intel_encoder *a, |
11952 | const struct intel_encoder *b) | |
11953 | { | |
11954 | /* masks could be asymmetric, so check both ways */ | |
11955 | return a == b || (a->cloneable & (1 << b->type) && | |
11956 | b->cloneable & (1 << a->type)); | |
11957 | } | |
11958 | ||
11959 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11960 | struct intel_crtc *crtc, | |
11961 | struct intel_encoder *encoder) | |
11962 | { | |
11963 | struct intel_encoder *source_encoder; | |
11964 | struct drm_connector *connector; | |
11965 | struct drm_connector_state *connector_state; | |
11966 | int i; | |
11967 | ||
11968 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11969 | if (connector_state->crtc != &crtc->base) | |
11970 | continue; | |
11971 | ||
11972 | source_encoder = | |
11973 | to_intel_encoder(connector_state->best_encoder); | |
11974 | if (!encoders_cloneable(encoder, source_encoder)) | |
11975 | return false; | |
11976 | } | |
11977 | ||
11978 | return true; | |
11979 | } | |
11980 | ||
6d3a1ce7 ML |
11981 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
11982 | struct drm_crtc_state *crtc_state) | |
11983 | { | |
cf5a15be | 11984 | struct drm_device *dev = crtc->dev; |
fac5e23e | 11985 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 11986 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11987 | struct intel_crtc_state *pipe_config = |
11988 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11989 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11990 | int ret; |
6d3a1ce7 ML |
11991 | bool mode_changed = needs_modeset(crtc_state); |
11992 | ||
852eb00d | 11993 | if (mode_changed && !crtc_state->active) |
caed361d | 11994 | pipe_config->update_wm_post = true; |
eddfcbcd | 11995 | |
ad421372 ML |
11996 | if (mode_changed && crtc_state->enable && |
11997 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 11998 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
11999 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
12000 | pipe_config); | |
12001 | if (ret) | |
12002 | return ret; | |
12003 | } | |
12004 | ||
82cf435b LL |
12005 | if (crtc_state->color_mgmt_changed) { |
12006 | ret = intel_color_check(crtc, crtc_state); | |
12007 | if (ret) | |
12008 | return ret; | |
e7852a4b LL |
12009 | |
12010 | /* | |
12011 | * Changing color management on Intel hardware is | |
12012 | * handled as part of planes update. | |
12013 | */ | |
12014 | crtc_state->planes_changed = true; | |
82cf435b LL |
12015 | } |
12016 | ||
e435d6e5 | 12017 | ret = 0; |
86c8bbbe | 12018 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 12019 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
12020 | if (ret) { |
12021 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
12022 | return ret; | |
12023 | } | |
12024 | } | |
12025 | ||
12026 | if (dev_priv->display.compute_intermediate_wm && | |
12027 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
12028 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
12029 | return 0; | |
12030 | ||
12031 | /* | |
12032 | * Calculate 'intermediate' watermarks that satisfy both the | |
12033 | * old state and the new state. We can program these | |
12034 | * immediately. | |
12035 | */ | |
12036 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
12037 | intel_crtc, | |
12038 | pipe_config); | |
12039 | if (ret) { | |
12040 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12041 | return ret; |
ed4a6a7c | 12042 | } |
e3d5457c VS |
12043 | } else if (dev_priv->display.compute_intermediate_wm) { |
12044 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
12045 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
12046 | } |
12047 | ||
e435d6e5 ML |
12048 | if (INTEL_INFO(dev)->gen >= 9) { |
12049 | if (mode_changed) | |
12050 | ret = skl_update_scaler_crtc(pipe_config); | |
12051 | ||
12052 | if (!ret) | |
12053 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12054 | pipe_config); | |
12055 | } | |
12056 | ||
12057 | return ret; | |
6d3a1ce7 ML |
12058 | } |
12059 | ||
65b38e0d | 12060 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 12061 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
5a21b665 DV |
12062 | .atomic_begin = intel_begin_crtc_commit, |
12063 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12064 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12065 | }; |
12066 | ||
d29b2f9d ACO |
12067 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12068 | { | |
12069 | struct intel_connector *connector; | |
12070 | ||
12071 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
12072 | if (connector->base.state->crtc) |
12073 | drm_connector_unreference(&connector->base); | |
12074 | ||
d29b2f9d ACO |
12075 | if (connector->base.encoder) { |
12076 | connector->base.state->best_encoder = | |
12077 | connector->base.encoder; | |
12078 | connector->base.state->crtc = | |
12079 | connector->base.encoder->crtc; | |
8863dc7f DV |
12080 | |
12081 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
12082 | } else { |
12083 | connector->base.state->best_encoder = NULL; | |
12084 | connector->base.state->crtc = NULL; | |
12085 | } | |
12086 | } | |
12087 | } | |
12088 | ||
050f7aeb | 12089 | static void |
eba905b2 | 12090 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12091 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12092 | { |
12093 | int bpp = pipe_config->pipe_bpp; | |
12094 | ||
12095 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12096 | connector->base.base.id, | |
c23cc417 | 12097 | connector->base.name); |
050f7aeb DV |
12098 | |
12099 | /* Don't use an invalid EDID bpc value */ | |
12100 | if (connector->base.display_info.bpc && | |
12101 | connector->base.display_info.bpc * 3 < bpp) { | |
12102 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12103 | bpp, connector->base.display_info.bpc*3); | |
12104 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12105 | } | |
12106 | ||
013dd9e0 JN |
12107 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12108 | if (connector->base.display_info.bpc == 0) { | |
12109 | int type = connector->base.connector_type; | |
12110 | int clamp_bpp = 24; | |
12111 | ||
12112 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12113 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12114 | type == DRM_MODE_CONNECTOR_eDP) | |
12115 | clamp_bpp = 18; | |
12116 | ||
12117 | if (bpp > clamp_bpp) { | |
12118 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12119 | bpp, clamp_bpp); | |
12120 | pipe_config->pipe_bpp = clamp_bpp; | |
12121 | } | |
050f7aeb DV |
12122 | } |
12123 | } | |
12124 | ||
4e53c2e0 | 12125 | static int |
050f7aeb | 12126 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12127 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12128 | { |
050f7aeb | 12129 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12130 | struct drm_atomic_state *state; |
da3ced29 ACO |
12131 | struct drm_connector *connector; |
12132 | struct drm_connector_state *connector_state; | |
1486017f | 12133 | int bpp, i; |
4e53c2e0 | 12134 | |
666a4537 | 12135 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12136 | bpp = 10*3; |
d328c9d7 DV |
12137 | else if (INTEL_INFO(dev)->gen >= 5) |
12138 | bpp = 12*3; | |
12139 | else | |
12140 | bpp = 8*3; | |
12141 | ||
4e53c2e0 | 12142 | |
4e53c2e0 DV |
12143 | pipe_config->pipe_bpp = bpp; |
12144 | ||
1486017f ACO |
12145 | state = pipe_config->base.state; |
12146 | ||
4e53c2e0 | 12147 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12148 | for_each_connector_in_state(state, connector, connector_state, i) { |
12149 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12150 | continue; |
12151 | ||
da3ced29 ACO |
12152 | connected_sink_compute_bpp(to_intel_connector(connector), |
12153 | pipe_config); | |
4e53c2e0 DV |
12154 | } |
12155 | ||
12156 | return bpp; | |
12157 | } | |
12158 | ||
644db711 DV |
12159 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12160 | { | |
12161 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12162 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12163 | mode->crtc_clock, |
644db711 DV |
12164 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12165 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12166 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12167 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12168 | } | |
12169 | ||
c0b03411 | 12170 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12171 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12172 | const char *context) |
12173 | { | |
6a60cd87 CK |
12174 | struct drm_device *dev = crtc->base.dev; |
12175 | struct drm_plane *plane; | |
12176 | struct intel_plane *intel_plane; | |
12177 | struct intel_plane_state *state; | |
12178 | struct drm_framebuffer *fb; | |
12179 | ||
78108b7c VS |
12180 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n", |
12181 | crtc->base.base.id, crtc->base.name, | |
6a60cd87 | 12182 | context, pipe_config, pipe_name(crtc->pipe)); |
c0b03411 | 12183 | |
da205630 | 12184 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
c0b03411 DV |
12185 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
12186 | pipe_config->pipe_bpp, pipe_config->dither); | |
12187 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12188 | pipe_config->has_pch_encoder, | |
12189 | pipe_config->fdi_lanes, | |
12190 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12191 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12192 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12193 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
37a5650b | 12194 | intel_crtc_has_dp_encoder(pipe_config), |
90a6b7b0 | 12195 | pipe_config->lane_count, |
eb14cb74 VS |
12196 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12197 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12198 | pipe_config->dp_m_n.tu); | |
b95af8be | 12199 | |
90a6b7b0 | 12200 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
37a5650b | 12201 | intel_crtc_has_dp_encoder(pipe_config), |
90a6b7b0 | 12202 | pipe_config->lane_count, |
b95af8be VK |
12203 | pipe_config->dp_m2_n2.gmch_m, |
12204 | pipe_config->dp_m2_n2.gmch_n, | |
12205 | pipe_config->dp_m2_n2.link_m, | |
12206 | pipe_config->dp_m2_n2.link_n, | |
12207 | pipe_config->dp_m2_n2.tu); | |
12208 | ||
55072d19 DV |
12209 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12210 | pipe_config->has_audio, | |
12211 | pipe_config->has_infoframe); | |
12212 | ||
c0b03411 | 12213 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12214 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12215 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12216 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12217 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12218 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12219 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12220 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12221 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12222 | crtc->num_scalers, | |
12223 | pipe_config->scaler_state.scaler_users, | |
12224 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12225 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12226 | pipe_config->gmch_pfit.control, | |
12227 | pipe_config->gmch_pfit.pgm_ratios, | |
12228 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12229 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12230 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12231 | pipe_config->pch_pfit.size, |
12232 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12233 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12234 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12235 | |
415ff0f6 | 12236 | if (IS_BROXTON(dev)) { |
05712c15 | 12237 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12238 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12239 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12240 | pipe_config->ddi_pll_sel, |
12241 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12242 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12243 | pipe_config->dpll_hw_state.pll0, |
12244 | pipe_config->dpll_hw_state.pll1, | |
12245 | pipe_config->dpll_hw_state.pll2, | |
12246 | pipe_config->dpll_hw_state.pll3, | |
12247 | pipe_config->dpll_hw_state.pll6, | |
12248 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12249 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12250 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12251 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12252 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12253 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12254 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12255 | pipe_config->ddi_pll_sel, | |
12256 | pipe_config->dpll_hw_state.ctrl1, | |
12257 | pipe_config->dpll_hw_state.cfgcr1, | |
12258 | pipe_config->dpll_hw_state.cfgcr2); | |
12259 | } else if (HAS_DDI(dev)) { | |
1260f07e | 12260 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12261 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12262 | pipe_config->dpll_hw_state.wrpll, |
12263 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12264 | } else { |
12265 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12266 | "fp0: 0x%x, fp1: 0x%x\n", | |
12267 | pipe_config->dpll_hw_state.dpll, | |
12268 | pipe_config->dpll_hw_state.dpll_md, | |
12269 | pipe_config->dpll_hw_state.fp0, | |
12270 | pipe_config->dpll_hw_state.fp1); | |
12271 | } | |
12272 | ||
6a60cd87 CK |
12273 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12274 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12275 | intel_plane = to_intel_plane(plane); | |
12276 | if (intel_plane->pipe != crtc->pipe) | |
12277 | continue; | |
12278 | ||
12279 | state = to_intel_plane_state(plane->state); | |
12280 | fb = state->base.fb; | |
12281 | if (!fb) { | |
1d577e02 VS |
12282 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
12283 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
12284 | continue; |
12285 | } | |
12286 | ||
1d577e02 VS |
12287 | DRM_DEBUG_KMS("[PLANE:%d:%s] enabled", |
12288 | plane->base.id, plane->name); | |
12289 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s", | |
12290 | fb->base.id, fb->width, fb->height, | |
12291 | drm_get_format_name(fb->pixel_format)); | |
12292 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
12293 | state->scaler_id, | |
12294 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12295 | drm_rect_width(&state->src) >> 16, | |
12296 | drm_rect_height(&state->src) >> 16, | |
12297 | state->dst.x1, state->dst.y1, | |
12298 | drm_rect_width(&state->dst), | |
12299 | drm_rect_height(&state->dst)); | |
6a60cd87 | 12300 | } |
c0b03411 DV |
12301 | } |
12302 | ||
5448a00d | 12303 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12304 | { |
5448a00d | 12305 | struct drm_device *dev = state->dev; |
da3ced29 | 12306 | struct drm_connector *connector; |
00f0b378 VS |
12307 | unsigned int used_ports = 0; |
12308 | ||
12309 | /* | |
12310 | * Walk the connector list instead of the encoder | |
12311 | * list to detect the problem on ddi platforms | |
12312 | * where there's just one encoder per digital port. | |
12313 | */ | |
0bff4858 VS |
12314 | drm_for_each_connector(connector, dev) { |
12315 | struct drm_connector_state *connector_state; | |
12316 | struct intel_encoder *encoder; | |
12317 | ||
12318 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12319 | if (!connector_state) | |
12320 | connector_state = connector->state; | |
12321 | ||
5448a00d | 12322 | if (!connector_state->best_encoder) |
00f0b378 VS |
12323 | continue; |
12324 | ||
5448a00d ACO |
12325 | encoder = to_intel_encoder(connector_state->best_encoder); |
12326 | ||
12327 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12328 | |
12329 | switch (encoder->type) { | |
12330 | unsigned int port_mask; | |
12331 | case INTEL_OUTPUT_UNKNOWN: | |
12332 | if (WARN_ON(!HAS_DDI(dev))) | |
12333 | break; | |
cca0502b | 12334 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
12335 | case INTEL_OUTPUT_HDMI: |
12336 | case INTEL_OUTPUT_EDP: | |
12337 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12338 | ||
12339 | /* the same port mustn't appear more than once */ | |
12340 | if (used_ports & port_mask) | |
12341 | return false; | |
12342 | ||
12343 | used_ports |= port_mask; | |
12344 | default: | |
12345 | break; | |
12346 | } | |
12347 | } | |
12348 | ||
12349 | return true; | |
12350 | } | |
12351 | ||
83a57153 ACO |
12352 | static void |
12353 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12354 | { | |
12355 | struct drm_crtc_state tmp_state; | |
663a3640 | 12356 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12357 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12358 | struct intel_shared_dpll *shared_dpll; |
8504c74c | 12359 | uint32_t ddi_pll_sel; |
c4e2d043 | 12360 | bool force_thru; |
83a57153 | 12361 | |
7546a384 ACO |
12362 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12363 | * kzalloc'd. Code that depends on any field being zero should be | |
12364 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12365 | * only fields that are know to not cause problems are preserved. */ | |
12366 | ||
83a57153 | 12367 | tmp_state = crtc_state->base; |
663a3640 | 12368 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12369 | shared_dpll = crtc_state->shared_dpll; |
12370 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12371 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12372 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12373 | |
83a57153 | 12374 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12375 | |
83a57153 | 12376 | crtc_state->base = tmp_state; |
663a3640 | 12377 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12378 | crtc_state->shared_dpll = shared_dpll; |
12379 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12380 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12381 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12382 | } |
12383 | ||
548ee15b | 12384 | static int |
b8cecdf5 | 12385 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12386 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12387 | { |
b359283a | 12388 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12389 | struct intel_encoder *encoder; |
da3ced29 | 12390 | struct drm_connector *connector; |
0b901879 | 12391 | struct drm_connector_state *connector_state; |
d328c9d7 | 12392 | int base_bpp, ret = -EINVAL; |
0b901879 | 12393 | int i; |
e29c22c0 | 12394 | bool retry = true; |
ee7b9f93 | 12395 | |
83a57153 | 12396 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12397 | |
e143a21c DV |
12398 | pipe_config->cpu_transcoder = |
12399 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12400 | |
2960bc9c ID |
12401 | /* |
12402 | * Sanitize sync polarity flags based on requested ones. If neither | |
12403 | * positive or negative polarity is requested, treat this as meaning | |
12404 | * negative polarity. | |
12405 | */ | |
2d112de7 | 12406 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12407 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12408 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12409 | |
2d112de7 | 12410 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12411 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12412 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12413 | |
d328c9d7 DV |
12414 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12415 | pipe_config); | |
12416 | if (base_bpp < 0) | |
4e53c2e0 DV |
12417 | goto fail; |
12418 | ||
e41a56be VS |
12419 | /* |
12420 | * Determine the real pipe dimensions. Note that stereo modes can | |
12421 | * increase the actual pipe size due to the frame doubling and | |
12422 | * insertion of additional space for blanks between the frame. This | |
12423 | * is stored in the crtc timings. We use the requested mode to do this | |
12424 | * computation to clearly distinguish it from the adjusted mode, which | |
12425 | * can be changed by the connectors in the below retry loop. | |
12426 | */ | |
2d112de7 | 12427 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12428 | &pipe_config->pipe_src_w, |
12429 | &pipe_config->pipe_src_h); | |
e41a56be | 12430 | |
253c84c8 VS |
12431 | for_each_connector_in_state(state, connector, connector_state, i) { |
12432 | if (connector_state->crtc != crtc) | |
12433 | continue; | |
12434 | ||
12435 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12436 | ||
e25148d0 VS |
12437 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
12438 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
12439 | goto fail; | |
12440 | } | |
12441 | ||
253c84c8 VS |
12442 | /* |
12443 | * Determine output_types before calling the .compute_config() | |
12444 | * hooks so that the hooks can use this information safely. | |
12445 | */ | |
12446 | pipe_config->output_types |= 1 << encoder->type; | |
12447 | } | |
12448 | ||
e29c22c0 | 12449 | encoder_retry: |
ef1b460d | 12450 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12451 | pipe_config->port_clock = 0; |
ef1b460d | 12452 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12453 | |
135c81b8 | 12454 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12455 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12456 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12457 | |
7758a113 DV |
12458 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12459 | * adjust it according to limitations or connector properties, and also | |
12460 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12461 | */ |
da3ced29 | 12462 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12463 | if (connector_state->crtc != crtc) |
7758a113 | 12464 | continue; |
7ae89233 | 12465 | |
0b901879 ACO |
12466 | encoder = to_intel_encoder(connector_state->best_encoder); |
12467 | ||
efea6e8e DV |
12468 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12469 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12470 | goto fail; |
12471 | } | |
ee7b9f93 | 12472 | } |
47f1c6c9 | 12473 | |
ff9a6750 DV |
12474 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12475 | * done afterwards in case the encoder adjusts the mode. */ | |
12476 | if (!pipe_config->port_clock) | |
2d112de7 | 12477 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12478 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12479 | |
a43f6e0f | 12480 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12481 | if (ret < 0) { |
7758a113 DV |
12482 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12483 | goto fail; | |
ee7b9f93 | 12484 | } |
e29c22c0 DV |
12485 | |
12486 | if (ret == RETRY) { | |
12487 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12488 | ret = -EINVAL; | |
12489 | goto fail; | |
12490 | } | |
12491 | ||
12492 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12493 | retry = false; | |
12494 | goto encoder_retry; | |
12495 | } | |
12496 | ||
e8fa4270 DV |
12497 | /* Dithering seems to not pass-through bits correctly when it should, so |
12498 | * only enable it on 6bpc panels. */ | |
12499 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12500 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12501 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12502 | |
7758a113 | 12503 | fail: |
548ee15b | 12504 | return ret; |
ee7b9f93 | 12505 | } |
47f1c6c9 | 12506 | |
ea9d758d | 12507 | static void |
4740b0f2 | 12508 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12509 | { |
0a9ab303 ACO |
12510 | struct drm_crtc *crtc; |
12511 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12512 | int i; |
ea9d758d | 12513 | |
7668851f | 12514 | /* Double check state. */ |
8a75d157 | 12515 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12516 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12517 | |
12518 | /* Update hwmode for vblank functions */ | |
12519 | if (crtc->state->active) | |
12520 | crtc->hwmode = crtc->state->adjusted_mode; | |
12521 | else | |
12522 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12523 | |
12524 | /* | |
12525 | * Update legacy state to satisfy fbc code. This can | |
12526 | * be removed when fbc uses the atomic state. | |
12527 | */ | |
12528 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12529 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12530 | ||
12531 | crtc->primary->fb = plane_state->fb; | |
12532 | crtc->x = plane_state->src_x >> 16; | |
12533 | crtc->y = plane_state->src_y >> 16; | |
12534 | } | |
ea9d758d | 12535 | } |
ea9d758d DV |
12536 | } |
12537 | ||
3bd26263 | 12538 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12539 | { |
3bd26263 | 12540 | int diff; |
f1f644dc JB |
12541 | |
12542 | if (clock1 == clock2) | |
12543 | return true; | |
12544 | ||
12545 | if (!clock1 || !clock2) | |
12546 | return false; | |
12547 | ||
12548 | diff = abs(clock1 - clock2); | |
12549 | ||
12550 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12551 | return true; | |
12552 | ||
12553 | return false; | |
12554 | } | |
12555 | ||
25c5b266 DV |
12556 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12557 | list_for_each_entry((intel_crtc), \ | |
12558 | &(dev)->mode_config.crtc_list, \ | |
12559 | base.head) \ | |
95150bdf | 12560 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12561 | |
cfb23ed6 ML |
12562 | static bool |
12563 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12564 | unsigned int m2, unsigned int n2, | |
12565 | bool exact) | |
12566 | { | |
12567 | if (m == m2 && n == n2) | |
12568 | return true; | |
12569 | ||
12570 | if (exact || !m || !n || !m2 || !n2) | |
12571 | return false; | |
12572 | ||
12573 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12574 | ||
31d10b57 ML |
12575 | if (n > n2) { |
12576 | while (n > n2) { | |
cfb23ed6 ML |
12577 | m2 <<= 1; |
12578 | n2 <<= 1; | |
12579 | } | |
31d10b57 ML |
12580 | } else if (n < n2) { |
12581 | while (n < n2) { | |
cfb23ed6 ML |
12582 | m <<= 1; |
12583 | n <<= 1; | |
12584 | } | |
12585 | } | |
12586 | ||
31d10b57 ML |
12587 | if (n != n2) |
12588 | return false; | |
12589 | ||
12590 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12591 | } |
12592 | ||
12593 | static bool | |
12594 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12595 | struct intel_link_m_n *m2_n2, | |
12596 | bool adjust) | |
12597 | { | |
12598 | if (m_n->tu == m2_n2->tu && | |
12599 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12600 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12601 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12602 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12603 | if (adjust) | |
12604 | *m2_n2 = *m_n; | |
12605 | ||
12606 | return true; | |
12607 | } | |
12608 | ||
12609 | return false; | |
12610 | } | |
12611 | ||
0e8ffe1b | 12612 | static bool |
2fa2fe9a | 12613 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12614 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12615 | struct intel_crtc_state *pipe_config, |
12616 | bool adjust) | |
0e8ffe1b | 12617 | { |
cfb23ed6 ML |
12618 | bool ret = true; |
12619 | ||
12620 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12621 | do { \ | |
12622 | if (!adjust) \ | |
12623 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12624 | else \ | |
12625 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12626 | } while (0) | |
12627 | ||
66e985c0 DV |
12628 | #define PIPE_CONF_CHECK_X(name) \ |
12629 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12630 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12631 | "(expected 0x%08x, found 0x%08x)\n", \ |
12632 | current_config->name, \ | |
12633 | pipe_config->name); \ | |
cfb23ed6 | 12634 | ret = false; \ |
66e985c0 DV |
12635 | } |
12636 | ||
08a24034 DV |
12637 | #define PIPE_CONF_CHECK_I(name) \ |
12638 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12639 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12640 | "(expected %i, found %i)\n", \ |
12641 | current_config->name, \ | |
12642 | pipe_config->name); \ | |
cfb23ed6 ML |
12643 | ret = false; \ |
12644 | } | |
12645 | ||
8106ddbd ACO |
12646 | #define PIPE_CONF_CHECK_P(name) \ |
12647 | if (current_config->name != pipe_config->name) { \ | |
12648 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12649 | "(expected %p, found %p)\n", \ | |
12650 | current_config->name, \ | |
12651 | pipe_config->name); \ | |
12652 | ret = false; \ | |
12653 | } | |
12654 | ||
cfb23ed6 ML |
12655 | #define PIPE_CONF_CHECK_M_N(name) \ |
12656 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12657 | &pipe_config->name,\ | |
12658 | adjust)) { \ | |
12659 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12660 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12661 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12662 | current_config->name.tu, \ | |
12663 | current_config->name.gmch_m, \ | |
12664 | current_config->name.gmch_n, \ | |
12665 | current_config->name.link_m, \ | |
12666 | current_config->name.link_n, \ | |
12667 | pipe_config->name.tu, \ | |
12668 | pipe_config->name.gmch_m, \ | |
12669 | pipe_config->name.gmch_n, \ | |
12670 | pipe_config->name.link_m, \ | |
12671 | pipe_config->name.link_n); \ | |
12672 | ret = false; \ | |
12673 | } | |
12674 | ||
55c561a7 DV |
12675 | /* This is required for BDW+ where there is only one set of registers for |
12676 | * switching between high and low RR. | |
12677 | * This macro can be used whenever a comparison has to be made between one | |
12678 | * hw state and multiple sw state variables. | |
12679 | */ | |
cfb23ed6 ML |
12680 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
12681 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12682 | &pipe_config->name, adjust) && \ | |
12683 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12684 | &pipe_config->name, adjust)) { \ | |
12685 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12686 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12687 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12688 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12689 | current_config->name.tu, \ | |
12690 | current_config->name.gmch_m, \ | |
12691 | current_config->name.gmch_n, \ | |
12692 | current_config->name.link_m, \ | |
12693 | current_config->name.link_n, \ | |
12694 | current_config->alt_name.tu, \ | |
12695 | current_config->alt_name.gmch_m, \ | |
12696 | current_config->alt_name.gmch_n, \ | |
12697 | current_config->alt_name.link_m, \ | |
12698 | current_config->alt_name.link_n, \ | |
12699 | pipe_config->name.tu, \ | |
12700 | pipe_config->name.gmch_m, \ | |
12701 | pipe_config->name.gmch_n, \ | |
12702 | pipe_config->name.link_m, \ | |
12703 | pipe_config->name.link_n); \ | |
12704 | ret = false; \ | |
88adfff1 DV |
12705 | } |
12706 | ||
1bd1bd80 DV |
12707 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12708 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12709 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12710 | "(expected %i, found %i)\n", \ |
12711 | current_config->name & (mask), \ | |
12712 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12713 | ret = false; \ |
1bd1bd80 DV |
12714 | } |
12715 | ||
5e550656 VS |
12716 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12717 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12718 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12719 | "(expected %i, found %i)\n", \ |
12720 | current_config->name, \ | |
12721 | pipe_config->name); \ | |
cfb23ed6 | 12722 | ret = false; \ |
5e550656 VS |
12723 | } |
12724 | ||
bb760063 DV |
12725 | #define PIPE_CONF_QUIRK(quirk) \ |
12726 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12727 | ||
eccb140b DV |
12728 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12729 | ||
08a24034 DV |
12730 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12731 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12732 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12733 | |
90a6b7b0 | 12734 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 12735 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be VK |
12736 | |
12737 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12738 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12739 | ||
cfb23ed6 ML |
12740 | if (current_config->has_drrs) |
12741 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12742 | } else | |
12743 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12744 | |
253c84c8 | 12745 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 12746 | |
2d112de7 ACO |
12747 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12748 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12749 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12750 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12751 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12752 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12753 | |
2d112de7 ACO |
12754 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12755 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12756 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12757 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12758 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12759 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12760 | |
c93f54cf | 12761 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12762 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12763 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12764 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12765 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12766 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12767 | |
9ed109a7 DV |
12768 | PIPE_CONF_CHECK_I(has_audio); |
12769 | ||
2d112de7 | 12770 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12771 | DRM_MODE_FLAG_INTERLACE); |
12772 | ||
bb760063 | 12773 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12774 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12775 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12776 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12777 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12778 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12779 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12780 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12781 | DRM_MODE_FLAG_NVSYNC); |
12782 | } | |
045ac3b5 | 12783 | |
333b8ca8 | 12784 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12785 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12786 | if (INTEL_INFO(dev)->gen < 4) | |
7f7d8dd6 | 12787 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 12788 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12789 | |
bfd16b2a ML |
12790 | if (!adjust) { |
12791 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12792 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12793 | ||
12794 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12795 | if (current_config->pch_pfit.enabled) { | |
12796 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12797 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12798 | } | |
2fa2fe9a | 12799 | |
7aefe2b5 ML |
12800 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12801 | } | |
a1b2278e | 12802 | |
e59150dc JB |
12803 | /* BDW+ don't expose a synchronous way to read the state */ |
12804 | if (IS_HASWELL(dev)) | |
12805 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12806 | |
282740f7 VS |
12807 | PIPE_CONF_CHECK_I(double_wide); |
12808 | ||
26804afd DV |
12809 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12810 | ||
8106ddbd | 12811 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 12812 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12813 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12814 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12815 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12816 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12817 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12818 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12819 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12820 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12821 | |
47eacbab VS |
12822 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
12823 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
12824 | ||
42571aef VS |
12825 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12826 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12827 | ||
2d112de7 | 12828 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12829 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12830 | |
66e985c0 | 12831 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12832 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 12833 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 12834 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12835 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12836 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12837 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12838 | |
cfb23ed6 | 12839 | return ret; |
0e8ffe1b DV |
12840 | } |
12841 | ||
e3b247da VS |
12842 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
12843 | const struct intel_crtc_state *pipe_config) | |
12844 | { | |
12845 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 12846 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
12847 | &pipe_config->fdi_m_n); |
12848 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
12849 | ||
12850 | /* | |
12851 | * FDI already provided one idea for the dotclock. | |
12852 | * Yell if the encoder disagrees. | |
12853 | */ | |
12854 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
12855 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
12856 | fdi_dotclock, dotclock); | |
12857 | } | |
12858 | } | |
12859 | ||
c0ead703 ML |
12860 | static void verify_wm_state(struct drm_crtc *crtc, |
12861 | struct drm_crtc_state *new_state) | |
08db6652 | 12862 | { |
e7c84544 | 12863 | struct drm_device *dev = crtc->dev; |
fac5e23e | 12864 | struct drm_i915_private *dev_priv = to_i915(dev); |
08db6652 | 12865 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
e7c84544 ML |
12866 | struct skl_ddb_entry *hw_entry, *sw_entry; |
12867 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12868 | const enum pipe pipe = intel_crtc->pipe; | |
08db6652 DL |
12869 | int plane; |
12870 | ||
e7c84544 | 12871 | if (INTEL_INFO(dev)->gen < 9 || !new_state->active) |
08db6652 DL |
12872 | return; |
12873 | ||
12874 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12875 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12876 | ||
e7c84544 ML |
12877 | /* planes */ |
12878 | for_each_plane(dev_priv, pipe, plane) { | |
12879 | hw_entry = &hw_ddb.plane[pipe][plane]; | |
12880 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
08db6652 | 12881 | |
e7c84544 | 12882 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
08db6652 DL |
12883 | continue; |
12884 | ||
e7c84544 ML |
12885 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " |
12886 | "(expected (%u,%u), found (%u,%u))\n", | |
12887 | pipe_name(pipe), plane + 1, | |
12888 | sw_entry->start, sw_entry->end, | |
12889 | hw_entry->start, hw_entry->end); | |
12890 | } | |
08db6652 | 12891 | |
e7c84544 ML |
12892 | /* cursor */ |
12893 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
12894 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 | 12895 | |
e7c84544 | 12896 | if (!skl_ddb_entry_equal(hw_entry, sw_entry)) { |
08db6652 DL |
12897 | DRM_ERROR("mismatch in DDB state pipe %c cursor " |
12898 | "(expected (%u,%u), found (%u,%u))\n", | |
12899 | pipe_name(pipe), | |
12900 | sw_entry->start, sw_entry->end, | |
12901 | hw_entry->start, hw_entry->end); | |
12902 | } | |
12903 | } | |
12904 | ||
91d1b4bd | 12905 | static void |
c0ead703 | 12906 | verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc) |
8af6cf88 | 12907 | { |
35dd3c64 | 12908 | struct drm_connector *connector; |
8af6cf88 | 12909 | |
e7c84544 | 12910 | drm_for_each_connector(connector, dev) { |
35dd3c64 ML |
12911 | struct drm_encoder *encoder = connector->encoder; |
12912 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12913 | |
e7c84544 ML |
12914 | if (state->crtc != crtc) |
12915 | continue; | |
12916 | ||
5a21b665 | 12917 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 12918 | |
ad3c558f | 12919 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12920 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12921 | } |
91d1b4bd DV |
12922 | } |
12923 | ||
12924 | static void | |
c0ead703 | 12925 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
12926 | { |
12927 | struct intel_encoder *encoder; | |
12928 | struct intel_connector *connector; | |
8af6cf88 | 12929 | |
b2784e15 | 12930 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12931 | bool enabled = false; |
4d20cd86 | 12932 | enum pipe pipe; |
8af6cf88 DV |
12933 | |
12934 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12935 | encoder->base.base.id, | |
8e329a03 | 12936 | encoder->base.name); |
8af6cf88 | 12937 | |
3a3371ff | 12938 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12939 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12940 | continue; |
12941 | enabled = true; | |
ad3c558f ML |
12942 | |
12943 | I915_STATE_WARN(connector->base.state->crtc != | |
12944 | encoder->base.crtc, | |
12945 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12946 | } |
0e32b39c | 12947 | |
e2c719b7 | 12948 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12949 | "encoder's enabled state mismatch " |
12950 | "(expected %i, found %i)\n", | |
12951 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12952 | |
12953 | if (!encoder->base.crtc) { | |
4d20cd86 | 12954 | bool active; |
7c60d198 | 12955 | |
4d20cd86 ML |
12956 | active = encoder->get_hw_state(encoder, &pipe); |
12957 | I915_STATE_WARN(active, | |
12958 | "encoder detached but still enabled on pipe %c.\n", | |
12959 | pipe_name(pipe)); | |
7c60d198 | 12960 | } |
8af6cf88 | 12961 | } |
91d1b4bd DV |
12962 | } |
12963 | ||
12964 | static void | |
c0ead703 ML |
12965 | verify_crtc_state(struct drm_crtc *crtc, |
12966 | struct drm_crtc_state *old_crtc_state, | |
12967 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 12968 | { |
e7c84544 | 12969 | struct drm_device *dev = crtc->dev; |
fac5e23e | 12970 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 12971 | struct intel_encoder *encoder; |
e7c84544 ML |
12972 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12973 | struct intel_crtc_state *pipe_config, *sw_config; | |
12974 | struct drm_atomic_state *old_state; | |
12975 | bool active; | |
045ac3b5 | 12976 | |
e7c84544 | 12977 | old_state = old_crtc_state->state; |
ec2dc6a0 | 12978 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
12979 | pipe_config = to_intel_crtc_state(old_crtc_state); |
12980 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12981 | pipe_config->base.crtc = crtc; | |
12982 | pipe_config->base.state = old_state; | |
8af6cf88 | 12983 | |
78108b7c | 12984 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 12985 | |
e7c84544 | 12986 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 12987 | |
e7c84544 ML |
12988 | /* hw state is inconsistent with the pipe quirk */ |
12989 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
12990 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12991 | active = new_crtc_state->active; | |
6c49f241 | 12992 | |
e7c84544 ML |
12993 | I915_STATE_WARN(new_crtc_state->active != active, |
12994 | "crtc active state doesn't match with hw state " | |
12995 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 12996 | |
e7c84544 ML |
12997 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
12998 | "transitional active state does not match atomic hw state " | |
12999 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 13000 | |
e7c84544 ML |
13001 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
13002 | enum pipe pipe; | |
4d20cd86 | 13003 | |
e7c84544 ML |
13004 | active = encoder->get_hw_state(encoder, &pipe); |
13005 | I915_STATE_WARN(active != new_crtc_state->active, | |
13006 | "[ENCODER:%i] active %i with crtc active %i\n", | |
13007 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 13008 | |
e7c84544 ML |
13009 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
13010 | "Encoder connected to wrong pipe %c\n", | |
13011 | pipe_name(pipe)); | |
4d20cd86 | 13012 | |
253c84c8 VS |
13013 | if (active) { |
13014 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 13015 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 13016 | } |
e7c84544 | 13017 | } |
53d9f4e9 | 13018 | |
e7c84544 ML |
13019 | if (!new_crtc_state->active) |
13020 | return; | |
cfb23ed6 | 13021 | |
e7c84544 | 13022 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 13023 | |
e7c84544 ML |
13024 | sw_config = to_intel_crtc_state(crtc->state); |
13025 | if (!intel_pipe_config_compare(dev, sw_config, | |
13026 | pipe_config, false)) { | |
13027 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
13028 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
13029 | "[hw state]"); | |
13030 | intel_dump_pipe_config(intel_crtc, sw_config, | |
13031 | "[sw state]"); | |
8af6cf88 DV |
13032 | } |
13033 | } | |
13034 | ||
91d1b4bd | 13035 | static void |
c0ead703 ML |
13036 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
13037 | struct intel_shared_dpll *pll, | |
13038 | struct drm_crtc *crtc, | |
13039 | struct drm_crtc_state *new_state) | |
91d1b4bd | 13040 | { |
91d1b4bd | 13041 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
13042 | unsigned crtc_mask; |
13043 | bool active; | |
5358901f | 13044 | |
e7c84544 | 13045 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 13046 | |
e7c84544 | 13047 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 13048 | |
e7c84544 | 13049 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 13050 | |
e7c84544 ML |
13051 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
13052 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
13053 | "pll in active use but not on in sw tracking\n"); | |
13054 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
13055 | "pll is on but not used by any active crtc\n"); | |
13056 | I915_STATE_WARN(pll->on != active, | |
13057 | "pll on state mismatch (expected %i, found %i)\n", | |
13058 | pll->on, active); | |
13059 | } | |
5358901f | 13060 | |
e7c84544 | 13061 | if (!crtc) { |
2dd66ebd | 13062 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
e7c84544 ML |
13063 | "more active pll users than references: %x vs %x\n", |
13064 | pll->active_mask, pll->config.crtc_mask); | |
5358901f | 13065 | |
e7c84544 ML |
13066 | return; |
13067 | } | |
13068 | ||
13069 | crtc_mask = 1 << drm_crtc_index(crtc); | |
13070 | ||
13071 | if (new_state->active) | |
13072 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
13073 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
13074 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
13075 | else | |
13076 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13077 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
13078 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 13079 | |
e7c84544 ML |
13080 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
13081 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
13082 | crtc_mask, pll->config.crtc_mask); | |
66e985c0 | 13083 | |
e7c84544 ML |
13084 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
13085 | &dpll_hw_state, | |
13086 | sizeof(dpll_hw_state)), | |
13087 | "pll hw state mismatch\n"); | |
13088 | } | |
13089 | ||
13090 | static void | |
c0ead703 ML |
13091 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
13092 | struct drm_crtc_state *old_crtc_state, | |
13093 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 13094 | { |
fac5e23e | 13095 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13096 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
13097 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
13098 | ||
13099 | if (new_state->shared_dpll) | |
c0ead703 | 13100 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
13101 | |
13102 | if (old_state->shared_dpll && | |
13103 | old_state->shared_dpll != new_state->shared_dpll) { | |
13104 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
13105 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
13106 | ||
13107 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13108 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
13109 | pipe_name(drm_crtc_index(crtc))); | |
13110 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
13111 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
13112 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 13113 | } |
8af6cf88 DV |
13114 | } |
13115 | ||
e7c84544 | 13116 | static void |
c0ead703 | 13117 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
e7c84544 ML |
13118 | struct drm_crtc_state *old_state, |
13119 | struct drm_crtc_state *new_state) | |
13120 | { | |
5a21b665 DV |
13121 | if (!needs_modeset(new_state) && |
13122 | !to_intel_crtc_state(new_state)->update_pipe) | |
13123 | return; | |
13124 | ||
c0ead703 | 13125 | verify_wm_state(crtc, new_state); |
5a21b665 | 13126 | verify_connector_state(crtc->dev, crtc); |
c0ead703 ML |
13127 | verify_crtc_state(crtc, old_state, new_state); |
13128 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
13129 | } |
13130 | ||
13131 | static void | |
c0ead703 | 13132 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 13133 | { |
fac5e23e | 13134 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13135 | int i; |
13136 | ||
13137 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 13138 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
13139 | } |
13140 | ||
13141 | static void | |
c0ead703 | 13142 | intel_modeset_verify_disabled(struct drm_device *dev) |
e7c84544 | 13143 | { |
c0ead703 ML |
13144 | verify_encoder_state(dev); |
13145 | verify_connector_state(dev, NULL); | |
13146 | verify_disabled_dpll_state(dev); | |
e7c84544 ML |
13147 | } |
13148 | ||
80715b2f VS |
13149 | static void update_scanline_offset(struct intel_crtc *crtc) |
13150 | { | |
13151 | struct drm_device *dev = crtc->base.dev; | |
13152 | ||
13153 | /* | |
13154 | * The scanline counter increments at the leading edge of hsync. | |
13155 | * | |
13156 | * On most platforms it starts counting from vtotal-1 on the | |
13157 | * first active line. That means the scanline counter value is | |
13158 | * always one less than what we would expect. Ie. just after | |
13159 | * start of vblank, which also occurs at start of hsync (on the | |
13160 | * last active line), the scanline counter will read vblank_start-1. | |
13161 | * | |
13162 | * On gen2 the scanline counter starts counting from 1 instead | |
13163 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13164 | * to keep the value positive), instead of adding one. | |
13165 | * | |
13166 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13167 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13168 | * there's an extra 1 line difference. So we need to add two instead of | |
13169 | * one to the value. | |
13170 | */ | |
13171 | if (IS_GEN2(dev)) { | |
124abe07 | 13172 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13173 | int vtotal; |
13174 | ||
124abe07 VS |
13175 | vtotal = adjusted_mode->crtc_vtotal; |
13176 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13177 | vtotal /= 2; |
13178 | ||
13179 | crtc->scanline_offset = vtotal - 1; | |
13180 | } else if (HAS_DDI(dev) && | |
2d84d2b3 | 13181 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13182 | crtc->scanline_offset = 2; |
13183 | } else | |
13184 | crtc->scanline_offset = 1; | |
13185 | } | |
13186 | ||
ad421372 | 13187 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13188 | { |
225da59b | 13189 | struct drm_device *dev = state->dev; |
ed6739ef | 13190 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13191 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13192 | struct drm_crtc *crtc; |
13193 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13194 | int i; |
ed6739ef ACO |
13195 | |
13196 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13197 | return; |
ed6739ef | 13198 | |
0a9ab303 | 13199 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 13200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
13201 | struct intel_shared_dpll *old_dpll = |
13202 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13203 | |
fb1a38a9 | 13204 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13205 | continue; |
13206 | ||
8106ddbd | 13207 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 13208 | |
8106ddbd | 13209 | if (!old_dpll) |
fb1a38a9 | 13210 | continue; |
0a9ab303 | 13211 | |
ad421372 ML |
13212 | if (!shared_dpll) |
13213 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13214 | |
8106ddbd | 13215 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13216 | } |
ed6739ef ACO |
13217 | } |
13218 | ||
99d736a2 ML |
13219 | /* |
13220 | * This implements the workaround described in the "notes" section of the mode | |
13221 | * set sequence documentation. When going from no pipes or single pipe to | |
13222 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13223 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13224 | */ | |
13225 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13226 | { | |
13227 | struct drm_crtc_state *crtc_state; | |
13228 | struct intel_crtc *intel_crtc; | |
13229 | struct drm_crtc *crtc; | |
13230 | struct intel_crtc_state *first_crtc_state = NULL; | |
13231 | struct intel_crtc_state *other_crtc_state = NULL; | |
13232 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13233 | int i; | |
13234 | ||
13235 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13236 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13237 | intel_crtc = to_intel_crtc(crtc); | |
13238 | ||
13239 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13240 | continue; | |
13241 | ||
13242 | if (first_crtc_state) { | |
13243 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13244 | break; | |
13245 | } else { | |
13246 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13247 | first_pipe = intel_crtc->pipe; | |
13248 | } | |
13249 | } | |
13250 | ||
13251 | /* No workaround needed? */ | |
13252 | if (!first_crtc_state) | |
13253 | return 0; | |
13254 | ||
13255 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13256 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13257 | struct intel_crtc_state *pipe_config; | |
13258 | ||
13259 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13260 | if (IS_ERR(pipe_config)) | |
13261 | return PTR_ERR(pipe_config); | |
13262 | ||
13263 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13264 | ||
13265 | if (!pipe_config->base.active || | |
13266 | needs_modeset(&pipe_config->base)) | |
13267 | continue; | |
13268 | ||
13269 | /* 2 or more enabled crtcs means no need for w/a */ | |
13270 | if (enabled_pipe != INVALID_PIPE) | |
13271 | return 0; | |
13272 | ||
13273 | enabled_pipe = intel_crtc->pipe; | |
13274 | } | |
13275 | ||
13276 | if (enabled_pipe != INVALID_PIPE) | |
13277 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13278 | else if (other_crtc_state) | |
13279 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13280 | ||
13281 | return 0; | |
13282 | } | |
13283 | ||
27c329ed ML |
13284 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13285 | { | |
13286 | struct drm_crtc *crtc; | |
13287 | struct drm_crtc_state *crtc_state; | |
13288 | int ret = 0; | |
13289 | ||
13290 | /* add all active pipes to the state */ | |
13291 | for_each_crtc(state->dev, crtc) { | |
13292 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13293 | if (IS_ERR(crtc_state)) | |
13294 | return PTR_ERR(crtc_state); | |
13295 | ||
13296 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13297 | continue; | |
13298 | ||
13299 | crtc_state->mode_changed = true; | |
13300 | ||
13301 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13302 | if (ret) | |
13303 | break; | |
13304 | ||
13305 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13306 | if (ret) | |
13307 | break; | |
13308 | } | |
13309 | ||
13310 | return ret; | |
13311 | } | |
13312 | ||
c347a676 | 13313 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13314 | { |
565602d7 | 13315 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 13316 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
13317 | struct drm_crtc *crtc; |
13318 | struct drm_crtc_state *crtc_state; | |
13319 | int ret = 0, i; | |
054518dd | 13320 | |
b359283a ML |
13321 | if (!check_digital_port_conflicts(state)) { |
13322 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13323 | return -EINVAL; | |
13324 | } | |
13325 | ||
565602d7 ML |
13326 | intel_state->modeset = true; |
13327 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13328 | ||
13329 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13330 | if (crtc_state->active) | |
13331 | intel_state->active_crtcs |= 1 << i; | |
13332 | else | |
13333 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
13334 | |
13335 | if (crtc_state->active != crtc->state->active) | |
13336 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
13337 | } |
13338 | ||
054518dd ACO |
13339 | /* |
13340 | * See if the config requires any additional preparation, e.g. | |
13341 | * to adjust global state with pipes off. We need to do this | |
13342 | * here so we can get the modeset_pipe updated config for the new | |
13343 | * mode set on this crtc. For other crtcs we need to use the | |
13344 | * adjusted_mode bits in the crtc directly. | |
13345 | */ | |
27c329ed | 13346 | if (dev_priv->display.modeset_calc_cdclk) { |
c89e39f3 | 13347 | if (!intel_state->cdclk_pll_vco) |
63911d72 | 13348 | intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco; |
b2045352 VS |
13349 | if (!intel_state->cdclk_pll_vco) |
13350 | intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq; | |
c89e39f3 | 13351 | |
27c329ed | 13352 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
13353 | if (ret < 0) |
13354 | return ret; | |
27c329ed | 13355 | |
c89e39f3 | 13356 | if (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 13357 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) |
27c329ed ML |
13358 | ret = intel_modeset_all_pipes(state); |
13359 | ||
13360 | if (ret < 0) | |
054518dd | 13361 | return ret; |
e8788cbc ML |
13362 | |
13363 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13364 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13365 | } else |
1a617b77 | 13366 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13367 | |
ad421372 | 13368 | intel_modeset_clear_plls(state); |
054518dd | 13369 | |
565602d7 | 13370 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13371 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13372 | |
ad421372 | 13373 | return 0; |
c347a676 ACO |
13374 | } |
13375 | ||
aa363136 MR |
13376 | /* |
13377 | * Handle calculation of various watermark data at the end of the atomic check | |
13378 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13379 | * handlers to ensure that all derived state has been updated. | |
13380 | */ | |
55994c2c | 13381 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
13382 | { |
13383 | struct drm_device *dev = state->dev; | |
98d39494 | 13384 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
13385 | |
13386 | /* Is there platform-specific watermark information to calculate? */ | |
13387 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
13388 | return dev_priv->display.compute_global_watermarks(state); |
13389 | ||
13390 | return 0; | |
aa363136 MR |
13391 | } |
13392 | ||
74c090b1 ML |
13393 | /** |
13394 | * intel_atomic_check - validate state object | |
13395 | * @dev: drm device | |
13396 | * @state: state to validate | |
13397 | */ | |
13398 | static int intel_atomic_check(struct drm_device *dev, | |
13399 | struct drm_atomic_state *state) | |
c347a676 | 13400 | { |
dd8b3bdb | 13401 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13402 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13403 | struct drm_crtc *crtc; |
13404 | struct drm_crtc_state *crtc_state; | |
13405 | int ret, i; | |
61333b60 | 13406 | bool any_ms = false; |
c347a676 | 13407 | |
74c090b1 | 13408 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13409 | if (ret) |
13410 | return ret; | |
13411 | ||
c347a676 | 13412 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13413 | struct intel_crtc_state *pipe_config = |
13414 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
13415 | |
13416 | /* Catch I915_MODE_FLAG_INHERITED */ | |
13417 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13418 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13419 | |
af4a879e | 13420 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
13421 | continue; |
13422 | ||
af4a879e DV |
13423 | if (!crtc_state->enable) { |
13424 | any_ms = true; | |
cfb23ed6 | 13425 | continue; |
af4a879e | 13426 | } |
cfb23ed6 | 13427 | |
26495481 DV |
13428 | /* FIXME: For only active_changed we shouldn't need to do any |
13429 | * state recomputation at all. */ | |
13430 | ||
1ed51de9 DV |
13431 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13432 | if (ret) | |
13433 | return ret; | |
b359283a | 13434 | |
cfb23ed6 | 13435 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
13436 | if (ret) { |
13437 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
13438 | pipe_config, "[failed]"); | |
c347a676 | 13439 | return ret; |
25aa1c39 | 13440 | } |
c347a676 | 13441 | |
73831236 | 13442 | if (i915.fastboot && |
dd8b3bdb | 13443 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13444 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13445 | pipe_config, true)) { |
26495481 | 13446 | crtc_state->mode_changed = false; |
bfd16b2a | 13447 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13448 | } |
13449 | ||
af4a879e | 13450 | if (needs_modeset(crtc_state)) |
26495481 | 13451 | any_ms = true; |
cfb23ed6 | 13452 | |
af4a879e DV |
13453 | ret = drm_atomic_add_affected_planes(state, crtc); |
13454 | if (ret) | |
13455 | return ret; | |
61333b60 | 13456 | |
26495481 DV |
13457 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13458 | needs_modeset(crtc_state) ? | |
13459 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13460 | } |
13461 | ||
61333b60 ML |
13462 | if (any_ms) { |
13463 | ret = intel_modeset_checks(state); | |
13464 | ||
13465 | if (ret) | |
13466 | return ret; | |
27c329ed | 13467 | } else |
dd8b3bdb | 13468 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13469 | |
dd8b3bdb | 13470 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13471 | if (ret) |
13472 | return ret; | |
13473 | ||
f51be2e0 | 13474 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 13475 | return calc_watermark_data(state); |
054518dd ACO |
13476 | } |
13477 | ||
5008e874 ML |
13478 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13479 | struct drm_atomic_state *state, | |
81072bfd | 13480 | bool nonblock) |
5008e874 | 13481 | { |
fac5e23e | 13482 | struct drm_i915_private *dev_priv = to_i915(dev); |
7580d774 | 13483 | struct drm_plane_state *plane_state; |
5008e874 | 13484 | struct drm_crtc_state *crtc_state; |
7580d774 | 13485 | struct drm_plane *plane; |
5008e874 ML |
13486 | struct drm_crtc *crtc; |
13487 | int i, ret; | |
13488 | ||
5a21b665 DV |
13489 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
13490 | if (state->legacy_cursor_update) | |
a6747b73 ML |
13491 | continue; |
13492 | ||
5a21b665 DV |
13493 | ret = intel_crtc_wait_for_pending_flips(crtc); |
13494 | if (ret) | |
13495 | return ret; | |
5008e874 | 13496 | |
5a21b665 DV |
13497 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
13498 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
13499 | } |
13500 | ||
f935675f ML |
13501 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13502 | if (ret) | |
13503 | return ret; | |
13504 | ||
5008e874 | 13505 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 13506 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 13507 | |
21daaeee | 13508 | if (!ret && !nonblock) { |
7580d774 ML |
13509 | for_each_plane_in_state(state, plane, plane_state, i) { |
13510 | struct intel_plane_state *intel_plane_state = | |
13511 | to_intel_plane_state(plane_state); | |
13512 | ||
13513 | if (!intel_plane_state->wait_req) | |
13514 | continue; | |
13515 | ||
13516 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
299259a3 | 13517 | true, NULL, NULL); |
f7e5838b | 13518 | if (ret) { |
f4457ae7 CW |
13519 | /* Any hang should be swallowed by the wait */ |
13520 | WARN_ON(ret == -EIO); | |
f7e5838b CW |
13521 | mutex_lock(&dev->struct_mutex); |
13522 | drm_atomic_helper_cleanup_planes(dev, state); | |
13523 | mutex_unlock(&dev->struct_mutex); | |
7580d774 | 13524 | break; |
f7e5838b | 13525 | } |
7580d774 | 13526 | } |
7580d774 | 13527 | } |
5008e874 ML |
13528 | |
13529 | return ret; | |
13530 | } | |
13531 | ||
a2991414 ML |
13532 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
13533 | { | |
13534 | struct drm_device *dev = crtc->base.dev; | |
13535 | ||
13536 | if (!dev->max_vblank_count) | |
13537 | return drm_accurate_vblank_count(&crtc->base); | |
13538 | ||
13539 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
13540 | } | |
13541 | ||
5a21b665 DV |
13542 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13543 | struct drm_i915_private *dev_priv, | |
13544 | unsigned crtc_mask) | |
e8861675 | 13545 | { |
5a21b665 DV |
13546 | unsigned last_vblank_count[I915_MAX_PIPES]; |
13547 | enum pipe pipe; | |
13548 | int ret; | |
e8861675 | 13549 | |
5a21b665 DV |
13550 | if (!crtc_mask) |
13551 | return; | |
e8861675 | 13552 | |
5a21b665 DV |
13553 | for_each_pipe(dev_priv, pipe) { |
13554 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
e8861675 | 13555 | |
5a21b665 | 13556 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
13557 | continue; |
13558 | ||
5a21b665 DV |
13559 | ret = drm_crtc_vblank_get(crtc); |
13560 | if (WARN_ON(ret != 0)) { | |
13561 | crtc_mask &= ~(1 << pipe); | |
13562 | continue; | |
e8861675 ML |
13563 | } |
13564 | ||
5a21b665 | 13565 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); |
e8861675 ML |
13566 | } |
13567 | ||
5a21b665 DV |
13568 | for_each_pipe(dev_priv, pipe) { |
13569 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13570 | long lret; | |
e8861675 | 13571 | |
5a21b665 DV |
13572 | if (!((1 << pipe) & crtc_mask)) |
13573 | continue; | |
d55dbd06 | 13574 | |
5a21b665 DV |
13575 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
13576 | last_vblank_count[pipe] != | |
13577 | drm_crtc_vblank_count(crtc), | |
13578 | msecs_to_jiffies(50)); | |
d55dbd06 | 13579 | |
5a21b665 | 13580 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 13581 | |
5a21b665 | 13582 | drm_crtc_vblank_put(crtc); |
d55dbd06 ML |
13583 | } |
13584 | } | |
13585 | ||
5a21b665 | 13586 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 13587 | { |
5a21b665 DV |
13588 | /* fb updated, need to unpin old fb */ |
13589 | if (crtc_state->fb_changed) | |
13590 | return true; | |
a6747b73 | 13591 | |
5a21b665 DV |
13592 | /* wm changes, need vblank before final wm's */ |
13593 | if (crtc_state->update_wm_post) | |
13594 | return true; | |
a6747b73 | 13595 | |
5a21b665 DV |
13596 | /* |
13597 | * cxsr is re-enabled after vblank. | |
13598 | * This is already handled by crtc_state->update_wm_post, | |
13599 | * but added for clarity. | |
13600 | */ | |
13601 | if (crtc_state->disable_cxsr) | |
13602 | return true; | |
a6747b73 | 13603 | |
5a21b665 | 13604 | return false; |
e8861675 ML |
13605 | } |
13606 | ||
94f05024 | 13607 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 13608 | { |
94f05024 | 13609 | struct drm_device *dev = state->dev; |
565602d7 | 13610 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 13611 | struct drm_i915_private *dev_priv = to_i915(dev); |
29ceb0e6 | 13612 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 13613 | struct drm_crtc *crtc; |
5a21b665 | 13614 | struct intel_crtc_state *intel_cstate; |
94f05024 DV |
13615 | struct drm_plane *plane; |
13616 | struct drm_plane_state *plane_state; | |
5a21b665 DV |
13617 | bool hw_check = intel_state->modeset; |
13618 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
13619 | unsigned crtc_vblank_mask = 0; | |
94f05024 | 13620 | int i, ret; |
a6778b3c | 13621 | |
94f05024 DV |
13622 | for_each_plane_in_state(state, plane, plane_state, i) { |
13623 | struct intel_plane_state *intel_plane_state = | |
13624 | to_intel_plane_state(plane_state); | |
ea0000f0 | 13625 | |
94f05024 DV |
13626 | if (!intel_plane_state->wait_req) |
13627 | continue; | |
d4afb8cc | 13628 | |
94f05024 DV |
13629 | ret = __i915_wait_request(intel_plane_state->wait_req, |
13630 | true, NULL, NULL); | |
13631 | /* EIO should be eaten, and we can't get interrupted in the | |
13632 | * worker, and blocking commits have waited already. */ | |
13633 | WARN_ON(ret); | |
13634 | } | |
1c5e19f8 | 13635 | |
ea0000f0 DV |
13636 | drm_atomic_helper_wait_for_dependencies(state); |
13637 | ||
565602d7 ML |
13638 | if (intel_state->modeset) { |
13639 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13640 | sizeof(intel_state->min_pixclk)); | |
13641 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13642 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
5a21b665 DV |
13643 | |
13644 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
13645 | } |
13646 | ||
29ceb0e6 | 13647 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
13648 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13649 | ||
5a21b665 DV |
13650 | if (needs_modeset(crtc->state) || |
13651 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13652 | hw_check = true; | |
13653 | ||
13654 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13655 | modeset_get_crtc_power_domains(crtc, | |
13656 | to_intel_crtc_state(crtc->state)); | |
13657 | } | |
13658 | ||
61333b60 ML |
13659 | if (!needs_modeset(crtc->state)) |
13660 | continue; | |
13661 | ||
29ceb0e6 | 13662 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 13663 | |
29ceb0e6 VS |
13664 | if (old_crtc_state->active) { |
13665 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
a539205a | 13666 | dev_priv->display.crtc_disable(crtc); |
eddfcbcd | 13667 | intel_crtc->active = false; |
58f9c0bc | 13668 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13669 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13670 | |
13671 | /* | |
13672 | * Underruns don't always raise | |
13673 | * interrupts, so check manually. | |
13674 | */ | |
13675 | intel_check_cpu_fifo_underruns(dev_priv); | |
13676 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13677 | |
13678 | if (!crtc->state->active) | |
13679 | intel_update_watermarks(crtc); | |
a539205a | 13680 | } |
b8cecdf5 | 13681 | } |
7758a113 | 13682 | |
ea9d758d DV |
13683 | /* Only after disabling all output pipelines that will be changed can we |
13684 | * update the the output configuration. */ | |
4740b0f2 | 13685 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13686 | |
565602d7 | 13687 | if (intel_state->modeset) { |
4740b0f2 | 13688 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
13689 | |
13690 | if (dev_priv->display.modeset_commit_cdclk && | |
c89e39f3 | 13691 | (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 13692 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)) |
33c8df89 | 13693 | dev_priv->display.modeset_commit_cdclk(state); |
f6d1973d | 13694 | |
c0ead703 | 13695 | intel_modeset_verify_disabled(dev); |
4740b0f2 | 13696 | } |
47fab737 | 13697 | |
a6778b3c | 13698 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
29ceb0e6 | 13699 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a ML |
13700 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13701 | bool modeset = needs_modeset(crtc->state); | |
5a21b665 DV |
13702 | struct intel_crtc_state *pipe_config = |
13703 | to_intel_crtc_state(crtc->state); | |
9f836f90 | 13704 | |
f6ac4b2a | 13705 | if (modeset && crtc->state->active) { |
a539205a ML |
13706 | update_scanline_offset(to_intel_crtc(crtc)); |
13707 | dev_priv->display.crtc_enable(crtc); | |
13708 | } | |
80715b2f | 13709 | |
1f7528c4 DV |
13710 | /* Complete events for now disable pipes here. */ |
13711 | if (modeset && !crtc->state->active && crtc->state->event) { | |
13712 | spin_lock_irq(&dev->event_lock); | |
13713 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
13714 | spin_unlock_irq(&dev->event_lock); | |
13715 | ||
13716 | crtc->state->event = NULL; | |
13717 | } | |
13718 | ||
f6ac4b2a | 13719 | if (!modeset) |
29ceb0e6 | 13720 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
f6ac4b2a | 13721 | |
5a21b665 DV |
13722 | if (crtc->state->active && |
13723 | drm_atomic_get_existing_plane_state(state, crtc->primary)) | |
faf68d92 | 13724 | intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state)); |
5a21b665 | 13725 | |
1f7528c4 | 13726 | if (crtc->state->active) |
5a21b665 | 13727 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); |
f6d1973d | 13728 | |
5a21b665 DV |
13729 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
13730 | crtc_vblank_mask |= 1 << i; | |
177246a8 MR |
13731 | } |
13732 | ||
94f05024 DV |
13733 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
13734 | * already, but still need the state for the delayed optimization. To | |
13735 | * fix this: | |
13736 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
13737 | * - schedule that vblank worker _before_ calling hw_done | |
13738 | * - at the start of commit_tail, cancel it _synchrously | |
13739 | * - switch over to the vblank wait helper in the core after that since | |
13740 | * we don't need out special handling any more. | |
13741 | */ | |
5a21b665 DV |
13742 | if (!state->legacy_cursor_update) |
13743 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
13744 | ||
13745 | /* | |
13746 | * Now that the vblank has passed, we can go ahead and program the | |
13747 | * optimal watermarks on platforms that need two-step watermark | |
13748 | * programming. | |
13749 | * | |
13750 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13751 | */ | |
13752 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
13753 | intel_cstate = to_intel_crtc_state(crtc->state); | |
13754 | ||
13755 | if (dev_priv->display.optimize_watermarks) | |
13756 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13757 | } | |
13758 | ||
13759 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
13760 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
13761 | ||
13762 | if (put_domains[i]) | |
13763 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
13764 | ||
13765 | intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); | |
13766 | } | |
13767 | ||
94f05024 DV |
13768 | drm_atomic_helper_commit_hw_done(state); |
13769 | ||
5a21b665 DV |
13770 | if (intel_state->modeset) |
13771 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
13772 | ||
13773 | mutex_lock(&dev->struct_mutex); | |
13774 | drm_atomic_helper_cleanup_planes(dev, state); | |
13775 | mutex_unlock(&dev->struct_mutex); | |
13776 | ||
ea0000f0 DV |
13777 | drm_atomic_helper_commit_cleanup_done(state); |
13778 | ||
ee165b1a | 13779 | drm_atomic_state_free(state); |
f30da187 | 13780 | |
75714940 MK |
13781 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13782 | * of triggering bugs in unclaimed access. After we finish | |
13783 | * modesetting, see if an error has been flagged, and if so | |
13784 | * enable debugging for the next modeset - and hope we catch | |
13785 | * the culprit. | |
13786 | * | |
13787 | * XXX note that we assume display power is on at this point. | |
13788 | * This might hold true now but we need to add pm helper to check | |
13789 | * unclaimed only when the hardware is on, as atomic commits | |
13790 | * can happen also when the device is completely off. | |
13791 | */ | |
13792 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
94f05024 DV |
13793 | } |
13794 | ||
13795 | static void intel_atomic_commit_work(struct work_struct *work) | |
13796 | { | |
13797 | struct drm_atomic_state *state = container_of(work, | |
13798 | struct drm_atomic_state, | |
13799 | commit_work); | |
13800 | intel_atomic_commit_tail(state); | |
13801 | } | |
13802 | ||
6c9c1b38 DV |
13803 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
13804 | { | |
13805 | struct drm_plane_state *old_plane_state; | |
13806 | struct drm_plane *plane; | |
13807 | struct drm_i915_gem_object *obj, *old_obj; | |
13808 | struct intel_plane *intel_plane; | |
13809 | int i; | |
13810 | ||
13811 | mutex_lock(&state->dev->struct_mutex); | |
13812 | for_each_plane_in_state(state, plane, old_plane_state, i) { | |
13813 | obj = intel_fb_obj(plane->state->fb); | |
13814 | old_obj = intel_fb_obj(old_plane_state->fb); | |
13815 | intel_plane = to_intel_plane(plane); | |
13816 | ||
13817 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
13818 | } | |
13819 | mutex_unlock(&state->dev->struct_mutex); | |
13820 | } | |
13821 | ||
94f05024 DV |
13822 | /** |
13823 | * intel_atomic_commit - commit validated state object | |
13824 | * @dev: DRM device | |
13825 | * @state: the top-level driver state object | |
13826 | * @nonblock: nonblocking commit | |
13827 | * | |
13828 | * This function commits a top-level state object that has been validated | |
13829 | * with drm_atomic_helper_check(). | |
13830 | * | |
13831 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13832 | * nonblocking commits are only safe for pure plane updates. Everything else | |
13833 | * should work though. | |
13834 | * | |
13835 | * RETURNS | |
13836 | * Zero for success or -errno. | |
13837 | */ | |
13838 | static int intel_atomic_commit(struct drm_device *dev, | |
13839 | struct drm_atomic_state *state, | |
13840 | bool nonblock) | |
13841 | { | |
13842 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 13843 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
13844 | int ret = 0; |
13845 | ||
13846 | if (intel_state->modeset && nonblock) { | |
13847 | DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n"); | |
13848 | return -EINVAL; | |
13849 | } | |
13850 | ||
13851 | ret = drm_atomic_helper_setup_commit(state, nonblock); | |
13852 | if (ret) | |
13853 | return ret; | |
13854 | ||
13855 | INIT_WORK(&state->commit_work, intel_atomic_commit_work); | |
13856 | ||
13857 | ret = intel_atomic_prepare_commit(dev, state, nonblock); | |
13858 | if (ret) { | |
13859 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
13860 | return ret; | |
13861 | } | |
13862 | ||
13863 | drm_atomic_helper_swap_state(state, true); | |
13864 | dev_priv->wm.distrust_bios_wm = false; | |
13865 | dev_priv->wm.skl_results = intel_state->wm_results; | |
13866 | intel_shared_dpll_commit(state); | |
6c9c1b38 | 13867 | intel_atomic_track_fbs(state); |
94f05024 DV |
13868 | |
13869 | if (nonblock) | |
13870 | queue_work(system_unbound_wq, &state->commit_work); | |
13871 | else | |
13872 | intel_atomic_commit_tail(state); | |
75714940 | 13873 | |
74c090b1 | 13874 | return 0; |
7f27126e JB |
13875 | } |
13876 | ||
c0c36b94 CW |
13877 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13878 | { | |
83a57153 ACO |
13879 | struct drm_device *dev = crtc->dev; |
13880 | struct drm_atomic_state *state; | |
e694eb02 | 13881 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13882 | int ret; |
83a57153 ACO |
13883 | |
13884 | state = drm_atomic_state_alloc(dev); | |
13885 | if (!state) { | |
78108b7c VS |
13886 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
13887 | crtc->base.id, crtc->name); | |
83a57153 ACO |
13888 | return; |
13889 | } | |
13890 | ||
e694eb02 | 13891 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13892 | |
e694eb02 ML |
13893 | retry: |
13894 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13895 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13896 | if (!ret) { | |
13897 | if (!crtc_state->active) | |
13898 | goto out; | |
83a57153 | 13899 | |
e694eb02 | 13900 | crtc_state->mode_changed = true; |
74c090b1 | 13901 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13902 | } |
13903 | ||
e694eb02 ML |
13904 | if (ret == -EDEADLK) { |
13905 | drm_atomic_state_clear(state); | |
13906 | drm_modeset_backoff(state->acquire_ctx); | |
13907 | goto retry; | |
4ed9fb37 | 13908 | } |
4be07317 | 13909 | |
2bfb4627 | 13910 | if (ret) |
e694eb02 | 13911 | out: |
2bfb4627 | 13912 | drm_atomic_state_free(state); |
c0c36b94 CW |
13913 | } |
13914 | ||
25c5b266 DV |
13915 | #undef for_each_intel_crtc_masked |
13916 | ||
a8784875 BP |
13917 | /* |
13918 | * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling | |
13919 | * drm_atomic_helper_legacy_gamma_set() directly. | |
13920 | */ | |
13921 | static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc, | |
13922 | u16 *red, u16 *green, u16 *blue, | |
13923 | uint32_t size) | |
13924 | { | |
13925 | struct drm_device *dev = crtc->dev; | |
13926 | struct drm_mode_config *config = &dev->mode_config; | |
13927 | struct drm_crtc_state *state; | |
13928 | int ret; | |
13929 | ||
13930 | ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size); | |
13931 | if (ret) | |
13932 | return ret; | |
13933 | ||
13934 | /* | |
13935 | * Make sure we update the legacy properties so this works when | |
13936 | * atomic is not enabled. | |
13937 | */ | |
13938 | ||
13939 | state = crtc->state; | |
13940 | ||
13941 | drm_object_property_set_value(&crtc->base, | |
13942 | config->degamma_lut_property, | |
13943 | (state->degamma_lut) ? | |
13944 | state->degamma_lut->base.id : 0); | |
13945 | ||
13946 | drm_object_property_set_value(&crtc->base, | |
13947 | config->ctm_property, | |
13948 | (state->ctm) ? | |
13949 | state->ctm->base.id : 0); | |
13950 | ||
13951 | drm_object_property_set_value(&crtc->base, | |
13952 | config->gamma_lut_property, | |
13953 | (state->gamma_lut) ? | |
13954 | state->gamma_lut->base.id : 0); | |
13955 | ||
13956 | return 0; | |
13957 | } | |
13958 | ||
f6e5b160 | 13959 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
a8784875 | 13960 | .gamma_set = intel_atomic_legacy_gamma_set, |
74c090b1 | 13961 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 13962 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 13963 | .destroy = intel_crtc_destroy, |
527b6abe | 13964 | .page_flip = intel_crtc_page_flip, |
1356837e MR |
13965 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13966 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13967 | }; |
13968 | ||
6beb8c23 MR |
13969 | /** |
13970 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13971 | * @plane: drm plane to prepare for | |
13972 | * @fb: framebuffer to prepare for presentation | |
13973 | * | |
13974 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13975 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13976 | * bits. Some older platforms need special physical address handling for | |
13977 | * cursor planes. | |
13978 | * | |
f935675f ML |
13979 | * Must be called with struct_mutex held. |
13980 | * | |
6beb8c23 MR |
13981 | * Returns 0 on success, negative error code on failure. |
13982 | */ | |
13983 | int | |
13984 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13985 | const struct drm_plane_state *new_state) |
465c120c MR |
13986 | { |
13987 | struct drm_device *dev = plane->dev; | |
844f9111 | 13988 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13989 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13990 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c37efb99 | 13991 | struct reservation_object *resv; |
6beb8c23 | 13992 | int ret = 0; |
465c120c | 13993 | |
1ee49399 | 13994 | if (!obj && !old_obj) |
465c120c MR |
13995 | return 0; |
13996 | ||
5008e874 ML |
13997 | if (old_obj) { |
13998 | struct drm_crtc_state *crtc_state = | |
13999 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
14000 | ||
14001 | /* Big Hammer, we also need to ensure that any pending | |
14002 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
14003 | * current scanout is retired before unpinning the old | |
14004 | * framebuffer. Note that we rely on userspace rendering | |
14005 | * into the buffer attached to the pipe they are waiting | |
14006 | * on. If not, userspace generates a GPU hang with IPEHR | |
14007 | * point to the MI_WAIT_FOR_EVENT. | |
14008 | * | |
14009 | * This should only fail upon a hung GPU, in which case we | |
14010 | * can safely continue. | |
14011 | */ | |
14012 | if (needs_modeset(crtc_state)) | |
14013 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
f4457ae7 CW |
14014 | if (ret) { |
14015 | /* GPU hangs should have been swallowed by the wait */ | |
14016 | WARN_ON(ret == -EIO); | |
f935675f | 14017 | return ret; |
f4457ae7 | 14018 | } |
5008e874 ML |
14019 | } |
14020 | ||
c37efb99 CW |
14021 | if (!obj) |
14022 | return 0; | |
14023 | ||
5a21b665 | 14024 | /* For framebuffer backed by dmabuf, wait for fence */ |
c37efb99 CW |
14025 | resv = i915_gem_object_get_dmabuf_resv(obj); |
14026 | if (resv) { | |
5a21b665 DV |
14027 | long lret; |
14028 | ||
c37efb99 | 14029 | lret = reservation_object_wait_timeout_rcu(resv, false, true, |
5a21b665 DV |
14030 | MAX_SCHEDULE_TIMEOUT); |
14031 | if (lret == -ERESTARTSYS) | |
14032 | return lret; | |
14033 | ||
14034 | WARN(lret < 0, "waiting returns %li\n", lret); | |
14035 | } | |
14036 | ||
c37efb99 | 14037 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
6beb8c23 MR |
14038 | INTEL_INFO(dev)->cursor_needs_physical) { |
14039 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
14040 | ret = i915_gem_object_attach_phys(obj, align); | |
14041 | if (ret) | |
14042 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
14043 | } else { | |
3465c580 | 14044 | ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation); |
6beb8c23 | 14045 | } |
465c120c | 14046 | |
c37efb99 | 14047 | if (ret == 0) { |
6c9c1b38 DV |
14048 | struct intel_plane_state *plane_state = |
14049 | to_intel_plane_state(new_state); | |
7580d774 | 14050 | |
6c9c1b38 DV |
14051 | i915_gem_request_assign(&plane_state->wait_req, |
14052 | obj->last_write_req); | |
7580d774 | 14053 | } |
fdd508a6 | 14054 | |
6beb8c23 MR |
14055 | return ret; |
14056 | } | |
14057 | ||
38f3ce3a MR |
14058 | /** |
14059 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
14060 | * @plane: drm plane to clean up for | |
14061 | * @fb: old framebuffer that was on plane | |
14062 | * | |
14063 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
14064 | * |
14065 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
14066 | */ |
14067 | void | |
14068 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 14069 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
14070 | { |
14071 | struct drm_device *dev = plane->dev; | |
7580d774 | 14072 | struct intel_plane_state *old_intel_state; |
84978257 | 14073 | struct intel_plane_state *intel_state = to_intel_plane_state(plane->state); |
1ee49399 ML |
14074 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
14075 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 14076 | |
7580d774 ML |
14077 | old_intel_state = to_intel_plane_state(old_state); |
14078 | ||
1ee49399 | 14079 | if (!obj && !old_obj) |
38f3ce3a MR |
14080 | return; |
14081 | ||
1ee49399 ML |
14082 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
14083 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 14084 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
1ee49399 | 14085 | |
84978257 | 14086 | i915_gem_request_assign(&intel_state->wait_req, NULL); |
7580d774 | 14087 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); |
465c120c MR |
14088 | } |
14089 | ||
6156a456 CK |
14090 | int |
14091 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
14092 | { | |
14093 | int max_scale; | |
6156a456 CK |
14094 | int crtc_clock, cdclk; |
14095 | ||
bf8a0af0 | 14096 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
14097 | return DRM_PLANE_HELPER_NO_SCALING; |
14098 | ||
6156a456 | 14099 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
27c329ed | 14100 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 14101 | |
54bf1ce6 | 14102 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
14103 | return DRM_PLANE_HELPER_NO_SCALING; |
14104 | ||
14105 | /* | |
14106 | * skl max scale is lower of: | |
14107 | * close to 3 but not 3, -1 is for that purpose | |
14108 | * or | |
14109 | * cdclk/crtc_clock | |
14110 | */ | |
14111 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
14112 | ||
14113 | return max_scale; | |
14114 | } | |
14115 | ||
465c120c | 14116 | static int |
3c692a41 | 14117 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 14118 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
14119 | struct intel_plane_state *state) |
14120 | { | |
2b875c22 MR |
14121 | struct drm_crtc *crtc = state->base.crtc; |
14122 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 14123 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
14124 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
14125 | bool can_position = false; | |
465c120c | 14126 | |
693bdc28 VS |
14127 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
14128 | /* use scaler when colorkey is not required */ | |
14129 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
14130 | min_scale = 1; | |
14131 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
14132 | } | |
d8106366 | 14133 | can_position = true; |
6156a456 | 14134 | } |
d8106366 | 14135 | |
061e4b8d ML |
14136 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14137 | &state->dst, &state->clip, | |
9b8b013d | 14138 | state->base.rotation, |
da20eabd ML |
14139 | min_scale, max_scale, |
14140 | can_position, true, | |
14141 | &state->visible); | |
14af293f GP |
14142 | } |
14143 | ||
5a21b665 DV |
14144 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14145 | struct drm_crtc_state *old_crtc_state) | |
14146 | { | |
14147 | struct drm_device *dev = crtc->dev; | |
14148 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14149 | struct intel_crtc_state *old_intel_state = | |
14150 | to_intel_crtc_state(old_crtc_state); | |
14151 | bool modeset = needs_modeset(crtc->state); | |
14152 | ||
14153 | /* Perform vblank evasion around commit operation */ | |
14154 | intel_pipe_update_start(intel_crtc); | |
14155 | ||
14156 | if (modeset) | |
14157 | return; | |
14158 | ||
14159 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { | |
14160 | intel_color_set_csc(crtc->state); | |
14161 | intel_color_load_luts(crtc->state); | |
14162 | } | |
14163 | ||
14164 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
14165 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
14166 | else if (INTEL_INFO(dev)->gen >= 9) | |
14167 | skl_detach_scalers(intel_crtc); | |
14168 | } | |
14169 | ||
14170 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
14171 | struct drm_crtc_state *old_crtc_state) | |
14172 | { | |
14173 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14174 | ||
14175 | intel_pipe_update_end(intel_crtc, NULL); | |
14176 | } | |
14177 | ||
cf4c7c12 | 14178 | /** |
4a3b8769 MR |
14179 | * intel_plane_destroy - destroy a plane |
14180 | * @plane: plane to destroy | |
cf4c7c12 | 14181 | * |
4a3b8769 MR |
14182 | * Common destruction function for all types of planes (primary, cursor, |
14183 | * sprite). | |
cf4c7c12 | 14184 | */ |
4a3b8769 | 14185 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 14186 | { |
69ae561f VS |
14187 | if (!plane) |
14188 | return; | |
14189 | ||
465c120c | 14190 | drm_plane_cleanup(plane); |
69ae561f | 14191 | kfree(to_intel_plane(plane)); |
465c120c MR |
14192 | } |
14193 | ||
65a3fea0 | 14194 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14195 | .update_plane = drm_atomic_helper_update_plane, |
14196 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14197 | .destroy = intel_plane_destroy, |
c196e1d6 | 14198 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14199 | .atomic_get_property = intel_plane_atomic_get_property, |
14200 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14201 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14202 | .atomic_destroy_state = intel_plane_destroy_state, | |
14203 | ||
465c120c MR |
14204 | }; |
14205 | ||
14206 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14207 | int pipe) | |
14208 | { | |
fca0ce2a VS |
14209 | struct intel_plane *primary = NULL; |
14210 | struct intel_plane_state *state = NULL; | |
465c120c | 14211 | const uint32_t *intel_primary_formats; |
45e3743a | 14212 | unsigned int num_formats; |
fca0ce2a | 14213 | int ret; |
465c120c MR |
14214 | |
14215 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
fca0ce2a VS |
14216 | if (!primary) |
14217 | goto fail; | |
465c120c | 14218 | |
8e7d688b | 14219 | state = intel_create_plane_state(&primary->base); |
fca0ce2a VS |
14220 | if (!state) |
14221 | goto fail; | |
8e7d688b | 14222 | primary->base.state = &state->base; |
ea2c67bb | 14223 | |
465c120c MR |
14224 | primary->can_scale = false; |
14225 | primary->max_downscale = 1; | |
6156a456 CK |
14226 | if (INTEL_INFO(dev)->gen >= 9) { |
14227 | primary->can_scale = true; | |
af99ceda | 14228 | state->scaler_id = -1; |
6156a456 | 14229 | } |
465c120c MR |
14230 | primary->pipe = pipe; |
14231 | primary->plane = pipe; | |
a9ff8714 | 14232 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14233 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
14234 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14235 | primary->plane = !pipe; | |
14236 | ||
6c0fd451 DL |
14237 | if (INTEL_INFO(dev)->gen >= 9) { |
14238 | intel_primary_formats = skl_primary_formats; | |
14239 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14240 | |
14241 | primary->update_plane = skylake_update_primary_plane; | |
14242 | primary->disable_plane = skylake_disable_primary_plane; | |
14243 | } else if (HAS_PCH_SPLIT(dev)) { | |
14244 | intel_primary_formats = i965_primary_formats; | |
14245 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14246 | ||
14247 | primary->update_plane = ironlake_update_primary_plane; | |
14248 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14249 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14250 | intel_primary_formats = i965_primary_formats; |
14251 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14252 | |
14253 | primary->update_plane = i9xx_update_primary_plane; | |
14254 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14255 | } else { |
14256 | intel_primary_formats = i8xx_primary_formats; | |
14257 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14258 | |
14259 | primary->update_plane = i9xx_update_primary_plane; | |
14260 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14261 | } |
14262 | ||
38573dc1 VS |
14263 | if (INTEL_INFO(dev)->gen >= 9) |
14264 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14265 | &intel_plane_funcs, | |
14266 | intel_primary_formats, num_formats, | |
14267 | DRM_PLANE_TYPE_PRIMARY, | |
14268 | "plane 1%c", pipe_name(pipe)); | |
14269 | else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
14270 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14271 | &intel_plane_funcs, | |
14272 | intel_primary_formats, num_formats, | |
14273 | DRM_PLANE_TYPE_PRIMARY, | |
14274 | "primary %c", pipe_name(pipe)); | |
14275 | else | |
14276 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14277 | &intel_plane_funcs, | |
14278 | intel_primary_formats, num_formats, | |
14279 | DRM_PLANE_TYPE_PRIMARY, | |
14280 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
14281 | if (ret) |
14282 | goto fail; | |
48404c1e | 14283 | |
3b7a5119 SJ |
14284 | if (INTEL_INFO(dev)->gen >= 4) |
14285 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14286 | |
ea2c67bb MR |
14287 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14288 | ||
465c120c | 14289 | return &primary->base; |
fca0ce2a VS |
14290 | |
14291 | fail: | |
14292 | kfree(state); | |
14293 | kfree(primary); | |
14294 | ||
14295 | return NULL; | |
465c120c MR |
14296 | } |
14297 | ||
3b7a5119 SJ |
14298 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14299 | { | |
14300 | if (!dev->mode_config.rotation_property) { | |
14301 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14302 | BIT(DRM_ROTATE_180); | |
14303 | ||
14304 | if (INTEL_INFO(dev)->gen >= 9) | |
14305 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14306 | ||
14307 | dev->mode_config.rotation_property = | |
14308 | drm_mode_create_rotation_property(dev, flags); | |
14309 | } | |
14310 | if (dev->mode_config.rotation_property) | |
14311 | drm_object_attach_property(&plane->base.base, | |
14312 | dev->mode_config.rotation_property, | |
14313 | plane->base.state->rotation); | |
14314 | } | |
14315 | ||
3d7d6510 | 14316 | static int |
852e787c | 14317 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14318 | struct intel_crtc_state *crtc_state, |
852e787c | 14319 | struct intel_plane_state *state) |
3d7d6510 | 14320 | { |
061e4b8d | 14321 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14322 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14323 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14324 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14325 | unsigned stride; |
14326 | int ret; | |
3d7d6510 | 14327 | |
061e4b8d ML |
14328 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14329 | &state->dst, &state->clip, | |
9b8b013d | 14330 | state->base.rotation, |
3d7d6510 MR |
14331 | DRM_PLANE_HELPER_NO_SCALING, |
14332 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14333 | true, true, &state->visible); |
757f9a3e GP |
14334 | if (ret) |
14335 | return ret; | |
14336 | ||
757f9a3e GP |
14337 | /* if we want to turn off the cursor ignore width and height */ |
14338 | if (!obj) | |
da20eabd | 14339 | return 0; |
757f9a3e | 14340 | |
757f9a3e | 14341 | /* Check for which cursor types we support */ |
061e4b8d | 14342 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14343 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14344 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14345 | return -EINVAL; |
14346 | } | |
14347 | ||
ea2c67bb MR |
14348 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14349 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14350 | DRM_DEBUG_KMS("buffer is too small\n"); |
14351 | return -ENOMEM; | |
14352 | } | |
14353 | ||
3a656b54 | 14354 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14355 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14356 | return -EINVAL; |
32b7eeec MR |
14357 | } |
14358 | ||
b29ec92c VS |
14359 | /* |
14360 | * There's something wrong with the cursor on CHV pipe C. | |
14361 | * If it straddles the left edge of the screen then | |
14362 | * moving it away from the edge or disabling it often | |
14363 | * results in a pipe underrun, and often that can lead to | |
14364 | * dead pipe (constant underrun reported, and it scans | |
14365 | * out just a solid color). To recover from that, the | |
14366 | * display power well must be turned off and on again. | |
14367 | * Refuse the put the cursor into that compromised position. | |
14368 | */ | |
14369 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14370 | state->visible && state->base.crtc_x < 0) { | |
14371 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14372 | return -EINVAL; | |
14373 | } | |
14374 | ||
da20eabd | 14375 | return 0; |
852e787c | 14376 | } |
3d7d6510 | 14377 | |
a8ad0d8e ML |
14378 | static void |
14379 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14380 | struct drm_crtc *crtc) |
a8ad0d8e | 14381 | { |
f2858021 ML |
14382 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14383 | ||
14384 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14385 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14386 | } |
14387 | ||
f4a2cf29 | 14388 | static void |
55a08b3f ML |
14389 | intel_update_cursor_plane(struct drm_plane *plane, |
14390 | const struct intel_crtc_state *crtc_state, | |
14391 | const struct intel_plane_state *state) | |
852e787c | 14392 | { |
55a08b3f ML |
14393 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14394 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14395 | struct drm_device *dev = plane->dev; |
2b875c22 | 14396 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14397 | uint32_t addr; |
852e787c | 14398 | |
f4a2cf29 | 14399 | if (!obj) |
a912f12f | 14400 | addr = 0; |
f4a2cf29 | 14401 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14402 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14403 | else |
a912f12f | 14404 | addr = obj->phys_handle->busaddr; |
852e787c | 14405 | |
a912f12f | 14406 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14407 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14408 | } |
14409 | ||
3d7d6510 MR |
14410 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14411 | int pipe) | |
14412 | { | |
fca0ce2a VS |
14413 | struct intel_plane *cursor = NULL; |
14414 | struct intel_plane_state *state = NULL; | |
14415 | int ret; | |
3d7d6510 MR |
14416 | |
14417 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
fca0ce2a VS |
14418 | if (!cursor) |
14419 | goto fail; | |
3d7d6510 | 14420 | |
8e7d688b | 14421 | state = intel_create_plane_state(&cursor->base); |
fca0ce2a VS |
14422 | if (!state) |
14423 | goto fail; | |
8e7d688b | 14424 | cursor->base.state = &state->base; |
ea2c67bb | 14425 | |
3d7d6510 MR |
14426 | cursor->can_scale = false; |
14427 | cursor->max_downscale = 1; | |
14428 | cursor->pipe = pipe; | |
14429 | cursor->plane = pipe; | |
a9ff8714 | 14430 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14431 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14432 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14433 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 14434 | |
fca0ce2a VS |
14435 | ret = drm_universal_plane_init(dev, &cursor->base, 0, |
14436 | &intel_plane_funcs, | |
14437 | intel_cursor_formats, | |
14438 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
14439 | DRM_PLANE_TYPE_CURSOR, |
14440 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
14441 | if (ret) |
14442 | goto fail; | |
4398ad45 VS |
14443 | |
14444 | if (INTEL_INFO(dev)->gen >= 4) { | |
14445 | if (!dev->mode_config.rotation_property) | |
14446 | dev->mode_config.rotation_property = | |
14447 | drm_mode_create_rotation_property(dev, | |
14448 | BIT(DRM_ROTATE_0) | | |
14449 | BIT(DRM_ROTATE_180)); | |
14450 | if (dev->mode_config.rotation_property) | |
14451 | drm_object_attach_property(&cursor->base.base, | |
14452 | dev->mode_config.rotation_property, | |
8e7d688b | 14453 | state->base.rotation); |
4398ad45 VS |
14454 | } |
14455 | ||
af99ceda CK |
14456 | if (INTEL_INFO(dev)->gen >=9) |
14457 | state->scaler_id = -1; | |
14458 | ||
ea2c67bb MR |
14459 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14460 | ||
3d7d6510 | 14461 | return &cursor->base; |
fca0ce2a VS |
14462 | |
14463 | fail: | |
14464 | kfree(state); | |
14465 | kfree(cursor); | |
14466 | ||
14467 | return NULL; | |
3d7d6510 MR |
14468 | } |
14469 | ||
549e2bfb CK |
14470 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14471 | struct intel_crtc_state *crtc_state) | |
14472 | { | |
14473 | int i; | |
14474 | struct intel_scaler *intel_scaler; | |
14475 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14476 | ||
14477 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14478 | intel_scaler = &scaler_state->scalers[i]; | |
14479 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14480 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14481 | } | |
14482 | ||
14483 | scaler_state->scaler_id = -1; | |
14484 | } | |
14485 | ||
b358d0a6 | 14486 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14487 | { |
fac5e23e | 14488 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 14489 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14490 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14491 | struct drm_plane *primary = NULL; |
14492 | struct drm_plane *cursor = NULL; | |
8563b1e8 | 14493 | int ret; |
79e53945 | 14494 | |
955382f3 | 14495 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14496 | if (intel_crtc == NULL) |
14497 | return; | |
14498 | ||
f5de6e07 ACO |
14499 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14500 | if (!crtc_state) | |
14501 | goto fail; | |
550acefd ACO |
14502 | intel_crtc->config = crtc_state; |
14503 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14504 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14505 | |
549e2bfb CK |
14506 | /* initialize shared scalers */ |
14507 | if (INTEL_INFO(dev)->gen >= 9) { | |
14508 | if (pipe == PIPE_C) | |
14509 | intel_crtc->num_scalers = 1; | |
14510 | else | |
14511 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14512 | ||
14513 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14514 | } | |
14515 | ||
465c120c | 14516 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14517 | if (!primary) |
14518 | goto fail; | |
14519 | ||
14520 | cursor = intel_cursor_plane_create(dev, pipe); | |
14521 | if (!cursor) | |
14522 | goto fail; | |
14523 | ||
465c120c | 14524 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
4d5d72b7 VS |
14525 | cursor, &intel_crtc_funcs, |
14526 | "pipe %c", pipe_name(pipe)); | |
3d7d6510 MR |
14527 | if (ret) |
14528 | goto fail; | |
79e53945 | 14529 | |
1f1c2e24 VS |
14530 | /* |
14531 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14532 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14533 | */ |
80824003 JB |
14534 | intel_crtc->pipe = pipe; |
14535 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14536 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14537 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14538 | intel_crtc->plane = !pipe; |
80824003 JB |
14539 | } |
14540 | ||
4b0e333e CW |
14541 | intel_crtc->cursor_base = ~0; |
14542 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14543 | intel_crtc->cursor_size = ~0; |
8d7849db | 14544 | |
852eb00d VS |
14545 | intel_crtc->wm.cxsr_allowed = true; |
14546 | ||
22fd0fab JB |
14547 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14548 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14549 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14550 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14551 | ||
79e53945 | 14552 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 14553 | |
8563b1e8 LL |
14554 | intel_color_init(&intel_crtc->base); |
14555 | ||
87b6b101 | 14556 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
3d7d6510 MR |
14557 | return; |
14558 | ||
14559 | fail: | |
69ae561f VS |
14560 | intel_plane_destroy(primary); |
14561 | intel_plane_destroy(cursor); | |
f5de6e07 | 14562 | kfree(crtc_state); |
3d7d6510 | 14563 | kfree(intel_crtc); |
79e53945 JB |
14564 | } |
14565 | ||
752aa88a JB |
14566 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14567 | { | |
14568 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14569 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14570 | |
51fd371b | 14571 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14572 | |
d3babd3f | 14573 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14574 | return INVALID_PIPE; |
14575 | ||
14576 | return to_intel_crtc(encoder->crtc)->pipe; | |
14577 | } | |
14578 | ||
08d7b3d1 | 14579 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14580 | struct drm_file *file) |
08d7b3d1 | 14581 | { |
08d7b3d1 | 14582 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14583 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14584 | struct intel_crtc *crtc; |
08d7b3d1 | 14585 | |
7707e653 | 14586 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 14587 | if (!drmmode_crtc) |
3f2c2057 | 14588 | return -ENOENT; |
08d7b3d1 | 14589 | |
7707e653 | 14590 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14591 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14592 | |
c05422d5 | 14593 | return 0; |
08d7b3d1 CW |
14594 | } |
14595 | ||
66a9278e | 14596 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14597 | { |
66a9278e DV |
14598 | struct drm_device *dev = encoder->base.dev; |
14599 | struct intel_encoder *source_encoder; | |
79e53945 | 14600 | int index_mask = 0; |
79e53945 JB |
14601 | int entry = 0; |
14602 | ||
b2784e15 | 14603 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14604 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14605 | index_mask |= (1 << entry); |
14606 | ||
79e53945 JB |
14607 | entry++; |
14608 | } | |
4ef69c7a | 14609 | |
79e53945 JB |
14610 | return index_mask; |
14611 | } | |
14612 | ||
4d302442 CW |
14613 | static bool has_edp_a(struct drm_device *dev) |
14614 | { | |
fac5e23e | 14615 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d302442 CW |
14616 | |
14617 | if (!IS_MOBILE(dev)) | |
14618 | return false; | |
14619 | ||
14620 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14621 | return false; | |
14622 | ||
e3589908 | 14623 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14624 | return false; |
14625 | ||
14626 | return true; | |
14627 | } | |
14628 | ||
84b4e042 JB |
14629 | static bool intel_crt_present(struct drm_device *dev) |
14630 | { | |
fac5e23e | 14631 | struct drm_i915_private *dev_priv = to_i915(dev); |
84b4e042 | 14632 | |
884497ed DL |
14633 | if (INTEL_INFO(dev)->gen >= 9) |
14634 | return false; | |
14635 | ||
cf404ce4 | 14636 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14637 | return false; |
14638 | ||
14639 | if (IS_CHERRYVIEW(dev)) | |
14640 | return false; | |
14641 | ||
65e472e4 VS |
14642 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14643 | return false; | |
14644 | ||
70ac54d0 VS |
14645 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14646 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14647 | return false; | |
14648 | ||
e4abb733 | 14649 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14650 | return false; |
14651 | ||
14652 | return true; | |
14653 | } | |
14654 | ||
79e53945 JB |
14655 | static void intel_setup_outputs(struct drm_device *dev) |
14656 | { | |
fac5e23e | 14657 | struct drm_i915_private *dev_priv = to_i915(dev); |
4ef69c7a | 14658 | struct intel_encoder *encoder; |
cb0953d7 | 14659 | bool dpd_is_edp = false; |
79e53945 | 14660 | |
97a824e1 ID |
14661 | /* |
14662 | * intel_edp_init_connector() depends on this completing first, to | |
14663 | * prevent the registeration of both eDP and LVDS and the incorrect | |
14664 | * sharing of the PPS. | |
14665 | */ | |
c9093354 | 14666 | intel_lvds_init(dev); |
79e53945 | 14667 | |
84b4e042 | 14668 | if (intel_crt_present(dev)) |
79935fca | 14669 | intel_crt_init(dev); |
cb0953d7 | 14670 | |
c776eb2e VK |
14671 | if (IS_BROXTON(dev)) { |
14672 | /* | |
14673 | * FIXME: Broxton doesn't support port detection via the | |
14674 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14675 | * detect the ports. | |
14676 | */ | |
14677 | intel_ddi_init(dev, PORT_A); | |
14678 | intel_ddi_init(dev, PORT_B); | |
14679 | intel_ddi_init(dev, PORT_C); | |
c6c794a2 SS |
14680 | |
14681 | intel_dsi_init(dev); | |
c776eb2e | 14682 | } else if (HAS_DDI(dev)) { |
0e72a5b5 ED |
14683 | int found; |
14684 | ||
de31facd JB |
14685 | /* |
14686 | * Haswell uses DDI functions to detect digital outputs. | |
14687 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14688 | * it's there. | |
14689 | */ | |
77179400 | 14690 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14691 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14692 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14693 | intel_ddi_init(dev, PORT_A); |
14694 | ||
14695 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14696 | * register */ | |
14697 | found = I915_READ(SFUSE_STRAP); | |
14698 | ||
14699 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14700 | intel_ddi_init(dev, PORT_B); | |
14701 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14702 | intel_ddi_init(dev, PORT_C); | |
14703 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14704 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14705 | /* |
14706 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14707 | */ | |
ef11bdb3 | 14708 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14709 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14710 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14711 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14712 | intel_ddi_init(dev, PORT_E); | |
14713 | ||
0e72a5b5 | 14714 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14715 | int found; |
5d8a7752 | 14716 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14717 | |
14718 | if (has_edp_a(dev)) | |
14719 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14720 | |
dc0fa718 | 14721 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14722 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14723 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14724 | if (!found) |
e2debe91 | 14725 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14726 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14727 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14728 | } |
14729 | ||
dc0fa718 | 14730 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14731 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14732 | |
dc0fa718 | 14733 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14734 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14735 | |
5eb08b69 | 14736 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14737 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14738 | |
270b3042 | 14739 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14740 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14741 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
22f35042 | 14742 | bool has_edp, has_port; |
457c52d8 | 14743 | |
e17ac6db VS |
14744 | /* |
14745 | * The DP_DETECTED bit is the latched state of the DDC | |
14746 | * SDA pin at boot. However since eDP doesn't require DDC | |
14747 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14748 | * eDP ports may have been muxed to an alternate function. | |
14749 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14750 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14751 | * detect eDP ports. | |
22f35042 VS |
14752 | * |
14753 | * Sadly the straps seem to be missing sometimes even for HDMI | |
14754 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
14755 | * and VBT for the presence of the port. Additionally we can't | |
14756 | * trust the port type the VBT declares as we've seen at least | |
14757 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 14758 | */ |
457c52d8 | 14759 | has_edp = intel_dp_is_edp(dev, PORT_B); |
22f35042 VS |
14760 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
14761 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
457c52d8 | 14762 | has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B); |
22f35042 | 14763 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 14764 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
585a94b8 | 14765 | |
457c52d8 | 14766 | has_edp = intel_dp_is_edp(dev, PORT_C); |
22f35042 VS |
14767 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
14768 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
457c52d8 | 14769 | has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C); |
22f35042 | 14770 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 14771 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
19c03924 | 14772 | |
9418c1f1 | 14773 | if (IS_CHERRYVIEW(dev)) { |
22f35042 VS |
14774 | /* |
14775 | * eDP not supported on port D, | |
14776 | * so no need to worry about it | |
14777 | */ | |
14778 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
14779 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
e66eb81d | 14780 | intel_dp_init(dev, CHV_DP_D, PORT_D); |
22f35042 VS |
14781 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
14782 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
9418c1f1 VS |
14783 | } |
14784 | ||
3cfca973 | 14785 | intel_dsi_init(dev); |
09da55dc | 14786 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14787 | bool found = false; |
7d57382e | 14788 | |
e2debe91 | 14789 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14790 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14791 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14792 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14793 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14794 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14795 | } |
27185ae1 | 14796 | |
3fec3d2f | 14797 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14798 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14799 | } |
13520b05 KH |
14800 | |
14801 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14802 | |
e2debe91 | 14803 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14804 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14805 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14806 | } |
27185ae1 | 14807 | |
e2debe91 | 14808 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14809 | |
3fec3d2f | 14810 | if (IS_G4X(dev)) { |
b01f2c3a | 14811 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14812 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14813 | } |
3fec3d2f | 14814 | if (IS_G4X(dev)) |
ab9d7c30 | 14815 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14816 | } |
27185ae1 | 14817 | |
3fec3d2f | 14818 | if (IS_G4X(dev) && |
e7281eab | 14819 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14820 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14821 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14822 | intel_dvo_init(dev); |
14823 | ||
103a196f | 14824 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14825 | intel_tv_init(dev); |
14826 | ||
0bc12bcb | 14827 | intel_psr_init(dev); |
7c8f8a70 | 14828 | |
b2784e15 | 14829 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14830 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14831 | encoder->base.possible_clones = | |
66a9278e | 14832 | intel_encoder_clones(encoder); |
79e53945 | 14833 | } |
47356eb6 | 14834 | |
dde86e2d | 14835 | intel_init_pch_refclk(dev); |
270b3042 DV |
14836 | |
14837 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14838 | } |
14839 | ||
14840 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14841 | { | |
60a5ca01 | 14842 | struct drm_device *dev = fb->dev; |
79e53945 | 14843 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14844 | |
ef2d633e | 14845 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14846 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14847 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
f8c417cd | 14848 | i915_gem_object_put(intel_fb->obj); |
60a5ca01 | 14849 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
14850 | kfree(intel_fb); |
14851 | } | |
14852 | ||
14853 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14854 | struct drm_file *file, |
79e53945 JB |
14855 | unsigned int *handle) |
14856 | { | |
14857 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14858 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14859 | |
cc917ab4 CW |
14860 | if (obj->userptr.mm) { |
14861 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14862 | return -EINVAL; | |
14863 | } | |
14864 | ||
05394f39 | 14865 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14866 | } |
14867 | ||
86c98588 RV |
14868 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14869 | struct drm_file *file, | |
14870 | unsigned flags, unsigned color, | |
14871 | struct drm_clip_rect *clips, | |
14872 | unsigned num_clips) | |
14873 | { | |
14874 | struct drm_device *dev = fb->dev; | |
14875 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14876 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14877 | ||
14878 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14879 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14880 | mutex_unlock(&dev->struct_mutex); |
14881 | ||
14882 | return 0; | |
14883 | } | |
14884 | ||
79e53945 JB |
14885 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14886 | .destroy = intel_user_framebuffer_destroy, | |
14887 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14888 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14889 | }; |
14890 | ||
b321803d DL |
14891 | static |
14892 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14893 | uint32_t pixel_format) | |
14894 | { | |
14895 | u32 gen = INTEL_INFO(dev)->gen; | |
14896 | ||
14897 | if (gen >= 9) { | |
ac484963 VS |
14898 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14899 | ||
b321803d DL |
14900 | /* "The stride in bytes must not exceed the of the size of 8K |
14901 | * pixels and 32K bytes." | |
14902 | */ | |
ac484963 | 14903 | return min(8192 * cpp, 32768); |
666a4537 | 14904 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14905 | return 32*1024; |
14906 | } else if (gen >= 4) { | |
14907 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14908 | return 16*1024; | |
14909 | else | |
14910 | return 32*1024; | |
14911 | } else if (gen >= 3) { | |
14912 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14913 | return 8*1024; | |
14914 | else | |
14915 | return 16*1024; | |
14916 | } else { | |
14917 | /* XXX DSPC is limited to 4k tiled */ | |
14918 | return 8*1024; | |
14919 | } | |
14920 | } | |
14921 | ||
b5ea642a DV |
14922 | static int intel_framebuffer_init(struct drm_device *dev, |
14923 | struct intel_framebuffer *intel_fb, | |
14924 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14925 | struct drm_i915_gem_object *obj) | |
79e53945 | 14926 | { |
7b49f948 | 14927 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14928 | unsigned int aligned_height; |
79e53945 | 14929 | int ret; |
b321803d | 14930 | u32 pitch_limit, stride_alignment; |
79e53945 | 14931 | |
dd4916c5 DV |
14932 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14933 | ||
2a80eada DV |
14934 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14935 | /* Enforce that fb modifier and tiling mode match, but only for | |
14936 | * X-tiled. This is needed for FBC. */ | |
14937 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14938 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14939 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14940 | return -EINVAL; | |
14941 | } | |
14942 | } else { | |
14943 | if (obj->tiling_mode == I915_TILING_X) | |
14944 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14945 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14946 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14947 | return -EINVAL; | |
14948 | } | |
14949 | } | |
14950 | ||
9a8f0a12 TU |
14951 | /* Passed in modifier sanity checking. */ |
14952 | switch (mode_cmd->modifier[0]) { | |
14953 | case I915_FORMAT_MOD_Y_TILED: | |
14954 | case I915_FORMAT_MOD_Yf_TILED: | |
14955 | if (INTEL_INFO(dev)->gen < 9) { | |
14956 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14957 | mode_cmd->modifier[0]); | |
14958 | return -EINVAL; | |
14959 | } | |
14960 | case DRM_FORMAT_MOD_NONE: | |
14961 | case I915_FORMAT_MOD_X_TILED: | |
14962 | break; | |
14963 | default: | |
c0f40428 JB |
14964 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14965 | mode_cmd->modifier[0]); | |
57cd6508 | 14966 | return -EINVAL; |
c16ed4be | 14967 | } |
57cd6508 | 14968 | |
7b49f948 VS |
14969 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14970 | mode_cmd->modifier[0], | |
b321803d DL |
14971 | mode_cmd->pixel_format); |
14972 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14973 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14974 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14975 | return -EINVAL; |
c16ed4be | 14976 | } |
57cd6508 | 14977 | |
b321803d DL |
14978 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14979 | mode_cmd->pixel_format); | |
a35cdaa0 | 14980 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14981 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14982 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14983 | "tiled" : "linear", |
a35cdaa0 | 14984 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14985 | return -EINVAL; |
c16ed4be | 14986 | } |
5d7bd705 | 14987 | |
2a80eada | 14988 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14989 | mode_cmd->pitches[0] != obj->stride) { |
14990 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14991 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14992 | return -EINVAL; |
c16ed4be | 14993 | } |
5d7bd705 | 14994 | |
57779d06 | 14995 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14996 | switch (mode_cmd->pixel_format) { |
57779d06 | 14997 | case DRM_FORMAT_C8: |
04b3924d VS |
14998 | case DRM_FORMAT_RGB565: |
14999 | case DRM_FORMAT_XRGB8888: | |
15000 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
15001 | break; |
15002 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 15003 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
15004 | DRM_DEBUG("unsupported pixel format: %s\n", |
15005 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15006 | return -EINVAL; |
c16ed4be | 15007 | } |
57779d06 | 15008 | break; |
57779d06 | 15009 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
15010 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
15011 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
15012 | DRM_DEBUG("unsupported pixel format: %s\n", |
15013 | drm_get_format_name(mode_cmd->pixel_format)); | |
15014 | return -EINVAL; | |
15015 | } | |
15016 | break; | |
15017 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 15018 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 15019 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 15020 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
15021 | DRM_DEBUG("unsupported pixel format: %s\n", |
15022 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15023 | return -EINVAL; |
c16ed4be | 15024 | } |
b5626747 | 15025 | break; |
7531208b | 15026 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 15027 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
15028 | DRM_DEBUG("unsupported pixel format: %s\n", |
15029 | drm_get_format_name(mode_cmd->pixel_format)); | |
15030 | return -EINVAL; | |
15031 | } | |
15032 | break; | |
04b3924d VS |
15033 | case DRM_FORMAT_YUYV: |
15034 | case DRM_FORMAT_UYVY: | |
15035 | case DRM_FORMAT_YVYU: | |
15036 | case DRM_FORMAT_VYUY: | |
c16ed4be | 15037 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
15038 | DRM_DEBUG("unsupported pixel format: %s\n", |
15039 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15040 | return -EINVAL; |
c16ed4be | 15041 | } |
57cd6508 CW |
15042 | break; |
15043 | default: | |
4ee62c76 VS |
15044 | DRM_DEBUG("unsupported pixel format: %s\n", |
15045 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
15046 | return -EINVAL; |
15047 | } | |
15048 | ||
90f9a336 VS |
15049 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
15050 | if (mode_cmd->offsets[0] != 0) | |
15051 | return -EINVAL; | |
15052 | ||
ec2c981e | 15053 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
15054 | mode_cmd->pixel_format, |
15055 | mode_cmd->modifier[0]); | |
53155c0a DV |
15056 | /* FIXME drm helper for size checks (especially planar formats)? */ |
15057 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
15058 | return -EINVAL; | |
15059 | ||
c7d73f6a DV |
15060 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
15061 | intel_fb->obj = obj; | |
15062 | ||
2d7a215f VS |
15063 | intel_fill_fb_info(dev_priv, &intel_fb->base); |
15064 | ||
79e53945 JB |
15065 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
15066 | if (ret) { | |
15067 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
15068 | return ret; | |
15069 | } | |
15070 | ||
0b05e1e0 VS |
15071 | intel_fb->obj->framebuffer_references++; |
15072 | ||
79e53945 JB |
15073 | return 0; |
15074 | } | |
15075 | ||
79e53945 JB |
15076 | static struct drm_framebuffer * |
15077 | intel_user_framebuffer_create(struct drm_device *dev, | |
15078 | struct drm_file *filp, | |
1eb83451 | 15079 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 15080 | { |
dcb1394e | 15081 | struct drm_framebuffer *fb; |
05394f39 | 15082 | struct drm_i915_gem_object *obj; |
76dc3769 | 15083 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 15084 | |
03ac0642 CW |
15085 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
15086 | if (!obj) | |
cce13ff7 | 15087 | return ERR_PTR(-ENOENT); |
79e53945 | 15088 | |
92907cbb | 15089 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e | 15090 | if (IS_ERR(fb)) |
34911fd3 | 15091 | i915_gem_object_put_unlocked(obj); |
dcb1394e LW |
15092 | |
15093 | return fb; | |
79e53945 JB |
15094 | } |
15095 | ||
0695726e | 15096 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 15097 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
15098 | { |
15099 | } | |
15100 | #endif | |
15101 | ||
79e53945 | 15102 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 15103 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 15104 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
15105 | .atomic_check = intel_atomic_check, |
15106 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
15107 | .atomic_state_alloc = intel_atomic_state_alloc, |
15108 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
15109 | }; |
15110 | ||
88212941 ID |
15111 | /** |
15112 | * intel_init_display_hooks - initialize the display modesetting hooks | |
15113 | * @dev_priv: device private | |
15114 | */ | |
15115 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 15116 | { |
88212941 | 15117 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 15118 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15119 | dev_priv->display.get_initial_plane_config = |
15120 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
15121 | dev_priv->display.crtc_compute_clock = |
15122 | haswell_crtc_compute_clock; | |
15123 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
15124 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15125 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 15126 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15127 | dev_priv->display.get_initial_plane_config = |
15128 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
15129 | dev_priv->display.crtc_compute_clock = |
15130 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
15131 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
15132 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15133 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 15134 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
15135 | dev_priv->display.get_initial_plane_config = |
15136 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
15137 | dev_priv->display.crtc_compute_clock = |
15138 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
15139 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
15140 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 15141 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 15142 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15143 | dev_priv->display.get_initial_plane_config = |
15144 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
15145 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
15146 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
15147 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
15148 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
15149 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15150 | dev_priv->display.get_initial_plane_config = | |
15151 | i9xx_get_initial_plane_config; | |
15152 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
15153 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
15154 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
15155 | } else if (IS_G4X(dev_priv)) { |
15156 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15157 | dev_priv->display.get_initial_plane_config = | |
15158 | i9xx_get_initial_plane_config; | |
15159 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
15160 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15161 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
15162 | } else if (IS_PINEVIEW(dev_priv)) { |
15163 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15164 | dev_priv->display.get_initial_plane_config = | |
15165 | i9xx_get_initial_plane_config; | |
15166 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
15167 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15168 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 15169 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 15170 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15171 | dev_priv->display.get_initial_plane_config = |
15172 | i9xx_get_initial_plane_config; | |
d6dfee7a | 15173 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
15174 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
15175 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
15176 | } else { |
15177 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15178 | dev_priv->display.get_initial_plane_config = | |
15179 | i9xx_get_initial_plane_config; | |
15180 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
15181 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15182 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 15183 | } |
e70236a8 | 15184 | |
e70236a8 | 15185 | /* Returns the core display clock speed */ |
88212941 | 15186 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
15187 | dev_priv->display.get_display_clock_speed = |
15188 | skylake_get_display_clock_speed; | |
88212941 | 15189 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
15190 | dev_priv->display.get_display_clock_speed = |
15191 | broxton_get_display_clock_speed; | |
88212941 | 15192 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
15193 | dev_priv->display.get_display_clock_speed = |
15194 | broadwell_get_display_clock_speed; | |
88212941 | 15195 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
15196 | dev_priv->display.get_display_clock_speed = |
15197 | haswell_get_display_clock_speed; | |
88212941 | 15198 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
15199 | dev_priv->display.get_display_clock_speed = |
15200 | valleyview_get_display_clock_speed; | |
88212941 | 15201 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
15202 | dev_priv->display.get_display_clock_speed = |
15203 | ilk_get_display_clock_speed; | |
88212941 ID |
15204 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
15205 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
15206 | dev_priv->display.get_display_clock_speed = |
15207 | i945_get_display_clock_speed; | |
88212941 | 15208 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
15209 | dev_priv->display.get_display_clock_speed = |
15210 | gm45_get_display_clock_speed; | |
88212941 | 15211 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
15212 | dev_priv->display.get_display_clock_speed = |
15213 | i965gm_get_display_clock_speed; | |
88212941 | 15214 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
15215 | dev_priv->display.get_display_clock_speed = |
15216 | pnv_get_display_clock_speed; | |
88212941 | 15217 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
15218 | dev_priv->display.get_display_clock_speed = |
15219 | g33_get_display_clock_speed; | |
88212941 | 15220 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
15221 | dev_priv->display.get_display_clock_speed = |
15222 | i915_get_display_clock_speed; | |
88212941 | 15223 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
15224 | dev_priv->display.get_display_clock_speed = |
15225 | i9xx_misc_get_display_clock_speed; | |
88212941 | 15226 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
15227 | dev_priv->display.get_display_clock_speed = |
15228 | i915gm_get_display_clock_speed; | |
88212941 | 15229 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
15230 | dev_priv->display.get_display_clock_speed = |
15231 | i865_get_display_clock_speed; | |
88212941 | 15232 | else if (IS_I85X(dev_priv)) |
e70236a8 | 15233 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 15234 | i85x_get_display_clock_speed; |
623e01e5 | 15235 | else { /* 830 */ |
88212941 | 15236 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
15237 | dev_priv->display.get_display_clock_speed = |
15238 | i830_get_display_clock_speed; | |
623e01e5 | 15239 | } |
e70236a8 | 15240 | |
88212941 | 15241 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 15242 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 15243 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 15244 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 15245 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
15246 | /* FIXME: detect B0+ stepping and use auto training */ |
15247 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 15248 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 15249 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
15250 | } |
15251 | ||
15252 | if (IS_BROADWELL(dev_priv)) { | |
15253 | dev_priv->display.modeset_commit_cdclk = | |
15254 | broadwell_modeset_commit_cdclk; | |
15255 | dev_priv->display.modeset_calc_cdclk = | |
15256 | broadwell_modeset_calc_cdclk; | |
88212941 | 15257 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
15258 | dev_priv->display.modeset_commit_cdclk = |
15259 | valleyview_modeset_commit_cdclk; | |
15260 | dev_priv->display.modeset_calc_cdclk = | |
15261 | valleyview_modeset_calc_cdclk; | |
88212941 | 15262 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed | 15263 | dev_priv->display.modeset_commit_cdclk = |
324513c0 | 15264 | bxt_modeset_commit_cdclk; |
27c329ed | 15265 | dev_priv->display.modeset_calc_cdclk = |
324513c0 | 15266 | bxt_modeset_calc_cdclk; |
c89e39f3 CT |
15267 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
15268 | dev_priv->display.modeset_commit_cdclk = | |
15269 | skl_modeset_commit_cdclk; | |
15270 | dev_priv->display.modeset_calc_cdclk = | |
15271 | skl_modeset_calc_cdclk; | |
e70236a8 | 15272 | } |
5a21b665 DV |
15273 | |
15274 | switch (INTEL_INFO(dev_priv)->gen) { | |
15275 | case 2: | |
15276 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15277 | break; | |
15278 | ||
15279 | case 3: | |
15280 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15281 | break; | |
15282 | ||
15283 | case 4: | |
15284 | case 5: | |
15285 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15286 | break; | |
15287 | ||
15288 | case 6: | |
15289 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15290 | break; | |
15291 | case 7: | |
15292 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
15293 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
15294 | break; | |
15295 | case 9: | |
15296 | /* Drop through - unsupported since execlist only. */ | |
15297 | default: | |
15298 | /* Default just returns -ENODEV to indicate unsupported */ | |
15299 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
15300 | } | |
e70236a8 JB |
15301 | } |
15302 | ||
b690e96c JB |
15303 | /* |
15304 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15305 | * resume, or other times. This quirk makes sure that's the case for | |
15306 | * affected systems. | |
15307 | */ | |
0206e353 | 15308 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c | 15309 | { |
fac5e23e | 15310 | struct drm_i915_private *dev_priv = to_i915(dev); |
b690e96c JB |
15311 | |
15312 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15313 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15314 | } |
15315 | ||
b6b5d049 VS |
15316 | static void quirk_pipeb_force(struct drm_device *dev) |
15317 | { | |
fac5e23e | 15318 | struct drm_i915_private *dev_priv = to_i915(dev); |
b6b5d049 VS |
15319 | |
15320 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15321 | DRM_INFO("applying pipe b force quirk\n"); | |
15322 | } | |
15323 | ||
435793df KP |
15324 | /* |
15325 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15326 | */ | |
15327 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15328 | { | |
fac5e23e | 15329 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 15330 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 15331 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15332 | } |
15333 | ||
4dca20ef | 15334 | /* |
5a15ab5b CE |
15335 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15336 | * brightness value | |
4dca20ef CE |
15337 | */ |
15338 | static void quirk_invert_brightness(struct drm_device *dev) | |
15339 | { | |
fac5e23e | 15340 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 15341 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 15342 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15343 | } |
15344 | ||
9c72cc6f SD |
15345 | /* Some VBT's incorrectly indicate no backlight is present */ |
15346 | static void quirk_backlight_present(struct drm_device *dev) | |
15347 | { | |
fac5e23e | 15348 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
15349 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
15350 | DRM_INFO("applying backlight present quirk\n"); | |
15351 | } | |
15352 | ||
b690e96c JB |
15353 | struct intel_quirk { |
15354 | int device; | |
15355 | int subsystem_vendor; | |
15356 | int subsystem_device; | |
15357 | void (*hook)(struct drm_device *dev); | |
15358 | }; | |
15359 | ||
5f85f176 EE |
15360 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15361 | struct intel_dmi_quirk { | |
15362 | void (*hook)(struct drm_device *dev); | |
15363 | const struct dmi_system_id (*dmi_id_list)[]; | |
15364 | }; | |
15365 | ||
15366 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15367 | { | |
15368 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15369 | return 1; | |
15370 | } | |
15371 | ||
15372 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15373 | { | |
15374 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15375 | { | |
15376 | .callback = intel_dmi_reverse_brightness, | |
15377 | .ident = "NCR Corporation", | |
15378 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15379 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15380 | }, | |
15381 | }, | |
15382 | { } /* terminating entry */ | |
15383 | }, | |
15384 | .hook = quirk_invert_brightness, | |
15385 | }, | |
15386 | }; | |
15387 | ||
c43b5634 | 15388 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15389 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15390 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15391 | ||
b690e96c JB |
15392 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15393 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15394 | ||
5f080c0f VS |
15395 | /* 830 needs to leave pipe A & dpll A up */ |
15396 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15397 | ||
b6b5d049 VS |
15398 | /* 830 needs to leave pipe B & dpll B up */ |
15399 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15400 | ||
435793df KP |
15401 | /* Lenovo U160 cannot use SSC on LVDS */ |
15402 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15403 | |
15404 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15405 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15406 | |
be505f64 AH |
15407 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15408 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15409 | ||
15410 | /* Acer/eMachines G725 */ | |
15411 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15412 | ||
15413 | /* Acer/eMachines e725 */ | |
15414 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15415 | ||
15416 | /* Acer/Packard Bell NCL20 */ | |
15417 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15418 | ||
15419 | /* Acer Aspire 4736Z */ | |
15420 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15421 | |
15422 | /* Acer Aspire 5336 */ | |
15423 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15424 | |
15425 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15426 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15427 | |
dfb3d47b SD |
15428 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15429 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15430 | ||
b2a9601c | 15431 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15432 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15433 | ||
1b9448b0 JN |
15434 | /* Apple Macbook 4,1 */ |
15435 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15436 | ||
d4967d8c SD |
15437 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15438 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15439 | |
15440 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15441 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15442 | |
15443 | /* Dell Chromebook 11 */ | |
15444 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15445 | |
15446 | /* Dell Chromebook 11 (2015 version) */ | |
15447 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15448 | }; |
15449 | ||
15450 | static void intel_init_quirks(struct drm_device *dev) | |
15451 | { | |
15452 | struct pci_dev *d = dev->pdev; | |
15453 | int i; | |
15454 | ||
15455 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15456 | struct intel_quirk *q = &intel_quirks[i]; | |
15457 | ||
15458 | if (d->device == q->device && | |
15459 | (d->subsystem_vendor == q->subsystem_vendor || | |
15460 | q->subsystem_vendor == PCI_ANY_ID) && | |
15461 | (d->subsystem_device == q->subsystem_device || | |
15462 | q->subsystem_device == PCI_ANY_ID)) | |
15463 | q->hook(dev); | |
15464 | } | |
5f85f176 EE |
15465 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15466 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15467 | intel_dmi_quirks[i].hook(dev); | |
15468 | } | |
b690e96c JB |
15469 | } |
15470 | ||
9cce37f4 JB |
15471 | /* Disable the VGA plane that we never use */ |
15472 | static void i915_disable_vga(struct drm_device *dev) | |
15473 | { | |
fac5e23e | 15474 | struct drm_i915_private *dev_priv = to_i915(dev); |
9cce37f4 | 15475 | u8 sr1; |
f0f59a00 | 15476 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15477 | |
2b37c616 | 15478 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15479 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15480 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15481 | sr1 = inb(VGA_SR_DATA); |
15482 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15483 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15484 | udelay(300); | |
15485 | ||
01f5a626 | 15486 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15487 | POSTING_READ(vga_reg); |
15488 | } | |
15489 | ||
f817586c DV |
15490 | void intel_modeset_init_hw(struct drm_device *dev) |
15491 | { | |
fac5e23e | 15492 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 15493 | |
b6283055 | 15494 | intel_update_cdclk(dev); |
1a617b77 ML |
15495 | |
15496 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15497 | ||
f817586c | 15498 | intel_init_clock_gating(dev); |
f817586c DV |
15499 | } |
15500 | ||
d93c0372 MR |
15501 | /* |
15502 | * Calculate what we think the watermarks should be for the state we've read | |
15503 | * out of the hardware and then immediately program those watermarks so that | |
15504 | * we ensure the hardware settings match our internal state. | |
15505 | * | |
15506 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15507 | * current state (which was constructed during hardware readout) and running it | |
15508 | * through the atomic check code to calculate new watermark values in the | |
15509 | * state object. | |
15510 | */ | |
15511 | static void sanitize_watermarks(struct drm_device *dev) | |
15512 | { | |
15513 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15514 | struct drm_atomic_state *state; | |
15515 | struct drm_crtc *crtc; | |
15516 | struct drm_crtc_state *cstate; | |
15517 | struct drm_modeset_acquire_ctx ctx; | |
15518 | int ret; | |
15519 | int i; | |
15520 | ||
15521 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 15522 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
15523 | return; |
15524 | ||
15525 | /* | |
15526 | * We need to hold connection_mutex before calling duplicate_state so | |
15527 | * that the connector loop is protected. | |
15528 | */ | |
15529 | drm_modeset_acquire_init(&ctx, 0); | |
15530 | retry: | |
0cd1262d | 15531 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15532 | if (ret == -EDEADLK) { |
15533 | drm_modeset_backoff(&ctx); | |
15534 | goto retry; | |
15535 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15536 | goto fail; |
d93c0372 MR |
15537 | } |
15538 | ||
15539 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15540 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15541 | goto fail; |
d93c0372 | 15542 | |
ed4a6a7c MR |
15543 | /* |
15544 | * Hardware readout is the only time we don't want to calculate | |
15545 | * intermediate watermarks (since we don't trust the current | |
15546 | * watermarks). | |
15547 | */ | |
15548 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15549 | ||
d93c0372 MR |
15550 | ret = intel_atomic_check(dev, state); |
15551 | if (ret) { | |
15552 | /* | |
15553 | * If we fail here, it means that the hardware appears to be | |
15554 | * programmed in a way that shouldn't be possible, given our | |
15555 | * understanding of watermark requirements. This might mean a | |
15556 | * mistake in the hardware readout code or a mistake in the | |
15557 | * watermark calculations for a given platform. Raise a WARN | |
15558 | * so that this is noticeable. | |
15559 | * | |
15560 | * If this actually happens, we'll have to just leave the | |
15561 | * BIOS-programmed watermarks untouched and hope for the best. | |
15562 | */ | |
15563 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15564 | goto fail; |
d93c0372 MR |
15565 | } |
15566 | ||
15567 | /* Write calculated watermark values back */ | |
d93c0372 MR |
15568 | for_each_crtc_in_state(state, crtc, cstate, i) { |
15569 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15570 | ||
ed4a6a7c MR |
15571 | cs->wm.need_postvbl_update = true; |
15572 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
15573 | } |
15574 | ||
15575 | drm_atomic_state_free(state); | |
0cd1262d | 15576 | fail: |
d93c0372 MR |
15577 | drm_modeset_drop_locks(&ctx); |
15578 | drm_modeset_acquire_fini(&ctx); | |
15579 | } | |
15580 | ||
79e53945 JB |
15581 | void intel_modeset_init(struct drm_device *dev) |
15582 | { | |
72e96d64 JL |
15583 | struct drm_i915_private *dev_priv = to_i915(dev); |
15584 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
1fe47785 | 15585 | int sprite, ret; |
8cc87b75 | 15586 | enum pipe pipe; |
46f297fb | 15587 | struct intel_crtc *crtc; |
79e53945 JB |
15588 | |
15589 | drm_mode_config_init(dev); | |
15590 | ||
15591 | dev->mode_config.min_width = 0; | |
15592 | dev->mode_config.min_height = 0; | |
15593 | ||
019d96cb DA |
15594 | dev->mode_config.preferred_depth = 24; |
15595 | dev->mode_config.prefer_shadow = 1; | |
15596 | ||
25bab385 TU |
15597 | dev->mode_config.allow_fb_modifiers = true; |
15598 | ||
e6ecefaa | 15599 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15600 | |
b690e96c JB |
15601 | intel_init_quirks(dev); |
15602 | ||
1fa61106 ED |
15603 | intel_init_pm(dev); |
15604 | ||
e3c74757 BW |
15605 | if (INTEL_INFO(dev)->num_pipes == 0) |
15606 | return; | |
15607 | ||
69f92f67 LW |
15608 | /* |
15609 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15610 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15611 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15612 | * indicates as much. | |
15613 | */ | |
15614 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15615 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15616 | DREF_SSC1_ENABLE); | |
15617 | ||
15618 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15619 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15620 | bios_lvds_use_ssc ? "en" : "dis", | |
15621 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15622 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15623 | } | |
15624 | } | |
15625 | ||
a6c45cf0 CW |
15626 | if (IS_GEN2(dev)) { |
15627 | dev->mode_config.max_width = 2048; | |
15628 | dev->mode_config.max_height = 2048; | |
15629 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15630 | dev->mode_config.max_width = 4096; |
15631 | dev->mode_config.max_height = 4096; | |
79e53945 | 15632 | } else { |
a6c45cf0 CW |
15633 | dev->mode_config.max_width = 8192; |
15634 | dev->mode_config.max_height = 8192; | |
79e53945 | 15635 | } |
068be561 | 15636 | |
dc41c154 VS |
15637 | if (IS_845G(dev) || IS_I865G(dev)) { |
15638 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15639 | dev->mode_config.cursor_height = 1023; | |
15640 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15641 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15642 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15643 | } else { | |
15644 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15645 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15646 | } | |
15647 | ||
72e96d64 | 15648 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 15649 | |
28c97730 | 15650 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15651 | INTEL_INFO(dev)->num_pipes, |
15652 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15653 | |
055e393f | 15654 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15655 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15656 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15657 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15658 | if (ret) |
06da8da2 | 15659 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15660 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15661 | } |
79e53945 JB |
15662 | } |
15663 | ||
bfa7df01 VS |
15664 | intel_update_czclk(dev_priv); |
15665 | intel_update_cdclk(dev); | |
15666 | ||
e72f9fbf | 15667 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15668 | |
b2045352 VS |
15669 | if (dev_priv->max_cdclk_freq == 0) |
15670 | intel_update_max_cdclk(dev); | |
15671 | ||
9cce37f4 JB |
15672 | /* Just disable it once at startup */ |
15673 | i915_disable_vga(dev); | |
79e53945 | 15674 | intel_setup_outputs(dev); |
11be49eb | 15675 | |
6e9f798d | 15676 | drm_modeset_lock_all(dev); |
043e9bda | 15677 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15678 | drm_modeset_unlock_all(dev); |
46f297fb | 15679 | |
d3fcc808 | 15680 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15681 | struct intel_initial_plane_config plane_config = {}; |
15682 | ||
46f297fb JB |
15683 | if (!crtc->active) |
15684 | continue; | |
15685 | ||
46f297fb | 15686 | /* |
46f297fb JB |
15687 | * Note that reserving the BIOS fb up front prevents us |
15688 | * from stuffing other stolen allocations like the ring | |
15689 | * on top. This prevents some ugliness at boot time, and | |
15690 | * can even allow for smooth boot transitions if the BIOS | |
15691 | * fb is large enough for the active pipe configuration. | |
15692 | */ | |
eeebeac5 ML |
15693 | dev_priv->display.get_initial_plane_config(crtc, |
15694 | &plane_config); | |
15695 | ||
15696 | /* | |
15697 | * If the fb is shared between multiple heads, we'll | |
15698 | * just get the first one. | |
15699 | */ | |
15700 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15701 | } |
d93c0372 MR |
15702 | |
15703 | /* | |
15704 | * Make sure hardware watermarks really match the state we read out. | |
15705 | * Note that we need to do this after reconstructing the BIOS fb's | |
15706 | * since the watermark calculation done here will use pstate->fb. | |
15707 | */ | |
15708 | sanitize_watermarks(dev); | |
2c7111db CW |
15709 | } |
15710 | ||
7fad798e DV |
15711 | static void intel_enable_pipe_a(struct drm_device *dev) |
15712 | { | |
15713 | struct intel_connector *connector; | |
15714 | struct drm_connector *crt = NULL; | |
15715 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15716 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15717 | |
15718 | /* We can't just switch on the pipe A, we need to set things up with a | |
15719 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15720 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15721 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15722 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15723 | crt = &connector->base; | |
15724 | break; | |
15725 | } | |
15726 | } | |
15727 | ||
15728 | if (!crt) | |
15729 | return; | |
15730 | ||
208bf9fd | 15731 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15732 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15733 | } |
15734 | ||
fa555837 DV |
15735 | static bool |
15736 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15737 | { | |
7eb552ae | 15738 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 15739 | struct drm_i915_private *dev_priv = to_i915(dev); |
649636ef | 15740 | u32 val; |
fa555837 | 15741 | |
7eb552ae | 15742 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15743 | return true; |
15744 | ||
649636ef | 15745 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15746 | |
15747 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15748 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15749 | return false; | |
15750 | ||
15751 | return true; | |
15752 | } | |
15753 | ||
02e93c35 VS |
15754 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15755 | { | |
15756 | struct drm_device *dev = crtc->base.dev; | |
15757 | struct intel_encoder *encoder; | |
15758 | ||
15759 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15760 | return true; | |
15761 | ||
15762 | return false; | |
15763 | } | |
15764 | ||
dd756198 VS |
15765 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
15766 | { | |
15767 | struct drm_device *dev = encoder->base.dev; | |
15768 | struct intel_connector *connector; | |
15769 | ||
15770 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15771 | return true; | |
15772 | ||
15773 | return false; | |
15774 | } | |
15775 | ||
24929352 DV |
15776 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15777 | { | |
15778 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 15779 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 15780 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 15781 | |
24929352 | 15782 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
15783 | if (!transcoder_is_dsi(cpu_transcoder)) { |
15784 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15785 | ||
15786 | I915_WRITE(reg, | |
15787 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15788 | } | |
24929352 | 15789 | |
d3eaf884 | 15790 | /* restore vblank interrupts to correct state */ |
9625604c | 15791 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15792 | if (crtc->active) { |
f9cd7b88 VS |
15793 | struct intel_plane *plane; |
15794 | ||
9625604c | 15795 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15796 | |
15797 | /* Disable everything but the primary plane */ | |
15798 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15799 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15800 | continue; | |
15801 | ||
15802 | plane->disable_plane(&plane->base, &crtc->base); | |
15803 | } | |
9625604c | 15804 | } |
d3eaf884 | 15805 | |
24929352 | 15806 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15807 | * disable the crtc (and hence change the state) if it is wrong. Note |
15808 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15809 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15810 | bool plane; |
15811 | ||
78108b7c VS |
15812 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
15813 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
15814 | |
15815 | /* Pipe has the wrong plane attached and the plane is active. | |
15816 | * Temporarily change the plane mapping and disable everything | |
15817 | * ... */ | |
15818 | plane = crtc->plane; | |
b70709a6 | 15819 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15820 | crtc->plane = !plane; |
b17d48e2 | 15821 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15822 | crtc->plane = plane; |
24929352 | 15823 | } |
24929352 | 15824 | |
7fad798e DV |
15825 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15826 | crtc->pipe == PIPE_A && !crtc->active) { | |
15827 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15828 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15829 | * call below we restore the pipe to the right state, but leave | |
15830 | * the required bits on. */ | |
15831 | intel_enable_pipe_a(dev); | |
15832 | } | |
15833 | ||
24929352 DV |
15834 | /* Adjust the state of the output pipe according to whether we |
15835 | * have active connectors/encoders. */ | |
842e0307 | 15836 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15837 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15838 | |
a3ed6aad | 15839 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15840 | /* |
15841 | * We start out with underrun reporting disabled to avoid races. | |
15842 | * For correct bookkeeping mark this on active crtcs. | |
15843 | * | |
c5ab3bc0 DV |
15844 | * Also on gmch platforms we dont have any hardware bits to |
15845 | * disable the underrun reporting. Which means we need to start | |
15846 | * out with underrun reporting disabled also on inactive pipes, | |
15847 | * since otherwise we'll complain about the garbage we read when | |
15848 | * e.g. coming up after runtime pm. | |
15849 | * | |
4cc31489 DV |
15850 | * No protection against concurrent access is required - at |
15851 | * worst a fifo underrun happens which also sets this to false. | |
15852 | */ | |
15853 | crtc->cpu_fifo_underrun_disabled = true; | |
15854 | crtc->pch_fifo_underrun_disabled = true; | |
15855 | } | |
24929352 DV |
15856 | } |
15857 | ||
15858 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15859 | { | |
15860 | struct intel_connector *connector; | |
15861 | struct drm_device *dev = encoder->base.dev; | |
15862 | ||
15863 | /* We need to check both for a crtc link (meaning that the | |
15864 | * encoder is active and trying to read from a pipe) and the | |
15865 | * pipe itself being active. */ | |
15866 | bool has_active_crtc = encoder->base.crtc && | |
15867 | to_intel_crtc(encoder->base.crtc)->active; | |
15868 | ||
dd756198 | 15869 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
15870 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15871 | encoder->base.base.id, | |
8e329a03 | 15872 | encoder->base.name); |
24929352 DV |
15873 | |
15874 | /* Connector is active, but has no active pipe. This is | |
15875 | * fallout from our resume register restoring. Disable | |
15876 | * the encoder manually again. */ | |
15877 | if (encoder->base.crtc) { | |
15878 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15879 | encoder->base.base.id, | |
8e329a03 | 15880 | encoder->base.name); |
24929352 | 15881 | encoder->disable(encoder); |
a62d1497 VS |
15882 | if (encoder->post_disable) |
15883 | encoder->post_disable(encoder); | |
24929352 | 15884 | } |
7f1950fb | 15885 | encoder->base.crtc = NULL; |
24929352 DV |
15886 | |
15887 | /* Inconsistent output/port/pipe state happens presumably due to | |
15888 | * a bug in one of the get_hw_state functions. Or someplace else | |
15889 | * in our code, like the register restore mess on resume. Clamp | |
15890 | * things to off as a safer default. */ | |
3a3371ff | 15891 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15892 | if (connector->encoder != encoder) |
15893 | continue; | |
7f1950fb EE |
15894 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15895 | connector->base.encoder = NULL; | |
24929352 DV |
15896 | } |
15897 | } | |
15898 | /* Enabled encoders without active connectors will be fixed in | |
15899 | * the crtc fixup. */ | |
15900 | } | |
15901 | ||
04098753 | 15902 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f | 15903 | { |
fac5e23e | 15904 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 15905 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15906 | |
04098753 ID |
15907 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15908 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15909 | i915_disable_vga(dev); | |
15910 | } | |
15911 | } | |
15912 | ||
15913 | void i915_redisable_vga(struct drm_device *dev) | |
15914 | { | |
fac5e23e | 15915 | struct drm_i915_private *dev_priv = to_i915(dev); |
04098753 | 15916 | |
8dc8a27c PZ |
15917 | /* This function can be called both from intel_modeset_setup_hw_state or |
15918 | * at a very early point in our resume sequence, where the power well | |
15919 | * structures are not yet restored. Since this function is at a very | |
15920 | * paranoid "someone might have enabled VGA while we were not looking" | |
15921 | * level, just check if the power well is enabled instead of trying to | |
15922 | * follow the "don't touch the power well if we don't need it" policy | |
15923 | * the rest of the driver uses. */ | |
6392f847 | 15924 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15925 | return; |
15926 | ||
04098753 | 15927 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
15928 | |
15929 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15930 | } |
15931 | ||
f9cd7b88 | 15932 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15933 | { |
f9cd7b88 | 15934 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15935 | |
f9cd7b88 | 15936 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15937 | } |
15938 | ||
f9cd7b88 VS |
15939 | /* FIXME read out full plane state for all planes */ |
15940 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15941 | { |
b26d3ea3 | 15942 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15943 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15944 | to_intel_plane_state(primary->state); |
d032ffa0 | 15945 | |
19b8d387 | 15946 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15947 | primary_get_hw_state(to_intel_plane(primary)); |
15948 | ||
15949 | if (plane_state->visible) | |
15950 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15951 | } |
15952 | ||
30e984df | 15953 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 15954 | { |
fac5e23e | 15955 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 15956 | enum pipe pipe; |
24929352 DV |
15957 | struct intel_crtc *crtc; |
15958 | struct intel_encoder *encoder; | |
15959 | struct intel_connector *connector; | |
5358901f | 15960 | int i; |
24929352 | 15961 | |
565602d7 ML |
15962 | dev_priv->active_crtcs = 0; |
15963 | ||
d3fcc808 | 15964 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15965 | struct intel_crtc_state *crtc_state = crtc->config; |
15966 | int pixclk = 0; | |
3b117c8f | 15967 | |
ec2dc6a0 | 15968 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
15969 | memset(crtc_state, 0, sizeof(*crtc_state)); |
15970 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15971 | |
565602d7 ML |
15972 | crtc_state->base.active = crtc_state->base.enable = |
15973 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15974 | ||
15975 | crtc->base.enabled = crtc_state->base.enable; | |
15976 | crtc->active = crtc_state->base.active; | |
15977 | ||
15978 | if (crtc_state->base.active) { | |
15979 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15980 | ||
c89e39f3 | 15981 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) |
565602d7 | 15982 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
9558d15d | 15983 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
565602d7 ML |
15984 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
15985 | else | |
15986 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
9558d15d VS |
15987 | |
15988 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15989 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
15990 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
565602d7 ML |
15991 | } |
15992 | ||
15993 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15994 | |
f9cd7b88 | 15995 | readout_plane_state(crtc); |
24929352 | 15996 | |
78108b7c VS |
15997 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
15998 | crtc->base.base.id, crtc->base.name, | |
24929352 DV |
15999 | crtc->active ? "enabled" : "disabled"); |
16000 | } | |
16001 | ||
5358901f DV |
16002 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16003 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16004 | ||
2edd6443 ACO |
16005 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
16006 | &pll->config.hw_state); | |
3e369b76 | 16007 | pll->config.crtc_mask = 0; |
d3fcc808 | 16008 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 16009 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 16010 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 16011 | } |
2dd66ebd | 16012 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 16013 | |
1e6f2ddc | 16014 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 16015 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
16016 | } |
16017 | ||
b2784e15 | 16018 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16019 | pipe = 0; |
16020 | ||
16021 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
16022 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16023 | encoder->base.crtc = &crtc->base; | |
253c84c8 | 16024 | crtc->config->output_types |= 1 << encoder->type; |
6e3c9717 | 16025 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
16026 | } else { |
16027 | encoder->base.crtc = NULL; | |
16028 | } | |
16029 | ||
6f2bcceb | 16030 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 16031 | encoder->base.base.id, |
8e329a03 | 16032 | encoder->base.name, |
24929352 | 16033 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 16034 | pipe_name(pipe)); |
24929352 DV |
16035 | } |
16036 | ||
3a3371ff | 16037 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16038 | if (connector->get_hw_state(connector)) { |
16039 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
16040 | |
16041 | encoder = connector->encoder; | |
16042 | connector->base.encoder = &encoder->base; | |
16043 | ||
16044 | if (encoder->base.crtc && | |
16045 | encoder->base.crtc->state->active) { | |
16046 | /* | |
16047 | * This has to be done during hardware readout | |
16048 | * because anything calling .crtc_disable may | |
16049 | * rely on the connector_mask being accurate. | |
16050 | */ | |
16051 | encoder->base.crtc->state->connector_mask |= | |
16052 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
16053 | encoder->base.crtc->state->encoder_mask |= |
16054 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
16055 | } |
16056 | ||
24929352 DV |
16057 | } else { |
16058 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16059 | connector->base.encoder = NULL; | |
16060 | } | |
16061 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
16062 | connector->base.base.id, | |
c23cc417 | 16063 | connector->base.name, |
24929352 DV |
16064 | connector->base.encoder ? "enabled" : "disabled"); |
16065 | } | |
7f4c6284 VS |
16066 | |
16067 | for_each_intel_crtc(dev, crtc) { | |
16068 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
16069 | ||
16070 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
16071 | if (crtc->base.state->active) { | |
16072 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
16073 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
16074 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
16075 | ||
16076 | /* | |
16077 | * The initial mode needs to be set in order to keep | |
16078 | * the atomic core happy. It wants a valid mode if the | |
16079 | * crtc's enabled, so we do the above call. | |
16080 | * | |
16081 | * At this point some state updated by the connectors | |
16082 | * in their ->detect() callback has not run yet, so | |
16083 | * no recalculation can be done yet. | |
16084 | * | |
16085 | * Even if we could do a recalculation and modeset | |
16086 | * right now it would cause a double modeset if | |
16087 | * fbdev or userspace chooses a different initial mode. | |
16088 | * | |
16089 | * If that happens, someone indicated they wanted a | |
16090 | * mode change, which means it's safe to do a full | |
16091 | * recalculation. | |
16092 | */ | |
16093 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
16094 | |
16095 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
16096 | update_scanline_offset(crtc); | |
7f4c6284 | 16097 | } |
e3b247da VS |
16098 | |
16099 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 16100 | } |
30e984df DV |
16101 | } |
16102 | ||
043e9bda ML |
16103 | /* Scan out the current hw modeset state, |
16104 | * and sanitizes it to the current state | |
16105 | */ | |
16106 | static void | |
16107 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df | 16108 | { |
fac5e23e | 16109 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 16110 | enum pipe pipe; |
30e984df DV |
16111 | struct intel_crtc *crtc; |
16112 | struct intel_encoder *encoder; | |
35c95375 | 16113 | int i; |
30e984df DV |
16114 | |
16115 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
16116 | |
16117 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 16118 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16119 | intel_sanitize_encoder(encoder); |
16120 | } | |
16121 | ||
055e393f | 16122 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
16123 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16124 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
16125 | intel_dump_pipe_config(crtc, crtc->config, |
16126 | "[setup_hw_state]"); | |
24929352 | 16127 | } |
9a935856 | 16128 | |
d29b2f9d ACO |
16129 | intel_modeset_update_connector_atomic_state(dev); |
16130 | ||
35c95375 DV |
16131 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16132 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16133 | ||
2dd66ebd | 16134 | if (!pll->on || pll->active_mask) |
35c95375 DV |
16135 | continue; |
16136 | ||
16137 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
16138 | ||
2edd6443 | 16139 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
16140 | pll->on = false; |
16141 | } | |
16142 | ||
666a4537 | 16143 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
16144 | vlv_wm_get_hw_state(dev); |
16145 | else if (IS_GEN9(dev)) | |
3078999f PB |
16146 | skl_wm_get_hw_state(dev); |
16147 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 16148 | ilk_wm_get_hw_state(dev); |
292b990e ML |
16149 | |
16150 | for_each_intel_crtc(dev, crtc) { | |
16151 | unsigned long put_domains; | |
16152 | ||
74bff5f9 | 16153 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
16154 | if (WARN_ON(put_domains)) |
16155 | modeset_put_power_domains(dev_priv, put_domains); | |
16156 | } | |
16157 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
16158 | |
16159 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 16160 | } |
7d0bc1ea | 16161 | |
043e9bda ML |
16162 | void intel_display_resume(struct drm_device *dev) |
16163 | { | |
e2c8b870 ML |
16164 | struct drm_i915_private *dev_priv = to_i915(dev); |
16165 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
16166 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 16167 | int ret; |
e2c8b870 | 16168 | bool setup = false; |
f30da187 | 16169 | |
e2c8b870 | 16170 | dev_priv->modeset_restore_state = NULL; |
043e9bda | 16171 | |
ea49c9ac ML |
16172 | /* |
16173 | * This is a cludge because with real atomic modeset mode_config.mutex | |
16174 | * won't be taken. Unfortunately some probed state like | |
16175 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
16176 | * it here for now. | |
16177 | */ | |
16178 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 16179 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 16180 | |
e2c8b870 ML |
16181 | retry: |
16182 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
043e9bda | 16183 | |
e2c8b870 ML |
16184 | if (ret == 0 && !setup) { |
16185 | setup = true; | |
043e9bda | 16186 | |
e2c8b870 ML |
16187 | intel_modeset_setup_hw_state(dev); |
16188 | i915_redisable_vga(dev); | |
45e2b5f6 | 16189 | } |
8af6cf88 | 16190 | |
e2c8b870 ML |
16191 | if (ret == 0 && state) { |
16192 | struct drm_crtc_state *crtc_state; | |
16193 | struct drm_crtc *crtc; | |
16194 | int i; | |
043e9bda | 16195 | |
e2c8b870 ML |
16196 | state->acquire_ctx = &ctx; |
16197 | ||
e3d5457c VS |
16198 | /* ignore any reset values/BIOS leftovers in the WM registers */ |
16199 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
16200 | ||
e2c8b870 ML |
16201 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
16202 | /* | |
16203 | * Force recalculation even if we restore | |
16204 | * current state. With fast modeset this may not result | |
16205 | * in a modeset when the state is compatible. | |
16206 | */ | |
16207 | crtc_state->mode_changed = true; | |
16208 | } | |
16209 | ||
16210 | ret = drm_atomic_commit(state); | |
043e9bda ML |
16211 | } |
16212 | ||
e2c8b870 ML |
16213 | if (ret == -EDEADLK) { |
16214 | drm_modeset_backoff(&ctx); | |
16215 | goto retry; | |
16216 | } | |
043e9bda | 16217 | |
e2c8b870 ML |
16218 | drm_modeset_drop_locks(&ctx); |
16219 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 16220 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 16221 | |
e2c8b870 ML |
16222 | if (ret) { |
16223 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
16224 | drm_atomic_state_free(state); | |
16225 | } | |
2c7111db CW |
16226 | } |
16227 | ||
16228 | void intel_modeset_gem_init(struct drm_device *dev) | |
16229 | { | |
dc97997a | 16230 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 16231 | struct drm_crtc *c; |
2ff8fde1 | 16232 | struct drm_i915_gem_object *obj; |
e0d6149b | 16233 | int ret; |
484b41dd | 16234 | |
dc97997a | 16235 | intel_init_gt_powersave(dev_priv); |
ae48434c | 16236 | |
1833b134 | 16237 | intel_modeset_init_hw(dev); |
02e792fb | 16238 | |
1ee8da6d | 16239 | intel_setup_overlay(dev_priv); |
484b41dd JB |
16240 | |
16241 | /* | |
16242 | * Make sure any fbs we allocated at startup are properly | |
16243 | * pinned & fenced. When we do the allocation it's too early | |
16244 | * for this. | |
16245 | */ | |
70e1e0ec | 16246 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
16247 | obj = intel_fb_obj(c->primary->fb); |
16248 | if (obj == NULL) | |
484b41dd JB |
16249 | continue; |
16250 | ||
e0d6149b | 16251 | mutex_lock(&dev->struct_mutex); |
3465c580 VS |
16252 | ret = intel_pin_and_fence_fb_obj(c->primary->fb, |
16253 | c->primary->state->rotation); | |
e0d6149b TU |
16254 | mutex_unlock(&dev->struct_mutex); |
16255 | if (ret) { | |
484b41dd JB |
16256 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
16257 | to_intel_crtc(c)->pipe); | |
66e514c1 | 16258 | drm_framebuffer_unreference(c->primary->fb); |
5a21b665 | 16259 | c->primary->fb = NULL; |
36750f28 | 16260 | c->primary->crtc = c->primary->state->crtc = NULL; |
5a21b665 | 16261 | update_state_fb(c->primary); |
36750f28 | 16262 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
16263 | } |
16264 | } | |
1ebaa0b9 CW |
16265 | } |
16266 | ||
16267 | int intel_connector_register(struct drm_connector *connector) | |
16268 | { | |
16269 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
16270 | int ret; | |
16271 | ||
16272 | ret = intel_backlight_device_register(intel_connector); | |
16273 | if (ret) | |
16274 | goto err; | |
16275 | ||
16276 | return 0; | |
0962c3c9 | 16277 | |
1ebaa0b9 CW |
16278 | err: |
16279 | return ret; | |
79e53945 JB |
16280 | } |
16281 | ||
c191eca1 | 16282 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 16283 | { |
e63d87c0 | 16284 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 16285 | |
e63d87c0 | 16286 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 16287 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
16288 | } |
16289 | ||
79e53945 JB |
16290 | void intel_modeset_cleanup(struct drm_device *dev) |
16291 | { | |
fac5e23e | 16292 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 16293 | |
dc97997a | 16294 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 16295 | |
fd0c0642 DV |
16296 | /* |
16297 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16298 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16299 | * experience fancy races otherwise. |
16300 | */ | |
2aeb7d3a | 16301 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16302 | |
fd0c0642 DV |
16303 | /* |
16304 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16305 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16306 | */ | |
f87ea761 | 16307 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16308 | |
723bfd70 JB |
16309 | intel_unregister_dsm_handler(); |
16310 | ||
c937ab3e | 16311 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16312 | |
1630fe75 CW |
16313 | /* flush any delayed tasks or pending work */ |
16314 | flush_scheduled_work(); | |
16315 | ||
79e53945 | 16316 | drm_mode_config_cleanup(dev); |
4d7bb011 | 16317 | |
1ee8da6d | 16318 | intel_cleanup_overlay(dev_priv); |
ae48434c | 16319 | |
dc97997a | 16320 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 DV |
16321 | |
16322 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16323 | } |
16324 | ||
df0e9248 CW |
16325 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16326 | struct intel_encoder *encoder) | |
16327 | { | |
16328 | connector->encoder = encoder; | |
16329 | drm_mode_connector_attach_encoder(&connector->base, | |
16330 | &encoder->base); | |
79e53945 | 16331 | } |
28d52043 DA |
16332 | |
16333 | /* | |
16334 | * set vga decode state - true == enable VGA decode | |
16335 | */ | |
16336 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16337 | { | |
fac5e23e | 16338 | struct drm_i915_private *dev_priv = to_i915(dev); |
a885b3cc | 16339 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16340 | u16 gmch_ctrl; |
16341 | ||
75fa041d CW |
16342 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16343 | DRM_ERROR("failed to read control word\n"); | |
16344 | return -EIO; | |
16345 | } | |
16346 | ||
c0cc8a55 CW |
16347 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16348 | return 0; | |
16349 | ||
28d52043 DA |
16350 | if (state) |
16351 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16352 | else | |
16353 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16354 | |
16355 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16356 | DRM_ERROR("failed to write control word\n"); | |
16357 | return -EIO; | |
16358 | } | |
16359 | ||
28d52043 DA |
16360 | return 0; |
16361 | } | |
c4a1d9e4 | 16362 | |
c4a1d9e4 | 16363 | struct intel_display_error_state { |
ff57f1b0 PZ |
16364 | |
16365 | u32 power_well_driver; | |
16366 | ||
63b66e5b CW |
16367 | int num_transcoders; |
16368 | ||
c4a1d9e4 CW |
16369 | struct intel_cursor_error_state { |
16370 | u32 control; | |
16371 | u32 position; | |
16372 | u32 base; | |
16373 | u32 size; | |
52331309 | 16374 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16375 | |
16376 | struct intel_pipe_error_state { | |
ddf9c536 | 16377 | bool power_domain_on; |
c4a1d9e4 | 16378 | u32 source; |
f301b1e1 | 16379 | u32 stat; |
52331309 | 16380 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16381 | |
16382 | struct intel_plane_error_state { | |
16383 | u32 control; | |
16384 | u32 stride; | |
16385 | u32 size; | |
16386 | u32 pos; | |
16387 | u32 addr; | |
16388 | u32 surface; | |
16389 | u32 tile_offset; | |
52331309 | 16390 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16391 | |
16392 | struct intel_transcoder_error_state { | |
ddf9c536 | 16393 | bool power_domain_on; |
63b66e5b CW |
16394 | enum transcoder cpu_transcoder; |
16395 | ||
16396 | u32 conf; | |
16397 | ||
16398 | u32 htotal; | |
16399 | u32 hblank; | |
16400 | u32 hsync; | |
16401 | u32 vtotal; | |
16402 | u32 vblank; | |
16403 | u32 vsync; | |
16404 | } transcoder[4]; | |
c4a1d9e4 CW |
16405 | }; |
16406 | ||
16407 | struct intel_display_error_state * | |
c033666a | 16408 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 16409 | { |
c4a1d9e4 | 16410 | struct intel_display_error_state *error; |
63b66e5b CW |
16411 | int transcoders[] = { |
16412 | TRANSCODER_A, | |
16413 | TRANSCODER_B, | |
16414 | TRANSCODER_C, | |
16415 | TRANSCODER_EDP, | |
16416 | }; | |
c4a1d9e4 CW |
16417 | int i; |
16418 | ||
c033666a | 16419 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
16420 | return NULL; |
16421 | ||
9d1cb914 | 16422 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16423 | if (error == NULL) |
16424 | return NULL; | |
16425 | ||
c033666a | 16426 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
16427 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16428 | ||
055e393f | 16429 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16430 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16431 | __intel_display_power_is_enabled(dev_priv, |
16432 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16433 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16434 | continue; |
16435 | ||
5efb3e28 VS |
16436 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16437 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16438 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16439 | |
16440 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16441 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 16442 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 16443 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16444 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16445 | } | |
c033666a | 16446 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 16447 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 16448 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
16449 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
16450 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16451 | } | |
16452 | ||
c4a1d9e4 | 16453 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16454 | |
c033666a | 16455 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 16456 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16457 | } |
16458 | ||
4d1de975 | 16459 | /* Note: this does not include DSI transcoders. */ |
c033666a | 16460 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 16461 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
16462 | error->num_transcoders++; /* Account for eDP. */ |
16463 | ||
16464 | for (i = 0; i < error->num_transcoders; i++) { | |
16465 | enum transcoder cpu_transcoder = transcoders[i]; | |
16466 | ||
ddf9c536 | 16467 | error->transcoder[i].power_domain_on = |
f458ebbc | 16468 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16469 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16470 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16471 | continue; |
16472 | ||
63b66e5b CW |
16473 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16474 | ||
16475 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16476 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16477 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16478 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16479 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16480 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16481 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16482 | } |
16483 | ||
16484 | return error; | |
16485 | } | |
16486 | ||
edc3d884 MK |
16487 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16488 | ||
c4a1d9e4 | 16489 | void |
edc3d884 | 16490 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16491 | struct drm_device *dev, |
16492 | struct intel_display_error_state *error) | |
16493 | { | |
fac5e23e | 16494 | struct drm_i915_private *dev_priv = to_i915(dev); |
c4a1d9e4 CW |
16495 | int i; |
16496 | ||
63b66e5b CW |
16497 | if (!error) |
16498 | return; | |
16499 | ||
edc3d884 | 16500 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16501 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16502 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16503 | error->power_well_driver); |
055e393f | 16504 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16505 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16506 | err_printf(m, " Power: %s\n", |
87ad3212 | 16507 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16508 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16509 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16510 | |
16511 | err_printf(m, "Plane [%d]:\n", i); | |
16512 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16513 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16514 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16515 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16516 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16517 | } |
4b71a570 | 16518 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16519 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16520 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16521 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16522 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16523 | } |
16524 | ||
edc3d884 MK |
16525 | err_printf(m, "Cursor [%d]:\n", i); |
16526 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16527 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16528 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16529 | } |
63b66e5b CW |
16530 | |
16531 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 16532 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 16533 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16534 | err_printf(m, " Power: %s\n", |
87ad3212 | 16535 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16536 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16537 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16538 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16539 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16540 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16541 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16542 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16543 | } | |
c4a1d9e4 | 16544 | } |