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drm/i915: Replace __I915__ with typesafe variant
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CommitLineData
79e53945
JB
1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
178f736a 29#include <linux/hdmi.h>
760285e7 30#include <drm/i915_drm.h>
80824003 31#include "i915_drv.h"
760285e7
DH
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_fb_helper.h>
0e32b39c 35#include <drm/drm_dp_mst_helper.h>
913d8d11 36
1d5bfac9
DV
37/**
38 * _wait_for - magic (register) wait macro
39 *
40 * Does the right thing for modeset paths when run under kdgb or similar atomic
41 * contexts. Note that it's important that we check the condition again after
42 * having timed out, since the timeout could be due to preemption or similar and
43 * we've never had a chance to check the condition before the timeout.
44 */
481b6af3 45#define _wait_for(COND, MS, W) ({ \
1d5bfac9 46 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
913d8d11 47 int ret__ = 0; \
0206e353 48 while (!(COND)) { \
913d8d11 49 if (time_after(jiffies, timeout__)) { \
1d5bfac9
DV
50 if (!(COND)) \
51 ret__ = -ETIMEDOUT; \
913d8d11
CW
52 break; \
53 } \
0cc2764c
BW
54 if (W && drm_can_sleep()) { \
55 msleep(W); \
56 } else { \
57 cpu_relax(); \
58 } \
913d8d11
CW
59 } \
60 ret__; \
61})
62
481b6af3
CW
63#define wait_for(COND, MS) _wait_for(COND, MS, 1)
64#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
6effa33b
DV
65#define wait_for_atomic_us(COND, US) _wait_for((COND), \
66 DIV_ROUND_UP((US), 1000), 0)
481b6af3 67
49938ac4
JN
68#define KHz(x) (1000 * (x))
69#define MHz(x) KHz(1000 * (x))
021357ac 70
79e53945
JB
71/*
72 * Display related stuff
73 */
74
75/* store information about an Ixxx DVO */
76/* The i830->i865 use multiple DVOs with multiple i2cs */
77/* the i915, i945 have a single sDVO i2c bus - which is different */
78#define MAX_OUTPUTS 6
79/* maximum connectors per crtcs in the mode set */
79e53945 80
4726e0b0
SK
81/* Maximum cursor sizes */
82#define GEN2_CURSOR_WIDTH 64
83#define GEN2_CURSOR_HEIGHT 64
068be561
DL
84#define MAX_CURSOR_WIDTH 256
85#define MAX_CURSOR_HEIGHT 256
4726e0b0 86
79e53945
JB
87#define INTEL_I2C_BUS_DVO 1
88#define INTEL_I2C_BUS_SDVO 2
89
90/* these are outputs from the chip - integrated only
91 external chips are via DVO or SDVO output */
92#define INTEL_OUTPUT_UNUSED 0
93#define INTEL_OUTPUT_ANALOG 1
94#define INTEL_OUTPUT_DVO 2
95#define INTEL_OUTPUT_SDVO 3
96#define INTEL_OUTPUT_LVDS 4
97#define INTEL_OUTPUT_TVOUT 5
7d57382e 98#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 99#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 100#define INTEL_OUTPUT_EDP 8
72ffa333
JN
101#define INTEL_OUTPUT_DSI 9
102#define INTEL_OUTPUT_UNKNOWN 10
0e32b39c 103#define INTEL_OUTPUT_DP_MST 11
79e53945
JB
104
105#define INTEL_DVO_CHIP_NONE 0
106#define INTEL_DVO_CHIP_LVDS 1
107#define INTEL_DVO_CHIP_TMDS 2
108#define INTEL_DVO_CHIP_TVOUT 4
109
dfba2e2d
SK
110#define INTEL_DSI_VIDEO_MODE 0
111#define INTEL_DSI_COMMAND_MODE 1
72ffa333 112
79e53945
JB
113struct intel_framebuffer {
114 struct drm_framebuffer base;
05394f39 115 struct drm_i915_gem_object *obj;
79e53945
JB
116};
117
37811fcc
CW
118struct intel_fbdev {
119 struct drm_fb_helper helper;
8bcd4553 120 struct intel_framebuffer *fb;
37811fcc
CW
121 struct list_head fbdev_list;
122 struct drm_display_mode *our_mode;
d978ef14 123 int preferred_bpp;
37811fcc 124};
79e53945 125
21d40d37 126struct intel_encoder {
4ef69c7a 127 struct drm_encoder base;
9a935856
DV
128 /*
129 * The new crtc this encoder will be driven from. Only differs from
130 * base->crtc while a modeset is in progress.
131 */
132 struct intel_crtc *new_crtc;
133
79e53945 134 int type;
bc079e8b 135 unsigned int cloneable;
5ab432ef 136 bool connectors_active;
21d40d37 137 void (*hot_plug)(struct intel_encoder *);
7ae89233
DV
138 bool (*compute_config)(struct intel_encoder *,
139 struct intel_crtc_config *);
dafd226c 140 void (*pre_pll_enable)(struct intel_encoder *);
bf49ec8c 141 void (*pre_enable)(struct intel_encoder *);
ef9c3aee 142 void (*enable)(struct intel_encoder *);
6cc5f341 143 void (*mode_set)(struct intel_encoder *intel_encoder);
ef9c3aee 144 void (*disable)(struct intel_encoder *);
bf49ec8c 145 void (*post_disable)(struct intel_encoder *);
f0947c37
DV
146 /* Read out the current hw state of this connector, returning true if
147 * the encoder is active. If the encoder is enabled it also set the pipe
148 * it is connected to in the pipe parameter. */
149 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
045ac3b5 150 /* Reconstructs the equivalent mode flags for the current hardware
fdafa9e2 151 * state. This must be called _after_ display->get_pipe_config has
63000ef6
XZ
152 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
153 * be set correctly before calling this function. */
045ac3b5
JB
154 void (*get_config)(struct intel_encoder *,
155 struct intel_crtc_config *pipe_config);
f8aed700 156 int crtc_mask;
1d843f9d 157 enum hpd_pin hpd_pin;
79e53945
JB
158};
159
1d508706 160struct intel_panel {
dd06f90e 161 struct drm_display_mode *fixed_mode;
ec9ed197 162 struct drm_display_mode *downclock_mode;
4d891523 163 int fitting_mode;
58c68779
JN
164
165 /* backlight */
166 struct {
c91c9f32 167 bool present;
58c68779 168 u32 level;
6dda730e 169 u32 min;
7bd688cd 170 u32 max;
58c68779 171 bool enabled;
636baebf
JN
172 bool combination_mode; /* gen 2/4 only */
173 bool active_low_pwm;
58c68779
JN
174 struct backlight_device *device;
175 } backlight;
1d508706
JN
176};
177
5daa55eb
ZW
178struct intel_connector {
179 struct drm_connector base;
9a935856
DV
180 /*
181 * The fixed encoder this connector is connected to.
182 */
df0e9248 183 struct intel_encoder *encoder;
9a935856
DV
184
185 /*
186 * The new encoder this connector will be driven. Only differs from
187 * encoder while a modeset is in progress.
188 */
189 struct intel_encoder *new_encoder;
190
f0947c37
DV
191 /* Reads out the current hw, returning true if the connector is enabled
192 * and active (i.e. dpms ON state). */
193 bool (*get_hw_state)(struct intel_connector *);
1d508706 194
4932e2c3
ID
195 /*
196 * Removes all interfaces through which the connector is accessible
197 * - like sysfs, debugfs entries -, so that no new operations can be
198 * started on the connector. Also makes sure all currently pending
199 * operations finish before returing.
200 */
201 void (*unregister)(struct intel_connector *);
202
1d508706
JN
203 /* Panel info for eDP and LVDS */
204 struct intel_panel panel;
9cd300e0
JN
205
206 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
207 struct edid *edid;
821450c6
EE
208
209 /* since POLL and HPD connectors may use the same HPD line keep the native
210 state of connector->polled in case hotplug storm detection changes it */
211 u8 polled;
0e32b39c
DA
212
213 void *port; /* store this opaque as its illegal to dereference it */
214
215 struct intel_dp *mst_port;
5daa55eb
ZW
216};
217
80ad9206
VS
218typedef struct dpll {
219 /* given values */
220 int n;
221 int m1, m2;
222 int p1, p2;
223 /* derived values */
224 int dot;
225 int vco;
226 int m;
227 int p;
228} intel_clock_t;
229
46f297fb 230struct intel_plane_config {
46f297fb
JB
231 bool tiled;
232 int size;
233 u32 base;
234};
235
b8cecdf5 236struct intel_crtc_config {
bb760063
DV
237 /**
238 * quirks - bitfield with hw state readout quirks
239 *
240 * For various reasons the hw state readout code might not be able to
241 * completely faithfully read out the current state. These cases are
242 * tracked with quirk flags so that fastboot and state checker can act
243 * accordingly.
244 */
9953599b
DV
245#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
246#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
bb760063
DV
247 unsigned long quirks;
248
5113bc9b
VS
249 /* User requested mode, only valid as a starting point to
250 * compute adjusted_mode, except in the case of (S)DVO where
251 * it's also for the output timings of the (S)DVO chip.
252 * adjusted_mode will then correspond to the S(DVO) chip's
253 * preferred input timings. */
b8cecdf5 254 struct drm_display_mode requested_mode;
3c52f4eb 255 /* Actual pipe timings ie. what we program into the pipe timing
241bfc38 256 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
b8cecdf5 257 struct drm_display_mode adjusted_mode;
37327abd
VS
258
259 /* Pipe source size (ie. panel fitter input size)
260 * All planes will be positioned inside this space,
261 * and get clipped at the edges. */
262 int pipe_src_w, pipe_src_h;
263
5bfe2ac0
DV
264 /* Whether to set up the PCH/FDI. Note that we never allow sharing
265 * between pch encoders and cpu encoders. */
266 bool has_pch_encoder;
50f3b016 267
3b117c8f
DV
268 /* CPU Transcoder for the pipe. Currently this can only differ from the
269 * pipe on Haswell (where we have a special eDP transcoder). */
270 enum transcoder cpu_transcoder;
271
50f3b016
DV
272 /*
273 * Use reduced/limited/broadcast rbg range, compressing from the full
274 * range fed into the crtcs.
275 */
276 bool limited_color_range;
277
03afc4a2
DV
278 /* DP has a bunch of special case unfortunately, so mark the pipe
279 * accordingly. */
280 bool has_dp_encoder;
d8b32247 281
6897b4b5
DV
282 /* Whether we should send NULL infoframes. Required for audio. */
283 bool has_hdmi_sink;
284
9ed109a7
DV
285 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
286 * has_dp_encoder is set. */
287 bool has_audio;
288
d8b32247
DV
289 /*
290 * Enable dithering, used when the selected pipe bpp doesn't match the
291 * plane bpp.
292 */
965e0c48 293 bool dither;
f47709a9
DV
294
295 /* Controls for the clock computation, to override various stages. */
296 bool clock_set;
297
09ede541
DV
298 /* SDVO TV has a bunch of special case. To make multifunction encoders
299 * work correctly, we need to track this at runtime.*/
300 bool sdvo_tv_clock;
301
e29c22c0
DV
302 /*
303 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
304 * required. This is set in the 2nd loop of calling encoder's
305 * ->compute_config if the first pick doesn't work out.
306 */
307 bool bw_constrained;
308
f47709a9
DV
309 /* Settings for the intel dpll used on pretty much everything but
310 * haswell. */
80ad9206 311 struct dpll dpll;
f47709a9 312
a43f6e0f
DV
313 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
314 enum intel_dpll_id shared_dpll;
315
de7cfc63
DV
316 /* PORT_CLK_SEL for DDI ports. */
317 uint32_t ddi_pll_sel;
318
66e985c0
DV
319 /* Actual register state of the dpll, for shared dpll cross-checking. */
320 struct intel_dpll_hw_state dpll_hw_state;
321
965e0c48 322 int pipe_bpp;
6cf86a5e 323 struct intel_link_m_n dp_m_n;
ff9a6750 324
439d7ac0
PB
325 /* m2_n2 for eDP downclock */
326 struct intel_link_m_n dp_m2_n2;
f769cd24 327 bool has_drrs;
439d7ac0 328
ff9a6750
DV
329 /*
330 * Frequence the dpll for the port should run at. Differs from the
3c52f4eb
VS
331 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
332 * already multiplied by pixel_multiplier.
df92b1e6 333 */
ff9a6750
DV
334 int port_clock;
335
6cc5f341
DV
336 /* Used by SDVO (and if we ever fix it, HDMI). */
337 unsigned pixel_multiplier;
2dd24552
JB
338
339 /* Panel fitter controls for gen2-gen4 + VLV */
b074cec8
JB
340 struct {
341 u32 control;
342 u32 pgm_ratios;
68fc8742 343 u32 lvds_border_bits;
b074cec8
JB
344 } gmch_pfit;
345
346 /* Panel fitter placement and size for Ironlake+ */
347 struct {
348 u32 pos;
349 u32 size;
fd4daa9c 350 bool enabled;
fabf6e51 351 bool force_thru;
b074cec8 352 } pch_pfit;
33d29b14 353
ca3a0ff8 354 /* FDI configuration, only valid if has_pch_encoder is set. */
33d29b14 355 int fdi_lanes;
ca3a0ff8 356 struct intel_link_m_n fdi_m_n;
42db64ef
PZ
357
358 bool ips_enabled;
cf532bb2
VS
359
360 bool double_wide;
0e32b39c
DA
361
362 bool dp_encoder_is_mst;
363 int pbn;
b8cecdf5
DV
364};
365
0b2ae6d7
VS
366struct intel_pipe_wm {
367 struct intel_wm_level wm[5];
368 uint32_t linetime;
369 bool fbc_wm_enabled;
2a44b76b
VS
370 bool pipe_enabled;
371 bool sprites_enabled;
372 bool sprites_scaled;
0b2ae6d7
VS
373};
374
84c33a64
SG
375struct intel_mmio_flip {
376 u32 seqno;
377 u32 ring_id;
378};
379
79e53945
JB
380struct intel_crtc {
381 struct drm_crtc base;
80824003
JB
382 enum pipe pipe;
383 enum plane plane;
79e53945 384 u8 lut_r[256], lut_g[256], lut_b[256];
08a48469
DV
385 /*
386 * Whether the crtc and the connected output pipeline is active. Implies
387 * that crtc->enabled is set, i.e. the current mode configuration has
388 * some outputs connected to this crtc.
08a48469
DV
389 */
390 bool active;
6efdf354 391 unsigned long enabled_power_domains;
4c445e0e 392 bool primary_enabled; /* is the primary plane (partially) visible? */
652c393a 393 bool lowfreq_avail;
02e792fb 394 struct intel_overlay *overlay;
6b95a207 395 struct intel_unpin_work *unpin_work;
cda4b7d3 396
b4a98e57
CW
397 atomic_t unpin_work_count;
398
e506a0c6
DV
399 /* Display surface base address adjustement for pageflips. Note that on
400 * gen4+ this only adjusts up to a tile, offsets within a tile are
401 * handled in the hw itself (with the TILEOFF register). */
402 unsigned long dspaddr_offset;
403
05394f39 404 struct drm_i915_gem_object *cursor_bo;
cda4b7d3 405 uint32_t cursor_addr;
cda4b7d3 406 int16_t cursor_width, cursor_height;
4b0e333e 407 uint32_t cursor_cntl;
dc41c154 408 uint32_t cursor_size;
4b0e333e 409 uint32_t cursor_base;
4b645f14 410
46f297fb 411 struct intel_plane_config plane_config;
b8cecdf5 412 struct intel_crtc_config config;
50741abc 413 struct intel_crtc_config *new_config;
7668851f 414 bool new_enabled;
b8cecdf5 415
10d83730
VS
416 /* reset counter value when the last flip was submitted */
417 unsigned int reset_counter;
8664281b
PZ
418
419 /* Access to these should be protected by dev_priv->irq_lock. */
420 bool cpu_fifo_underrun_disabled;
421 bool pch_fifo_underrun_disabled;
0b2ae6d7
VS
422
423 /* per-pipe watermark state */
424 struct {
425 /* watermarks currently being used */
426 struct intel_pipe_wm active;
427 } wm;
8d7849db 428
80715b2f 429 int scanline_offset;
84c33a64 430 struct intel_mmio_flip mmio_flip;
79e53945
JB
431};
432
c35426d2
VS
433struct intel_plane_wm_parameters {
434 uint32_t horiz_pixels;
ed57cb8a 435 uint32_t vert_pixels;
c35426d2
VS
436 uint8_t bytes_per_pixel;
437 bool enabled;
438 bool scaled;
439};
440
b840d907
JB
441struct intel_plane {
442 struct drm_plane base;
7f1f3851 443 int plane;
b840d907
JB
444 enum pipe pipe;
445 struct drm_i915_gem_object *obj;
2d354c34 446 bool can_scale;
b840d907 447 int max_downscale;
5e1bac2f
JB
448 int crtc_x, crtc_y;
449 unsigned int crtc_w, crtc_h;
450 uint32_t src_x, src_y;
451 uint32_t src_w, src_h;
76eebda7 452 unsigned int rotation;
526682e9
PZ
453
454 /* Since we need to change the watermarks before/after
455 * enabling/disabling the planes, we need to store the parameters here
456 * as the other pieces of the struct may not reflect the values we want
457 * for the watermark calculations. Currently only Haswell uses this.
458 */
c35426d2 459 struct intel_plane_wm_parameters wm;
526682e9 460
b840d907 461 void (*update_plane)(struct drm_plane *plane,
b39d53f6 462 struct drm_crtc *crtc,
b840d907
JB
463 struct drm_framebuffer *fb,
464 struct drm_i915_gem_object *obj,
465 int crtc_x, int crtc_y,
466 unsigned int crtc_w, unsigned int crtc_h,
467 uint32_t x, uint32_t y,
468 uint32_t src_w, uint32_t src_h);
b39d53f6
VS
469 void (*disable_plane)(struct drm_plane *plane,
470 struct drm_crtc *crtc);
8ea30864
JB
471 int (*update_colorkey)(struct drm_plane *plane,
472 struct drm_intel_sprite_colorkey *key);
473 void (*get_colorkey)(struct drm_plane *plane,
474 struct drm_intel_sprite_colorkey *key);
b840d907
JB
475};
476
b445e3b0
ED
477struct intel_watermark_params {
478 unsigned long fifo_size;
479 unsigned long max_wm;
480 unsigned long default_wm;
481 unsigned long guard_size;
482 unsigned long cacheline_size;
483};
484
485struct cxsr_latency {
486 int is_desktop;
487 int is_ddr3;
488 unsigned long fsb_freq;
489 unsigned long mem_freq;
490 unsigned long display_sr;
491 unsigned long display_hpll_disable;
492 unsigned long cursor_sr;
493 unsigned long cursor_hpll_disable;
494};
495
79e53945 496#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 497#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 498#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 499#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 500#define to_intel_plane(x) container_of(x, struct intel_plane, base)
155e6369 501#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
79e53945 502
f5bbfca3 503struct intel_hdmi {
b242b7f7 504 u32 hdmi_reg;
f5bbfca3 505 int ddc_bus;
f5bbfca3 506 uint32_t color_range;
55bc60db 507 bool color_range_auto;
f5bbfca3
ED
508 bool has_hdmi_sink;
509 bool has_audio;
510 enum hdmi_force_audio force_audio;
abedc077 511 bool rgb_quant_range_selectable;
94a11ddc 512 enum hdmi_picture_aspect aspect_ratio;
f5bbfca3 513 void (*write_infoframe)(struct drm_encoder *encoder,
178f736a 514 enum hdmi_infoframe_type type,
fff63867 515 const void *frame, ssize_t len);
687f4d06 516 void (*set_infoframes)(struct drm_encoder *encoder,
6897b4b5 517 bool enable,
687f4d06 518 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED
519};
520
0e32b39c 521struct intel_dp_mst_encoder;
b091cd92 522#define DP_MAX_DOWNSTREAM_PORTS 0x10
54d63ca6 523
4f9db5b5
PB
524/**
525 * HIGH_RR is the highest eDP panel refresh rate read from EDID
526 * LOW_RR is the lowest eDP panel refresh rate found from EDID
527 * parsing for same resolution.
528 */
529enum edp_drrs_refresh_rate_type {
530 DRRS_HIGH_RR,
531 DRRS_LOW_RR,
532 DRRS_MAX_RR, /* RR count */
533};
534
54d63ca6 535struct intel_dp {
54d63ca6 536 uint32_t output_reg;
9ed35ab1 537 uint32_t aux_ch_ctl_reg;
54d63ca6 538 uint32_t DP;
54d63ca6
SK
539 bool has_audio;
540 enum hdmi_force_audio force_audio;
541 uint32_t color_range;
55bc60db 542 bool color_range_auto;
54d63ca6
SK
543 uint8_t link_bw;
544 uint8_t lane_count;
545 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
2293bb5c 546 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
b091cd92 547 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
9d1a1031 548 struct drm_dp_aux aux;
54d63ca6
SK
549 uint8_t train_set[4];
550 int panel_power_up_delay;
551 int panel_power_down_delay;
552 int panel_power_cycle_delay;
553 int backlight_on_delay;
554 int backlight_off_delay;
54d63ca6
SK
555 struct delayed_work panel_vdd_work;
556 bool want_panel_vdd;
dce56b3c
PZ
557 unsigned long last_power_cycle;
558 unsigned long last_power_on;
559 unsigned long last_backlight_off;
5d42f82a 560
01527b31
CT
561 struct notifier_block edp_notifier;
562
06ea66b6 563 bool use_tps3;
0e32b39c
DA
564 bool can_mst; /* this port supports mst */
565 bool is_mst;
566 int active_mst_links;
567 /* connector directly attached - won't be use for modeset in mst world */
dd06f90e 568 struct intel_connector *attached_connector;
ec5b01dd 569
0e32b39c
DA
570 /* mst connector list */
571 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
572 struct drm_dp_mst_topology_mgr mst_mgr;
573
ec5b01dd 574 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
153b1100
DL
575 /*
576 * This function returns the value we have to program the AUX_CTL
577 * register with to kick off an AUX transaction.
578 */
579 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
580 bool has_aux_irq,
581 int send_bytes,
582 uint32_t aux_clock_divider);
4f9db5b5
PB
583 struct {
584 enum drrs_support_type type;
585 enum edp_drrs_refresh_rate_type refresh_rate_type;
439d7ac0 586 struct mutex mutex;
4f9db5b5
PB
587 } drrs_state;
588
54d63ca6
SK
589};
590
da63a9f2
PZ
591struct intel_digital_port {
592 struct intel_encoder base;
174edf1f 593 enum port port;
bcf53de4 594 u32 saved_port_bits;
da63a9f2
PZ
595 struct intel_dp dp;
596 struct intel_hdmi hdmi;
13cf5504 597 bool (*hpd_pulse)(struct intel_digital_port *, bool);
da63a9f2
PZ
598};
599
0e32b39c
DA
600struct intel_dp_mst_encoder {
601 struct intel_encoder base;
602 enum pipe pipe;
603 struct intel_digital_port *primary;
604 void *port; /* store this opaque as its illegal to dereference it */
605};
606
89b667f8
JB
607static inline int
608vlv_dport_to_channel(struct intel_digital_port *dport)
609{
610 switch (dport->port) {
611 case PORT_B:
00fc31b7 612 case PORT_D:
e4607fcf 613 return DPIO_CH0;
89b667f8 614 case PORT_C:
e4607fcf 615 return DPIO_CH1;
89b667f8
JB
616 default:
617 BUG();
618 }
619}
620
eb69b0e5
CML
621static inline int
622vlv_pipe_to_channel(enum pipe pipe)
623{
624 switch (pipe) {
625 case PIPE_A:
626 case PIPE_C:
627 return DPIO_CH0;
628 case PIPE_B:
629 return DPIO_CH1;
630 default:
631 BUG();
632 }
633}
634
f875c15a
CW
635static inline struct drm_crtc *
636intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
637{
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 return dev_priv->pipe_to_crtc_mapping[pipe];
640}
641
417ae147
CW
642static inline struct drm_crtc *
643intel_get_crtc_for_plane(struct drm_device *dev, int plane)
644{
645 struct drm_i915_private *dev_priv = dev->dev_private;
646 return dev_priv->plane_to_crtc_mapping[plane];
647}
648
4e5359cd
SF
649struct intel_unpin_work {
650 struct work_struct work;
b4a98e57 651 struct drm_crtc *crtc;
05394f39
CW
652 struct drm_i915_gem_object *old_fb_obj;
653 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd 654 struct drm_pending_vblank_event *event;
e7d841ca
CW
655 atomic_t pending;
656#define INTEL_FLIP_INACTIVE 0
657#define INTEL_FLIP_PENDING 1
658#define INTEL_FLIP_COMPLETE 2
75f7f3ec
VS
659 u32 flip_count;
660 u32 gtt_offset;
4e5359cd
SF
661 bool enable_stall_check;
662};
663
d9e55608 664struct intel_set_config {
1aa4b628
DV
665 struct drm_encoder **save_connector_encoders;
666 struct drm_crtc **save_encoder_crtcs;
7668851f 667 bool *save_crtc_enabled;
5e2b584e
DV
668
669 bool fb_changed;
670 bool mode_changed;
d9e55608
DV
671};
672
5f1aae65
PZ
673struct intel_load_detect_pipe {
674 struct drm_framebuffer *release_fb;
675 bool load_detect_temp;
676 int dpms_mode;
677};
79e53945 678
5f1aae65
PZ
679static inline struct intel_encoder *
680intel_attached_encoder(struct drm_connector *connector)
df0e9248
CW
681{
682 return to_intel_connector(connector)->encoder;
683}
684
da63a9f2
PZ
685static inline struct intel_digital_port *
686enc_to_dig_port(struct drm_encoder *encoder)
687{
688 return container_of(encoder, struct intel_digital_port, base.base);
9ff8c9ba
ID
689}
690
0e32b39c
DA
691static inline struct intel_dp_mst_encoder *
692enc_to_mst(struct drm_encoder *encoder)
693{
694 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
695}
696
9ff8c9ba
ID
697static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
698{
699 return &enc_to_dig_port(encoder)->dp;
da63a9f2
PZ
700}
701
702static inline struct intel_digital_port *
703dp_to_dig_port(struct intel_dp *intel_dp)
704{
705 return container_of(intel_dp, struct intel_digital_port, dp);
706}
707
708static inline struct intel_digital_port *
709hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
710{
711 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
7739c33b
PZ
712}
713
5f1aae65
PZ
714
715/* i915_irq.c */
87440425
PZ
716bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
717 enum pipe pipe, bool enable);
718bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
719 enum transcoder pch_transcoder,
720 bool enable);
480c8033
DV
721void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
722void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
723void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
724void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
725void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
726void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
730488b2
PZ
727void intel_runtime_pm_disable_interrupts(struct drm_device *dev);
728void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
9df7575f
JB
729static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
730{
731 /*
732 * We only use drm_irq_uninstall() at unload and VT switch, so
733 * this is the only thing we need to check.
734 */
735 return !dev_priv->pm._irqs_disabled;
736}
737
a225f079 738int intel_get_crtc_scanline(struct intel_crtc *crtc);
56b80e1f 739void i9xx_check_fifo_underruns(struct drm_device *dev);
d49bdb0e 740void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
5f1aae65 741
5f1aae65 742/* intel_crt.c */
87440425 743void intel_crt_init(struct drm_device *dev);
5f1aae65
PZ
744
745
746/* intel_ddi.c */
87440425
PZ
747void intel_prepare_ddi(struct drm_device *dev);
748void hsw_fdi_link_train(struct drm_crtc *crtc);
749void intel_ddi_init(struct drm_device *dev, enum port port);
750enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
751bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
752int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
753void intel_ddi_pll_init(struct drm_device *dev);
754void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
755void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
756 enum transcoder cpu_transcoder);
757void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
758void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
566b734a 759bool intel_ddi_pll_select(struct intel_crtc *crtc);
87440425
PZ
760void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
761void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
762bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
763void intel_ddi_fdi_disable(struct drm_crtc *crtc);
764void intel_ddi_get_config(struct intel_encoder *encoder,
765 struct intel_crtc_config *pipe_config);
5f1aae65 766
44905a27 767void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
0e32b39c
DA
768void intel_ddi_clock_get(struct intel_encoder *encoder,
769 struct intel_crtc_config *pipe_config);
770void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
5f1aae65
PZ
771
772/* intel_display.c */
ba0fbca4 773const char *intel_output_name(int output);
5dce5b93 774bool intel_has_pending_fb_unpin(struct drm_device *dev);
5f1aae65 775int intel_pch_rawclk(struct drm_device *dev);
87440425 776void intel_mark_busy(struct drm_device *dev);
f99d7069
DV
777void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
778 struct intel_engine_cs *ring);
779void intel_frontbuffer_flip_prepare(struct drm_device *dev,
780 unsigned frontbuffer_bits);
781void intel_frontbuffer_flip_complete(struct drm_device *dev,
782 unsigned frontbuffer_bits);
783void intel_frontbuffer_flush(struct drm_device *dev,
784 unsigned frontbuffer_bits);
785/**
786 * intel_frontbuffer_flip - prepare frontbuffer flip
787 * @dev: DRM device
788 * @frontbuffer_bits: frontbuffer plane tracking bits
789 *
790 * This function gets called after scheduling a flip on @obj. This is for
791 * synchronous plane updates which will happen on the next vblank and which will
792 * not get delayed by pending gpu rendering.
793 *
794 * Can be called without any locks held.
795 */
796static inline
797void intel_frontbuffer_flip(struct drm_device *dev,
798 unsigned frontbuffer_bits)
799{
800 intel_frontbuffer_flush(dev, frontbuffer_bits);
801}
802
803void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
87440425
PZ
804void intel_mark_idle(struct drm_device *dev);
805void intel_crtc_restore_mode(struct drm_crtc *crtc);
b04c5bd6 806void intel_crtc_control(struct drm_crtc *crtc, bool enable);
87440425
PZ
807void intel_crtc_update_dpms(struct drm_crtc *crtc);
808void intel_encoder_destroy(struct drm_encoder *encoder);
809void intel_connector_dpms(struct drm_connector *, int mode);
810bool intel_connector_get_hw_state(struct intel_connector *connector);
811void intel_modeset_check_state(struct drm_device *dev);
b0ea7d37
DL
812bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
813 struct intel_digital_port *port);
87440425
PZ
814void intel_connector_attach_encoder(struct intel_connector *connector,
815 struct intel_encoder *encoder);
816struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
817struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
818 struct drm_crtc *crtc);
752aa88a 819enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
08d7b3d1
CW
820int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
821 struct drm_file *file_priv);
87440425
PZ
822enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
823 enum pipe pipe);
824void intel_wait_for_vblank(struct drm_device *dev, int pipe);
825void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
826int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
e4607fcf
CML
827void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
828 struct intel_digital_port *dport);
87440425
PZ
829bool intel_get_load_detect_pipe(struct drm_connector *connector,
830 struct drm_display_mode *mode,
51fd371b
RC
831 struct intel_load_detect_pipe *old,
832 struct drm_modeset_acquire_ctx *ctx);
87440425 833void intel_release_load_detect_pipe(struct drm_connector *connector,
51fd371b
RC
834 struct intel_load_detect_pipe *old,
835 struct drm_modeset_acquire_ctx *ctx);
87440425
PZ
836int intel_pin_and_fence_fb_obj(struct drm_device *dev,
837 struct drm_i915_gem_object *obj,
a4872ba6 838 struct intel_engine_cs *pipelined);
87440425 839void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
a8bb6818
DV
840struct drm_framebuffer *
841__intel_framebuffer_create(struct drm_device *dev,
87440425
PZ
842 struct drm_mode_fb_cmd2 *mode_cmd,
843 struct drm_i915_gem_object *obj);
87440425
PZ
844void intel_prepare_page_flip(struct drm_device *dev, int plane);
845void intel_finish_page_flip(struct drm_device *dev, int pipe);
846void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
716c2e55
DV
847
848/* shared dpll functions */
5f1aae65 849struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
55607e8a
DV
850void assert_shared_dpll(struct drm_i915_private *dev_priv,
851 struct intel_shared_dpll *pll,
852 bool state);
853#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
854#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
716c2e55
DV
855struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
856void intel_put_shared_dpll(struct intel_crtc *crtc);
857
858/* modesetting asserts */
55607e8a
DV
859void assert_pll(struct drm_i915_private *dev_priv,
860 enum pipe pipe, bool state);
861#define assert_pll_enabled(d, p) assert_pll(d, p, true)
862#define assert_pll_disabled(d, p) assert_pll(d, p, false)
863void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
864 enum pipe pipe, bool state);
865#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
866#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
87440425 867void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
b840d907
JB
868#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
869#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
87440425
PZ
870void intel_write_eld(struct drm_encoder *encoder,
871 struct drm_display_mode *mode);
872unsigned long intel_gen4_compute_page_offset(int *x, int *y,
873 unsigned int tiling_mode,
874 unsigned int bpp,
875 unsigned int pitch);
876void intel_display_handle_reset(struct drm_device *dev);
a14cb6fc
PZ
877void hsw_enable_pc8(struct drm_i915_private *dev_priv);
878void hsw_disable_pc8(struct drm_i915_private *dev_priv);
87440425
PZ
879void intel_dp_get_m_n(struct intel_crtc *crtc,
880 struct intel_crtc_config *pipe_config);
f769cd24 881void intel_dp_set_m_n(struct intel_crtc *crtc);
87440425
PZ
882int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
883void
5f1aae65
PZ
884ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
885 int dotclock);
87440425 886bool intel_crtc_active(struct drm_crtc *crtc);
20bc8673
VS
887void hsw_enable_ips(struct intel_crtc *crtc);
888void hsw_disable_ips(struct intel_crtc *crtc);
da7e29bd 889void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
319be8ae
ID
890enum intel_display_power_domain
891intel_display_port_power_domain(struct intel_encoder *intel_encoder);
f6a83288
DV
892void intel_mode_from_pipe_config(struct drm_display_mode *mode,
893 struct intel_crtc_config *pipe_config);
46f297fb 894int intel_format_to_fourcc(int format);
46a55d30 895void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
e2fcdaa9 896void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
46a55d30 897
5f1aae65 898/* intel_dp.c */
87440425
PZ
899void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
900bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
901 struct intel_connector *intel_connector);
87440425
PZ
902void intel_dp_start_link_train(struct intel_dp *intel_dp);
903void intel_dp_complete_link_train(struct intel_dp *intel_dp);
904void intel_dp_stop_link_train(struct intel_dp *intel_dp);
905void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
906void intel_dp_encoder_destroy(struct drm_encoder *encoder);
907void intel_dp_check_link_status(struct intel_dp *intel_dp);
d2e216d0 908int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
87440425
PZ
909bool intel_dp_compute_config(struct intel_encoder *encoder,
910 struct intel_crtc_config *pipe_config);
5d8a7752 911bool intel_dp_is_edp(struct drm_device *dev, enum port port);
13cf5504
DA
912bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
913 bool long_hpd);
4be73780
DV
914void intel_edp_backlight_on(struct intel_dp *intel_dp);
915void intel_edp_backlight_off(struct intel_dp *intel_dp);
24f3e092 916void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
aba86890 917void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder);
4be73780
DV
918void intel_edp_panel_on(struct intel_dp *intel_dp);
919void intel_edp_panel_off(struct intel_dp *intel_dp);
87440425
PZ
920void intel_edp_psr_enable(struct intel_dp *intel_dp);
921void intel_edp_psr_disable(struct intel_dp *intel_dp);
439d7ac0 922void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
9ca15301
DV
923void intel_edp_psr_invalidate(struct drm_device *dev,
924 unsigned frontbuffer_bits);
925void intel_edp_psr_flush(struct drm_device *dev,
926 unsigned frontbuffer_bits);
7c8f8a70
RV
927void intel_edp_psr_init(struct drm_device *dev);
928
0e32b39c
DA
929int intel_dp_handle_hpd_irq(struct intel_digital_port *digport, bool long_hpd);
930void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
931void intel_dp_mst_suspend(struct drm_device *dev);
932void intel_dp_mst_resume(struct drm_device *dev);
933int intel_dp_max_link_bw(struct intel_dp *intel_dp);
934void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
935/* intel_dp_mst.c */
936int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
937void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
5f1aae65 938/* intel_dsi.c */
4328633d 939void intel_dsi_init(struct drm_device *dev);
5f1aae65
PZ
940
941
942/* intel_dvo.c */
87440425 943void intel_dvo_init(struct drm_device *dev);
5f1aae65
PZ
944
945
0632fef6 946/* legacy fbdev emulation in intel_fbdev.c */
4520f53a
DV
947#ifdef CONFIG_DRM_I915_FBDEV
948extern int intel_fbdev_init(struct drm_device *dev);
949extern void intel_fbdev_initial_config(struct drm_device *dev);
950extern void intel_fbdev_fini(struct drm_device *dev);
951extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
0632fef6
DV
952extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
953extern void intel_fbdev_restore_mode(struct drm_device *dev);
4520f53a
DV
954#else
955static inline int intel_fbdev_init(struct drm_device *dev)
956{
957 return 0;
958}
5f1aae65 959
4520f53a
DV
960static inline void intel_fbdev_initial_config(struct drm_device *dev)
961{
962}
963
964static inline void intel_fbdev_fini(struct drm_device *dev)
965{
966}
967
968static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
969{
970}
971
0632fef6 972static inline void intel_fbdev_restore_mode(struct drm_device *dev)
4520f53a
DV
973{
974}
975#endif
5f1aae65
PZ
976
977/* intel_hdmi.c */
87440425
PZ
978void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
979void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
980 struct intel_connector *intel_connector);
981struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
982bool intel_hdmi_compute_config(struct intel_encoder *encoder,
983 struct intel_crtc_config *pipe_config);
5f1aae65
PZ
984
985
986/* intel_lvds.c */
87440425
PZ
987void intel_lvds_init(struct drm_device *dev);
988bool intel_is_dual_link_lvds(struct drm_device *dev);
5f1aae65
PZ
989
990
991/* intel_modes.c */
992int intel_connector_update_modes(struct drm_connector *connector,
87440425 993 struct edid *edid);
5f1aae65 994int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
87440425
PZ
995void intel_attach_force_audio_property(struct drm_connector *connector);
996void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
5f1aae65
PZ
997
998
999/* intel_overlay.c */
87440425
PZ
1000void intel_setup_overlay(struct drm_device *dev);
1001void intel_cleanup_overlay(struct drm_device *dev);
1002int intel_overlay_switch_off(struct intel_overlay *overlay);
1003int intel_overlay_put_image(struct drm_device *dev, void *data,
1004 struct drm_file *file_priv);
1005int intel_overlay_attrs(struct drm_device *dev, void *data,
1006 struct drm_file *file_priv);
5f1aae65
PZ
1007
1008
1009/* intel_panel.c */
87440425 1010int intel_panel_init(struct intel_panel *panel,
4b6ed685
VK
1011 struct drm_display_mode *fixed_mode,
1012 struct drm_display_mode *downclock_mode);
87440425
PZ
1013void intel_panel_fini(struct intel_panel *panel);
1014void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1015 struct drm_display_mode *adjusted_mode);
1016void intel_pch_panel_fitting(struct intel_crtc *crtc,
1017 struct intel_crtc_config *pipe_config,
1018 int fitting_mode);
1019void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1020 struct intel_crtc_config *pipe_config,
1021 int fitting_mode);
6dda730e
JN
1022void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1023 u32 level, u32 max);
87440425 1024int intel_panel_setup_backlight(struct drm_connector *connector);
752aa88a
JB
1025void intel_panel_enable_backlight(struct intel_connector *connector);
1026void intel_panel_disable_backlight(struct intel_connector *connector);
db31af1d 1027void intel_panel_destroy_backlight(struct drm_connector *connector);
7bd688cd 1028void intel_panel_init_backlight_funcs(struct drm_device *dev);
87440425 1029enum drm_connector_status intel_panel_detect(struct drm_device *dev);
ec9ed197
VK
1030extern struct drm_display_mode *intel_find_panel_downclock(
1031 struct drm_device *dev,
1032 struct drm_display_mode *fixed_mode,
1033 struct drm_connector *connector);
5f1aae65
PZ
1034
1035/* intel_pm.c */
87440425
PZ
1036void intel_init_clock_gating(struct drm_device *dev);
1037void intel_suspend_hw(struct drm_device *dev);
546c81fd 1038int ilk_wm_max_level(const struct drm_device *dev);
87440425
PZ
1039void intel_update_watermarks(struct drm_crtc *crtc);
1040void intel_update_sprite_watermarks(struct drm_plane *plane,
1041 struct drm_crtc *crtc,
ed57cb8a
DL
1042 uint32_t sprite_width,
1043 uint32_t sprite_height,
1044 int pixel_size,
87440425
PZ
1045 bool enabled, bool scaled);
1046void intel_init_pm(struct drm_device *dev);
f742a552 1047void intel_pm_setup(struct drm_device *dev);
87440425
PZ
1048bool intel_fbc_enabled(struct drm_device *dev);
1049void intel_update_fbc(struct drm_device *dev);
1050void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1051void intel_gpu_ips_teardown(void);
da7e29bd
ID
1052int intel_power_domains_init(struct drm_i915_private *);
1053void intel_power_domains_remove(struct drm_i915_private *);
1054bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
87440425 1055 enum intel_display_power_domain domain);
bfafe93a
ID
1056bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
1057 enum intel_display_power_domain domain);
da7e29bd 1058void intel_display_power_get(struct drm_i915_private *dev_priv,
87440425 1059 enum intel_display_power_domain domain);
da7e29bd 1060void intel_display_power_put(struct drm_i915_private *dev_priv,
87440425 1061 enum intel_display_power_domain domain);
da7e29bd 1062void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
ae48434c
ID
1063void intel_init_gt_powersave(struct drm_device *dev);
1064void intel_cleanup_gt_powersave(struct drm_device *dev);
87440425
PZ
1065void intel_enable_gt_powersave(struct drm_device *dev);
1066void intel_disable_gt_powersave(struct drm_device *dev);
156c7ca0 1067void intel_suspend_gt_powersave(struct drm_device *dev);
c6df39b5 1068void intel_reset_gt_powersave(struct drm_device *dev);
87440425 1069void ironlake_teardown_rc6(struct drm_device *dev);
c67a470b 1070void gen6_update_ring_freq(struct drm_device *dev);
076e29f2
DV
1071void gen6_rps_idle(struct drm_i915_private *dev_priv);
1072void gen6_rps_boost(struct drm_i915_private *dev_priv);
87440425
PZ
1073void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1074void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
8a187455 1075void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
c6df39b5 1076void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
8a187455
PZ
1077void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1078void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
1079void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
243e6a44 1080void ilk_wm_get_hw_state(struct drm_device *dev);
d2011dc8 1081
72662e10 1082
5f1aae65 1083/* intel_sdvo.c */
87440425 1084bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
96a02917 1085
2b28bb1b 1086
5f1aae65 1087/* intel_sprite.c */
87440425 1088int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1dba99f4 1089void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
87440425 1090 enum plane plane);
e57465f3 1091int intel_plane_restore(struct drm_plane *plane);
87440425
PZ
1092void intel_plane_disable(struct drm_plane *plane);
1093int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1094 struct drm_file *file_priv);
1095int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1096 struct drm_file *file_priv);
5f1aae65
PZ
1097
1098
1099/* intel_tv.c */
87440425 1100void intel_tv_init(struct drm_device *dev);
20ddf665 1101
79e53945 1102#endif /* __INTEL_DRV_H__ */