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79e53945
JB
1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
178f736a 29#include <linux/hdmi.h>
760285e7 30#include <drm/i915_drm.h>
80824003 31#include "i915_drv.h"
760285e7
DH
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_fb_helper.h>
612a9aab 35#include <drm/drm_dp_helper.h>
913d8d11 36
1d5bfac9
DV
37/**
38 * _wait_for - magic (register) wait macro
39 *
40 * Does the right thing for modeset paths when run under kdgb or similar atomic
41 * contexts. Note that it's important that we check the condition again after
42 * having timed out, since the timeout could be due to preemption or similar and
43 * we've never had a chance to check the condition before the timeout.
44 */
481b6af3 45#define _wait_for(COND, MS, W) ({ \
1d5bfac9 46 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
913d8d11 47 int ret__ = 0; \
0206e353 48 while (!(COND)) { \
913d8d11 49 if (time_after(jiffies, timeout__)) { \
1d5bfac9
DV
50 if (!(COND)) \
51 ret__ = -ETIMEDOUT; \
913d8d11
CW
52 break; \
53 } \
0cc2764c
BW
54 if (W && drm_can_sleep()) { \
55 msleep(W); \
56 } else { \
57 cpu_relax(); \
58 } \
913d8d11
CW
59 } \
60 ret__; \
61})
62
481b6af3
CW
63#define wait_for(COND, MS) _wait_for(COND, MS, 1)
64#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
6effa33b
DV
65#define wait_for_atomic_us(COND, US) _wait_for((COND), \
66 DIV_ROUND_UP((US), 1000), 0)
481b6af3 67
49938ac4
JN
68#define KHz(x) (1000 * (x))
69#define MHz(x) KHz(1000 * (x))
021357ac 70
79e53945
JB
71/*
72 * Display related stuff
73 */
74
75/* store information about an Ixxx DVO */
76/* The i830->i865 use multiple DVOs with multiple i2cs */
77/* the i915, i945 have a single sDVO i2c bus - which is different */
78#define MAX_OUTPUTS 6
79/* maximum connectors per crtcs in the mode set */
79e53945
JB
80
81#define INTEL_I2C_BUS_DVO 1
82#define INTEL_I2C_BUS_SDVO 2
83
84/* these are outputs from the chip - integrated only
85 external chips are via DVO or SDVO output */
86#define INTEL_OUTPUT_UNUSED 0
87#define INTEL_OUTPUT_ANALOG 1
88#define INTEL_OUTPUT_DVO 2
89#define INTEL_OUTPUT_SDVO 3
90#define INTEL_OUTPUT_LVDS 4
91#define INTEL_OUTPUT_TVOUT 5
7d57382e 92#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 93#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 94#define INTEL_OUTPUT_EDP 8
72ffa333
JN
95#define INTEL_OUTPUT_DSI 9
96#define INTEL_OUTPUT_UNKNOWN 10
79e53945
JB
97
98#define INTEL_DVO_CHIP_NONE 0
99#define INTEL_DVO_CHIP_LVDS 1
100#define INTEL_DVO_CHIP_TMDS 2
101#define INTEL_DVO_CHIP_TVOUT 4
102
72ffa333
JN
103#define INTEL_DSI_COMMAND_MODE 0
104#define INTEL_DSI_VIDEO_MODE 1
105
79e53945
JB
106struct intel_framebuffer {
107 struct drm_framebuffer base;
05394f39 108 struct drm_i915_gem_object *obj;
79e53945
JB
109};
110
37811fcc
CW
111struct intel_fbdev {
112 struct drm_fb_helper helper;
8bcd4553 113 struct intel_framebuffer *fb;
37811fcc
CW
114 struct list_head fbdev_list;
115 struct drm_display_mode *our_mode;
116};
79e53945 117
21d40d37 118struct intel_encoder {
4ef69c7a 119 struct drm_encoder base;
9a935856
DV
120 /*
121 * The new crtc this encoder will be driven from. Only differs from
122 * base->crtc while a modeset is in progress.
123 */
124 struct intel_crtc *new_crtc;
125
79e53945 126 int type;
66a9278e
DV
127 /*
128 * Intel hw has only one MUX where encoders could be clone, hence a
129 * simple flag is enough to compute the possible_clones mask.
130 */
131 bool cloneable;
5ab432ef 132 bool connectors_active;
21d40d37 133 void (*hot_plug)(struct intel_encoder *);
7ae89233
DV
134 bool (*compute_config)(struct intel_encoder *,
135 struct intel_crtc_config *);
dafd226c 136 void (*pre_pll_enable)(struct intel_encoder *);
bf49ec8c 137 void (*pre_enable)(struct intel_encoder *);
ef9c3aee 138 void (*enable)(struct intel_encoder *);
6cc5f341 139 void (*mode_set)(struct intel_encoder *intel_encoder);
ef9c3aee 140 void (*disable)(struct intel_encoder *);
bf49ec8c 141 void (*post_disable)(struct intel_encoder *);
f0947c37
DV
142 /* Read out the current hw state of this connector, returning true if
143 * the encoder is active. If the encoder is enabled it also set the pipe
144 * it is connected to in the pipe parameter. */
145 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
045ac3b5 146 /* Reconstructs the equivalent mode flags for the current hardware
fdafa9e2 147 * state. This must be called _after_ display->get_pipe_config has
63000ef6
XZ
148 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
149 * be set correctly before calling this function. */
045ac3b5
JB
150 void (*get_config)(struct intel_encoder *,
151 struct intel_crtc_config *pipe_config);
f8aed700 152 int crtc_mask;
1d843f9d 153 enum hpd_pin hpd_pin;
79e53945
JB
154};
155
1d508706 156struct intel_panel {
dd06f90e 157 struct drm_display_mode *fixed_mode;
ec9ed197 158 struct drm_display_mode *downclock_mode;
4d891523 159 int fitting_mode;
58c68779
JN
160
161 /* backlight */
162 struct {
c91c9f32 163 bool present;
58c68779 164 u32 level;
7bd688cd 165 u32 max;
58c68779 166 bool enabled;
636baebf
JN
167 bool combination_mode; /* gen 2/4 only */
168 bool active_low_pwm;
58c68779
JN
169 struct backlight_device *device;
170 } backlight;
1d508706
JN
171};
172
5daa55eb
ZW
173struct intel_connector {
174 struct drm_connector base;
9a935856
DV
175 /*
176 * The fixed encoder this connector is connected to.
177 */
df0e9248 178 struct intel_encoder *encoder;
9a935856
DV
179
180 /*
181 * The new encoder this connector will be driven. Only differs from
182 * encoder while a modeset is in progress.
183 */
184 struct intel_encoder *new_encoder;
185
f0947c37
DV
186 /* Reads out the current hw, returning true if the connector is enabled
187 * and active (i.e. dpms ON state). */
188 bool (*get_hw_state)(struct intel_connector *);
1d508706 189
4932e2c3
ID
190 /*
191 * Removes all interfaces through which the connector is accessible
192 * - like sysfs, debugfs entries -, so that no new operations can be
193 * started on the connector. Also makes sure all currently pending
194 * operations finish before returing.
195 */
196 void (*unregister)(struct intel_connector *);
197
1d508706
JN
198 /* Panel info for eDP and LVDS */
199 struct intel_panel panel;
9cd300e0
JN
200
201 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
202 struct edid *edid;
821450c6
EE
203
204 /* since POLL and HPD connectors may use the same HPD line keep the native
205 state of connector->polled in case hotplug storm detection changes it */
206 u8 polled;
5daa55eb
ZW
207};
208
80ad9206
VS
209typedef struct dpll {
210 /* given values */
211 int n;
212 int m1, m2;
213 int p1, p2;
214 /* derived values */
215 int dot;
216 int vco;
217 int m;
218 int p;
219} intel_clock_t;
220
b8cecdf5 221struct intel_crtc_config {
bb760063
DV
222 /**
223 * quirks - bitfield with hw state readout quirks
224 *
225 * For various reasons the hw state readout code might not be able to
226 * completely faithfully read out the current state. These cases are
227 * tracked with quirk flags so that fastboot and state checker can act
228 * accordingly.
229 */
230#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
231 unsigned long quirks;
232
5113bc9b
VS
233 /* User requested mode, only valid as a starting point to
234 * compute adjusted_mode, except in the case of (S)DVO where
235 * it's also for the output timings of the (S)DVO chip.
236 * adjusted_mode will then correspond to the S(DVO) chip's
237 * preferred input timings. */
b8cecdf5 238 struct drm_display_mode requested_mode;
3c52f4eb 239 /* Actual pipe timings ie. what we program into the pipe timing
241bfc38 240 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
b8cecdf5 241 struct drm_display_mode adjusted_mode;
37327abd
VS
242
243 /* Pipe source size (ie. panel fitter input size)
244 * All planes will be positioned inside this space,
245 * and get clipped at the edges. */
246 int pipe_src_w, pipe_src_h;
247
5bfe2ac0
DV
248 /* Whether to set up the PCH/FDI. Note that we never allow sharing
249 * between pch encoders and cpu encoders. */
250 bool has_pch_encoder;
50f3b016 251
3b117c8f
DV
252 /* CPU Transcoder for the pipe. Currently this can only differ from the
253 * pipe on Haswell (where we have a special eDP transcoder). */
254 enum transcoder cpu_transcoder;
255
50f3b016
DV
256 /*
257 * Use reduced/limited/broadcast rbg range, compressing from the full
258 * range fed into the crtcs.
259 */
260 bool limited_color_range;
261
03afc4a2
DV
262 /* DP has a bunch of special case unfortunately, so mark the pipe
263 * accordingly. */
264 bool has_dp_encoder;
d8b32247
DV
265
266 /*
267 * Enable dithering, used when the selected pipe bpp doesn't match the
268 * plane bpp.
269 */
965e0c48 270 bool dither;
f47709a9
DV
271
272 /* Controls for the clock computation, to override various stages. */
273 bool clock_set;
274
09ede541
DV
275 /* SDVO TV has a bunch of special case. To make multifunction encoders
276 * work correctly, we need to track this at runtime.*/
277 bool sdvo_tv_clock;
278
e29c22c0
DV
279 /*
280 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
281 * required. This is set in the 2nd loop of calling encoder's
282 * ->compute_config if the first pick doesn't work out.
283 */
284 bool bw_constrained;
285
f47709a9
DV
286 /* Settings for the intel dpll used on pretty much everything but
287 * haswell. */
80ad9206 288 struct dpll dpll;
f47709a9 289
a43f6e0f
DV
290 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
291 enum intel_dpll_id shared_dpll;
292
66e985c0
DV
293 /* Actual register state of the dpll, for shared dpll cross-checking. */
294 struct intel_dpll_hw_state dpll_hw_state;
295
965e0c48 296 int pipe_bpp;
6cf86a5e 297 struct intel_link_m_n dp_m_n;
ff9a6750
DV
298
299 /*
300 * Frequence the dpll for the port should run at. Differs from the
3c52f4eb
VS
301 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
302 * already multiplied by pixel_multiplier.
df92b1e6 303 */
ff9a6750
DV
304 int port_clock;
305
6cc5f341
DV
306 /* Used by SDVO (and if we ever fix it, HDMI). */
307 unsigned pixel_multiplier;
2dd24552
JB
308
309 /* Panel fitter controls for gen2-gen4 + VLV */
b074cec8
JB
310 struct {
311 u32 control;
312 u32 pgm_ratios;
68fc8742 313 u32 lvds_border_bits;
b074cec8
JB
314 } gmch_pfit;
315
316 /* Panel fitter placement and size for Ironlake+ */
317 struct {
318 u32 pos;
319 u32 size;
fd4daa9c 320 bool enabled;
b074cec8 321 } pch_pfit;
33d29b14 322
ca3a0ff8 323 /* FDI configuration, only valid if has_pch_encoder is set. */
33d29b14 324 int fdi_lanes;
ca3a0ff8 325 struct intel_link_m_n fdi_m_n;
42db64ef
PZ
326
327 bool ips_enabled;
cf532bb2
VS
328
329 bool double_wide;
b8cecdf5
DV
330};
331
0b2ae6d7
VS
332struct intel_pipe_wm {
333 struct intel_wm_level wm[5];
334 uint32_t linetime;
335 bool fbc_wm_enabled;
336};
337
79e53945
JB
338struct intel_crtc {
339 struct drm_crtc base;
80824003
JB
340 enum pipe pipe;
341 enum plane plane;
79e53945 342 u8 lut_r[256], lut_g[256], lut_b[256];
08a48469
DV
343 /*
344 * Whether the crtc and the connected output pipeline is active. Implies
345 * that crtc->enabled is set, i.e. the current mode configuration has
346 * some outputs connected to this crtc.
08a48469
DV
347 */
348 bool active;
6efdf354 349 unsigned long enabled_power_domains;
7b9f35a6 350 bool eld_vld;
4c445e0e 351 bool primary_enabled; /* is the primary plane (partially) visible? */
652c393a 352 bool lowfreq_avail;
02e792fb 353 struct intel_overlay *overlay;
6b95a207 354 struct intel_unpin_work *unpin_work;
cda4b7d3 355
b4a98e57
CW
356 atomic_t unpin_work_count;
357
e506a0c6
DV
358 /* Display surface base address adjustement for pageflips. Note that on
359 * gen4+ this only adjusts up to a tile, offsets within a tile are
360 * handled in the hw itself (with the TILEOFF register). */
361 unsigned long dspaddr_offset;
362
05394f39 363 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW
364 uint32_t cursor_addr;
365 int16_t cursor_x, cursor_y;
366 int16_t cursor_width, cursor_height;
6b383a7f 367 bool cursor_visible;
4b645f14 368
b8cecdf5 369 struct intel_crtc_config config;
50741abc 370 struct intel_crtc_config *new_config;
7668851f 371 bool new_enabled;
b8cecdf5 372
6441ab5f 373 uint32_t ddi_pll_sel;
10d83730
VS
374
375 /* reset counter value when the last flip was submitted */
376 unsigned int reset_counter;
8664281b
PZ
377
378 /* Access to these should be protected by dev_priv->irq_lock. */
379 bool cpu_fifo_underrun_disabled;
380 bool pch_fifo_underrun_disabled;
0b2ae6d7
VS
381
382 /* per-pipe watermark state */
383 struct {
384 /* watermarks currently being used */
385 struct intel_pipe_wm active;
386 } wm;
79e53945
JB
387};
388
c35426d2
VS
389struct intel_plane_wm_parameters {
390 uint32_t horiz_pixels;
391 uint8_t bytes_per_pixel;
392 bool enabled;
393 bool scaled;
394};
395
b840d907
JB
396struct intel_plane {
397 struct drm_plane base;
7f1f3851 398 int plane;
b840d907
JB
399 enum pipe pipe;
400 struct drm_i915_gem_object *obj;
2d354c34 401 bool can_scale;
b840d907
JB
402 int max_downscale;
403 u32 lut_r[1024], lut_g[1024], lut_b[1024];
5e1bac2f
JB
404 int crtc_x, crtc_y;
405 unsigned int crtc_w, crtc_h;
406 uint32_t src_x, src_y;
407 uint32_t src_w, src_h;
526682e9
PZ
408
409 /* Since we need to change the watermarks before/after
410 * enabling/disabling the planes, we need to store the parameters here
411 * as the other pieces of the struct may not reflect the values we want
412 * for the watermark calculations. Currently only Haswell uses this.
413 */
c35426d2 414 struct intel_plane_wm_parameters wm;
526682e9 415
b840d907 416 void (*update_plane)(struct drm_plane *plane,
b39d53f6 417 struct drm_crtc *crtc,
b840d907
JB
418 struct drm_framebuffer *fb,
419 struct drm_i915_gem_object *obj,
420 int crtc_x, int crtc_y,
421 unsigned int crtc_w, unsigned int crtc_h,
422 uint32_t x, uint32_t y,
423 uint32_t src_w, uint32_t src_h);
b39d53f6
VS
424 void (*disable_plane)(struct drm_plane *plane,
425 struct drm_crtc *crtc);
8ea30864
JB
426 int (*update_colorkey)(struct drm_plane *plane,
427 struct drm_intel_sprite_colorkey *key);
428 void (*get_colorkey)(struct drm_plane *plane,
429 struct drm_intel_sprite_colorkey *key);
b840d907
JB
430};
431
b445e3b0
ED
432struct intel_watermark_params {
433 unsigned long fifo_size;
434 unsigned long max_wm;
435 unsigned long default_wm;
436 unsigned long guard_size;
437 unsigned long cacheline_size;
438};
439
440struct cxsr_latency {
441 int is_desktop;
442 int is_ddr3;
443 unsigned long fsb_freq;
444 unsigned long mem_freq;
445 unsigned long display_sr;
446 unsigned long display_hpll_disable;
447 unsigned long cursor_sr;
448 unsigned long cursor_hpll_disable;
449};
450
79e53945 451#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 452#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 453#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 454#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 455#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 456
f5bbfca3 457struct intel_hdmi {
b242b7f7 458 u32 hdmi_reg;
f5bbfca3 459 int ddc_bus;
f5bbfca3 460 uint32_t color_range;
55bc60db 461 bool color_range_auto;
f5bbfca3
ED
462 bool has_hdmi_sink;
463 bool has_audio;
464 enum hdmi_force_audio force_audio;
abedc077 465 bool rgb_quant_range_selectable;
f5bbfca3 466 void (*write_infoframe)(struct drm_encoder *encoder,
178f736a 467 enum hdmi_infoframe_type type,
fff63867 468 const void *frame, ssize_t len);
687f4d06
PZ
469 void (*set_infoframes)(struct drm_encoder *encoder,
470 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED
471};
472
b091cd92 473#define DP_MAX_DOWNSTREAM_PORTS 0x10
54d63ca6
SK
474
475struct intel_dp {
54d63ca6 476 uint32_t output_reg;
9ed35ab1 477 uint32_t aux_ch_ctl_reg;
54d63ca6 478 uint32_t DP;
54d63ca6
SK
479 bool has_audio;
480 enum hdmi_force_audio force_audio;
481 uint32_t color_range;
55bc60db 482 bool color_range_auto;
54d63ca6
SK
483 uint8_t link_bw;
484 uint8_t lane_count;
485 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
2293bb5c 486 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
b091cd92 487 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
54d63ca6
SK
488 struct i2c_adapter adapter;
489 struct i2c_algo_dp_aux_data algo;
54d63ca6
SK
490 uint8_t train_set[4];
491 int panel_power_up_delay;
492 int panel_power_down_delay;
493 int panel_power_cycle_delay;
494 int backlight_on_delay;
495 int backlight_off_delay;
54d63ca6
SK
496 struct delayed_work panel_vdd_work;
497 bool want_panel_vdd;
dce56b3c
PZ
498 unsigned long last_power_cycle;
499 unsigned long last_power_on;
500 unsigned long last_backlight_off;
2b28bb1b 501 bool psr_setup_done;
06ea66b6 502 bool use_tps3;
dd06f90e 503 struct intel_connector *attached_connector;
ec5b01dd
DL
504
505 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
153b1100
DL
506 /*
507 * This function returns the value we have to program the AUX_CTL
508 * register with to kick off an AUX transaction.
509 */
510 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
511 bool has_aux_irq,
512 int send_bytes,
513 uint32_t aux_clock_divider);
54d63ca6
SK
514};
515
da63a9f2
PZ
516struct intel_digital_port {
517 struct intel_encoder base;
174edf1f 518 enum port port;
bcf53de4 519 u32 saved_port_bits;
da63a9f2
PZ
520 struct intel_dp dp;
521 struct intel_hdmi hdmi;
522};
523
89b667f8
JB
524static inline int
525vlv_dport_to_channel(struct intel_digital_port *dport)
526{
527 switch (dport->port) {
528 case PORT_B:
e4607fcf 529 return DPIO_CH0;
89b667f8 530 case PORT_C:
e4607fcf 531 return DPIO_CH1;
89b667f8
JB
532 default:
533 BUG();
534 }
535}
536
f875c15a
CW
537static inline struct drm_crtc *
538intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
539{
540 struct drm_i915_private *dev_priv = dev->dev_private;
541 return dev_priv->pipe_to_crtc_mapping[pipe];
542}
543
417ae147
CW
544static inline struct drm_crtc *
545intel_get_crtc_for_plane(struct drm_device *dev, int plane)
546{
547 struct drm_i915_private *dev_priv = dev->dev_private;
548 return dev_priv->plane_to_crtc_mapping[plane];
549}
550
4e5359cd
SF
551struct intel_unpin_work {
552 struct work_struct work;
b4a98e57 553 struct drm_crtc *crtc;
05394f39
CW
554 struct drm_i915_gem_object *old_fb_obj;
555 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd 556 struct drm_pending_vblank_event *event;
e7d841ca
CW
557 atomic_t pending;
558#define INTEL_FLIP_INACTIVE 0
559#define INTEL_FLIP_PENDING 1
560#define INTEL_FLIP_COMPLETE 2
4e5359cd
SF
561 bool enable_stall_check;
562};
563
d9e55608 564struct intel_set_config {
1aa4b628
DV
565 struct drm_encoder **save_connector_encoders;
566 struct drm_crtc **save_encoder_crtcs;
7668851f 567 bool *save_crtc_enabled;
5e2b584e
DV
568
569 bool fb_changed;
570 bool mode_changed;
d9e55608
DV
571};
572
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573struct intel_load_detect_pipe {
574 struct drm_framebuffer *release_fb;
575 bool load_detect_temp;
576 int dpms_mode;
577};
79e53945 578
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579static inline struct intel_encoder *
580intel_attached_encoder(struct drm_connector *connector)
df0e9248
CW
581{
582 return to_intel_connector(connector)->encoder;
583}
584
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PZ
585static inline struct intel_digital_port *
586enc_to_dig_port(struct drm_encoder *encoder)
587{
588 return container_of(encoder, struct intel_digital_port, base.base);
9ff8c9ba
ID
589}
590
591static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
592{
593 return &enc_to_dig_port(encoder)->dp;
da63a9f2
PZ
594}
595
596static inline struct intel_digital_port *
597dp_to_dig_port(struct intel_dp *intel_dp)
598{
599 return container_of(intel_dp, struct intel_digital_port, dp);
600}
601
602static inline struct intel_digital_port *
603hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
604{
605 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
7739c33b
PZ
606}
607
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608
609/* i915_irq.c */
87440425
PZ
610bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
611 enum pipe pipe, bool enable);
77961eb9
ID
612bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
613 enum pipe pipe, bool enable);
87440425
PZ
614bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
615 enum transcoder pch_transcoder,
616 bool enable);
617void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
618void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
619void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
620void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
621void hsw_pc8_disable_interrupts(struct drm_device *dev);
622void hsw_pc8_restore_interrupts(struct drm_device *dev);
5f1aae65
PZ
623
624
625/* intel_crt.c */
87440425 626void intel_crt_init(struct drm_device *dev);
5f1aae65
PZ
627
628
629/* intel_ddi.c */
87440425
PZ
630void intel_prepare_ddi(struct drm_device *dev);
631void hsw_fdi_link_train(struct drm_crtc *crtc);
632void intel_ddi_init(struct drm_device *dev, enum port port);
633enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
634bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
635int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
636void intel_ddi_pll_init(struct drm_device *dev);
637void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
638void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
639 enum transcoder cpu_transcoder);
640void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
641void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
642void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
566b734a
PZ
643bool intel_ddi_pll_select(struct intel_crtc *crtc);
644void intel_ddi_pll_enable(struct intel_crtc *crtc);
87440425
PZ
645void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
646void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
647void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
648bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
649void intel_ddi_fdi_disable(struct drm_crtc *crtc);
650void intel_ddi_get_config(struct intel_encoder *encoder,
651 struct intel_crtc_config *pipe_config);
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PZ
652
653
654/* intel_display.c */
ba0fbca4 655const char *intel_output_name(int output);
5dce5b93 656bool intel_has_pending_fb_unpin(struct drm_device *dev);
5f1aae65 657int intel_pch_rawclk(struct drm_device *dev);
87440425
PZ
658void intel_mark_busy(struct drm_device *dev);
659void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
660 struct intel_ring_buffer *ring);
661void intel_mark_idle(struct drm_device *dev);
662void intel_crtc_restore_mode(struct drm_crtc *crtc);
663void intel_crtc_update_dpms(struct drm_crtc *crtc);
664void intel_encoder_destroy(struct drm_encoder *encoder);
665void intel_connector_dpms(struct drm_connector *, int mode);
666bool intel_connector_get_hw_state(struct intel_connector *connector);
667void intel_modeset_check_state(struct drm_device *dev);
b0ea7d37
DL
668bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
669 struct intel_digital_port *port);
87440425
PZ
670void intel_connector_attach_encoder(struct intel_connector *connector,
671 struct intel_encoder *encoder);
672struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
673struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
674 struct drm_crtc *crtc);
752aa88a 675enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
08d7b3d1
CW
676int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
677 struct drm_file *file_priv);
87440425
PZ
678enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
679 enum pipe pipe);
680void intel_wait_for_vblank(struct drm_device *dev, int pipe);
681void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
682int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
e4607fcf
CML
683void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
684 struct intel_digital_port *dport);
87440425
PZ
685bool intel_get_load_detect_pipe(struct drm_connector *connector,
686 struct drm_display_mode *mode,
687 struct intel_load_detect_pipe *old);
688void intel_release_load_detect_pipe(struct drm_connector *connector,
689 struct intel_load_detect_pipe *old);
690int intel_pin_and_fence_fb_obj(struct drm_device *dev,
691 struct drm_i915_gem_object *obj,
692 struct intel_ring_buffer *pipelined);
693void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
a8bb6818
DV
694struct drm_framebuffer *
695__intel_framebuffer_create(struct drm_device *dev,
87440425
PZ
696 struct drm_mode_fb_cmd2 *mode_cmd,
697 struct drm_i915_gem_object *obj);
87440425
PZ
698void intel_prepare_page_flip(struct drm_device *dev, int plane);
699void intel_finish_page_flip(struct drm_device *dev, int pipe);
700void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
5f1aae65 701struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
55607e8a
DV
702void assert_shared_dpll(struct drm_i915_private *dev_priv,
703 struct intel_shared_dpll *pll,
704 bool state);
705#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
706#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
707void assert_pll(struct drm_i915_private *dev_priv,
708 enum pipe pipe, bool state);
709#define assert_pll_enabled(d, p) assert_pll(d, p, true)
710#define assert_pll_disabled(d, p) assert_pll(d, p, false)
711void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
712 enum pipe pipe, bool state);
713#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
714#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
87440425 715void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
b840d907
JB
716#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
717#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
87440425
PZ
718void intel_write_eld(struct drm_encoder *encoder,
719 struct drm_display_mode *mode);
720unsigned long intel_gen4_compute_page_offset(int *x, int *y,
721 unsigned int tiling_mode,
722 unsigned int bpp,
723 unsigned int pitch);
724void intel_display_handle_reset(struct drm_device *dev);
725void hsw_enable_pc8_work(struct work_struct *__work);
726void hsw_enable_package_c8(struct drm_i915_private *dev_priv);
727void hsw_disable_package_c8(struct drm_i915_private *dev_priv);
728void intel_dp_get_m_n(struct intel_crtc *crtc,
729 struct intel_crtc_config *pipe_config);
730int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
731void
5f1aae65
PZ
732ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
733 int dotclock);
87440425 734bool intel_crtc_active(struct drm_crtc *crtc);
20bc8673
VS
735void hsw_enable_ips(struct intel_crtc *crtc);
736void hsw_disable_ips(struct intel_crtc *crtc);
da7e29bd 737void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
319be8ae
ID
738enum intel_display_power_domain
739intel_display_port_power_domain(struct intel_encoder *intel_encoder);
586f49dc 740int valleyview_get_vco(struct drm_i915_private *dev_priv);
f6a83288
DV
741void intel_mode_from_pipe_config(struct drm_display_mode *mode,
742 struct intel_crtc_config *pipe_config);
8ea30864 743
5f1aae65 744/* intel_dp.c */
87440425
PZ
745void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
746bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
747 struct intel_connector *intel_connector);
87440425
PZ
748void intel_dp_start_link_train(struct intel_dp *intel_dp);
749void intel_dp_complete_link_train(struct intel_dp *intel_dp);
750void intel_dp_stop_link_train(struct intel_dp *intel_dp);
751void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
752void intel_dp_encoder_destroy(struct drm_encoder *encoder);
753void intel_dp_check_link_status(struct intel_dp *intel_dp);
d2e216d0 754int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
87440425
PZ
755bool intel_dp_compute_config(struct intel_encoder *encoder,
756 struct intel_crtc_config *pipe_config);
5d8a7752 757bool intel_dp_is_edp(struct drm_device *dev, enum port port);
4be73780
DV
758void intel_edp_backlight_on(struct intel_dp *intel_dp);
759void intel_edp_backlight_off(struct intel_dp *intel_dp);
760void intel_edp_panel_on(struct intel_dp *intel_dp);
761void intel_edp_panel_off(struct intel_dp *intel_dp);
87440425
PZ
762void intel_edp_psr_enable(struct intel_dp *intel_dp);
763void intel_edp_psr_disable(struct intel_dp *intel_dp);
764void intel_edp_psr_update(struct drm_device *dev);
5f1aae65
PZ
765
766
767/* intel_dsi.c */
87440425 768bool intel_dsi_init(struct drm_device *dev);
5f1aae65
PZ
769
770
771/* intel_dvo.c */
87440425 772void intel_dvo_init(struct drm_device *dev);
5f1aae65
PZ
773
774
0632fef6 775/* legacy fbdev emulation in intel_fbdev.c */
4520f53a
DV
776#ifdef CONFIG_DRM_I915_FBDEV
777extern int intel_fbdev_init(struct drm_device *dev);
778extern void intel_fbdev_initial_config(struct drm_device *dev);
779extern void intel_fbdev_fini(struct drm_device *dev);
780extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
0632fef6
DV
781extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
782extern void intel_fbdev_restore_mode(struct drm_device *dev);
4520f53a
DV
783#else
784static inline int intel_fbdev_init(struct drm_device *dev)
785{
786 return 0;
787}
5f1aae65 788
4520f53a
DV
789static inline void intel_fbdev_initial_config(struct drm_device *dev)
790{
791}
792
793static inline void intel_fbdev_fini(struct drm_device *dev)
794{
795}
796
797static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
798{
799}
800
0632fef6 801static inline void intel_fbdev_restore_mode(struct drm_device *dev)
4520f53a
DV
802{
803}
804#endif
5f1aae65
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805
806/* intel_hdmi.c */
87440425
PZ
807void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
808void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
809 struct intel_connector *intel_connector);
810struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
811bool intel_hdmi_compute_config(struct intel_encoder *encoder,
812 struct intel_crtc_config *pipe_config);
5f1aae65
PZ
813
814
815/* intel_lvds.c */
87440425
PZ
816void intel_lvds_init(struct drm_device *dev);
817bool intel_is_dual_link_lvds(struct drm_device *dev);
5f1aae65
PZ
818
819
820/* intel_modes.c */
821int intel_connector_update_modes(struct drm_connector *connector,
87440425 822 struct edid *edid);
5f1aae65 823int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
87440425
PZ
824void intel_attach_force_audio_property(struct drm_connector *connector);
825void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
5f1aae65
PZ
826
827
828/* intel_overlay.c */
87440425
PZ
829void intel_setup_overlay(struct drm_device *dev);
830void intel_cleanup_overlay(struct drm_device *dev);
831int intel_overlay_switch_off(struct intel_overlay *overlay);
832int intel_overlay_put_image(struct drm_device *dev, void *data,
833 struct drm_file *file_priv);
834int intel_overlay_attrs(struct drm_device *dev, void *data,
835 struct drm_file *file_priv);
5f1aae65
PZ
836
837
838/* intel_panel.c */
87440425 839int intel_panel_init(struct intel_panel *panel,
4b6ed685
VK
840 struct drm_display_mode *fixed_mode,
841 struct drm_display_mode *downclock_mode);
87440425
PZ
842void intel_panel_fini(struct intel_panel *panel);
843void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
844 struct drm_display_mode *adjusted_mode);
845void intel_pch_panel_fitting(struct intel_crtc *crtc,
846 struct intel_crtc_config *pipe_config,
847 int fitting_mode);
848void intel_gmch_panel_fitting(struct intel_crtc *crtc,
849 struct intel_crtc_config *pipe_config,
850 int fitting_mode);
752aa88a
JB
851void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
852 u32 max);
87440425 853int intel_panel_setup_backlight(struct drm_connector *connector);
752aa88a
JB
854void intel_panel_enable_backlight(struct intel_connector *connector);
855void intel_panel_disable_backlight(struct intel_connector *connector);
db31af1d 856void intel_panel_destroy_backlight(struct drm_connector *connector);
7bd688cd 857void intel_panel_init_backlight_funcs(struct drm_device *dev);
87440425 858enum drm_connector_status intel_panel_detect(struct drm_device *dev);
ec9ed197
VK
859extern struct drm_display_mode *intel_find_panel_downclock(
860 struct drm_device *dev,
861 struct drm_display_mode *fixed_mode,
862 struct drm_connector *connector);
5f1aae65
PZ
863
864/* intel_pm.c */
87440425
PZ
865void intel_init_clock_gating(struct drm_device *dev);
866void intel_suspend_hw(struct drm_device *dev);
867void intel_update_watermarks(struct drm_crtc *crtc);
868void intel_update_sprite_watermarks(struct drm_plane *plane,
869 struct drm_crtc *crtc,
870 uint32_t sprite_width, int pixel_size,
871 bool enabled, bool scaled);
872void intel_init_pm(struct drm_device *dev);
f742a552 873void intel_pm_setup(struct drm_device *dev);
87440425
PZ
874bool intel_fbc_enabled(struct drm_device *dev);
875void intel_update_fbc(struct drm_device *dev);
876void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
877void intel_gpu_ips_teardown(void);
da7e29bd
ID
878int intel_power_domains_init(struct drm_i915_private *);
879void intel_power_domains_remove(struct drm_i915_private *);
880bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
87440425 881 enum intel_display_power_domain domain);
da7e29bd 882bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
ddf9c536 883 enum intel_display_power_domain domain);
da7e29bd 884void intel_display_power_get(struct drm_i915_private *dev_priv,
87440425 885 enum intel_display_power_domain domain);
da7e29bd 886void intel_display_power_put(struct drm_i915_private *dev_priv,
87440425 887 enum intel_display_power_domain domain);
da7e29bd 888void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
87440425
PZ
889void intel_enable_gt_powersave(struct drm_device *dev);
890void intel_disable_gt_powersave(struct drm_device *dev);
891void ironlake_teardown_rc6(struct drm_device *dev);
c67a470b 892void gen6_update_ring_freq(struct drm_device *dev);
076e29f2
DV
893void gen6_rps_idle(struct drm_i915_private *dev_priv);
894void gen6_rps_boost(struct drm_i915_private *dev_priv);
87440425
PZ
895void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
896void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
8a187455
PZ
897void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
898void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
899void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
900void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
243e6a44 901void ilk_wm_get_hw_state(struct drm_device *dev);
b3daeaef 902
72662e10 903
5f1aae65 904/* intel_sdvo.c */
87440425 905bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
96a02917 906
2b28bb1b 907
5f1aae65 908/* intel_sprite.c */
87440425 909int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1dba99f4 910void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
87440425
PZ
911 enum plane plane);
912void intel_plane_restore(struct drm_plane *plane);
913void intel_plane_disable(struct drm_plane *plane);
914int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
915 struct drm_file *file_priv);
916int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
917 struct drm_file *file_priv);
5f1aae65
PZ
918
919
920/* intel_tv.c */
87440425 921void intel_tv_init(struct drm_device *dev);
20ddf665 922
79e53945 923#endif /* __INTEL_DRV_H__ */