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CommitLineData
79e53945
JB
1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
178f736a 29#include <linux/hdmi.h>
760285e7 30#include <drm/i915_drm.h>
80824003 31#include "i915_drv.h"
760285e7
DH
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_fb_helper.h>
612a9aab 35#include <drm/drm_dp_helper.h>
913d8d11 36
1d5bfac9
DV
37/**
38 * _wait_for - magic (register) wait macro
39 *
40 * Does the right thing for modeset paths when run under kdgb or similar atomic
41 * contexts. Note that it's important that we check the condition again after
42 * having timed out, since the timeout could be due to preemption or similar and
43 * we've never had a chance to check the condition before the timeout.
44 */
481b6af3 45#define _wait_for(COND, MS, W) ({ \
1d5bfac9 46 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
913d8d11 47 int ret__ = 0; \
0206e353 48 while (!(COND)) { \
913d8d11 49 if (time_after(jiffies, timeout__)) { \
1d5bfac9
DV
50 if (!(COND)) \
51 ret__ = -ETIMEDOUT; \
913d8d11
CW
52 break; \
53 } \
0cc2764c
BW
54 if (W && drm_can_sleep()) { \
55 msleep(W); \
56 } else { \
57 cpu_relax(); \
58 } \
913d8d11
CW
59 } \
60 ret__; \
61})
62
481b6af3
CW
63#define wait_for(COND, MS) _wait_for(COND, MS, 1)
64#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
6effa33b
DV
65#define wait_for_atomic_us(COND, US) _wait_for((COND), \
66 DIV_ROUND_UP((US), 1000), 0)
481b6af3 67
49938ac4
JN
68#define KHz(x) (1000 * (x))
69#define MHz(x) KHz(1000 * (x))
021357ac 70
79e53945
JB
71/*
72 * Display related stuff
73 */
74
75/* store information about an Ixxx DVO */
76/* The i830->i865 use multiple DVOs with multiple i2cs */
77/* the i915, i945 have a single sDVO i2c bus - which is different */
78#define MAX_OUTPUTS 6
79/* maximum connectors per crtcs in the mode set */
79e53945 80
4726e0b0
SK
81/* Maximum cursor sizes */
82#define GEN2_CURSOR_WIDTH 64
83#define GEN2_CURSOR_HEIGHT 64
068be561
DL
84#define MAX_CURSOR_WIDTH 256
85#define MAX_CURSOR_HEIGHT 256
4726e0b0 86
79e53945
JB
87#define INTEL_I2C_BUS_DVO 1
88#define INTEL_I2C_BUS_SDVO 2
89
90/* these are outputs from the chip - integrated only
91 external chips are via DVO or SDVO output */
92#define INTEL_OUTPUT_UNUSED 0
93#define INTEL_OUTPUT_ANALOG 1
94#define INTEL_OUTPUT_DVO 2
95#define INTEL_OUTPUT_SDVO 3
96#define INTEL_OUTPUT_LVDS 4
97#define INTEL_OUTPUT_TVOUT 5
7d57382e 98#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 99#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 100#define INTEL_OUTPUT_EDP 8
72ffa333
JN
101#define INTEL_OUTPUT_DSI 9
102#define INTEL_OUTPUT_UNKNOWN 10
79e53945
JB
103
104#define INTEL_DVO_CHIP_NONE 0
105#define INTEL_DVO_CHIP_LVDS 1
106#define INTEL_DVO_CHIP_TMDS 2
107#define INTEL_DVO_CHIP_TVOUT 4
108
72ffa333
JN
109#define INTEL_DSI_COMMAND_MODE 0
110#define INTEL_DSI_VIDEO_MODE 1
111
79e53945
JB
112struct intel_framebuffer {
113 struct drm_framebuffer base;
05394f39 114 struct drm_i915_gem_object *obj;
79e53945
JB
115};
116
37811fcc
CW
117struct intel_fbdev {
118 struct drm_fb_helper helper;
8bcd4553 119 struct intel_framebuffer *fb;
37811fcc
CW
120 struct list_head fbdev_list;
121 struct drm_display_mode *our_mode;
d978ef14 122 int preferred_bpp;
37811fcc 123};
79e53945 124
21d40d37 125struct intel_encoder {
4ef69c7a 126 struct drm_encoder base;
9a935856
DV
127 /*
128 * The new crtc this encoder will be driven from. Only differs from
129 * base->crtc while a modeset is in progress.
130 */
131 struct intel_crtc *new_crtc;
132
79e53945 133 int type;
bc079e8b 134 unsigned int cloneable;
5ab432ef 135 bool connectors_active;
21d40d37 136 void (*hot_plug)(struct intel_encoder *);
7ae89233
DV
137 bool (*compute_config)(struct intel_encoder *,
138 struct intel_crtc_config *);
dafd226c 139 void (*pre_pll_enable)(struct intel_encoder *);
bf49ec8c 140 void (*pre_enable)(struct intel_encoder *);
ef9c3aee 141 void (*enable)(struct intel_encoder *);
6cc5f341 142 void (*mode_set)(struct intel_encoder *intel_encoder);
ef9c3aee 143 void (*disable)(struct intel_encoder *);
bf49ec8c 144 void (*post_disable)(struct intel_encoder *);
f0947c37
DV
145 /* Read out the current hw state of this connector, returning true if
146 * the encoder is active. If the encoder is enabled it also set the pipe
147 * it is connected to in the pipe parameter. */
148 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
045ac3b5 149 /* Reconstructs the equivalent mode flags for the current hardware
fdafa9e2 150 * state. This must be called _after_ display->get_pipe_config has
63000ef6
XZ
151 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
152 * be set correctly before calling this function. */
045ac3b5
JB
153 void (*get_config)(struct intel_encoder *,
154 struct intel_crtc_config *pipe_config);
f8aed700 155 int crtc_mask;
1d843f9d 156 enum hpd_pin hpd_pin;
79e53945
JB
157};
158
1d508706 159struct intel_panel {
dd06f90e 160 struct drm_display_mode *fixed_mode;
ec9ed197 161 struct drm_display_mode *downclock_mode;
4d891523 162 int fitting_mode;
58c68779
JN
163
164 /* backlight */
165 struct {
c91c9f32 166 bool present;
58c68779 167 u32 level;
7bd688cd 168 u32 max;
58c68779 169 bool enabled;
636baebf
JN
170 bool combination_mode; /* gen 2/4 only */
171 bool active_low_pwm;
58c68779
JN
172 struct backlight_device *device;
173 } backlight;
1d508706
JN
174};
175
5daa55eb
ZW
176struct intel_connector {
177 struct drm_connector base;
9a935856
DV
178 /*
179 * The fixed encoder this connector is connected to.
180 */
df0e9248 181 struct intel_encoder *encoder;
9a935856
DV
182
183 /*
184 * The new encoder this connector will be driven. Only differs from
185 * encoder while a modeset is in progress.
186 */
187 struct intel_encoder *new_encoder;
188
f0947c37
DV
189 /* Reads out the current hw, returning true if the connector is enabled
190 * and active (i.e. dpms ON state). */
191 bool (*get_hw_state)(struct intel_connector *);
1d508706 192
4932e2c3
ID
193 /*
194 * Removes all interfaces through which the connector is accessible
195 * - like sysfs, debugfs entries -, so that no new operations can be
196 * started on the connector. Also makes sure all currently pending
197 * operations finish before returing.
198 */
199 void (*unregister)(struct intel_connector *);
200
1d508706
JN
201 /* Panel info for eDP and LVDS */
202 struct intel_panel panel;
9cd300e0
JN
203
204 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
205 struct edid *edid;
821450c6
EE
206
207 /* since POLL and HPD connectors may use the same HPD line keep the native
208 state of connector->polled in case hotplug storm detection changes it */
209 u8 polled;
5daa55eb
ZW
210};
211
80ad9206
VS
212typedef struct dpll {
213 /* given values */
214 int n;
215 int m1, m2;
216 int p1, p2;
217 /* derived values */
218 int dot;
219 int vco;
220 int m;
221 int p;
222} intel_clock_t;
223
46f297fb 224struct intel_plane_config {
46f297fb
JB
225 bool tiled;
226 int size;
227 u32 base;
228};
229
b8cecdf5 230struct intel_crtc_config {
bb760063
DV
231 /**
232 * quirks - bitfield with hw state readout quirks
233 *
234 * For various reasons the hw state readout code might not be able to
235 * completely faithfully read out the current state. These cases are
236 * tracked with quirk flags so that fastboot and state checker can act
237 * accordingly.
238 */
9953599b
DV
239#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
240#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
bb760063
DV
241 unsigned long quirks;
242
5113bc9b
VS
243 /* User requested mode, only valid as a starting point to
244 * compute adjusted_mode, except in the case of (S)DVO where
245 * it's also for the output timings of the (S)DVO chip.
246 * adjusted_mode will then correspond to the S(DVO) chip's
247 * preferred input timings. */
b8cecdf5 248 struct drm_display_mode requested_mode;
3c52f4eb 249 /* Actual pipe timings ie. what we program into the pipe timing
241bfc38 250 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
b8cecdf5 251 struct drm_display_mode adjusted_mode;
37327abd
VS
252
253 /* Pipe source size (ie. panel fitter input size)
254 * All planes will be positioned inside this space,
255 * and get clipped at the edges. */
256 int pipe_src_w, pipe_src_h;
257
5bfe2ac0
DV
258 /* Whether to set up the PCH/FDI. Note that we never allow sharing
259 * between pch encoders and cpu encoders. */
260 bool has_pch_encoder;
50f3b016 261
3b117c8f
DV
262 /* CPU Transcoder for the pipe. Currently this can only differ from the
263 * pipe on Haswell (where we have a special eDP transcoder). */
264 enum transcoder cpu_transcoder;
265
50f3b016
DV
266 /*
267 * Use reduced/limited/broadcast rbg range, compressing from the full
268 * range fed into the crtcs.
269 */
270 bool limited_color_range;
271
03afc4a2
DV
272 /* DP has a bunch of special case unfortunately, so mark the pipe
273 * accordingly. */
274 bool has_dp_encoder;
d8b32247
DV
275
276 /*
277 * Enable dithering, used when the selected pipe bpp doesn't match the
278 * plane bpp.
279 */
965e0c48 280 bool dither;
f47709a9
DV
281
282 /* Controls for the clock computation, to override various stages. */
283 bool clock_set;
284
09ede541
DV
285 /* SDVO TV has a bunch of special case. To make multifunction encoders
286 * work correctly, we need to track this at runtime.*/
287 bool sdvo_tv_clock;
288
e29c22c0
DV
289 /*
290 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
291 * required. This is set in the 2nd loop of calling encoder's
292 * ->compute_config if the first pick doesn't work out.
293 */
294 bool bw_constrained;
295
f47709a9
DV
296 /* Settings for the intel dpll used on pretty much everything but
297 * haswell. */
80ad9206 298 struct dpll dpll;
f47709a9 299
a43f6e0f
DV
300 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
301 enum intel_dpll_id shared_dpll;
302
66e985c0
DV
303 /* Actual register state of the dpll, for shared dpll cross-checking. */
304 struct intel_dpll_hw_state dpll_hw_state;
305
965e0c48 306 int pipe_bpp;
6cf86a5e 307 struct intel_link_m_n dp_m_n;
ff9a6750 308
439d7ac0
PB
309 /* m2_n2 for eDP downclock */
310 struct intel_link_m_n dp_m2_n2;
311
ff9a6750
DV
312 /*
313 * Frequence the dpll for the port should run at. Differs from the
3c52f4eb
VS
314 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
315 * already multiplied by pixel_multiplier.
df92b1e6 316 */
ff9a6750
DV
317 int port_clock;
318
6cc5f341
DV
319 /* Used by SDVO (and if we ever fix it, HDMI). */
320 unsigned pixel_multiplier;
2dd24552
JB
321
322 /* Panel fitter controls for gen2-gen4 + VLV */
b074cec8
JB
323 struct {
324 u32 control;
325 u32 pgm_ratios;
68fc8742 326 u32 lvds_border_bits;
b074cec8
JB
327 } gmch_pfit;
328
329 /* Panel fitter placement and size for Ironlake+ */
330 struct {
331 u32 pos;
332 u32 size;
fd4daa9c 333 bool enabled;
b074cec8 334 } pch_pfit;
33d29b14 335
ca3a0ff8 336 /* FDI configuration, only valid if has_pch_encoder is set. */
33d29b14 337 int fdi_lanes;
ca3a0ff8 338 struct intel_link_m_n fdi_m_n;
42db64ef
PZ
339
340 bool ips_enabled;
cf532bb2
VS
341
342 bool double_wide;
b8cecdf5
DV
343};
344
0b2ae6d7
VS
345struct intel_pipe_wm {
346 struct intel_wm_level wm[5];
347 uint32_t linetime;
348 bool fbc_wm_enabled;
2a44b76b
VS
349 bool pipe_enabled;
350 bool sprites_enabled;
351 bool sprites_scaled;
0b2ae6d7
VS
352};
353
79e53945
JB
354struct intel_crtc {
355 struct drm_crtc base;
80824003
JB
356 enum pipe pipe;
357 enum plane plane;
79e53945 358 u8 lut_r[256], lut_g[256], lut_b[256];
08a48469
DV
359 /*
360 * Whether the crtc and the connected output pipeline is active. Implies
361 * that crtc->enabled is set, i.e. the current mode configuration has
362 * some outputs connected to this crtc.
08a48469
DV
363 */
364 bool active;
6efdf354 365 unsigned long enabled_power_domains;
7b9f35a6 366 bool eld_vld;
4c445e0e 367 bool primary_enabled; /* is the primary plane (partially) visible? */
652c393a 368 bool lowfreq_avail;
02e792fb 369 struct intel_overlay *overlay;
6b95a207 370 struct intel_unpin_work *unpin_work;
cda4b7d3 371
b4a98e57
CW
372 atomic_t unpin_work_count;
373
e506a0c6
DV
374 /* Display surface base address adjustement for pageflips. Note that on
375 * gen4+ this only adjusts up to a tile, offsets within a tile are
376 * handled in the hw itself (with the TILEOFF register). */
377 unsigned long dspaddr_offset;
378
05394f39 379 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW
380 uint32_t cursor_addr;
381 int16_t cursor_x, cursor_y;
382 int16_t cursor_width, cursor_height;
6b383a7f 383 bool cursor_visible;
4b645f14 384
46f297fb 385 struct intel_plane_config plane_config;
b8cecdf5 386 struct intel_crtc_config config;
50741abc 387 struct intel_crtc_config *new_config;
7668851f 388 bool new_enabled;
b8cecdf5 389
6441ab5f 390 uint32_t ddi_pll_sel;
10d83730
VS
391
392 /* reset counter value when the last flip was submitted */
393 unsigned int reset_counter;
8664281b
PZ
394
395 /* Access to these should be protected by dev_priv->irq_lock. */
396 bool cpu_fifo_underrun_disabled;
397 bool pch_fifo_underrun_disabled;
0b2ae6d7
VS
398
399 /* per-pipe watermark state */
400 struct {
401 /* watermarks currently being used */
402 struct intel_pipe_wm active;
403 } wm;
79e53945
JB
404};
405
c35426d2
VS
406struct intel_plane_wm_parameters {
407 uint32_t horiz_pixels;
408 uint8_t bytes_per_pixel;
409 bool enabled;
410 bool scaled;
411};
412
b840d907
JB
413struct intel_plane {
414 struct drm_plane base;
7f1f3851 415 int plane;
b840d907
JB
416 enum pipe pipe;
417 struct drm_i915_gem_object *obj;
2d354c34 418 bool can_scale;
b840d907
JB
419 int max_downscale;
420 u32 lut_r[1024], lut_g[1024], lut_b[1024];
5e1bac2f
JB
421 int crtc_x, crtc_y;
422 unsigned int crtc_w, crtc_h;
423 uint32_t src_x, src_y;
424 uint32_t src_w, src_h;
526682e9
PZ
425
426 /* Since we need to change the watermarks before/after
427 * enabling/disabling the planes, we need to store the parameters here
428 * as the other pieces of the struct may not reflect the values we want
429 * for the watermark calculations. Currently only Haswell uses this.
430 */
c35426d2 431 struct intel_plane_wm_parameters wm;
526682e9 432
b840d907 433 void (*update_plane)(struct drm_plane *plane,
b39d53f6 434 struct drm_crtc *crtc,
b840d907
JB
435 struct drm_framebuffer *fb,
436 struct drm_i915_gem_object *obj,
437 int crtc_x, int crtc_y,
438 unsigned int crtc_w, unsigned int crtc_h,
439 uint32_t x, uint32_t y,
440 uint32_t src_w, uint32_t src_h);
b39d53f6
VS
441 void (*disable_plane)(struct drm_plane *plane,
442 struct drm_crtc *crtc);
8ea30864
JB
443 int (*update_colorkey)(struct drm_plane *plane,
444 struct drm_intel_sprite_colorkey *key);
445 void (*get_colorkey)(struct drm_plane *plane,
446 struct drm_intel_sprite_colorkey *key);
b840d907
JB
447};
448
b445e3b0
ED
449struct intel_watermark_params {
450 unsigned long fifo_size;
451 unsigned long max_wm;
452 unsigned long default_wm;
453 unsigned long guard_size;
454 unsigned long cacheline_size;
455};
456
457struct cxsr_latency {
458 int is_desktop;
459 int is_ddr3;
460 unsigned long fsb_freq;
461 unsigned long mem_freq;
462 unsigned long display_sr;
463 unsigned long display_hpll_disable;
464 unsigned long cursor_sr;
465 unsigned long cursor_hpll_disable;
466};
467
79e53945 468#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 469#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 470#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 471#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 472#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 473
f5bbfca3 474struct intel_hdmi {
b242b7f7 475 u32 hdmi_reg;
f5bbfca3 476 int ddc_bus;
f5bbfca3 477 uint32_t color_range;
55bc60db 478 bool color_range_auto;
f5bbfca3
ED
479 bool has_hdmi_sink;
480 bool has_audio;
481 enum hdmi_force_audio force_audio;
abedc077 482 bool rgb_quant_range_selectable;
f5bbfca3 483 void (*write_infoframe)(struct drm_encoder *encoder,
178f736a 484 enum hdmi_infoframe_type type,
fff63867 485 const void *frame, ssize_t len);
687f4d06
PZ
486 void (*set_infoframes)(struct drm_encoder *encoder,
487 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED
488};
489
b091cd92 490#define DP_MAX_DOWNSTREAM_PORTS 0x10
54d63ca6 491
4f9db5b5
PB
492/**
493 * HIGH_RR is the highest eDP panel refresh rate read from EDID
494 * LOW_RR is the lowest eDP panel refresh rate found from EDID
495 * parsing for same resolution.
496 */
497enum edp_drrs_refresh_rate_type {
498 DRRS_HIGH_RR,
499 DRRS_LOW_RR,
500 DRRS_MAX_RR, /* RR count */
501};
502
54d63ca6 503struct intel_dp {
54d63ca6 504 uint32_t output_reg;
9ed35ab1 505 uint32_t aux_ch_ctl_reg;
54d63ca6 506 uint32_t DP;
54d63ca6
SK
507 bool has_audio;
508 enum hdmi_force_audio force_audio;
509 uint32_t color_range;
55bc60db 510 bool color_range_auto;
54d63ca6
SK
511 uint8_t link_bw;
512 uint8_t lane_count;
513 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
2293bb5c 514 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
b091cd92 515 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
9d1a1031 516 struct drm_dp_aux aux;
54d63ca6
SK
517 uint8_t train_set[4];
518 int panel_power_up_delay;
519 int panel_power_down_delay;
520 int panel_power_cycle_delay;
521 int backlight_on_delay;
522 int backlight_off_delay;
54d63ca6
SK
523 struct delayed_work panel_vdd_work;
524 bool want_panel_vdd;
dce56b3c
PZ
525 unsigned long last_power_cycle;
526 unsigned long last_power_on;
527 unsigned long last_backlight_off;
2b28bb1b 528 bool psr_setup_done;
06ea66b6 529 bool use_tps3;
dd06f90e 530 struct intel_connector *attached_connector;
ec5b01dd
DL
531
532 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
153b1100
DL
533 /*
534 * This function returns the value we have to program the AUX_CTL
535 * register with to kick off an AUX transaction.
536 */
537 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
538 bool has_aux_irq,
539 int send_bytes,
540 uint32_t aux_clock_divider);
4f9db5b5
PB
541 struct {
542 enum drrs_support_type type;
543 enum edp_drrs_refresh_rate_type refresh_rate_type;
439d7ac0 544 struct mutex mutex;
4f9db5b5
PB
545 } drrs_state;
546
54d63ca6
SK
547};
548
da63a9f2
PZ
549struct intel_digital_port {
550 struct intel_encoder base;
174edf1f 551 enum port port;
bcf53de4 552 u32 saved_port_bits;
da63a9f2
PZ
553 struct intel_dp dp;
554 struct intel_hdmi hdmi;
555};
556
89b667f8
JB
557static inline int
558vlv_dport_to_channel(struct intel_digital_port *dport)
559{
560 switch (dport->port) {
561 case PORT_B:
e4607fcf 562 return DPIO_CH0;
89b667f8 563 case PORT_C:
e4607fcf 564 return DPIO_CH1;
89b667f8
JB
565 default:
566 BUG();
567 }
568}
569
f875c15a
CW
570static inline struct drm_crtc *
571intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
572{
573 struct drm_i915_private *dev_priv = dev->dev_private;
574 return dev_priv->pipe_to_crtc_mapping[pipe];
575}
576
417ae147
CW
577static inline struct drm_crtc *
578intel_get_crtc_for_plane(struct drm_device *dev, int plane)
579{
580 struct drm_i915_private *dev_priv = dev->dev_private;
581 return dev_priv->plane_to_crtc_mapping[plane];
582}
583
4e5359cd
SF
584struct intel_unpin_work {
585 struct work_struct work;
b4a98e57 586 struct drm_crtc *crtc;
05394f39
CW
587 struct drm_i915_gem_object *old_fb_obj;
588 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd 589 struct drm_pending_vblank_event *event;
e7d841ca
CW
590 atomic_t pending;
591#define INTEL_FLIP_INACTIVE 0
592#define INTEL_FLIP_PENDING 1
593#define INTEL_FLIP_COMPLETE 2
4e5359cd
SF
594 bool enable_stall_check;
595};
596
d9e55608 597struct intel_set_config {
1aa4b628
DV
598 struct drm_encoder **save_connector_encoders;
599 struct drm_crtc **save_encoder_crtcs;
7668851f 600 bool *save_crtc_enabled;
5e2b584e
DV
601
602 bool fb_changed;
603 bool mode_changed;
d9e55608
DV
604};
605
5f1aae65
PZ
606struct intel_load_detect_pipe {
607 struct drm_framebuffer *release_fb;
608 bool load_detect_temp;
609 int dpms_mode;
610};
79e53945 611
5f1aae65
PZ
612static inline struct intel_encoder *
613intel_attached_encoder(struct drm_connector *connector)
df0e9248
CW
614{
615 return to_intel_connector(connector)->encoder;
616}
617
da63a9f2
PZ
618static inline struct intel_digital_port *
619enc_to_dig_port(struct drm_encoder *encoder)
620{
621 return container_of(encoder, struct intel_digital_port, base.base);
9ff8c9ba
ID
622}
623
624static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
625{
626 return &enc_to_dig_port(encoder)->dp;
da63a9f2
PZ
627}
628
629static inline struct intel_digital_port *
630dp_to_dig_port(struct intel_dp *intel_dp)
631{
632 return container_of(intel_dp, struct intel_digital_port, dp);
633}
634
635static inline struct intel_digital_port *
636hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
637{
638 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
7739c33b
PZ
639}
640
5f1aae65
PZ
641
642/* i915_irq.c */
87440425
PZ
643bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
644 enum pipe pipe, bool enable);
77961eb9
ID
645bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
646 enum pipe pipe, bool enable);
87440425
PZ
647bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
648 enum transcoder pch_transcoder,
649 bool enable);
650void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
651void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
652void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
653void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
730488b2
PZ
654void intel_runtime_pm_disable_interrupts(struct drm_device *dev);
655void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
5f1aae65
PZ
656
657
658/* intel_crt.c */
87440425 659void intel_crt_init(struct drm_device *dev);
5f1aae65
PZ
660
661
662/* intel_ddi.c */
87440425
PZ
663void intel_prepare_ddi(struct drm_device *dev);
664void hsw_fdi_link_train(struct drm_crtc *crtc);
665void intel_ddi_init(struct drm_device *dev, enum port port);
666enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
667bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
668int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
669void intel_ddi_pll_init(struct drm_device *dev);
670void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
671void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
672 enum transcoder cpu_transcoder);
673void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
674void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
675void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
566b734a
PZ
676bool intel_ddi_pll_select(struct intel_crtc *crtc);
677void intel_ddi_pll_enable(struct intel_crtc *crtc);
87440425
PZ
678void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
679void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
680void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
681bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
682void intel_ddi_fdi_disable(struct drm_crtc *crtc);
683void intel_ddi_get_config(struct intel_encoder *encoder,
684 struct intel_crtc_config *pipe_config);
5f1aae65
PZ
685
686
687/* intel_display.c */
ba0fbca4 688const char *intel_output_name(int output);
5dce5b93 689bool intel_has_pending_fb_unpin(struct drm_device *dev);
5f1aae65 690int intel_pch_rawclk(struct drm_device *dev);
d60c4473 691int valleyview_cur_cdclk(struct drm_i915_private *dev_priv);
87440425
PZ
692void intel_mark_busy(struct drm_device *dev);
693void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
694 struct intel_ring_buffer *ring);
695void intel_mark_idle(struct drm_device *dev);
696void intel_crtc_restore_mode(struct drm_crtc *crtc);
697void intel_crtc_update_dpms(struct drm_crtc *crtc);
698void intel_encoder_destroy(struct drm_encoder *encoder);
699void intel_connector_dpms(struct drm_connector *, int mode);
700bool intel_connector_get_hw_state(struct intel_connector *connector);
701void intel_modeset_check_state(struct drm_device *dev);
b0ea7d37
DL
702bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
703 struct intel_digital_port *port);
87440425
PZ
704void intel_connector_attach_encoder(struct intel_connector *connector,
705 struct intel_encoder *encoder);
706struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
707struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
708 struct drm_crtc *crtc);
752aa88a 709enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
08d7b3d1
CW
710int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
711 struct drm_file *file_priv);
87440425
PZ
712enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
713 enum pipe pipe);
714void intel_wait_for_vblank(struct drm_device *dev, int pipe);
715void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
716int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
e4607fcf
CML
717void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
718 struct intel_digital_port *dport);
87440425
PZ
719bool intel_get_load_detect_pipe(struct drm_connector *connector,
720 struct drm_display_mode *mode,
721 struct intel_load_detect_pipe *old);
722void intel_release_load_detect_pipe(struct drm_connector *connector,
723 struct intel_load_detect_pipe *old);
724int intel_pin_and_fence_fb_obj(struct drm_device *dev,
725 struct drm_i915_gem_object *obj,
726 struct intel_ring_buffer *pipelined);
727void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
a8bb6818
DV
728struct drm_framebuffer *
729__intel_framebuffer_create(struct drm_device *dev,
87440425
PZ
730 struct drm_mode_fb_cmd2 *mode_cmd,
731 struct drm_i915_gem_object *obj);
87440425
PZ
732void intel_prepare_page_flip(struct drm_device *dev, int plane);
733void intel_finish_page_flip(struct drm_device *dev, int pipe);
734void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
5f1aae65 735struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
55607e8a
DV
736void assert_shared_dpll(struct drm_i915_private *dev_priv,
737 struct intel_shared_dpll *pll,
738 bool state);
739#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
740#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
741void assert_pll(struct drm_i915_private *dev_priv,
742 enum pipe pipe, bool state);
743#define assert_pll_enabled(d, p) assert_pll(d, p, true)
744#define assert_pll_disabled(d, p) assert_pll(d, p, false)
745void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
746 enum pipe pipe, bool state);
747#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
748#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
87440425 749void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
b840d907
JB
750#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
751#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
87440425
PZ
752void intel_write_eld(struct drm_encoder *encoder,
753 struct drm_display_mode *mode);
754unsigned long intel_gen4_compute_page_offset(int *x, int *y,
755 unsigned int tiling_mode,
756 unsigned int bpp,
757 unsigned int pitch);
758void intel_display_handle_reset(struct drm_device *dev);
a14cb6fc
PZ
759void hsw_enable_pc8(struct drm_i915_private *dev_priv);
760void hsw_disable_pc8(struct drm_i915_private *dev_priv);
87440425
PZ
761void intel_dp_get_m_n(struct intel_crtc *crtc,
762 struct intel_crtc_config *pipe_config);
763int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
764void
5f1aae65
PZ
765ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
766 int dotclock);
87440425 767bool intel_crtc_active(struct drm_crtc *crtc);
20bc8673
VS
768void hsw_enable_ips(struct intel_crtc *crtc);
769void hsw_disable_ips(struct intel_crtc *crtc);
da7e29bd 770void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
319be8ae
ID
771enum intel_display_power_domain
772intel_display_port_power_domain(struct intel_encoder *intel_encoder);
586f49dc 773int valleyview_get_vco(struct drm_i915_private *dev_priv);
f6a83288
DV
774void intel_mode_from_pipe_config(struct drm_display_mode *mode,
775 struct intel_crtc_config *pipe_config);
46f297fb 776int intel_format_to_fourcc(int format);
8ea30864 777
5f1aae65 778/* intel_dp.c */
87440425
PZ
779void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
780bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
781 struct intel_connector *intel_connector);
87440425
PZ
782void intel_dp_start_link_train(struct intel_dp *intel_dp);
783void intel_dp_complete_link_train(struct intel_dp *intel_dp);
784void intel_dp_stop_link_train(struct intel_dp *intel_dp);
785void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
786void intel_dp_encoder_destroy(struct drm_encoder *encoder);
787void intel_dp_check_link_status(struct intel_dp *intel_dp);
d2e216d0 788int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
87440425
PZ
789bool intel_dp_compute_config(struct intel_encoder *encoder,
790 struct intel_crtc_config *pipe_config);
5d8a7752 791bool intel_dp_is_edp(struct drm_device *dev, enum port port);
4be73780
DV
792void intel_edp_backlight_on(struct intel_dp *intel_dp);
793void intel_edp_backlight_off(struct intel_dp *intel_dp);
24f3e092 794void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780
DV
795void intel_edp_panel_on(struct intel_dp *intel_dp);
796void intel_edp_panel_off(struct intel_dp *intel_dp);
87440425
PZ
797void intel_edp_psr_enable(struct intel_dp *intel_dp);
798void intel_edp_psr_disable(struct intel_dp *intel_dp);
799void intel_edp_psr_update(struct drm_device *dev);
439d7ac0 800void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
5f1aae65
PZ
801
802/* intel_dsi.c */
87440425 803bool intel_dsi_init(struct drm_device *dev);
5f1aae65
PZ
804
805
806/* intel_dvo.c */
87440425 807void intel_dvo_init(struct drm_device *dev);
5f1aae65
PZ
808
809
0632fef6 810/* legacy fbdev emulation in intel_fbdev.c */
4520f53a
DV
811#ifdef CONFIG_DRM_I915_FBDEV
812extern int intel_fbdev_init(struct drm_device *dev);
813extern void intel_fbdev_initial_config(struct drm_device *dev);
814extern void intel_fbdev_fini(struct drm_device *dev);
815extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
0632fef6
DV
816extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
817extern void intel_fbdev_restore_mode(struct drm_device *dev);
4520f53a
DV
818#else
819static inline int intel_fbdev_init(struct drm_device *dev)
820{
821 return 0;
822}
5f1aae65 823
4520f53a
DV
824static inline void intel_fbdev_initial_config(struct drm_device *dev)
825{
826}
827
828static inline void intel_fbdev_fini(struct drm_device *dev)
829{
830}
831
832static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
833{
834}
835
0632fef6 836static inline void intel_fbdev_restore_mode(struct drm_device *dev)
4520f53a
DV
837{
838}
839#endif
5f1aae65
PZ
840
841/* intel_hdmi.c */
87440425
PZ
842void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
843void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
844 struct intel_connector *intel_connector);
845struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
846bool intel_hdmi_compute_config(struct intel_encoder *encoder,
847 struct intel_crtc_config *pipe_config);
5f1aae65
PZ
848
849
850/* intel_lvds.c */
87440425
PZ
851void intel_lvds_init(struct drm_device *dev);
852bool intel_is_dual_link_lvds(struct drm_device *dev);
5f1aae65
PZ
853
854
855/* intel_modes.c */
856int intel_connector_update_modes(struct drm_connector *connector,
87440425 857 struct edid *edid);
5f1aae65 858int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
87440425
PZ
859void intel_attach_force_audio_property(struct drm_connector *connector);
860void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
5f1aae65
PZ
861
862
863/* intel_overlay.c */
87440425
PZ
864void intel_setup_overlay(struct drm_device *dev);
865void intel_cleanup_overlay(struct drm_device *dev);
866int intel_overlay_switch_off(struct intel_overlay *overlay);
867int intel_overlay_put_image(struct drm_device *dev, void *data,
868 struct drm_file *file_priv);
869int intel_overlay_attrs(struct drm_device *dev, void *data,
870 struct drm_file *file_priv);
5f1aae65
PZ
871
872
873/* intel_panel.c */
87440425 874int intel_panel_init(struct intel_panel *panel,
4b6ed685
VK
875 struct drm_display_mode *fixed_mode,
876 struct drm_display_mode *downclock_mode);
87440425
PZ
877void intel_panel_fini(struct intel_panel *panel);
878void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
879 struct drm_display_mode *adjusted_mode);
880void intel_pch_panel_fitting(struct intel_crtc *crtc,
881 struct intel_crtc_config *pipe_config,
882 int fitting_mode);
883void intel_gmch_panel_fitting(struct intel_crtc *crtc,
884 struct intel_crtc_config *pipe_config,
885 int fitting_mode);
752aa88a
JB
886void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
887 u32 max);
87440425 888int intel_panel_setup_backlight(struct drm_connector *connector);
752aa88a
JB
889void intel_panel_enable_backlight(struct intel_connector *connector);
890void intel_panel_disable_backlight(struct intel_connector *connector);
db31af1d 891void intel_panel_destroy_backlight(struct drm_connector *connector);
7bd688cd 892void intel_panel_init_backlight_funcs(struct drm_device *dev);
87440425 893enum drm_connector_status intel_panel_detect(struct drm_device *dev);
ec9ed197
VK
894extern struct drm_display_mode *intel_find_panel_downclock(
895 struct drm_device *dev,
896 struct drm_display_mode *fixed_mode,
897 struct drm_connector *connector);
5f1aae65
PZ
898
899/* intel_pm.c */
87440425
PZ
900void intel_init_clock_gating(struct drm_device *dev);
901void intel_suspend_hw(struct drm_device *dev);
902void intel_update_watermarks(struct drm_crtc *crtc);
903void intel_update_sprite_watermarks(struct drm_plane *plane,
904 struct drm_crtc *crtc,
905 uint32_t sprite_width, int pixel_size,
906 bool enabled, bool scaled);
907void intel_init_pm(struct drm_device *dev);
f742a552 908void intel_pm_setup(struct drm_device *dev);
87440425
PZ
909bool intel_fbc_enabled(struct drm_device *dev);
910void intel_update_fbc(struct drm_device *dev);
911void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
912void intel_gpu_ips_teardown(void);
da7e29bd
ID
913int intel_power_domains_init(struct drm_i915_private *);
914void intel_power_domains_remove(struct drm_i915_private *);
915bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
87440425 916 enum intel_display_power_domain domain);
da7e29bd 917bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
ddf9c536 918 enum intel_display_power_domain domain);
da7e29bd 919void intel_display_power_get(struct drm_i915_private *dev_priv,
87440425 920 enum intel_display_power_domain domain);
da7e29bd 921void intel_display_power_put(struct drm_i915_private *dev_priv,
87440425 922 enum intel_display_power_domain domain);
da7e29bd 923void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
ae48434c
ID
924void intel_init_gt_powersave(struct drm_device *dev);
925void intel_cleanup_gt_powersave(struct drm_device *dev);
87440425
PZ
926void intel_enable_gt_powersave(struct drm_device *dev);
927void intel_disable_gt_powersave(struct drm_device *dev);
c6df39b5 928void intel_reset_gt_powersave(struct drm_device *dev);
87440425 929void ironlake_teardown_rc6(struct drm_device *dev);
c67a470b 930void gen6_update_ring_freq(struct drm_device *dev);
076e29f2
DV
931void gen6_rps_idle(struct drm_i915_private *dev_priv);
932void gen6_rps_boost(struct drm_i915_private *dev_priv);
87440425
PZ
933void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
934void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
8a187455 935void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
c6df39b5 936void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
8a187455
PZ
937void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
938void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
939void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
243e6a44 940void ilk_wm_get_hw_state(struct drm_device *dev);
b3daeaef 941
72662e10 942
5f1aae65 943/* intel_sdvo.c */
87440425 944bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
96a02917 945
2b28bb1b 946
5f1aae65 947/* intel_sprite.c */
87440425 948int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1dba99f4 949void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
87440425
PZ
950 enum plane plane);
951void intel_plane_restore(struct drm_plane *plane);
952void intel_plane_disable(struct drm_plane *plane);
953int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
954 struct drm_file *file_priv);
955int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
956 struct drm_file *file_priv);
5f1aae65
PZ
957
958
959/* intel_tv.c */
87440425 960void intel_tv_init(struct drm_device *dev);
20ddf665 961
79e53945 962#endif /* __INTEL_DRV_H__ */