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Commit | Line | Data |
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54936004 | 1 | /* |
5b6dd868 | 2 | * Virtual page mapping |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
7b31bbc2 | 19 | #include "qemu/osdep.h" |
da34e65c | 20 | #include "qapi/error.h" |
777872e5 | 21 | #ifndef _WIN32 |
d5a8f07c | 22 | #endif |
54936004 | 23 | |
f348b6d1 | 24 | #include "qemu/cutils.h" |
6180a181 | 25 | #include "cpu.h" |
63c91552 | 26 | #include "exec/exec-all.h" |
51180423 | 27 | #include "exec/target_page.h" |
b67d9a52 | 28 | #include "tcg.h" |
741da0d3 | 29 | #include "hw/qdev-core.h" |
c7e002c5 | 30 | #include "hw/qdev-properties.h" |
4485bd26 | 31 | #if !defined(CONFIG_USER_ONLY) |
47c8ca53 | 32 | #include "hw/boards.h" |
33c11879 | 33 | #include "hw/xen/xen.h" |
4485bd26 | 34 | #endif |
9c17d615 | 35 | #include "sysemu/kvm.h" |
2ff3de68 | 36 | #include "sysemu/sysemu.h" |
1de7afc9 PB |
37 | #include "qemu/timer.h" |
38 | #include "qemu/config-file.h" | |
75a34036 | 39 | #include "qemu/error-report.h" |
53a5960a | 40 | #if defined(CONFIG_USER_ONLY) |
a9c94277 | 41 | #include "qemu.h" |
432d268c | 42 | #else /* !CONFIG_USER_ONLY */ |
741da0d3 PB |
43 | #include "hw/hw.h" |
44 | #include "exec/memory.h" | |
df43d49c | 45 | #include "exec/ioport.h" |
741da0d3 | 46 | #include "sysemu/dma.h" |
9c607668 | 47 | #include "sysemu/numa.h" |
79ca7a1b | 48 | #include "sysemu/hw_accel.h" |
741da0d3 | 49 | #include "exec/address-spaces.h" |
9c17d615 | 50 | #include "sysemu/xen-mapcache.h" |
0ab8ed18 | 51 | #include "trace-root.h" |
d3a5038c | 52 | |
e2fa71f5 DDAG |
53 | #ifdef CONFIG_FALLOCATE_PUNCH_HOLE |
54 | #include <fcntl.h> | |
55 | #include <linux/falloc.h> | |
56 | #endif | |
57 | ||
53a5960a | 58 | #endif |
0dc3f44a | 59 | #include "qemu/rcu_queue.h" |
4840f10e | 60 | #include "qemu/main-loop.h" |
5b6dd868 | 61 | #include "translate-all.h" |
7615936e | 62 | #include "sysemu/replay.h" |
0cac1b66 | 63 | |
022c62cb | 64 | #include "exec/memory-internal.h" |
220c3ebd | 65 | #include "exec/ram_addr.h" |
508127e2 | 66 | #include "exec/log.h" |
67d95c15 | 67 | |
9dfeca7c BR |
68 | #include "migration/vmstate.h" |
69 | ||
b35ba30f | 70 | #include "qemu/range.h" |
794e8f30 MT |
71 | #ifndef _WIN32 |
72 | #include "qemu/mmap-alloc.h" | |
73 | #endif | |
b35ba30f | 74 | |
be9b23c4 PX |
75 | #include "monitor/monitor.h" |
76 | ||
db7b5426 | 77 | //#define DEBUG_SUBPAGE |
1196be37 | 78 | |
e2eef170 | 79 | #if !defined(CONFIG_USER_ONLY) |
0dc3f44a MD |
80 | /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes |
81 | * are protected by the ramlist lock. | |
82 | */ | |
0d53d9fe | 83 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) }; |
62152b8a AK |
84 | |
85 | static MemoryRegion *system_memory; | |
309cb471 | 86 | static MemoryRegion *system_io; |
62152b8a | 87 | |
f6790af6 AK |
88 | AddressSpace address_space_io; |
89 | AddressSpace address_space_memory; | |
2673a5da | 90 | |
0844e007 | 91 | MemoryRegion io_mem_rom, io_mem_notdirty; |
acc9d80b | 92 | static MemoryRegion io_mem_unassigned; |
0e0df1e2 | 93 | |
7bd4f430 PB |
94 | /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */ |
95 | #define RAM_PREALLOC (1 << 0) | |
96 | ||
dbcb8981 PB |
97 | /* RAM is mmap-ed with MAP_SHARED */ |
98 | #define RAM_SHARED (1 << 1) | |
99 | ||
62be4e3a MT |
100 | /* Only a portion of RAM (used_length) is actually used, and migrated. |
101 | * This used_length size can change across reboots. | |
102 | */ | |
103 | #define RAM_RESIZEABLE (1 << 2) | |
104 | ||
e2eef170 | 105 | #endif |
9fa3e853 | 106 | |
20bccb82 PM |
107 | #ifdef TARGET_PAGE_BITS_VARY |
108 | int target_page_bits; | |
109 | bool target_page_bits_decided; | |
110 | #endif | |
111 | ||
bdc44640 | 112 | struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus); |
6a00d601 FB |
113 | /* current CPU in the current thread. It is only valid inside |
114 | cpu_exec() */ | |
f240eb6f | 115 | __thread CPUState *current_cpu; |
2e70f6ef | 116 | /* 0 = Do not count executed instructions. |
bf20dc07 | 117 | 1 = Precise instruction counting. |
2e70f6ef | 118 | 2 = Adaptive rate instruction counting. */ |
5708fc66 | 119 | int use_icount; |
6a00d601 | 120 | |
a0be0c58 YZ |
121 | uintptr_t qemu_host_page_size; |
122 | intptr_t qemu_host_page_mask; | |
a0be0c58 | 123 | |
20bccb82 PM |
124 | bool set_preferred_target_page_bits(int bits) |
125 | { | |
126 | /* The target page size is the lowest common denominator for all | |
127 | * the CPUs in the system, so we can only make it smaller, never | |
128 | * larger. And we can't make it smaller once we've committed to | |
129 | * a particular size. | |
130 | */ | |
131 | #ifdef TARGET_PAGE_BITS_VARY | |
132 | assert(bits >= TARGET_PAGE_BITS_MIN); | |
133 | if (target_page_bits == 0 || target_page_bits > bits) { | |
134 | if (target_page_bits_decided) { | |
135 | return false; | |
136 | } | |
137 | target_page_bits = bits; | |
138 | } | |
139 | #endif | |
140 | return true; | |
141 | } | |
142 | ||
e2eef170 | 143 | #if !defined(CONFIG_USER_ONLY) |
4346ae3e | 144 | |
20bccb82 PM |
145 | static void finalize_target_page_bits(void) |
146 | { | |
147 | #ifdef TARGET_PAGE_BITS_VARY | |
148 | if (target_page_bits == 0) { | |
149 | target_page_bits = TARGET_PAGE_BITS_MIN; | |
150 | } | |
151 | target_page_bits_decided = true; | |
152 | #endif | |
153 | } | |
154 | ||
1db8abb1 PB |
155 | typedef struct PhysPageEntry PhysPageEntry; |
156 | ||
157 | struct PhysPageEntry { | |
9736e55b | 158 | /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */ |
8b795765 | 159 | uint32_t skip : 6; |
9736e55b | 160 | /* index into phys_sections (!skip) or phys_map_nodes (skip) */ |
8b795765 | 161 | uint32_t ptr : 26; |
1db8abb1 PB |
162 | }; |
163 | ||
8b795765 MT |
164 | #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6) |
165 | ||
03f49957 | 166 | /* Size of the L2 (and L3, etc) page tables. */ |
57271d63 | 167 | #define ADDR_SPACE_BITS 64 |
03f49957 | 168 | |
026736ce | 169 | #define P_L2_BITS 9 |
03f49957 PB |
170 | #define P_L2_SIZE (1 << P_L2_BITS) |
171 | ||
172 | #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1) | |
173 | ||
174 | typedef PhysPageEntry Node[P_L2_SIZE]; | |
0475d94f | 175 | |
53cb28cb | 176 | typedef struct PhysPageMap { |
79e2b9ae PB |
177 | struct rcu_head rcu; |
178 | ||
53cb28cb MA |
179 | unsigned sections_nb; |
180 | unsigned sections_nb_alloc; | |
181 | unsigned nodes_nb; | |
182 | unsigned nodes_nb_alloc; | |
183 | Node *nodes; | |
184 | MemoryRegionSection *sections; | |
185 | } PhysPageMap; | |
186 | ||
1db8abb1 | 187 | struct AddressSpaceDispatch { |
729633c2 | 188 | MemoryRegionSection *mru_section; |
1db8abb1 PB |
189 | /* This is a multi-level map on the physical address space. |
190 | * The bottom level has pointers to MemoryRegionSections. | |
191 | */ | |
192 | PhysPageEntry phys_map; | |
53cb28cb | 193 | PhysPageMap map; |
1db8abb1 PB |
194 | }; |
195 | ||
90260c6c JK |
196 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
197 | typedef struct subpage_t { | |
198 | MemoryRegion iomem; | |
16620684 | 199 | FlatView *fv; |
90260c6c | 200 | hwaddr base; |
2615fabd | 201 | uint16_t sub_section[]; |
90260c6c JK |
202 | } subpage_t; |
203 | ||
b41aac4f LPF |
204 | #define PHYS_SECTION_UNASSIGNED 0 |
205 | #define PHYS_SECTION_NOTDIRTY 1 | |
206 | #define PHYS_SECTION_ROM 2 | |
207 | #define PHYS_SECTION_WATCH 3 | |
5312bd8b | 208 | |
e2eef170 | 209 | static void io_mem_init(void); |
62152b8a | 210 | static void memory_map_init(void); |
09daed84 | 211 | static void tcg_commit(MemoryListener *listener); |
e2eef170 | 212 | |
1ec9b909 | 213 | static MemoryRegion io_mem_watch; |
32857f4d PM |
214 | |
215 | /** | |
216 | * CPUAddressSpace: all the information a CPU needs about an AddressSpace | |
217 | * @cpu: the CPU whose AddressSpace this is | |
218 | * @as: the AddressSpace itself | |
219 | * @memory_dispatch: its dispatch pointer (cached, RCU protected) | |
220 | * @tcg_as_listener: listener for tracking changes to the AddressSpace | |
221 | */ | |
222 | struct CPUAddressSpace { | |
223 | CPUState *cpu; | |
224 | AddressSpace *as; | |
225 | struct AddressSpaceDispatch *memory_dispatch; | |
226 | MemoryListener tcg_as_listener; | |
227 | }; | |
228 | ||
8deaf12c GH |
229 | struct DirtyBitmapSnapshot { |
230 | ram_addr_t start; | |
231 | ram_addr_t end; | |
232 | unsigned long dirty[]; | |
233 | }; | |
234 | ||
6658ffb8 | 235 | #endif |
fd6ce8f6 | 236 | |
6d9a1304 | 237 | #if !defined(CONFIG_USER_ONLY) |
d6f2ea22 | 238 | |
53cb28cb | 239 | static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes) |
d6f2ea22 | 240 | { |
101420b8 | 241 | static unsigned alloc_hint = 16; |
53cb28cb | 242 | if (map->nodes_nb + nodes > map->nodes_nb_alloc) { |
101420b8 | 243 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint); |
53cb28cb MA |
244 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes); |
245 | map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc); | |
101420b8 | 246 | alloc_hint = map->nodes_nb_alloc; |
d6f2ea22 | 247 | } |
f7bf5461 AK |
248 | } |
249 | ||
db94604b | 250 | static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf) |
f7bf5461 AK |
251 | { |
252 | unsigned i; | |
8b795765 | 253 | uint32_t ret; |
db94604b PB |
254 | PhysPageEntry e; |
255 | PhysPageEntry *p; | |
f7bf5461 | 256 | |
53cb28cb | 257 | ret = map->nodes_nb++; |
db94604b | 258 | p = map->nodes[ret]; |
f7bf5461 | 259 | assert(ret != PHYS_MAP_NODE_NIL); |
53cb28cb | 260 | assert(ret != map->nodes_nb_alloc); |
db94604b PB |
261 | |
262 | e.skip = leaf ? 0 : 1; | |
263 | e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL; | |
03f49957 | 264 | for (i = 0; i < P_L2_SIZE; ++i) { |
db94604b | 265 | memcpy(&p[i], &e, sizeof(e)); |
d6f2ea22 | 266 | } |
f7bf5461 | 267 | return ret; |
d6f2ea22 AK |
268 | } |
269 | ||
53cb28cb MA |
270 | static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp, |
271 | hwaddr *index, hwaddr *nb, uint16_t leaf, | |
2999097b | 272 | int level) |
f7bf5461 AK |
273 | { |
274 | PhysPageEntry *p; | |
03f49957 | 275 | hwaddr step = (hwaddr)1 << (level * P_L2_BITS); |
108c49b8 | 276 | |
9736e55b | 277 | if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) { |
db94604b | 278 | lp->ptr = phys_map_node_alloc(map, level == 0); |
92e873b9 | 279 | } |
db94604b | 280 | p = map->nodes[lp->ptr]; |
03f49957 | 281 | lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
f7bf5461 | 282 | |
03f49957 | 283 | while (*nb && lp < &p[P_L2_SIZE]) { |
07f07b31 | 284 | if ((*index & (step - 1)) == 0 && *nb >= step) { |
9736e55b | 285 | lp->skip = 0; |
c19e8800 | 286 | lp->ptr = leaf; |
07f07b31 AK |
287 | *index += step; |
288 | *nb -= step; | |
2999097b | 289 | } else { |
53cb28cb | 290 | phys_page_set_level(map, lp, index, nb, leaf, level - 1); |
2999097b AK |
291 | } |
292 | ++lp; | |
f7bf5461 AK |
293 | } |
294 | } | |
295 | ||
ac1970fb | 296 | static void phys_page_set(AddressSpaceDispatch *d, |
a8170e5e | 297 | hwaddr index, hwaddr nb, |
2999097b | 298 | uint16_t leaf) |
f7bf5461 | 299 | { |
2999097b | 300 | /* Wildly overreserve - it doesn't matter much. */ |
53cb28cb | 301 | phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS); |
5cd2c5b6 | 302 | |
53cb28cb | 303 | phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1); |
92e873b9 FB |
304 | } |
305 | ||
b35ba30f MT |
306 | /* Compact a non leaf page entry. Simply detect that the entry has a single child, |
307 | * and update our entry so we can skip it and go directly to the destination. | |
308 | */ | |
efee678d | 309 | static void phys_page_compact(PhysPageEntry *lp, Node *nodes) |
b35ba30f MT |
310 | { |
311 | unsigned valid_ptr = P_L2_SIZE; | |
312 | int valid = 0; | |
313 | PhysPageEntry *p; | |
314 | int i; | |
315 | ||
316 | if (lp->ptr == PHYS_MAP_NODE_NIL) { | |
317 | return; | |
318 | } | |
319 | ||
320 | p = nodes[lp->ptr]; | |
321 | for (i = 0; i < P_L2_SIZE; i++) { | |
322 | if (p[i].ptr == PHYS_MAP_NODE_NIL) { | |
323 | continue; | |
324 | } | |
325 | ||
326 | valid_ptr = i; | |
327 | valid++; | |
328 | if (p[i].skip) { | |
efee678d | 329 | phys_page_compact(&p[i], nodes); |
b35ba30f MT |
330 | } |
331 | } | |
332 | ||
333 | /* We can only compress if there's only one child. */ | |
334 | if (valid != 1) { | |
335 | return; | |
336 | } | |
337 | ||
338 | assert(valid_ptr < P_L2_SIZE); | |
339 | ||
340 | /* Don't compress if it won't fit in the # of bits we have. */ | |
341 | if (lp->skip + p[valid_ptr].skip >= (1 << 3)) { | |
342 | return; | |
343 | } | |
344 | ||
345 | lp->ptr = p[valid_ptr].ptr; | |
346 | if (!p[valid_ptr].skip) { | |
347 | /* If our only child is a leaf, make this a leaf. */ | |
348 | /* By design, we should have made this node a leaf to begin with so we | |
349 | * should never reach here. | |
350 | * But since it's so simple to handle this, let's do it just in case we | |
351 | * change this rule. | |
352 | */ | |
353 | lp->skip = 0; | |
354 | } else { | |
355 | lp->skip += p[valid_ptr].skip; | |
356 | } | |
357 | } | |
358 | ||
8629d3fc | 359 | void address_space_dispatch_compact(AddressSpaceDispatch *d) |
b35ba30f | 360 | { |
b35ba30f | 361 | if (d->phys_map.skip) { |
efee678d | 362 | phys_page_compact(&d->phys_map, d->map.nodes); |
b35ba30f MT |
363 | } |
364 | } | |
365 | ||
29cb533d FZ |
366 | static inline bool section_covers_addr(const MemoryRegionSection *section, |
367 | hwaddr addr) | |
368 | { | |
369 | /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means | |
370 | * the section must cover the entire address space. | |
371 | */ | |
258dfaaa | 372 | return int128_gethi(section->size) || |
29cb533d | 373 | range_covers_byte(section->offset_within_address_space, |
258dfaaa | 374 | int128_getlo(section->size), addr); |
29cb533d FZ |
375 | } |
376 | ||
003a0cf2 | 377 | static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr) |
92e873b9 | 378 | { |
003a0cf2 PX |
379 | PhysPageEntry lp = d->phys_map, *p; |
380 | Node *nodes = d->map.nodes; | |
381 | MemoryRegionSection *sections = d->map.sections; | |
97115a8d | 382 | hwaddr index = addr >> TARGET_PAGE_BITS; |
31ab2b4a | 383 | int i; |
f1f6e3b8 | 384 | |
9736e55b | 385 | for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) { |
c19e8800 | 386 | if (lp.ptr == PHYS_MAP_NODE_NIL) { |
9affd6fc | 387 | return §ions[PHYS_SECTION_UNASSIGNED]; |
31ab2b4a | 388 | } |
9affd6fc | 389 | p = nodes[lp.ptr]; |
03f49957 | 390 | lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
5312bd8b | 391 | } |
b35ba30f | 392 | |
29cb533d | 393 | if (section_covers_addr(§ions[lp.ptr], addr)) { |
b35ba30f MT |
394 | return §ions[lp.ptr]; |
395 | } else { | |
396 | return §ions[PHYS_SECTION_UNASSIGNED]; | |
397 | } | |
f3705d53 AK |
398 | } |
399 | ||
e5548617 BS |
400 | bool memory_region_is_unassigned(MemoryRegion *mr) |
401 | { | |
2a8e7499 | 402 | return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device |
5b6dd868 | 403 | && mr != &io_mem_watch; |
fd6ce8f6 | 404 | } |
149f54b5 | 405 | |
79e2b9ae | 406 | /* Called from RCU critical section */ |
c7086b4a | 407 | static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d, |
90260c6c JK |
408 | hwaddr addr, |
409 | bool resolve_subpage) | |
9f029603 | 410 | { |
729633c2 | 411 | MemoryRegionSection *section = atomic_read(&d->mru_section); |
90260c6c | 412 | subpage_t *subpage; |
729633c2 | 413 | bool update; |
90260c6c | 414 | |
729633c2 FZ |
415 | if (section && section != &d->map.sections[PHYS_SECTION_UNASSIGNED] && |
416 | section_covers_addr(section, addr)) { | |
417 | update = false; | |
418 | } else { | |
003a0cf2 | 419 | section = phys_page_find(d, addr); |
729633c2 FZ |
420 | update = true; |
421 | } | |
90260c6c JK |
422 | if (resolve_subpage && section->mr->subpage) { |
423 | subpage = container_of(section->mr, subpage_t, iomem); | |
53cb28cb | 424 | section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]]; |
90260c6c | 425 | } |
729633c2 FZ |
426 | if (update) { |
427 | atomic_set(&d->mru_section, section); | |
428 | } | |
90260c6c | 429 | return section; |
9f029603 JK |
430 | } |
431 | ||
79e2b9ae | 432 | /* Called from RCU critical section */ |
90260c6c | 433 | static MemoryRegionSection * |
c7086b4a | 434 | address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat, |
90260c6c | 435 | hwaddr *plen, bool resolve_subpage) |
149f54b5 PB |
436 | { |
437 | MemoryRegionSection *section; | |
965eb2fc | 438 | MemoryRegion *mr; |
a87f3954 | 439 | Int128 diff; |
149f54b5 | 440 | |
c7086b4a | 441 | section = address_space_lookup_region(d, addr, resolve_subpage); |
149f54b5 PB |
442 | /* Compute offset within MemoryRegionSection */ |
443 | addr -= section->offset_within_address_space; | |
444 | ||
445 | /* Compute offset within MemoryRegion */ | |
446 | *xlat = addr + section->offset_within_region; | |
447 | ||
965eb2fc | 448 | mr = section->mr; |
b242e0e0 PB |
449 | |
450 | /* MMIO registers can be expected to perform full-width accesses based only | |
451 | * on their address, without considering adjacent registers that could | |
452 | * decode to completely different MemoryRegions. When such registers | |
453 | * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO | |
454 | * regions overlap wildly. For this reason we cannot clamp the accesses | |
455 | * here. | |
456 | * | |
457 | * If the length is small (as is the case for address_space_ldl/stl), | |
458 | * everything works fine. If the incoming length is large, however, | |
459 | * the caller really has to do the clamping through memory_access_size. | |
460 | */ | |
965eb2fc | 461 | if (memory_region_is_ram(mr)) { |
e4a511f8 | 462 | diff = int128_sub(section->size, int128_make64(addr)); |
965eb2fc PB |
463 | *plen = int128_get64(int128_min(diff, int128_make64(*plen))); |
464 | } | |
149f54b5 PB |
465 | return section; |
466 | } | |
90260c6c | 467 | |
41063e1e | 468 | /* Called from RCU critical section */ |
16620684 AK |
469 | static MemoryRegionSection flatview_do_translate(FlatView *fv, |
470 | hwaddr addr, | |
471 | hwaddr *xlat, | |
472 | hwaddr *plen, | |
473 | bool is_write, | |
474 | bool is_mmio, | |
475 | AddressSpace **target_as) | |
052c8fa9 | 476 | { |
a764040c | 477 | IOMMUTLBEntry iotlb; |
052c8fa9 | 478 | MemoryRegionSection *section; |
3df9d748 | 479 | IOMMUMemoryRegion *iommu_mr; |
1221a474 | 480 | IOMMUMemoryRegionClass *imrc; |
052c8fa9 JW |
481 | |
482 | for (;;) { | |
16620684 AK |
483 | section = address_space_translate_internal( |
484 | flatview_to_dispatch(fv), addr, &addr, | |
485 | plen, is_mmio); | |
052c8fa9 | 486 | |
3df9d748 AK |
487 | iommu_mr = memory_region_get_iommu(section->mr); |
488 | if (!iommu_mr) { | |
052c8fa9 JW |
489 | break; |
490 | } | |
1221a474 | 491 | imrc = memory_region_get_iommu_class_nocheck(iommu_mr); |
052c8fa9 | 492 | |
1221a474 AK |
493 | iotlb = imrc->translate(iommu_mr, addr, is_write ? |
494 | IOMMU_WO : IOMMU_RO); | |
a764040c PX |
495 | addr = ((iotlb.translated_addr & ~iotlb.addr_mask) |
496 | | (addr & iotlb.addr_mask)); | |
497 | *plen = MIN(*plen, (addr | iotlb.addr_mask) - addr + 1); | |
052c8fa9 | 498 | if (!(iotlb.perm & (1 << is_write))) { |
a764040c | 499 | goto translate_fail; |
052c8fa9 JW |
500 | } |
501 | ||
16620684 | 502 | fv = address_space_to_flatview(iotlb.target_as); |
e76bb18f | 503 | *target_as = iotlb.target_as; |
052c8fa9 JW |
504 | } |
505 | ||
a764040c PX |
506 | *xlat = addr; |
507 | ||
508 | return *section; | |
509 | ||
510 | translate_fail: | |
511 | return (MemoryRegionSection) { .mr = &io_mem_unassigned }; | |
052c8fa9 JW |
512 | } |
513 | ||
514 | /* Called from RCU critical section */ | |
a764040c PX |
515 | IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, |
516 | bool is_write) | |
90260c6c | 517 | { |
a764040c PX |
518 | MemoryRegionSection section; |
519 | hwaddr xlat, plen; | |
30951157 | 520 | |
a764040c PX |
521 | /* Try to get maximum page mask during translation. */ |
522 | plen = (hwaddr)-1; | |
30951157 | 523 | |
a764040c | 524 | /* This can never be MMIO. */ |
16620684 AK |
525 | section = flatview_do_translate(address_space_to_flatview(as), addr, |
526 | &xlat, &plen, is_write, false, &as); | |
30951157 | 527 | |
a764040c PX |
528 | /* Illegal translation */ |
529 | if (section.mr == &io_mem_unassigned) { | |
530 | goto iotlb_fail; | |
531 | } | |
30951157 | 532 | |
a764040c PX |
533 | /* Convert memory region offset into address space offset */ |
534 | xlat += section.offset_within_address_space - | |
535 | section.offset_within_region; | |
536 | ||
537 | if (plen == (hwaddr)-1) { | |
538 | /* | |
539 | * We use default page size here. Logically it only happens | |
540 | * for identity mappings. | |
541 | */ | |
542 | plen = TARGET_PAGE_SIZE; | |
30951157 AK |
543 | } |
544 | ||
a764040c PX |
545 | /* Convert to address mask */ |
546 | plen -= 1; | |
547 | ||
548 | return (IOMMUTLBEntry) { | |
e76bb18f | 549 | .target_as = as, |
a764040c PX |
550 | .iova = addr & ~plen, |
551 | .translated_addr = xlat & ~plen, | |
552 | .addr_mask = plen, | |
553 | /* IOTLBs are for DMAs, and DMA only allows on RAMs. */ | |
554 | .perm = IOMMU_RW, | |
555 | }; | |
556 | ||
557 | iotlb_fail: | |
558 | return (IOMMUTLBEntry) {0}; | |
559 | } | |
560 | ||
561 | /* Called from RCU critical section */ | |
16620684 AK |
562 | MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, |
563 | hwaddr *plen, bool is_write) | |
a764040c PX |
564 | { |
565 | MemoryRegion *mr; | |
566 | MemoryRegionSection section; | |
16620684 | 567 | AddressSpace *as = NULL; |
a764040c PX |
568 | |
569 | /* This can be MMIO, so setup MMIO bit. */ | |
16620684 | 570 | section = flatview_do_translate(fv, addr, xlat, plen, is_write, true, &as); |
a764040c PX |
571 | mr = section.mr; |
572 | ||
fe680d0d | 573 | if (xen_enabled() && memory_access_is_direct(mr, is_write)) { |
a87f3954 | 574 | hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr; |
23820dbf | 575 | *plen = MIN(page, *plen); |
a87f3954 PB |
576 | } |
577 | ||
30951157 | 578 | return mr; |
90260c6c JK |
579 | } |
580 | ||
79e2b9ae | 581 | /* Called from RCU critical section */ |
90260c6c | 582 | MemoryRegionSection * |
d7898cda | 583 | address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, |
9d82b5a7 | 584 | hwaddr *xlat, hwaddr *plen) |
90260c6c | 585 | { |
30951157 | 586 | MemoryRegionSection *section; |
f35e44e7 | 587 | AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch); |
d7898cda PM |
588 | |
589 | section = address_space_translate_internal(d, addr, xlat, plen, false); | |
30951157 | 590 | |
3df9d748 | 591 | assert(!memory_region_is_iommu(section->mr)); |
30951157 | 592 | return section; |
90260c6c | 593 | } |
5b6dd868 | 594 | #endif |
fd6ce8f6 | 595 | |
b170fce3 | 596 | #if !defined(CONFIG_USER_ONLY) |
5b6dd868 BS |
597 | |
598 | static int cpu_common_post_load(void *opaque, int version_id) | |
fd6ce8f6 | 599 | { |
259186a7 | 600 | CPUState *cpu = opaque; |
a513fe19 | 601 | |
5b6dd868 BS |
602 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
603 | version_id is increased. */ | |
259186a7 | 604 | cpu->interrupt_request &= ~0x01; |
d10eb08f | 605 | tlb_flush(cpu); |
5b6dd868 BS |
606 | |
607 | return 0; | |
a513fe19 | 608 | } |
7501267e | 609 | |
6c3bff0e PD |
610 | static int cpu_common_pre_load(void *opaque) |
611 | { | |
612 | CPUState *cpu = opaque; | |
613 | ||
adee6424 | 614 | cpu->exception_index = -1; |
6c3bff0e PD |
615 | |
616 | return 0; | |
617 | } | |
618 | ||
619 | static bool cpu_common_exception_index_needed(void *opaque) | |
620 | { | |
621 | CPUState *cpu = opaque; | |
622 | ||
adee6424 | 623 | return tcg_enabled() && cpu->exception_index != -1; |
6c3bff0e PD |
624 | } |
625 | ||
626 | static const VMStateDescription vmstate_cpu_common_exception_index = { | |
627 | .name = "cpu_common/exception_index", | |
628 | .version_id = 1, | |
629 | .minimum_version_id = 1, | |
5cd8cada | 630 | .needed = cpu_common_exception_index_needed, |
6c3bff0e PD |
631 | .fields = (VMStateField[]) { |
632 | VMSTATE_INT32(exception_index, CPUState), | |
633 | VMSTATE_END_OF_LIST() | |
634 | } | |
635 | }; | |
636 | ||
bac05aa9 AS |
637 | static bool cpu_common_crash_occurred_needed(void *opaque) |
638 | { | |
639 | CPUState *cpu = opaque; | |
640 | ||
641 | return cpu->crash_occurred; | |
642 | } | |
643 | ||
644 | static const VMStateDescription vmstate_cpu_common_crash_occurred = { | |
645 | .name = "cpu_common/crash_occurred", | |
646 | .version_id = 1, | |
647 | .minimum_version_id = 1, | |
648 | .needed = cpu_common_crash_occurred_needed, | |
649 | .fields = (VMStateField[]) { | |
650 | VMSTATE_BOOL(crash_occurred, CPUState), | |
651 | VMSTATE_END_OF_LIST() | |
652 | } | |
653 | }; | |
654 | ||
1a1562f5 | 655 | const VMStateDescription vmstate_cpu_common = { |
5b6dd868 BS |
656 | .name = "cpu_common", |
657 | .version_id = 1, | |
658 | .minimum_version_id = 1, | |
6c3bff0e | 659 | .pre_load = cpu_common_pre_load, |
5b6dd868 | 660 | .post_load = cpu_common_post_load, |
35d08458 | 661 | .fields = (VMStateField[]) { |
259186a7 AF |
662 | VMSTATE_UINT32(halted, CPUState), |
663 | VMSTATE_UINT32(interrupt_request, CPUState), | |
5b6dd868 | 664 | VMSTATE_END_OF_LIST() |
6c3bff0e | 665 | }, |
5cd8cada JQ |
666 | .subsections = (const VMStateDescription*[]) { |
667 | &vmstate_cpu_common_exception_index, | |
bac05aa9 | 668 | &vmstate_cpu_common_crash_occurred, |
5cd8cada | 669 | NULL |
5b6dd868 BS |
670 | } |
671 | }; | |
1a1562f5 | 672 | |
5b6dd868 | 673 | #endif |
ea041c0e | 674 | |
38d8f5c8 | 675 | CPUState *qemu_get_cpu(int index) |
ea041c0e | 676 | { |
bdc44640 | 677 | CPUState *cpu; |
ea041c0e | 678 | |
bdc44640 | 679 | CPU_FOREACH(cpu) { |
55e5c285 | 680 | if (cpu->cpu_index == index) { |
bdc44640 | 681 | return cpu; |
55e5c285 | 682 | } |
ea041c0e | 683 | } |
5b6dd868 | 684 | |
bdc44640 | 685 | return NULL; |
ea041c0e FB |
686 | } |
687 | ||
09daed84 | 688 | #if !defined(CONFIG_USER_ONLY) |
56943e8c | 689 | void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx) |
09daed84 | 690 | { |
12ebc9a7 PM |
691 | CPUAddressSpace *newas; |
692 | ||
693 | /* Target code should have set num_ases before calling us */ | |
694 | assert(asidx < cpu->num_ases); | |
695 | ||
56943e8c PM |
696 | if (asidx == 0) { |
697 | /* address space 0 gets the convenience alias */ | |
698 | cpu->as = as; | |
699 | } | |
700 | ||
12ebc9a7 PM |
701 | /* KVM cannot currently support multiple address spaces. */ |
702 | assert(asidx == 0 || !kvm_enabled()); | |
09daed84 | 703 | |
12ebc9a7 PM |
704 | if (!cpu->cpu_ases) { |
705 | cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases); | |
09daed84 | 706 | } |
32857f4d | 707 | |
12ebc9a7 PM |
708 | newas = &cpu->cpu_ases[asidx]; |
709 | newas->cpu = cpu; | |
710 | newas->as = as; | |
56943e8c | 711 | if (tcg_enabled()) { |
12ebc9a7 PM |
712 | newas->tcg_as_listener.commit = tcg_commit; |
713 | memory_listener_register(&newas->tcg_as_listener, as); | |
56943e8c | 714 | } |
09daed84 | 715 | } |
651a5bc0 PM |
716 | |
717 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx) | |
718 | { | |
719 | /* Return the AddressSpace corresponding to the specified index */ | |
720 | return cpu->cpu_ases[asidx].as; | |
721 | } | |
09daed84 EI |
722 | #endif |
723 | ||
7bbc124e | 724 | void cpu_exec_unrealizefn(CPUState *cpu) |
1c59eb39 | 725 | { |
9dfeca7c BR |
726 | CPUClass *cc = CPU_GET_CLASS(cpu); |
727 | ||
267f685b | 728 | cpu_list_remove(cpu); |
9dfeca7c BR |
729 | |
730 | if (cc->vmsd != NULL) { | |
731 | vmstate_unregister(NULL, cc->vmsd, cpu); | |
732 | } | |
733 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { | |
734 | vmstate_unregister(NULL, &vmstate_cpu_common, cpu); | |
735 | } | |
1c59eb39 BR |
736 | } |
737 | ||
c7e002c5 FZ |
738 | Property cpu_common_props[] = { |
739 | #ifndef CONFIG_USER_ONLY | |
740 | /* Create a memory property for softmmu CPU object, | |
741 | * so users can wire up its memory. (This can't go in qom/cpu.c | |
742 | * because that file is compiled only once for both user-mode | |
743 | * and system builds.) The default if no link is set up is to use | |
744 | * the system address space. | |
745 | */ | |
746 | DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, | |
747 | MemoryRegion *), | |
748 | #endif | |
749 | DEFINE_PROP_END_OF_LIST(), | |
750 | }; | |
751 | ||
39e329e3 | 752 | void cpu_exec_initfn(CPUState *cpu) |
ea041c0e | 753 | { |
56943e8c | 754 | cpu->as = NULL; |
12ebc9a7 | 755 | cpu->num_ases = 0; |
56943e8c | 756 | |
291135b5 | 757 | #ifndef CONFIG_USER_ONLY |
291135b5 | 758 | cpu->thread_id = qemu_get_thread_id(); |
6731d864 PC |
759 | cpu->memory = system_memory; |
760 | object_ref(OBJECT(cpu->memory)); | |
291135b5 | 761 | #endif |
39e329e3 LV |
762 | } |
763 | ||
ce5b1bbf | 764 | void cpu_exec_realizefn(CPUState *cpu, Error **errp) |
39e329e3 LV |
765 | { |
766 | CPUClass *cc ATTRIBUTE_UNUSED = CPU_GET_CLASS(cpu); | |
291135b5 | 767 | |
267f685b | 768 | cpu_list_add(cpu); |
1bc7e522 IM |
769 | |
770 | #ifndef CONFIG_USER_ONLY | |
e0d47944 | 771 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { |
741da0d3 | 772 | vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); |
e0d47944 | 773 | } |
b170fce3 | 774 | if (cc->vmsd != NULL) { |
741da0d3 | 775 | vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); |
b170fce3 | 776 | } |
741da0d3 | 777 | #endif |
ea041c0e FB |
778 | } |
779 | ||
406bc339 | 780 | #if defined(CONFIG_USER_ONLY) |
00b941e5 | 781 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) |
1e7855a5 | 782 | { |
406bc339 PK |
783 | mmap_lock(); |
784 | tb_lock(); | |
785 | tb_invalidate_phys_page_range(pc, pc + 1, 0); | |
786 | tb_unlock(); | |
787 | mmap_unlock(); | |
788 | } | |
789 | #else | |
790 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) | |
791 | { | |
792 | MemTxAttrs attrs; | |
793 | hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs); | |
794 | int asidx = cpu_asidx_from_attrs(cpu, attrs); | |
795 | if (phys != -1) { | |
796 | /* Locks grabbed by tb_invalidate_phys_addr */ | |
797 | tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as, | |
798 | phys | (pc & ~TARGET_PAGE_MASK)); | |
799 | } | |
1e7855a5 | 800 | } |
406bc339 | 801 | #endif |
d720b93d | 802 | |
c527ee8f | 803 | #if defined(CONFIG_USER_ONLY) |
75a34036 | 804 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) |
c527ee8f PB |
805 | |
806 | { | |
807 | } | |
808 | ||
3ee887e8 PM |
809 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, |
810 | int flags) | |
811 | { | |
812 | return -ENOSYS; | |
813 | } | |
814 | ||
815 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) | |
816 | { | |
817 | } | |
818 | ||
75a34036 | 819 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
c527ee8f PB |
820 | int flags, CPUWatchpoint **watchpoint) |
821 | { | |
822 | return -ENOSYS; | |
823 | } | |
824 | #else | |
6658ffb8 | 825 | /* Add a watchpoint. */ |
75a34036 | 826 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
a1d1bb31 | 827 | int flags, CPUWatchpoint **watchpoint) |
6658ffb8 | 828 | { |
c0ce998e | 829 | CPUWatchpoint *wp; |
6658ffb8 | 830 | |
05068c0d | 831 | /* forbid ranges which are empty or run off the end of the address space */ |
07e2863d | 832 | if (len == 0 || (addr + len - 1) < addr) { |
75a34036 AF |
833 | error_report("tried to set invalid watchpoint at %" |
834 | VADDR_PRIx ", len=%" VADDR_PRIu, addr, len); | |
b4051334 AL |
835 | return -EINVAL; |
836 | } | |
7267c094 | 837 | wp = g_malloc(sizeof(*wp)); |
a1d1bb31 AL |
838 | |
839 | wp->vaddr = addr; | |
05068c0d | 840 | wp->len = len; |
a1d1bb31 AL |
841 | wp->flags = flags; |
842 | ||
2dc9f411 | 843 | /* keep all GDB-injected watchpoints in front */ |
ff4700b0 AF |
844 | if (flags & BP_GDB) { |
845 | QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry); | |
846 | } else { | |
847 | QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); | |
848 | } | |
6658ffb8 | 849 | |
31b030d4 | 850 | tlb_flush_page(cpu, addr); |
a1d1bb31 AL |
851 | |
852 | if (watchpoint) | |
853 | *watchpoint = wp; | |
854 | return 0; | |
6658ffb8 PB |
855 | } |
856 | ||
a1d1bb31 | 857 | /* Remove a specific watchpoint. */ |
75a34036 | 858 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, |
a1d1bb31 | 859 | int flags) |
6658ffb8 | 860 | { |
a1d1bb31 | 861 | CPUWatchpoint *wp; |
6658ffb8 | 862 | |
ff4700b0 | 863 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d | 864 | if (addr == wp->vaddr && len == wp->len |
6e140f28 | 865 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
75a34036 | 866 | cpu_watchpoint_remove_by_ref(cpu, wp); |
6658ffb8 PB |
867 | return 0; |
868 | } | |
869 | } | |
a1d1bb31 | 870 | return -ENOENT; |
6658ffb8 PB |
871 | } |
872 | ||
a1d1bb31 | 873 | /* Remove a specific watchpoint by reference. */ |
75a34036 | 874 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) |
a1d1bb31 | 875 | { |
ff4700b0 | 876 | QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); |
7d03f82f | 877 | |
31b030d4 | 878 | tlb_flush_page(cpu, watchpoint->vaddr); |
a1d1bb31 | 879 | |
7267c094 | 880 | g_free(watchpoint); |
a1d1bb31 AL |
881 | } |
882 | ||
883 | /* Remove all matching watchpoints. */ | |
75a34036 | 884 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) |
a1d1bb31 | 885 | { |
c0ce998e | 886 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 887 | |
ff4700b0 | 888 | QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { |
75a34036 AF |
889 | if (wp->flags & mask) { |
890 | cpu_watchpoint_remove_by_ref(cpu, wp); | |
891 | } | |
c0ce998e | 892 | } |
7d03f82f | 893 | } |
05068c0d PM |
894 | |
895 | /* Return true if this watchpoint address matches the specified | |
896 | * access (ie the address range covered by the watchpoint overlaps | |
897 | * partially or completely with the address range covered by the | |
898 | * access). | |
899 | */ | |
900 | static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp, | |
901 | vaddr addr, | |
902 | vaddr len) | |
903 | { | |
904 | /* We know the lengths are non-zero, but a little caution is | |
905 | * required to avoid errors in the case where the range ends | |
906 | * exactly at the top of the address space and so addr + len | |
907 | * wraps round to zero. | |
908 | */ | |
909 | vaddr wpend = wp->vaddr + wp->len - 1; | |
910 | vaddr addrend = addr + len - 1; | |
911 | ||
912 | return !(addr > wpend || wp->vaddr > addrend); | |
913 | } | |
914 | ||
c527ee8f | 915 | #endif |
7d03f82f | 916 | |
a1d1bb31 | 917 | /* Add a breakpoint. */ |
b3310ab3 | 918 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, |
a1d1bb31 | 919 | CPUBreakpoint **breakpoint) |
4c3a88a2 | 920 | { |
c0ce998e | 921 | CPUBreakpoint *bp; |
3b46e624 | 922 | |
7267c094 | 923 | bp = g_malloc(sizeof(*bp)); |
4c3a88a2 | 924 | |
a1d1bb31 AL |
925 | bp->pc = pc; |
926 | bp->flags = flags; | |
927 | ||
2dc9f411 | 928 | /* keep all GDB-injected breakpoints in front */ |
00b941e5 | 929 | if (flags & BP_GDB) { |
f0c3c505 | 930 | QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry); |
00b941e5 | 931 | } else { |
f0c3c505 | 932 | QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); |
00b941e5 | 933 | } |
3b46e624 | 934 | |
f0c3c505 | 935 | breakpoint_invalidate(cpu, pc); |
a1d1bb31 | 936 | |
00b941e5 | 937 | if (breakpoint) { |
a1d1bb31 | 938 | *breakpoint = bp; |
00b941e5 | 939 | } |
4c3a88a2 | 940 | return 0; |
4c3a88a2 FB |
941 | } |
942 | ||
a1d1bb31 | 943 | /* Remove a specific breakpoint. */ |
b3310ab3 | 944 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) |
a1d1bb31 | 945 | { |
a1d1bb31 AL |
946 | CPUBreakpoint *bp; |
947 | ||
f0c3c505 | 948 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { |
a1d1bb31 | 949 | if (bp->pc == pc && bp->flags == flags) { |
b3310ab3 | 950 | cpu_breakpoint_remove_by_ref(cpu, bp); |
a1d1bb31 AL |
951 | return 0; |
952 | } | |
7d03f82f | 953 | } |
a1d1bb31 | 954 | return -ENOENT; |
7d03f82f EI |
955 | } |
956 | ||
a1d1bb31 | 957 | /* Remove a specific breakpoint by reference. */ |
b3310ab3 | 958 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint) |
4c3a88a2 | 959 | { |
f0c3c505 AF |
960 | QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry); |
961 | ||
962 | breakpoint_invalidate(cpu, breakpoint->pc); | |
a1d1bb31 | 963 | |
7267c094 | 964 | g_free(breakpoint); |
a1d1bb31 AL |
965 | } |
966 | ||
967 | /* Remove all matching breakpoints. */ | |
b3310ab3 | 968 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask) |
a1d1bb31 | 969 | { |
c0ce998e | 970 | CPUBreakpoint *bp, *next; |
a1d1bb31 | 971 | |
f0c3c505 | 972 | QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { |
b3310ab3 AF |
973 | if (bp->flags & mask) { |
974 | cpu_breakpoint_remove_by_ref(cpu, bp); | |
975 | } | |
c0ce998e | 976 | } |
4c3a88a2 FB |
977 | } |
978 | ||
c33a346e FB |
979 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
980 | CPU loop after each instruction */ | |
3825b28f | 981 | void cpu_single_step(CPUState *cpu, int enabled) |
c33a346e | 982 | { |
ed2803da AF |
983 | if (cpu->singlestep_enabled != enabled) { |
984 | cpu->singlestep_enabled = enabled; | |
985 | if (kvm_enabled()) { | |
38e478ec | 986 | kvm_update_guest_debug(cpu, 0); |
ed2803da | 987 | } else { |
ccbb4d44 | 988 | /* must flush all the translated code to avoid inconsistencies */ |
e22a25c9 | 989 | /* XXX: only flush what is necessary */ |
bbd77c18 | 990 | tb_flush(cpu); |
e22a25c9 | 991 | } |
c33a346e | 992 | } |
c33a346e FB |
993 | } |
994 | ||
a47dddd7 | 995 | void cpu_abort(CPUState *cpu, const char *fmt, ...) |
7501267e FB |
996 | { |
997 | va_list ap; | |
493ae1f0 | 998 | va_list ap2; |
7501267e FB |
999 | |
1000 | va_start(ap, fmt); | |
493ae1f0 | 1001 | va_copy(ap2, ap); |
7501267e FB |
1002 | fprintf(stderr, "qemu: fatal: "); |
1003 | vfprintf(stderr, fmt, ap); | |
1004 | fprintf(stderr, "\n"); | |
878096ee | 1005 | cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
013a2942 | 1006 | if (qemu_log_separate()) { |
1ee73216 | 1007 | qemu_log_lock(); |
93fcfe39 AL |
1008 | qemu_log("qemu: fatal: "); |
1009 | qemu_log_vprintf(fmt, ap2); | |
1010 | qemu_log("\n"); | |
a0762859 | 1011 | log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
31b1a7b4 | 1012 | qemu_log_flush(); |
1ee73216 | 1013 | qemu_log_unlock(); |
93fcfe39 | 1014 | qemu_log_close(); |
924edcae | 1015 | } |
493ae1f0 | 1016 | va_end(ap2); |
f9373291 | 1017 | va_end(ap); |
7615936e | 1018 | replay_finish(); |
fd052bf6 RV |
1019 | #if defined(CONFIG_USER_ONLY) |
1020 | { | |
1021 | struct sigaction act; | |
1022 | sigfillset(&act.sa_mask); | |
1023 | act.sa_handler = SIG_DFL; | |
1024 | sigaction(SIGABRT, &act, NULL); | |
1025 | } | |
1026 | #endif | |
7501267e FB |
1027 | abort(); |
1028 | } | |
1029 | ||
0124311e | 1030 | #if !defined(CONFIG_USER_ONLY) |
0dc3f44a | 1031 | /* Called from RCU critical section */ |
041603fe PB |
1032 | static RAMBlock *qemu_get_ram_block(ram_addr_t addr) |
1033 | { | |
1034 | RAMBlock *block; | |
1035 | ||
43771539 | 1036 | block = atomic_rcu_read(&ram_list.mru_block); |
9b8424d5 | 1037 | if (block && addr - block->offset < block->max_length) { |
68851b98 | 1038 | return block; |
041603fe | 1039 | } |
99e15582 | 1040 | RAMBLOCK_FOREACH(block) { |
9b8424d5 | 1041 | if (addr - block->offset < block->max_length) { |
041603fe PB |
1042 | goto found; |
1043 | } | |
1044 | } | |
1045 | ||
1046 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
1047 | abort(); | |
1048 | ||
1049 | found: | |
43771539 PB |
1050 | /* It is safe to write mru_block outside the iothread lock. This |
1051 | * is what happens: | |
1052 | * | |
1053 | * mru_block = xxx | |
1054 | * rcu_read_unlock() | |
1055 | * xxx removed from list | |
1056 | * rcu_read_lock() | |
1057 | * read mru_block | |
1058 | * mru_block = NULL; | |
1059 | * call_rcu(reclaim_ramblock, xxx); | |
1060 | * rcu_read_unlock() | |
1061 | * | |
1062 | * atomic_rcu_set is not needed here. The block was already published | |
1063 | * when it was placed into the list. Here we're just making an extra | |
1064 | * copy of the pointer. | |
1065 | */ | |
041603fe PB |
1066 | ram_list.mru_block = block; |
1067 | return block; | |
1068 | } | |
1069 | ||
a2f4d5be | 1070 | static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length) |
d24981d3 | 1071 | { |
9a13565d | 1072 | CPUState *cpu; |
041603fe | 1073 | ram_addr_t start1; |
a2f4d5be JQ |
1074 | RAMBlock *block; |
1075 | ram_addr_t end; | |
1076 | ||
1077 | end = TARGET_PAGE_ALIGN(start + length); | |
1078 | start &= TARGET_PAGE_MASK; | |
d24981d3 | 1079 | |
0dc3f44a | 1080 | rcu_read_lock(); |
041603fe PB |
1081 | block = qemu_get_ram_block(start); |
1082 | assert(block == qemu_get_ram_block(end - 1)); | |
1240be24 | 1083 | start1 = (uintptr_t)ramblock_ptr(block, start - block->offset); |
9a13565d PC |
1084 | CPU_FOREACH(cpu) { |
1085 | tlb_reset_dirty(cpu, start1, length); | |
1086 | } | |
0dc3f44a | 1087 | rcu_read_unlock(); |
d24981d3 JQ |
1088 | } |
1089 | ||
5579c7f3 | 1090 | /* Note: start and end must be within the same ram block. */ |
03eebc9e SH |
1091 | bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start, |
1092 | ram_addr_t length, | |
1093 | unsigned client) | |
1ccde1cb | 1094 | { |
5b82b703 | 1095 | DirtyMemoryBlocks *blocks; |
03eebc9e | 1096 | unsigned long end, page; |
5b82b703 | 1097 | bool dirty = false; |
03eebc9e SH |
1098 | |
1099 | if (length == 0) { | |
1100 | return false; | |
1101 | } | |
f23db169 | 1102 | |
03eebc9e SH |
1103 | end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; |
1104 | page = start >> TARGET_PAGE_BITS; | |
5b82b703 SH |
1105 | |
1106 | rcu_read_lock(); | |
1107 | ||
1108 | blocks = atomic_rcu_read(&ram_list.dirty_memory[client]); | |
1109 | ||
1110 | while (page < end) { | |
1111 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
1112 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
1113 | unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset); | |
1114 | ||
1115 | dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx], | |
1116 | offset, num); | |
1117 | page += num; | |
1118 | } | |
1119 | ||
1120 | rcu_read_unlock(); | |
03eebc9e SH |
1121 | |
1122 | if (dirty && tcg_enabled()) { | |
a2f4d5be | 1123 | tlb_reset_dirty_range_all(start, length); |
5579c7f3 | 1124 | } |
03eebc9e SH |
1125 | |
1126 | return dirty; | |
1ccde1cb FB |
1127 | } |
1128 | ||
8deaf12c GH |
1129 | DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty |
1130 | (ram_addr_t start, ram_addr_t length, unsigned client) | |
1131 | { | |
1132 | DirtyMemoryBlocks *blocks; | |
1133 | unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL); | |
1134 | ram_addr_t first = QEMU_ALIGN_DOWN(start, align); | |
1135 | ram_addr_t last = QEMU_ALIGN_UP(start + length, align); | |
1136 | DirtyBitmapSnapshot *snap; | |
1137 | unsigned long page, end, dest; | |
1138 | ||
1139 | snap = g_malloc0(sizeof(*snap) + | |
1140 | ((last - first) >> (TARGET_PAGE_BITS + 3))); | |
1141 | snap->start = first; | |
1142 | snap->end = last; | |
1143 | ||
1144 | page = first >> TARGET_PAGE_BITS; | |
1145 | end = last >> TARGET_PAGE_BITS; | |
1146 | dest = 0; | |
1147 | ||
1148 | rcu_read_lock(); | |
1149 | ||
1150 | blocks = atomic_rcu_read(&ram_list.dirty_memory[client]); | |
1151 | ||
1152 | while (page < end) { | |
1153 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
1154 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
1155 | unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset); | |
1156 | ||
1157 | assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL))); | |
1158 | assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL))); | |
1159 | offset >>= BITS_PER_LEVEL; | |
1160 | ||
1161 | bitmap_copy_and_clear_atomic(snap->dirty + dest, | |
1162 | blocks->blocks[idx] + offset, | |
1163 | num); | |
1164 | page += num; | |
1165 | dest += num >> BITS_PER_LEVEL; | |
1166 | } | |
1167 | ||
1168 | rcu_read_unlock(); | |
1169 | ||
1170 | if (tcg_enabled()) { | |
1171 | tlb_reset_dirty_range_all(start, length); | |
1172 | } | |
1173 | ||
1174 | return snap; | |
1175 | } | |
1176 | ||
1177 | bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap, | |
1178 | ram_addr_t start, | |
1179 | ram_addr_t length) | |
1180 | { | |
1181 | unsigned long page, end; | |
1182 | ||
1183 | assert(start >= snap->start); | |
1184 | assert(start + length <= snap->end); | |
1185 | ||
1186 | end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS; | |
1187 | page = (start - snap->start) >> TARGET_PAGE_BITS; | |
1188 | ||
1189 | while (page < end) { | |
1190 | if (test_bit(page, snap->dirty)) { | |
1191 | return true; | |
1192 | } | |
1193 | page++; | |
1194 | } | |
1195 | return false; | |
1196 | } | |
1197 | ||
79e2b9ae | 1198 | /* Called from RCU critical section */ |
bb0e627a | 1199 | hwaddr memory_region_section_get_iotlb(CPUState *cpu, |
149f54b5 PB |
1200 | MemoryRegionSection *section, |
1201 | target_ulong vaddr, | |
1202 | hwaddr paddr, hwaddr xlat, | |
1203 | int prot, | |
1204 | target_ulong *address) | |
e5548617 | 1205 | { |
a8170e5e | 1206 | hwaddr iotlb; |
e5548617 BS |
1207 | CPUWatchpoint *wp; |
1208 | ||
cc5bea60 | 1209 | if (memory_region_is_ram(section->mr)) { |
e5548617 | 1210 | /* Normal RAM. */ |
e4e69794 | 1211 | iotlb = memory_region_get_ram_addr(section->mr) + xlat; |
e5548617 | 1212 | if (!section->readonly) { |
b41aac4f | 1213 | iotlb |= PHYS_SECTION_NOTDIRTY; |
e5548617 | 1214 | } else { |
b41aac4f | 1215 | iotlb |= PHYS_SECTION_ROM; |
e5548617 BS |
1216 | } |
1217 | } else { | |
0b8e2c10 PM |
1218 | AddressSpaceDispatch *d; |
1219 | ||
16620684 | 1220 | d = flatview_to_dispatch(section->fv); |
0b8e2c10 | 1221 | iotlb = section - d->map.sections; |
149f54b5 | 1222 | iotlb += xlat; |
e5548617 BS |
1223 | } |
1224 | ||
1225 | /* Make accesses to pages with watchpoints go via the | |
1226 | watchpoint trap routines. */ | |
ff4700b0 | 1227 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d | 1228 | if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) { |
e5548617 BS |
1229 | /* Avoid trapping reads of pages with a write breakpoint. */ |
1230 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { | |
b41aac4f | 1231 | iotlb = PHYS_SECTION_WATCH + paddr; |
e5548617 BS |
1232 | *address |= TLB_MMIO; |
1233 | break; | |
1234 | } | |
1235 | } | |
1236 | } | |
1237 | ||
1238 | return iotlb; | |
1239 | } | |
9fa3e853 FB |
1240 | #endif /* defined(CONFIG_USER_ONLY) */ |
1241 | ||
e2eef170 | 1242 | #if !defined(CONFIG_USER_ONLY) |
8da3ff18 | 1243 | |
c227f099 | 1244 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
5312bd8b | 1245 | uint16_t section); |
16620684 | 1246 | static subpage_t *subpage_init(FlatView *fv, hwaddr base); |
54688b1e | 1247 | |
a2b257d6 IM |
1248 | static void *(*phys_mem_alloc)(size_t size, uint64_t *align) = |
1249 | qemu_anon_ram_alloc; | |
91138037 MA |
1250 | |
1251 | /* | |
1252 | * Set a custom physical guest memory alloator. | |
1253 | * Accelerators with unusual needs may need this. Hopefully, we can | |
1254 | * get rid of it eventually. | |
1255 | */ | |
a2b257d6 | 1256 | void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align)) |
91138037 MA |
1257 | { |
1258 | phys_mem_alloc = alloc; | |
1259 | } | |
1260 | ||
53cb28cb MA |
1261 | static uint16_t phys_section_add(PhysPageMap *map, |
1262 | MemoryRegionSection *section) | |
5312bd8b | 1263 | { |
68f3f65b PB |
1264 | /* The physical section number is ORed with a page-aligned |
1265 | * pointer to produce the iotlb entries. Thus it should | |
1266 | * never overflow into the page-aligned value. | |
1267 | */ | |
53cb28cb | 1268 | assert(map->sections_nb < TARGET_PAGE_SIZE); |
68f3f65b | 1269 | |
53cb28cb MA |
1270 | if (map->sections_nb == map->sections_nb_alloc) { |
1271 | map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16); | |
1272 | map->sections = g_renew(MemoryRegionSection, map->sections, | |
1273 | map->sections_nb_alloc); | |
5312bd8b | 1274 | } |
53cb28cb | 1275 | map->sections[map->sections_nb] = *section; |
dfde4e6e | 1276 | memory_region_ref(section->mr); |
53cb28cb | 1277 | return map->sections_nb++; |
5312bd8b AK |
1278 | } |
1279 | ||
058bc4b5 PB |
1280 | static void phys_section_destroy(MemoryRegion *mr) |
1281 | { | |
55b4e80b DS |
1282 | bool have_sub_page = mr->subpage; |
1283 | ||
dfde4e6e PB |
1284 | memory_region_unref(mr); |
1285 | ||
55b4e80b | 1286 | if (have_sub_page) { |
058bc4b5 | 1287 | subpage_t *subpage = container_of(mr, subpage_t, iomem); |
b4fefef9 | 1288 | object_unref(OBJECT(&subpage->iomem)); |
058bc4b5 PB |
1289 | g_free(subpage); |
1290 | } | |
1291 | } | |
1292 | ||
6092666e | 1293 | static void phys_sections_free(PhysPageMap *map) |
5312bd8b | 1294 | { |
9affd6fc PB |
1295 | while (map->sections_nb > 0) { |
1296 | MemoryRegionSection *section = &map->sections[--map->sections_nb]; | |
058bc4b5 PB |
1297 | phys_section_destroy(section->mr); |
1298 | } | |
9affd6fc PB |
1299 | g_free(map->sections); |
1300 | g_free(map->nodes); | |
5312bd8b AK |
1301 | } |
1302 | ||
9950322a | 1303 | static void register_subpage(FlatView *fv, MemoryRegionSection *section) |
0f0cb164 | 1304 | { |
9950322a | 1305 | AddressSpaceDispatch *d = flatview_to_dispatch(fv); |
0f0cb164 | 1306 | subpage_t *subpage; |
a8170e5e | 1307 | hwaddr base = section->offset_within_address_space |
0f0cb164 | 1308 | & TARGET_PAGE_MASK; |
003a0cf2 | 1309 | MemoryRegionSection *existing = phys_page_find(d, base); |
0f0cb164 AK |
1310 | MemoryRegionSection subsection = { |
1311 | .offset_within_address_space = base, | |
052e87b0 | 1312 | .size = int128_make64(TARGET_PAGE_SIZE), |
0f0cb164 | 1313 | }; |
a8170e5e | 1314 | hwaddr start, end; |
0f0cb164 | 1315 | |
f3705d53 | 1316 | assert(existing->mr->subpage || existing->mr == &io_mem_unassigned); |
0f0cb164 | 1317 | |
f3705d53 | 1318 | if (!(existing->mr->subpage)) { |
16620684 AK |
1319 | subpage = subpage_init(fv, base); |
1320 | subsection.fv = fv; | |
0f0cb164 | 1321 | subsection.mr = &subpage->iomem; |
ac1970fb | 1322 | phys_page_set(d, base >> TARGET_PAGE_BITS, 1, |
53cb28cb | 1323 | phys_section_add(&d->map, &subsection)); |
0f0cb164 | 1324 | } else { |
f3705d53 | 1325 | subpage = container_of(existing->mr, subpage_t, iomem); |
0f0cb164 AK |
1326 | } |
1327 | start = section->offset_within_address_space & ~TARGET_PAGE_MASK; | |
052e87b0 | 1328 | end = start + int128_get64(section->size) - 1; |
53cb28cb MA |
1329 | subpage_register(subpage, start, end, |
1330 | phys_section_add(&d->map, section)); | |
0f0cb164 AK |
1331 | } |
1332 | ||
1333 | ||
9950322a | 1334 | static void register_multipage(FlatView *fv, |
052e87b0 | 1335 | MemoryRegionSection *section) |
33417e70 | 1336 | { |
9950322a | 1337 | AddressSpaceDispatch *d = flatview_to_dispatch(fv); |
a8170e5e | 1338 | hwaddr start_addr = section->offset_within_address_space; |
53cb28cb | 1339 | uint16_t section_index = phys_section_add(&d->map, section); |
052e87b0 PB |
1340 | uint64_t num_pages = int128_get64(int128_rshift(section->size, |
1341 | TARGET_PAGE_BITS)); | |
dd81124b | 1342 | |
733d5ef5 PB |
1343 | assert(num_pages); |
1344 | phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index); | |
33417e70 FB |
1345 | } |
1346 | ||
8629d3fc | 1347 | void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section) |
0f0cb164 | 1348 | { |
99b9cc06 | 1349 | MemoryRegionSection now = *section, remain = *section; |
052e87b0 | 1350 | Int128 page_size = int128_make64(TARGET_PAGE_SIZE); |
0f0cb164 | 1351 | |
733d5ef5 PB |
1352 | if (now.offset_within_address_space & ~TARGET_PAGE_MASK) { |
1353 | uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space) | |
1354 | - now.offset_within_address_space; | |
1355 | ||
052e87b0 | 1356 | now.size = int128_min(int128_make64(left), now.size); |
9950322a | 1357 | register_subpage(fv, &now); |
733d5ef5 | 1358 | } else { |
052e87b0 | 1359 | now.size = int128_zero(); |
733d5ef5 | 1360 | } |
052e87b0 PB |
1361 | while (int128_ne(remain.size, now.size)) { |
1362 | remain.size = int128_sub(remain.size, now.size); | |
1363 | remain.offset_within_address_space += int128_get64(now.size); | |
1364 | remain.offset_within_region += int128_get64(now.size); | |
69b67646 | 1365 | now = remain; |
052e87b0 | 1366 | if (int128_lt(remain.size, page_size)) { |
9950322a | 1367 | register_subpage(fv, &now); |
88266249 | 1368 | } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) { |
052e87b0 | 1369 | now.size = page_size; |
9950322a | 1370 | register_subpage(fv, &now); |
69b67646 | 1371 | } else { |
052e87b0 | 1372 | now.size = int128_and(now.size, int128_neg(page_size)); |
9950322a | 1373 | register_multipage(fv, &now); |
69b67646 | 1374 | } |
0f0cb164 AK |
1375 | } |
1376 | } | |
1377 | ||
62a2744c SY |
1378 | void qemu_flush_coalesced_mmio_buffer(void) |
1379 | { | |
1380 | if (kvm_enabled()) | |
1381 | kvm_flush_coalesced_mmio_buffer(); | |
1382 | } | |
1383 | ||
b2a8658e UD |
1384 | void qemu_mutex_lock_ramlist(void) |
1385 | { | |
1386 | qemu_mutex_lock(&ram_list.mutex); | |
1387 | } | |
1388 | ||
1389 | void qemu_mutex_unlock_ramlist(void) | |
1390 | { | |
1391 | qemu_mutex_unlock(&ram_list.mutex); | |
1392 | } | |
1393 | ||
be9b23c4 PX |
1394 | void ram_block_dump(Monitor *mon) |
1395 | { | |
1396 | RAMBlock *block; | |
1397 | char *psize; | |
1398 | ||
1399 | rcu_read_lock(); | |
1400 | monitor_printf(mon, "%24s %8s %18s %18s %18s\n", | |
1401 | "Block Name", "PSize", "Offset", "Used", "Total"); | |
1402 | RAMBLOCK_FOREACH(block) { | |
1403 | psize = size_to_str(block->page_size); | |
1404 | monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64 | |
1405 | " 0x%016" PRIx64 "\n", block->idstr, psize, | |
1406 | (uint64_t)block->offset, | |
1407 | (uint64_t)block->used_length, | |
1408 | (uint64_t)block->max_length); | |
1409 | g_free(psize); | |
1410 | } | |
1411 | rcu_read_unlock(); | |
1412 | } | |
1413 | ||
9c607668 AK |
1414 | #ifdef __linux__ |
1415 | /* | |
1416 | * FIXME TOCTTOU: this iterates over memory backends' mem-path, which | |
1417 | * may or may not name the same files / on the same filesystem now as | |
1418 | * when we actually open and map them. Iterate over the file | |
1419 | * descriptors instead, and use qemu_fd_getpagesize(). | |
1420 | */ | |
1421 | static int find_max_supported_pagesize(Object *obj, void *opaque) | |
1422 | { | |
1423 | char *mem_path; | |
1424 | long *hpsize_min = opaque; | |
1425 | ||
1426 | if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { | |
1427 | mem_path = object_property_get_str(obj, "mem-path", NULL); | |
1428 | if (mem_path) { | |
1429 | long hpsize = qemu_mempath_getpagesize(mem_path); | |
1430 | if (hpsize < *hpsize_min) { | |
1431 | *hpsize_min = hpsize; | |
1432 | } | |
1433 | } else { | |
1434 | *hpsize_min = getpagesize(); | |
1435 | } | |
1436 | } | |
1437 | ||
1438 | return 0; | |
1439 | } | |
1440 | ||
1441 | long qemu_getrampagesize(void) | |
1442 | { | |
1443 | long hpsize = LONG_MAX; | |
1444 | long mainrampagesize; | |
1445 | Object *memdev_root; | |
1446 | ||
1447 | if (mem_path) { | |
1448 | mainrampagesize = qemu_mempath_getpagesize(mem_path); | |
1449 | } else { | |
1450 | mainrampagesize = getpagesize(); | |
1451 | } | |
1452 | ||
1453 | /* it's possible we have memory-backend objects with | |
1454 | * hugepage-backed RAM. these may get mapped into system | |
1455 | * address space via -numa parameters or memory hotplug | |
1456 | * hooks. we want to take these into account, but we | |
1457 | * also want to make sure these supported hugepage | |
1458 | * sizes are applicable across the entire range of memory | |
1459 | * we may boot from, so we take the min across all | |
1460 | * backends, and assume normal pages in cases where a | |
1461 | * backend isn't backed by hugepages. | |
1462 | */ | |
1463 | memdev_root = object_resolve_path("/objects", NULL); | |
1464 | if (memdev_root) { | |
1465 | object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize); | |
1466 | } | |
1467 | if (hpsize == LONG_MAX) { | |
1468 | /* No additional memory regions found ==> Report main RAM page size */ | |
1469 | return mainrampagesize; | |
1470 | } | |
1471 | ||
1472 | /* If NUMA is disabled or the NUMA nodes are not backed with a | |
1473 | * memory-backend, then there is at least one node using "normal" RAM, | |
1474 | * so if its page size is smaller we have got to report that size instead. | |
1475 | */ | |
1476 | if (hpsize > mainrampagesize && | |
1477 | (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) { | |
1478 | static bool warned; | |
1479 | if (!warned) { | |
1480 | error_report("Huge page support disabled (n/a for main memory)."); | |
1481 | warned = true; | |
1482 | } | |
1483 | return mainrampagesize; | |
1484 | } | |
1485 | ||
1486 | return hpsize; | |
1487 | } | |
1488 | #else | |
1489 | long qemu_getrampagesize(void) | |
1490 | { | |
1491 | return getpagesize(); | |
1492 | } | |
1493 | #endif | |
1494 | ||
e1e84ba0 | 1495 | #ifdef __linux__ |
d6af99c9 HZ |
1496 | static int64_t get_file_size(int fd) |
1497 | { | |
1498 | int64_t size = lseek(fd, 0, SEEK_END); | |
1499 | if (size < 0) { | |
1500 | return -errno; | |
1501 | } | |
1502 | return size; | |
1503 | } | |
1504 | ||
8d37b030 MAL |
1505 | static int file_ram_open(const char *path, |
1506 | const char *region_name, | |
1507 | bool *created, | |
1508 | Error **errp) | |
c902760f MT |
1509 | { |
1510 | char *filename; | |
8ca761f6 PF |
1511 | char *sanitized_name; |
1512 | char *c; | |
5c3ece79 | 1513 | int fd = -1; |
c902760f | 1514 | |
8d37b030 | 1515 | *created = false; |
fd97fd44 MA |
1516 | for (;;) { |
1517 | fd = open(path, O_RDWR); | |
1518 | if (fd >= 0) { | |
1519 | /* @path names an existing file, use it */ | |
1520 | break; | |
8d31d6b6 | 1521 | } |
fd97fd44 MA |
1522 | if (errno == ENOENT) { |
1523 | /* @path names a file that doesn't exist, create it */ | |
1524 | fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644); | |
1525 | if (fd >= 0) { | |
8d37b030 | 1526 | *created = true; |
fd97fd44 MA |
1527 | break; |
1528 | } | |
1529 | } else if (errno == EISDIR) { | |
1530 | /* @path names a directory, create a file there */ | |
1531 | /* Make name safe to use with mkstemp by replacing '/' with '_'. */ | |
8d37b030 | 1532 | sanitized_name = g_strdup(region_name); |
fd97fd44 MA |
1533 | for (c = sanitized_name; *c != '\0'; c++) { |
1534 | if (*c == '/') { | |
1535 | *c = '_'; | |
1536 | } | |
1537 | } | |
8ca761f6 | 1538 | |
fd97fd44 MA |
1539 | filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path, |
1540 | sanitized_name); | |
1541 | g_free(sanitized_name); | |
8d31d6b6 | 1542 | |
fd97fd44 MA |
1543 | fd = mkstemp(filename); |
1544 | if (fd >= 0) { | |
1545 | unlink(filename); | |
1546 | g_free(filename); | |
1547 | break; | |
1548 | } | |
1549 | g_free(filename); | |
8d31d6b6 | 1550 | } |
fd97fd44 MA |
1551 | if (errno != EEXIST && errno != EINTR) { |
1552 | error_setg_errno(errp, errno, | |
1553 | "can't open backing store %s for guest RAM", | |
1554 | path); | |
8d37b030 | 1555 | return -1; |
fd97fd44 MA |
1556 | } |
1557 | /* | |
1558 | * Try again on EINTR and EEXIST. The latter happens when | |
1559 | * something else creates the file between our two open(). | |
1560 | */ | |
8d31d6b6 | 1561 | } |
c902760f | 1562 | |
8d37b030 MAL |
1563 | return fd; |
1564 | } | |
1565 | ||
1566 | static void *file_ram_alloc(RAMBlock *block, | |
1567 | ram_addr_t memory, | |
1568 | int fd, | |
1569 | bool truncate, | |
1570 | Error **errp) | |
1571 | { | |
1572 | void *area; | |
1573 | ||
863e9621 | 1574 | block->page_size = qemu_fd_getpagesize(fd); |
8360668e HZ |
1575 | block->mr->align = block->page_size; |
1576 | #if defined(__s390x__) | |
1577 | if (kvm_enabled()) { | |
1578 | block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN); | |
1579 | } | |
1580 | #endif | |
fd97fd44 | 1581 | |
863e9621 | 1582 | if (memory < block->page_size) { |
fd97fd44 | 1583 | error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to " |
863e9621 DDAG |
1584 | "or larger than page size 0x%zx", |
1585 | memory, block->page_size); | |
8d37b030 | 1586 | return NULL; |
1775f111 HZ |
1587 | } |
1588 | ||
863e9621 | 1589 | memory = ROUND_UP(memory, block->page_size); |
c902760f MT |
1590 | |
1591 | /* | |
1592 | * ftruncate is not supported by hugetlbfs in older | |
1593 | * hosts, so don't bother bailing out on errors. | |
1594 | * If anything goes wrong with it under other filesystems, | |
1595 | * mmap will fail. | |
d6af99c9 HZ |
1596 | * |
1597 | * Do not truncate the non-empty backend file to avoid corrupting | |
1598 | * the existing data in the file. Disabling shrinking is not | |
1599 | * enough. For example, the current vNVDIMM implementation stores | |
1600 | * the guest NVDIMM labels at the end of the backend file. If the | |
1601 | * backend file is later extended, QEMU will not be able to find | |
1602 | * those labels. Therefore, extending the non-empty backend file | |
1603 | * is disabled as well. | |
c902760f | 1604 | */ |
8d37b030 | 1605 | if (truncate && ftruncate(fd, memory)) { |
9742bf26 | 1606 | perror("ftruncate"); |
7f56e740 | 1607 | } |
c902760f | 1608 | |
d2f39add DD |
1609 | area = qemu_ram_mmap(fd, memory, block->mr->align, |
1610 | block->flags & RAM_SHARED); | |
c902760f | 1611 | if (area == MAP_FAILED) { |
7f56e740 | 1612 | error_setg_errno(errp, errno, |
fd97fd44 | 1613 | "unable to map backing store for guest RAM"); |
8d37b030 | 1614 | return NULL; |
c902760f | 1615 | } |
ef36fa14 MT |
1616 | |
1617 | if (mem_prealloc) { | |
1e356fc1 | 1618 | os_mem_prealloc(fd, area, memory, smp_cpus, errp); |
056b68af | 1619 | if (errp && *errp) { |
8d37b030 MAL |
1620 | qemu_ram_munmap(area, memory); |
1621 | return NULL; | |
056b68af | 1622 | } |
ef36fa14 MT |
1623 | } |
1624 | ||
04b16653 | 1625 | block->fd = fd; |
c902760f MT |
1626 | return area; |
1627 | } | |
1628 | #endif | |
1629 | ||
0dc3f44a | 1630 | /* Called with the ramlist lock held. */ |
d17b5288 | 1631 | static ram_addr_t find_ram_offset(ram_addr_t size) |
04b16653 AW |
1632 | { |
1633 | RAMBlock *block, *next_block; | |
3e837b2c | 1634 | ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX; |
04b16653 | 1635 | |
49cd9ac6 SH |
1636 | assert(size != 0); /* it would hand out same offset multiple times */ |
1637 | ||
0dc3f44a | 1638 | if (QLIST_EMPTY_RCU(&ram_list.blocks)) { |
04b16653 | 1639 | return 0; |
0d53d9fe | 1640 | } |
04b16653 | 1641 | |
99e15582 | 1642 | RAMBLOCK_FOREACH(block) { |
f15fbc4b | 1643 | ram_addr_t end, next = RAM_ADDR_MAX; |
04b16653 | 1644 | |
62be4e3a | 1645 | end = block->offset + block->max_length; |
04b16653 | 1646 | |
99e15582 | 1647 | RAMBLOCK_FOREACH(next_block) { |
04b16653 AW |
1648 | if (next_block->offset >= end) { |
1649 | next = MIN(next, next_block->offset); | |
1650 | } | |
1651 | } | |
1652 | if (next - end >= size && next - end < mingap) { | |
3e837b2c | 1653 | offset = end; |
04b16653 AW |
1654 | mingap = next - end; |
1655 | } | |
1656 | } | |
3e837b2c AW |
1657 | |
1658 | if (offset == RAM_ADDR_MAX) { | |
1659 | fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n", | |
1660 | (uint64_t)size); | |
1661 | abort(); | |
1662 | } | |
1663 | ||
04b16653 AW |
1664 | return offset; |
1665 | } | |
1666 | ||
b8c48993 | 1667 | unsigned long last_ram_page(void) |
d17b5288 AW |
1668 | { |
1669 | RAMBlock *block; | |
1670 | ram_addr_t last = 0; | |
1671 | ||
0dc3f44a | 1672 | rcu_read_lock(); |
99e15582 | 1673 | RAMBLOCK_FOREACH(block) { |
62be4e3a | 1674 | last = MAX(last, block->offset + block->max_length); |
0d53d9fe | 1675 | } |
0dc3f44a | 1676 | rcu_read_unlock(); |
b8c48993 | 1677 | return last >> TARGET_PAGE_BITS; |
d17b5288 AW |
1678 | } |
1679 | ||
ddb97f1d JB |
1680 | static void qemu_ram_setup_dump(void *addr, ram_addr_t size) |
1681 | { | |
1682 | int ret; | |
ddb97f1d JB |
1683 | |
1684 | /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */ | |
47c8ca53 | 1685 | if (!machine_dump_guest_core(current_machine)) { |
ddb97f1d JB |
1686 | ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP); |
1687 | if (ret) { | |
1688 | perror("qemu_madvise"); | |
1689 | fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, " | |
1690 | "but dump_guest_core=off specified\n"); | |
1691 | } | |
1692 | } | |
1693 | } | |
1694 | ||
422148d3 DDAG |
1695 | const char *qemu_ram_get_idstr(RAMBlock *rb) |
1696 | { | |
1697 | return rb->idstr; | |
1698 | } | |
1699 | ||
463a4ac2 DDAG |
1700 | bool qemu_ram_is_shared(RAMBlock *rb) |
1701 | { | |
1702 | return rb->flags & RAM_SHARED; | |
1703 | } | |
1704 | ||
ae3a7047 | 1705 | /* Called with iothread lock held. */ |
fa53a0e5 | 1706 | void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev) |
20cfe881 | 1707 | { |
fa53a0e5 | 1708 | RAMBlock *block; |
20cfe881 | 1709 | |
c5705a77 AK |
1710 | assert(new_block); |
1711 | assert(!new_block->idstr[0]); | |
84b89d78 | 1712 | |
09e5ab63 AL |
1713 | if (dev) { |
1714 | char *id = qdev_get_dev_path(dev); | |
84b89d78 CM |
1715 | if (id) { |
1716 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); | |
7267c094 | 1717 | g_free(id); |
84b89d78 CM |
1718 | } |
1719 | } | |
1720 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); | |
1721 | ||
ab0a9956 | 1722 | rcu_read_lock(); |
99e15582 | 1723 | RAMBLOCK_FOREACH(block) { |
fa53a0e5 GA |
1724 | if (block != new_block && |
1725 | !strcmp(block->idstr, new_block->idstr)) { | |
84b89d78 CM |
1726 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", |
1727 | new_block->idstr); | |
1728 | abort(); | |
1729 | } | |
1730 | } | |
0dc3f44a | 1731 | rcu_read_unlock(); |
c5705a77 AK |
1732 | } |
1733 | ||
ae3a7047 | 1734 | /* Called with iothread lock held. */ |
fa53a0e5 | 1735 | void qemu_ram_unset_idstr(RAMBlock *block) |
20cfe881 | 1736 | { |
ae3a7047 MD |
1737 | /* FIXME: arch_init.c assumes that this is not called throughout |
1738 | * migration. Ignore the problem since hot-unplug during migration | |
1739 | * does not work anyway. | |
1740 | */ | |
20cfe881 HT |
1741 | if (block) { |
1742 | memset(block->idstr, 0, sizeof(block->idstr)); | |
1743 | } | |
1744 | } | |
1745 | ||
863e9621 DDAG |
1746 | size_t qemu_ram_pagesize(RAMBlock *rb) |
1747 | { | |
1748 | return rb->page_size; | |
1749 | } | |
1750 | ||
67f11b5c DDAG |
1751 | /* Returns the largest size of page in use */ |
1752 | size_t qemu_ram_pagesize_largest(void) | |
1753 | { | |
1754 | RAMBlock *block; | |
1755 | size_t largest = 0; | |
1756 | ||
99e15582 | 1757 | RAMBLOCK_FOREACH(block) { |
67f11b5c DDAG |
1758 | largest = MAX(largest, qemu_ram_pagesize(block)); |
1759 | } | |
1760 | ||
1761 | return largest; | |
1762 | } | |
1763 | ||
8490fc78 LC |
1764 | static int memory_try_enable_merging(void *addr, size_t len) |
1765 | { | |
75cc7f01 | 1766 | if (!machine_mem_merge(current_machine)) { |
8490fc78 LC |
1767 | /* disabled by the user */ |
1768 | return 0; | |
1769 | } | |
1770 | ||
1771 | return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE); | |
1772 | } | |
1773 | ||
62be4e3a MT |
1774 | /* Only legal before guest might have detected the memory size: e.g. on |
1775 | * incoming migration, or right after reset. | |
1776 | * | |
1777 | * As memory core doesn't know how is memory accessed, it is up to | |
1778 | * resize callback to update device state and/or add assertions to detect | |
1779 | * misuse, if necessary. | |
1780 | */ | |
fa53a0e5 | 1781 | int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp) |
62be4e3a | 1782 | { |
62be4e3a MT |
1783 | assert(block); |
1784 | ||
4ed023ce | 1785 | newsize = HOST_PAGE_ALIGN(newsize); |
129ddaf3 | 1786 | |
62be4e3a MT |
1787 | if (block->used_length == newsize) { |
1788 | return 0; | |
1789 | } | |
1790 | ||
1791 | if (!(block->flags & RAM_RESIZEABLE)) { | |
1792 | error_setg_errno(errp, EINVAL, | |
1793 | "Length mismatch: %s: 0x" RAM_ADDR_FMT | |
1794 | " in != 0x" RAM_ADDR_FMT, block->idstr, | |
1795 | newsize, block->used_length); | |
1796 | return -EINVAL; | |
1797 | } | |
1798 | ||
1799 | if (block->max_length < newsize) { | |
1800 | error_setg_errno(errp, EINVAL, | |
1801 | "Length too large: %s: 0x" RAM_ADDR_FMT | |
1802 | " > 0x" RAM_ADDR_FMT, block->idstr, | |
1803 | newsize, block->max_length); | |
1804 | return -EINVAL; | |
1805 | } | |
1806 | ||
1807 | cpu_physical_memory_clear_dirty_range(block->offset, block->used_length); | |
1808 | block->used_length = newsize; | |
58d2707e PB |
1809 | cpu_physical_memory_set_dirty_range(block->offset, block->used_length, |
1810 | DIRTY_CLIENTS_ALL); | |
62be4e3a MT |
1811 | memory_region_set_size(block->mr, newsize); |
1812 | if (block->resized) { | |
1813 | block->resized(block->idstr, newsize, block->host); | |
1814 | } | |
1815 | return 0; | |
1816 | } | |
1817 | ||
5b82b703 SH |
1818 | /* Called with ram_list.mutex held */ |
1819 | static void dirty_memory_extend(ram_addr_t old_ram_size, | |
1820 | ram_addr_t new_ram_size) | |
1821 | { | |
1822 | ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size, | |
1823 | DIRTY_MEMORY_BLOCK_SIZE); | |
1824 | ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size, | |
1825 | DIRTY_MEMORY_BLOCK_SIZE); | |
1826 | int i; | |
1827 | ||
1828 | /* Only need to extend if block count increased */ | |
1829 | if (new_num_blocks <= old_num_blocks) { | |
1830 | return; | |
1831 | } | |
1832 | ||
1833 | for (i = 0; i < DIRTY_MEMORY_NUM; i++) { | |
1834 | DirtyMemoryBlocks *old_blocks; | |
1835 | DirtyMemoryBlocks *new_blocks; | |
1836 | int j; | |
1837 | ||
1838 | old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]); | |
1839 | new_blocks = g_malloc(sizeof(*new_blocks) + | |
1840 | sizeof(new_blocks->blocks[0]) * new_num_blocks); | |
1841 | ||
1842 | if (old_num_blocks) { | |
1843 | memcpy(new_blocks->blocks, old_blocks->blocks, | |
1844 | old_num_blocks * sizeof(old_blocks->blocks[0])); | |
1845 | } | |
1846 | ||
1847 | for (j = old_num_blocks; j < new_num_blocks; j++) { | |
1848 | new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE); | |
1849 | } | |
1850 | ||
1851 | atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks); | |
1852 | ||
1853 | if (old_blocks) { | |
1854 | g_free_rcu(old_blocks, rcu); | |
1855 | } | |
1856 | } | |
1857 | } | |
1858 | ||
528f46af | 1859 | static void ram_block_add(RAMBlock *new_block, Error **errp) |
c5705a77 | 1860 | { |
e1c57ab8 | 1861 | RAMBlock *block; |
0d53d9fe | 1862 | RAMBlock *last_block = NULL; |
2152f5ca | 1863 | ram_addr_t old_ram_size, new_ram_size; |
37aa7a0e | 1864 | Error *err = NULL; |
2152f5ca | 1865 | |
b8c48993 | 1866 | old_ram_size = last_ram_page(); |
c5705a77 | 1867 | |
b2a8658e | 1868 | qemu_mutex_lock_ramlist(); |
9b8424d5 | 1869 | new_block->offset = find_ram_offset(new_block->max_length); |
e1c57ab8 PB |
1870 | |
1871 | if (!new_block->host) { | |
1872 | if (xen_enabled()) { | |
9b8424d5 | 1873 | xen_ram_alloc(new_block->offset, new_block->max_length, |
37aa7a0e MA |
1874 | new_block->mr, &err); |
1875 | if (err) { | |
1876 | error_propagate(errp, err); | |
1877 | qemu_mutex_unlock_ramlist(); | |
39c350ee | 1878 | return; |
37aa7a0e | 1879 | } |
e1c57ab8 | 1880 | } else { |
9b8424d5 | 1881 | new_block->host = phys_mem_alloc(new_block->max_length, |
a2b257d6 | 1882 | &new_block->mr->align); |
39228250 | 1883 | if (!new_block->host) { |
ef701d7b HT |
1884 | error_setg_errno(errp, errno, |
1885 | "cannot set up guest memory '%s'", | |
1886 | memory_region_name(new_block->mr)); | |
1887 | qemu_mutex_unlock_ramlist(); | |
39c350ee | 1888 | return; |
39228250 | 1889 | } |
9b8424d5 | 1890 | memory_try_enable_merging(new_block->host, new_block->max_length); |
6977dfe6 | 1891 | } |
c902760f | 1892 | } |
94a6b54f | 1893 | |
dd631697 LZ |
1894 | new_ram_size = MAX(old_ram_size, |
1895 | (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS); | |
1896 | if (new_ram_size > old_ram_size) { | |
5b82b703 | 1897 | dirty_memory_extend(old_ram_size, new_ram_size); |
dd631697 | 1898 | } |
0d53d9fe MD |
1899 | /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ, |
1900 | * QLIST (which has an RCU-friendly variant) does not have insertion at | |
1901 | * tail, so save the last element in last_block. | |
1902 | */ | |
99e15582 | 1903 | RAMBLOCK_FOREACH(block) { |
0d53d9fe | 1904 | last_block = block; |
9b8424d5 | 1905 | if (block->max_length < new_block->max_length) { |
abb26d63 PB |
1906 | break; |
1907 | } | |
1908 | } | |
1909 | if (block) { | |
0dc3f44a | 1910 | QLIST_INSERT_BEFORE_RCU(block, new_block, next); |
0d53d9fe | 1911 | } else if (last_block) { |
0dc3f44a | 1912 | QLIST_INSERT_AFTER_RCU(last_block, new_block, next); |
0d53d9fe | 1913 | } else { /* list is empty */ |
0dc3f44a | 1914 | QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next); |
abb26d63 | 1915 | } |
0d6d3c87 | 1916 | ram_list.mru_block = NULL; |
94a6b54f | 1917 | |
0dc3f44a MD |
1918 | /* Write list before version */ |
1919 | smp_wmb(); | |
f798b07f | 1920 | ram_list.version++; |
b2a8658e | 1921 | qemu_mutex_unlock_ramlist(); |
f798b07f | 1922 | |
9b8424d5 | 1923 | cpu_physical_memory_set_dirty_range(new_block->offset, |
58d2707e PB |
1924 | new_block->used_length, |
1925 | DIRTY_CLIENTS_ALL); | |
94a6b54f | 1926 | |
a904c911 PB |
1927 | if (new_block->host) { |
1928 | qemu_ram_setup_dump(new_block->host, new_block->max_length); | |
1929 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE); | |
c2cd627d | 1930 | /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */ |
a904c911 | 1931 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK); |
0987d735 | 1932 | ram_block_notify_add(new_block->host, new_block->max_length); |
e1c57ab8 | 1933 | } |
94a6b54f | 1934 | } |
e9a1ab19 | 1935 | |
0b183fc8 | 1936 | #ifdef __linux__ |
38b3362d MAL |
1937 | RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr, |
1938 | bool share, int fd, | |
1939 | Error **errp) | |
e1c57ab8 PB |
1940 | { |
1941 | RAMBlock *new_block; | |
ef701d7b | 1942 | Error *local_err = NULL; |
8d37b030 | 1943 | int64_t file_size; |
e1c57ab8 PB |
1944 | |
1945 | if (xen_enabled()) { | |
7f56e740 | 1946 | error_setg(errp, "-mem-path not supported with Xen"); |
528f46af | 1947 | return NULL; |
e1c57ab8 PB |
1948 | } |
1949 | ||
e45e7ae2 MAL |
1950 | if (kvm_enabled() && !kvm_has_sync_mmu()) { |
1951 | error_setg(errp, | |
1952 | "host lacks kvm mmu notifiers, -mem-path unsupported"); | |
1953 | return NULL; | |
1954 | } | |
1955 | ||
e1c57ab8 PB |
1956 | if (phys_mem_alloc != qemu_anon_ram_alloc) { |
1957 | /* | |
1958 | * file_ram_alloc() needs to allocate just like | |
1959 | * phys_mem_alloc, but we haven't bothered to provide | |
1960 | * a hook there. | |
1961 | */ | |
7f56e740 PB |
1962 | error_setg(errp, |
1963 | "-mem-path not supported with this accelerator"); | |
528f46af | 1964 | return NULL; |
e1c57ab8 PB |
1965 | } |
1966 | ||
4ed023ce | 1967 | size = HOST_PAGE_ALIGN(size); |
8d37b030 MAL |
1968 | file_size = get_file_size(fd); |
1969 | if (file_size > 0 && file_size < size) { | |
1970 | error_setg(errp, "backing store %s size 0x%" PRIx64 | |
1971 | " does not match 'size' option 0x" RAM_ADDR_FMT, | |
1972 | mem_path, file_size, size); | |
8d37b030 MAL |
1973 | return NULL; |
1974 | } | |
1975 | ||
e1c57ab8 PB |
1976 | new_block = g_malloc0(sizeof(*new_block)); |
1977 | new_block->mr = mr; | |
9b8424d5 MT |
1978 | new_block->used_length = size; |
1979 | new_block->max_length = size; | |
dbcb8981 | 1980 | new_block->flags = share ? RAM_SHARED : 0; |
8d37b030 | 1981 | new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp); |
7f56e740 PB |
1982 | if (!new_block->host) { |
1983 | g_free(new_block); | |
528f46af | 1984 | return NULL; |
7f56e740 PB |
1985 | } |
1986 | ||
528f46af | 1987 | ram_block_add(new_block, &local_err); |
ef701d7b HT |
1988 | if (local_err) { |
1989 | g_free(new_block); | |
1990 | error_propagate(errp, local_err); | |
528f46af | 1991 | return NULL; |
ef701d7b | 1992 | } |
528f46af | 1993 | return new_block; |
38b3362d MAL |
1994 | |
1995 | } | |
1996 | ||
1997 | ||
1998 | RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr, | |
1999 | bool share, const char *mem_path, | |
2000 | Error **errp) | |
2001 | { | |
2002 | int fd; | |
2003 | bool created; | |
2004 | RAMBlock *block; | |
2005 | ||
2006 | fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp); | |
2007 | if (fd < 0) { | |
2008 | return NULL; | |
2009 | } | |
2010 | ||
2011 | block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp); | |
2012 | if (!block) { | |
2013 | if (created) { | |
2014 | unlink(mem_path); | |
2015 | } | |
2016 | close(fd); | |
2017 | return NULL; | |
2018 | } | |
2019 | ||
2020 | return block; | |
e1c57ab8 | 2021 | } |
0b183fc8 | 2022 | #endif |
e1c57ab8 | 2023 | |
62be4e3a | 2024 | static |
528f46af FZ |
2025 | RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size, |
2026 | void (*resized)(const char*, | |
2027 | uint64_t length, | |
2028 | void *host), | |
2029 | void *host, bool resizeable, | |
2030 | MemoryRegion *mr, Error **errp) | |
e1c57ab8 PB |
2031 | { |
2032 | RAMBlock *new_block; | |
ef701d7b | 2033 | Error *local_err = NULL; |
e1c57ab8 | 2034 | |
4ed023ce DDAG |
2035 | size = HOST_PAGE_ALIGN(size); |
2036 | max_size = HOST_PAGE_ALIGN(max_size); | |
e1c57ab8 PB |
2037 | new_block = g_malloc0(sizeof(*new_block)); |
2038 | new_block->mr = mr; | |
62be4e3a | 2039 | new_block->resized = resized; |
9b8424d5 MT |
2040 | new_block->used_length = size; |
2041 | new_block->max_length = max_size; | |
62be4e3a | 2042 | assert(max_size >= size); |
e1c57ab8 | 2043 | new_block->fd = -1; |
863e9621 | 2044 | new_block->page_size = getpagesize(); |
e1c57ab8 PB |
2045 | new_block->host = host; |
2046 | if (host) { | |
7bd4f430 | 2047 | new_block->flags |= RAM_PREALLOC; |
e1c57ab8 | 2048 | } |
62be4e3a MT |
2049 | if (resizeable) { |
2050 | new_block->flags |= RAM_RESIZEABLE; | |
2051 | } | |
528f46af | 2052 | ram_block_add(new_block, &local_err); |
ef701d7b HT |
2053 | if (local_err) { |
2054 | g_free(new_block); | |
2055 | error_propagate(errp, local_err); | |
528f46af | 2056 | return NULL; |
ef701d7b | 2057 | } |
528f46af | 2058 | return new_block; |
e1c57ab8 PB |
2059 | } |
2060 | ||
528f46af | 2061 | RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, |
62be4e3a MT |
2062 | MemoryRegion *mr, Error **errp) |
2063 | { | |
2064 | return qemu_ram_alloc_internal(size, size, NULL, host, false, mr, errp); | |
2065 | } | |
2066 | ||
528f46af | 2067 | RAMBlock *qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr, Error **errp) |
6977dfe6 | 2068 | { |
62be4e3a MT |
2069 | return qemu_ram_alloc_internal(size, size, NULL, NULL, false, mr, errp); |
2070 | } | |
2071 | ||
528f46af | 2072 | RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz, |
62be4e3a MT |
2073 | void (*resized)(const char*, |
2074 | uint64_t length, | |
2075 | void *host), | |
2076 | MemoryRegion *mr, Error **errp) | |
2077 | { | |
2078 | return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, mr, errp); | |
6977dfe6 YT |
2079 | } |
2080 | ||
43771539 PB |
2081 | static void reclaim_ramblock(RAMBlock *block) |
2082 | { | |
2083 | if (block->flags & RAM_PREALLOC) { | |
2084 | ; | |
2085 | } else if (xen_enabled()) { | |
2086 | xen_invalidate_map_cache_entry(block->host); | |
2087 | #ifndef _WIN32 | |
2088 | } else if (block->fd >= 0) { | |
2f3a2bb1 | 2089 | qemu_ram_munmap(block->host, block->max_length); |
43771539 PB |
2090 | close(block->fd); |
2091 | #endif | |
2092 | } else { | |
2093 | qemu_anon_ram_free(block->host, block->max_length); | |
2094 | } | |
2095 | g_free(block); | |
2096 | } | |
2097 | ||
f1060c55 | 2098 | void qemu_ram_free(RAMBlock *block) |
e9a1ab19 | 2099 | { |
85bc2a15 MAL |
2100 | if (!block) { |
2101 | return; | |
2102 | } | |
2103 | ||
0987d735 PB |
2104 | if (block->host) { |
2105 | ram_block_notify_remove(block->host, block->max_length); | |
2106 | } | |
2107 | ||
b2a8658e | 2108 | qemu_mutex_lock_ramlist(); |
f1060c55 FZ |
2109 | QLIST_REMOVE_RCU(block, next); |
2110 | ram_list.mru_block = NULL; | |
2111 | /* Write list before version */ | |
2112 | smp_wmb(); | |
2113 | ram_list.version++; | |
2114 | call_rcu(block, reclaim_ramblock, rcu); | |
b2a8658e | 2115 | qemu_mutex_unlock_ramlist(); |
e9a1ab19 FB |
2116 | } |
2117 | ||
cd19cfa2 HY |
2118 | #ifndef _WIN32 |
2119 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) | |
2120 | { | |
2121 | RAMBlock *block; | |
2122 | ram_addr_t offset; | |
2123 | int flags; | |
2124 | void *area, *vaddr; | |
2125 | ||
99e15582 | 2126 | RAMBLOCK_FOREACH(block) { |
cd19cfa2 | 2127 | offset = addr - block->offset; |
9b8424d5 | 2128 | if (offset < block->max_length) { |
1240be24 | 2129 | vaddr = ramblock_ptr(block, offset); |
7bd4f430 | 2130 | if (block->flags & RAM_PREALLOC) { |
cd19cfa2 | 2131 | ; |
dfeaf2ab MA |
2132 | } else if (xen_enabled()) { |
2133 | abort(); | |
cd19cfa2 HY |
2134 | } else { |
2135 | flags = MAP_FIXED; | |
3435f395 | 2136 | if (block->fd >= 0) { |
dbcb8981 PB |
2137 | flags |= (block->flags & RAM_SHARED ? |
2138 | MAP_SHARED : MAP_PRIVATE); | |
3435f395 MA |
2139 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
2140 | flags, block->fd, offset); | |
cd19cfa2 | 2141 | } else { |
2eb9fbaa MA |
2142 | /* |
2143 | * Remap needs to match alloc. Accelerators that | |
2144 | * set phys_mem_alloc never remap. If they did, | |
2145 | * we'd need a remap hook here. | |
2146 | */ | |
2147 | assert(phys_mem_alloc == qemu_anon_ram_alloc); | |
2148 | ||
cd19cfa2 HY |
2149 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; |
2150 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
2151 | flags, -1, 0); | |
cd19cfa2 HY |
2152 | } |
2153 | if (area != vaddr) { | |
f15fbc4b AP |
2154 | fprintf(stderr, "Could not remap addr: " |
2155 | RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n", | |
cd19cfa2 HY |
2156 | length, addr); |
2157 | exit(1); | |
2158 | } | |
8490fc78 | 2159 | memory_try_enable_merging(vaddr, length); |
ddb97f1d | 2160 | qemu_ram_setup_dump(vaddr, length); |
cd19cfa2 | 2161 | } |
cd19cfa2 HY |
2162 | } |
2163 | } | |
2164 | } | |
2165 | #endif /* !_WIN32 */ | |
2166 | ||
1b5ec234 | 2167 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
ae3a7047 MD |
2168 | * This should not be used for general purpose DMA. Use address_space_map |
2169 | * or address_space_rw instead. For local memory (e.g. video ram) that the | |
2170 | * device owns, use memory_region_get_ram_ptr. | |
0dc3f44a | 2171 | * |
49b24afc | 2172 | * Called within RCU critical section. |
1b5ec234 | 2173 | */ |
0878d0e1 | 2174 | void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr) |
1b5ec234 | 2175 | { |
3655cb9c GA |
2176 | RAMBlock *block = ram_block; |
2177 | ||
2178 | if (block == NULL) { | |
2179 | block = qemu_get_ram_block(addr); | |
0878d0e1 | 2180 | addr -= block->offset; |
3655cb9c | 2181 | } |
ae3a7047 MD |
2182 | |
2183 | if (xen_enabled() && block->host == NULL) { | |
0d6d3c87 PB |
2184 | /* We need to check if the requested address is in the RAM |
2185 | * because we don't want to map the entire memory in QEMU. | |
2186 | * In that case just map until the end of the page. | |
2187 | */ | |
2188 | if (block->offset == 0) { | |
1ff7c598 | 2189 | return xen_map_cache(addr, 0, 0, false); |
0d6d3c87 | 2190 | } |
ae3a7047 | 2191 | |
1ff7c598 | 2192 | block->host = xen_map_cache(block->offset, block->max_length, 1, false); |
0d6d3c87 | 2193 | } |
0878d0e1 | 2194 | return ramblock_ptr(block, addr); |
dc828ca1 PB |
2195 | } |
2196 | ||
0878d0e1 | 2197 | /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr |
ae3a7047 | 2198 | * but takes a size argument. |
0dc3f44a | 2199 | * |
e81bcda5 | 2200 | * Called within RCU critical section. |
ae3a7047 | 2201 | */ |
3655cb9c | 2202 | static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr, |
f5aa69bd | 2203 | hwaddr *size, bool lock) |
38bee5dc | 2204 | { |
3655cb9c | 2205 | RAMBlock *block = ram_block; |
8ab934f9 SS |
2206 | if (*size == 0) { |
2207 | return NULL; | |
2208 | } | |
e81bcda5 | 2209 | |
3655cb9c GA |
2210 | if (block == NULL) { |
2211 | block = qemu_get_ram_block(addr); | |
0878d0e1 | 2212 | addr -= block->offset; |
3655cb9c | 2213 | } |
0878d0e1 | 2214 | *size = MIN(*size, block->max_length - addr); |
e81bcda5 PB |
2215 | |
2216 | if (xen_enabled() && block->host == NULL) { | |
2217 | /* We need to check if the requested address is in the RAM | |
2218 | * because we don't want to map the entire memory in QEMU. | |
2219 | * In that case just map the requested area. | |
2220 | */ | |
2221 | if (block->offset == 0) { | |
f5aa69bd | 2222 | return xen_map_cache(addr, *size, lock, lock); |
38bee5dc SS |
2223 | } |
2224 | ||
f5aa69bd | 2225 | block->host = xen_map_cache(block->offset, block->max_length, 1, lock); |
38bee5dc | 2226 | } |
e81bcda5 | 2227 | |
0878d0e1 | 2228 | return ramblock_ptr(block, addr); |
38bee5dc SS |
2229 | } |
2230 | ||
422148d3 DDAG |
2231 | /* |
2232 | * Translates a host ptr back to a RAMBlock, a ram_addr and an offset | |
2233 | * in that RAMBlock. | |
2234 | * | |
2235 | * ptr: Host pointer to look up | |
2236 | * round_offset: If true round the result offset down to a page boundary | |
2237 | * *ram_addr: set to result ram_addr | |
2238 | * *offset: set to result offset within the RAMBlock | |
2239 | * | |
2240 | * Returns: RAMBlock (or NULL if not found) | |
ae3a7047 MD |
2241 | * |
2242 | * By the time this function returns, the returned pointer is not protected | |
2243 | * by RCU anymore. If the caller is not within an RCU critical section and | |
2244 | * does not hold the iothread lock, it must have other means of protecting the | |
2245 | * pointer, such as a reference to the region that includes the incoming | |
2246 | * ram_addr_t. | |
2247 | */ | |
422148d3 | 2248 | RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, |
422148d3 | 2249 | ram_addr_t *offset) |
5579c7f3 | 2250 | { |
94a6b54f PB |
2251 | RAMBlock *block; |
2252 | uint8_t *host = ptr; | |
2253 | ||
868bb33f | 2254 | if (xen_enabled()) { |
f615f396 | 2255 | ram_addr_t ram_addr; |
0dc3f44a | 2256 | rcu_read_lock(); |
f615f396 PB |
2257 | ram_addr = xen_ram_addr_from_mapcache(ptr); |
2258 | block = qemu_get_ram_block(ram_addr); | |
422148d3 | 2259 | if (block) { |
d6b6aec4 | 2260 | *offset = ram_addr - block->offset; |
422148d3 | 2261 | } |
0dc3f44a | 2262 | rcu_read_unlock(); |
422148d3 | 2263 | return block; |
712c2b41 SS |
2264 | } |
2265 | ||
0dc3f44a MD |
2266 | rcu_read_lock(); |
2267 | block = atomic_rcu_read(&ram_list.mru_block); | |
9b8424d5 | 2268 | if (block && block->host && host - block->host < block->max_length) { |
23887b79 PB |
2269 | goto found; |
2270 | } | |
2271 | ||
99e15582 | 2272 | RAMBLOCK_FOREACH(block) { |
432d268c JN |
2273 | /* This case append when the block is not mapped. */ |
2274 | if (block->host == NULL) { | |
2275 | continue; | |
2276 | } | |
9b8424d5 | 2277 | if (host - block->host < block->max_length) { |
23887b79 | 2278 | goto found; |
f471a17e | 2279 | } |
94a6b54f | 2280 | } |
432d268c | 2281 | |
0dc3f44a | 2282 | rcu_read_unlock(); |
1b5ec234 | 2283 | return NULL; |
23887b79 PB |
2284 | |
2285 | found: | |
422148d3 DDAG |
2286 | *offset = (host - block->host); |
2287 | if (round_offset) { | |
2288 | *offset &= TARGET_PAGE_MASK; | |
2289 | } | |
0dc3f44a | 2290 | rcu_read_unlock(); |
422148d3 DDAG |
2291 | return block; |
2292 | } | |
2293 | ||
e3dd7493 DDAG |
2294 | /* |
2295 | * Finds the named RAMBlock | |
2296 | * | |
2297 | * name: The name of RAMBlock to find | |
2298 | * | |
2299 | * Returns: RAMBlock (or NULL if not found) | |
2300 | */ | |
2301 | RAMBlock *qemu_ram_block_by_name(const char *name) | |
2302 | { | |
2303 | RAMBlock *block; | |
2304 | ||
99e15582 | 2305 | RAMBLOCK_FOREACH(block) { |
e3dd7493 DDAG |
2306 | if (!strcmp(name, block->idstr)) { |
2307 | return block; | |
2308 | } | |
2309 | } | |
2310 | ||
2311 | return NULL; | |
2312 | } | |
2313 | ||
422148d3 DDAG |
2314 | /* Some of the softmmu routines need to translate from a host pointer |
2315 | (typically a TLB entry) back to a ram offset. */ | |
07bdaa41 | 2316 | ram_addr_t qemu_ram_addr_from_host(void *ptr) |
422148d3 DDAG |
2317 | { |
2318 | RAMBlock *block; | |
f615f396 | 2319 | ram_addr_t offset; |
422148d3 | 2320 | |
f615f396 | 2321 | block = qemu_ram_block_from_host(ptr, false, &offset); |
422148d3 | 2322 | if (!block) { |
07bdaa41 | 2323 | return RAM_ADDR_INVALID; |
422148d3 DDAG |
2324 | } |
2325 | ||
07bdaa41 | 2326 | return block->offset + offset; |
e890261f | 2327 | } |
f471a17e | 2328 | |
49b24afc | 2329 | /* Called within RCU critical section. */ |
a8170e5e | 2330 | static void notdirty_mem_write(void *opaque, hwaddr ram_addr, |
0e0df1e2 | 2331 | uint64_t val, unsigned size) |
9fa3e853 | 2332 | { |
ba051fb5 AB |
2333 | bool locked = false; |
2334 | ||
5aa1ef71 | 2335 | assert(tcg_enabled()); |
52159192 | 2336 | if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { |
ba051fb5 AB |
2337 | locked = true; |
2338 | tb_lock(); | |
0e0df1e2 | 2339 | tb_invalidate_phys_page_fast(ram_addr, size); |
3a7d929e | 2340 | } |
0e0df1e2 AK |
2341 | switch (size) { |
2342 | case 1: | |
0878d0e1 | 2343 | stb_p(qemu_map_ram_ptr(NULL, ram_addr), val); |
0e0df1e2 AK |
2344 | break; |
2345 | case 2: | |
0878d0e1 | 2346 | stw_p(qemu_map_ram_ptr(NULL, ram_addr), val); |
0e0df1e2 AK |
2347 | break; |
2348 | case 4: | |
0878d0e1 | 2349 | stl_p(qemu_map_ram_ptr(NULL, ram_addr), val); |
0e0df1e2 AK |
2350 | break; |
2351 | default: | |
2352 | abort(); | |
3a7d929e | 2353 | } |
ba051fb5 AB |
2354 | |
2355 | if (locked) { | |
2356 | tb_unlock(); | |
2357 | } | |
2358 | ||
58d2707e PB |
2359 | /* Set both VGA and migration bits for simplicity and to remove |
2360 | * the notdirty callback faster. | |
2361 | */ | |
2362 | cpu_physical_memory_set_dirty_range(ram_addr, size, | |
2363 | DIRTY_CLIENTS_NOCODE); | |
f23db169 FB |
2364 | /* we remove the notdirty callback only if the code has been |
2365 | flushed */ | |
a2cd8c85 | 2366 | if (!cpu_physical_memory_is_clean(ram_addr)) { |
bcae01e4 | 2367 | tlb_set_dirty(current_cpu, current_cpu->mem_io_vaddr); |
4917cf44 | 2368 | } |
9fa3e853 FB |
2369 | } |
2370 | ||
b018ddf6 PB |
2371 | static bool notdirty_mem_accepts(void *opaque, hwaddr addr, |
2372 | unsigned size, bool is_write) | |
2373 | { | |
2374 | return is_write; | |
2375 | } | |
2376 | ||
0e0df1e2 | 2377 | static const MemoryRegionOps notdirty_mem_ops = { |
0e0df1e2 | 2378 | .write = notdirty_mem_write, |
b018ddf6 | 2379 | .valid.accepts = notdirty_mem_accepts, |
0e0df1e2 | 2380 | .endianness = DEVICE_NATIVE_ENDIAN, |
1ccde1cb FB |
2381 | }; |
2382 | ||
0f459d16 | 2383 | /* Generate a debug exception if a watchpoint has been hit. */ |
66b9b43c | 2384 | static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags) |
0f459d16 | 2385 | { |
93afeade | 2386 | CPUState *cpu = current_cpu; |
568496c0 | 2387 | CPUClass *cc = CPU_GET_CLASS(cpu); |
93afeade | 2388 | CPUArchState *env = cpu->env_ptr; |
06d55cc1 | 2389 | target_ulong pc, cs_base; |
0f459d16 | 2390 | target_ulong vaddr; |
a1d1bb31 | 2391 | CPUWatchpoint *wp; |
89fee74a | 2392 | uint32_t cpu_flags; |
0f459d16 | 2393 | |
5aa1ef71 | 2394 | assert(tcg_enabled()); |
ff4700b0 | 2395 | if (cpu->watchpoint_hit) { |
06d55cc1 AL |
2396 | /* We re-entered the check after replacing the TB. Now raise |
2397 | * the debug interrupt so that is will trigger after the | |
2398 | * current instruction. */ | |
93afeade | 2399 | cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); |
06d55cc1 AL |
2400 | return; |
2401 | } | |
93afeade | 2402 | vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
40612000 | 2403 | vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len); |
ff4700b0 | 2404 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d PM |
2405 | if (cpu_watchpoint_address_matches(wp, vaddr, len) |
2406 | && (wp->flags & flags)) { | |
08225676 PM |
2407 | if (flags == BP_MEM_READ) { |
2408 | wp->flags |= BP_WATCHPOINT_HIT_READ; | |
2409 | } else { | |
2410 | wp->flags |= BP_WATCHPOINT_HIT_WRITE; | |
2411 | } | |
2412 | wp->hitaddr = vaddr; | |
66b9b43c | 2413 | wp->hitattrs = attrs; |
ff4700b0 | 2414 | if (!cpu->watchpoint_hit) { |
568496c0 SF |
2415 | if (wp->flags & BP_CPU && |
2416 | !cc->debug_check_watchpoint(cpu, wp)) { | |
2417 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
2418 | continue; | |
2419 | } | |
ff4700b0 | 2420 | cpu->watchpoint_hit = wp; |
a5e99826 | 2421 | |
8d04fb55 JK |
2422 | /* Both tb_lock and iothread_mutex will be reset when |
2423 | * cpu_loop_exit or cpu_loop_exit_noexc longjmp | |
2424 | * back into the cpu_exec main loop. | |
a5e99826 FK |
2425 | */ |
2426 | tb_lock(); | |
239c51a5 | 2427 | tb_check_watchpoint(cpu); |
6e140f28 | 2428 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { |
27103424 | 2429 | cpu->exception_index = EXCP_DEBUG; |
5638d180 | 2430 | cpu_loop_exit(cpu); |
6e140f28 AL |
2431 | } else { |
2432 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); | |
648f034c | 2433 | tb_gen_code(cpu, pc, cs_base, cpu_flags, 1); |
6886b980 | 2434 | cpu_loop_exit_noexc(cpu); |
6e140f28 | 2435 | } |
06d55cc1 | 2436 | } |
6e140f28 AL |
2437 | } else { |
2438 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
0f459d16 PB |
2439 | } |
2440 | } | |
2441 | } | |
2442 | ||
6658ffb8 PB |
2443 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
2444 | so these check for a hit then pass through to the normal out-of-line | |
2445 | phys routines. */ | |
66b9b43c PM |
2446 | static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata, |
2447 | unsigned size, MemTxAttrs attrs) | |
6658ffb8 | 2448 | { |
66b9b43c PM |
2449 | MemTxResult res; |
2450 | uint64_t data; | |
79ed0416 PM |
2451 | int asidx = cpu_asidx_from_attrs(current_cpu, attrs); |
2452 | AddressSpace *as = current_cpu->cpu_ases[asidx].as; | |
66b9b43c PM |
2453 | |
2454 | check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ); | |
1ec9b909 | 2455 | switch (size) { |
66b9b43c | 2456 | case 1: |
79ed0416 | 2457 | data = address_space_ldub(as, addr, attrs, &res); |
66b9b43c PM |
2458 | break; |
2459 | case 2: | |
79ed0416 | 2460 | data = address_space_lduw(as, addr, attrs, &res); |
66b9b43c PM |
2461 | break; |
2462 | case 4: | |
79ed0416 | 2463 | data = address_space_ldl(as, addr, attrs, &res); |
66b9b43c | 2464 | break; |
1ec9b909 AK |
2465 | default: abort(); |
2466 | } | |
66b9b43c PM |
2467 | *pdata = data; |
2468 | return res; | |
6658ffb8 PB |
2469 | } |
2470 | ||
66b9b43c PM |
2471 | static MemTxResult watch_mem_write(void *opaque, hwaddr addr, |
2472 | uint64_t val, unsigned size, | |
2473 | MemTxAttrs attrs) | |
6658ffb8 | 2474 | { |
66b9b43c | 2475 | MemTxResult res; |
79ed0416 PM |
2476 | int asidx = cpu_asidx_from_attrs(current_cpu, attrs); |
2477 | AddressSpace *as = current_cpu->cpu_ases[asidx].as; | |
66b9b43c PM |
2478 | |
2479 | check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE); | |
1ec9b909 | 2480 | switch (size) { |
67364150 | 2481 | case 1: |
79ed0416 | 2482 | address_space_stb(as, addr, val, attrs, &res); |
67364150 MF |
2483 | break; |
2484 | case 2: | |
79ed0416 | 2485 | address_space_stw(as, addr, val, attrs, &res); |
67364150 MF |
2486 | break; |
2487 | case 4: | |
79ed0416 | 2488 | address_space_stl(as, addr, val, attrs, &res); |
67364150 | 2489 | break; |
1ec9b909 AK |
2490 | default: abort(); |
2491 | } | |
66b9b43c | 2492 | return res; |
6658ffb8 PB |
2493 | } |
2494 | ||
1ec9b909 | 2495 | static const MemoryRegionOps watch_mem_ops = { |
66b9b43c PM |
2496 | .read_with_attrs = watch_mem_read, |
2497 | .write_with_attrs = watch_mem_write, | |
1ec9b909 | 2498 | .endianness = DEVICE_NATIVE_ENDIAN, |
6658ffb8 | 2499 | }; |
6658ffb8 | 2500 | |
16620684 AK |
2501 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, |
2502 | const uint8_t *buf, int len); | |
2503 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, | |
2504 | bool is_write); | |
2505 | ||
f25a49e0 PM |
2506 | static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, |
2507 | unsigned len, MemTxAttrs attrs) | |
db7b5426 | 2508 | { |
acc9d80b | 2509 | subpage_t *subpage = opaque; |
ff6cff75 | 2510 | uint8_t buf[8]; |
5c9eb028 | 2511 | MemTxResult res; |
791af8c8 | 2512 | |
db7b5426 | 2513 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2514 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__, |
acc9d80b | 2515 | subpage, len, addr); |
db7b5426 | 2516 | #endif |
16620684 | 2517 | res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len); |
5c9eb028 PM |
2518 | if (res) { |
2519 | return res; | |
f25a49e0 | 2520 | } |
acc9d80b JK |
2521 | switch (len) { |
2522 | case 1: | |
f25a49e0 PM |
2523 | *data = ldub_p(buf); |
2524 | return MEMTX_OK; | |
acc9d80b | 2525 | case 2: |
f25a49e0 PM |
2526 | *data = lduw_p(buf); |
2527 | return MEMTX_OK; | |
acc9d80b | 2528 | case 4: |
f25a49e0 PM |
2529 | *data = ldl_p(buf); |
2530 | return MEMTX_OK; | |
ff6cff75 | 2531 | case 8: |
f25a49e0 PM |
2532 | *data = ldq_p(buf); |
2533 | return MEMTX_OK; | |
acc9d80b JK |
2534 | default: |
2535 | abort(); | |
2536 | } | |
db7b5426 BS |
2537 | } |
2538 | ||
f25a49e0 PM |
2539 | static MemTxResult subpage_write(void *opaque, hwaddr addr, |
2540 | uint64_t value, unsigned len, MemTxAttrs attrs) | |
db7b5426 | 2541 | { |
acc9d80b | 2542 | subpage_t *subpage = opaque; |
ff6cff75 | 2543 | uint8_t buf[8]; |
acc9d80b | 2544 | |
db7b5426 | 2545 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2546 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx |
acc9d80b JK |
2547 | " value %"PRIx64"\n", |
2548 | __func__, subpage, len, addr, value); | |
db7b5426 | 2549 | #endif |
acc9d80b JK |
2550 | switch (len) { |
2551 | case 1: | |
2552 | stb_p(buf, value); | |
2553 | break; | |
2554 | case 2: | |
2555 | stw_p(buf, value); | |
2556 | break; | |
2557 | case 4: | |
2558 | stl_p(buf, value); | |
2559 | break; | |
ff6cff75 PB |
2560 | case 8: |
2561 | stq_p(buf, value); | |
2562 | break; | |
acc9d80b JK |
2563 | default: |
2564 | abort(); | |
2565 | } | |
16620684 | 2566 | return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len); |
db7b5426 BS |
2567 | } |
2568 | ||
c353e4cc | 2569 | static bool subpage_accepts(void *opaque, hwaddr addr, |
016e9d62 | 2570 | unsigned len, bool is_write) |
c353e4cc | 2571 | { |
acc9d80b | 2572 | subpage_t *subpage = opaque; |
c353e4cc | 2573 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2574 | printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n", |
acc9d80b | 2575 | __func__, subpage, is_write ? 'w' : 'r', len, addr); |
c353e4cc PB |
2576 | #endif |
2577 | ||
16620684 AK |
2578 | return flatview_access_valid(subpage->fv, addr + subpage->base, |
2579 | len, is_write); | |
c353e4cc PB |
2580 | } |
2581 | ||
70c68e44 | 2582 | static const MemoryRegionOps subpage_ops = { |
f25a49e0 PM |
2583 | .read_with_attrs = subpage_read, |
2584 | .write_with_attrs = subpage_write, | |
ff6cff75 PB |
2585 | .impl.min_access_size = 1, |
2586 | .impl.max_access_size = 8, | |
2587 | .valid.min_access_size = 1, | |
2588 | .valid.max_access_size = 8, | |
c353e4cc | 2589 | .valid.accepts = subpage_accepts, |
70c68e44 | 2590 | .endianness = DEVICE_NATIVE_ENDIAN, |
db7b5426 BS |
2591 | }; |
2592 | ||
c227f099 | 2593 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
5312bd8b | 2594 | uint16_t section) |
db7b5426 BS |
2595 | { |
2596 | int idx, eidx; | |
2597 | ||
2598 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
2599 | return -1; | |
2600 | idx = SUBPAGE_IDX(start); | |
2601 | eidx = SUBPAGE_IDX(end); | |
2602 | #if defined(DEBUG_SUBPAGE) | |
016e9d62 AK |
2603 | printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n", |
2604 | __func__, mmio, start, end, idx, eidx, section); | |
db7b5426 | 2605 | #endif |
db7b5426 | 2606 | for (; idx <= eidx; idx++) { |
5312bd8b | 2607 | mmio->sub_section[idx] = section; |
db7b5426 BS |
2608 | } |
2609 | ||
2610 | return 0; | |
2611 | } | |
2612 | ||
16620684 | 2613 | static subpage_t *subpage_init(FlatView *fv, hwaddr base) |
db7b5426 | 2614 | { |
c227f099 | 2615 | subpage_t *mmio; |
db7b5426 | 2616 | |
2615fabd | 2617 | mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t)); |
16620684 | 2618 | mmio->fv = fv; |
1eec614b | 2619 | mmio->base = base; |
2c9b15ca | 2620 | memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio, |
b4fefef9 | 2621 | NULL, TARGET_PAGE_SIZE); |
b3b00c78 | 2622 | mmio->iomem.subpage = true; |
db7b5426 | 2623 | #if defined(DEBUG_SUBPAGE) |
016e9d62 AK |
2624 | printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__, |
2625 | mmio, base, TARGET_PAGE_SIZE); | |
db7b5426 | 2626 | #endif |
b41aac4f | 2627 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED); |
db7b5426 BS |
2628 | |
2629 | return mmio; | |
2630 | } | |
2631 | ||
16620684 | 2632 | static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr) |
5312bd8b | 2633 | { |
16620684 | 2634 | assert(fv); |
5312bd8b | 2635 | MemoryRegionSection section = { |
16620684 | 2636 | .fv = fv, |
5312bd8b AK |
2637 | .mr = mr, |
2638 | .offset_within_address_space = 0, | |
2639 | .offset_within_region = 0, | |
052e87b0 | 2640 | .size = int128_2_64(), |
5312bd8b AK |
2641 | }; |
2642 | ||
53cb28cb | 2643 | return phys_section_add(map, §ion); |
5312bd8b AK |
2644 | } |
2645 | ||
a54c87b6 | 2646 | MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs) |
aa102231 | 2647 | { |
a54c87b6 PM |
2648 | int asidx = cpu_asidx_from_attrs(cpu, attrs); |
2649 | CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx]; | |
32857f4d | 2650 | AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch); |
79e2b9ae | 2651 | MemoryRegionSection *sections = d->map.sections; |
9d82b5a7 PB |
2652 | |
2653 | return sections[index & ~TARGET_PAGE_MASK].mr; | |
aa102231 AK |
2654 | } |
2655 | ||
e9179ce1 AK |
2656 | static void io_mem_init(void) |
2657 | { | |
1f6245e5 | 2658 | memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX); |
2c9b15ca | 2659 | memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, |
1f6245e5 | 2660 | NULL, UINT64_MAX); |
8d04fb55 JK |
2661 | |
2662 | /* io_mem_notdirty calls tb_invalidate_phys_page_fast, | |
2663 | * which can be called without the iothread mutex. | |
2664 | */ | |
2c9b15ca | 2665 | memory_region_init_io(&io_mem_notdirty, NULL, ¬dirty_mem_ops, NULL, |
1f6245e5 | 2666 | NULL, UINT64_MAX); |
8d04fb55 JK |
2667 | memory_region_clear_global_locking(&io_mem_notdirty); |
2668 | ||
2c9b15ca | 2669 | memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL, |
1f6245e5 | 2670 | NULL, UINT64_MAX); |
e9179ce1 AK |
2671 | } |
2672 | ||
8629d3fc | 2673 | AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv) |
00752703 | 2674 | { |
53cb28cb MA |
2675 | AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1); |
2676 | uint16_t n; | |
2677 | ||
16620684 | 2678 | n = dummy_section(&d->map, fv, &io_mem_unassigned); |
53cb28cb | 2679 | assert(n == PHYS_SECTION_UNASSIGNED); |
16620684 | 2680 | n = dummy_section(&d->map, fv, &io_mem_notdirty); |
53cb28cb | 2681 | assert(n == PHYS_SECTION_NOTDIRTY); |
16620684 | 2682 | n = dummy_section(&d->map, fv, &io_mem_rom); |
53cb28cb | 2683 | assert(n == PHYS_SECTION_ROM); |
16620684 | 2684 | n = dummy_section(&d->map, fv, &io_mem_watch); |
53cb28cb | 2685 | assert(n == PHYS_SECTION_WATCH); |
00752703 | 2686 | |
9736e55b | 2687 | d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 }; |
66a6df1d AK |
2688 | |
2689 | return d; | |
00752703 PB |
2690 | } |
2691 | ||
66a6df1d | 2692 | void address_space_dispatch_free(AddressSpaceDispatch *d) |
79e2b9ae PB |
2693 | { |
2694 | phys_sections_free(&d->map); | |
2695 | g_free(d); | |
2696 | } | |
2697 | ||
1d71148e | 2698 | static void tcg_commit(MemoryListener *listener) |
50c1e149 | 2699 | { |
32857f4d PM |
2700 | CPUAddressSpace *cpuas; |
2701 | AddressSpaceDispatch *d; | |
117712c3 AK |
2702 | |
2703 | /* since each CPU stores ram addresses in its TLB cache, we must | |
2704 | reset the modified entries */ | |
32857f4d PM |
2705 | cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener); |
2706 | cpu_reloading_memory_map(); | |
2707 | /* The CPU and TLB are protected by the iothread lock. | |
2708 | * We reload the dispatch pointer now because cpu_reloading_memory_map() | |
2709 | * may have split the RCU critical section. | |
2710 | */ | |
66a6df1d | 2711 | d = address_space_to_dispatch(cpuas->as); |
f35e44e7 | 2712 | atomic_rcu_set(&cpuas->memory_dispatch, d); |
d10eb08f | 2713 | tlb_flush(cpuas->cpu); |
50c1e149 AK |
2714 | } |
2715 | ||
62152b8a AK |
2716 | static void memory_map_init(void) |
2717 | { | |
7267c094 | 2718 | system_memory = g_malloc(sizeof(*system_memory)); |
03f49957 | 2719 | |
57271d63 | 2720 | memory_region_init(system_memory, NULL, "system", UINT64_MAX); |
7dca8043 | 2721 | address_space_init(&address_space_memory, system_memory, "memory"); |
309cb471 | 2722 | |
7267c094 | 2723 | system_io = g_malloc(sizeof(*system_io)); |
3bb28b72 JK |
2724 | memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io", |
2725 | 65536); | |
7dca8043 | 2726 | address_space_init(&address_space_io, system_io, "I/O"); |
62152b8a AK |
2727 | } |
2728 | ||
2729 | MemoryRegion *get_system_memory(void) | |
2730 | { | |
2731 | return system_memory; | |
2732 | } | |
2733 | ||
309cb471 AK |
2734 | MemoryRegion *get_system_io(void) |
2735 | { | |
2736 | return system_io; | |
2737 | } | |
2738 | ||
e2eef170 PB |
2739 | #endif /* !defined(CONFIG_USER_ONLY) */ |
2740 | ||
13eb76e0 FB |
2741 | /* physical memory access (slow version, mainly for debug) */ |
2742 | #if defined(CONFIG_USER_ONLY) | |
f17ec444 | 2743 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
a68fe89c | 2744 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
2745 | { |
2746 | int l, flags; | |
2747 | target_ulong page; | |
53a5960a | 2748 | void * p; |
13eb76e0 FB |
2749 | |
2750 | while (len > 0) { | |
2751 | page = addr & TARGET_PAGE_MASK; | |
2752 | l = (page + TARGET_PAGE_SIZE) - addr; | |
2753 | if (l > len) | |
2754 | l = len; | |
2755 | flags = page_get_flags(page); | |
2756 | if (!(flags & PAGE_VALID)) | |
a68fe89c | 2757 | return -1; |
13eb76e0 FB |
2758 | if (is_write) { |
2759 | if (!(flags & PAGE_WRITE)) | |
a68fe89c | 2760 | return -1; |
579a97f7 | 2761 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 2762 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
a68fe89c | 2763 | return -1; |
72fb7daa AJ |
2764 | memcpy(p, buf, l); |
2765 | unlock_user(p, addr, l); | |
13eb76e0 FB |
2766 | } else { |
2767 | if (!(flags & PAGE_READ)) | |
a68fe89c | 2768 | return -1; |
579a97f7 | 2769 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 2770 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
a68fe89c | 2771 | return -1; |
72fb7daa | 2772 | memcpy(buf, p, l); |
5b257578 | 2773 | unlock_user(p, addr, 0); |
13eb76e0 FB |
2774 | } |
2775 | len -= l; | |
2776 | buf += l; | |
2777 | addr += l; | |
2778 | } | |
a68fe89c | 2779 | return 0; |
13eb76e0 | 2780 | } |
8df1cd07 | 2781 | |
13eb76e0 | 2782 | #else |
51d7a9eb | 2783 | |
845b6214 | 2784 | static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr, |
a8170e5e | 2785 | hwaddr length) |
51d7a9eb | 2786 | { |
e87f7778 | 2787 | uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr); |
0878d0e1 PB |
2788 | addr += memory_region_get_ram_addr(mr); |
2789 | ||
e87f7778 PB |
2790 | /* No early return if dirty_log_mask is or becomes 0, because |
2791 | * cpu_physical_memory_set_dirty_range will still call | |
2792 | * xen_modified_memory. | |
2793 | */ | |
2794 | if (dirty_log_mask) { | |
2795 | dirty_log_mask = | |
2796 | cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask); | |
2797 | } | |
2798 | if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) { | |
5aa1ef71 | 2799 | assert(tcg_enabled()); |
ba051fb5 | 2800 | tb_lock(); |
e87f7778 | 2801 | tb_invalidate_phys_range(addr, addr + length); |
ba051fb5 | 2802 | tb_unlock(); |
e87f7778 | 2803 | dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE); |
51d7a9eb | 2804 | } |
e87f7778 | 2805 | cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask); |
51d7a9eb AP |
2806 | } |
2807 | ||
23326164 | 2808 | static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) |
82f2563f | 2809 | { |
e1622f4b | 2810 | unsigned access_size_max = mr->ops->valid.max_access_size; |
23326164 RH |
2811 | |
2812 | /* Regions are assumed to support 1-4 byte accesses unless | |
2813 | otherwise specified. */ | |
23326164 RH |
2814 | if (access_size_max == 0) { |
2815 | access_size_max = 4; | |
2816 | } | |
2817 | ||
2818 | /* Bound the maximum access by the alignment of the address. */ | |
2819 | if (!mr->ops->impl.unaligned) { | |
2820 | unsigned align_size_max = addr & -addr; | |
2821 | if (align_size_max != 0 && align_size_max < access_size_max) { | |
2822 | access_size_max = align_size_max; | |
2823 | } | |
82f2563f | 2824 | } |
23326164 RH |
2825 | |
2826 | /* Don't attempt accesses larger than the maximum. */ | |
2827 | if (l > access_size_max) { | |
2828 | l = access_size_max; | |
82f2563f | 2829 | } |
6554f5c0 | 2830 | l = pow2floor(l); |
23326164 RH |
2831 | |
2832 | return l; | |
82f2563f PB |
2833 | } |
2834 | ||
4840f10e | 2835 | static bool prepare_mmio_access(MemoryRegion *mr) |
125b3806 | 2836 | { |
4840f10e JK |
2837 | bool unlocked = !qemu_mutex_iothread_locked(); |
2838 | bool release_lock = false; | |
2839 | ||
2840 | if (unlocked && mr->global_locking) { | |
2841 | qemu_mutex_lock_iothread(); | |
2842 | unlocked = false; | |
2843 | release_lock = true; | |
2844 | } | |
125b3806 | 2845 | if (mr->flush_coalesced_mmio) { |
4840f10e JK |
2846 | if (unlocked) { |
2847 | qemu_mutex_lock_iothread(); | |
2848 | } | |
125b3806 | 2849 | qemu_flush_coalesced_mmio_buffer(); |
4840f10e JK |
2850 | if (unlocked) { |
2851 | qemu_mutex_unlock_iothread(); | |
2852 | } | |
125b3806 | 2853 | } |
4840f10e JK |
2854 | |
2855 | return release_lock; | |
125b3806 PB |
2856 | } |
2857 | ||
a203ac70 | 2858 | /* Called within RCU critical section. */ |
16620684 AK |
2859 | static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, |
2860 | MemTxAttrs attrs, | |
2861 | const uint8_t *buf, | |
2862 | int len, hwaddr addr1, | |
2863 | hwaddr l, MemoryRegion *mr) | |
13eb76e0 | 2864 | { |
13eb76e0 | 2865 | uint8_t *ptr; |
791af8c8 | 2866 | uint64_t val; |
3b643495 | 2867 | MemTxResult result = MEMTX_OK; |
4840f10e | 2868 | bool release_lock = false; |
3b46e624 | 2869 | |
a203ac70 | 2870 | for (;;) { |
eb7eeb88 PB |
2871 | if (!memory_access_is_direct(mr, true)) { |
2872 | release_lock |= prepare_mmio_access(mr); | |
2873 | l = memory_access_size(mr, l, addr1); | |
2874 | /* XXX: could force current_cpu to NULL to avoid | |
2875 | potential bugs */ | |
2876 | switch (l) { | |
2877 | case 8: | |
2878 | /* 64 bit write access */ | |
2879 | val = ldq_p(buf); | |
2880 | result |= memory_region_dispatch_write(mr, addr1, val, 8, | |
2881 | attrs); | |
2882 | break; | |
2883 | case 4: | |
2884 | /* 32 bit write access */ | |
6da67de6 | 2885 | val = (uint32_t)ldl_p(buf); |
eb7eeb88 PB |
2886 | result |= memory_region_dispatch_write(mr, addr1, val, 4, |
2887 | attrs); | |
2888 | break; | |
2889 | case 2: | |
2890 | /* 16 bit write access */ | |
2891 | val = lduw_p(buf); | |
2892 | result |= memory_region_dispatch_write(mr, addr1, val, 2, | |
2893 | attrs); | |
2894 | break; | |
2895 | case 1: | |
2896 | /* 8 bit write access */ | |
2897 | val = ldub_p(buf); | |
2898 | result |= memory_region_dispatch_write(mr, addr1, val, 1, | |
2899 | attrs); | |
2900 | break; | |
2901 | default: | |
2902 | abort(); | |
13eb76e0 FB |
2903 | } |
2904 | } else { | |
eb7eeb88 | 2905 | /* RAM case */ |
f5aa69bd | 2906 | ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); |
eb7eeb88 PB |
2907 | memcpy(ptr, buf, l); |
2908 | invalidate_and_set_dirty(mr, addr1, l); | |
13eb76e0 | 2909 | } |
4840f10e JK |
2910 | |
2911 | if (release_lock) { | |
2912 | qemu_mutex_unlock_iothread(); | |
2913 | release_lock = false; | |
2914 | } | |
2915 | ||
13eb76e0 FB |
2916 | len -= l; |
2917 | buf += l; | |
2918 | addr += l; | |
a203ac70 PB |
2919 | |
2920 | if (!len) { | |
2921 | break; | |
2922 | } | |
2923 | ||
2924 | l = len; | |
16620684 | 2925 | mr = flatview_translate(fv, addr, &addr1, &l, true); |
13eb76e0 | 2926 | } |
fd8aaa76 | 2927 | |
3b643495 | 2928 | return result; |
13eb76e0 | 2929 | } |
8df1cd07 | 2930 | |
16620684 AK |
2931 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, |
2932 | const uint8_t *buf, int len) | |
ac1970fb | 2933 | { |
eb7eeb88 | 2934 | hwaddr l; |
eb7eeb88 PB |
2935 | hwaddr addr1; |
2936 | MemoryRegion *mr; | |
2937 | MemTxResult result = MEMTX_OK; | |
eb7eeb88 | 2938 | |
a203ac70 PB |
2939 | if (len > 0) { |
2940 | rcu_read_lock(); | |
eb7eeb88 | 2941 | l = len; |
16620684 AK |
2942 | mr = flatview_translate(fv, addr, &addr1, &l, true); |
2943 | result = flatview_write_continue(fv, addr, attrs, buf, len, | |
2944 | addr1, l, mr); | |
a203ac70 PB |
2945 | rcu_read_unlock(); |
2946 | } | |
2947 | ||
2948 | return result; | |
2949 | } | |
2950 | ||
16620684 AK |
2951 | MemTxResult address_space_write(AddressSpace *as, hwaddr addr, |
2952 | MemTxAttrs attrs, | |
2953 | const uint8_t *buf, int len) | |
2954 | { | |
2955 | return flatview_write(address_space_to_flatview(as), addr, attrs, buf, len); | |
2956 | } | |
2957 | ||
a203ac70 | 2958 | /* Called within RCU critical section. */ |
16620684 AK |
2959 | MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, |
2960 | MemTxAttrs attrs, uint8_t *buf, | |
2961 | int len, hwaddr addr1, hwaddr l, | |
2962 | MemoryRegion *mr) | |
a203ac70 PB |
2963 | { |
2964 | uint8_t *ptr; | |
2965 | uint64_t val; | |
2966 | MemTxResult result = MEMTX_OK; | |
2967 | bool release_lock = false; | |
eb7eeb88 | 2968 | |
a203ac70 | 2969 | for (;;) { |
eb7eeb88 PB |
2970 | if (!memory_access_is_direct(mr, false)) { |
2971 | /* I/O case */ | |
2972 | release_lock |= prepare_mmio_access(mr); | |
2973 | l = memory_access_size(mr, l, addr1); | |
2974 | switch (l) { | |
2975 | case 8: | |
2976 | /* 64 bit read access */ | |
2977 | result |= memory_region_dispatch_read(mr, addr1, &val, 8, | |
2978 | attrs); | |
2979 | stq_p(buf, val); | |
2980 | break; | |
2981 | case 4: | |
2982 | /* 32 bit read access */ | |
2983 | result |= memory_region_dispatch_read(mr, addr1, &val, 4, | |
2984 | attrs); | |
2985 | stl_p(buf, val); | |
2986 | break; | |
2987 | case 2: | |
2988 | /* 16 bit read access */ | |
2989 | result |= memory_region_dispatch_read(mr, addr1, &val, 2, | |
2990 | attrs); | |
2991 | stw_p(buf, val); | |
2992 | break; | |
2993 | case 1: | |
2994 | /* 8 bit read access */ | |
2995 | result |= memory_region_dispatch_read(mr, addr1, &val, 1, | |
2996 | attrs); | |
2997 | stb_p(buf, val); | |
2998 | break; | |
2999 | default: | |
3000 | abort(); | |
3001 | } | |
3002 | } else { | |
3003 | /* RAM case */ | |
f5aa69bd | 3004 | ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); |
eb7eeb88 PB |
3005 | memcpy(buf, ptr, l); |
3006 | } | |
3007 | ||
3008 | if (release_lock) { | |
3009 | qemu_mutex_unlock_iothread(); | |
3010 | release_lock = false; | |
3011 | } | |
3012 | ||
3013 | len -= l; | |
3014 | buf += l; | |
3015 | addr += l; | |
a203ac70 PB |
3016 | |
3017 | if (!len) { | |
3018 | break; | |
3019 | } | |
3020 | ||
3021 | l = len; | |
16620684 | 3022 | mr = flatview_translate(fv, addr, &addr1, &l, false); |
a203ac70 PB |
3023 | } |
3024 | ||
3025 | return result; | |
3026 | } | |
3027 | ||
16620684 AK |
3028 | MemTxResult flatview_read_full(FlatView *fv, hwaddr addr, |
3029 | MemTxAttrs attrs, uint8_t *buf, int len) | |
a203ac70 PB |
3030 | { |
3031 | hwaddr l; | |
3032 | hwaddr addr1; | |
3033 | MemoryRegion *mr; | |
3034 | MemTxResult result = MEMTX_OK; | |
3035 | ||
3036 | if (len > 0) { | |
3037 | rcu_read_lock(); | |
3038 | l = len; | |
16620684 AK |
3039 | mr = flatview_translate(fv, addr, &addr1, &l, false); |
3040 | result = flatview_read_continue(fv, addr, attrs, buf, len, | |
3041 | addr1, l, mr); | |
a203ac70 | 3042 | rcu_read_unlock(); |
eb7eeb88 | 3043 | } |
eb7eeb88 PB |
3044 | |
3045 | return result; | |
ac1970fb AK |
3046 | } |
3047 | ||
16620684 AK |
3048 | static MemTxResult flatview_rw(FlatView *fv, hwaddr addr, MemTxAttrs attrs, |
3049 | uint8_t *buf, int len, bool is_write) | |
eb7eeb88 PB |
3050 | { |
3051 | if (is_write) { | |
16620684 | 3052 | return flatview_write(fv, addr, attrs, (uint8_t *)buf, len); |
eb7eeb88 | 3053 | } else { |
16620684 | 3054 | return flatview_read(fv, addr, attrs, (uint8_t *)buf, len); |
eb7eeb88 PB |
3055 | } |
3056 | } | |
ac1970fb | 3057 | |
16620684 AK |
3058 | MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, |
3059 | MemTxAttrs attrs, uint8_t *buf, | |
3060 | int len, bool is_write) | |
3061 | { | |
3062 | return flatview_rw(address_space_to_flatview(as), | |
3063 | addr, attrs, buf, len, is_write); | |
3064 | } | |
3065 | ||
a8170e5e | 3066 | void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, |
ac1970fb AK |
3067 | int len, int is_write) |
3068 | { | |
5c9eb028 PM |
3069 | address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED, |
3070 | buf, len, is_write); | |
ac1970fb AK |
3071 | } |
3072 | ||
582b55a9 AG |
3073 | enum write_rom_type { |
3074 | WRITE_DATA, | |
3075 | FLUSH_CACHE, | |
3076 | }; | |
3077 | ||
2a221651 | 3078 | static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as, |
582b55a9 | 3079 | hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type) |
d0ecd2aa | 3080 | { |
149f54b5 | 3081 | hwaddr l; |
d0ecd2aa | 3082 | uint8_t *ptr; |
149f54b5 | 3083 | hwaddr addr1; |
5c8a00ce | 3084 | MemoryRegion *mr; |
3b46e624 | 3085 | |
41063e1e | 3086 | rcu_read_lock(); |
d0ecd2aa | 3087 | while (len > 0) { |
149f54b5 | 3088 | l = len; |
2a221651 | 3089 | mr = address_space_translate(as, addr, &addr1, &l, true); |
3b46e624 | 3090 | |
5c8a00ce PB |
3091 | if (!(memory_region_is_ram(mr) || |
3092 | memory_region_is_romd(mr))) { | |
b242e0e0 | 3093 | l = memory_access_size(mr, l, addr1); |
d0ecd2aa | 3094 | } else { |
d0ecd2aa | 3095 | /* ROM/RAM case */ |
0878d0e1 | 3096 | ptr = qemu_map_ram_ptr(mr->ram_block, addr1); |
582b55a9 AG |
3097 | switch (type) { |
3098 | case WRITE_DATA: | |
3099 | memcpy(ptr, buf, l); | |
845b6214 | 3100 | invalidate_and_set_dirty(mr, addr1, l); |
582b55a9 AG |
3101 | break; |
3102 | case FLUSH_CACHE: | |
3103 | flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l); | |
3104 | break; | |
3105 | } | |
d0ecd2aa FB |
3106 | } |
3107 | len -= l; | |
3108 | buf += l; | |
3109 | addr += l; | |
3110 | } | |
41063e1e | 3111 | rcu_read_unlock(); |
d0ecd2aa FB |
3112 | } |
3113 | ||
582b55a9 | 3114 | /* used for ROM loading : can write in RAM and ROM */ |
2a221651 | 3115 | void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr, |
582b55a9 AG |
3116 | const uint8_t *buf, int len) |
3117 | { | |
2a221651 | 3118 | cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA); |
582b55a9 AG |
3119 | } |
3120 | ||
3121 | void cpu_flush_icache_range(hwaddr start, int len) | |
3122 | { | |
3123 | /* | |
3124 | * This function should do the same thing as an icache flush that was | |
3125 | * triggered from within the guest. For TCG we are always cache coherent, | |
3126 | * so there is no need to flush anything. For KVM / Xen we need to flush | |
3127 | * the host's instruction cache at least. | |
3128 | */ | |
3129 | if (tcg_enabled()) { | |
3130 | return; | |
3131 | } | |
3132 | ||
2a221651 EI |
3133 | cpu_physical_memory_write_rom_internal(&address_space_memory, |
3134 | start, NULL, len, FLUSH_CACHE); | |
582b55a9 AG |
3135 | } |
3136 | ||
6d16c2f8 | 3137 | typedef struct { |
d3e71559 | 3138 | MemoryRegion *mr; |
6d16c2f8 | 3139 | void *buffer; |
a8170e5e AK |
3140 | hwaddr addr; |
3141 | hwaddr len; | |
c2cba0ff | 3142 | bool in_use; |
6d16c2f8 AL |
3143 | } BounceBuffer; |
3144 | ||
3145 | static BounceBuffer bounce; | |
3146 | ||
ba223c29 | 3147 | typedef struct MapClient { |
e95205e1 | 3148 | QEMUBH *bh; |
72cf2d4f | 3149 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
3150 | } MapClient; |
3151 | ||
38e047b5 | 3152 | QemuMutex map_client_list_lock; |
72cf2d4f BS |
3153 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
3154 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
ba223c29 | 3155 | |
e95205e1 FZ |
3156 | static void cpu_unregister_map_client_do(MapClient *client) |
3157 | { | |
3158 | QLIST_REMOVE(client, link); | |
3159 | g_free(client); | |
3160 | } | |
3161 | ||
33b6c2ed FZ |
3162 | static void cpu_notify_map_clients_locked(void) |
3163 | { | |
3164 | MapClient *client; | |
3165 | ||
3166 | while (!QLIST_EMPTY(&map_client_list)) { | |
3167 | client = QLIST_FIRST(&map_client_list); | |
e95205e1 FZ |
3168 | qemu_bh_schedule(client->bh); |
3169 | cpu_unregister_map_client_do(client); | |
33b6c2ed FZ |
3170 | } |
3171 | } | |
3172 | ||
e95205e1 | 3173 | void cpu_register_map_client(QEMUBH *bh) |
ba223c29 | 3174 | { |
7267c094 | 3175 | MapClient *client = g_malloc(sizeof(*client)); |
ba223c29 | 3176 | |
38e047b5 | 3177 | qemu_mutex_lock(&map_client_list_lock); |
e95205e1 | 3178 | client->bh = bh; |
72cf2d4f | 3179 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
33b6c2ed FZ |
3180 | if (!atomic_read(&bounce.in_use)) { |
3181 | cpu_notify_map_clients_locked(); | |
3182 | } | |
38e047b5 | 3183 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
3184 | } |
3185 | ||
38e047b5 | 3186 | void cpu_exec_init_all(void) |
ba223c29 | 3187 | { |
38e047b5 | 3188 | qemu_mutex_init(&ram_list.mutex); |
20bccb82 PM |
3189 | /* The data structures we set up here depend on knowing the page size, |
3190 | * so no more changes can be made after this point. | |
3191 | * In an ideal world, nothing we did before we had finished the | |
3192 | * machine setup would care about the target page size, and we could | |
3193 | * do this much later, rather than requiring board models to state | |
3194 | * up front what their requirements are. | |
3195 | */ | |
3196 | finalize_target_page_bits(); | |
38e047b5 | 3197 | io_mem_init(); |
680a4783 | 3198 | memory_map_init(); |
38e047b5 | 3199 | qemu_mutex_init(&map_client_list_lock); |
ba223c29 AL |
3200 | } |
3201 | ||
e95205e1 | 3202 | void cpu_unregister_map_client(QEMUBH *bh) |
ba223c29 AL |
3203 | { |
3204 | MapClient *client; | |
3205 | ||
e95205e1 FZ |
3206 | qemu_mutex_lock(&map_client_list_lock); |
3207 | QLIST_FOREACH(client, &map_client_list, link) { | |
3208 | if (client->bh == bh) { | |
3209 | cpu_unregister_map_client_do(client); | |
3210 | break; | |
3211 | } | |
ba223c29 | 3212 | } |
e95205e1 | 3213 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
3214 | } |
3215 | ||
3216 | static void cpu_notify_map_clients(void) | |
3217 | { | |
38e047b5 | 3218 | qemu_mutex_lock(&map_client_list_lock); |
33b6c2ed | 3219 | cpu_notify_map_clients_locked(); |
38e047b5 | 3220 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
3221 | } |
3222 | ||
16620684 AK |
3223 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, |
3224 | bool is_write) | |
51644ab7 | 3225 | { |
5c8a00ce | 3226 | MemoryRegion *mr; |
51644ab7 PB |
3227 | hwaddr l, xlat; |
3228 | ||
41063e1e | 3229 | rcu_read_lock(); |
51644ab7 PB |
3230 | while (len > 0) { |
3231 | l = len; | |
16620684 | 3232 | mr = flatview_translate(fv, addr, &xlat, &l, is_write); |
5c8a00ce PB |
3233 | if (!memory_access_is_direct(mr, is_write)) { |
3234 | l = memory_access_size(mr, l, addr); | |
3235 | if (!memory_region_access_valid(mr, xlat, l, is_write)) { | |
5ad4a2b7 | 3236 | rcu_read_unlock(); |
51644ab7 PB |
3237 | return false; |
3238 | } | |
3239 | } | |
3240 | ||
3241 | len -= l; | |
3242 | addr += l; | |
3243 | } | |
41063e1e | 3244 | rcu_read_unlock(); |
51644ab7 PB |
3245 | return true; |
3246 | } | |
3247 | ||
16620684 AK |
3248 | bool address_space_access_valid(AddressSpace *as, hwaddr addr, |
3249 | int len, bool is_write) | |
3250 | { | |
3251 | return flatview_access_valid(address_space_to_flatview(as), | |
3252 | addr, len, is_write); | |
3253 | } | |
3254 | ||
715c31ec | 3255 | static hwaddr |
16620684 AK |
3256 | flatview_extend_translation(FlatView *fv, hwaddr addr, |
3257 | hwaddr target_len, | |
715c31ec PB |
3258 | MemoryRegion *mr, hwaddr base, hwaddr len, |
3259 | bool is_write) | |
3260 | { | |
3261 | hwaddr done = 0; | |
3262 | hwaddr xlat; | |
3263 | MemoryRegion *this_mr; | |
3264 | ||
3265 | for (;;) { | |
3266 | target_len -= len; | |
3267 | addr += len; | |
3268 | done += len; | |
3269 | if (target_len == 0) { | |
3270 | return done; | |
3271 | } | |
3272 | ||
3273 | len = target_len; | |
16620684 AK |
3274 | this_mr = flatview_translate(fv, addr, &xlat, |
3275 | &len, is_write); | |
715c31ec PB |
3276 | if (this_mr != mr || xlat != base + done) { |
3277 | return done; | |
3278 | } | |
3279 | } | |
3280 | } | |
3281 | ||
6d16c2f8 AL |
3282 | /* Map a physical memory region into a host virtual address. |
3283 | * May map a subset of the requested range, given by and returned in *plen. | |
3284 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3285 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
3286 | * Use cpu_register_map_client() to know when retrying the map operation is |
3287 | * likely to succeed. | |
6d16c2f8 | 3288 | */ |
ac1970fb | 3289 | void *address_space_map(AddressSpace *as, |
a8170e5e AK |
3290 | hwaddr addr, |
3291 | hwaddr *plen, | |
ac1970fb | 3292 | bool is_write) |
6d16c2f8 | 3293 | { |
a8170e5e | 3294 | hwaddr len = *plen; |
715c31ec PB |
3295 | hwaddr l, xlat; |
3296 | MemoryRegion *mr; | |
e81bcda5 | 3297 | void *ptr; |
16620684 | 3298 | FlatView *fv = address_space_to_flatview(as); |
6d16c2f8 | 3299 | |
e3127ae0 PB |
3300 | if (len == 0) { |
3301 | return NULL; | |
3302 | } | |
38bee5dc | 3303 | |
e3127ae0 | 3304 | l = len; |
41063e1e | 3305 | rcu_read_lock(); |
16620684 | 3306 | mr = flatview_translate(fv, addr, &xlat, &l, is_write); |
41063e1e | 3307 | |
e3127ae0 | 3308 | if (!memory_access_is_direct(mr, is_write)) { |
c2cba0ff | 3309 | if (atomic_xchg(&bounce.in_use, true)) { |
41063e1e | 3310 | rcu_read_unlock(); |
e3127ae0 | 3311 | return NULL; |
6d16c2f8 | 3312 | } |
e85d9db5 KW |
3313 | /* Avoid unbounded allocations */ |
3314 | l = MIN(l, TARGET_PAGE_SIZE); | |
3315 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l); | |
e3127ae0 PB |
3316 | bounce.addr = addr; |
3317 | bounce.len = l; | |
d3e71559 PB |
3318 | |
3319 | memory_region_ref(mr); | |
3320 | bounce.mr = mr; | |
e3127ae0 | 3321 | if (!is_write) { |
16620684 | 3322 | flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED, |
5c9eb028 | 3323 | bounce.buffer, l); |
8ab934f9 | 3324 | } |
6d16c2f8 | 3325 | |
41063e1e | 3326 | rcu_read_unlock(); |
e3127ae0 PB |
3327 | *plen = l; |
3328 | return bounce.buffer; | |
3329 | } | |
3330 | ||
e3127ae0 | 3331 | |
d3e71559 | 3332 | memory_region_ref(mr); |
16620684 AK |
3333 | *plen = flatview_extend_translation(fv, addr, len, mr, xlat, |
3334 | l, is_write); | |
f5aa69bd | 3335 | ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true); |
e81bcda5 PB |
3336 | rcu_read_unlock(); |
3337 | ||
3338 | return ptr; | |
6d16c2f8 AL |
3339 | } |
3340 | ||
ac1970fb | 3341 | /* Unmaps a memory region previously mapped by address_space_map(). |
6d16c2f8 AL |
3342 | * Will also mark the memory as dirty if is_write == 1. access_len gives |
3343 | * the amount of memory that was actually read or written by the caller. | |
3344 | */ | |
a8170e5e AK |
3345 | void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, |
3346 | int is_write, hwaddr access_len) | |
6d16c2f8 AL |
3347 | { |
3348 | if (buffer != bounce.buffer) { | |
d3e71559 PB |
3349 | MemoryRegion *mr; |
3350 | ram_addr_t addr1; | |
3351 | ||
07bdaa41 | 3352 | mr = memory_region_from_host(buffer, &addr1); |
d3e71559 | 3353 | assert(mr != NULL); |
6d16c2f8 | 3354 | if (is_write) { |
845b6214 | 3355 | invalidate_and_set_dirty(mr, addr1, access_len); |
6d16c2f8 | 3356 | } |
868bb33f | 3357 | if (xen_enabled()) { |
e41d7c69 | 3358 | xen_invalidate_map_cache_entry(buffer); |
050a0ddf | 3359 | } |
d3e71559 | 3360 | memory_region_unref(mr); |
6d16c2f8 AL |
3361 | return; |
3362 | } | |
3363 | if (is_write) { | |
5c9eb028 PM |
3364 | address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED, |
3365 | bounce.buffer, access_len); | |
6d16c2f8 | 3366 | } |
f8a83245 | 3367 | qemu_vfree(bounce.buffer); |
6d16c2f8 | 3368 | bounce.buffer = NULL; |
d3e71559 | 3369 | memory_region_unref(bounce.mr); |
c2cba0ff | 3370 | atomic_mb_set(&bounce.in_use, false); |
ba223c29 | 3371 | cpu_notify_map_clients(); |
6d16c2f8 | 3372 | } |
d0ecd2aa | 3373 | |
a8170e5e AK |
3374 | void *cpu_physical_memory_map(hwaddr addr, |
3375 | hwaddr *plen, | |
ac1970fb AK |
3376 | int is_write) |
3377 | { | |
3378 | return address_space_map(&address_space_memory, addr, plen, is_write); | |
3379 | } | |
3380 | ||
a8170e5e AK |
3381 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
3382 | int is_write, hwaddr access_len) | |
ac1970fb AK |
3383 | { |
3384 | return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len); | |
3385 | } | |
3386 | ||
0ce265ff PB |
3387 | #define ARG1_DECL AddressSpace *as |
3388 | #define ARG1 as | |
3389 | #define SUFFIX | |
3390 | #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__) | |
3391 | #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write) | |
3392 | #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs) | |
3393 | #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len) | |
3394 | #define RCU_READ_LOCK(...) rcu_read_lock() | |
3395 | #define RCU_READ_UNLOCK(...) rcu_read_unlock() | |
3396 | #include "memory_ldst.inc.c" | |
1e78bcc1 | 3397 | |
1f4e496e PB |
3398 | int64_t address_space_cache_init(MemoryRegionCache *cache, |
3399 | AddressSpace *as, | |
3400 | hwaddr addr, | |
3401 | hwaddr len, | |
3402 | bool is_write) | |
3403 | { | |
90c4fe5f PB |
3404 | cache->len = len; |
3405 | cache->as = as; | |
3406 | cache->xlat = addr; | |
3407 | return len; | |
1f4e496e PB |
3408 | } |
3409 | ||
3410 | void address_space_cache_invalidate(MemoryRegionCache *cache, | |
3411 | hwaddr addr, | |
3412 | hwaddr access_len) | |
3413 | { | |
1f4e496e PB |
3414 | } |
3415 | ||
3416 | void address_space_cache_destroy(MemoryRegionCache *cache) | |
3417 | { | |
90c4fe5f | 3418 | cache->as = NULL; |
1f4e496e PB |
3419 | } |
3420 | ||
3421 | #define ARG1_DECL MemoryRegionCache *cache | |
3422 | #define ARG1 cache | |
3423 | #define SUFFIX _cached | |
90c4fe5f PB |
3424 | #define TRANSLATE(addr, ...) \ |
3425 | address_space_translate(cache->as, cache->xlat + (addr), __VA_ARGS__) | |
1f4e496e | 3426 | #define IS_DIRECT(mr, is_write) true |
90c4fe5f PB |
3427 | #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs) |
3428 | #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len) | |
3429 | #define RCU_READ_LOCK() rcu_read_lock() | |
3430 | #define RCU_READ_UNLOCK() rcu_read_unlock() | |
1f4e496e PB |
3431 | #include "memory_ldst.inc.c" |
3432 | ||
5e2972fd | 3433 | /* virtual memory access for debug (includes writing to ROM) */ |
f17ec444 | 3434 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
b448f2f3 | 3435 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
3436 | { |
3437 | int l; | |
a8170e5e | 3438 | hwaddr phys_addr; |
9b3c35e0 | 3439 | target_ulong page; |
13eb76e0 | 3440 | |
79ca7a1b | 3441 | cpu_synchronize_state(cpu); |
13eb76e0 | 3442 | while (len > 0) { |
5232e4c7 PM |
3443 | int asidx; |
3444 | MemTxAttrs attrs; | |
3445 | ||
13eb76e0 | 3446 | page = addr & TARGET_PAGE_MASK; |
5232e4c7 PM |
3447 | phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs); |
3448 | asidx = cpu_asidx_from_attrs(cpu, attrs); | |
13eb76e0 FB |
3449 | /* if no physical page mapped, return an error */ |
3450 | if (phys_addr == -1) | |
3451 | return -1; | |
3452 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3453 | if (l > len) | |
3454 | l = len; | |
5e2972fd | 3455 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
2e38847b | 3456 | if (is_write) { |
5232e4c7 PM |
3457 | cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as, |
3458 | phys_addr, buf, l); | |
2e38847b | 3459 | } else { |
5232e4c7 PM |
3460 | address_space_rw(cpu->cpu_ases[asidx].as, phys_addr, |
3461 | MEMTXATTRS_UNSPECIFIED, | |
5c9eb028 | 3462 | buf, l, 0); |
2e38847b | 3463 | } |
13eb76e0 FB |
3464 | len -= l; |
3465 | buf += l; | |
3466 | addr += l; | |
3467 | } | |
3468 | return 0; | |
3469 | } | |
038629a6 DDAG |
3470 | |
3471 | /* | |
3472 | * Allows code that needs to deal with migration bitmaps etc to still be built | |
3473 | * target independent. | |
3474 | */ | |
20afaed9 | 3475 | size_t qemu_target_page_size(void) |
038629a6 | 3476 | { |
20afaed9 | 3477 | return TARGET_PAGE_SIZE; |
038629a6 DDAG |
3478 | } |
3479 | ||
46d702b1 JQ |
3480 | int qemu_target_page_bits(void) |
3481 | { | |
3482 | return TARGET_PAGE_BITS; | |
3483 | } | |
3484 | ||
3485 | int qemu_target_page_bits_min(void) | |
3486 | { | |
3487 | return TARGET_PAGE_BITS_MIN; | |
3488 | } | |
a68fe89c | 3489 | #endif |
13eb76e0 | 3490 | |
8e4a424b BS |
3491 | /* |
3492 | * A helper function for the _utterly broken_ virtio device model to find out if | |
3493 | * it's running on a big endian machine. Don't do this at home kids! | |
3494 | */ | |
98ed8ecf GK |
3495 | bool target_words_bigendian(void); |
3496 | bool target_words_bigendian(void) | |
8e4a424b BS |
3497 | { |
3498 | #if defined(TARGET_WORDS_BIGENDIAN) | |
3499 | return true; | |
3500 | #else | |
3501 | return false; | |
3502 | #endif | |
3503 | } | |
3504 | ||
76f35538 | 3505 | #ifndef CONFIG_USER_ONLY |
a8170e5e | 3506 | bool cpu_physical_memory_is_io(hwaddr phys_addr) |
76f35538 | 3507 | { |
5c8a00ce | 3508 | MemoryRegion*mr; |
149f54b5 | 3509 | hwaddr l = 1; |
41063e1e | 3510 | bool res; |
76f35538 | 3511 | |
41063e1e | 3512 | rcu_read_lock(); |
5c8a00ce PB |
3513 | mr = address_space_translate(&address_space_memory, |
3514 | phys_addr, &phys_addr, &l, false); | |
76f35538 | 3515 | |
41063e1e PB |
3516 | res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr)); |
3517 | rcu_read_unlock(); | |
3518 | return res; | |
76f35538 | 3519 | } |
bd2fa51f | 3520 | |
e3807054 | 3521 | int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque) |
bd2fa51f MH |
3522 | { |
3523 | RAMBlock *block; | |
e3807054 | 3524 | int ret = 0; |
bd2fa51f | 3525 | |
0dc3f44a | 3526 | rcu_read_lock(); |
99e15582 | 3527 | RAMBLOCK_FOREACH(block) { |
e3807054 DDAG |
3528 | ret = func(block->idstr, block->host, block->offset, |
3529 | block->used_length, opaque); | |
3530 | if (ret) { | |
3531 | break; | |
3532 | } | |
bd2fa51f | 3533 | } |
0dc3f44a | 3534 | rcu_read_unlock(); |
e3807054 | 3535 | return ret; |
bd2fa51f | 3536 | } |
d3a5038c DDAG |
3537 | |
3538 | /* | |
3539 | * Unmap pages of memory from start to start+length such that | |
3540 | * they a) read as 0, b) Trigger whatever fault mechanism | |
3541 | * the OS provides for postcopy. | |
3542 | * The pages must be unmapped by the end of the function. | |
3543 | * Returns: 0 on success, none-0 on failure | |
3544 | * | |
3545 | */ | |
3546 | int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length) | |
3547 | { | |
3548 | int ret = -1; | |
3549 | ||
3550 | uint8_t *host_startaddr = rb->host + start; | |
3551 | ||
3552 | if ((uintptr_t)host_startaddr & (rb->page_size - 1)) { | |
3553 | error_report("ram_block_discard_range: Unaligned start address: %p", | |
3554 | host_startaddr); | |
3555 | goto err; | |
3556 | } | |
3557 | ||
3558 | if ((start + length) <= rb->used_length) { | |
3559 | uint8_t *host_endaddr = host_startaddr + length; | |
3560 | if ((uintptr_t)host_endaddr & (rb->page_size - 1)) { | |
3561 | error_report("ram_block_discard_range: Unaligned end address: %p", | |
3562 | host_endaddr); | |
3563 | goto err; | |
3564 | } | |
3565 | ||
3566 | errno = ENOTSUP; /* If we are missing MADVISE etc */ | |
3567 | ||
e2fa71f5 | 3568 | if (rb->page_size == qemu_host_page_size) { |
d3a5038c | 3569 | #if defined(CONFIG_MADVISE) |
e2fa71f5 DDAG |
3570 | /* Note: We need the madvise MADV_DONTNEED behaviour of definitely |
3571 | * freeing the page. | |
3572 | */ | |
3573 | ret = madvise(host_startaddr, length, MADV_DONTNEED); | |
d3a5038c | 3574 | #endif |
e2fa71f5 DDAG |
3575 | } else { |
3576 | /* Huge page case - unfortunately it can't do DONTNEED, but | |
3577 | * it can do the equivalent by FALLOC_FL_PUNCH_HOLE in the | |
3578 | * huge page file. | |
3579 | */ | |
3580 | #ifdef CONFIG_FALLOCATE_PUNCH_HOLE | |
3581 | ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE, | |
3582 | start, length); | |
3583 | #endif | |
3584 | } | |
d3a5038c DDAG |
3585 | if (ret) { |
3586 | ret = -errno; | |
3587 | error_report("ram_block_discard_range: Failed to discard range " | |
3588 | "%s:%" PRIx64 " +%zx (%d)", | |
3589 | rb->idstr, start, length, ret); | |
3590 | } | |
3591 | } else { | |
3592 | error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64 | |
3593 | "/%zx/" RAM_ADDR_FMT")", | |
3594 | rb->idstr, start, length, rb->used_length); | |
3595 | } | |
3596 | ||
3597 | err: | |
3598 | return ret; | |
3599 | } | |
3600 | ||
ec3f8c99 | 3601 | #endif |
a0be0c58 YZ |
3602 | |
3603 | void page_size_init(void) | |
3604 | { | |
3605 | /* NOTE: we can always suppose that qemu_host_page_size >= | |
3606 | TARGET_PAGE_SIZE */ | |
a0be0c58 YZ |
3607 | if (qemu_host_page_size == 0) { |
3608 | qemu_host_page_size = qemu_real_host_page_size; | |
3609 | } | |
3610 | if (qemu_host_page_size < TARGET_PAGE_SIZE) { | |
3611 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
3612 | } | |
3613 | qemu_host_page_mask = -(intptr_t)qemu_host_page_size; | |
3614 | } | |
5e8fd947 AK |
3615 | |
3616 | #if !defined(CONFIG_USER_ONLY) | |
3617 | ||
3618 | static void mtree_print_phys_entries(fprintf_function mon, void *f, | |
3619 | int start, int end, int skip, int ptr) | |
3620 | { | |
3621 | if (start == end - 1) { | |
3622 | mon(f, "\t%3d ", start); | |
3623 | } else { | |
3624 | mon(f, "\t%3d..%-3d ", start, end - 1); | |
3625 | } | |
3626 | mon(f, " skip=%d ", skip); | |
3627 | if (ptr == PHYS_MAP_NODE_NIL) { | |
3628 | mon(f, " ptr=NIL"); | |
3629 | } else if (!skip) { | |
3630 | mon(f, " ptr=#%d", ptr); | |
3631 | } else { | |
3632 | mon(f, " ptr=[%d]", ptr); | |
3633 | } | |
3634 | mon(f, "\n"); | |
3635 | } | |
3636 | ||
3637 | #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \ | |
3638 | int128_sub((size), int128_one())) : 0) | |
3639 | ||
3640 | void mtree_print_dispatch(fprintf_function mon, void *f, | |
3641 | AddressSpaceDispatch *d, MemoryRegion *root) | |
3642 | { | |
3643 | int i; | |
3644 | ||
3645 | mon(f, " Dispatch\n"); | |
3646 | mon(f, " Physical sections\n"); | |
3647 | ||
3648 | for (i = 0; i < d->map.sections_nb; ++i) { | |
3649 | MemoryRegionSection *s = d->map.sections + i; | |
3650 | const char *names[] = { " [unassigned]", " [not dirty]", | |
3651 | " [ROM]", " [watch]" }; | |
3652 | ||
3653 | mon(f, " #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx " %s%s%s%s%s", | |
3654 | i, | |
3655 | s->offset_within_address_space, | |
3656 | s->offset_within_address_space + MR_SIZE(s->mr->size), | |
3657 | s->mr->name ? s->mr->name : "(noname)", | |
3658 | i < ARRAY_SIZE(names) ? names[i] : "", | |
3659 | s->mr == root ? " [ROOT]" : "", | |
3660 | s == d->mru_section ? " [MRU]" : "", | |
3661 | s->mr->is_iommu ? " [iommu]" : ""); | |
3662 | ||
3663 | if (s->mr->alias) { | |
3664 | mon(f, " alias=%s", s->mr->alias->name ? | |
3665 | s->mr->alias->name : "noname"); | |
3666 | } | |
3667 | mon(f, "\n"); | |
3668 | } | |
3669 | ||
3670 | mon(f, " Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n", | |
3671 | P_L2_BITS, P_L2_LEVELS, d->phys_map.ptr, d->phys_map.skip); | |
3672 | for (i = 0; i < d->map.nodes_nb; ++i) { | |
3673 | int j, jprev; | |
3674 | PhysPageEntry prev; | |
3675 | Node *n = d->map.nodes + i; | |
3676 | ||
3677 | mon(f, " [%d]\n", i); | |
3678 | ||
3679 | for (j = 0, jprev = 0, prev = *n[0]; j < ARRAY_SIZE(*n); ++j) { | |
3680 | PhysPageEntry *pe = *n + j; | |
3681 | ||
3682 | if (pe->ptr == prev.ptr && pe->skip == prev.skip) { | |
3683 | continue; | |
3684 | } | |
3685 | ||
3686 | mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr); | |
3687 | ||
3688 | jprev = j; | |
3689 | prev = *pe; | |
3690 | } | |
3691 | ||
3692 | if (jprev != ARRAY_SIZE(*n)) { | |
3693 | mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr); | |
3694 | } | |
3695 | } | |
3696 | } | |
3697 | ||
3698 | #endif |