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Commit | Line | Data |
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54936004 | 1 | /* |
5b6dd868 | 2 | * Virtual page mapping |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
7b31bbc2 | 19 | #include "qemu/osdep.h" |
da34e65c | 20 | #include "qapi/error.h" |
54936004 | 21 | |
f348b6d1 | 22 | #include "qemu/cutils.h" |
6180a181 | 23 | #include "cpu.h" |
63c91552 | 24 | #include "exec/exec-all.h" |
51180423 | 25 | #include "exec/target_page.h" |
b67d9a52 | 26 | #include "tcg.h" |
741da0d3 | 27 | #include "hw/qdev-core.h" |
c7e002c5 | 28 | #include "hw/qdev-properties.h" |
4485bd26 | 29 | #if !defined(CONFIG_USER_ONLY) |
47c8ca53 | 30 | #include "hw/boards.h" |
33c11879 | 31 | #include "hw/xen/xen.h" |
4485bd26 | 32 | #endif |
9c17d615 | 33 | #include "sysemu/kvm.h" |
2ff3de68 | 34 | #include "sysemu/sysemu.h" |
1de7afc9 PB |
35 | #include "qemu/timer.h" |
36 | #include "qemu/config-file.h" | |
75a34036 | 37 | #include "qemu/error-report.h" |
53a5960a | 38 | #if defined(CONFIG_USER_ONLY) |
a9c94277 | 39 | #include "qemu.h" |
432d268c | 40 | #else /* !CONFIG_USER_ONLY */ |
741da0d3 PB |
41 | #include "hw/hw.h" |
42 | #include "exec/memory.h" | |
df43d49c | 43 | #include "exec/ioport.h" |
741da0d3 | 44 | #include "sysemu/dma.h" |
9c607668 | 45 | #include "sysemu/numa.h" |
79ca7a1b | 46 | #include "sysemu/hw_accel.h" |
741da0d3 | 47 | #include "exec/address-spaces.h" |
9c17d615 | 48 | #include "sysemu/xen-mapcache.h" |
0ab8ed18 | 49 | #include "trace-root.h" |
d3a5038c | 50 | |
e2fa71f5 | 51 | #ifdef CONFIG_FALLOCATE_PUNCH_HOLE |
e2fa71f5 DDAG |
52 | #include <linux/falloc.h> |
53 | #endif | |
54 | ||
53a5960a | 55 | #endif |
0dc3f44a | 56 | #include "qemu/rcu_queue.h" |
4840f10e | 57 | #include "qemu/main-loop.h" |
5b6dd868 | 58 | #include "translate-all.h" |
7615936e | 59 | #include "sysemu/replay.h" |
0cac1b66 | 60 | |
022c62cb | 61 | #include "exec/memory-internal.h" |
220c3ebd | 62 | #include "exec/ram_addr.h" |
508127e2 | 63 | #include "exec/log.h" |
67d95c15 | 64 | |
9dfeca7c BR |
65 | #include "migration/vmstate.h" |
66 | ||
b35ba30f | 67 | #include "qemu/range.h" |
794e8f30 MT |
68 | #ifndef _WIN32 |
69 | #include "qemu/mmap-alloc.h" | |
70 | #endif | |
b35ba30f | 71 | |
be9b23c4 PX |
72 | #include "monitor/monitor.h" |
73 | ||
db7b5426 | 74 | //#define DEBUG_SUBPAGE |
1196be37 | 75 | |
e2eef170 | 76 | #if !defined(CONFIG_USER_ONLY) |
0dc3f44a MD |
77 | /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes |
78 | * are protected by the ramlist lock. | |
79 | */ | |
0d53d9fe | 80 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) }; |
62152b8a AK |
81 | |
82 | static MemoryRegion *system_memory; | |
309cb471 | 83 | static MemoryRegion *system_io; |
62152b8a | 84 | |
f6790af6 AK |
85 | AddressSpace address_space_io; |
86 | AddressSpace address_space_memory; | |
2673a5da | 87 | |
0844e007 | 88 | MemoryRegion io_mem_rom, io_mem_notdirty; |
acc9d80b | 89 | static MemoryRegion io_mem_unassigned; |
0e0df1e2 | 90 | |
7bd4f430 PB |
91 | /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */ |
92 | #define RAM_PREALLOC (1 << 0) | |
93 | ||
dbcb8981 PB |
94 | /* RAM is mmap-ed with MAP_SHARED */ |
95 | #define RAM_SHARED (1 << 1) | |
96 | ||
62be4e3a MT |
97 | /* Only a portion of RAM (used_length) is actually used, and migrated. |
98 | * This used_length size can change across reboots. | |
99 | */ | |
100 | #define RAM_RESIZEABLE (1 << 2) | |
101 | ||
e2eef170 | 102 | #endif |
9fa3e853 | 103 | |
20bccb82 PM |
104 | #ifdef TARGET_PAGE_BITS_VARY |
105 | int target_page_bits; | |
106 | bool target_page_bits_decided; | |
107 | #endif | |
108 | ||
bdc44640 | 109 | struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus); |
6a00d601 FB |
110 | /* current CPU in the current thread. It is only valid inside |
111 | cpu_exec() */ | |
f240eb6f | 112 | __thread CPUState *current_cpu; |
2e70f6ef | 113 | /* 0 = Do not count executed instructions. |
bf20dc07 | 114 | 1 = Precise instruction counting. |
2e70f6ef | 115 | 2 = Adaptive rate instruction counting. */ |
5708fc66 | 116 | int use_icount; |
6a00d601 | 117 | |
a0be0c58 YZ |
118 | uintptr_t qemu_host_page_size; |
119 | intptr_t qemu_host_page_mask; | |
a0be0c58 | 120 | |
20bccb82 PM |
121 | bool set_preferred_target_page_bits(int bits) |
122 | { | |
123 | /* The target page size is the lowest common denominator for all | |
124 | * the CPUs in the system, so we can only make it smaller, never | |
125 | * larger. And we can't make it smaller once we've committed to | |
126 | * a particular size. | |
127 | */ | |
128 | #ifdef TARGET_PAGE_BITS_VARY | |
129 | assert(bits >= TARGET_PAGE_BITS_MIN); | |
130 | if (target_page_bits == 0 || target_page_bits > bits) { | |
131 | if (target_page_bits_decided) { | |
132 | return false; | |
133 | } | |
134 | target_page_bits = bits; | |
135 | } | |
136 | #endif | |
137 | return true; | |
138 | } | |
139 | ||
e2eef170 | 140 | #if !defined(CONFIG_USER_ONLY) |
4346ae3e | 141 | |
20bccb82 PM |
142 | static void finalize_target_page_bits(void) |
143 | { | |
144 | #ifdef TARGET_PAGE_BITS_VARY | |
145 | if (target_page_bits == 0) { | |
146 | target_page_bits = TARGET_PAGE_BITS_MIN; | |
147 | } | |
148 | target_page_bits_decided = true; | |
149 | #endif | |
150 | } | |
151 | ||
1db8abb1 PB |
152 | typedef struct PhysPageEntry PhysPageEntry; |
153 | ||
154 | struct PhysPageEntry { | |
9736e55b | 155 | /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */ |
8b795765 | 156 | uint32_t skip : 6; |
9736e55b | 157 | /* index into phys_sections (!skip) or phys_map_nodes (skip) */ |
8b795765 | 158 | uint32_t ptr : 26; |
1db8abb1 PB |
159 | }; |
160 | ||
8b795765 MT |
161 | #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6) |
162 | ||
03f49957 | 163 | /* Size of the L2 (and L3, etc) page tables. */ |
57271d63 | 164 | #define ADDR_SPACE_BITS 64 |
03f49957 | 165 | |
026736ce | 166 | #define P_L2_BITS 9 |
03f49957 PB |
167 | #define P_L2_SIZE (1 << P_L2_BITS) |
168 | ||
169 | #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1) | |
170 | ||
171 | typedef PhysPageEntry Node[P_L2_SIZE]; | |
0475d94f | 172 | |
53cb28cb | 173 | typedef struct PhysPageMap { |
79e2b9ae PB |
174 | struct rcu_head rcu; |
175 | ||
53cb28cb MA |
176 | unsigned sections_nb; |
177 | unsigned sections_nb_alloc; | |
178 | unsigned nodes_nb; | |
179 | unsigned nodes_nb_alloc; | |
180 | Node *nodes; | |
181 | MemoryRegionSection *sections; | |
182 | } PhysPageMap; | |
183 | ||
1db8abb1 | 184 | struct AddressSpaceDispatch { |
729633c2 | 185 | MemoryRegionSection *mru_section; |
1db8abb1 PB |
186 | /* This is a multi-level map on the physical address space. |
187 | * The bottom level has pointers to MemoryRegionSections. | |
188 | */ | |
189 | PhysPageEntry phys_map; | |
53cb28cb | 190 | PhysPageMap map; |
1db8abb1 PB |
191 | }; |
192 | ||
90260c6c JK |
193 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
194 | typedef struct subpage_t { | |
195 | MemoryRegion iomem; | |
16620684 | 196 | FlatView *fv; |
90260c6c | 197 | hwaddr base; |
2615fabd | 198 | uint16_t sub_section[]; |
90260c6c JK |
199 | } subpage_t; |
200 | ||
b41aac4f LPF |
201 | #define PHYS_SECTION_UNASSIGNED 0 |
202 | #define PHYS_SECTION_NOTDIRTY 1 | |
203 | #define PHYS_SECTION_ROM 2 | |
204 | #define PHYS_SECTION_WATCH 3 | |
5312bd8b | 205 | |
e2eef170 | 206 | static void io_mem_init(void); |
62152b8a | 207 | static void memory_map_init(void); |
09daed84 | 208 | static void tcg_commit(MemoryListener *listener); |
e2eef170 | 209 | |
1ec9b909 | 210 | static MemoryRegion io_mem_watch; |
32857f4d PM |
211 | |
212 | /** | |
213 | * CPUAddressSpace: all the information a CPU needs about an AddressSpace | |
214 | * @cpu: the CPU whose AddressSpace this is | |
215 | * @as: the AddressSpace itself | |
216 | * @memory_dispatch: its dispatch pointer (cached, RCU protected) | |
217 | * @tcg_as_listener: listener for tracking changes to the AddressSpace | |
218 | */ | |
219 | struct CPUAddressSpace { | |
220 | CPUState *cpu; | |
221 | AddressSpace *as; | |
222 | struct AddressSpaceDispatch *memory_dispatch; | |
223 | MemoryListener tcg_as_listener; | |
224 | }; | |
225 | ||
8deaf12c GH |
226 | struct DirtyBitmapSnapshot { |
227 | ram_addr_t start; | |
228 | ram_addr_t end; | |
229 | unsigned long dirty[]; | |
230 | }; | |
231 | ||
6658ffb8 | 232 | #endif |
fd6ce8f6 | 233 | |
6d9a1304 | 234 | #if !defined(CONFIG_USER_ONLY) |
d6f2ea22 | 235 | |
53cb28cb | 236 | static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes) |
d6f2ea22 | 237 | { |
101420b8 | 238 | static unsigned alloc_hint = 16; |
53cb28cb | 239 | if (map->nodes_nb + nodes > map->nodes_nb_alloc) { |
101420b8 | 240 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint); |
53cb28cb MA |
241 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes); |
242 | map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc); | |
101420b8 | 243 | alloc_hint = map->nodes_nb_alloc; |
d6f2ea22 | 244 | } |
f7bf5461 AK |
245 | } |
246 | ||
db94604b | 247 | static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf) |
f7bf5461 AK |
248 | { |
249 | unsigned i; | |
8b795765 | 250 | uint32_t ret; |
db94604b PB |
251 | PhysPageEntry e; |
252 | PhysPageEntry *p; | |
f7bf5461 | 253 | |
53cb28cb | 254 | ret = map->nodes_nb++; |
db94604b | 255 | p = map->nodes[ret]; |
f7bf5461 | 256 | assert(ret != PHYS_MAP_NODE_NIL); |
53cb28cb | 257 | assert(ret != map->nodes_nb_alloc); |
db94604b PB |
258 | |
259 | e.skip = leaf ? 0 : 1; | |
260 | e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL; | |
03f49957 | 261 | for (i = 0; i < P_L2_SIZE; ++i) { |
db94604b | 262 | memcpy(&p[i], &e, sizeof(e)); |
d6f2ea22 | 263 | } |
f7bf5461 | 264 | return ret; |
d6f2ea22 AK |
265 | } |
266 | ||
53cb28cb MA |
267 | static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp, |
268 | hwaddr *index, hwaddr *nb, uint16_t leaf, | |
2999097b | 269 | int level) |
f7bf5461 AK |
270 | { |
271 | PhysPageEntry *p; | |
03f49957 | 272 | hwaddr step = (hwaddr)1 << (level * P_L2_BITS); |
108c49b8 | 273 | |
9736e55b | 274 | if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) { |
db94604b | 275 | lp->ptr = phys_map_node_alloc(map, level == 0); |
92e873b9 | 276 | } |
db94604b | 277 | p = map->nodes[lp->ptr]; |
03f49957 | 278 | lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
f7bf5461 | 279 | |
03f49957 | 280 | while (*nb && lp < &p[P_L2_SIZE]) { |
07f07b31 | 281 | if ((*index & (step - 1)) == 0 && *nb >= step) { |
9736e55b | 282 | lp->skip = 0; |
c19e8800 | 283 | lp->ptr = leaf; |
07f07b31 AK |
284 | *index += step; |
285 | *nb -= step; | |
2999097b | 286 | } else { |
53cb28cb | 287 | phys_page_set_level(map, lp, index, nb, leaf, level - 1); |
2999097b AK |
288 | } |
289 | ++lp; | |
f7bf5461 AK |
290 | } |
291 | } | |
292 | ||
ac1970fb | 293 | static void phys_page_set(AddressSpaceDispatch *d, |
a8170e5e | 294 | hwaddr index, hwaddr nb, |
2999097b | 295 | uint16_t leaf) |
f7bf5461 | 296 | { |
2999097b | 297 | /* Wildly overreserve - it doesn't matter much. */ |
53cb28cb | 298 | phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS); |
5cd2c5b6 | 299 | |
53cb28cb | 300 | phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1); |
92e873b9 FB |
301 | } |
302 | ||
b35ba30f MT |
303 | /* Compact a non leaf page entry. Simply detect that the entry has a single child, |
304 | * and update our entry so we can skip it and go directly to the destination. | |
305 | */ | |
efee678d | 306 | static void phys_page_compact(PhysPageEntry *lp, Node *nodes) |
b35ba30f MT |
307 | { |
308 | unsigned valid_ptr = P_L2_SIZE; | |
309 | int valid = 0; | |
310 | PhysPageEntry *p; | |
311 | int i; | |
312 | ||
313 | if (lp->ptr == PHYS_MAP_NODE_NIL) { | |
314 | return; | |
315 | } | |
316 | ||
317 | p = nodes[lp->ptr]; | |
318 | for (i = 0; i < P_L2_SIZE; i++) { | |
319 | if (p[i].ptr == PHYS_MAP_NODE_NIL) { | |
320 | continue; | |
321 | } | |
322 | ||
323 | valid_ptr = i; | |
324 | valid++; | |
325 | if (p[i].skip) { | |
efee678d | 326 | phys_page_compact(&p[i], nodes); |
b35ba30f MT |
327 | } |
328 | } | |
329 | ||
330 | /* We can only compress if there's only one child. */ | |
331 | if (valid != 1) { | |
332 | return; | |
333 | } | |
334 | ||
335 | assert(valid_ptr < P_L2_SIZE); | |
336 | ||
337 | /* Don't compress if it won't fit in the # of bits we have. */ | |
338 | if (lp->skip + p[valid_ptr].skip >= (1 << 3)) { | |
339 | return; | |
340 | } | |
341 | ||
342 | lp->ptr = p[valid_ptr].ptr; | |
343 | if (!p[valid_ptr].skip) { | |
344 | /* If our only child is a leaf, make this a leaf. */ | |
345 | /* By design, we should have made this node a leaf to begin with so we | |
346 | * should never reach here. | |
347 | * But since it's so simple to handle this, let's do it just in case we | |
348 | * change this rule. | |
349 | */ | |
350 | lp->skip = 0; | |
351 | } else { | |
352 | lp->skip += p[valid_ptr].skip; | |
353 | } | |
354 | } | |
355 | ||
8629d3fc | 356 | void address_space_dispatch_compact(AddressSpaceDispatch *d) |
b35ba30f | 357 | { |
b35ba30f | 358 | if (d->phys_map.skip) { |
efee678d | 359 | phys_page_compact(&d->phys_map, d->map.nodes); |
b35ba30f MT |
360 | } |
361 | } | |
362 | ||
29cb533d FZ |
363 | static inline bool section_covers_addr(const MemoryRegionSection *section, |
364 | hwaddr addr) | |
365 | { | |
366 | /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means | |
367 | * the section must cover the entire address space. | |
368 | */ | |
258dfaaa | 369 | return int128_gethi(section->size) || |
29cb533d | 370 | range_covers_byte(section->offset_within_address_space, |
258dfaaa | 371 | int128_getlo(section->size), addr); |
29cb533d FZ |
372 | } |
373 | ||
003a0cf2 | 374 | static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr) |
92e873b9 | 375 | { |
003a0cf2 PX |
376 | PhysPageEntry lp = d->phys_map, *p; |
377 | Node *nodes = d->map.nodes; | |
378 | MemoryRegionSection *sections = d->map.sections; | |
97115a8d | 379 | hwaddr index = addr >> TARGET_PAGE_BITS; |
31ab2b4a | 380 | int i; |
f1f6e3b8 | 381 | |
9736e55b | 382 | for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) { |
c19e8800 | 383 | if (lp.ptr == PHYS_MAP_NODE_NIL) { |
9affd6fc | 384 | return §ions[PHYS_SECTION_UNASSIGNED]; |
31ab2b4a | 385 | } |
9affd6fc | 386 | p = nodes[lp.ptr]; |
03f49957 | 387 | lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)]; |
5312bd8b | 388 | } |
b35ba30f | 389 | |
29cb533d | 390 | if (section_covers_addr(§ions[lp.ptr], addr)) { |
b35ba30f MT |
391 | return §ions[lp.ptr]; |
392 | } else { | |
393 | return §ions[PHYS_SECTION_UNASSIGNED]; | |
394 | } | |
f3705d53 AK |
395 | } |
396 | ||
e5548617 BS |
397 | bool memory_region_is_unassigned(MemoryRegion *mr) |
398 | { | |
2a8e7499 | 399 | return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device |
5b6dd868 | 400 | && mr != &io_mem_watch; |
fd6ce8f6 | 401 | } |
149f54b5 | 402 | |
79e2b9ae | 403 | /* Called from RCU critical section */ |
c7086b4a | 404 | static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d, |
90260c6c JK |
405 | hwaddr addr, |
406 | bool resolve_subpage) | |
9f029603 | 407 | { |
729633c2 | 408 | MemoryRegionSection *section = atomic_read(&d->mru_section); |
90260c6c JK |
409 | subpage_t *subpage; |
410 | ||
07c114bb PB |
411 | if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] || |
412 | !section_covers_addr(section, addr)) { | |
003a0cf2 | 413 | section = phys_page_find(d, addr); |
07c114bb | 414 | atomic_set(&d->mru_section, section); |
729633c2 | 415 | } |
90260c6c JK |
416 | if (resolve_subpage && section->mr->subpage) { |
417 | subpage = container_of(section->mr, subpage_t, iomem); | |
53cb28cb | 418 | section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]]; |
90260c6c JK |
419 | } |
420 | return section; | |
9f029603 JK |
421 | } |
422 | ||
79e2b9ae | 423 | /* Called from RCU critical section */ |
90260c6c | 424 | static MemoryRegionSection * |
c7086b4a | 425 | address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat, |
90260c6c | 426 | hwaddr *plen, bool resolve_subpage) |
149f54b5 PB |
427 | { |
428 | MemoryRegionSection *section; | |
965eb2fc | 429 | MemoryRegion *mr; |
a87f3954 | 430 | Int128 diff; |
149f54b5 | 431 | |
c7086b4a | 432 | section = address_space_lookup_region(d, addr, resolve_subpage); |
149f54b5 PB |
433 | /* Compute offset within MemoryRegionSection */ |
434 | addr -= section->offset_within_address_space; | |
435 | ||
436 | /* Compute offset within MemoryRegion */ | |
437 | *xlat = addr + section->offset_within_region; | |
438 | ||
965eb2fc | 439 | mr = section->mr; |
b242e0e0 PB |
440 | |
441 | /* MMIO registers can be expected to perform full-width accesses based only | |
442 | * on their address, without considering adjacent registers that could | |
443 | * decode to completely different MemoryRegions. When such registers | |
444 | * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO | |
445 | * regions overlap wildly. For this reason we cannot clamp the accesses | |
446 | * here. | |
447 | * | |
448 | * If the length is small (as is the case for address_space_ldl/stl), | |
449 | * everything works fine. If the incoming length is large, however, | |
450 | * the caller really has to do the clamping through memory_access_size. | |
451 | */ | |
965eb2fc | 452 | if (memory_region_is_ram(mr)) { |
e4a511f8 | 453 | diff = int128_sub(section->size, int128_make64(addr)); |
965eb2fc PB |
454 | *plen = int128_get64(int128_min(diff, int128_make64(*plen))); |
455 | } | |
149f54b5 PB |
456 | return section; |
457 | } | |
90260c6c | 458 | |
d5e5fafd PX |
459 | /** |
460 | * flatview_do_translate - translate an address in FlatView | |
461 | * | |
462 | * @fv: the flat view that we want to translate on | |
463 | * @addr: the address to be translated in above address space | |
464 | * @xlat: the translated address offset within memory region. It | |
465 | * cannot be @NULL. | |
466 | * @plen_out: valid read/write length of the translated address. It | |
467 | * can be @NULL when we don't care about it. | |
468 | * @page_mask_out: page mask for the translated address. This | |
469 | * should only be meaningful for IOMMU translated | |
470 | * addresses, since there may be huge pages that this bit | |
471 | * would tell. It can be @NULL if we don't care about it. | |
472 | * @is_write: whether the translation operation is for write | |
473 | * @is_mmio: whether this can be MMIO, set true if it can | |
474 | * | |
475 | * This function is called from RCU critical section | |
476 | */ | |
16620684 AK |
477 | static MemoryRegionSection flatview_do_translate(FlatView *fv, |
478 | hwaddr addr, | |
479 | hwaddr *xlat, | |
d5e5fafd PX |
480 | hwaddr *plen_out, |
481 | hwaddr *page_mask_out, | |
16620684 AK |
482 | bool is_write, |
483 | bool is_mmio, | |
484 | AddressSpace **target_as) | |
052c8fa9 | 485 | { |
a764040c | 486 | IOMMUTLBEntry iotlb; |
052c8fa9 | 487 | MemoryRegionSection *section; |
3df9d748 | 488 | IOMMUMemoryRegion *iommu_mr; |
1221a474 | 489 | IOMMUMemoryRegionClass *imrc; |
d5e5fafd PX |
490 | hwaddr page_mask = (hwaddr)(-1); |
491 | hwaddr plen = (hwaddr)(-1); | |
492 | ||
493 | if (plen_out) { | |
494 | plen = *plen_out; | |
495 | } | |
052c8fa9 JW |
496 | |
497 | for (;;) { | |
16620684 AK |
498 | section = address_space_translate_internal( |
499 | flatview_to_dispatch(fv), addr, &addr, | |
d5e5fafd | 500 | &plen, is_mmio); |
052c8fa9 | 501 | |
3df9d748 AK |
502 | iommu_mr = memory_region_get_iommu(section->mr); |
503 | if (!iommu_mr) { | |
052c8fa9 JW |
504 | break; |
505 | } | |
1221a474 | 506 | imrc = memory_region_get_iommu_class_nocheck(iommu_mr); |
052c8fa9 | 507 | |
1221a474 AK |
508 | iotlb = imrc->translate(iommu_mr, addr, is_write ? |
509 | IOMMU_WO : IOMMU_RO); | |
a764040c PX |
510 | addr = ((iotlb.translated_addr & ~iotlb.addr_mask) |
511 | | (addr & iotlb.addr_mask)); | |
d5e5fafd PX |
512 | page_mask &= iotlb.addr_mask; |
513 | plen = MIN(plen, (addr | iotlb.addr_mask) - addr + 1); | |
052c8fa9 | 514 | if (!(iotlb.perm & (1 << is_write))) { |
a764040c | 515 | goto translate_fail; |
052c8fa9 JW |
516 | } |
517 | ||
16620684 | 518 | fv = address_space_to_flatview(iotlb.target_as); |
e76bb18f | 519 | *target_as = iotlb.target_as; |
052c8fa9 JW |
520 | } |
521 | ||
a764040c PX |
522 | *xlat = addr; |
523 | ||
d5e5fafd PX |
524 | if (page_mask == (hwaddr)(-1)) { |
525 | /* Not behind an IOMMU, use default page size. */ | |
526 | page_mask = ~TARGET_PAGE_MASK; | |
527 | } | |
528 | ||
529 | if (page_mask_out) { | |
530 | *page_mask_out = page_mask; | |
531 | } | |
532 | ||
533 | if (plen_out) { | |
534 | *plen_out = plen; | |
535 | } | |
536 | ||
a764040c PX |
537 | return *section; |
538 | ||
539 | translate_fail: | |
540 | return (MemoryRegionSection) { .mr = &io_mem_unassigned }; | |
052c8fa9 JW |
541 | } |
542 | ||
543 | /* Called from RCU critical section */ | |
a764040c PX |
544 | IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, |
545 | bool is_write) | |
90260c6c | 546 | { |
a764040c | 547 | MemoryRegionSection section; |
076a93d7 | 548 | hwaddr xlat, page_mask; |
30951157 | 549 | |
076a93d7 PX |
550 | /* |
551 | * This can never be MMIO, and we don't really care about plen, | |
552 | * but page mask. | |
553 | */ | |
554 | section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat, | |
555 | NULL, &page_mask, is_write, false, &as); | |
30951157 | 556 | |
a764040c PX |
557 | /* Illegal translation */ |
558 | if (section.mr == &io_mem_unassigned) { | |
559 | goto iotlb_fail; | |
560 | } | |
30951157 | 561 | |
a764040c PX |
562 | /* Convert memory region offset into address space offset */ |
563 | xlat += section.offset_within_address_space - | |
564 | section.offset_within_region; | |
565 | ||
a764040c | 566 | return (IOMMUTLBEntry) { |
e76bb18f | 567 | .target_as = as, |
076a93d7 PX |
568 | .iova = addr & ~page_mask, |
569 | .translated_addr = xlat & ~page_mask, | |
570 | .addr_mask = page_mask, | |
a764040c PX |
571 | /* IOTLBs are for DMAs, and DMA only allows on RAMs. */ |
572 | .perm = IOMMU_RW, | |
573 | }; | |
574 | ||
575 | iotlb_fail: | |
576 | return (IOMMUTLBEntry) {0}; | |
577 | } | |
578 | ||
579 | /* Called from RCU critical section */ | |
16620684 AK |
580 | MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, |
581 | hwaddr *plen, bool is_write) | |
a764040c PX |
582 | { |
583 | MemoryRegion *mr; | |
584 | MemoryRegionSection section; | |
16620684 | 585 | AddressSpace *as = NULL; |
a764040c PX |
586 | |
587 | /* This can be MMIO, so setup MMIO bit. */ | |
d5e5fafd PX |
588 | section = flatview_do_translate(fv, addr, xlat, plen, NULL, |
589 | is_write, true, &as); | |
a764040c PX |
590 | mr = section.mr; |
591 | ||
fe680d0d | 592 | if (xen_enabled() && memory_access_is_direct(mr, is_write)) { |
a87f3954 | 593 | hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr; |
23820dbf | 594 | *plen = MIN(page, *plen); |
a87f3954 PB |
595 | } |
596 | ||
30951157 | 597 | return mr; |
90260c6c JK |
598 | } |
599 | ||
79e2b9ae | 600 | /* Called from RCU critical section */ |
90260c6c | 601 | MemoryRegionSection * |
d7898cda | 602 | address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, |
9d82b5a7 | 603 | hwaddr *xlat, hwaddr *plen) |
90260c6c | 604 | { |
30951157 | 605 | MemoryRegionSection *section; |
f35e44e7 | 606 | AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch); |
d7898cda PM |
607 | |
608 | section = address_space_translate_internal(d, addr, xlat, plen, false); | |
30951157 | 609 | |
3df9d748 | 610 | assert(!memory_region_is_iommu(section->mr)); |
30951157 | 611 | return section; |
90260c6c | 612 | } |
5b6dd868 | 613 | #endif |
fd6ce8f6 | 614 | |
b170fce3 | 615 | #if !defined(CONFIG_USER_ONLY) |
5b6dd868 BS |
616 | |
617 | static int cpu_common_post_load(void *opaque, int version_id) | |
fd6ce8f6 | 618 | { |
259186a7 | 619 | CPUState *cpu = opaque; |
a513fe19 | 620 | |
5b6dd868 BS |
621 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
622 | version_id is increased. */ | |
259186a7 | 623 | cpu->interrupt_request &= ~0x01; |
d10eb08f | 624 | tlb_flush(cpu); |
5b6dd868 BS |
625 | |
626 | return 0; | |
a513fe19 | 627 | } |
7501267e | 628 | |
6c3bff0e PD |
629 | static int cpu_common_pre_load(void *opaque) |
630 | { | |
631 | CPUState *cpu = opaque; | |
632 | ||
adee6424 | 633 | cpu->exception_index = -1; |
6c3bff0e PD |
634 | |
635 | return 0; | |
636 | } | |
637 | ||
638 | static bool cpu_common_exception_index_needed(void *opaque) | |
639 | { | |
640 | CPUState *cpu = opaque; | |
641 | ||
adee6424 | 642 | return tcg_enabled() && cpu->exception_index != -1; |
6c3bff0e PD |
643 | } |
644 | ||
645 | static const VMStateDescription vmstate_cpu_common_exception_index = { | |
646 | .name = "cpu_common/exception_index", | |
647 | .version_id = 1, | |
648 | .minimum_version_id = 1, | |
5cd8cada | 649 | .needed = cpu_common_exception_index_needed, |
6c3bff0e PD |
650 | .fields = (VMStateField[]) { |
651 | VMSTATE_INT32(exception_index, CPUState), | |
652 | VMSTATE_END_OF_LIST() | |
653 | } | |
654 | }; | |
655 | ||
bac05aa9 AS |
656 | static bool cpu_common_crash_occurred_needed(void *opaque) |
657 | { | |
658 | CPUState *cpu = opaque; | |
659 | ||
660 | return cpu->crash_occurred; | |
661 | } | |
662 | ||
663 | static const VMStateDescription vmstate_cpu_common_crash_occurred = { | |
664 | .name = "cpu_common/crash_occurred", | |
665 | .version_id = 1, | |
666 | .minimum_version_id = 1, | |
667 | .needed = cpu_common_crash_occurred_needed, | |
668 | .fields = (VMStateField[]) { | |
669 | VMSTATE_BOOL(crash_occurred, CPUState), | |
670 | VMSTATE_END_OF_LIST() | |
671 | } | |
672 | }; | |
673 | ||
1a1562f5 | 674 | const VMStateDescription vmstate_cpu_common = { |
5b6dd868 BS |
675 | .name = "cpu_common", |
676 | .version_id = 1, | |
677 | .minimum_version_id = 1, | |
6c3bff0e | 678 | .pre_load = cpu_common_pre_load, |
5b6dd868 | 679 | .post_load = cpu_common_post_load, |
35d08458 | 680 | .fields = (VMStateField[]) { |
259186a7 AF |
681 | VMSTATE_UINT32(halted, CPUState), |
682 | VMSTATE_UINT32(interrupt_request, CPUState), | |
5b6dd868 | 683 | VMSTATE_END_OF_LIST() |
6c3bff0e | 684 | }, |
5cd8cada JQ |
685 | .subsections = (const VMStateDescription*[]) { |
686 | &vmstate_cpu_common_exception_index, | |
bac05aa9 | 687 | &vmstate_cpu_common_crash_occurred, |
5cd8cada | 688 | NULL |
5b6dd868 BS |
689 | } |
690 | }; | |
1a1562f5 | 691 | |
5b6dd868 | 692 | #endif |
ea041c0e | 693 | |
38d8f5c8 | 694 | CPUState *qemu_get_cpu(int index) |
ea041c0e | 695 | { |
bdc44640 | 696 | CPUState *cpu; |
ea041c0e | 697 | |
bdc44640 | 698 | CPU_FOREACH(cpu) { |
55e5c285 | 699 | if (cpu->cpu_index == index) { |
bdc44640 | 700 | return cpu; |
55e5c285 | 701 | } |
ea041c0e | 702 | } |
5b6dd868 | 703 | |
bdc44640 | 704 | return NULL; |
ea041c0e FB |
705 | } |
706 | ||
09daed84 | 707 | #if !defined(CONFIG_USER_ONLY) |
56943e8c | 708 | void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx) |
09daed84 | 709 | { |
12ebc9a7 PM |
710 | CPUAddressSpace *newas; |
711 | ||
712 | /* Target code should have set num_ases before calling us */ | |
713 | assert(asidx < cpu->num_ases); | |
714 | ||
56943e8c PM |
715 | if (asidx == 0) { |
716 | /* address space 0 gets the convenience alias */ | |
717 | cpu->as = as; | |
718 | } | |
719 | ||
12ebc9a7 PM |
720 | /* KVM cannot currently support multiple address spaces. */ |
721 | assert(asidx == 0 || !kvm_enabled()); | |
09daed84 | 722 | |
12ebc9a7 PM |
723 | if (!cpu->cpu_ases) { |
724 | cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases); | |
09daed84 | 725 | } |
32857f4d | 726 | |
12ebc9a7 PM |
727 | newas = &cpu->cpu_ases[asidx]; |
728 | newas->cpu = cpu; | |
729 | newas->as = as; | |
56943e8c | 730 | if (tcg_enabled()) { |
12ebc9a7 PM |
731 | newas->tcg_as_listener.commit = tcg_commit; |
732 | memory_listener_register(&newas->tcg_as_listener, as); | |
56943e8c | 733 | } |
09daed84 | 734 | } |
651a5bc0 PM |
735 | |
736 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx) | |
737 | { | |
738 | /* Return the AddressSpace corresponding to the specified index */ | |
739 | return cpu->cpu_ases[asidx].as; | |
740 | } | |
09daed84 EI |
741 | #endif |
742 | ||
7bbc124e | 743 | void cpu_exec_unrealizefn(CPUState *cpu) |
1c59eb39 | 744 | { |
9dfeca7c BR |
745 | CPUClass *cc = CPU_GET_CLASS(cpu); |
746 | ||
267f685b | 747 | cpu_list_remove(cpu); |
9dfeca7c BR |
748 | |
749 | if (cc->vmsd != NULL) { | |
750 | vmstate_unregister(NULL, cc->vmsd, cpu); | |
751 | } | |
752 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { | |
753 | vmstate_unregister(NULL, &vmstate_cpu_common, cpu); | |
754 | } | |
1c59eb39 BR |
755 | } |
756 | ||
c7e002c5 FZ |
757 | Property cpu_common_props[] = { |
758 | #ifndef CONFIG_USER_ONLY | |
759 | /* Create a memory property for softmmu CPU object, | |
760 | * so users can wire up its memory. (This can't go in qom/cpu.c | |
761 | * because that file is compiled only once for both user-mode | |
762 | * and system builds.) The default if no link is set up is to use | |
763 | * the system address space. | |
764 | */ | |
765 | DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, | |
766 | MemoryRegion *), | |
767 | #endif | |
768 | DEFINE_PROP_END_OF_LIST(), | |
769 | }; | |
770 | ||
39e329e3 | 771 | void cpu_exec_initfn(CPUState *cpu) |
ea041c0e | 772 | { |
56943e8c | 773 | cpu->as = NULL; |
12ebc9a7 | 774 | cpu->num_ases = 0; |
56943e8c | 775 | |
291135b5 | 776 | #ifndef CONFIG_USER_ONLY |
291135b5 | 777 | cpu->thread_id = qemu_get_thread_id(); |
6731d864 PC |
778 | cpu->memory = system_memory; |
779 | object_ref(OBJECT(cpu->memory)); | |
291135b5 | 780 | #endif |
39e329e3 LV |
781 | } |
782 | ||
ce5b1bbf | 783 | void cpu_exec_realizefn(CPUState *cpu, Error **errp) |
39e329e3 | 784 | { |
55c3ceef | 785 | CPUClass *cc = CPU_GET_CLASS(cpu); |
2dda6354 | 786 | static bool tcg_target_initialized; |
291135b5 | 787 | |
267f685b | 788 | cpu_list_add(cpu); |
1bc7e522 | 789 | |
2dda6354 EC |
790 | if (tcg_enabled() && !tcg_target_initialized) { |
791 | tcg_target_initialized = true; | |
55c3ceef RH |
792 | cc->tcg_initialize(); |
793 | } | |
794 | ||
1bc7e522 | 795 | #ifndef CONFIG_USER_ONLY |
e0d47944 | 796 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { |
741da0d3 | 797 | vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); |
e0d47944 | 798 | } |
b170fce3 | 799 | if (cc->vmsd != NULL) { |
741da0d3 | 800 | vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); |
b170fce3 | 801 | } |
741da0d3 | 802 | #endif |
ea041c0e FB |
803 | } |
804 | ||
406bc339 | 805 | #if defined(CONFIG_USER_ONLY) |
00b941e5 | 806 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) |
1e7855a5 | 807 | { |
406bc339 PK |
808 | mmap_lock(); |
809 | tb_lock(); | |
810 | tb_invalidate_phys_page_range(pc, pc + 1, 0); | |
811 | tb_unlock(); | |
812 | mmap_unlock(); | |
813 | } | |
814 | #else | |
815 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) | |
816 | { | |
817 | MemTxAttrs attrs; | |
818 | hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs); | |
819 | int asidx = cpu_asidx_from_attrs(cpu, attrs); | |
820 | if (phys != -1) { | |
821 | /* Locks grabbed by tb_invalidate_phys_addr */ | |
822 | tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as, | |
823 | phys | (pc & ~TARGET_PAGE_MASK)); | |
824 | } | |
1e7855a5 | 825 | } |
406bc339 | 826 | #endif |
d720b93d | 827 | |
c527ee8f | 828 | #if defined(CONFIG_USER_ONLY) |
75a34036 | 829 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) |
c527ee8f PB |
830 | |
831 | { | |
832 | } | |
833 | ||
3ee887e8 PM |
834 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, |
835 | int flags) | |
836 | { | |
837 | return -ENOSYS; | |
838 | } | |
839 | ||
840 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) | |
841 | { | |
842 | } | |
843 | ||
75a34036 | 844 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
c527ee8f PB |
845 | int flags, CPUWatchpoint **watchpoint) |
846 | { | |
847 | return -ENOSYS; | |
848 | } | |
849 | #else | |
6658ffb8 | 850 | /* Add a watchpoint. */ |
75a34036 | 851 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
a1d1bb31 | 852 | int flags, CPUWatchpoint **watchpoint) |
6658ffb8 | 853 | { |
c0ce998e | 854 | CPUWatchpoint *wp; |
6658ffb8 | 855 | |
05068c0d | 856 | /* forbid ranges which are empty or run off the end of the address space */ |
07e2863d | 857 | if (len == 0 || (addr + len - 1) < addr) { |
75a34036 AF |
858 | error_report("tried to set invalid watchpoint at %" |
859 | VADDR_PRIx ", len=%" VADDR_PRIu, addr, len); | |
b4051334 AL |
860 | return -EINVAL; |
861 | } | |
7267c094 | 862 | wp = g_malloc(sizeof(*wp)); |
a1d1bb31 AL |
863 | |
864 | wp->vaddr = addr; | |
05068c0d | 865 | wp->len = len; |
a1d1bb31 AL |
866 | wp->flags = flags; |
867 | ||
2dc9f411 | 868 | /* keep all GDB-injected watchpoints in front */ |
ff4700b0 AF |
869 | if (flags & BP_GDB) { |
870 | QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry); | |
871 | } else { | |
872 | QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); | |
873 | } | |
6658ffb8 | 874 | |
31b030d4 | 875 | tlb_flush_page(cpu, addr); |
a1d1bb31 AL |
876 | |
877 | if (watchpoint) | |
878 | *watchpoint = wp; | |
879 | return 0; | |
6658ffb8 PB |
880 | } |
881 | ||
a1d1bb31 | 882 | /* Remove a specific watchpoint. */ |
75a34036 | 883 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, |
a1d1bb31 | 884 | int flags) |
6658ffb8 | 885 | { |
a1d1bb31 | 886 | CPUWatchpoint *wp; |
6658ffb8 | 887 | |
ff4700b0 | 888 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d | 889 | if (addr == wp->vaddr && len == wp->len |
6e140f28 | 890 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
75a34036 | 891 | cpu_watchpoint_remove_by_ref(cpu, wp); |
6658ffb8 PB |
892 | return 0; |
893 | } | |
894 | } | |
a1d1bb31 | 895 | return -ENOENT; |
6658ffb8 PB |
896 | } |
897 | ||
a1d1bb31 | 898 | /* Remove a specific watchpoint by reference. */ |
75a34036 | 899 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) |
a1d1bb31 | 900 | { |
ff4700b0 | 901 | QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); |
7d03f82f | 902 | |
31b030d4 | 903 | tlb_flush_page(cpu, watchpoint->vaddr); |
a1d1bb31 | 904 | |
7267c094 | 905 | g_free(watchpoint); |
a1d1bb31 AL |
906 | } |
907 | ||
908 | /* Remove all matching watchpoints. */ | |
75a34036 | 909 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) |
a1d1bb31 | 910 | { |
c0ce998e | 911 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 912 | |
ff4700b0 | 913 | QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { |
75a34036 AF |
914 | if (wp->flags & mask) { |
915 | cpu_watchpoint_remove_by_ref(cpu, wp); | |
916 | } | |
c0ce998e | 917 | } |
7d03f82f | 918 | } |
05068c0d PM |
919 | |
920 | /* Return true if this watchpoint address matches the specified | |
921 | * access (ie the address range covered by the watchpoint overlaps | |
922 | * partially or completely with the address range covered by the | |
923 | * access). | |
924 | */ | |
925 | static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp, | |
926 | vaddr addr, | |
927 | vaddr len) | |
928 | { | |
929 | /* We know the lengths are non-zero, but a little caution is | |
930 | * required to avoid errors in the case where the range ends | |
931 | * exactly at the top of the address space and so addr + len | |
932 | * wraps round to zero. | |
933 | */ | |
934 | vaddr wpend = wp->vaddr + wp->len - 1; | |
935 | vaddr addrend = addr + len - 1; | |
936 | ||
937 | return !(addr > wpend || wp->vaddr > addrend); | |
938 | } | |
939 | ||
c527ee8f | 940 | #endif |
7d03f82f | 941 | |
a1d1bb31 | 942 | /* Add a breakpoint. */ |
b3310ab3 | 943 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, |
a1d1bb31 | 944 | CPUBreakpoint **breakpoint) |
4c3a88a2 | 945 | { |
c0ce998e | 946 | CPUBreakpoint *bp; |
3b46e624 | 947 | |
7267c094 | 948 | bp = g_malloc(sizeof(*bp)); |
4c3a88a2 | 949 | |
a1d1bb31 AL |
950 | bp->pc = pc; |
951 | bp->flags = flags; | |
952 | ||
2dc9f411 | 953 | /* keep all GDB-injected breakpoints in front */ |
00b941e5 | 954 | if (flags & BP_GDB) { |
f0c3c505 | 955 | QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry); |
00b941e5 | 956 | } else { |
f0c3c505 | 957 | QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); |
00b941e5 | 958 | } |
3b46e624 | 959 | |
f0c3c505 | 960 | breakpoint_invalidate(cpu, pc); |
a1d1bb31 | 961 | |
00b941e5 | 962 | if (breakpoint) { |
a1d1bb31 | 963 | *breakpoint = bp; |
00b941e5 | 964 | } |
4c3a88a2 | 965 | return 0; |
4c3a88a2 FB |
966 | } |
967 | ||
a1d1bb31 | 968 | /* Remove a specific breakpoint. */ |
b3310ab3 | 969 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) |
a1d1bb31 | 970 | { |
a1d1bb31 AL |
971 | CPUBreakpoint *bp; |
972 | ||
f0c3c505 | 973 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { |
a1d1bb31 | 974 | if (bp->pc == pc && bp->flags == flags) { |
b3310ab3 | 975 | cpu_breakpoint_remove_by_ref(cpu, bp); |
a1d1bb31 AL |
976 | return 0; |
977 | } | |
7d03f82f | 978 | } |
a1d1bb31 | 979 | return -ENOENT; |
7d03f82f EI |
980 | } |
981 | ||
a1d1bb31 | 982 | /* Remove a specific breakpoint by reference. */ |
b3310ab3 | 983 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint) |
4c3a88a2 | 984 | { |
f0c3c505 AF |
985 | QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry); |
986 | ||
987 | breakpoint_invalidate(cpu, breakpoint->pc); | |
a1d1bb31 | 988 | |
7267c094 | 989 | g_free(breakpoint); |
a1d1bb31 AL |
990 | } |
991 | ||
992 | /* Remove all matching breakpoints. */ | |
b3310ab3 | 993 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask) |
a1d1bb31 | 994 | { |
c0ce998e | 995 | CPUBreakpoint *bp, *next; |
a1d1bb31 | 996 | |
f0c3c505 | 997 | QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { |
b3310ab3 AF |
998 | if (bp->flags & mask) { |
999 | cpu_breakpoint_remove_by_ref(cpu, bp); | |
1000 | } | |
c0ce998e | 1001 | } |
4c3a88a2 FB |
1002 | } |
1003 | ||
c33a346e FB |
1004 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
1005 | CPU loop after each instruction */ | |
3825b28f | 1006 | void cpu_single_step(CPUState *cpu, int enabled) |
c33a346e | 1007 | { |
ed2803da AF |
1008 | if (cpu->singlestep_enabled != enabled) { |
1009 | cpu->singlestep_enabled = enabled; | |
1010 | if (kvm_enabled()) { | |
38e478ec | 1011 | kvm_update_guest_debug(cpu, 0); |
ed2803da | 1012 | } else { |
ccbb4d44 | 1013 | /* must flush all the translated code to avoid inconsistencies */ |
e22a25c9 | 1014 | /* XXX: only flush what is necessary */ |
bbd77c18 | 1015 | tb_flush(cpu); |
e22a25c9 | 1016 | } |
c33a346e | 1017 | } |
c33a346e FB |
1018 | } |
1019 | ||
a47dddd7 | 1020 | void cpu_abort(CPUState *cpu, const char *fmt, ...) |
7501267e FB |
1021 | { |
1022 | va_list ap; | |
493ae1f0 | 1023 | va_list ap2; |
7501267e FB |
1024 | |
1025 | va_start(ap, fmt); | |
493ae1f0 | 1026 | va_copy(ap2, ap); |
7501267e FB |
1027 | fprintf(stderr, "qemu: fatal: "); |
1028 | vfprintf(stderr, fmt, ap); | |
1029 | fprintf(stderr, "\n"); | |
878096ee | 1030 | cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
013a2942 | 1031 | if (qemu_log_separate()) { |
1ee73216 | 1032 | qemu_log_lock(); |
93fcfe39 AL |
1033 | qemu_log("qemu: fatal: "); |
1034 | qemu_log_vprintf(fmt, ap2); | |
1035 | qemu_log("\n"); | |
a0762859 | 1036 | log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
31b1a7b4 | 1037 | qemu_log_flush(); |
1ee73216 | 1038 | qemu_log_unlock(); |
93fcfe39 | 1039 | qemu_log_close(); |
924edcae | 1040 | } |
493ae1f0 | 1041 | va_end(ap2); |
f9373291 | 1042 | va_end(ap); |
7615936e | 1043 | replay_finish(); |
fd052bf6 RV |
1044 | #if defined(CONFIG_USER_ONLY) |
1045 | { | |
1046 | struct sigaction act; | |
1047 | sigfillset(&act.sa_mask); | |
1048 | act.sa_handler = SIG_DFL; | |
1049 | sigaction(SIGABRT, &act, NULL); | |
1050 | } | |
1051 | #endif | |
7501267e FB |
1052 | abort(); |
1053 | } | |
1054 | ||
0124311e | 1055 | #if !defined(CONFIG_USER_ONLY) |
0dc3f44a | 1056 | /* Called from RCU critical section */ |
041603fe PB |
1057 | static RAMBlock *qemu_get_ram_block(ram_addr_t addr) |
1058 | { | |
1059 | RAMBlock *block; | |
1060 | ||
43771539 | 1061 | block = atomic_rcu_read(&ram_list.mru_block); |
9b8424d5 | 1062 | if (block && addr - block->offset < block->max_length) { |
68851b98 | 1063 | return block; |
041603fe | 1064 | } |
99e15582 | 1065 | RAMBLOCK_FOREACH(block) { |
9b8424d5 | 1066 | if (addr - block->offset < block->max_length) { |
041603fe PB |
1067 | goto found; |
1068 | } | |
1069 | } | |
1070 | ||
1071 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
1072 | abort(); | |
1073 | ||
1074 | found: | |
43771539 PB |
1075 | /* It is safe to write mru_block outside the iothread lock. This |
1076 | * is what happens: | |
1077 | * | |
1078 | * mru_block = xxx | |
1079 | * rcu_read_unlock() | |
1080 | * xxx removed from list | |
1081 | * rcu_read_lock() | |
1082 | * read mru_block | |
1083 | * mru_block = NULL; | |
1084 | * call_rcu(reclaim_ramblock, xxx); | |
1085 | * rcu_read_unlock() | |
1086 | * | |
1087 | * atomic_rcu_set is not needed here. The block was already published | |
1088 | * when it was placed into the list. Here we're just making an extra | |
1089 | * copy of the pointer. | |
1090 | */ | |
041603fe PB |
1091 | ram_list.mru_block = block; |
1092 | return block; | |
1093 | } | |
1094 | ||
a2f4d5be | 1095 | static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length) |
d24981d3 | 1096 | { |
9a13565d | 1097 | CPUState *cpu; |
041603fe | 1098 | ram_addr_t start1; |
a2f4d5be JQ |
1099 | RAMBlock *block; |
1100 | ram_addr_t end; | |
1101 | ||
1102 | end = TARGET_PAGE_ALIGN(start + length); | |
1103 | start &= TARGET_PAGE_MASK; | |
d24981d3 | 1104 | |
0dc3f44a | 1105 | rcu_read_lock(); |
041603fe PB |
1106 | block = qemu_get_ram_block(start); |
1107 | assert(block == qemu_get_ram_block(end - 1)); | |
1240be24 | 1108 | start1 = (uintptr_t)ramblock_ptr(block, start - block->offset); |
9a13565d PC |
1109 | CPU_FOREACH(cpu) { |
1110 | tlb_reset_dirty(cpu, start1, length); | |
1111 | } | |
0dc3f44a | 1112 | rcu_read_unlock(); |
d24981d3 JQ |
1113 | } |
1114 | ||
5579c7f3 | 1115 | /* Note: start and end must be within the same ram block. */ |
03eebc9e SH |
1116 | bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start, |
1117 | ram_addr_t length, | |
1118 | unsigned client) | |
1ccde1cb | 1119 | { |
5b82b703 | 1120 | DirtyMemoryBlocks *blocks; |
03eebc9e | 1121 | unsigned long end, page; |
5b82b703 | 1122 | bool dirty = false; |
03eebc9e SH |
1123 | |
1124 | if (length == 0) { | |
1125 | return false; | |
1126 | } | |
f23db169 | 1127 | |
03eebc9e SH |
1128 | end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; |
1129 | page = start >> TARGET_PAGE_BITS; | |
5b82b703 SH |
1130 | |
1131 | rcu_read_lock(); | |
1132 | ||
1133 | blocks = atomic_rcu_read(&ram_list.dirty_memory[client]); | |
1134 | ||
1135 | while (page < end) { | |
1136 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
1137 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
1138 | unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset); | |
1139 | ||
1140 | dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx], | |
1141 | offset, num); | |
1142 | page += num; | |
1143 | } | |
1144 | ||
1145 | rcu_read_unlock(); | |
03eebc9e SH |
1146 | |
1147 | if (dirty && tcg_enabled()) { | |
a2f4d5be | 1148 | tlb_reset_dirty_range_all(start, length); |
5579c7f3 | 1149 | } |
03eebc9e SH |
1150 | |
1151 | return dirty; | |
1ccde1cb FB |
1152 | } |
1153 | ||
8deaf12c GH |
1154 | DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty |
1155 | (ram_addr_t start, ram_addr_t length, unsigned client) | |
1156 | { | |
1157 | DirtyMemoryBlocks *blocks; | |
1158 | unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL); | |
1159 | ram_addr_t first = QEMU_ALIGN_DOWN(start, align); | |
1160 | ram_addr_t last = QEMU_ALIGN_UP(start + length, align); | |
1161 | DirtyBitmapSnapshot *snap; | |
1162 | unsigned long page, end, dest; | |
1163 | ||
1164 | snap = g_malloc0(sizeof(*snap) + | |
1165 | ((last - first) >> (TARGET_PAGE_BITS + 3))); | |
1166 | snap->start = first; | |
1167 | snap->end = last; | |
1168 | ||
1169 | page = first >> TARGET_PAGE_BITS; | |
1170 | end = last >> TARGET_PAGE_BITS; | |
1171 | dest = 0; | |
1172 | ||
1173 | rcu_read_lock(); | |
1174 | ||
1175 | blocks = atomic_rcu_read(&ram_list.dirty_memory[client]); | |
1176 | ||
1177 | while (page < end) { | |
1178 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
1179 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
1180 | unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset); | |
1181 | ||
1182 | assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL))); | |
1183 | assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL))); | |
1184 | offset >>= BITS_PER_LEVEL; | |
1185 | ||
1186 | bitmap_copy_and_clear_atomic(snap->dirty + dest, | |
1187 | blocks->blocks[idx] + offset, | |
1188 | num); | |
1189 | page += num; | |
1190 | dest += num >> BITS_PER_LEVEL; | |
1191 | } | |
1192 | ||
1193 | rcu_read_unlock(); | |
1194 | ||
1195 | if (tcg_enabled()) { | |
1196 | tlb_reset_dirty_range_all(start, length); | |
1197 | } | |
1198 | ||
1199 | return snap; | |
1200 | } | |
1201 | ||
1202 | bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap, | |
1203 | ram_addr_t start, | |
1204 | ram_addr_t length) | |
1205 | { | |
1206 | unsigned long page, end; | |
1207 | ||
1208 | assert(start >= snap->start); | |
1209 | assert(start + length <= snap->end); | |
1210 | ||
1211 | end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS; | |
1212 | page = (start - snap->start) >> TARGET_PAGE_BITS; | |
1213 | ||
1214 | while (page < end) { | |
1215 | if (test_bit(page, snap->dirty)) { | |
1216 | return true; | |
1217 | } | |
1218 | page++; | |
1219 | } | |
1220 | return false; | |
1221 | } | |
1222 | ||
79e2b9ae | 1223 | /* Called from RCU critical section */ |
bb0e627a | 1224 | hwaddr memory_region_section_get_iotlb(CPUState *cpu, |
149f54b5 PB |
1225 | MemoryRegionSection *section, |
1226 | target_ulong vaddr, | |
1227 | hwaddr paddr, hwaddr xlat, | |
1228 | int prot, | |
1229 | target_ulong *address) | |
e5548617 | 1230 | { |
a8170e5e | 1231 | hwaddr iotlb; |
e5548617 BS |
1232 | CPUWatchpoint *wp; |
1233 | ||
cc5bea60 | 1234 | if (memory_region_is_ram(section->mr)) { |
e5548617 | 1235 | /* Normal RAM. */ |
e4e69794 | 1236 | iotlb = memory_region_get_ram_addr(section->mr) + xlat; |
e5548617 | 1237 | if (!section->readonly) { |
b41aac4f | 1238 | iotlb |= PHYS_SECTION_NOTDIRTY; |
e5548617 | 1239 | } else { |
b41aac4f | 1240 | iotlb |= PHYS_SECTION_ROM; |
e5548617 BS |
1241 | } |
1242 | } else { | |
0b8e2c10 PM |
1243 | AddressSpaceDispatch *d; |
1244 | ||
16620684 | 1245 | d = flatview_to_dispatch(section->fv); |
0b8e2c10 | 1246 | iotlb = section - d->map.sections; |
149f54b5 | 1247 | iotlb += xlat; |
e5548617 BS |
1248 | } |
1249 | ||
1250 | /* Make accesses to pages with watchpoints go via the | |
1251 | watchpoint trap routines. */ | |
ff4700b0 | 1252 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d | 1253 | if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) { |
e5548617 BS |
1254 | /* Avoid trapping reads of pages with a write breakpoint. */ |
1255 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { | |
b41aac4f | 1256 | iotlb = PHYS_SECTION_WATCH + paddr; |
e5548617 BS |
1257 | *address |= TLB_MMIO; |
1258 | break; | |
1259 | } | |
1260 | } | |
1261 | } | |
1262 | ||
1263 | return iotlb; | |
1264 | } | |
9fa3e853 FB |
1265 | #endif /* defined(CONFIG_USER_ONLY) */ |
1266 | ||
e2eef170 | 1267 | #if !defined(CONFIG_USER_ONLY) |
8da3ff18 | 1268 | |
c227f099 | 1269 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
5312bd8b | 1270 | uint16_t section); |
16620684 | 1271 | static subpage_t *subpage_init(FlatView *fv, hwaddr base); |
54688b1e | 1272 | |
a2b257d6 IM |
1273 | static void *(*phys_mem_alloc)(size_t size, uint64_t *align) = |
1274 | qemu_anon_ram_alloc; | |
91138037 MA |
1275 | |
1276 | /* | |
1277 | * Set a custom physical guest memory alloator. | |
1278 | * Accelerators with unusual needs may need this. Hopefully, we can | |
1279 | * get rid of it eventually. | |
1280 | */ | |
a2b257d6 | 1281 | void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align)) |
91138037 MA |
1282 | { |
1283 | phys_mem_alloc = alloc; | |
1284 | } | |
1285 | ||
53cb28cb MA |
1286 | static uint16_t phys_section_add(PhysPageMap *map, |
1287 | MemoryRegionSection *section) | |
5312bd8b | 1288 | { |
68f3f65b PB |
1289 | /* The physical section number is ORed with a page-aligned |
1290 | * pointer to produce the iotlb entries. Thus it should | |
1291 | * never overflow into the page-aligned value. | |
1292 | */ | |
53cb28cb | 1293 | assert(map->sections_nb < TARGET_PAGE_SIZE); |
68f3f65b | 1294 | |
53cb28cb MA |
1295 | if (map->sections_nb == map->sections_nb_alloc) { |
1296 | map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16); | |
1297 | map->sections = g_renew(MemoryRegionSection, map->sections, | |
1298 | map->sections_nb_alloc); | |
5312bd8b | 1299 | } |
53cb28cb | 1300 | map->sections[map->sections_nb] = *section; |
dfde4e6e | 1301 | memory_region_ref(section->mr); |
53cb28cb | 1302 | return map->sections_nb++; |
5312bd8b AK |
1303 | } |
1304 | ||
058bc4b5 PB |
1305 | static void phys_section_destroy(MemoryRegion *mr) |
1306 | { | |
55b4e80b DS |
1307 | bool have_sub_page = mr->subpage; |
1308 | ||
dfde4e6e PB |
1309 | memory_region_unref(mr); |
1310 | ||
55b4e80b | 1311 | if (have_sub_page) { |
058bc4b5 | 1312 | subpage_t *subpage = container_of(mr, subpage_t, iomem); |
b4fefef9 | 1313 | object_unref(OBJECT(&subpage->iomem)); |
058bc4b5 PB |
1314 | g_free(subpage); |
1315 | } | |
1316 | } | |
1317 | ||
6092666e | 1318 | static void phys_sections_free(PhysPageMap *map) |
5312bd8b | 1319 | { |
9affd6fc PB |
1320 | while (map->sections_nb > 0) { |
1321 | MemoryRegionSection *section = &map->sections[--map->sections_nb]; | |
058bc4b5 PB |
1322 | phys_section_destroy(section->mr); |
1323 | } | |
9affd6fc PB |
1324 | g_free(map->sections); |
1325 | g_free(map->nodes); | |
5312bd8b AK |
1326 | } |
1327 | ||
9950322a | 1328 | static void register_subpage(FlatView *fv, MemoryRegionSection *section) |
0f0cb164 | 1329 | { |
9950322a | 1330 | AddressSpaceDispatch *d = flatview_to_dispatch(fv); |
0f0cb164 | 1331 | subpage_t *subpage; |
a8170e5e | 1332 | hwaddr base = section->offset_within_address_space |
0f0cb164 | 1333 | & TARGET_PAGE_MASK; |
003a0cf2 | 1334 | MemoryRegionSection *existing = phys_page_find(d, base); |
0f0cb164 AK |
1335 | MemoryRegionSection subsection = { |
1336 | .offset_within_address_space = base, | |
052e87b0 | 1337 | .size = int128_make64(TARGET_PAGE_SIZE), |
0f0cb164 | 1338 | }; |
a8170e5e | 1339 | hwaddr start, end; |
0f0cb164 | 1340 | |
f3705d53 | 1341 | assert(existing->mr->subpage || existing->mr == &io_mem_unassigned); |
0f0cb164 | 1342 | |
f3705d53 | 1343 | if (!(existing->mr->subpage)) { |
16620684 AK |
1344 | subpage = subpage_init(fv, base); |
1345 | subsection.fv = fv; | |
0f0cb164 | 1346 | subsection.mr = &subpage->iomem; |
ac1970fb | 1347 | phys_page_set(d, base >> TARGET_PAGE_BITS, 1, |
53cb28cb | 1348 | phys_section_add(&d->map, &subsection)); |
0f0cb164 | 1349 | } else { |
f3705d53 | 1350 | subpage = container_of(existing->mr, subpage_t, iomem); |
0f0cb164 AK |
1351 | } |
1352 | start = section->offset_within_address_space & ~TARGET_PAGE_MASK; | |
052e87b0 | 1353 | end = start + int128_get64(section->size) - 1; |
53cb28cb MA |
1354 | subpage_register(subpage, start, end, |
1355 | phys_section_add(&d->map, section)); | |
0f0cb164 AK |
1356 | } |
1357 | ||
1358 | ||
9950322a | 1359 | static void register_multipage(FlatView *fv, |
052e87b0 | 1360 | MemoryRegionSection *section) |
33417e70 | 1361 | { |
9950322a | 1362 | AddressSpaceDispatch *d = flatview_to_dispatch(fv); |
a8170e5e | 1363 | hwaddr start_addr = section->offset_within_address_space; |
53cb28cb | 1364 | uint16_t section_index = phys_section_add(&d->map, section); |
052e87b0 PB |
1365 | uint64_t num_pages = int128_get64(int128_rshift(section->size, |
1366 | TARGET_PAGE_BITS)); | |
dd81124b | 1367 | |
733d5ef5 PB |
1368 | assert(num_pages); |
1369 | phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index); | |
33417e70 FB |
1370 | } |
1371 | ||
8629d3fc | 1372 | void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section) |
0f0cb164 | 1373 | { |
99b9cc06 | 1374 | MemoryRegionSection now = *section, remain = *section; |
052e87b0 | 1375 | Int128 page_size = int128_make64(TARGET_PAGE_SIZE); |
0f0cb164 | 1376 | |
733d5ef5 PB |
1377 | if (now.offset_within_address_space & ~TARGET_PAGE_MASK) { |
1378 | uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space) | |
1379 | - now.offset_within_address_space; | |
1380 | ||
052e87b0 | 1381 | now.size = int128_min(int128_make64(left), now.size); |
9950322a | 1382 | register_subpage(fv, &now); |
733d5ef5 | 1383 | } else { |
052e87b0 | 1384 | now.size = int128_zero(); |
733d5ef5 | 1385 | } |
052e87b0 PB |
1386 | while (int128_ne(remain.size, now.size)) { |
1387 | remain.size = int128_sub(remain.size, now.size); | |
1388 | remain.offset_within_address_space += int128_get64(now.size); | |
1389 | remain.offset_within_region += int128_get64(now.size); | |
69b67646 | 1390 | now = remain; |
052e87b0 | 1391 | if (int128_lt(remain.size, page_size)) { |
9950322a | 1392 | register_subpage(fv, &now); |
88266249 | 1393 | } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) { |
052e87b0 | 1394 | now.size = page_size; |
9950322a | 1395 | register_subpage(fv, &now); |
69b67646 | 1396 | } else { |
052e87b0 | 1397 | now.size = int128_and(now.size, int128_neg(page_size)); |
9950322a | 1398 | register_multipage(fv, &now); |
69b67646 | 1399 | } |
0f0cb164 AK |
1400 | } |
1401 | } | |
1402 | ||
62a2744c SY |
1403 | void qemu_flush_coalesced_mmio_buffer(void) |
1404 | { | |
1405 | if (kvm_enabled()) | |
1406 | kvm_flush_coalesced_mmio_buffer(); | |
1407 | } | |
1408 | ||
b2a8658e UD |
1409 | void qemu_mutex_lock_ramlist(void) |
1410 | { | |
1411 | qemu_mutex_lock(&ram_list.mutex); | |
1412 | } | |
1413 | ||
1414 | void qemu_mutex_unlock_ramlist(void) | |
1415 | { | |
1416 | qemu_mutex_unlock(&ram_list.mutex); | |
1417 | } | |
1418 | ||
be9b23c4 PX |
1419 | void ram_block_dump(Monitor *mon) |
1420 | { | |
1421 | RAMBlock *block; | |
1422 | char *psize; | |
1423 | ||
1424 | rcu_read_lock(); | |
1425 | monitor_printf(mon, "%24s %8s %18s %18s %18s\n", | |
1426 | "Block Name", "PSize", "Offset", "Used", "Total"); | |
1427 | RAMBLOCK_FOREACH(block) { | |
1428 | psize = size_to_str(block->page_size); | |
1429 | monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64 | |
1430 | " 0x%016" PRIx64 "\n", block->idstr, psize, | |
1431 | (uint64_t)block->offset, | |
1432 | (uint64_t)block->used_length, | |
1433 | (uint64_t)block->max_length); | |
1434 | g_free(psize); | |
1435 | } | |
1436 | rcu_read_unlock(); | |
1437 | } | |
1438 | ||
9c607668 AK |
1439 | #ifdef __linux__ |
1440 | /* | |
1441 | * FIXME TOCTTOU: this iterates over memory backends' mem-path, which | |
1442 | * may or may not name the same files / on the same filesystem now as | |
1443 | * when we actually open and map them. Iterate over the file | |
1444 | * descriptors instead, and use qemu_fd_getpagesize(). | |
1445 | */ | |
1446 | static int find_max_supported_pagesize(Object *obj, void *opaque) | |
1447 | { | |
1448 | char *mem_path; | |
1449 | long *hpsize_min = opaque; | |
1450 | ||
1451 | if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { | |
1452 | mem_path = object_property_get_str(obj, "mem-path", NULL); | |
1453 | if (mem_path) { | |
1454 | long hpsize = qemu_mempath_getpagesize(mem_path); | |
1455 | if (hpsize < *hpsize_min) { | |
1456 | *hpsize_min = hpsize; | |
1457 | } | |
1458 | } else { | |
1459 | *hpsize_min = getpagesize(); | |
1460 | } | |
1461 | } | |
1462 | ||
1463 | return 0; | |
1464 | } | |
1465 | ||
1466 | long qemu_getrampagesize(void) | |
1467 | { | |
1468 | long hpsize = LONG_MAX; | |
1469 | long mainrampagesize; | |
1470 | Object *memdev_root; | |
1471 | ||
1472 | if (mem_path) { | |
1473 | mainrampagesize = qemu_mempath_getpagesize(mem_path); | |
1474 | } else { | |
1475 | mainrampagesize = getpagesize(); | |
1476 | } | |
1477 | ||
1478 | /* it's possible we have memory-backend objects with | |
1479 | * hugepage-backed RAM. these may get mapped into system | |
1480 | * address space via -numa parameters or memory hotplug | |
1481 | * hooks. we want to take these into account, but we | |
1482 | * also want to make sure these supported hugepage | |
1483 | * sizes are applicable across the entire range of memory | |
1484 | * we may boot from, so we take the min across all | |
1485 | * backends, and assume normal pages in cases where a | |
1486 | * backend isn't backed by hugepages. | |
1487 | */ | |
1488 | memdev_root = object_resolve_path("/objects", NULL); | |
1489 | if (memdev_root) { | |
1490 | object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize); | |
1491 | } | |
1492 | if (hpsize == LONG_MAX) { | |
1493 | /* No additional memory regions found ==> Report main RAM page size */ | |
1494 | return mainrampagesize; | |
1495 | } | |
1496 | ||
1497 | /* If NUMA is disabled or the NUMA nodes are not backed with a | |
1498 | * memory-backend, then there is at least one node using "normal" RAM, | |
1499 | * so if its page size is smaller we have got to report that size instead. | |
1500 | */ | |
1501 | if (hpsize > mainrampagesize && | |
1502 | (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) { | |
1503 | static bool warned; | |
1504 | if (!warned) { | |
1505 | error_report("Huge page support disabled (n/a for main memory)."); | |
1506 | warned = true; | |
1507 | } | |
1508 | return mainrampagesize; | |
1509 | } | |
1510 | ||
1511 | return hpsize; | |
1512 | } | |
1513 | #else | |
1514 | long qemu_getrampagesize(void) | |
1515 | { | |
1516 | return getpagesize(); | |
1517 | } | |
1518 | #endif | |
1519 | ||
e1e84ba0 | 1520 | #ifdef __linux__ |
d6af99c9 HZ |
1521 | static int64_t get_file_size(int fd) |
1522 | { | |
1523 | int64_t size = lseek(fd, 0, SEEK_END); | |
1524 | if (size < 0) { | |
1525 | return -errno; | |
1526 | } | |
1527 | return size; | |
1528 | } | |
1529 | ||
8d37b030 MAL |
1530 | static int file_ram_open(const char *path, |
1531 | const char *region_name, | |
1532 | bool *created, | |
1533 | Error **errp) | |
c902760f MT |
1534 | { |
1535 | char *filename; | |
8ca761f6 PF |
1536 | char *sanitized_name; |
1537 | char *c; | |
5c3ece79 | 1538 | int fd = -1; |
c902760f | 1539 | |
8d37b030 | 1540 | *created = false; |
fd97fd44 MA |
1541 | for (;;) { |
1542 | fd = open(path, O_RDWR); | |
1543 | if (fd >= 0) { | |
1544 | /* @path names an existing file, use it */ | |
1545 | break; | |
8d31d6b6 | 1546 | } |
fd97fd44 MA |
1547 | if (errno == ENOENT) { |
1548 | /* @path names a file that doesn't exist, create it */ | |
1549 | fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644); | |
1550 | if (fd >= 0) { | |
8d37b030 | 1551 | *created = true; |
fd97fd44 MA |
1552 | break; |
1553 | } | |
1554 | } else if (errno == EISDIR) { | |
1555 | /* @path names a directory, create a file there */ | |
1556 | /* Make name safe to use with mkstemp by replacing '/' with '_'. */ | |
8d37b030 | 1557 | sanitized_name = g_strdup(region_name); |
fd97fd44 MA |
1558 | for (c = sanitized_name; *c != '\0'; c++) { |
1559 | if (*c == '/') { | |
1560 | *c = '_'; | |
1561 | } | |
1562 | } | |
8ca761f6 | 1563 | |
fd97fd44 MA |
1564 | filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path, |
1565 | sanitized_name); | |
1566 | g_free(sanitized_name); | |
8d31d6b6 | 1567 | |
fd97fd44 MA |
1568 | fd = mkstemp(filename); |
1569 | if (fd >= 0) { | |
1570 | unlink(filename); | |
1571 | g_free(filename); | |
1572 | break; | |
1573 | } | |
1574 | g_free(filename); | |
8d31d6b6 | 1575 | } |
fd97fd44 MA |
1576 | if (errno != EEXIST && errno != EINTR) { |
1577 | error_setg_errno(errp, errno, | |
1578 | "can't open backing store %s for guest RAM", | |
1579 | path); | |
8d37b030 | 1580 | return -1; |
fd97fd44 MA |
1581 | } |
1582 | /* | |
1583 | * Try again on EINTR and EEXIST. The latter happens when | |
1584 | * something else creates the file between our two open(). | |
1585 | */ | |
8d31d6b6 | 1586 | } |
c902760f | 1587 | |
8d37b030 MAL |
1588 | return fd; |
1589 | } | |
1590 | ||
1591 | static void *file_ram_alloc(RAMBlock *block, | |
1592 | ram_addr_t memory, | |
1593 | int fd, | |
1594 | bool truncate, | |
1595 | Error **errp) | |
1596 | { | |
1597 | void *area; | |
1598 | ||
863e9621 | 1599 | block->page_size = qemu_fd_getpagesize(fd); |
8360668e HZ |
1600 | block->mr->align = block->page_size; |
1601 | #if defined(__s390x__) | |
1602 | if (kvm_enabled()) { | |
1603 | block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN); | |
1604 | } | |
1605 | #endif | |
fd97fd44 | 1606 | |
863e9621 | 1607 | if (memory < block->page_size) { |
fd97fd44 | 1608 | error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to " |
863e9621 DDAG |
1609 | "or larger than page size 0x%zx", |
1610 | memory, block->page_size); | |
8d37b030 | 1611 | return NULL; |
1775f111 HZ |
1612 | } |
1613 | ||
863e9621 | 1614 | memory = ROUND_UP(memory, block->page_size); |
c902760f MT |
1615 | |
1616 | /* | |
1617 | * ftruncate is not supported by hugetlbfs in older | |
1618 | * hosts, so don't bother bailing out on errors. | |
1619 | * If anything goes wrong with it under other filesystems, | |
1620 | * mmap will fail. | |
d6af99c9 HZ |
1621 | * |
1622 | * Do not truncate the non-empty backend file to avoid corrupting | |
1623 | * the existing data in the file. Disabling shrinking is not | |
1624 | * enough. For example, the current vNVDIMM implementation stores | |
1625 | * the guest NVDIMM labels at the end of the backend file. If the | |
1626 | * backend file is later extended, QEMU will not be able to find | |
1627 | * those labels. Therefore, extending the non-empty backend file | |
1628 | * is disabled as well. | |
c902760f | 1629 | */ |
8d37b030 | 1630 | if (truncate && ftruncate(fd, memory)) { |
9742bf26 | 1631 | perror("ftruncate"); |
7f56e740 | 1632 | } |
c902760f | 1633 | |
d2f39add DD |
1634 | area = qemu_ram_mmap(fd, memory, block->mr->align, |
1635 | block->flags & RAM_SHARED); | |
c902760f | 1636 | if (area == MAP_FAILED) { |
7f56e740 | 1637 | error_setg_errno(errp, errno, |
fd97fd44 | 1638 | "unable to map backing store for guest RAM"); |
8d37b030 | 1639 | return NULL; |
c902760f | 1640 | } |
ef36fa14 MT |
1641 | |
1642 | if (mem_prealloc) { | |
1e356fc1 | 1643 | os_mem_prealloc(fd, area, memory, smp_cpus, errp); |
056b68af | 1644 | if (errp && *errp) { |
8d37b030 MAL |
1645 | qemu_ram_munmap(area, memory); |
1646 | return NULL; | |
056b68af | 1647 | } |
ef36fa14 MT |
1648 | } |
1649 | ||
04b16653 | 1650 | block->fd = fd; |
c902760f MT |
1651 | return area; |
1652 | } | |
1653 | #endif | |
1654 | ||
0dc3f44a | 1655 | /* Called with the ramlist lock held. */ |
d17b5288 | 1656 | static ram_addr_t find_ram_offset(ram_addr_t size) |
04b16653 AW |
1657 | { |
1658 | RAMBlock *block, *next_block; | |
3e837b2c | 1659 | ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX; |
04b16653 | 1660 | |
49cd9ac6 SH |
1661 | assert(size != 0); /* it would hand out same offset multiple times */ |
1662 | ||
0dc3f44a | 1663 | if (QLIST_EMPTY_RCU(&ram_list.blocks)) { |
04b16653 | 1664 | return 0; |
0d53d9fe | 1665 | } |
04b16653 | 1666 | |
99e15582 | 1667 | RAMBLOCK_FOREACH(block) { |
f15fbc4b | 1668 | ram_addr_t end, next = RAM_ADDR_MAX; |
04b16653 | 1669 | |
62be4e3a | 1670 | end = block->offset + block->max_length; |
04b16653 | 1671 | |
99e15582 | 1672 | RAMBLOCK_FOREACH(next_block) { |
04b16653 AW |
1673 | if (next_block->offset >= end) { |
1674 | next = MIN(next, next_block->offset); | |
1675 | } | |
1676 | } | |
1677 | if (next - end >= size && next - end < mingap) { | |
3e837b2c | 1678 | offset = end; |
04b16653 AW |
1679 | mingap = next - end; |
1680 | } | |
1681 | } | |
3e837b2c AW |
1682 | |
1683 | if (offset == RAM_ADDR_MAX) { | |
1684 | fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n", | |
1685 | (uint64_t)size); | |
1686 | abort(); | |
1687 | } | |
1688 | ||
04b16653 AW |
1689 | return offset; |
1690 | } | |
1691 | ||
b8c48993 | 1692 | unsigned long last_ram_page(void) |
d17b5288 AW |
1693 | { |
1694 | RAMBlock *block; | |
1695 | ram_addr_t last = 0; | |
1696 | ||
0dc3f44a | 1697 | rcu_read_lock(); |
99e15582 | 1698 | RAMBLOCK_FOREACH(block) { |
62be4e3a | 1699 | last = MAX(last, block->offset + block->max_length); |
0d53d9fe | 1700 | } |
0dc3f44a | 1701 | rcu_read_unlock(); |
b8c48993 | 1702 | return last >> TARGET_PAGE_BITS; |
d17b5288 AW |
1703 | } |
1704 | ||
ddb97f1d JB |
1705 | static void qemu_ram_setup_dump(void *addr, ram_addr_t size) |
1706 | { | |
1707 | int ret; | |
ddb97f1d JB |
1708 | |
1709 | /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */ | |
47c8ca53 | 1710 | if (!machine_dump_guest_core(current_machine)) { |
ddb97f1d JB |
1711 | ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP); |
1712 | if (ret) { | |
1713 | perror("qemu_madvise"); | |
1714 | fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, " | |
1715 | "but dump_guest_core=off specified\n"); | |
1716 | } | |
1717 | } | |
1718 | } | |
1719 | ||
422148d3 DDAG |
1720 | const char *qemu_ram_get_idstr(RAMBlock *rb) |
1721 | { | |
1722 | return rb->idstr; | |
1723 | } | |
1724 | ||
463a4ac2 DDAG |
1725 | bool qemu_ram_is_shared(RAMBlock *rb) |
1726 | { | |
1727 | return rb->flags & RAM_SHARED; | |
1728 | } | |
1729 | ||
ae3a7047 | 1730 | /* Called with iothread lock held. */ |
fa53a0e5 | 1731 | void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev) |
20cfe881 | 1732 | { |
fa53a0e5 | 1733 | RAMBlock *block; |
20cfe881 | 1734 | |
c5705a77 AK |
1735 | assert(new_block); |
1736 | assert(!new_block->idstr[0]); | |
84b89d78 | 1737 | |
09e5ab63 AL |
1738 | if (dev) { |
1739 | char *id = qdev_get_dev_path(dev); | |
84b89d78 CM |
1740 | if (id) { |
1741 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); | |
7267c094 | 1742 | g_free(id); |
84b89d78 CM |
1743 | } |
1744 | } | |
1745 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); | |
1746 | ||
ab0a9956 | 1747 | rcu_read_lock(); |
99e15582 | 1748 | RAMBLOCK_FOREACH(block) { |
fa53a0e5 GA |
1749 | if (block != new_block && |
1750 | !strcmp(block->idstr, new_block->idstr)) { | |
84b89d78 CM |
1751 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", |
1752 | new_block->idstr); | |
1753 | abort(); | |
1754 | } | |
1755 | } | |
0dc3f44a | 1756 | rcu_read_unlock(); |
c5705a77 AK |
1757 | } |
1758 | ||
ae3a7047 | 1759 | /* Called with iothread lock held. */ |
fa53a0e5 | 1760 | void qemu_ram_unset_idstr(RAMBlock *block) |
20cfe881 | 1761 | { |
ae3a7047 MD |
1762 | /* FIXME: arch_init.c assumes that this is not called throughout |
1763 | * migration. Ignore the problem since hot-unplug during migration | |
1764 | * does not work anyway. | |
1765 | */ | |
20cfe881 HT |
1766 | if (block) { |
1767 | memset(block->idstr, 0, sizeof(block->idstr)); | |
1768 | } | |
1769 | } | |
1770 | ||
863e9621 DDAG |
1771 | size_t qemu_ram_pagesize(RAMBlock *rb) |
1772 | { | |
1773 | return rb->page_size; | |
1774 | } | |
1775 | ||
67f11b5c DDAG |
1776 | /* Returns the largest size of page in use */ |
1777 | size_t qemu_ram_pagesize_largest(void) | |
1778 | { | |
1779 | RAMBlock *block; | |
1780 | size_t largest = 0; | |
1781 | ||
99e15582 | 1782 | RAMBLOCK_FOREACH(block) { |
67f11b5c DDAG |
1783 | largest = MAX(largest, qemu_ram_pagesize(block)); |
1784 | } | |
1785 | ||
1786 | return largest; | |
1787 | } | |
1788 | ||
8490fc78 LC |
1789 | static int memory_try_enable_merging(void *addr, size_t len) |
1790 | { | |
75cc7f01 | 1791 | if (!machine_mem_merge(current_machine)) { |
8490fc78 LC |
1792 | /* disabled by the user */ |
1793 | return 0; | |
1794 | } | |
1795 | ||
1796 | return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE); | |
1797 | } | |
1798 | ||
62be4e3a MT |
1799 | /* Only legal before guest might have detected the memory size: e.g. on |
1800 | * incoming migration, or right after reset. | |
1801 | * | |
1802 | * As memory core doesn't know how is memory accessed, it is up to | |
1803 | * resize callback to update device state and/or add assertions to detect | |
1804 | * misuse, if necessary. | |
1805 | */ | |
fa53a0e5 | 1806 | int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp) |
62be4e3a | 1807 | { |
62be4e3a MT |
1808 | assert(block); |
1809 | ||
4ed023ce | 1810 | newsize = HOST_PAGE_ALIGN(newsize); |
129ddaf3 | 1811 | |
62be4e3a MT |
1812 | if (block->used_length == newsize) { |
1813 | return 0; | |
1814 | } | |
1815 | ||
1816 | if (!(block->flags & RAM_RESIZEABLE)) { | |
1817 | error_setg_errno(errp, EINVAL, | |
1818 | "Length mismatch: %s: 0x" RAM_ADDR_FMT | |
1819 | " in != 0x" RAM_ADDR_FMT, block->idstr, | |
1820 | newsize, block->used_length); | |
1821 | return -EINVAL; | |
1822 | } | |
1823 | ||
1824 | if (block->max_length < newsize) { | |
1825 | error_setg_errno(errp, EINVAL, | |
1826 | "Length too large: %s: 0x" RAM_ADDR_FMT | |
1827 | " > 0x" RAM_ADDR_FMT, block->idstr, | |
1828 | newsize, block->max_length); | |
1829 | return -EINVAL; | |
1830 | } | |
1831 | ||
1832 | cpu_physical_memory_clear_dirty_range(block->offset, block->used_length); | |
1833 | block->used_length = newsize; | |
58d2707e PB |
1834 | cpu_physical_memory_set_dirty_range(block->offset, block->used_length, |
1835 | DIRTY_CLIENTS_ALL); | |
62be4e3a MT |
1836 | memory_region_set_size(block->mr, newsize); |
1837 | if (block->resized) { | |
1838 | block->resized(block->idstr, newsize, block->host); | |
1839 | } | |
1840 | return 0; | |
1841 | } | |
1842 | ||
5b82b703 SH |
1843 | /* Called with ram_list.mutex held */ |
1844 | static void dirty_memory_extend(ram_addr_t old_ram_size, | |
1845 | ram_addr_t new_ram_size) | |
1846 | { | |
1847 | ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size, | |
1848 | DIRTY_MEMORY_BLOCK_SIZE); | |
1849 | ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size, | |
1850 | DIRTY_MEMORY_BLOCK_SIZE); | |
1851 | int i; | |
1852 | ||
1853 | /* Only need to extend if block count increased */ | |
1854 | if (new_num_blocks <= old_num_blocks) { | |
1855 | return; | |
1856 | } | |
1857 | ||
1858 | for (i = 0; i < DIRTY_MEMORY_NUM; i++) { | |
1859 | DirtyMemoryBlocks *old_blocks; | |
1860 | DirtyMemoryBlocks *new_blocks; | |
1861 | int j; | |
1862 | ||
1863 | old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]); | |
1864 | new_blocks = g_malloc(sizeof(*new_blocks) + | |
1865 | sizeof(new_blocks->blocks[0]) * new_num_blocks); | |
1866 | ||
1867 | if (old_num_blocks) { | |
1868 | memcpy(new_blocks->blocks, old_blocks->blocks, | |
1869 | old_num_blocks * sizeof(old_blocks->blocks[0])); | |
1870 | } | |
1871 | ||
1872 | for (j = old_num_blocks; j < new_num_blocks; j++) { | |
1873 | new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE); | |
1874 | } | |
1875 | ||
1876 | atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks); | |
1877 | ||
1878 | if (old_blocks) { | |
1879 | g_free_rcu(old_blocks, rcu); | |
1880 | } | |
1881 | } | |
1882 | } | |
1883 | ||
528f46af | 1884 | static void ram_block_add(RAMBlock *new_block, Error **errp) |
c5705a77 | 1885 | { |
e1c57ab8 | 1886 | RAMBlock *block; |
0d53d9fe | 1887 | RAMBlock *last_block = NULL; |
2152f5ca | 1888 | ram_addr_t old_ram_size, new_ram_size; |
37aa7a0e | 1889 | Error *err = NULL; |
2152f5ca | 1890 | |
b8c48993 | 1891 | old_ram_size = last_ram_page(); |
c5705a77 | 1892 | |
b2a8658e | 1893 | qemu_mutex_lock_ramlist(); |
9b8424d5 | 1894 | new_block->offset = find_ram_offset(new_block->max_length); |
e1c57ab8 PB |
1895 | |
1896 | if (!new_block->host) { | |
1897 | if (xen_enabled()) { | |
9b8424d5 | 1898 | xen_ram_alloc(new_block->offset, new_block->max_length, |
37aa7a0e MA |
1899 | new_block->mr, &err); |
1900 | if (err) { | |
1901 | error_propagate(errp, err); | |
1902 | qemu_mutex_unlock_ramlist(); | |
39c350ee | 1903 | return; |
37aa7a0e | 1904 | } |
e1c57ab8 | 1905 | } else { |
9b8424d5 | 1906 | new_block->host = phys_mem_alloc(new_block->max_length, |
a2b257d6 | 1907 | &new_block->mr->align); |
39228250 | 1908 | if (!new_block->host) { |
ef701d7b HT |
1909 | error_setg_errno(errp, errno, |
1910 | "cannot set up guest memory '%s'", | |
1911 | memory_region_name(new_block->mr)); | |
1912 | qemu_mutex_unlock_ramlist(); | |
39c350ee | 1913 | return; |
39228250 | 1914 | } |
9b8424d5 | 1915 | memory_try_enable_merging(new_block->host, new_block->max_length); |
6977dfe6 | 1916 | } |
c902760f | 1917 | } |
94a6b54f | 1918 | |
dd631697 LZ |
1919 | new_ram_size = MAX(old_ram_size, |
1920 | (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS); | |
1921 | if (new_ram_size > old_ram_size) { | |
5b82b703 | 1922 | dirty_memory_extend(old_ram_size, new_ram_size); |
dd631697 | 1923 | } |
0d53d9fe MD |
1924 | /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ, |
1925 | * QLIST (which has an RCU-friendly variant) does not have insertion at | |
1926 | * tail, so save the last element in last_block. | |
1927 | */ | |
99e15582 | 1928 | RAMBLOCK_FOREACH(block) { |
0d53d9fe | 1929 | last_block = block; |
9b8424d5 | 1930 | if (block->max_length < new_block->max_length) { |
abb26d63 PB |
1931 | break; |
1932 | } | |
1933 | } | |
1934 | if (block) { | |
0dc3f44a | 1935 | QLIST_INSERT_BEFORE_RCU(block, new_block, next); |
0d53d9fe | 1936 | } else if (last_block) { |
0dc3f44a | 1937 | QLIST_INSERT_AFTER_RCU(last_block, new_block, next); |
0d53d9fe | 1938 | } else { /* list is empty */ |
0dc3f44a | 1939 | QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next); |
abb26d63 | 1940 | } |
0d6d3c87 | 1941 | ram_list.mru_block = NULL; |
94a6b54f | 1942 | |
0dc3f44a MD |
1943 | /* Write list before version */ |
1944 | smp_wmb(); | |
f798b07f | 1945 | ram_list.version++; |
b2a8658e | 1946 | qemu_mutex_unlock_ramlist(); |
f798b07f | 1947 | |
9b8424d5 | 1948 | cpu_physical_memory_set_dirty_range(new_block->offset, |
58d2707e PB |
1949 | new_block->used_length, |
1950 | DIRTY_CLIENTS_ALL); | |
94a6b54f | 1951 | |
a904c911 PB |
1952 | if (new_block->host) { |
1953 | qemu_ram_setup_dump(new_block->host, new_block->max_length); | |
1954 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE); | |
c2cd627d | 1955 | /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */ |
a904c911 | 1956 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK); |
0987d735 | 1957 | ram_block_notify_add(new_block->host, new_block->max_length); |
e1c57ab8 | 1958 | } |
94a6b54f | 1959 | } |
e9a1ab19 | 1960 | |
0b183fc8 | 1961 | #ifdef __linux__ |
38b3362d MAL |
1962 | RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr, |
1963 | bool share, int fd, | |
1964 | Error **errp) | |
e1c57ab8 PB |
1965 | { |
1966 | RAMBlock *new_block; | |
ef701d7b | 1967 | Error *local_err = NULL; |
8d37b030 | 1968 | int64_t file_size; |
e1c57ab8 PB |
1969 | |
1970 | if (xen_enabled()) { | |
7f56e740 | 1971 | error_setg(errp, "-mem-path not supported with Xen"); |
528f46af | 1972 | return NULL; |
e1c57ab8 PB |
1973 | } |
1974 | ||
e45e7ae2 MAL |
1975 | if (kvm_enabled() && !kvm_has_sync_mmu()) { |
1976 | error_setg(errp, | |
1977 | "host lacks kvm mmu notifiers, -mem-path unsupported"); | |
1978 | return NULL; | |
1979 | } | |
1980 | ||
e1c57ab8 PB |
1981 | if (phys_mem_alloc != qemu_anon_ram_alloc) { |
1982 | /* | |
1983 | * file_ram_alloc() needs to allocate just like | |
1984 | * phys_mem_alloc, but we haven't bothered to provide | |
1985 | * a hook there. | |
1986 | */ | |
7f56e740 PB |
1987 | error_setg(errp, |
1988 | "-mem-path not supported with this accelerator"); | |
528f46af | 1989 | return NULL; |
e1c57ab8 PB |
1990 | } |
1991 | ||
4ed023ce | 1992 | size = HOST_PAGE_ALIGN(size); |
8d37b030 MAL |
1993 | file_size = get_file_size(fd); |
1994 | if (file_size > 0 && file_size < size) { | |
1995 | error_setg(errp, "backing store %s size 0x%" PRIx64 | |
1996 | " does not match 'size' option 0x" RAM_ADDR_FMT, | |
1997 | mem_path, file_size, size); | |
8d37b030 MAL |
1998 | return NULL; |
1999 | } | |
2000 | ||
e1c57ab8 PB |
2001 | new_block = g_malloc0(sizeof(*new_block)); |
2002 | new_block->mr = mr; | |
9b8424d5 MT |
2003 | new_block->used_length = size; |
2004 | new_block->max_length = size; | |
dbcb8981 | 2005 | new_block->flags = share ? RAM_SHARED : 0; |
8d37b030 | 2006 | new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp); |
7f56e740 PB |
2007 | if (!new_block->host) { |
2008 | g_free(new_block); | |
528f46af | 2009 | return NULL; |
7f56e740 PB |
2010 | } |
2011 | ||
528f46af | 2012 | ram_block_add(new_block, &local_err); |
ef701d7b HT |
2013 | if (local_err) { |
2014 | g_free(new_block); | |
2015 | error_propagate(errp, local_err); | |
528f46af | 2016 | return NULL; |
ef701d7b | 2017 | } |
528f46af | 2018 | return new_block; |
38b3362d MAL |
2019 | |
2020 | } | |
2021 | ||
2022 | ||
2023 | RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr, | |
2024 | bool share, const char *mem_path, | |
2025 | Error **errp) | |
2026 | { | |
2027 | int fd; | |
2028 | bool created; | |
2029 | RAMBlock *block; | |
2030 | ||
2031 | fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp); | |
2032 | if (fd < 0) { | |
2033 | return NULL; | |
2034 | } | |
2035 | ||
2036 | block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp); | |
2037 | if (!block) { | |
2038 | if (created) { | |
2039 | unlink(mem_path); | |
2040 | } | |
2041 | close(fd); | |
2042 | return NULL; | |
2043 | } | |
2044 | ||
2045 | return block; | |
e1c57ab8 | 2046 | } |
0b183fc8 | 2047 | #endif |
e1c57ab8 | 2048 | |
62be4e3a | 2049 | static |
528f46af FZ |
2050 | RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size, |
2051 | void (*resized)(const char*, | |
2052 | uint64_t length, | |
2053 | void *host), | |
2054 | void *host, bool resizeable, | |
2055 | MemoryRegion *mr, Error **errp) | |
e1c57ab8 PB |
2056 | { |
2057 | RAMBlock *new_block; | |
ef701d7b | 2058 | Error *local_err = NULL; |
e1c57ab8 | 2059 | |
4ed023ce DDAG |
2060 | size = HOST_PAGE_ALIGN(size); |
2061 | max_size = HOST_PAGE_ALIGN(max_size); | |
e1c57ab8 PB |
2062 | new_block = g_malloc0(sizeof(*new_block)); |
2063 | new_block->mr = mr; | |
62be4e3a | 2064 | new_block->resized = resized; |
9b8424d5 MT |
2065 | new_block->used_length = size; |
2066 | new_block->max_length = max_size; | |
62be4e3a | 2067 | assert(max_size >= size); |
e1c57ab8 | 2068 | new_block->fd = -1; |
863e9621 | 2069 | new_block->page_size = getpagesize(); |
e1c57ab8 PB |
2070 | new_block->host = host; |
2071 | if (host) { | |
7bd4f430 | 2072 | new_block->flags |= RAM_PREALLOC; |
e1c57ab8 | 2073 | } |
62be4e3a MT |
2074 | if (resizeable) { |
2075 | new_block->flags |= RAM_RESIZEABLE; | |
2076 | } | |
528f46af | 2077 | ram_block_add(new_block, &local_err); |
ef701d7b HT |
2078 | if (local_err) { |
2079 | g_free(new_block); | |
2080 | error_propagate(errp, local_err); | |
528f46af | 2081 | return NULL; |
ef701d7b | 2082 | } |
528f46af | 2083 | return new_block; |
e1c57ab8 PB |
2084 | } |
2085 | ||
528f46af | 2086 | RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, |
62be4e3a MT |
2087 | MemoryRegion *mr, Error **errp) |
2088 | { | |
2089 | return qemu_ram_alloc_internal(size, size, NULL, host, false, mr, errp); | |
2090 | } | |
2091 | ||
528f46af | 2092 | RAMBlock *qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr, Error **errp) |
6977dfe6 | 2093 | { |
62be4e3a MT |
2094 | return qemu_ram_alloc_internal(size, size, NULL, NULL, false, mr, errp); |
2095 | } | |
2096 | ||
528f46af | 2097 | RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz, |
62be4e3a MT |
2098 | void (*resized)(const char*, |
2099 | uint64_t length, | |
2100 | void *host), | |
2101 | MemoryRegion *mr, Error **errp) | |
2102 | { | |
2103 | return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, mr, errp); | |
6977dfe6 YT |
2104 | } |
2105 | ||
43771539 PB |
2106 | static void reclaim_ramblock(RAMBlock *block) |
2107 | { | |
2108 | if (block->flags & RAM_PREALLOC) { | |
2109 | ; | |
2110 | } else if (xen_enabled()) { | |
2111 | xen_invalidate_map_cache_entry(block->host); | |
2112 | #ifndef _WIN32 | |
2113 | } else if (block->fd >= 0) { | |
2f3a2bb1 | 2114 | qemu_ram_munmap(block->host, block->max_length); |
43771539 PB |
2115 | close(block->fd); |
2116 | #endif | |
2117 | } else { | |
2118 | qemu_anon_ram_free(block->host, block->max_length); | |
2119 | } | |
2120 | g_free(block); | |
2121 | } | |
2122 | ||
f1060c55 | 2123 | void qemu_ram_free(RAMBlock *block) |
e9a1ab19 | 2124 | { |
85bc2a15 MAL |
2125 | if (!block) { |
2126 | return; | |
2127 | } | |
2128 | ||
0987d735 PB |
2129 | if (block->host) { |
2130 | ram_block_notify_remove(block->host, block->max_length); | |
2131 | } | |
2132 | ||
b2a8658e | 2133 | qemu_mutex_lock_ramlist(); |
f1060c55 FZ |
2134 | QLIST_REMOVE_RCU(block, next); |
2135 | ram_list.mru_block = NULL; | |
2136 | /* Write list before version */ | |
2137 | smp_wmb(); | |
2138 | ram_list.version++; | |
2139 | call_rcu(block, reclaim_ramblock, rcu); | |
b2a8658e | 2140 | qemu_mutex_unlock_ramlist(); |
e9a1ab19 FB |
2141 | } |
2142 | ||
cd19cfa2 HY |
2143 | #ifndef _WIN32 |
2144 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) | |
2145 | { | |
2146 | RAMBlock *block; | |
2147 | ram_addr_t offset; | |
2148 | int flags; | |
2149 | void *area, *vaddr; | |
2150 | ||
99e15582 | 2151 | RAMBLOCK_FOREACH(block) { |
cd19cfa2 | 2152 | offset = addr - block->offset; |
9b8424d5 | 2153 | if (offset < block->max_length) { |
1240be24 | 2154 | vaddr = ramblock_ptr(block, offset); |
7bd4f430 | 2155 | if (block->flags & RAM_PREALLOC) { |
cd19cfa2 | 2156 | ; |
dfeaf2ab MA |
2157 | } else if (xen_enabled()) { |
2158 | abort(); | |
cd19cfa2 HY |
2159 | } else { |
2160 | flags = MAP_FIXED; | |
3435f395 | 2161 | if (block->fd >= 0) { |
dbcb8981 PB |
2162 | flags |= (block->flags & RAM_SHARED ? |
2163 | MAP_SHARED : MAP_PRIVATE); | |
3435f395 MA |
2164 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
2165 | flags, block->fd, offset); | |
cd19cfa2 | 2166 | } else { |
2eb9fbaa MA |
2167 | /* |
2168 | * Remap needs to match alloc. Accelerators that | |
2169 | * set phys_mem_alloc never remap. If they did, | |
2170 | * we'd need a remap hook here. | |
2171 | */ | |
2172 | assert(phys_mem_alloc == qemu_anon_ram_alloc); | |
2173 | ||
cd19cfa2 HY |
2174 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; |
2175 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
2176 | flags, -1, 0); | |
cd19cfa2 HY |
2177 | } |
2178 | if (area != vaddr) { | |
f15fbc4b AP |
2179 | fprintf(stderr, "Could not remap addr: " |
2180 | RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n", | |
cd19cfa2 HY |
2181 | length, addr); |
2182 | exit(1); | |
2183 | } | |
8490fc78 | 2184 | memory_try_enable_merging(vaddr, length); |
ddb97f1d | 2185 | qemu_ram_setup_dump(vaddr, length); |
cd19cfa2 | 2186 | } |
cd19cfa2 HY |
2187 | } |
2188 | } | |
2189 | } | |
2190 | #endif /* !_WIN32 */ | |
2191 | ||
1b5ec234 | 2192 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
ae3a7047 MD |
2193 | * This should not be used for general purpose DMA. Use address_space_map |
2194 | * or address_space_rw instead. For local memory (e.g. video ram) that the | |
2195 | * device owns, use memory_region_get_ram_ptr. | |
0dc3f44a | 2196 | * |
49b24afc | 2197 | * Called within RCU critical section. |
1b5ec234 | 2198 | */ |
0878d0e1 | 2199 | void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr) |
1b5ec234 | 2200 | { |
3655cb9c GA |
2201 | RAMBlock *block = ram_block; |
2202 | ||
2203 | if (block == NULL) { | |
2204 | block = qemu_get_ram_block(addr); | |
0878d0e1 | 2205 | addr -= block->offset; |
3655cb9c | 2206 | } |
ae3a7047 MD |
2207 | |
2208 | if (xen_enabled() && block->host == NULL) { | |
0d6d3c87 PB |
2209 | /* We need to check if the requested address is in the RAM |
2210 | * because we don't want to map the entire memory in QEMU. | |
2211 | * In that case just map until the end of the page. | |
2212 | */ | |
2213 | if (block->offset == 0) { | |
1ff7c598 | 2214 | return xen_map_cache(addr, 0, 0, false); |
0d6d3c87 | 2215 | } |
ae3a7047 | 2216 | |
1ff7c598 | 2217 | block->host = xen_map_cache(block->offset, block->max_length, 1, false); |
0d6d3c87 | 2218 | } |
0878d0e1 | 2219 | return ramblock_ptr(block, addr); |
dc828ca1 PB |
2220 | } |
2221 | ||
0878d0e1 | 2222 | /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr |
ae3a7047 | 2223 | * but takes a size argument. |
0dc3f44a | 2224 | * |
e81bcda5 | 2225 | * Called within RCU critical section. |
ae3a7047 | 2226 | */ |
3655cb9c | 2227 | static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr, |
f5aa69bd | 2228 | hwaddr *size, bool lock) |
38bee5dc | 2229 | { |
3655cb9c | 2230 | RAMBlock *block = ram_block; |
8ab934f9 SS |
2231 | if (*size == 0) { |
2232 | return NULL; | |
2233 | } | |
e81bcda5 | 2234 | |
3655cb9c GA |
2235 | if (block == NULL) { |
2236 | block = qemu_get_ram_block(addr); | |
0878d0e1 | 2237 | addr -= block->offset; |
3655cb9c | 2238 | } |
0878d0e1 | 2239 | *size = MIN(*size, block->max_length - addr); |
e81bcda5 PB |
2240 | |
2241 | if (xen_enabled() && block->host == NULL) { | |
2242 | /* We need to check if the requested address is in the RAM | |
2243 | * because we don't want to map the entire memory in QEMU. | |
2244 | * In that case just map the requested area. | |
2245 | */ | |
2246 | if (block->offset == 0) { | |
f5aa69bd | 2247 | return xen_map_cache(addr, *size, lock, lock); |
38bee5dc SS |
2248 | } |
2249 | ||
f5aa69bd | 2250 | block->host = xen_map_cache(block->offset, block->max_length, 1, lock); |
38bee5dc | 2251 | } |
e81bcda5 | 2252 | |
0878d0e1 | 2253 | return ramblock_ptr(block, addr); |
38bee5dc SS |
2254 | } |
2255 | ||
422148d3 DDAG |
2256 | /* |
2257 | * Translates a host ptr back to a RAMBlock, a ram_addr and an offset | |
2258 | * in that RAMBlock. | |
2259 | * | |
2260 | * ptr: Host pointer to look up | |
2261 | * round_offset: If true round the result offset down to a page boundary | |
2262 | * *ram_addr: set to result ram_addr | |
2263 | * *offset: set to result offset within the RAMBlock | |
2264 | * | |
2265 | * Returns: RAMBlock (or NULL if not found) | |
ae3a7047 MD |
2266 | * |
2267 | * By the time this function returns, the returned pointer is not protected | |
2268 | * by RCU anymore. If the caller is not within an RCU critical section and | |
2269 | * does not hold the iothread lock, it must have other means of protecting the | |
2270 | * pointer, such as a reference to the region that includes the incoming | |
2271 | * ram_addr_t. | |
2272 | */ | |
422148d3 | 2273 | RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, |
422148d3 | 2274 | ram_addr_t *offset) |
5579c7f3 | 2275 | { |
94a6b54f PB |
2276 | RAMBlock *block; |
2277 | uint8_t *host = ptr; | |
2278 | ||
868bb33f | 2279 | if (xen_enabled()) { |
f615f396 | 2280 | ram_addr_t ram_addr; |
0dc3f44a | 2281 | rcu_read_lock(); |
f615f396 PB |
2282 | ram_addr = xen_ram_addr_from_mapcache(ptr); |
2283 | block = qemu_get_ram_block(ram_addr); | |
422148d3 | 2284 | if (block) { |
d6b6aec4 | 2285 | *offset = ram_addr - block->offset; |
422148d3 | 2286 | } |
0dc3f44a | 2287 | rcu_read_unlock(); |
422148d3 | 2288 | return block; |
712c2b41 SS |
2289 | } |
2290 | ||
0dc3f44a MD |
2291 | rcu_read_lock(); |
2292 | block = atomic_rcu_read(&ram_list.mru_block); | |
9b8424d5 | 2293 | if (block && block->host && host - block->host < block->max_length) { |
23887b79 PB |
2294 | goto found; |
2295 | } | |
2296 | ||
99e15582 | 2297 | RAMBLOCK_FOREACH(block) { |
432d268c JN |
2298 | /* This case append when the block is not mapped. */ |
2299 | if (block->host == NULL) { | |
2300 | continue; | |
2301 | } | |
9b8424d5 | 2302 | if (host - block->host < block->max_length) { |
23887b79 | 2303 | goto found; |
f471a17e | 2304 | } |
94a6b54f | 2305 | } |
432d268c | 2306 | |
0dc3f44a | 2307 | rcu_read_unlock(); |
1b5ec234 | 2308 | return NULL; |
23887b79 PB |
2309 | |
2310 | found: | |
422148d3 DDAG |
2311 | *offset = (host - block->host); |
2312 | if (round_offset) { | |
2313 | *offset &= TARGET_PAGE_MASK; | |
2314 | } | |
0dc3f44a | 2315 | rcu_read_unlock(); |
422148d3 DDAG |
2316 | return block; |
2317 | } | |
2318 | ||
e3dd7493 DDAG |
2319 | /* |
2320 | * Finds the named RAMBlock | |
2321 | * | |
2322 | * name: The name of RAMBlock to find | |
2323 | * | |
2324 | * Returns: RAMBlock (or NULL if not found) | |
2325 | */ | |
2326 | RAMBlock *qemu_ram_block_by_name(const char *name) | |
2327 | { | |
2328 | RAMBlock *block; | |
2329 | ||
99e15582 | 2330 | RAMBLOCK_FOREACH(block) { |
e3dd7493 DDAG |
2331 | if (!strcmp(name, block->idstr)) { |
2332 | return block; | |
2333 | } | |
2334 | } | |
2335 | ||
2336 | return NULL; | |
2337 | } | |
2338 | ||
422148d3 DDAG |
2339 | /* Some of the softmmu routines need to translate from a host pointer |
2340 | (typically a TLB entry) back to a ram offset. */ | |
07bdaa41 | 2341 | ram_addr_t qemu_ram_addr_from_host(void *ptr) |
422148d3 DDAG |
2342 | { |
2343 | RAMBlock *block; | |
f615f396 | 2344 | ram_addr_t offset; |
422148d3 | 2345 | |
f615f396 | 2346 | block = qemu_ram_block_from_host(ptr, false, &offset); |
422148d3 | 2347 | if (!block) { |
07bdaa41 | 2348 | return RAM_ADDR_INVALID; |
422148d3 DDAG |
2349 | } |
2350 | ||
07bdaa41 | 2351 | return block->offset + offset; |
e890261f | 2352 | } |
f471a17e | 2353 | |
27266271 PM |
2354 | /* Called within RCU critical section. */ |
2355 | void memory_notdirty_write_prepare(NotDirtyInfo *ndi, | |
2356 | CPUState *cpu, | |
2357 | vaddr mem_vaddr, | |
2358 | ram_addr_t ram_addr, | |
2359 | unsigned size) | |
2360 | { | |
2361 | ndi->cpu = cpu; | |
2362 | ndi->ram_addr = ram_addr; | |
2363 | ndi->mem_vaddr = mem_vaddr; | |
2364 | ndi->size = size; | |
2365 | ndi->locked = false; | |
ba051fb5 | 2366 | |
5aa1ef71 | 2367 | assert(tcg_enabled()); |
52159192 | 2368 | if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { |
27266271 | 2369 | ndi->locked = true; |
ba051fb5 | 2370 | tb_lock(); |
0e0df1e2 | 2371 | tb_invalidate_phys_page_fast(ram_addr, size); |
3a7d929e | 2372 | } |
27266271 PM |
2373 | } |
2374 | ||
2375 | /* Called within RCU critical section. */ | |
2376 | void memory_notdirty_write_complete(NotDirtyInfo *ndi) | |
2377 | { | |
2378 | if (ndi->locked) { | |
2379 | tb_unlock(); | |
2380 | } | |
2381 | ||
2382 | /* Set both VGA and migration bits for simplicity and to remove | |
2383 | * the notdirty callback faster. | |
2384 | */ | |
2385 | cpu_physical_memory_set_dirty_range(ndi->ram_addr, ndi->size, | |
2386 | DIRTY_CLIENTS_NOCODE); | |
2387 | /* we remove the notdirty callback only if the code has been | |
2388 | flushed */ | |
2389 | if (!cpu_physical_memory_is_clean(ndi->ram_addr)) { | |
2390 | tlb_set_dirty(ndi->cpu, ndi->mem_vaddr); | |
2391 | } | |
2392 | } | |
2393 | ||
2394 | /* Called within RCU critical section. */ | |
2395 | static void notdirty_mem_write(void *opaque, hwaddr ram_addr, | |
2396 | uint64_t val, unsigned size) | |
2397 | { | |
2398 | NotDirtyInfo ndi; | |
2399 | ||
2400 | memory_notdirty_write_prepare(&ndi, current_cpu, current_cpu->mem_io_vaddr, | |
2401 | ram_addr, size); | |
2402 | ||
0e0df1e2 AK |
2403 | switch (size) { |
2404 | case 1: | |
0878d0e1 | 2405 | stb_p(qemu_map_ram_ptr(NULL, ram_addr), val); |
0e0df1e2 AK |
2406 | break; |
2407 | case 2: | |
0878d0e1 | 2408 | stw_p(qemu_map_ram_ptr(NULL, ram_addr), val); |
0e0df1e2 AK |
2409 | break; |
2410 | case 4: | |
0878d0e1 | 2411 | stl_p(qemu_map_ram_ptr(NULL, ram_addr), val); |
0e0df1e2 | 2412 | break; |
ad52878f AB |
2413 | case 8: |
2414 | stq_p(qemu_map_ram_ptr(NULL, ram_addr), val); | |
2415 | break; | |
0e0df1e2 AK |
2416 | default: |
2417 | abort(); | |
3a7d929e | 2418 | } |
27266271 | 2419 | memory_notdirty_write_complete(&ndi); |
9fa3e853 FB |
2420 | } |
2421 | ||
b018ddf6 PB |
2422 | static bool notdirty_mem_accepts(void *opaque, hwaddr addr, |
2423 | unsigned size, bool is_write) | |
2424 | { | |
2425 | return is_write; | |
2426 | } | |
2427 | ||
0e0df1e2 | 2428 | static const MemoryRegionOps notdirty_mem_ops = { |
0e0df1e2 | 2429 | .write = notdirty_mem_write, |
b018ddf6 | 2430 | .valid.accepts = notdirty_mem_accepts, |
0e0df1e2 | 2431 | .endianness = DEVICE_NATIVE_ENDIAN, |
ad52878f AB |
2432 | .valid = { |
2433 | .min_access_size = 1, | |
2434 | .max_access_size = 8, | |
2435 | .unaligned = false, | |
2436 | }, | |
2437 | .impl = { | |
2438 | .min_access_size = 1, | |
2439 | .max_access_size = 8, | |
2440 | .unaligned = false, | |
2441 | }, | |
1ccde1cb FB |
2442 | }; |
2443 | ||
0f459d16 | 2444 | /* Generate a debug exception if a watchpoint has been hit. */ |
66b9b43c | 2445 | static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags) |
0f459d16 | 2446 | { |
93afeade | 2447 | CPUState *cpu = current_cpu; |
568496c0 | 2448 | CPUClass *cc = CPU_GET_CLASS(cpu); |
0f459d16 | 2449 | target_ulong vaddr; |
a1d1bb31 | 2450 | CPUWatchpoint *wp; |
0f459d16 | 2451 | |
5aa1ef71 | 2452 | assert(tcg_enabled()); |
ff4700b0 | 2453 | if (cpu->watchpoint_hit) { |
06d55cc1 AL |
2454 | /* We re-entered the check after replacing the TB. Now raise |
2455 | * the debug interrupt so that is will trigger after the | |
2456 | * current instruction. */ | |
93afeade | 2457 | cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); |
06d55cc1 AL |
2458 | return; |
2459 | } | |
93afeade | 2460 | vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
40612000 | 2461 | vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len); |
ff4700b0 | 2462 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d PM |
2463 | if (cpu_watchpoint_address_matches(wp, vaddr, len) |
2464 | && (wp->flags & flags)) { | |
08225676 PM |
2465 | if (flags == BP_MEM_READ) { |
2466 | wp->flags |= BP_WATCHPOINT_HIT_READ; | |
2467 | } else { | |
2468 | wp->flags |= BP_WATCHPOINT_HIT_WRITE; | |
2469 | } | |
2470 | wp->hitaddr = vaddr; | |
66b9b43c | 2471 | wp->hitattrs = attrs; |
ff4700b0 | 2472 | if (!cpu->watchpoint_hit) { |
568496c0 SF |
2473 | if (wp->flags & BP_CPU && |
2474 | !cc->debug_check_watchpoint(cpu, wp)) { | |
2475 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
2476 | continue; | |
2477 | } | |
ff4700b0 | 2478 | cpu->watchpoint_hit = wp; |
a5e99826 | 2479 | |
8d04fb55 JK |
2480 | /* Both tb_lock and iothread_mutex will be reset when |
2481 | * cpu_loop_exit or cpu_loop_exit_noexc longjmp | |
2482 | * back into the cpu_exec main loop. | |
a5e99826 FK |
2483 | */ |
2484 | tb_lock(); | |
239c51a5 | 2485 | tb_check_watchpoint(cpu); |
6e140f28 | 2486 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { |
27103424 | 2487 | cpu->exception_index = EXCP_DEBUG; |
5638d180 | 2488 | cpu_loop_exit(cpu); |
6e140f28 | 2489 | } else { |
9b990ee5 RH |
2490 | /* Force execution of one insn next time. */ |
2491 | cpu->cflags_next_tb = 1 | curr_cflags(); | |
6886b980 | 2492 | cpu_loop_exit_noexc(cpu); |
6e140f28 | 2493 | } |
06d55cc1 | 2494 | } |
6e140f28 AL |
2495 | } else { |
2496 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
0f459d16 PB |
2497 | } |
2498 | } | |
2499 | } | |
2500 | ||
6658ffb8 PB |
2501 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
2502 | so these check for a hit then pass through to the normal out-of-line | |
2503 | phys routines. */ | |
66b9b43c PM |
2504 | static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata, |
2505 | unsigned size, MemTxAttrs attrs) | |
6658ffb8 | 2506 | { |
66b9b43c PM |
2507 | MemTxResult res; |
2508 | uint64_t data; | |
79ed0416 PM |
2509 | int asidx = cpu_asidx_from_attrs(current_cpu, attrs); |
2510 | AddressSpace *as = current_cpu->cpu_ases[asidx].as; | |
66b9b43c PM |
2511 | |
2512 | check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ); | |
1ec9b909 | 2513 | switch (size) { |
66b9b43c | 2514 | case 1: |
79ed0416 | 2515 | data = address_space_ldub(as, addr, attrs, &res); |
66b9b43c PM |
2516 | break; |
2517 | case 2: | |
79ed0416 | 2518 | data = address_space_lduw(as, addr, attrs, &res); |
66b9b43c PM |
2519 | break; |
2520 | case 4: | |
79ed0416 | 2521 | data = address_space_ldl(as, addr, attrs, &res); |
66b9b43c | 2522 | break; |
306526b5 PB |
2523 | case 8: |
2524 | data = address_space_ldq(as, addr, attrs, &res); | |
2525 | break; | |
1ec9b909 AK |
2526 | default: abort(); |
2527 | } | |
66b9b43c PM |
2528 | *pdata = data; |
2529 | return res; | |
6658ffb8 PB |
2530 | } |
2531 | ||
66b9b43c PM |
2532 | static MemTxResult watch_mem_write(void *opaque, hwaddr addr, |
2533 | uint64_t val, unsigned size, | |
2534 | MemTxAttrs attrs) | |
6658ffb8 | 2535 | { |
66b9b43c | 2536 | MemTxResult res; |
79ed0416 PM |
2537 | int asidx = cpu_asidx_from_attrs(current_cpu, attrs); |
2538 | AddressSpace *as = current_cpu->cpu_ases[asidx].as; | |
66b9b43c PM |
2539 | |
2540 | check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE); | |
1ec9b909 | 2541 | switch (size) { |
67364150 | 2542 | case 1: |
79ed0416 | 2543 | address_space_stb(as, addr, val, attrs, &res); |
67364150 MF |
2544 | break; |
2545 | case 2: | |
79ed0416 | 2546 | address_space_stw(as, addr, val, attrs, &res); |
67364150 MF |
2547 | break; |
2548 | case 4: | |
79ed0416 | 2549 | address_space_stl(as, addr, val, attrs, &res); |
67364150 | 2550 | break; |
306526b5 PB |
2551 | case 8: |
2552 | address_space_stq(as, addr, val, attrs, &res); | |
2553 | break; | |
1ec9b909 AK |
2554 | default: abort(); |
2555 | } | |
66b9b43c | 2556 | return res; |
6658ffb8 PB |
2557 | } |
2558 | ||
1ec9b909 | 2559 | static const MemoryRegionOps watch_mem_ops = { |
66b9b43c PM |
2560 | .read_with_attrs = watch_mem_read, |
2561 | .write_with_attrs = watch_mem_write, | |
1ec9b909 | 2562 | .endianness = DEVICE_NATIVE_ENDIAN, |
306526b5 PB |
2563 | .valid = { |
2564 | .min_access_size = 1, | |
2565 | .max_access_size = 8, | |
2566 | .unaligned = false, | |
2567 | }, | |
2568 | .impl = { | |
2569 | .min_access_size = 1, | |
2570 | .max_access_size = 8, | |
2571 | .unaligned = false, | |
2572 | }, | |
6658ffb8 | 2573 | }; |
6658ffb8 | 2574 | |
16620684 AK |
2575 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, |
2576 | const uint8_t *buf, int len); | |
2577 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, | |
2578 | bool is_write); | |
2579 | ||
f25a49e0 PM |
2580 | static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, |
2581 | unsigned len, MemTxAttrs attrs) | |
db7b5426 | 2582 | { |
acc9d80b | 2583 | subpage_t *subpage = opaque; |
ff6cff75 | 2584 | uint8_t buf[8]; |
5c9eb028 | 2585 | MemTxResult res; |
791af8c8 | 2586 | |
db7b5426 | 2587 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2588 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__, |
acc9d80b | 2589 | subpage, len, addr); |
db7b5426 | 2590 | #endif |
16620684 | 2591 | res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len); |
5c9eb028 PM |
2592 | if (res) { |
2593 | return res; | |
f25a49e0 | 2594 | } |
acc9d80b JK |
2595 | switch (len) { |
2596 | case 1: | |
f25a49e0 PM |
2597 | *data = ldub_p(buf); |
2598 | return MEMTX_OK; | |
acc9d80b | 2599 | case 2: |
f25a49e0 PM |
2600 | *data = lduw_p(buf); |
2601 | return MEMTX_OK; | |
acc9d80b | 2602 | case 4: |
f25a49e0 PM |
2603 | *data = ldl_p(buf); |
2604 | return MEMTX_OK; | |
ff6cff75 | 2605 | case 8: |
f25a49e0 PM |
2606 | *data = ldq_p(buf); |
2607 | return MEMTX_OK; | |
acc9d80b JK |
2608 | default: |
2609 | abort(); | |
2610 | } | |
db7b5426 BS |
2611 | } |
2612 | ||
f25a49e0 PM |
2613 | static MemTxResult subpage_write(void *opaque, hwaddr addr, |
2614 | uint64_t value, unsigned len, MemTxAttrs attrs) | |
db7b5426 | 2615 | { |
acc9d80b | 2616 | subpage_t *subpage = opaque; |
ff6cff75 | 2617 | uint8_t buf[8]; |
acc9d80b | 2618 | |
db7b5426 | 2619 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2620 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx |
acc9d80b JK |
2621 | " value %"PRIx64"\n", |
2622 | __func__, subpage, len, addr, value); | |
db7b5426 | 2623 | #endif |
acc9d80b JK |
2624 | switch (len) { |
2625 | case 1: | |
2626 | stb_p(buf, value); | |
2627 | break; | |
2628 | case 2: | |
2629 | stw_p(buf, value); | |
2630 | break; | |
2631 | case 4: | |
2632 | stl_p(buf, value); | |
2633 | break; | |
ff6cff75 PB |
2634 | case 8: |
2635 | stq_p(buf, value); | |
2636 | break; | |
acc9d80b JK |
2637 | default: |
2638 | abort(); | |
2639 | } | |
16620684 | 2640 | return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len); |
db7b5426 BS |
2641 | } |
2642 | ||
c353e4cc | 2643 | static bool subpage_accepts(void *opaque, hwaddr addr, |
016e9d62 | 2644 | unsigned len, bool is_write) |
c353e4cc | 2645 | { |
acc9d80b | 2646 | subpage_t *subpage = opaque; |
c353e4cc | 2647 | #if defined(DEBUG_SUBPAGE) |
016e9d62 | 2648 | printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n", |
acc9d80b | 2649 | __func__, subpage, is_write ? 'w' : 'r', len, addr); |
c353e4cc PB |
2650 | #endif |
2651 | ||
16620684 AK |
2652 | return flatview_access_valid(subpage->fv, addr + subpage->base, |
2653 | len, is_write); | |
c353e4cc PB |
2654 | } |
2655 | ||
70c68e44 | 2656 | static const MemoryRegionOps subpage_ops = { |
f25a49e0 PM |
2657 | .read_with_attrs = subpage_read, |
2658 | .write_with_attrs = subpage_write, | |
ff6cff75 PB |
2659 | .impl.min_access_size = 1, |
2660 | .impl.max_access_size = 8, | |
2661 | .valid.min_access_size = 1, | |
2662 | .valid.max_access_size = 8, | |
c353e4cc | 2663 | .valid.accepts = subpage_accepts, |
70c68e44 | 2664 | .endianness = DEVICE_NATIVE_ENDIAN, |
db7b5426 BS |
2665 | }; |
2666 | ||
c227f099 | 2667 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
5312bd8b | 2668 | uint16_t section) |
db7b5426 BS |
2669 | { |
2670 | int idx, eidx; | |
2671 | ||
2672 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
2673 | return -1; | |
2674 | idx = SUBPAGE_IDX(start); | |
2675 | eidx = SUBPAGE_IDX(end); | |
2676 | #if defined(DEBUG_SUBPAGE) | |
016e9d62 AK |
2677 | printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n", |
2678 | __func__, mmio, start, end, idx, eidx, section); | |
db7b5426 | 2679 | #endif |
db7b5426 | 2680 | for (; idx <= eidx; idx++) { |
5312bd8b | 2681 | mmio->sub_section[idx] = section; |
db7b5426 BS |
2682 | } |
2683 | ||
2684 | return 0; | |
2685 | } | |
2686 | ||
16620684 | 2687 | static subpage_t *subpage_init(FlatView *fv, hwaddr base) |
db7b5426 | 2688 | { |
c227f099 | 2689 | subpage_t *mmio; |
db7b5426 | 2690 | |
2615fabd | 2691 | mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t)); |
16620684 | 2692 | mmio->fv = fv; |
1eec614b | 2693 | mmio->base = base; |
2c9b15ca | 2694 | memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio, |
b4fefef9 | 2695 | NULL, TARGET_PAGE_SIZE); |
b3b00c78 | 2696 | mmio->iomem.subpage = true; |
db7b5426 | 2697 | #if defined(DEBUG_SUBPAGE) |
016e9d62 AK |
2698 | printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__, |
2699 | mmio, base, TARGET_PAGE_SIZE); | |
db7b5426 | 2700 | #endif |
b41aac4f | 2701 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED); |
db7b5426 BS |
2702 | |
2703 | return mmio; | |
2704 | } | |
2705 | ||
16620684 | 2706 | static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr) |
5312bd8b | 2707 | { |
16620684 | 2708 | assert(fv); |
5312bd8b | 2709 | MemoryRegionSection section = { |
16620684 | 2710 | .fv = fv, |
5312bd8b AK |
2711 | .mr = mr, |
2712 | .offset_within_address_space = 0, | |
2713 | .offset_within_region = 0, | |
052e87b0 | 2714 | .size = int128_2_64(), |
5312bd8b AK |
2715 | }; |
2716 | ||
53cb28cb | 2717 | return phys_section_add(map, §ion); |
5312bd8b AK |
2718 | } |
2719 | ||
a54c87b6 | 2720 | MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs) |
aa102231 | 2721 | { |
a54c87b6 PM |
2722 | int asidx = cpu_asidx_from_attrs(cpu, attrs); |
2723 | CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx]; | |
32857f4d | 2724 | AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch); |
79e2b9ae | 2725 | MemoryRegionSection *sections = d->map.sections; |
9d82b5a7 PB |
2726 | |
2727 | return sections[index & ~TARGET_PAGE_MASK].mr; | |
aa102231 AK |
2728 | } |
2729 | ||
e9179ce1 AK |
2730 | static void io_mem_init(void) |
2731 | { | |
1f6245e5 | 2732 | memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX); |
2c9b15ca | 2733 | memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, |
1f6245e5 | 2734 | NULL, UINT64_MAX); |
8d04fb55 JK |
2735 | |
2736 | /* io_mem_notdirty calls tb_invalidate_phys_page_fast, | |
2737 | * which can be called without the iothread mutex. | |
2738 | */ | |
2c9b15ca | 2739 | memory_region_init_io(&io_mem_notdirty, NULL, ¬dirty_mem_ops, NULL, |
1f6245e5 | 2740 | NULL, UINT64_MAX); |
8d04fb55 JK |
2741 | memory_region_clear_global_locking(&io_mem_notdirty); |
2742 | ||
2c9b15ca | 2743 | memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL, |
1f6245e5 | 2744 | NULL, UINT64_MAX); |
e9179ce1 AK |
2745 | } |
2746 | ||
8629d3fc | 2747 | AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv) |
00752703 | 2748 | { |
53cb28cb MA |
2749 | AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1); |
2750 | uint16_t n; | |
2751 | ||
16620684 | 2752 | n = dummy_section(&d->map, fv, &io_mem_unassigned); |
53cb28cb | 2753 | assert(n == PHYS_SECTION_UNASSIGNED); |
16620684 | 2754 | n = dummy_section(&d->map, fv, &io_mem_notdirty); |
53cb28cb | 2755 | assert(n == PHYS_SECTION_NOTDIRTY); |
16620684 | 2756 | n = dummy_section(&d->map, fv, &io_mem_rom); |
53cb28cb | 2757 | assert(n == PHYS_SECTION_ROM); |
16620684 | 2758 | n = dummy_section(&d->map, fv, &io_mem_watch); |
53cb28cb | 2759 | assert(n == PHYS_SECTION_WATCH); |
00752703 | 2760 | |
9736e55b | 2761 | d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 }; |
66a6df1d AK |
2762 | |
2763 | return d; | |
00752703 PB |
2764 | } |
2765 | ||
66a6df1d | 2766 | void address_space_dispatch_free(AddressSpaceDispatch *d) |
79e2b9ae PB |
2767 | { |
2768 | phys_sections_free(&d->map); | |
2769 | g_free(d); | |
2770 | } | |
2771 | ||
1d71148e | 2772 | static void tcg_commit(MemoryListener *listener) |
50c1e149 | 2773 | { |
32857f4d PM |
2774 | CPUAddressSpace *cpuas; |
2775 | AddressSpaceDispatch *d; | |
117712c3 AK |
2776 | |
2777 | /* since each CPU stores ram addresses in its TLB cache, we must | |
2778 | reset the modified entries */ | |
32857f4d PM |
2779 | cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener); |
2780 | cpu_reloading_memory_map(); | |
2781 | /* The CPU and TLB are protected by the iothread lock. | |
2782 | * We reload the dispatch pointer now because cpu_reloading_memory_map() | |
2783 | * may have split the RCU critical section. | |
2784 | */ | |
66a6df1d | 2785 | d = address_space_to_dispatch(cpuas->as); |
f35e44e7 | 2786 | atomic_rcu_set(&cpuas->memory_dispatch, d); |
d10eb08f | 2787 | tlb_flush(cpuas->cpu); |
50c1e149 AK |
2788 | } |
2789 | ||
62152b8a AK |
2790 | static void memory_map_init(void) |
2791 | { | |
7267c094 | 2792 | system_memory = g_malloc(sizeof(*system_memory)); |
03f49957 | 2793 | |
57271d63 | 2794 | memory_region_init(system_memory, NULL, "system", UINT64_MAX); |
7dca8043 | 2795 | address_space_init(&address_space_memory, system_memory, "memory"); |
309cb471 | 2796 | |
7267c094 | 2797 | system_io = g_malloc(sizeof(*system_io)); |
3bb28b72 JK |
2798 | memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io", |
2799 | 65536); | |
7dca8043 | 2800 | address_space_init(&address_space_io, system_io, "I/O"); |
62152b8a AK |
2801 | } |
2802 | ||
2803 | MemoryRegion *get_system_memory(void) | |
2804 | { | |
2805 | return system_memory; | |
2806 | } | |
2807 | ||
309cb471 AK |
2808 | MemoryRegion *get_system_io(void) |
2809 | { | |
2810 | return system_io; | |
2811 | } | |
2812 | ||
e2eef170 PB |
2813 | #endif /* !defined(CONFIG_USER_ONLY) */ |
2814 | ||
13eb76e0 FB |
2815 | /* physical memory access (slow version, mainly for debug) */ |
2816 | #if defined(CONFIG_USER_ONLY) | |
f17ec444 | 2817 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
a68fe89c | 2818 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
2819 | { |
2820 | int l, flags; | |
2821 | target_ulong page; | |
53a5960a | 2822 | void * p; |
13eb76e0 FB |
2823 | |
2824 | while (len > 0) { | |
2825 | page = addr & TARGET_PAGE_MASK; | |
2826 | l = (page + TARGET_PAGE_SIZE) - addr; | |
2827 | if (l > len) | |
2828 | l = len; | |
2829 | flags = page_get_flags(page); | |
2830 | if (!(flags & PAGE_VALID)) | |
a68fe89c | 2831 | return -1; |
13eb76e0 FB |
2832 | if (is_write) { |
2833 | if (!(flags & PAGE_WRITE)) | |
a68fe89c | 2834 | return -1; |
579a97f7 | 2835 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 2836 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
a68fe89c | 2837 | return -1; |
72fb7daa AJ |
2838 | memcpy(p, buf, l); |
2839 | unlock_user(p, addr, l); | |
13eb76e0 FB |
2840 | } else { |
2841 | if (!(flags & PAGE_READ)) | |
a68fe89c | 2842 | return -1; |
579a97f7 | 2843 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 2844 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
a68fe89c | 2845 | return -1; |
72fb7daa | 2846 | memcpy(buf, p, l); |
5b257578 | 2847 | unlock_user(p, addr, 0); |
13eb76e0 FB |
2848 | } |
2849 | len -= l; | |
2850 | buf += l; | |
2851 | addr += l; | |
2852 | } | |
a68fe89c | 2853 | return 0; |
13eb76e0 | 2854 | } |
8df1cd07 | 2855 | |
13eb76e0 | 2856 | #else |
51d7a9eb | 2857 | |
845b6214 | 2858 | static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr, |
a8170e5e | 2859 | hwaddr length) |
51d7a9eb | 2860 | { |
e87f7778 | 2861 | uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr); |
0878d0e1 PB |
2862 | addr += memory_region_get_ram_addr(mr); |
2863 | ||
e87f7778 PB |
2864 | /* No early return if dirty_log_mask is or becomes 0, because |
2865 | * cpu_physical_memory_set_dirty_range will still call | |
2866 | * xen_modified_memory. | |
2867 | */ | |
2868 | if (dirty_log_mask) { | |
2869 | dirty_log_mask = | |
2870 | cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask); | |
2871 | } | |
2872 | if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) { | |
5aa1ef71 | 2873 | assert(tcg_enabled()); |
ba051fb5 | 2874 | tb_lock(); |
e87f7778 | 2875 | tb_invalidate_phys_range(addr, addr + length); |
ba051fb5 | 2876 | tb_unlock(); |
e87f7778 | 2877 | dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE); |
51d7a9eb | 2878 | } |
e87f7778 | 2879 | cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask); |
51d7a9eb AP |
2880 | } |
2881 | ||
23326164 | 2882 | static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) |
82f2563f | 2883 | { |
e1622f4b | 2884 | unsigned access_size_max = mr->ops->valid.max_access_size; |
23326164 RH |
2885 | |
2886 | /* Regions are assumed to support 1-4 byte accesses unless | |
2887 | otherwise specified. */ | |
23326164 RH |
2888 | if (access_size_max == 0) { |
2889 | access_size_max = 4; | |
2890 | } | |
2891 | ||
2892 | /* Bound the maximum access by the alignment of the address. */ | |
2893 | if (!mr->ops->impl.unaligned) { | |
2894 | unsigned align_size_max = addr & -addr; | |
2895 | if (align_size_max != 0 && align_size_max < access_size_max) { | |
2896 | access_size_max = align_size_max; | |
2897 | } | |
82f2563f | 2898 | } |
23326164 RH |
2899 | |
2900 | /* Don't attempt accesses larger than the maximum. */ | |
2901 | if (l > access_size_max) { | |
2902 | l = access_size_max; | |
82f2563f | 2903 | } |
6554f5c0 | 2904 | l = pow2floor(l); |
23326164 RH |
2905 | |
2906 | return l; | |
82f2563f PB |
2907 | } |
2908 | ||
4840f10e | 2909 | static bool prepare_mmio_access(MemoryRegion *mr) |
125b3806 | 2910 | { |
4840f10e JK |
2911 | bool unlocked = !qemu_mutex_iothread_locked(); |
2912 | bool release_lock = false; | |
2913 | ||
2914 | if (unlocked && mr->global_locking) { | |
2915 | qemu_mutex_lock_iothread(); | |
2916 | unlocked = false; | |
2917 | release_lock = true; | |
2918 | } | |
125b3806 | 2919 | if (mr->flush_coalesced_mmio) { |
4840f10e JK |
2920 | if (unlocked) { |
2921 | qemu_mutex_lock_iothread(); | |
2922 | } | |
125b3806 | 2923 | qemu_flush_coalesced_mmio_buffer(); |
4840f10e JK |
2924 | if (unlocked) { |
2925 | qemu_mutex_unlock_iothread(); | |
2926 | } | |
125b3806 | 2927 | } |
4840f10e JK |
2928 | |
2929 | return release_lock; | |
125b3806 PB |
2930 | } |
2931 | ||
a203ac70 | 2932 | /* Called within RCU critical section. */ |
16620684 AK |
2933 | static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, |
2934 | MemTxAttrs attrs, | |
2935 | const uint8_t *buf, | |
2936 | int len, hwaddr addr1, | |
2937 | hwaddr l, MemoryRegion *mr) | |
13eb76e0 | 2938 | { |
13eb76e0 | 2939 | uint8_t *ptr; |
791af8c8 | 2940 | uint64_t val; |
3b643495 | 2941 | MemTxResult result = MEMTX_OK; |
4840f10e | 2942 | bool release_lock = false; |
3b46e624 | 2943 | |
a203ac70 | 2944 | for (;;) { |
eb7eeb88 PB |
2945 | if (!memory_access_is_direct(mr, true)) { |
2946 | release_lock |= prepare_mmio_access(mr); | |
2947 | l = memory_access_size(mr, l, addr1); | |
2948 | /* XXX: could force current_cpu to NULL to avoid | |
2949 | potential bugs */ | |
2950 | switch (l) { | |
2951 | case 8: | |
2952 | /* 64 bit write access */ | |
2953 | val = ldq_p(buf); | |
2954 | result |= memory_region_dispatch_write(mr, addr1, val, 8, | |
2955 | attrs); | |
2956 | break; | |
2957 | case 4: | |
2958 | /* 32 bit write access */ | |
6da67de6 | 2959 | val = (uint32_t)ldl_p(buf); |
eb7eeb88 PB |
2960 | result |= memory_region_dispatch_write(mr, addr1, val, 4, |
2961 | attrs); | |
2962 | break; | |
2963 | case 2: | |
2964 | /* 16 bit write access */ | |
2965 | val = lduw_p(buf); | |
2966 | result |= memory_region_dispatch_write(mr, addr1, val, 2, | |
2967 | attrs); | |
2968 | break; | |
2969 | case 1: | |
2970 | /* 8 bit write access */ | |
2971 | val = ldub_p(buf); | |
2972 | result |= memory_region_dispatch_write(mr, addr1, val, 1, | |
2973 | attrs); | |
2974 | break; | |
2975 | default: | |
2976 | abort(); | |
13eb76e0 FB |
2977 | } |
2978 | } else { | |
eb7eeb88 | 2979 | /* RAM case */ |
f5aa69bd | 2980 | ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); |
eb7eeb88 PB |
2981 | memcpy(ptr, buf, l); |
2982 | invalidate_and_set_dirty(mr, addr1, l); | |
13eb76e0 | 2983 | } |
4840f10e JK |
2984 | |
2985 | if (release_lock) { | |
2986 | qemu_mutex_unlock_iothread(); | |
2987 | release_lock = false; | |
2988 | } | |
2989 | ||
13eb76e0 FB |
2990 | len -= l; |
2991 | buf += l; | |
2992 | addr += l; | |
a203ac70 PB |
2993 | |
2994 | if (!len) { | |
2995 | break; | |
2996 | } | |
2997 | ||
2998 | l = len; | |
16620684 | 2999 | mr = flatview_translate(fv, addr, &addr1, &l, true); |
13eb76e0 | 3000 | } |
fd8aaa76 | 3001 | |
3b643495 | 3002 | return result; |
13eb76e0 | 3003 | } |
8df1cd07 | 3004 | |
16620684 AK |
3005 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, |
3006 | const uint8_t *buf, int len) | |
ac1970fb | 3007 | { |
eb7eeb88 | 3008 | hwaddr l; |
eb7eeb88 PB |
3009 | hwaddr addr1; |
3010 | MemoryRegion *mr; | |
3011 | MemTxResult result = MEMTX_OK; | |
eb7eeb88 | 3012 | |
a203ac70 PB |
3013 | if (len > 0) { |
3014 | rcu_read_lock(); | |
eb7eeb88 | 3015 | l = len; |
16620684 AK |
3016 | mr = flatview_translate(fv, addr, &addr1, &l, true); |
3017 | result = flatview_write_continue(fv, addr, attrs, buf, len, | |
3018 | addr1, l, mr); | |
a203ac70 PB |
3019 | rcu_read_unlock(); |
3020 | } | |
3021 | ||
3022 | return result; | |
3023 | } | |
3024 | ||
16620684 AK |
3025 | MemTxResult address_space_write(AddressSpace *as, hwaddr addr, |
3026 | MemTxAttrs attrs, | |
3027 | const uint8_t *buf, int len) | |
3028 | { | |
3029 | return flatview_write(address_space_to_flatview(as), addr, attrs, buf, len); | |
3030 | } | |
3031 | ||
a203ac70 | 3032 | /* Called within RCU critical section. */ |
16620684 AK |
3033 | MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, |
3034 | MemTxAttrs attrs, uint8_t *buf, | |
3035 | int len, hwaddr addr1, hwaddr l, | |
3036 | MemoryRegion *mr) | |
a203ac70 PB |
3037 | { |
3038 | uint8_t *ptr; | |
3039 | uint64_t val; | |
3040 | MemTxResult result = MEMTX_OK; | |
3041 | bool release_lock = false; | |
eb7eeb88 | 3042 | |
a203ac70 | 3043 | for (;;) { |
eb7eeb88 PB |
3044 | if (!memory_access_is_direct(mr, false)) { |
3045 | /* I/O case */ | |
3046 | release_lock |= prepare_mmio_access(mr); | |
3047 | l = memory_access_size(mr, l, addr1); | |
3048 | switch (l) { | |
3049 | case 8: | |
3050 | /* 64 bit read access */ | |
3051 | result |= memory_region_dispatch_read(mr, addr1, &val, 8, | |
3052 | attrs); | |
3053 | stq_p(buf, val); | |
3054 | break; | |
3055 | case 4: | |
3056 | /* 32 bit read access */ | |
3057 | result |= memory_region_dispatch_read(mr, addr1, &val, 4, | |
3058 | attrs); | |
3059 | stl_p(buf, val); | |
3060 | break; | |
3061 | case 2: | |
3062 | /* 16 bit read access */ | |
3063 | result |= memory_region_dispatch_read(mr, addr1, &val, 2, | |
3064 | attrs); | |
3065 | stw_p(buf, val); | |
3066 | break; | |
3067 | case 1: | |
3068 | /* 8 bit read access */ | |
3069 | result |= memory_region_dispatch_read(mr, addr1, &val, 1, | |
3070 | attrs); | |
3071 | stb_p(buf, val); | |
3072 | break; | |
3073 | default: | |
3074 | abort(); | |
3075 | } | |
3076 | } else { | |
3077 | /* RAM case */ | |
f5aa69bd | 3078 | ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); |
eb7eeb88 PB |
3079 | memcpy(buf, ptr, l); |
3080 | } | |
3081 | ||
3082 | if (release_lock) { | |
3083 | qemu_mutex_unlock_iothread(); | |
3084 | release_lock = false; | |
3085 | } | |
3086 | ||
3087 | len -= l; | |
3088 | buf += l; | |
3089 | addr += l; | |
a203ac70 PB |
3090 | |
3091 | if (!len) { | |
3092 | break; | |
3093 | } | |
3094 | ||
3095 | l = len; | |
16620684 | 3096 | mr = flatview_translate(fv, addr, &addr1, &l, false); |
a203ac70 PB |
3097 | } |
3098 | ||
3099 | return result; | |
3100 | } | |
3101 | ||
16620684 AK |
3102 | MemTxResult flatview_read_full(FlatView *fv, hwaddr addr, |
3103 | MemTxAttrs attrs, uint8_t *buf, int len) | |
a203ac70 PB |
3104 | { |
3105 | hwaddr l; | |
3106 | hwaddr addr1; | |
3107 | MemoryRegion *mr; | |
3108 | MemTxResult result = MEMTX_OK; | |
3109 | ||
3110 | if (len > 0) { | |
3111 | rcu_read_lock(); | |
3112 | l = len; | |
16620684 AK |
3113 | mr = flatview_translate(fv, addr, &addr1, &l, false); |
3114 | result = flatview_read_continue(fv, addr, attrs, buf, len, | |
3115 | addr1, l, mr); | |
a203ac70 | 3116 | rcu_read_unlock(); |
eb7eeb88 | 3117 | } |
eb7eeb88 PB |
3118 | |
3119 | return result; | |
ac1970fb AK |
3120 | } |
3121 | ||
16620684 AK |
3122 | static MemTxResult flatview_rw(FlatView *fv, hwaddr addr, MemTxAttrs attrs, |
3123 | uint8_t *buf, int len, bool is_write) | |
eb7eeb88 PB |
3124 | { |
3125 | if (is_write) { | |
16620684 | 3126 | return flatview_write(fv, addr, attrs, (uint8_t *)buf, len); |
eb7eeb88 | 3127 | } else { |
16620684 | 3128 | return flatview_read(fv, addr, attrs, (uint8_t *)buf, len); |
eb7eeb88 PB |
3129 | } |
3130 | } | |
ac1970fb | 3131 | |
16620684 AK |
3132 | MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, |
3133 | MemTxAttrs attrs, uint8_t *buf, | |
3134 | int len, bool is_write) | |
3135 | { | |
3136 | return flatview_rw(address_space_to_flatview(as), | |
3137 | addr, attrs, buf, len, is_write); | |
3138 | } | |
3139 | ||
a8170e5e | 3140 | void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, |
ac1970fb AK |
3141 | int len, int is_write) |
3142 | { | |
5c9eb028 PM |
3143 | address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED, |
3144 | buf, len, is_write); | |
ac1970fb AK |
3145 | } |
3146 | ||
582b55a9 AG |
3147 | enum write_rom_type { |
3148 | WRITE_DATA, | |
3149 | FLUSH_CACHE, | |
3150 | }; | |
3151 | ||
2a221651 | 3152 | static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as, |
582b55a9 | 3153 | hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type) |
d0ecd2aa | 3154 | { |
149f54b5 | 3155 | hwaddr l; |
d0ecd2aa | 3156 | uint8_t *ptr; |
149f54b5 | 3157 | hwaddr addr1; |
5c8a00ce | 3158 | MemoryRegion *mr; |
3b46e624 | 3159 | |
41063e1e | 3160 | rcu_read_lock(); |
d0ecd2aa | 3161 | while (len > 0) { |
149f54b5 | 3162 | l = len; |
2a221651 | 3163 | mr = address_space_translate(as, addr, &addr1, &l, true); |
3b46e624 | 3164 | |
5c8a00ce PB |
3165 | if (!(memory_region_is_ram(mr) || |
3166 | memory_region_is_romd(mr))) { | |
b242e0e0 | 3167 | l = memory_access_size(mr, l, addr1); |
d0ecd2aa | 3168 | } else { |
d0ecd2aa | 3169 | /* ROM/RAM case */ |
0878d0e1 | 3170 | ptr = qemu_map_ram_ptr(mr->ram_block, addr1); |
582b55a9 AG |
3171 | switch (type) { |
3172 | case WRITE_DATA: | |
3173 | memcpy(ptr, buf, l); | |
845b6214 | 3174 | invalidate_and_set_dirty(mr, addr1, l); |
582b55a9 AG |
3175 | break; |
3176 | case FLUSH_CACHE: | |
3177 | flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l); | |
3178 | break; | |
3179 | } | |
d0ecd2aa FB |
3180 | } |
3181 | len -= l; | |
3182 | buf += l; | |
3183 | addr += l; | |
3184 | } | |
41063e1e | 3185 | rcu_read_unlock(); |
d0ecd2aa FB |
3186 | } |
3187 | ||
582b55a9 | 3188 | /* used for ROM loading : can write in RAM and ROM */ |
2a221651 | 3189 | void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr, |
582b55a9 AG |
3190 | const uint8_t *buf, int len) |
3191 | { | |
2a221651 | 3192 | cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA); |
582b55a9 AG |
3193 | } |
3194 | ||
3195 | void cpu_flush_icache_range(hwaddr start, int len) | |
3196 | { | |
3197 | /* | |
3198 | * This function should do the same thing as an icache flush that was | |
3199 | * triggered from within the guest. For TCG we are always cache coherent, | |
3200 | * so there is no need to flush anything. For KVM / Xen we need to flush | |
3201 | * the host's instruction cache at least. | |
3202 | */ | |
3203 | if (tcg_enabled()) { | |
3204 | return; | |
3205 | } | |
3206 | ||
2a221651 EI |
3207 | cpu_physical_memory_write_rom_internal(&address_space_memory, |
3208 | start, NULL, len, FLUSH_CACHE); | |
582b55a9 AG |
3209 | } |
3210 | ||
6d16c2f8 | 3211 | typedef struct { |
d3e71559 | 3212 | MemoryRegion *mr; |
6d16c2f8 | 3213 | void *buffer; |
a8170e5e AK |
3214 | hwaddr addr; |
3215 | hwaddr len; | |
c2cba0ff | 3216 | bool in_use; |
6d16c2f8 AL |
3217 | } BounceBuffer; |
3218 | ||
3219 | static BounceBuffer bounce; | |
3220 | ||
ba223c29 | 3221 | typedef struct MapClient { |
e95205e1 | 3222 | QEMUBH *bh; |
72cf2d4f | 3223 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
3224 | } MapClient; |
3225 | ||
38e047b5 | 3226 | QemuMutex map_client_list_lock; |
72cf2d4f BS |
3227 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
3228 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
ba223c29 | 3229 | |
e95205e1 FZ |
3230 | static void cpu_unregister_map_client_do(MapClient *client) |
3231 | { | |
3232 | QLIST_REMOVE(client, link); | |
3233 | g_free(client); | |
3234 | } | |
3235 | ||
33b6c2ed FZ |
3236 | static void cpu_notify_map_clients_locked(void) |
3237 | { | |
3238 | MapClient *client; | |
3239 | ||
3240 | while (!QLIST_EMPTY(&map_client_list)) { | |
3241 | client = QLIST_FIRST(&map_client_list); | |
e95205e1 FZ |
3242 | qemu_bh_schedule(client->bh); |
3243 | cpu_unregister_map_client_do(client); | |
33b6c2ed FZ |
3244 | } |
3245 | } | |
3246 | ||
e95205e1 | 3247 | void cpu_register_map_client(QEMUBH *bh) |
ba223c29 | 3248 | { |
7267c094 | 3249 | MapClient *client = g_malloc(sizeof(*client)); |
ba223c29 | 3250 | |
38e047b5 | 3251 | qemu_mutex_lock(&map_client_list_lock); |
e95205e1 | 3252 | client->bh = bh; |
72cf2d4f | 3253 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
33b6c2ed FZ |
3254 | if (!atomic_read(&bounce.in_use)) { |
3255 | cpu_notify_map_clients_locked(); | |
3256 | } | |
38e047b5 | 3257 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
3258 | } |
3259 | ||
38e047b5 | 3260 | void cpu_exec_init_all(void) |
ba223c29 | 3261 | { |
38e047b5 | 3262 | qemu_mutex_init(&ram_list.mutex); |
20bccb82 PM |
3263 | /* The data structures we set up here depend on knowing the page size, |
3264 | * so no more changes can be made after this point. | |
3265 | * In an ideal world, nothing we did before we had finished the | |
3266 | * machine setup would care about the target page size, and we could | |
3267 | * do this much later, rather than requiring board models to state | |
3268 | * up front what their requirements are. | |
3269 | */ | |
3270 | finalize_target_page_bits(); | |
38e047b5 | 3271 | io_mem_init(); |
680a4783 | 3272 | memory_map_init(); |
38e047b5 | 3273 | qemu_mutex_init(&map_client_list_lock); |
ba223c29 AL |
3274 | } |
3275 | ||
e95205e1 | 3276 | void cpu_unregister_map_client(QEMUBH *bh) |
ba223c29 AL |
3277 | { |
3278 | MapClient *client; | |
3279 | ||
e95205e1 FZ |
3280 | qemu_mutex_lock(&map_client_list_lock); |
3281 | QLIST_FOREACH(client, &map_client_list, link) { | |
3282 | if (client->bh == bh) { | |
3283 | cpu_unregister_map_client_do(client); | |
3284 | break; | |
3285 | } | |
ba223c29 | 3286 | } |
e95205e1 | 3287 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
3288 | } |
3289 | ||
3290 | static void cpu_notify_map_clients(void) | |
3291 | { | |
38e047b5 | 3292 | qemu_mutex_lock(&map_client_list_lock); |
33b6c2ed | 3293 | cpu_notify_map_clients_locked(); |
38e047b5 | 3294 | qemu_mutex_unlock(&map_client_list_lock); |
ba223c29 AL |
3295 | } |
3296 | ||
16620684 AK |
3297 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, |
3298 | bool is_write) | |
51644ab7 | 3299 | { |
5c8a00ce | 3300 | MemoryRegion *mr; |
51644ab7 PB |
3301 | hwaddr l, xlat; |
3302 | ||
41063e1e | 3303 | rcu_read_lock(); |
51644ab7 PB |
3304 | while (len > 0) { |
3305 | l = len; | |
16620684 | 3306 | mr = flatview_translate(fv, addr, &xlat, &l, is_write); |
5c8a00ce PB |
3307 | if (!memory_access_is_direct(mr, is_write)) { |
3308 | l = memory_access_size(mr, l, addr); | |
3309 | if (!memory_region_access_valid(mr, xlat, l, is_write)) { | |
5ad4a2b7 | 3310 | rcu_read_unlock(); |
51644ab7 PB |
3311 | return false; |
3312 | } | |
3313 | } | |
3314 | ||
3315 | len -= l; | |
3316 | addr += l; | |
3317 | } | |
41063e1e | 3318 | rcu_read_unlock(); |
51644ab7 PB |
3319 | return true; |
3320 | } | |
3321 | ||
16620684 AK |
3322 | bool address_space_access_valid(AddressSpace *as, hwaddr addr, |
3323 | int len, bool is_write) | |
3324 | { | |
3325 | return flatview_access_valid(address_space_to_flatview(as), | |
3326 | addr, len, is_write); | |
3327 | } | |
3328 | ||
715c31ec | 3329 | static hwaddr |
16620684 AK |
3330 | flatview_extend_translation(FlatView *fv, hwaddr addr, |
3331 | hwaddr target_len, | |
715c31ec PB |
3332 | MemoryRegion *mr, hwaddr base, hwaddr len, |
3333 | bool is_write) | |
3334 | { | |
3335 | hwaddr done = 0; | |
3336 | hwaddr xlat; | |
3337 | MemoryRegion *this_mr; | |
3338 | ||
3339 | for (;;) { | |
3340 | target_len -= len; | |
3341 | addr += len; | |
3342 | done += len; | |
3343 | if (target_len == 0) { | |
3344 | return done; | |
3345 | } | |
3346 | ||
3347 | len = target_len; | |
16620684 AK |
3348 | this_mr = flatview_translate(fv, addr, &xlat, |
3349 | &len, is_write); | |
715c31ec PB |
3350 | if (this_mr != mr || xlat != base + done) { |
3351 | return done; | |
3352 | } | |
3353 | } | |
3354 | } | |
3355 | ||
6d16c2f8 AL |
3356 | /* Map a physical memory region into a host virtual address. |
3357 | * May map a subset of the requested range, given by and returned in *plen. | |
3358 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3359 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
3360 | * Use cpu_register_map_client() to know when retrying the map operation is |
3361 | * likely to succeed. | |
6d16c2f8 | 3362 | */ |
ac1970fb | 3363 | void *address_space_map(AddressSpace *as, |
a8170e5e AK |
3364 | hwaddr addr, |
3365 | hwaddr *plen, | |
ac1970fb | 3366 | bool is_write) |
6d16c2f8 | 3367 | { |
a8170e5e | 3368 | hwaddr len = *plen; |
715c31ec PB |
3369 | hwaddr l, xlat; |
3370 | MemoryRegion *mr; | |
e81bcda5 | 3371 | void *ptr; |
16620684 | 3372 | FlatView *fv = address_space_to_flatview(as); |
6d16c2f8 | 3373 | |
e3127ae0 PB |
3374 | if (len == 0) { |
3375 | return NULL; | |
3376 | } | |
38bee5dc | 3377 | |
e3127ae0 | 3378 | l = len; |
41063e1e | 3379 | rcu_read_lock(); |
16620684 | 3380 | mr = flatview_translate(fv, addr, &xlat, &l, is_write); |
41063e1e | 3381 | |
e3127ae0 | 3382 | if (!memory_access_is_direct(mr, is_write)) { |
c2cba0ff | 3383 | if (atomic_xchg(&bounce.in_use, true)) { |
41063e1e | 3384 | rcu_read_unlock(); |
e3127ae0 | 3385 | return NULL; |
6d16c2f8 | 3386 | } |
e85d9db5 KW |
3387 | /* Avoid unbounded allocations */ |
3388 | l = MIN(l, TARGET_PAGE_SIZE); | |
3389 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l); | |
e3127ae0 PB |
3390 | bounce.addr = addr; |
3391 | bounce.len = l; | |
d3e71559 PB |
3392 | |
3393 | memory_region_ref(mr); | |
3394 | bounce.mr = mr; | |
e3127ae0 | 3395 | if (!is_write) { |
16620684 | 3396 | flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED, |
5c9eb028 | 3397 | bounce.buffer, l); |
8ab934f9 | 3398 | } |
6d16c2f8 | 3399 | |
41063e1e | 3400 | rcu_read_unlock(); |
e3127ae0 PB |
3401 | *plen = l; |
3402 | return bounce.buffer; | |
3403 | } | |
3404 | ||
e3127ae0 | 3405 | |
d3e71559 | 3406 | memory_region_ref(mr); |
16620684 AK |
3407 | *plen = flatview_extend_translation(fv, addr, len, mr, xlat, |
3408 | l, is_write); | |
f5aa69bd | 3409 | ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true); |
e81bcda5 PB |
3410 | rcu_read_unlock(); |
3411 | ||
3412 | return ptr; | |
6d16c2f8 AL |
3413 | } |
3414 | ||
ac1970fb | 3415 | /* Unmaps a memory region previously mapped by address_space_map(). |
6d16c2f8 AL |
3416 | * Will also mark the memory as dirty if is_write == 1. access_len gives |
3417 | * the amount of memory that was actually read or written by the caller. | |
3418 | */ | |
a8170e5e AK |
3419 | void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, |
3420 | int is_write, hwaddr access_len) | |
6d16c2f8 AL |
3421 | { |
3422 | if (buffer != bounce.buffer) { | |
d3e71559 PB |
3423 | MemoryRegion *mr; |
3424 | ram_addr_t addr1; | |
3425 | ||
07bdaa41 | 3426 | mr = memory_region_from_host(buffer, &addr1); |
d3e71559 | 3427 | assert(mr != NULL); |
6d16c2f8 | 3428 | if (is_write) { |
845b6214 | 3429 | invalidate_and_set_dirty(mr, addr1, access_len); |
6d16c2f8 | 3430 | } |
868bb33f | 3431 | if (xen_enabled()) { |
e41d7c69 | 3432 | xen_invalidate_map_cache_entry(buffer); |
050a0ddf | 3433 | } |
d3e71559 | 3434 | memory_region_unref(mr); |
6d16c2f8 AL |
3435 | return; |
3436 | } | |
3437 | if (is_write) { | |
5c9eb028 PM |
3438 | address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED, |
3439 | bounce.buffer, access_len); | |
6d16c2f8 | 3440 | } |
f8a83245 | 3441 | qemu_vfree(bounce.buffer); |
6d16c2f8 | 3442 | bounce.buffer = NULL; |
d3e71559 | 3443 | memory_region_unref(bounce.mr); |
c2cba0ff | 3444 | atomic_mb_set(&bounce.in_use, false); |
ba223c29 | 3445 | cpu_notify_map_clients(); |
6d16c2f8 | 3446 | } |
d0ecd2aa | 3447 | |
a8170e5e AK |
3448 | void *cpu_physical_memory_map(hwaddr addr, |
3449 | hwaddr *plen, | |
ac1970fb AK |
3450 | int is_write) |
3451 | { | |
3452 | return address_space_map(&address_space_memory, addr, plen, is_write); | |
3453 | } | |
3454 | ||
a8170e5e AK |
3455 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
3456 | int is_write, hwaddr access_len) | |
ac1970fb AK |
3457 | { |
3458 | return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len); | |
3459 | } | |
3460 | ||
0ce265ff PB |
3461 | #define ARG1_DECL AddressSpace *as |
3462 | #define ARG1 as | |
3463 | #define SUFFIX | |
3464 | #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__) | |
3465 | #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write) | |
3466 | #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs) | |
3467 | #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len) | |
3468 | #define RCU_READ_LOCK(...) rcu_read_lock() | |
3469 | #define RCU_READ_UNLOCK(...) rcu_read_unlock() | |
3470 | #include "memory_ldst.inc.c" | |
1e78bcc1 | 3471 | |
1f4e496e PB |
3472 | int64_t address_space_cache_init(MemoryRegionCache *cache, |
3473 | AddressSpace *as, | |
3474 | hwaddr addr, | |
3475 | hwaddr len, | |
3476 | bool is_write) | |
3477 | { | |
90c4fe5f PB |
3478 | cache->len = len; |
3479 | cache->as = as; | |
3480 | cache->xlat = addr; | |
3481 | return len; | |
1f4e496e PB |
3482 | } |
3483 | ||
3484 | void address_space_cache_invalidate(MemoryRegionCache *cache, | |
3485 | hwaddr addr, | |
3486 | hwaddr access_len) | |
3487 | { | |
1f4e496e PB |
3488 | } |
3489 | ||
3490 | void address_space_cache_destroy(MemoryRegionCache *cache) | |
3491 | { | |
90c4fe5f | 3492 | cache->as = NULL; |
1f4e496e PB |
3493 | } |
3494 | ||
3495 | #define ARG1_DECL MemoryRegionCache *cache | |
3496 | #define ARG1 cache | |
3497 | #define SUFFIX _cached | |
90c4fe5f PB |
3498 | #define TRANSLATE(addr, ...) \ |
3499 | address_space_translate(cache->as, cache->xlat + (addr), __VA_ARGS__) | |
1f4e496e | 3500 | #define IS_DIRECT(mr, is_write) true |
90c4fe5f PB |
3501 | #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs) |
3502 | #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len) | |
3503 | #define RCU_READ_LOCK() rcu_read_lock() | |
3504 | #define RCU_READ_UNLOCK() rcu_read_unlock() | |
1f4e496e PB |
3505 | #include "memory_ldst.inc.c" |
3506 | ||
5e2972fd | 3507 | /* virtual memory access for debug (includes writing to ROM) */ |
f17ec444 | 3508 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, |
b448f2f3 | 3509 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
3510 | { |
3511 | int l; | |
a8170e5e | 3512 | hwaddr phys_addr; |
9b3c35e0 | 3513 | target_ulong page; |
13eb76e0 | 3514 | |
79ca7a1b | 3515 | cpu_synchronize_state(cpu); |
13eb76e0 | 3516 | while (len > 0) { |
5232e4c7 PM |
3517 | int asidx; |
3518 | MemTxAttrs attrs; | |
3519 | ||
13eb76e0 | 3520 | page = addr & TARGET_PAGE_MASK; |
5232e4c7 PM |
3521 | phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs); |
3522 | asidx = cpu_asidx_from_attrs(cpu, attrs); | |
13eb76e0 FB |
3523 | /* if no physical page mapped, return an error */ |
3524 | if (phys_addr == -1) | |
3525 | return -1; | |
3526 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3527 | if (l > len) | |
3528 | l = len; | |
5e2972fd | 3529 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
2e38847b | 3530 | if (is_write) { |
5232e4c7 PM |
3531 | cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as, |
3532 | phys_addr, buf, l); | |
2e38847b | 3533 | } else { |
5232e4c7 PM |
3534 | address_space_rw(cpu->cpu_ases[asidx].as, phys_addr, |
3535 | MEMTXATTRS_UNSPECIFIED, | |
5c9eb028 | 3536 | buf, l, 0); |
2e38847b | 3537 | } |
13eb76e0 FB |
3538 | len -= l; |
3539 | buf += l; | |
3540 | addr += l; | |
3541 | } | |
3542 | return 0; | |
3543 | } | |
038629a6 DDAG |
3544 | |
3545 | /* | |
3546 | * Allows code that needs to deal with migration bitmaps etc to still be built | |
3547 | * target independent. | |
3548 | */ | |
20afaed9 | 3549 | size_t qemu_target_page_size(void) |
038629a6 | 3550 | { |
20afaed9 | 3551 | return TARGET_PAGE_SIZE; |
038629a6 DDAG |
3552 | } |
3553 | ||
46d702b1 JQ |
3554 | int qemu_target_page_bits(void) |
3555 | { | |
3556 | return TARGET_PAGE_BITS; | |
3557 | } | |
3558 | ||
3559 | int qemu_target_page_bits_min(void) | |
3560 | { | |
3561 | return TARGET_PAGE_BITS_MIN; | |
3562 | } | |
a68fe89c | 3563 | #endif |
13eb76e0 | 3564 | |
8e4a424b BS |
3565 | /* |
3566 | * A helper function for the _utterly broken_ virtio device model to find out if | |
3567 | * it's running on a big endian machine. Don't do this at home kids! | |
3568 | */ | |
98ed8ecf GK |
3569 | bool target_words_bigendian(void); |
3570 | bool target_words_bigendian(void) | |
8e4a424b BS |
3571 | { |
3572 | #if defined(TARGET_WORDS_BIGENDIAN) | |
3573 | return true; | |
3574 | #else | |
3575 | return false; | |
3576 | #endif | |
3577 | } | |
3578 | ||
76f35538 | 3579 | #ifndef CONFIG_USER_ONLY |
a8170e5e | 3580 | bool cpu_physical_memory_is_io(hwaddr phys_addr) |
76f35538 | 3581 | { |
5c8a00ce | 3582 | MemoryRegion*mr; |
149f54b5 | 3583 | hwaddr l = 1; |
41063e1e | 3584 | bool res; |
76f35538 | 3585 | |
41063e1e | 3586 | rcu_read_lock(); |
5c8a00ce PB |
3587 | mr = address_space_translate(&address_space_memory, |
3588 | phys_addr, &phys_addr, &l, false); | |
76f35538 | 3589 | |
41063e1e PB |
3590 | res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr)); |
3591 | rcu_read_unlock(); | |
3592 | return res; | |
76f35538 | 3593 | } |
bd2fa51f | 3594 | |
e3807054 | 3595 | int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque) |
bd2fa51f MH |
3596 | { |
3597 | RAMBlock *block; | |
e3807054 | 3598 | int ret = 0; |
bd2fa51f | 3599 | |
0dc3f44a | 3600 | rcu_read_lock(); |
99e15582 | 3601 | RAMBLOCK_FOREACH(block) { |
e3807054 DDAG |
3602 | ret = func(block->idstr, block->host, block->offset, |
3603 | block->used_length, opaque); | |
3604 | if (ret) { | |
3605 | break; | |
3606 | } | |
bd2fa51f | 3607 | } |
0dc3f44a | 3608 | rcu_read_unlock(); |
e3807054 | 3609 | return ret; |
bd2fa51f | 3610 | } |
d3a5038c DDAG |
3611 | |
3612 | /* | |
3613 | * Unmap pages of memory from start to start+length such that | |
3614 | * they a) read as 0, b) Trigger whatever fault mechanism | |
3615 | * the OS provides for postcopy. | |
3616 | * The pages must be unmapped by the end of the function. | |
3617 | * Returns: 0 on success, none-0 on failure | |
3618 | * | |
3619 | */ | |
3620 | int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length) | |
3621 | { | |
3622 | int ret = -1; | |
3623 | ||
3624 | uint8_t *host_startaddr = rb->host + start; | |
3625 | ||
3626 | if ((uintptr_t)host_startaddr & (rb->page_size - 1)) { | |
3627 | error_report("ram_block_discard_range: Unaligned start address: %p", | |
3628 | host_startaddr); | |
3629 | goto err; | |
3630 | } | |
3631 | ||
3632 | if ((start + length) <= rb->used_length) { | |
3633 | uint8_t *host_endaddr = host_startaddr + length; | |
3634 | if ((uintptr_t)host_endaddr & (rb->page_size - 1)) { | |
3635 | error_report("ram_block_discard_range: Unaligned end address: %p", | |
3636 | host_endaddr); | |
3637 | goto err; | |
3638 | } | |
3639 | ||
3640 | errno = ENOTSUP; /* If we are missing MADVISE etc */ | |
3641 | ||
e2fa71f5 | 3642 | if (rb->page_size == qemu_host_page_size) { |
d3a5038c | 3643 | #if defined(CONFIG_MADVISE) |
e2fa71f5 DDAG |
3644 | /* Note: We need the madvise MADV_DONTNEED behaviour of definitely |
3645 | * freeing the page. | |
3646 | */ | |
3647 | ret = madvise(host_startaddr, length, MADV_DONTNEED); | |
d3a5038c | 3648 | #endif |
e2fa71f5 DDAG |
3649 | } else { |
3650 | /* Huge page case - unfortunately it can't do DONTNEED, but | |
3651 | * it can do the equivalent by FALLOC_FL_PUNCH_HOLE in the | |
3652 | * huge page file. | |
3653 | */ | |
3654 | #ifdef CONFIG_FALLOCATE_PUNCH_HOLE | |
3655 | ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE, | |
3656 | start, length); | |
3657 | #endif | |
3658 | } | |
d3a5038c DDAG |
3659 | if (ret) { |
3660 | ret = -errno; | |
3661 | error_report("ram_block_discard_range: Failed to discard range " | |
3662 | "%s:%" PRIx64 " +%zx (%d)", | |
3663 | rb->idstr, start, length, ret); | |
3664 | } | |
3665 | } else { | |
3666 | error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64 | |
3667 | "/%zx/" RAM_ADDR_FMT")", | |
3668 | rb->idstr, start, length, rb->used_length); | |
3669 | } | |
3670 | ||
3671 | err: | |
3672 | return ret; | |
3673 | } | |
3674 | ||
ec3f8c99 | 3675 | #endif |
a0be0c58 YZ |
3676 | |
3677 | void page_size_init(void) | |
3678 | { | |
3679 | /* NOTE: we can always suppose that qemu_host_page_size >= | |
3680 | TARGET_PAGE_SIZE */ | |
a0be0c58 YZ |
3681 | if (qemu_host_page_size == 0) { |
3682 | qemu_host_page_size = qemu_real_host_page_size; | |
3683 | } | |
3684 | if (qemu_host_page_size < TARGET_PAGE_SIZE) { | |
3685 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
3686 | } | |
3687 | qemu_host_page_mask = -(intptr_t)qemu_host_page_size; | |
3688 | } | |
5e8fd947 AK |
3689 | |
3690 | #if !defined(CONFIG_USER_ONLY) | |
3691 | ||
3692 | static void mtree_print_phys_entries(fprintf_function mon, void *f, | |
3693 | int start, int end, int skip, int ptr) | |
3694 | { | |
3695 | if (start == end - 1) { | |
3696 | mon(f, "\t%3d ", start); | |
3697 | } else { | |
3698 | mon(f, "\t%3d..%-3d ", start, end - 1); | |
3699 | } | |
3700 | mon(f, " skip=%d ", skip); | |
3701 | if (ptr == PHYS_MAP_NODE_NIL) { | |
3702 | mon(f, " ptr=NIL"); | |
3703 | } else if (!skip) { | |
3704 | mon(f, " ptr=#%d", ptr); | |
3705 | } else { | |
3706 | mon(f, " ptr=[%d]", ptr); | |
3707 | } | |
3708 | mon(f, "\n"); | |
3709 | } | |
3710 | ||
3711 | #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \ | |
3712 | int128_sub((size), int128_one())) : 0) | |
3713 | ||
3714 | void mtree_print_dispatch(fprintf_function mon, void *f, | |
3715 | AddressSpaceDispatch *d, MemoryRegion *root) | |
3716 | { | |
3717 | int i; | |
3718 | ||
3719 | mon(f, " Dispatch\n"); | |
3720 | mon(f, " Physical sections\n"); | |
3721 | ||
3722 | for (i = 0; i < d->map.sections_nb; ++i) { | |
3723 | MemoryRegionSection *s = d->map.sections + i; | |
3724 | const char *names[] = { " [unassigned]", " [not dirty]", | |
3725 | " [ROM]", " [watch]" }; | |
3726 | ||
3727 | mon(f, " #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx " %s%s%s%s%s", | |
3728 | i, | |
3729 | s->offset_within_address_space, | |
3730 | s->offset_within_address_space + MR_SIZE(s->mr->size), | |
3731 | s->mr->name ? s->mr->name : "(noname)", | |
3732 | i < ARRAY_SIZE(names) ? names[i] : "", | |
3733 | s->mr == root ? " [ROOT]" : "", | |
3734 | s == d->mru_section ? " [MRU]" : "", | |
3735 | s->mr->is_iommu ? " [iommu]" : ""); | |
3736 | ||
3737 | if (s->mr->alias) { | |
3738 | mon(f, " alias=%s", s->mr->alias->name ? | |
3739 | s->mr->alias->name : "noname"); | |
3740 | } | |
3741 | mon(f, "\n"); | |
3742 | } | |
3743 | ||
3744 | mon(f, " Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n", | |
3745 | P_L2_BITS, P_L2_LEVELS, d->phys_map.ptr, d->phys_map.skip); | |
3746 | for (i = 0; i < d->map.nodes_nb; ++i) { | |
3747 | int j, jprev; | |
3748 | PhysPageEntry prev; | |
3749 | Node *n = d->map.nodes + i; | |
3750 | ||
3751 | mon(f, " [%d]\n", i); | |
3752 | ||
3753 | for (j = 0, jprev = 0, prev = *n[0]; j < ARRAY_SIZE(*n); ++j) { | |
3754 | PhysPageEntry *pe = *n + j; | |
3755 | ||
3756 | if (pe->ptr == prev.ptr && pe->skip == prev.skip) { | |
3757 | continue; | |
3758 | } | |
3759 | ||
3760 | mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr); | |
3761 | ||
3762 | jprev = j; | |
3763 | prev = *pe; | |
3764 | } | |
3765 | ||
3766 | if (jprev != ARRAY_SIZE(*n)) { | |
3767 | mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr); | |
3768 | } | |
3769 | } | |
3770 | } | |
3771 | ||
3772 | #endif |