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Commit | Line | Data |
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327d8e4e AJ |
1 | /* |
2 | * OpenPOWER Palmetto BMC | |
3 | * | |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * | |
6 | * Copyright 2016 IBM Corp. | |
7 | * | |
8 | * This code is licensed under the GPL version 2 or later. See | |
9 | * the COPYING file in the top-level directory. | |
10 | */ | |
11 | ||
12 | #include "qemu/osdep.h" | |
da34e65c | 13 | #include "qapi/error.h" |
4771d756 | 14 | #include "cpu.h" |
327d8e4e | 15 | #include "exec/address-spaces.h" |
12ec8bd5 | 16 | #include "hw/arm/boot.h" |
fca9ca1b | 17 | #include "hw/arm/aspeed.h" |
00442402 | 18 | #include "hw/arm/aspeed_soc.h" |
327d8e4e | 19 | #include "hw/boards.h" |
93198b6c | 20 | #include "hw/i2c/smbus_eeprom.h" |
044475f3 PMD |
21 | #include "hw/misc/pca9552.h" |
22 | #include "hw/misc/tmp105.h" | |
03dd024f | 23 | #include "qemu/log.h" |
e1ad9bc4 | 24 | #include "sysemu/block-backend.h" |
ece09bee | 25 | #include "sysemu/sysemu.h" |
d769a1da CLG |
26 | #include "hw/loader.h" |
27 | #include "qemu/error-report.h" | |
a9df9622 | 28 | #include "qemu/units.h" |
327d8e4e | 29 | |
74fb1f38 | 30 | static struct arm_boot_info aspeed_board_binfo = { |
b033271f | 31 | .board_id = -1, /* device-tree-only board */ |
327d8e4e AJ |
32 | }; |
33 | ||
ea066d39 | 34 | struct AspeedBoardState { |
ff90606f | 35 | AspeedSoCState soc; |
ad1a9782 | 36 | MemoryRegion ram_container; |
327d8e4e | 37 | MemoryRegion ram; |
ebe31c0a | 38 | MemoryRegion max_ram; |
ea066d39 | 39 | }; |
327d8e4e | 40 | |
ef17f836 | 41 | /* Palmetto hardware value: 0x120CE416 */ |
8da33ef7 CLG |
42 | #define PALMETTO_BMC_HW_STRAP1 ( \ |
43 | SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ | |
44 | SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ | |
45 | SCU_AST2400_HW_STRAP_ACPI_DIS | \ | |
46 | SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ | |
47 | SCU_HW_STRAP_VGA_CLASS_CODE | \ | |
48 | SCU_HW_STRAP_LPC_RESET_PIN | \ | |
49 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ | |
50 | SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ | |
51 | SCU_HW_STRAP_SPI_WIDTH | \ | |
52 | SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ | |
53 | SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) | |
54 | ||
ef17f836 | 55 | /* AST2500 evb hardware value: 0xF100C2E6 */ |
9a7c1750 CLG |
56 | #define AST2500_EVB_HW_STRAP1 (( \ |
57 | AST2500_HW_STRAP1_DEFAULTS | \ | |
58 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
59 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
60 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
61 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
62 | SCU_HW_STRAP_MAC1_RGMII | \ | |
63 | SCU_HW_STRAP_MAC0_RGMII) & \ | |
64 | ~SCU_HW_STRAP_2ND_BOOT_WDT) | |
65 | ||
ef17f836 CLG |
66 | /* Romulus hardware value: 0xF10AD206 */ |
67 | #define ROMULUS_BMC_HW_STRAP1 ( \ | |
68 | AST2500_HW_STRAP1_DEFAULTS | \ | |
69 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
70 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
71 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
72 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
73 | SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ | |
74 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) | |
75 | ||
aae7a18d AK |
76 | /* Swift hardware value: 0xF11AD206 */ |
77 | #define SWIFT_BMC_HW_STRAP1 ( \ | |
78 | AST2500_HW_STRAP1_DEFAULTS | \ | |
79 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
80 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
81 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
82 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
83 | SCU_H_PLL_BYPASS_EN | \ | |
84 | SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ | |
85 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) | |
86 | ||
62c2c2eb CLG |
87 | /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ |
88 | #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 | |
89 | ||
ebe31c0a CLG |
90 | /* |
91 | * The max ram region is for firmwares that scan the address space | |
92 | * with load/store to guess how much RAM the SoC has. | |
93 | */ | |
94 | static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) | |
95 | { | |
96 | return 0; | |
97 | } | |
98 | ||
99 | static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, | |
100 | unsigned size) | |
101 | { | |
102 | /* Discard writes */ | |
103 | } | |
104 | ||
105 | static const MemoryRegionOps max_ram_ops = { | |
106 | .read = max_ram_read, | |
107 | .write = max_ram_write, | |
108 | .endianness = DEVICE_NATIVE_ENDIAN, | |
109 | }; | |
110 | ||
d769a1da CLG |
111 | #define FIRMWARE_ADDR 0x0 |
112 | ||
113 | static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, | |
114 | Error **errp) | |
115 | { | |
116 | BlockBackend *blk = blk_by_legacy_dinfo(dinfo); | |
117 | uint8_t *storage; | |
0c7209be CLG |
118 | int64_t size; |
119 | ||
120 | /* The block backend size should have already been 'validated' by | |
121 | * the creation of the m25p80 object. | |
122 | */ | |
123 | size = blk_getlength(blk); | |
124 | if (size <= 0) { | |
125 | error_setg(errp, "failed to get flash size"); | |
126 | return; | |
127 | } | |
d769a1da | 128 | |
0c7209be CLG |
129 | if (rom_size > size) { |
130 | rom_size = size; | |
d769a1da CLG |
131 | } |
132 | ||
133 | storage = g_new0(uint8_t, rom_size); | |
134 | if (blk_pread(blk, 0, storage, rom_size) < 0) { | |
135 | error_setg(errp, "failed to read the initial flash content"); | |
136 | return; | |
137 | } | |
138 | ||
139 | rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); | |
140 | g_free(storage); | |
141 | } | |
142 | ||
74fb1f38 | 143 | static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, |
e1ad9bc4 CLG |
144 | Error **errp) |
145 | { | |
146 | int i ; | |
147 | ||
148 | for (i = 0; i < s->num_cs; ++i) { | |
149 | AspeedSMCFlash *fl = &s->flashes[i]; | |
150 | DriveInfo *dinfo = drive_get_next(IF_MTD); | |
151 | qemu_irq cs_line; | |
152 | ||
e1ad9bc4 CLG |
153 | fl->flash = ssi_create_slave_no_init(s->spi, flashtype); |
154 | if (dinfo) { | |
155 | qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo), | |
156 | errp); | |
157 | } | |
158 | qdev_init_nofail(fl->flash); | |
159 | ||
160 | cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); | |
161 | sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); | |
162 | } | |
163 | } | |
164 | ||
c3ba99f7 CLG |
165 | static void aspeed_board_init(MachineState *machine, |
166 | const AspeedBoardConfig *cfg) | |
327d8e4e | 167 | { |
74fb1f38 | 168 | AspeedBoardState *bmc; |
b033271f | 169 | AspeedSoCClass *sc; |
d769a1da | 170 | DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); |
ebe31c0a | 171 | ram_addr_t max_ram_size; |
327d8e4e | 172 | |
74fb1f38 | 173 | bmc = g_new0(AspeedBoardState, 1); |
ad1a9782 CLG |
174 | |
175 | memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", | |
176 | UINT32_MAX); | |
177 | ||
1b0ad567 PMD |
178 | object_initialize_child(OBJECT(machine), "soc", &bmc->soc, |
179 | (sizeof(bmc->soc)), cfg->soc_name, &error_abort, | |
180 | NULL); | |
327d8e4e | 181 | |
b033271f CLG |
182 | sc = ASPEED_SOC_GET_CLASS(&bmc->soc); |
183 | ||
19e9cdf0 MAL |
184 | object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size", |
185 | &error_abort); | |
c3ba99f7 | 186 | object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1", |
87e79af0 | 187 | &error_abort); |
26d5df95 CLG |
188 | object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs", |
189 | &error_abort); | |
ece09bee CLG |
190 | object_property_set_int(OBJECT(&bmc->soc), smp_cpus, "num-cpus", |
191 | &error_abort); | |
b6e70d1d JS |
192 | if (machine->kernel_filename) { |
193 | /* | |
194 | * When booting with a -kernel command line there is no u-boot | |
195 | * that runs to unlock the SCU. In this case set the default to | |
196 | * be unlocked as the kernel expects | |
197 | */ | |
198 | object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY, | |
199 | "hw-prot-key", &error_abort); | |
200 | } | |
327d8e4e AJ |
201 | object_property_set_bool(OBJECT(&bmc->soc), true, "realized", |
202 | &error_abort); | |
203 | ||
de46f5f4 CLG |
204 | /* |
205 | * Allocate RAM after the memory controller has checked the size | |
206 | * was valid. If not, a default value is used. | |
207 | */ | |
19e9cdf0 MAL |
208 | ram_size = object_property_get_uint(OBJECT(&bmc->soc), "ram-size", |
209 | &error_abort); | |
de46f5f4 CLG |
210 | |
211 | memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size); | |
ad1a9782 | 212 | memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram); |
d783d1fe | 213 | memory_region_add_subregion(get_system_memory(), |
ad1a9782 CLG |
214 | sc->info->memmap[ASPEED_SDRAM], |
215 | &bmc->ram_container); | |
de46f5f4 | 216 | |
ebe31c0a CLG |
217 | max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", |
218 | &error_abort); | |
219 | memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, | |
220 | "max_ram", max_ram_size - ram_size); | |
ad1a9782 | 221 | memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram); |
ebe31c0a | 222 | |
6a0e947b CLG |
223 | aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort); |
224 | aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort); | |
74fb1f38 | 225 | |
d769a1da CLG |
226 | /* Install first FMC flash content as a boot rom. */ |
227 | if (drive0) { | |
228 | AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; | |
229 | MemoryRegion *boot_rom = g_new(MemoryRegion, 1); | |
230 | ||
231 | /* | |
232 | * create a ROM region using the default mapping window size of | |
93bf276d CLG |
233 | * the flash module. The window size is 64MB for the AST2400 |
234 | * SoC and 128MB for the AST2500 SoC, which is twice as big as | |
235 | * needed by the flash modules of the Aspeed machines. | |
d769a1da | 236 | */ |
44cf837d | 237 | memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", |
d769a1da CLG |
238 | fl->size, &error_abort); |
239 | memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, | |
240 | boot_rom); | |
241 | write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); | |
242 | } | |
243 | ||
74fb1f38 CLG |
244 | aspeed_board_binfo.kernel_filename = machine->kernel_filename; |
245 | aspeed_board_binfo.initrd_filename = machine->initrd_filename; | |
246 | aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline; | |
247 | aspeed_board_binfo.ram_size = ram_size; | |
d783d1fe | 248 | aspeed_board_binfo.loader_start = sc->info->memmap[ASPEED_SDRAM]; |
ece09bee | 249 | aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus; |
e1ad9bc4 | 250 | |
2cf6cb50 CLG |
251 | if (cfg->i2c_init) { |
252 | cfg->i2c_init(bmc); | |
253 | } | |
254 | ||
74fb1f38 CLG |
255 | arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo); |
256 | } | |
b033271f | 257 | |
2cf6cb50 CLG |
258 | static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) |
259 | { | |
260 | AspeedSoCState *soc = &bmc->soc; | |
a87e81b9 | 261 | DeviceState *dev; |
3d165f12 | 262 | uint8_t *eeprom_buf = g_malloc0(32 * 1024); |
2cf6cb50 CLG |
263 | |
264 | /* The palmetto platform expects a ds3231 RTC but a ds1338 is | |
265 | * enough to provide basic RTC features. Alarms will be missing */ | |
266 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68); | |
a87e81b9 | 267 | |
3d165f12 CLG |
268 | smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), 0x50, |
269 | eeprom_buf); | |
270 | ||
a87e81b9 CLG |
271 | /* add a TMP423 temperature sensor */ |
272 | dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), | |
273 | "tmp423", 0x4c); | |
274 | object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort); | |
275 | object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort); | |
276 | object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort); | |
277 | object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort); | |
2cf6cb50 CLG |
278 | } |
279 | ||
2cf6cb50 CLG |
280 | static void ast2500_evb_i2c_init(AspeedBoardState *bmc) |
281 | { | |
282 | AspeedSoCState *soc = &bmc->soc; | |
3d165f12 CLG |
283 | uint8_t *eeprom_buf = g_malloc0(8 * 1024); |
284 | ||
285 | smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), 0x50, | |
286 | eeprom_buf); | |
2cf6cb50 CLG |
287 | |
288 | /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ | |
044475f3 PMD |
289 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), |
290 | TYPE_TMP105, 0x4d); | |
6c4567c7 CLG |
291 | |
292 | /* The AST2500 EVB does not have an RTC. Let's pretend that one is | |
293 | * plugged on the I2C bus header */ | |
294 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); | |
2cf6cb50 CLG |
295 | } |
296 | ||
6c4567c7 CLG |
297 | static void romulus_bmc_i2c_init(AspeedBoardState *bmc) |
298 | { | |
299 | AspeedSoCState *soc = &bmc->soc; | |
300 | ||
301 | /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is | |
302 | * good enough */ | |
303 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); | |
304 | } | |
305 | ||
aae7a18d AK |
306 | static void swift_bmc_i2c_init(AspeedBoardState *bmc) |
307 | { | |
308 | AspeedSoCState *soc = &bmc->soc; | |
309 | ||
310 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), "pca9552", 0x60); | |
311 | ||
312 | /* The swift board expects a TMP275 but a TMP105 is compatible */ | |
313 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x48); | |
314 | /* The swift board expects a pca9551 but a pca9552 is compatible */ | |
315 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "pca9552", 0x60); | |
316 | ||
317 | /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ | |
318 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "ds1338", 0x32); | |
319 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x60); | |
320 | ||
321 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp423", 0x4c); | |
322 | /* The swift board expects a pca9539 but a pca9552 is compatible */ | |
323 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "pca9552", 0x74); | |
324 | ||
325 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "tmp423", 0x4c); | |
326 | /* The swift board expects a pca9539 but a pca9552 is compatible */ | |
327 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "pca9552", | |
328 | 0x74); | |
329 | ||
330 | /* The swift board expects a TMP275 but a TMP105 is compatible */ | |
331 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x48); | |
332 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x4a); | |
333 | } | |
334 | ||
62c2c2eb CLG |
335 | static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) |
336 | { | |
337 | AspeedSoCState *soc = &bmc->soc; | |
3d165f12 | 338 | uint8_t *eeprom_buf = g_malloc0(8 * 1024); |
62c2c2eb | 339 | |
044475f3 PMD |
340 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), TYPE_PCA9552, |
341 | 0x60); | |
8c9a61d7 | 342 | |
62c2c2eb CLG |
343 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c); |
344 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c); | |
345 | ||
346 | /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ | |
044475f3 PMD |
347 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), TYPE_TMP105, |
348 | 0x4a); | |
6c4567c7 CLG |
349 | |
350 | /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is | |
351 | * good enough */ | |
352 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); | |
3d165f12 CLG |
353 | |
354 | smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51, | |
355 | eeprom_buf); | |
044475f3 | 356 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), TYPE_PCA9552, |
8c9a61d7 | 357 | 0x60); |
62c2c2eb CLG |
358 | } |
359 | ||
fca9ca1b | 360 | static void aspeed_machine_init(MachineState *machine) |
62c2c2eb | 361 | { |
fca9ca1b CLG |
362 | AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); |
363 | ||
364 | aspeed_board_init(machine, amc->board); | |
62c2c2eb CLG |
365 | } |
366 | ||
fca9ca1b | 367 | static void aspeed_machine_class_init(ObjectClass *oc, void *data) |
62c2c2eb CLG |
368 | { |
369 | MachineClass *mc = MACHINE_CLASS(oc); | |
fca9ca1b CLG |
370 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); |
371 | const AspeedBoardConfig *board = data; | |
62c2c2eb | 372 | |
fca9ca1b CLG |
373 | mc->desc = board->desc; |
374 | mc->init = aspeed_machine_init; | |
ece09bee | 375 | mc->max_cpus = ASPEED_CPUS_NUM; |
62c2c2eb CLG |
376 | mc->no_sdcard = 1; |
377 | mc->no_floppy = 1; | |
378 | mc->no_cdrom = 1; | |
379 | mc->no_parallel = 1; | |
a9df9622 JS |
380 | if (board->ram) { |
381 | mc->default_ram_size = board->ram; | |
382 | } | |
fca9ca1b | 383 | amc->board = board; |
62c2c2eb CLG |
384 | } |
385 | ||
fca9ca1b CLG |
386 | static const TypeInfo aspeed_machine_type = { |
387 | .name = TYPE_ASPEED_MACHINE, | |
62c2c2eb | 388 | .parent = TYPE_MACHINE, |
fca9ca1b CLG |
389 | .instance_size = sizeof(AspeedMachine), |
390 | .class_size = sizeof(AspeedMachineClass), | |
391 | .abstract = true, | |
392 | }; | |
393 | ||
394 | static const AspeedBoardConfig aspeed_boards[] = { | |
395 | { | |
396 | .name = MACHINE_TYPE_NAME("palmetto-bmc"), | |
397 | .desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)", | |
398 | .soc_name = "ast2400-a1", | |
399 | .hw_strap1 = PALMETTO_BMC_HW_STRAP1, | |
400 | .fmc_model = "n25q256a", | |
401 | .spi_model = "mx25l25635e", | |
402 | .num_cs = 1, | |
403 | .i2c_init = palmetto_bmc_i2c_init, | |
a9df9622 | 404 | .ram = 256 * MiB, |
fca9ca1b CLG |
405 | }, { |
406 | .name = MACHINE_TYPE_NAME("ast2500-evb"), | |
407 | .desc = "Aspeed AST2500 EVB (ARM1176)", | |
408 | .soc_name = "ast2500-a1", | |
409 | .hw_strap1 = AST2500_EVB_HW_STRAP1, | |
410 | .fmc_model = "w25q256", | |
411 | .spi_model = "mx25l25635e", | |
412 | .num_cs = 1, | |
413 | .i2c_init = ast2500_evb_i2c_init, | |
a9df9622 | 414 | .ram = 512 * MiB, |
fca9ca1b CLG |
415 | }, { |
416 | .name = MACHINE_TYPE_NAME("romulus-bmc"), | |
417 | .desc = "OpenPOWER Romulus BMC (ARM1176)", | |
418 | .soc_name = "ast2500-a1", | |
419 | .hw_strap1 = ROMULUS_BMC_HW_STRAP1, | |
420 | .fmc_model = "n25q256a", | |
421 | .spi_model = "mx66l1g45g", | |
422 | .num_cs = 2, | |
423 | .i2c_init = romulus_bmc_i2c_init, | |
a9df9622 | 424 | .ram = 512 * MiB, |
aae7a18d AK |
425 | }, { |
426 | .name = MACHINE_TYPE_NAME("swift-bmc"), | |
427 | .desc = "OpenPOWER Swift BMC (ARM1176)", | |
428 | .soc_name = "ast2500-a1", | |
429 | .hw_strap1 = SWIFT_BMC_HW_STRAP1, | |
430 | .fmc_model = "mx66l1g45g", | |
431 | .spi_model = "mx66l1g45g", | |
432 | .num_cs = 2, | |
433 | .i2c_init = swift_bmc_i2c_init, | |
434 | .ram = 512 * MiB, | |
fca9ca1b CLG |
435 | }, { |
436 | .name = MACHINE_TYPE_NAME("witherspoon-bmc"), | |
437 | .desc = "OpenPOWER Witherspoon BMC (ARM1176)", | |
438 | .soc_name = "ast2500-a1", | |
439 | .hw_strap1 = WITHERSPOON_BMC_HW_STRAP1, | |
440 | .fmc_model = "mx25l25635e", | |
441 | .spi_model = "mx66l1g45g", | |
442 | .num_cs = 2, | |
443 | .i2c_init = witherspoon_bmc_i2c_init, | |
a9df9622 | 444 | .ram = 512 * MiB, |
fca9ca1b | 445 | }, |
62c2c2eb CLG |
446 | }; |
447 | ||
fca9ca1b | 448 | static void aspeed_machine_types(void) |
74fb1f38 | 449 | { |
fca9ca1b CLG |
450 | int i; |
451 | ||
452 | type_register_static(&aspeed_machine_type); | |
453 | for (i = 0; i < ARRAY_SIZE(aspeed_boards); ++i) { | |
454 | TypeInfo ti = { | |
455 | .name = aspeed_boards[i].name, | |
456 | .parent = TYPE_ASPEED_MACHINE, | |
457 | .class_init = aspeed_machine_class_init, | |
458 | .class_data = (void *)&aspeed_boards[i], | |
459 | }; | |
460 | type_register(&ti); | |
461 | } | |
74fb1f38 CLG |
462 | } |
463 | ||
fca9ca1b | 464 | type_init(aspeed_machine_types) |