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f25c0ae1 CLG |
1 | /* |
2 | * ASPEED SoC 2600 family | |
3 | * | |
4 | * Copyright (c) 2016-2019, IBM Corporation. | |
5 | * | |
6 | * This code is licensed under the GPL version 2 or later. See | |
7 | * the COPYING file in the top-level directory. | |
8 | */ | |
9 | ||
10 | #include "qemu/osdep.h" | |
11 | #include "qapi/error.h" | |
f25c0ae1 CLG |
12 | #include "hw/misc/unimp.h" |
13 | #include "hw/arm/aspeed_soc.h" | |
14 | #include "hw/char/serial.h" | |
f25c0ae1 CLG |
15 | #include "qemu/module.h" |
16 | #include "qemu/error-report.h" | |
17 | #include "hw/i2c/aspeed_i2c.h" | |
18 | #include "net/net.h" | |
19 | #include "sysemu/sysemu.h" | |
20 | ||
21 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 | |
22 | ||
23 | static const hwaddr aspeed_soc_ast2600_memmap[] = { | |
347df6f8 | 24 | [ASPEED_DEV_SRAM] = 0x10000000, |
f25c0ae1 | 25 | /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ |
347df6f8 EH |
26 | [ASPEED_DEV_IOMEM] = 0x1E600000, |
27 | [ASPEED_DEV_PWM] = 0x1E610000, | |
28 | [ASPEED_DEV_FMC] = 0x1E620000, | |
29 | [ASPEED_DEV_SPI1] = 0x1E630000, | |
30 | [ASPEED_DEV_SPI2] = 0x1E641000, | |
31 | [ASPEED_DEV_EHCI1] = 0x1E6A1000, | |
32 | [ASPEED_DEV_EHCI2] = 0x1E6A3000, | |
33 | [ASPEED_DEV_MII1] = 0x1E650000, | |
34 | [ASPEED_DEV_MII2] = 0x1E650008, | |
35 | [ASPEED_DEV_MII3] = 0x1E650010, | |
36 | [ASPEED_DEV_MII4] = 0x1E650018, | |
37 | [ASPEED_DEV_ETH1] = 0x1E660000, | |
38 | [ASPEED_DEV_ETH3] = 0x1E670000, | |
39 | [ASPEED_DEV_ETH2] = 0x1E680000, | |
40 | [ASPEED_DEV_ETH4] = 0x1E690000, | |
41 | [ASPEED_DEV_VIC] = 0x1E6C0000, | |
a3888d75 | 42 | [ASPEED_DEV_HACE] = 0x1E6D0000, |
347df6f8 EH |
43 | [ASPEED_DEV_SDMC] = 0x1E6E0000, |
44 | [ASPEED_DEV_SCU] = 0x1E6E2000, | |
45 | [ASPEED_DEV_XDMA] = 0x1E6E7000, | |
46 | [ASPEED_DEV_ADC] = 0x1E6E9000, | |
47 | [ASPEED_DEV_VIDEO] = 0x1E700000, | |
48 | [ASPEED_DEV_SDHCI] = 0x1E740000, | |
49 | [ASPEED_DEV_EMMC] = 0x1E750000, | |
50 | [ASPEED_DEV_GPIO] = 0x1E780000, | |
51 | [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, | |
52 | [ASPEED_DEV_RTC] = 0x1E781000, | |
53 | [ASPEED_DEV_TIMER1] = 0x1E782000, | |
54 | [ASPEED_DEV_WDT] = 0x1E785000, | |
55 | [ASPEED_DEV_LPC] = 0x1E789000, | |
56 | [ASPEED_DEV_IBT] = 0x1E789140, | |
57 | [ASPEED_DEV_I2C] = 0x1E78A000, | |
58 | [ASPEED_DEV_UART1] = 0x1E783000, | |
59 | [ASPEED_DEV_UART5] = 0x1E784000, | |
60 | [ASPEED_DEV_VUART] = 0x1E787000, | |
61 | [ASPEED_DEV_SDRAM] = 0x80000000, | |
f25c0ae1 CLG |
62 | }; |
63 | ||
64 | #define ASPEED_A7MPCORE_ADDR 0x40460000 | |
65 | ||
b151de69 | 66 | #define AST2600_MAX_IRQ 197 |
f25c0ae1 | 67 | |
a29e3e12 | 68 | /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ |
f25c0ae1 | 69 | static const int aspeed_soc_ast2600_irqmap[] = { |
347df6f8 EH |
70 | [ASPEED_DEV_UART1] = 47, |
71 | [ASPEED_DEV_UART2] = 48, | |
72 | [ASPEED_DEV_UART3] = 49, | |
73 | [ASPEED_DEV_UART4] = 50, | |
74 | [ASPEED_DEV_UART5] = 8, | |
75 | [ASPEED_DEV_VUART] = 8, | |
76 | [ASPEED_DEV_FMC] = 39, | |
77 | [ASPEED_DEV_SDMC] = 0, | |
78 | [ASPEED_DEV_SCU] = 12, | |
79 | [ASPEED_DEV_ADC] = 78, | |
80 | [ASPEED_DEV_XDMA] = 6, | |
81 | [ASPEED_DEV_SDHCI] = 43, | |
82 | [ASPEED_DEV_EHCI1] = 5, | |
83 | [ASPEED_DEV_EHCI2] = 9, | |
84 | [ASPEED_DEV_EMMC] = 15, | |
85 | [ASPEED_DEV_GPIO] = 40, | |
86 | [ASPEED_DEV_GPIO_1_8V] = 11, | |
87 | [ASPEED_DEV_RTC] = 13, | |
88 | [ASPEED_DEV_TIMER1] = 16, | |
89 | [ASPEED_DEV_TIMER2] = 17, | |
90 | [ASPEED_DEV_TIMER3] = 18, | |
91 | [ASPEED_DEV_TIMER4] = 19, | |
92 | [ASPEED_DEV_TIMER5] = 20, | |
93 | [ASPEED_DEV_TIMER6] = 21, | |
94 | [ASPEED_DEV_TIMER7] = 22, | |
95 | [ASPEED_DEV_TIMER8] = 23, | |
96 | [ASPEED_DEV_WDT] = 24, | |
97 | [ASPEED_DEV_PWM] = 44, | |
98 | [ASPEED_DEV_LPC] = 35, | |
6820588e | 99 | [ASPEED_DEV_IBT] = 143, |
347df6f8 EH |
100 | [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ |
101 | [ASPEED_DEV_ETH1] = 2, | |
102 | [ASPEED_DEV_ETH2] = 3, | |
a3888d75 | 103 | [ASPEED_DEV_HACE] = 4, |
347df6f8 EH |
104 | [ASPEED_DEV_ETH3] = 32, |
105 | [ASPEED_DEV_ETH4] = 33, | |
c59f781e | 106 | [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ |
f25c0ae1 CLG |
107 | }; |
108 | ||
109 | static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) | |
110 | { | |
111 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
112 | ||
113 | return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); | |
114 | } | |
115 | ||
116 | static void aspeed_soc_ast2600_init(Object *obj) | |
117 | { | |
118 | AspeedSoCState *s = ASPEED_SOC(obj); | |
119 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
120 | int i; | |
121 | char socname[8]; | |
122 | char typename[64]; | |
123 | ||
124 | if (sscanf(sc->name, "%7s", socname) != 1) { | |
125 | g_assert_not_reached(); | |
126 | } | |
127 | ||
128 | for (i = 0; i < sc->num_cpus; i++) { | |
9fc7fc4d | 129 | object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); |
f25c0ae1 CLG |
130 | } |
131 | ||
132 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); | |
db873cc5 | 133 | object_initialize_child(obj, "scu", &s->scu, typename); |
f25c0ae1 CLG |
134 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", |
135 | sc->silicon_rev); | |
136 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), | |
d2623129 | 137 | "hw-strap1"); |
f25c0ae1 | 138 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), |
d2623129 | 139 | "hw-strap2"); |
f25c0ae1 | 140 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
d2623129 | 141 | "hw-prot-key"); |
f25c0ae1 | 142 | |
db873cc5 MA |
143 | object_initialize_child(obj, "a7mpcore", &s->a7mpcore, |
144 | TYPE_A15MPCORE_PRIV); | |
f25c0ae1 | 145 | |
db873cc5 | 146 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); |
f25c0ae1 CLG |
147 | |
148 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); | |
db873cc5 | 149 | object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); |
f25c0ae1 | 150 | |
199fd623 AJ |
151 | snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); |
152 | object_initialize_child(obj, "adc", &s->adc, typename); | |
153 | ||
f25c0ae1 | 154 | snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); |
db873cc5 | 155 | object_initialize_child(obj, "i2c", &s->i2c, typename); |
f25c0ae1 CLG |
156 | |
157 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); | |
db873cc5 | 158 | object_initialize_child(obj, "fmc", &s->fmc, typename); |
d2623129 | 159 | object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); |
f25c0ae1 CLG |
160 | |
161 | for (i = 0; i < sc->spis_num; i++) { | |
162 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); | |
db873cc5 | 163 | object_initialize_child(obj, "spi[*]", &s->spi[i], typename); |
f25c0ae1 CLG |
164 | } |
165 | ||
917940ce | 166 | for (i = 0; i < sc->ehcis_num; i++) { |
db873cc5 MA |
167 | object_initialize_child(obj, "ehci[*]", &s->ehci[i], |
168 | TYPE_PLATFORM_EHCI); | |
917940ce GR |
169 | } |
170 | ||
f25c0ae1 | 171 | snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); |
db873cc5 | 172 | object_initialize_child(obj, "sdmc", &s->sdmc, typename); |
f25c0ae1 | 173 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
d2623129 | 174 | "ram-size"); |
f25c0ae1 | 175 | object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), |
d2623129 | 176 | "max-ram-size"); |
f25c0ae1 CLG |
177 | |
178 | for (i = 0; i < sc->wdts_num; i++) { | |
179 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); | |
db873cc5 | 180 | object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); |
f25c0ae1 CLG |
181 | } |
182 | ||
d300db02 | 183 | for (i = 0; i < sc->macs_num; i++) { |
db873cc5 MA |
184 | object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], |
185 | TYPE_FTGMAC100); | |
289251b0 | 186 | |
db873cc5 | 187 | object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); |
f25c0ae1 CLG |
188 | } |
189 | ||
8efbee28 CLG |
190 | snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); |
191 | object_initialize_child(obj, "xdma", &s->xdma, typename); | |
f25c0ae1 CLG |
192 | |
193 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); | |
db873cc5 | 194 | object_initialize_child(obj, "gpio", &s->gpio, typename); |
f25c0ae1 CLG |
195 | |
196 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); | |
db873cc5 | 197 | object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); |
f25c0ae1 | 198 | |
db873cc5 MA |
199 | object_initialize_child(obj, "sd-controller", &s->sdhci, |
200 | TYPE_ASPEED_SDHCI); | |
f25c0ae1 | 201 | |
5325cc34 | 202 | object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); |
0e2c24c6 | 203 | |
f25c0ae1 CLG |
204 | /* Init sd card slot class here so that they're under the correct parent */ |
205 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | |
7089e0cc MA |
206 | object_initialize_child(obj, "sd-controller.sdhci[*]", |
207 | &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); | |
f25c0ae1 | 208 | } |
a29e3e12 | 209 | |
db873cc5 MA |
210 | object_initialize_child(obj, "emmc-controller", &s->emmc, |
211 | TYPE_ASPEED_SDHCI); | |
a29e3e12 | 212 | |
5325cc34 | 213 | object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); |
a29e3e12 | 214 | |
7089e0cc MA |
215 | object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], |
216 | TYPE_SYSBUS_SDHCI); | |
2ecf1726 CLG |
217 | |
218 | object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); | |
a3888d75 JS |
219 | |
220 | snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); | |
221 | object_initialize_child(obj, "hace", &s->hace, typename); | |
f25c0ae1 CLG |
222 | } |
223 | ||
224 | /* | |
225 | * ASPEED ast2600 has 0xf as cluster ID | |
226 | * | |
932a8d1f | 227 | * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register |
f25c0ae1 CLG |
228 | */ |
229 | static uint64_t aspeed_calc_affinity(int cpu) | |
230 | { | |
231 | return (0xf << ARM_AFF1_SHIFT) | cpu; | |
232 | } | |
233 | ||
234 | static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | |
235 | { | |
236 | int i; | |
237 | AspeedSoCState *s = ASPEED_SOC(dev); | |
238 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
123327d1 | 239 | Error *err = NULL; |
f25c0ae1 CLG |
240 | qemu_irq irq; |
241 | ||
242 | /* IO space */ | |
347df6f8 | 243 | create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM], |
f25c0ae1 CLG |
244 | ASPEED_SOC_IOMEM_SIZE); |
245 | ||
514bcf6f | 246 | /* Video engine stub */ |
347df6f8 | 247 | create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], |
514bcf6f JS |
248 | 0x1000); |
249 | ||
f25c0ae1 | 250 | /* CPU */ |
b7f1a0cb | 251 | for (i = 0; i < sc->num_cpus; i++) { |
b7f1a0cb | 252 | if (sc->num_cpus > 1) { |
5325cc34 MA |
253 | object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", |
254 | ASPEED_A7MPCORE_ADDR, &error_abort); | |
f25c0ae1 | 255 | } |
5325cc34 MA |
256 | object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", |
257 | aspeed_calc_affinity(i), &error_abort); | |
f25c0ae1 | 258 | |
5325cc34 | 259 | object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, |
058d0955 AJ |
260 | &error_abort); |
261 | ||
668f62ec | 262 | if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { |
f25c0ae1 CLG |
263 | return; |
264 | } | |
265 | } | |
266 | ||
267 | /* A7MPCORE */ | |
5325cc34 | 268 | object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, |
f25c0ae1 | 269 | &error_abort); |
5325cc34 | 270 | object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", |
957ad79f | 271 | ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), |
5325cc34 | 272 | &error_abort); |
f25c0ae1 | 273 | |
db873cc5 | 274 | sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); |
f25c0ae1 CLG |
275 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); |
276 | ||
b7f1a0cb | 277 | for (i = 0; i < sc->num_cpus; i++) { |
f25c0ae1 CLG |
278 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); |
279 | DeviceState *d = DEVICE(qemu_get_cpu(i)); | |
280 | ||
281 | irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); | |
282 | sysbus_connect_irq(sbd, i, irq); | |
283 | irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); | |
b7f1a0cb | 284 | sysbus_connect_irq(sbd, i + sc->num_cpus, irq); |
f25c0ae1 | 285 | irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); |
b7f1a0cb | 286 | sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); |
f25c0ae1 | 287 | irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); |
b7f1a0cb | 288 | sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); |
f25c0ae1 CLG |
289 | } |
290 | ||
291 | /* SRAM */ | |
292 | memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", | |
293 | sc->sram_size, &err); | |
294 | if (err) { | |
295 | error_propagate(errp, err); | |
296 | return; | |
297 | } | |
298 | memory_region_add_subregion(get_system_memory(), | |
347df6f8 | 299 | sc->memmap[ASPEED_DEV_SRAM], &s->sram); |
f25c0ae1 CLG |
300 | |
301 | /* SCU */ | |
668f62ec | 302 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { |
f25c0ae1 CLG |
303 | return; |
304 | } | |
347df6f8 | 305 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); |
f25c0ae1 CLG |
306 | |
307 | /* RTC */ | |
668f62ec | 308 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { |
f25c0ae1 CLG |
309 | return; |
310 | } | |
347df6f8 | 311 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); |
f25c0ae1 | 312 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, |
347df6f8 | 313 | aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); |
f25c0ae1 CLG |
314 | |
315 | /* Timer */ | |
5325cc34 MA |
316 | object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), |
317 | &error_abort); | |
668f62ec | 318 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { |
f25c0ae1 CLG |
319 | return; |
320 | } | |
321 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, | |
347df6f8 | 322 | sc->memmap[ASPEED_DEV_TIMER1]); |
f25c0ae1 | 323 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { |
347df6f8 | 324 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); |
f25c0ae1 CLG |
325 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); |
326 | } | |
327 | ||
199fd623 AJ |
328 | /* ADC */ |
329 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { | |
330 | return; | |
331 | } | |
332 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); | |
333 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, | |
334 | aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); | |
335 | ||
5d63d0c7 PD |
336 | /* UART - attach an 8250 to the IO space as our UART */ |
337 | serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, | |
338 | aspeed_soc_get_irq(s, s->uart_default), 38400, | |
339 | serial_hd(0), DEVICE_LITTLE_ENDIAN); | |
f25c0ae1 CLG |
340 | |
341 | /* I2C */ | |
5325cc34 | 342 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), |
c24d9716 | 343 | &error_abort); |
668f62ec | 344 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { |
f25c0ae1 CLG |
345 | return; |
346 | } | |
347df6f8 | 347 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); |
f25c0ae1 CLG |
348 | for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { |
349 | qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
347df6f8 | 350 | sc->irqmap[ASPEED_DEV_I2C] + i); |
60261038 CLG |
351 | /* The AST2600 I2C controller has one IRQ per bus. */ |
352 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); | |
f25c0ae1 CLG |
353 | } |
354 | ||
355 | /* FMC, The number of CS is set at the board level */ | |
5325cc34 | 356 | object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), |
c24d9716 | 357 | &error_abort); |
668f62ec | 358 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { |
f25c0ae1 CLG |
359 | return; |
360 | } | |
347df6f8 | 361 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); |
f25c0ae1 | 362 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, |
30b6852c | 363 | ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); |
f25c0ae1 | 364 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, |
347df6f8 | 365 | aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); |
f25c0ae1 CLG |
366 | |
367 | /* SPI */ | |
368 | for (i = 0; i < sc->spis_num; i++) { | |
5325cc34 MA |
369 | object_property_set_link(OBJECT(&s->spi[i]), "dram", |
370 | OBJECT(s->dram_mr), &error_abort); | |
371 | object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort); | |
668f62ec | 372 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
f25c0ae1 CLG |
373 | return; |
374 | } | |
375 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, | |
347df6f8 | 376 | sc->memmap[ASPEED_DEV_SPI1 + i]); |
f25c0ae1 | 377 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, |
30b6852c | 378 | ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); |
f25c0ae1 CLG |
379 | } |
380 | ||
917940ce GR |
381 | /* EHCI */ |
382 | for (i = 0; i < sc->ehcis_num; i++) { | |
668f62ec | 383 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { |
917940ce GR |
384 | return; |
385 | } | |
386 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, | |
347df6f8 | 387 | sc->memmap[ASPEED_DEV_EHCI1 + i]); |
917940ce | 388 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, |
347df6f8 | 389 | aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); |
917940ce GR |
390 | } |
391 | ||
f25c0ae1 | 392 | /* SDMC - SDRAM Memory Controller */ |
668f62ec | 393 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { |
f25c0ae1 CLG |
394 | return; |
395 | } | |
347df6f8 | 396 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); |
f25c0ae1 CLG |
397 | |
398 | /* Watch dog */ | |
399 | for (i = 0; i < sc->wdts_num; i++) { | |
400 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); | |
401 | ||
5325cc34 MA |
402 | object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), |
403 | &error_abort); | |
668f62ec | 404 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { |
f25c0ae1 CLG |
405 | return; |
406 | } | |
407 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | |
347df6f8 | 408 | sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); |
f25c0ae1 CLG |
409 | } |
410 | ||
411 | /* Net */ | |
d3bad7e7 | 412 | for (i = 0; i < sc->macs_num; i++) { |
5325cc34 | 413 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, |
2255f6b7 | 414 | &error_abort); |
668f62ec | 415 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { |
123327d1 | 416 | return; |
f25c0ae1 CLG |
417 | } |
418 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | |
347df6f8 | 419 | sc->memmap[ASPEED_DEV_ETH1 + i]); |
f25c0ae1 | 420 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
347df6f8 | 421 | aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); |
289251b0 | 422 | |
5325cc34 MA |
423 | object_property_set_link(OBJECT(&s->mii[i]), "nic", |
424 | OBJECT(&s->ftgmac100[i]), &error_abort); | |
668f62ec | 425 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { |
289251b0 CLG |
426 | return; |
427 | } | |
428 | ||
429 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, | |
347df6f8 | 430 | sc->memmap[ASPEED_DEV_MII1 + i]); |
f25c0ae1 CLG |
431 | } |
432 | ||
433 | /* XDMA */ | |
668f62ec | 434 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { |
f25c0ae1 CLG |
435 | return; |
436 | } | |
437 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, | |
347df6f8 | 438 | sc->memmap[ASPEED_DEV_XDMA]); |
f25c0ae1 | 439 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, |
347df6f8 | 440 | aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); |
f25c0ae1 CLG |
441 | |
442 | /* GPIO */ | |
668f62ec | 443 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
f25c0ae1 CLG |
444 | return; |
445 | } | |
347df6f8 | 446 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); |
f25c0ae1 | 447 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, |
347df6f8 | 448 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); |
f25c0ae1 | 449 | |
668f62ec | 450 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { |
f25c0ae1 CLG |
451 | return; |
452 | } | |
453 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, | |
347df6f8 | 454 | sc->memmap[ASPEED_DEV_GPIO_1_8V]); |
f25c0ae1 | 455 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, |
347df6f8 | 456 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); |
f25c0ae1 CLG |
457 | |
458 | /* SDHCI */ | |
668f62ec | 459 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { |
f25c0ae1 CLG |
460 | return; |
461 | } | |
462 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | |
347df6f8 | 463 | sc->memmap[ASPEED_DEV_SDHCI]); |
f25c0ae1 | 464 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, |
347df6f8 | 465 | aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); |
a29e3e12 AJ |
466 | |
467 | /* eMMC */ | |
668f62ec | 468 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { |
a29e3e12 AJ |
469 | return; |
470 | } | |
347df6f8 | 471 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); |
a29e3e12 | 472 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, |
347df6f8 | 473 | aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); |
2ecf1726 CLG |
474 | |
475 | /* LPC */ | |
476 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { | |
477 | return; | |
478 | } | |
479 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); | |
c59f781e AJ |
480 | |
481 | /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ | |
2ecf1726 CLG |
482 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, |
483 | aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); | |
c59f781e AJ |
484 | |
485 | /* | |
486 | * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. | |
487 | * | |
488 | * LPC subdevice IRQ sources are offset from 1 because the LPC model caters | |
489 | * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ | |
490 | * shared across the subdevices, and the shared IRQ output to the VIC is at | |
491 | * offset 0. | |
492 | */ | |
493 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, | |
494 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
495 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); | |
496 | ||
497 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, | |
498 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
499 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); | |
500 | ||
501 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, | |
502 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
503 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); | |
504 | ||
505 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, | |
506 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
507 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); | |
a3888d75 JS |
508 | |
509 | /* HACE */ | |
510 | object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), | |
511 | &error_abort); | |
512 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { | |
513 | return; | |
514 | } | |
515 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); | |
516 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, | |
517 | aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); | |
f25c0ae1 CLG |
518 | } |
519 | ||
520 | static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) | |
521 | { | |
522 | DeviceClass *dc = DEVICE_CLASS(oc); | |
523 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | |
524 | ||
525 | dc->realize = aspeed_soc_ast2600_realize; | |
526 | ||
c5811bb3 | 527 | sc->name = "ast2600-a3"; |
f25c0ae1 | 528 | sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); |
c5811bb3 | 529 | sc->silicon_rev = AST2600_A3_SILICON_REV; |
e01b4d5b | 530 | sc->sram_size = 0x16400; |
f25c0ae1 | 531 | sc->spis_num = 2; |
917940ce | 532 | sc->ehcis_num = 2; |
f25c0ae1 | 533 | sc->wdts_num = 4; |
d300db02 | 534 | sc->macs_num = 4; |
f25c0ae1 CLG |
535 | sc->irqmap = aspeed_soc_ast2600_irqmap; |
536 | sc->memmap = aspeed_soc_ast2600_memmap; | |
537 | sc->num_cpus = 2; | |
538 | } | |
539 | ||
540 | static const TypeInfo aspeed_soc_ast2600_type_info = { | |
c5811bb3 | 541 | .name = "ast2600-a3", |
f25c0ae1 CLG |
542 | .parent = TYPE_ASPEED_SOC, |
543 | .instance_size = sizeof(AspeedSoCState), | |
544 | .instance_init = aspeed_soc_ast2600_init, | |
545 | .class_init = aspeed_soc_ast2600_class_init, | |
546 | .class_size = sizeof(AspeedSoCClass), | |
547 | }; | |
548 | ||
549 | static void aspeed_soc_register_types(void) | |
550 | { | |
551 | type_register_static(&aspeed_soc_ast2600_type_info); | |
552 | }; | |
553 | ||
554 | type_init(aspeed_soc_register_types) |