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f25c0ae1 CLG |
1 | /* |
2 | * ASPEED SoC 2600 family | |
3 | * | |
4 | * Copyright (c) 2016-2019, IBM Corporation. | |
5 | * | |
6 | * This code is licensed under the GPL version 2 or later. See | |
7 | * the COPYING file in the top-level directory. | |
8 | */ | |
9 | ||
10 | #include "qemu/osdep.h" | |
11 | #include "qapi/error.h" | |
f25c0ae1 CLG |
12 | #include "hw/misc/unimp.h" |
13 | #include "hw/arm/aspeed_soc.h" | |
14 | #include "hw/char/serial.h" | |
f25c0ae1 CLG |
15 | #include "qemu/module.h" |
16 | #include "qemu/error-report.h" | |
17 | #include "hw/i2c/aspeed_i2c.h" | |
18 | #include "net/net.h" | |
19 | #include "sysemu/sysemu.h" | |
20 | ||
21 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 | |
d9e9cd59 | 22 | #define ASPEED_SOC_DPMCU_SIZE 0x00040000 |
f25c0ae1 CLG |
23 | |
24 | static const hwaddr aspeed_soc_ast2600_memmap[] = { | |
347df6f8 | 25 | [ASPEED_DEV_SRAM] = 0x10000000, |
d9e9cd59 | 26 | [ASPEED_DEV_DPMCU] = 0x18000000, |
f25c0ae1 | 27 | /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ |
347df6f8 EH |
28 | [ASPEED_DEV_IOMEM] = 0x1E600000, |
29 | [ASPEED_DEV_PWM] = 0x1E610000, | |
30 | [ASPEED_DEV_FMC] = 0x1E620000, | |
31 | [ASPEED_DEV_SPI1] = 0x1E630000, | |
08048cbd | 32 | [ASPEED_DEV_SPI2] = 0x1E631000, |
347df6f8 EH |
33 | [ASPEED_DEV_EHCI1] = 0x1E6A1000, |
34 | [ASPEED_DEV_EHCI2] = 0x1E6A3000, | |
35 | [ASPEED_DEV_MII1] = 0x1E650000, | |
36 | [ASPEED_DEV_MII2] = 0x1E650008, | |
37 | [ASPEED_DEV_MII3] = 0x1E650010, | |
38 | [ASPEED_DEV_MII4] = 0x1E650018, | |
39 | [ASPEED_DEV_ETH1] = 0x1E660000, | |
40 | [ASPEED_DEV_ETH3] = 0x1E670000, | |
41 | [ASPEED_DEV_ETH2] = 0x1E680000, | |
42 | [ASPEED_DEV_ETH4] = 0x1E690000, | |
43 | [ASPEED_DEV_VIC] = 0x1E6C0000, | |
a3888d75 | 44 | [ASPEED_DEV_HACE] = 0x1E6D0000, |
347df6f8 EH |
45 | [ASPEED_DEV_SDMC] = 0x1E6E0000, |
46 | [ASPEED_DEV_SCU] = 0x1E6E2000, | |
47 | [ASPEED_DEV_XDMA] = 0x1E6E7000, | |
48 | [ASPEED_DEV_ADC] = 0x1E6E9000, | |
d9e9cd59 | 49 | [ASPEED_DEV_DP] = 0x1E6EB000, |
e1acf581 | 50 | [ASPEED_DEV_SBC] = 0x1E6F2000, |
347df6f8 EH |
51 | [ASPEED_DEV_VIDEO] = 0x1E700000, |
52 | [ASPEED_DEV_SDHCI] = 0x1E740000, | |
53 | [ASPEED_DEV_EMMC] = 0x1E750000, | |
54 | [ASPEED_DEV_GPIO] = 0x1E780000, | |
55 | [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, | |
56 | [ASPEED_DEV_RTC] = 0x1E781000, | |
57 | [ASPEED_DEV_TIMER1] = 0x1E782000, | |
58 | [ASPEED_DEV_WDT] = 0x1E785000, | |
59 | [ASPEED_DEV_LPC] = 0x1E789000, | |
60 | [ASPEED_DEV_IBT] = 0x1E789140, | |
61 | [ASPEED_DEV_I2C] = 0x1E78A000, | |
62 | [ASPEED_DEV_UART1] = 0x1E783000, | |
63 | [ASPEED_DEV_UART5] = 0x1E784000, | |
64 | [ASPEED_DEV_VUART] = 0x1E787000, | |
3222165d | 65 | [ASPEED_DEV_I3C] = 0x1E7A0000, |
347df6f8 | 66 | [ASPEED_DEV_SDRAM] = 0x80000000, |
f25c0ae1 CLG |
67 | }; |
68 | ||
69 | #define ASPEED_A7MPCORE_ADDR 0x40460000 | |
70 | ||
b151de69 | 71 | #define AST2600_MAX_IRQ 197 |
f25c0ae1 | 72 | |
a29e3e12 | 73 | /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ |
f25c0ae1 | 74 | static const int aspeed_soc_ast2600_irqmap[] = { |
347df6f8 EH |
75 | [ASPEED_DEV_UART1] = 47, |
76 | [ASPEED_DEV_UART2] = 48, | |
77 | [ASPEED_DEV_UART3] = 49, | |
78 | [ASPEED_DEV_UART4] = 50, | |
79 | [ASPEED_DEV_UART5] = 8, | |
80 | [ASPEED_DEV_VUART] = 8, | |
81 | [ASPEED_DEV_FMC] = 39, | |
82 | [ASPEED_DEV_SDMC] = 0, | |
83 | [ASPEED_DEV_SCU] = 12, | |
84 | [ASPEED_DEV_ADC] = 78, | |
85 | [ASPEED_DEV_XDMA] = 6, | |
86 | [ASPEED_DEV_SDHCI] = 43, | |
87 | [ASPEED_DEV_EHCI1] = 5, | |
88 | [ASPEED_DEV_EHCI2] = 9, | |
89 | [ASPEED_DEV_EMMC] = 15, | |
90 | [ASPEED_DEV_GPIO] = 40, | |
91 | [ASPEED_DEV_GPIO_1_8V] = 11, | |
92 | [ASPEED_DEV_RTC] = 13, | |
93 | [ASPEED_DEV_TIMER1] = 16, | |
94 | [ASPEED_DEV_TIMER2] = 17, | |
95 | [ASPEED_DEV_TIMER3] = 18, | |
96 | [ASPEED_DEV_TIMER4] = 19, | |
97 | [ASPEED_DEV_TIMER5] = 20, | |
98 | [ASPEED_DEV_TIMER6] = 21, | |
99 | [ASPEED_DEV_TIMER7] = 22, | |
100 | [ASPEED_DEV_TIMER8] = 23, | |
101 | [ASPEED_DEV_WDT] = 24, | |
102 | [ASPEED_DEV_PWM] = 44, | |
103 | [ASPEED_DEV_LPC] = 35, | |
6820588e | 104 | [ASPEED_DEV_IBT] = 143, |
347df6f8 EH |
105 | [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ |
106 | [ASPEED_DEV_ETH1] = 2, | |
107 | [ASPEED_DEV_ETH2] = 3, | |
a3888d75 | 108 | [ASPEED_DEV_HACE] = 4, |
347df6f8 EH |
109 | [ASPEED_DEV_ETH3] = 32, |
110 | [ASPEED_DEV_ETH4] = 33, | |
c59f781e | 111 | [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ |
d9e9cd59 | 112 | [ASPEED_DEV_DP] = 62, |
3222165d | 113 | [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ |
f25c0ae1 CLG |
114 | }; |
115 | ||
116 | static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) | |
117 | { | |
118 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
119 | ||
120 | return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); | |
121 | } | |
122 | ||
123 | static void aspeed_soc_ast2600_init(Object *obj) | |
124 | { | |
125 | AspeedSoCState *s = ASPEED_SOC(obj); | |
126 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
127 | int i; | |
128 | char socname[8]; | |
129 | char typename[64]; | |
130 | ||
131 | if (sscanf(sc->name, "%7s", socname) != 1) { | |
132 | g_assert_not_reached(); | |
133 | } | |
134 | ||
135 | for (i = 0; i < sc->num_cpus; i++) { | |
9fc7fc4d | 136 | object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); |
f25c0ae1 CLG |
137 | } |
138 | ||
139 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); | |
db873cc5 | 140 | object_initialize_child(obj, "scu", &s->scu, typename); |
f25c0ae1 CLG |
141 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", |
142 | sc->silicon_rev); | |
143 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), | |
d2623129 | 144 | "hw-strap1"); |
f25c0ae1 | 145 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), |
d2623129 | 146 | "hw-strap2"); |
f25c0ae1 | 147 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
d2623129 | 148 | "hw-prot-key"); |
f25c0ae1 | 149 | |
db873cc5 MA |
150 | object_initialize_child(obj, "a7mpcore", &s->a7mpcore, |
151 | TYPE_A15MPCORE_PRIV); | |
f25c0ae1 | 152 | |
db873cc5 | 153 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); |
f25c0ae1 CLG |
154 | |
155 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); | |
db873cc5 | 156 | object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); |
f25c0ae1 | 157 | |
199fd623 AJ |
158 | snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); |
159 | object_initialize_child(obj, "adc", &s->adc, typename); | |
160 | ||
f25c0ae1 | 161 | snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); |
db873cc5 | 162 | object_initialize_child(obj, "i2c", &s->i2c, typename); |
f25c0ae1 CLG |
163 | |
164 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); | |
db873cc5 | 165 | object_initialize_child(obj, "fmc", &s->fmc, typename); |
d2623129 | 166 | object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); |
f25c0ae1 CLG |
167 | |
168 | for (i = 0; i < sc->spis_num; i++) { | |
169 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); | |
db873cc5 | 170 | object_initialize_child(obj, "spi[*]", &s->spi[i], typename); |
f25c0ae1 CLG |
171 | } |
172 | ||
917940ce | 173 | for (i = 0; i < sc->ehcis_num; i++) { |
db873cc5 MA |
174 | object_initialize_child(obj, "ehci[*]", &s->ehci[i], |
175 | TYPE_PLATFORM_EHCI); | |
917940ce GR |
176 | } |
177 | ||
f25c0ae1 | 178 | snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); |
db873cc5 | 179 | object_initialize_child(obj, "sdmc", &s->sdmc, typename); |
f25c0ae1 | 180 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
d2623129 | 181 | "ram-size"); |
f25c0ae1 | 182 | object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), |
d2623129 | 183 | "max-ram-size"); |
f25c0ae1 CLG |
184 | |
185 | for (i = 0; i < sc->wdts_num; i++) { | |
186 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); | |
db873cc5 | 187 | object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); |
f25c0ae1 CLG |
188 | } |
189 | ||
d300db02 | 190 | for (i = 0; i < sc->macs_num; i++) { |
db873cc5 MA |
191 | object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], |
192 | TYPE_FTGMAC100); | |
289251b0 | 193 | |
db873cc5 | 194 | object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); |
f25c0ae1 CLG |
195 | } |
196 | ||
8efbee28 CLG |
197 | snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); |
198 | object_initialize_child(obj, "xdma", &s->xdma, typename); | |
f25c0ae1 CLG |
199 | |
200 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); | |
db873cc5 | 201 | object_initialize_child(obj, "gpio", &s->gpio, typename); |
f25c0ae1 CLG |
202 | |
203 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); | |
db873cc5 | 204 | object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); |
f25c0ae1 | 205 | |
db873cc5 MA |
206 | object_initialize_child(obj, "sd-controller", &s->sdhci, |
207 | TYPE_ASPEED_SDHCI); | |
f25c0ae1 | 208 | |
5325cc34 | 209 | object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); |
0e2c24c6 | 210 | |
f25c0ae1 CLG |
211 | /* Init sd card slot class here so that they're under the correct parent */ |
212 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | |
7089e0cc MA |
213 | object_initialize_child(obj, "sd-controller.sdhci[*]", |
214 | &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); | |
f25c0ae1 | 215 | } |
a29e3e12 | 216 | |
db873cc5 MA |
217 | object_initialize_child(obj, "emmc-controller", &s->emmc, |
218 | TYPE_ASPEED_SDHCI); | |
a29e3e12 | 219 | |
5325cc34 | 220 | object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); |
a29e3e12 | 221 | |
7089e0cc MA |
222 | object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], |
223 | TYPE_SYSBUS_SDHCI); | |
2ecf1726 CLG |
224 | |
225 | object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); | |
a3888d75 JS |
226 | |
227 | snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); | |
228 | object_initialize_child(obj, "hace", &s->hace, typename); | |
3222165d TL |
229 | |
230 | object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); | |
e1acf581 JS |
231 | |
232 | object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); | |
f25c0ae1 CLG |
233 | } |
234 | ||
235 | /* | |
236 | * ASPEED ast2600 has 0xf as cluster ID | |
237 | * | |
932a8d1f | 238 | * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register |
f25c0ae1 CLG |
239 | */ |
240 | static uint64_t aspeed_calc_affinity(int cpu) | |
241 | { | |
242 | return (0xf << ARM_AFF1_SHIFT) | cpu; | |
243 | } | |
244 | ||
245 | static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | |
246 | { | |
247 | int i; | |
248 | AspeedSoCState *s = ASPEED_SOC(dev); | |
249 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
123327d1 | 250 | Error *err = NULL; |
f25c0ae1 CLG |
251 | qemu_irq irq; |
252 | ||
253 | /* IO space */ | |
347df6f8 | 254 | create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM], |
f25c0ae1 CLG |
255 | ASPEED_SOC_IOMEM_SIZE); |
256 | ||
514bcf6f | 257 | /* Video engine stub */ |
347df6f8 | 258 | create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], |
514bcf6f JS |
259 | 0x1000); |
260 | ||
f25c0ae1 | 261 | /* CPU */ |
b7f1a0cb | 262 | for (i = 0; i < sc->num_cpus; i++) { |
b7f1a0cb | 263 | if (sc->num_cpus > 1) { |
5325cc34 MA |
264 | object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", |
265 | ASPEED_A7MPCORE_ADDR, &error_abort); | |
f25c0ae1 | 266 | } |
5325cc34 MA |
267 | object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", |
268 | aspeed_calc_affinity(i), &error_abort); | |
f25c0ae1 | 269 | |
5325cc34 | 270 | object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, |
058d0955 AJ |
271 | &error_abort); |
272 | ||
668f62ec | 273 | if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { |
f25c0ae1 CLG |
274 | return; |
275 | } | |
276 | } | |
277 | ||
278 | /* A7MPCORE */ | |
5325cc34 | 279 | object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, |
f25c0ae1 | 280 | &error_abort); |
5325cc34 | 281 | object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", |
957ad79f | 282 | ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), |
5325cc34 | 283 | &error_abort); |
f25c0ae1 | 284 | |
db873cc5 | 285 | sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); |
f25c0ae1 CLG |
286 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); |
287 | ||
b7f1a0cb | 288 | for (i = 0; i < sc->num_cpus; i++) { |
f25c0ae1 CLG |
289 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); |
290 | DeviceState *d = DEVICE(qemu_get_cpu(i)); | |
291 | ||
292 | irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); | |
293 | sysbus_connect_irq(sbd, i, irq); | |
294 | irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); | |
b7f1a0cb | 295 | sysbus_connect_irq(sbd, i + sc->num_cpus, irq); |
f25c0ae1 | 296 | irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); |
b7f1a0cb | 297 | sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); |
f25c0ae1 | 298 | irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); |
b7f1a0cb | 299 | sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); |
f25c0ae1 CLG |
300 | } |
301 | ||
302 | /* SRAM */ | |
303 | memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", | |
304 | sc->sram_size, &err); | |
305 | if (err) { | |
306 | error_propagate(errp, err); | |
307 | return; | |
308 | } | |
309 | memory_region_add_subregion(get_system_memory(), | |
347df6f8 | 310 | sc->memmap[ASPEED_DEV_SRAM], &s->sram); |
f25c0ae1 | 311 | |
d9e9cd59 TL |
312 | /* DPMCU */ |
313 | create_unimplemented_device("aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], | |
314 | ASPEED_SOC_DPMCU_SIZE); | |
315 | ||
f25c0ae1 | 316 | /* SCU */ |
668f62ec | 317 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { |
f25c0ae1 CLG |
318 | return; |
319 | } | |
347df6f8 | 320 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); |
f25c0ae1 CLG |
321 | |
322 | /* RTC */ | |
668f62ec | 323 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { |
f25c0ae1 CLG |
324 | return; |
325 | } | |
347df6f8 | 326 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); |
f25c0ae1 | 327 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, |
347df6f8 | 328 | aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); |
f25c0ae1 CLG |
329 | |
330 | /* Timer */ | |
5325cc34 MA |
331 | object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), |
332 | &error_abort); | |
668f62ec | 333 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { |
f25c0ae1 CLG |
334 | return; |
335 | } | |
336 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, | |
347df6f8 | 337 | sc->memmap[ASPEED_DEV_TIMER1]); |
f25c0ae1 | 338 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { |
347df6f8 | 339 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); |
f25c0ae1 CLG |
340 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); |
341 | } | |
342 | ||
199fd623 AJ |
343 | /* ADC */ |
344 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { | |
345 | return; | |
346 | } | |
347 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); | |
348 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, | |
349 | aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); | |
350 | ||
5d63d0c7 PD |
351 | /* UART - attach an 8250 to the IO space as our UART */ |
352 | serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, | |
353 | aspeed_soc_get_irq(s, s->uart_default), 38400, | |
354 | serial_hd(0), DEVICE_LITTLE_ENDIAN); | |
f25c0ae1 CLG |
355 | |
356 | /* I2C */ | |
5325cc34 | 357 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), |
c24d9716 | 358 | &error_abort); |
668f62ec | 359 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { |
f25c0ae1 CLG |
360 | return; |
361 | } | |
347df6f8 | 362 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); |
f25c0ae1 CLG |
363 | for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { |
364 | qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
347df6f8 | 365 | sc->irqmap[ASPEED_DEV_I2C] + i); |
60261038 CLG |
366 | /* The AST2600 I2C controller has one IRQ per bus. */ |
367 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); | |
f25c0ae1 CLG |
368 | } |
369 | ||
370 | /* FMC, The number of CS is set at the board level */ | |
5325cc34 | 371 | object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), |
c24d9716 | 372 | &error_abort); |
668f62ec | 373 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { |
f25c0ae1 CLG |
374 | return; |
375 | } | |
347df6f8 | 376 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); |
f25c0ae1 | 377 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, |
30b6852c | 378 | ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); |
f25c0ae1 | 379 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, |
347df6f8 | 380 | aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); |
f25c0ae1 CLG |
381 | |
382 | /* SPI */ | |
383 | for (i = 0; i < sc->spis_num; i++) { | |
5325cc34 MA |
384 | object_property_set_link(OBJECT(&s->spi[i]), "dram", |
385 | OBJECT(s->dram_mr), &error_abort); | |
386 | object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort); | |
668f62ec | 387 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
f25c0ae1 CLG |
388 | return; |
389 | } | |
390 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, | |
347df6f8 | 391 | sc->memmap[ASPEED_DEV_SPI1 + i]); |
f25c0ae1 | 392 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, |
30b6852c | 393 | ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); |
f25c0ae1 CLG |
394 | } |
395 | ||
917940ce GR |
396 | /* EHCI */ |
397 | for (i = 0; i < sc->ehcis_num; i++) { | |
668f62ec | 398 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { |
917940ce GR |
399 | return; |
400 | } | |
401 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, | |
347df6f8 | 402 | sc->memmap[ASPEED_DEV_EHCI1 + i]); |
917940ce | 403 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, |
347df6f8 | 404 | aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); |
917940ce GR |
405 | } |
406 | ||
f25c0ae1 | 407 | /* SDMC - SDRAM Memory Controller */ |
668f62ec | 408 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { |
f25c0ae1 CLG |
409 | return; |
410 | } | |
347df6f8 | 411 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); |
f25c0ae1 CLG |
412 | |
413 | /* Watch dog */ | |
414 | for (i = 0; i < sc->wdts_num; i++) { | |
415 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); | |
416 | ||
5325cc34 MA |
417 | object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), |
418 | &error_abort); | |
668f62ec | 419 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { |
f25c0ae1 CLG |
420 | return; |
421 | } | |
422 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | |
347df6f8 | 423 | sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); |
f25c0ae1 CLG |
424 | } |
425 | ||
426 | /* Net */ | |
d3bad7e7 | 427 | for (i = 0; i < sc->macs_num; i++) { |
5325cc34 | 428 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, |
2255f6b7 | 429 | &error_abort); |
668f62ec | 430 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { |
123327d1 | 431 | return; |
f25c0ae1 CLG |
432 | } |
433 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | |
347df6f8 | 434 | sc->memmap[ASPEED_DEV_ETH1 + i]); |
f25c0ae1 | 435 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
347df6f8 | 436 | aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); |
289251b0 | 437 | |
5325cc34 MA |
438 | object_property_set_link(OBJECT(&s->mii[i]), "nic", |
439 | OBJECT(&s->ftgmac100[i]), &error_abort); | |
668f62ec | 440 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { |
289251b0 CLG |
441 | return; |
442 | } | |
443 | ||
444 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, | |
347df6f8 | 445 | sc->memmap[ASPEED_DEV_MII1 + i]); |
f25c0ae1 CLG |
446 | } |
447 | ||
448 | /* XDMA */ | |
668f62ec | 449 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { |
f25c0ae1 CLG |
450 | return; |
451 | } | |
452 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, | |
347df6f8 | 453 | sc->memmap[ASPEED_DEV_XDMA]); |
f25c0ae1 | 454 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, |
347df6f8 | 455 | aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); |
f25c0ae1 CLG |
456 | |
457 | /* GPIO */ | |
668f62ec | 458 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
f25c0ae1 CLG |
459 | return; |
460 | } | |
347df6f8 | 461 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); |
f25c0ae1 | 462 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, |
347df6f8 | 463 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); |
f25c0ae1 | 464 | |
668f62ec | 465 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { |
f25c0ae1 CLG |
466 | return; |
467 | } | |
468 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, | |
347df6f8 | 469 | sc->memmap[ASPEED_DEV_GPIO_1_8V]); |
f25c0ae1 | 470 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, |
347df6f8 | 471 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); |
f25c0ae1 CLG |
472 | |
473 | /* SDHCI */ | |
668f62ec | 474 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { |
f25c0ae1 CLG |
475 | return; |
476 | } | |
477 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | |
347df6f8 | 478 | sc->memmap[ASPEED_DEV_SDHCI]); |
f25c0ae1 | 479 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, |
347df6f8 | 480 | aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); |
a29e3e12 AJ |
481 | |
482 | /* eMMC */ | |
668f62ec | 483 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { |
a29e3e12 AJ |
484 | return; |
485 | } | |
347df6f8 | 486 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); |
a29e3e12 | 487 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, |
347df6f8 | 488 | aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); |
2ecf1726 CLG |
489 | |
490 | /* LPC */ | |
491 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { | |
492 | return; | |
493 | } | |
494 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); | |
c59f781e AJ |
495 | |
496 | /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ | |
2ecf1726 CLG |
497 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, |
498 | aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); | |
c59f781e AJ |
499 | |
500 | /* | |
501 | * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. | |
502 | * | |
503 | * LPC subdevice IRQ sources are offset from 1 because the LPC model caters | |
504 | * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ | |
505 | * shared across the subdevices, and the shared IRQ output to the VIC is at | |
506 | * offset 0. | |
507 | */ | |
508 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, | |
509 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
510 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); | |
511 | ||
512 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, | |
513 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
514 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); | |
515 | ||
516 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, | |
517 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
518 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); | |
519 | ||
520 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, | |
521 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
522 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); | |
a3888d75 JS |
523 | |
524 | /* HACE */ | |
525 | object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), | |
526 | &error_abort); | |
527 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { | |
528 | return; | |
529 | } | |
530 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); | |
531 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, | |
532 | aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); | |
3222165d TL |
533 | |
534 | /* I3C */ | |
535 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { | |
536 | return; | |
537 | } | |
538 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); | |
539 | for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { | |
540 | qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
541 | sc->irqmap[ASPEED_DEV_I3C] + i); | |
542 | /* The AST2600 I3C controller has one IRQ per bus. */ | |
543 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); | |
544 | } | |
e1acf581 JS |
545 | |
546 | /* Secure Boot Controller */ | |
547 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { | |
548 | return; | |
549 | } | |
550 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); | |
f25c0ae1 CLG |
551 | } |
552 | ||
553 | static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) | |
554 | { | |
555 | DeviceClass *dc = DEVICE_CLASS(oc); | |
556 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | |
557 | ||
558 | dc->realize = aspeed_soc_ast2600_realize; | |
559 | ||
c5811bb3 | 560 | sc->name = "ast2600-a3"; |
f25c0ae1 | 561 | sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); |
c5811bb3 | 562 | sc->silicon_rev = AST2600_A3_SILICON_REV; |
e01b4d5b | 563 | sc->sram_size = 0x16400; |
f25c0ae1 | 564 | sc->spis_num = 2; |
917940ce | 565 | sc->ehcis_num = 2; |
f25c0ae1 | 566 | sc->wdts_num = 4; |
d300db02 | 567 | sc->macs_num = 4; |
f25c0ae1 CLG |
568 | sc->irqmap = aspeed_soc_ast2600_irqmap; |
569 | sc->memmap = aspeed_soc_ast2600_memmap; | |
570 | sc->num_cpus = 2; | |
571 | } | |
572 | ||
573 | static const TypeInfo aspeed_soc_ast2600_type_info = { | |
c5811bb3 | 574 | .name = "ast2600-a3", |
f25c0ae1 CLG |
575 | .parent = TYPE_ASPEED_SOC, |
576 | .instance_size = sizeof(AspeedSoCState), | |
577 | .instance_init = aspeed_soc_ast2600_init, | |
578 | .class_init = aspeed_soc_ast2600_class_init, | |
579 | .class_size = sizeof(AspeedSoCClass), | |
580 | }; | |
581 | ||
582 | static void aspeed_soc_register_types(void) | |
583 | { | |
584 | type_register_static(&aspeed_soc_ast2600_type_info); | |
585 | }; | |
586 | ||
587 | type_init(aspeed_soc_register_types) |