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Commit | Line | Data |
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3475187d | 1 | /* |
c7ba218d | 2 | * QEMU Sun4u/Sun4v System Emulator |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
26 | #include "pc.h" | |
27 | #include "nvram.h" | |
28 | #include "fdc.h" | |
29 | #include "net.h" | |
30 | #include "qemu-timer.h" | |
31 | #include "sysemu.h" | |
32 | #include "boards.h" | |
d2c63fc1 | 33 | #include "firmware_abi.h" |
3cce6243 | 34 | #include "fw_cfg.h" |
1baffa46 | 35 | #include "sysbus.h" |
3475187d | 36 | |
9d926598 BS |
37 | //#define DEBUG_IRQ |
38 | ||
39 | #ifdef DEBUG_IRQ | |
001faf32 BS |
40 | #define DPRINTF(fmt, ...) \ |
41 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
9d926598 | 42 | #else |
001faf32 | 43 | #define DPRINTF(fmt, ...) |
9d926598 BS |
44 | #endif |
45 | ||
83469015 FB |
46 | #define KERNEL_LOAD_ADDR 0x00404000 |
47 | #define CMDLINE_ADDR 0x003ff000 | |
48 | #define INITRD_LOAD_ADDR 0x00300000 | |
ac2e9d66 | 49 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
f930d07e | 50 | #define PROM_VADDR 0x000ffd00000ULL |
83469015 | 51 | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
f930d07e BS |
52 | #define APB_MEM_BASE 0x1ff00000000ULL |
53 | #define VGA_BASE (APB_MEM_BASE + 0x400000ULL) | |
54 | #define PROM_FILENAME "openbios-sparc64" | |
83469015 | 55 | #define NVRAM_SIZE 0x2000 |
e4bcb14c | 56 | #define MAX_IDE_BUS 2 |
3cce6243 | 57 | #define BIOS_CFG_IOPORT 0x510 |
3475187d | 58 | |
9d926598 BS |
59 | #define MAX_PILS 16 |
60 | ||
8fa211e8 BS |
61 | #define TICK_INT_DIS 0x8000000000000000ULL |
62 | #define TICK_MAX 0x7fffffffffffffffULL | |
63 | ||
c7ba218d BS |
64 | struct hwdef { |
65 | const char * const default_cpu_model; | |
905fdcb5 | 66 | uint16_t machine_id; |
e87231d4 BS |
67 | uint64_t prom_addr; |
68 | uint64_t console_serial_base; | |
c7ba218d BS |
69 | }; |
70 | ||
3475187d FB |
71 | int DMA_get_channel_mode (int nchan) |
72 | { | |
73 | return 0; | |
74 | } | |
75 | int DMA_read_memory (int nchan, void *buf, int pos, int size) | |
76 | { | |
77 | return 0; | |
78 | } | |
79 | int DMA_write_memory (int nchan, void *buf, int pos, int size) | |
80 | { | |
81 | return 0; | |
82 | } | |
83 | void DMA_hold_DREQ (int nchan) {} | |
84 | void DMA_release_DREQ (int nchan) {} | |
85 | void DMA_schedule(int nchan) {} | |
3475187d FB |
86 | void DMA_init (int high_page_enable) {} |
87 | void DMA_register_channel (int nchan, | |
88 | DMA_transfer_handler transfer_handler, | |
89 | void *opaque) | |
90 | { | |
91 | } | |
92 | ||
513f789f | 93 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
81864572 | 94 | { |
513f789f | 95 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
96 | return 0; |
97 | } | |
98 | ||
d2c63fc1 | 99 | static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, |
e7fb1406 | 100 | const char *arch, |
77f193da BS |
101 | ram_addr_t RAM_size, |
102 | const char *boot_devices, | |
d2c63fc1 BS |
103 | uint32_t kernel_image, uint32_t kernel_size, |
104 | const char *cmdline, | |
105 | uint32_t initrd_image, uint32_t initrd_size, | |
106 | uint32_t NVRAM_image, | |
0d31cb99 BS |
107 | int width, int height, int depth, |
108 | const uint8_t *macaddr) | |
83469015 | 109 | { |
66508601 BS |
110 | unsigned int i; |
111 | uint32_t start, end; | |
d2c63fc1 | 112 | uint8_t image[0x1ff0]; |
d2c63fc1 BS |
113 | struct OpenBIOS_nvpart_v1 *part_header; |
114 | ||
115 | memset(image, '\0', sizeof(image)); | |
116 | ||
513f789f | 117 | start = 0; |
83469015 | 118 | |
66508601 BS |
119 | // OpenBIOS nvram variables |
120 | // Variable partition | |
d2c63fc1 BS |
121 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
122 | part_header->signature = OPENBIOS_PART_SYSTEM; | |
363a37d5 | 123 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
66508601 | 124 | |
d2c63fc1 | 125 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
66508601 | 126 | for (i = 0; i < nb_prom_envs; i++) |
d2c63fc1 BS |
127 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
128 | ||
129 | // End marker | |
130 | image[end++] = '\0'; | |
66508601 | 131 | |
66508601 | 132 | end = start + ((end - start + 15) & ~15); |
d2c63fc1 | 133 | OpenBIOS_finish_partition(part_header, end - start); |
66508601 BS |
134 | |
135 | // free partition | |
136 | start = end; | |
d2c63fc1 BS |
137 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
138 | part_header->signature = OPENBIOS_PART_FREE; | |
363a37d5 | 139 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
66508601 BS |
140 | |
141 | end = 0x1fd0; | |
d2c63fc1 BS |
142 | OpenBIOS_finish_partition(part_header, end - start); |
143 | ||
0d31cb99 BS |
144 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
145 | ||
d2c63fc1 BS |
146 | for (i = 0; i < sizeof(image); i++) |
147 | m48t59_write(nvram, i, image[i]); | |
66508601 | 148 | |
83469015 | 149 | return 0; |
3475187d FB |
150 | } |
151 | ||
b4950060 | 152 | void pic_info(Monitor *mon) |
3475187d FB |
153 | { |
154 | } | |
155 | ||
b4950060 | 156 | void irq_info(Monitor *mon) |
3475187d FB |
157 | { |
158 | } | |
159 | ||
9d926598 BS |
160 | void cpu_check_irqs(CPUState *env) |
161 | { | |
162 | uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) | | |
163 | ((env->softint & SOFTINT_TIMER) << 14); | |
164 | ||
165 | if (pil && (env->interrupt_index == 0 || | |
166 | (env->interrupt_index & ~15) == TT_EXTINT)) { | |
167 | unsigned int i; | |
168 | ||
169 | for (i = 15; i > 0; i--) { | |
170 | if (pil & (1 << i)) { | |
171 | int old_interrupt = env->interrupt_index; | |
172 | ||
173 | env->interrupt_index = TT_EXTINT | i; | |
174 | if (old_interrupt != env->interrupt_index) { | |
175 | DPRINTF("Set CPU IRQ %d\n", i); | |
176 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
177 | } | |
178 | break; | |
179 | } | |
180 | } | |
181 | } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) { | |
182 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); | |
183 | env->interrupt_index = 0; | |
184 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
185 | } | |
186 | } | |
187 | ||
188 | static void cpu_set_irq(void *opaque, int irq, int level) | |
189 | { | |
190 | CPUState *env = opaque; | |
191 | ||
192 | if (level) { | |
193 | DPRINTF("Raise CPU IRQ %d\n", irq); | |
194 | env->halted = 0; | |
195 | env->pil_in |= 1 << irq; | |
196 | cpu_check_irqs(env); | |
197 | } else { | |
198 | DPRINTF("Lower CPU IRQ %d\n", irq); | |
199 | env->pil_in &= ~(1 << irq); | |
200 | cpu_check_irqs(env); | |
201 | } | |
202 | } | |
203 | ||
83469015 | 204 | void qemu_system_powerdown(void) |
3475187d FB |
205 | { |
206 | } | |
207 | ||
e87231d4 BS |
208 | typedef struct ResetData { |
209 | CPUState *env; | |
210 | uint64_t reset_addr; | |
211 | } ResetData; | |
212 | ||
c68ea704 FB |
213 | static void main_cpu_reset(void *opaque) |
214 | { | |
e87231d4 BS |
215 | ResetData *s = (ResetData *)opaque; |
216 | CPUState *env = s->env; | |
20c9f095 | 217 | |
c68ea704 | 218 | cpu_reset(env); |
8fa211e8 BS |
219 | env->tick_cmpr = TICK_INT_DIS | 0; |
220 | ptimer_set_limit(env->tick, TICK_MAX, 1); | |
2f43e00e | 221 | ptimer_run(env->tick, 1); |
8fa211e8 BS |
222 | env->stick_cmpr = TICK_INT_DIS | 0; |
223 | ptimer_set_limit(env->stick, TICK_MAX, 1); | |
2f43e00e | 224 | ptimer_run(env->stick, 1); |
8fa211e8 BS |
225 | env->hstick_cmpr = TICK_INT_DIS | 0; |
226 | ptimer_set_limit(env->hstick, TICK_MAX, 1); | |
2f43e00e | 227 | ptimer_run(env->hstick, 1); |
e87231d4 BS |
228 | env->gregs[1] = 0; // Memory start |
229 | env->gregs[2] = ram_size; // Memory size | |
230 | env->gregs[3] = 0; // Machine description XXX | |
231 | env->pc = s->reset_addr; | |
232 | env->npc = env->pc + 4; | |
20c9f095 BS |
233 | } |
234 | ||
22548760 | 235 | static void tick_irq(void *opaque) |
20c9f095 BS |
236 | { |
237 | CPUState *env = opaque; | |
238 | ||
8fa211e8 BS |
239 | if (!(env->tick_cmpr & TICK_INT_DIS)) { |
240 | env->softint |= SOFTINT_TIMER; | |
241 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
242 | } | |
20c9f095 BS |
243 | } |
244 | ||
22548760 | 245 | static void stick_irq(void *opaque) |
20c9f095 BS |
246 | { |
247 | CPUState *env = opaque; | |
248 | ||
8fa211e8 BS |
249 | if (!(env->stick_cmpr & TICK_INT_DIS)) { |
250 | env->softint |= SOFTINT_STIMER; | |
251 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
252 | } | |
20c9f095 BS |
253 | } |
254 | ||
22548760 | 255 | static void hstick_irq(void *opaque) |
20c9f095 BS |
256 | { |
257 | CPUState *env = opaque; | |
258 | ||
8fa211e8 BS |
259 | if (!(env->hstick_cmpr & TICK_INT_DIS)) { |
260 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
261 | } | |
c68ea704 FB |
262 | } |
263 | ||
f4b1a842 BS |
264 | void cpu_tick_set_count(void *opaque, uint64_t count) |
265 | { | |
266 | ptimer_set_count(opaque, -count); | |
267 | } | |
268 | ||
269 | uint64_t cpu_tick_get_count(void *opaque) | |
270 | { | |
271 | return -ptimer_get_count(opaque); | |
272 | } | |
273 | ||
274 | void cpu_tick_set_limit(void *opaque, uint64_t limit) | |
275 | { | |
276 | ptimer_set_limit(opaque, -limit, 0); | |
277 | } | |
278 | ||
83469015 FB |
279 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
280 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
281 | static const int ide_irq[2] = { 14, 15 }; | |
3475187d | 282 | |
83469015 FB |
283 | static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
284 | static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; | |
285 | ||
286 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; | |
287 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
288 | ||
289 | static fdctrl_t *floppy_controller; | |
3475187d | 290 | |
c190ea07 BS |
291 | static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num, |
292 | uint32_t addr, uint32_t size, int type) | |
293 | { | |
294 | DPRINTF("Mapping region %d registers at %08x\n", region_num, addr); | |
295 | switch (region_num) { | |
296 | case 0: | |
297 | isa_mmio_init(addr, 0x1000000); | |
298 | break; | |
299 | case 1: | |
300 | isa_mmio_init(addr, 0x800000); | |
301 | break; | |
302 | } | |
303 | } | |
304 | ||
305 | /* EBUS (Eight bit bus) bridge */ | |
306 | static void | |
307 | pci_ebus_init(PCIBus *bus, int devfn) | |
308 | { | |
53e3c4f9 BS |
309 | pci_create_simple(bus, devfn, "ebus"); |
310 | } | |
c190ea07 | 311 | |
53e3c4f9 BS |
312 | static void |
313 | pci_ebus_init1(PCIDevice *s) | |
314 | { | |
deb54399 AL |
315 | pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN); |
316 | pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS); | |
c190ea07 BS |
317 | s->config[0x04] = 0x06; // command = bus master, pci mem |
318 | s->config[0x05] = 0x00; | |
319 | s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
320 | s->config[0x07] = 0x03; // status = medium devsel | |
321 | s->config[0x08] = 0x01; // revision | |
322 | s->config[0x09] = 0x00; // programming i/f | |
173a543b | 323 | pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER); |
c190ea07 | 324 | s->config[0x0D] = 0x0a; // latency_timer |
6407f373 | 325 | s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type |
c190ea07 | 326 | |
28c2c264 | 327 | pci_register_bar(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM, |
c190ea07 | 328 | ebus_mmio_mapfunc); |
28c2c264 | 329 | pci_register_bar(s, 1, 0x800000, PCI_ADDRESS_SPACE_MEM, |
c190ea07 BS |
330 | ebus_mmio_mapfunc); |
331 | } | |
332 | ||
53e3c4f9 BS |
333 | static PCIDeviceInfo ebus_info = { |
334 | .qdev.name = "ebus", | |
335 | .qdev.size = sizeof(PCIDevice), | |
336 | .init = pci_ebus_init1, | |
337 | }; | |
338 | ||
339 | static void pci_ebus_register(void) | |
340 | { | |
341 | pci_qdev_register(&ebus_info); | |
342 | } | |
343 | ||
344 | device_init(pci_ebus_register); | |
345 | ||
1baffa46 BS |
346 | /* Boot PROM (OpenBIOS) */ |
347 | static void prom_init(target_phys_addr_t addr, const char *bios_name) | |
348 | { | |
349 | DeviceState *dev; | |
350 | SysBusDevice *s; | |
351 | char *filename; | |
352 | int ret; | |
353 | ||
354 | dev = qdev_create(NULL, "openprom"); | |
355 | qdev_init(dev); | |
356 | s = sysbus_from_qdev(dev); | |
357 | ||
358 | sysbus_mmio_map(s, 0, addr); | |
359 | ||
360 | /* load boot prom */ | |
361 | if (bios_name == NULL) { | |
362 | bios_name = PROM_FILENAME; | |
363 | } | |
364 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
365 | if (filename) { | |
366 | ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL); | |
367 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
368 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
369 | } | |
370 | qemu_free(filename); | |
371 | } else { | |
372 | ret = -1; | |
373 | } | |
374 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
375 | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); | |
376 | exit(1); | |
377 | } | |
378 | } | |
379 | ||
380 | static void prom_init1(SysBusDevice *dev) | |
381 | { | |
382 | ram_addr_t prom_offset; | |
383 | ||
384 | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); | |
385 | sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); | |
386 | } | |
387 | ||
388 | static SysBusDeviceInfo prom_info = { | |
389 | .init = prom_init1, | |
390 | .qdev.name = "openprom", | |
391 | .qdev.size = sizeof(SysBusDevice), | |
392 | .qdev.props = (Property[]) { | |
393 | {/* end of property list */} | |
394 | } | |
395 | }; | |
396 | ||
397 | static void prom_register_devices(void) | |
398 | { | |
399 | sysbus_register_withprop(&prom_info); | |
400 | } | |
401 | ||
402 | device_init(prom_register_devices); | |
403 | ||
bda42033 BS |
404 | |
405 | typedef struct RamDevice | |
406 | { | |
407 | SysBusDevice busdev; | |
408 | uint32_t size; // XXX | |
409 | } RamDevice; | |
410 | ||
411 | /* System RAM */ | |
412 | static void ram_init1(SysBusDevice *dev) | |
413 | { | |
414 | ram_addr_t RAM_size, ram_offset; | |
415 | RamDevice *d = FROM_SYSBUS(RamDevice, dev); | |
416 | ||
417 | RAM_size = d->size; | |
418 | ||
419 | ram_offset = qemu_ram_alloc(RAM_size); | |
420 | sysbus_init_mmio(dev, RAM_size, ram_offset); | |
421 | } | |
422 | ||
423 | static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size) | |
424 | { | |
425 | DeviceState *dev; | |
426 | SysBusDevice *s; | |
427 | RamDevice *d; | |
428 | ||
429 | /* allocate RAM */ | |
430 | dev = qdev_create(NULL, "memory"); | |
431 | s = sysbus_from_qdev(dev); | |
432 | ||
433 | d = FROM_SYSBUS(RamDevice, s); | |
434 | d->size = RAM_size; | |
435 | qdev_init(dev); | |
436 | ||
437 | sysbus_mmio_map(s, 0, addr); | |
438 | } | |
439 | ||
440 | static SysBusDeviceInfo ram_info = { | |
441 | .init = ram_init1, | |
442 | .qdev.name = "memory", | |
443 | .qdev.size = sizeof(RamDevice), | |
444 | .qdev.props = (Property[]) { | |
445 | { | |
446 | .name = "size", | |
447 | .info = &qdev_prop_uint32, | |
448 | .offset = offsetof(RamDevice, size), | |
449 | }, | |
450 | {/* end of property list */} | |
451 | } | |
452 | }; | |
453 | ||
454 | static void ram_register_devices(void) | |
455 | { | |
456 | sysbus_register_withprop(&ram_info); | |
457 | } | |
458 | ||
459 | device_init(ram_register_devices); | |
460 | ||
fbe1b595 | 461 | static void sun4uv_init(ram_addr_t RAM_size, |
3023f332 | 462 | const char *boot_devices, |
c7ba218d BS |
463 | const char *kernel_filename, const char *kernel_cmdline, |
464 | const char *initrd_filename, const char *cpu_model, | |
465 | const struct hwdef *hwdef) | |
3475187d | 466 | { |
c68ea704 | 467 | CPUState *env; |
83469015 | 468 | m48t59_t *nvram; |
1baffa46 | 469 | int linux_boot; |
3475187d | 470 | unsigned int i; |
5c6602c5 | 471 | long initrd_size, kernel_size; |
c190ea07 | 472 | PCIBus *pci_bus, *pci_bus2, *pci_bus3; |
20c9f095 | 473 | QEMUBH *bh; |
f19e918d | 474 | qemu_irq *irq; |
22548760 | 475 | int drive_index; |
e4bcb14c TS |
476 | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
477 | BlockDriverState *fd[MAX_FD]; | |
3cce6243 | 478 | void *fw_cfg; |
e87231d4 | 479 | ResetData *reset_info; |
3475187d FB |
480 | |
481 | linux_boot = (kernel_filename != NULL); | |
482 | ||
62724a37 | 483 | /* init CPUs */ |
c7ba218d BS |
484 | if (!cpu_model) |
485 | cpu_model = hwdef->default_cpu_model; | |
486 | ||
aaed909a FB |
487 | env = cpu_init(cpu_model); |
488 | if (!env) { | |
62724a37 BS |
489 | fprintf(stderr, "Unable to find Sparc CPU definition\n"); |
490 | exit(1); | |
491 | } | |
20c9f095 BS |
492 | bh = qemu_bh_new(tick_irq, env); |
493 | env->tick = ptimer_init(bh); | |
494 | ptimer_set_period(env->tick, 1ULL); | |
495 | ||
496 | bh = qemu_bh_new(stick_irq, env); | |
497 | env->stick = ptimer_init(bh); | |
498 | ptimer_set_period(env->stick, 1ULL); | |
499 | ||
500 | bh = qemu_bh_new(hstick_irq, env); | |
501 | env->hstick = ptimer_init(bh); | |
502 | ptimer_set_period(env->hstick, 1ULL); | |
e87231d4 BS |
503 | |
504 | reset_info = qemu_mallocz(sizeof(ResetData)); | |
505 | reset_info->env = env; | |
506 | reset_info->reset_addr = hwdef->prom_addr + 0x40ULL; | |
a08d4367 | 507 | qemu_register_reset(main_cpu_reset, reset_info); |
e87231d4 BS |
508 | main_cpu_reset(reset_info); |
509 | // Override warm reset address with cold start address | |
510 | env->pc = hwdef->prom_addr + 0x20ULL; | |
511 | env->npc = env->pc + 4; | |
c68ea704 | 512 | |
bda42033 BS |
513 | /* set up devices */ |
514 | ram_init(0, RAM_size); | |
3475187d | 515 | |
1baffa46 | 516 | prom_init(hwdef->prom_addr, bios_name); |
3475187d FB |
517 | |
518 | kernel_size = 0; | |
83469015 | 519 | initrd_size = 0; |
3475187d | 520 | if (linux_boot) { |
b3783731 | 521 | /* XXX: put correct offset */ |
74287114 | 522 | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); |
3475187d | 523 | if (kernel_size < 0) |
293f78bc BS |
524 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
525 | ram_size - KERNEL_LOAD_ADDR); | |
f930d07e | 526 | if (kernel_size < 0) |
293f78bc BS |
527 | kernel_size = load_image_targphys(kernel_filename, |
528 | KERNEL_LOAD_ADDR, | |
529 | ram_size - KERNEL_LOAD_ADDR); | |
3475187d | 530 | if (kernel_size < 0) { |
5fafdf24 | 531 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
3475187d | 532 | kernel_filename); |
f930d07e | 533 | exit(1); |
3475187d FB |
534 | } |
535 | ||
536 | /* load initrd */ | |
3475187d | 537 | if (initrd_filename) { |
293f78bc BS |
538 | initrd_size = load_image_targphys(initrd_filename, |
539 | INITRD_LOAD_ADDR, | |
540 | ram_size - INITRD_LOAD_ADDR); | |
3475187d | 541 | if (initrd_size < 0) { |
5fafdf24 | 542 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
3475187d FB |
543 | initrd_filename); |
544 | exit(1); | |
545 | } | |
546 | } | |
547 | if (initrd_size > 0) { | |
f930d07e | 548 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
293f78bc BS |
549 | if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
550 | stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
551 | stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size); | |
f930d07e BS |
552 | break; |
553 | } | |
554 | } | |
3475187d FB |
555 | } |
556 | } | |
7d55273f IK |
557 | |
558 | irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); | |
559 | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2, | |
c190ea07 | 560 | &pci_bus3); |
83469015 | 561 | isa_mem_base = VGA_BASE; |
fbe1b595 | 562 | pci_vga_init(pci_bus, 0, 0); |
83469015 | 563 | |
c190ea07 BS |
564 | // XXX Should be pci_bus3 |
565 | pci_ebus_init(pci_bus, -1); | |
566 | ||
e87231d4 BS |
567 | i = 0; |
568 | if (hwdef->console_serial_base) { | |
569 | serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200, | |
570 | serial_hds[i], 1); | |
571 | i++; | |
572 | } | |
573 | for(; i < MAX_SERIAL_PORTS; i++) { | |
83469015 | 574 | if (serial_hds[i]) { |
cbf5c748 BS |
575 | serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200, |
576 | serial_hds[i]); | |
83469015 FB |
577 | } |
578 | } | |
579 | ||
580 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
581 | if (parallel_hds[i]) { | |
77f193da BS |
582 | parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, |
583 | parallel_hds[i]); | |
83469015 FB |
584 | } |
585 | } | |
586 | ||
cb457d76 | 587 | for(i = 0; i < nb_nics; i++) |
6d53bfd1 | 588 | pci_nic_init(&nd_table[i], "ne2k_pci", NULL); |
83469015 | 589 | |
e4bcb14c TS |
590 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
591 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
592 | exit(1); | |
593 | } | |
594 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
22548760 BS |
595 | drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, |
596 | i % MAX_IDE_DEVS); | |
597 | if (drive_index != -1) | |
598 | hd[i] = drives_table[drive_index].bdrv; | |
e4bcb14c TS |
599 | else |
600 | hd[i] = NULL; | |
601 | } | |
602 | ||
3b898dda BS |
603 | pci_cmd646_ide_init(pci_bus, hd, 1); |
604 | ||
d537cf6c PB |
605 | /* FIXME: wire up interrupts. */ |
606 | i8042_init(NULL/*1*/, NULL/*12*/, 0x60); | |
e4bcb14c | 607 | for(i = 0; i < MAX_FD; i++) { |
22548760 BS |
608 | drive_index = drive_get_index(IF_FLOPPY, 0, i); |
609 | if (drive_index != -1) | |
610 | fd[i] = drives_table[drive_index].bdrv; | |
e4bcb14c TS |
611 | else |
612 | fd[i] = NULL; | |
613 | } | |
614 | floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd); | |
d537cf6c | 615 | nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59); |
22548760 | 616 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices, |
0d31cb99 BS |
617 | KERNEL_LOAD_ADDR, kernel_size, |
618 | kernel_cmdline, | |
619 | INITRD_LOAD_ADDR, initrd_size, | |
620 | /* XXX: need an option to load a NVRAM image */ | |
621 | 0, | |
622 | graphic_width, graphic_height, graphic_depth, | |
623 | (uint8_t *)&nd_table[0].macaddr); | |
83469015 | 624 | |
3cce6243 BS |
625 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
626 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
905fdcb5 BS |
627 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
628 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
513f789f BS |
629 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
630 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
631 | if (kernel_cmdline) { | |
632 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); | |
633 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); | |
634 | } else { | |
635 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
636 | } | |
637 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); | |
638 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
639 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]); | |
640 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); | |
3475187d FB |
641 | } |
642 | ||
905fdcb5 BS |
643 | enum { |
644 | sun4u_id = 0, | |
645 | sun4v_id = 64, | |
e87231d4 | 646 | niagara_id, |
905fdcb5 BS |
647 | }; |
648 | ||
c7ba218d BS |
649 | static const struct hwdef hwdefs[] = { |
650 | /* Sun4u generic PC-like machine */ | |
651 | { | |
652 | .default_cpu_model = "TI UltraSparc II", | |
905fdcb5 | 653 | .machine_id = sun4u_id, |
e87231d4 BS |
654 | .prom_addr = 0x1fff0000000ULL, |
655 | .console_serial_base = 0, | |
c7ba218d BS |
656 | }, |
657 | /* Sun4v generic PC-like machine */ | |
658 | { | |
659 | .default_cpu_model = "Sun UltraSparc T1", | |
905fdcb5 | 660 | .machine_id = sun4v_id, |
e87231d4 BS |
661 | .prom_addr = 0x1fff0000000ULL, |
662 | .console_serial_base = 0, | |
663 | }, | |
664 | /* Sun4v generic Niagara machine */ | |
665 | { | |
666 | .default_cpu_model = "Sun UltraSparc T1", | |
667 | .machine_id = niagara_id, | |
668 | .prom_addr = 0xfff0000000ULL, | |
669 | .console_serial_base = 0xfff0c2c000ULL, | |
c7ba218d BS |
670 | }, |
671 | }; | |
672 | ||
673 | /* Sun4u hardware initialisation */ | |
fbe1b595 | 674 | static void sun4u_init(ram_addr_t RAM_size, |
3023f332 | 675 | const char *boot_devices, |
c7ba218d BS |
676 | const char *kernel_filename, const char *kernel_cmdline, |
677 | const char *initrd_filename, const char *cpu_model) | |
678 | { | |
fbe1b595 | 679 | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
c7ba218d BS |
680 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]); |
681 | } | |
682 | ||
683 | /* Sun4v hardware initialisation */ | |
fbe1b595 | 684 | static void sun4v_init(ram_addr_t RAM_size, |
3023f332 | 685 | const char *boot_devices, |
c7ba218d BS |
686 | const char *kernel_filename, const char *kernel_cmdline, |
687 | const char *initrd_filename, const char *cpu_model) | |
688 | { | |
fbe1b595 | 689 | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
c7ba218d BS |
690 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]); |
691 | } | |
692 | ||
e87231d4 | 693 | /* Niagara hardware initialisation */ |
fbe1b595 | 694 | static void niagara_init(ram_addr_t RAM_size, |
3023f332 | 695 | const char *boot_devices, |
e87231d4 BS |
696 | const char *kernel_filename, const char *kernel_cmdline, |
697 | const char *initrd_filename, const char *cpu_model) | |
698 | { | |
fbe1b595 | 699 | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
e87231d4 BS |
700 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]); |
701 | } | |
702 | ||
f80f9ec9 | 703 | static QEMUMachine sun4u_machine = { |
66de733b BS |
704 | .name = "sun4u", |
705 | .desc = "Sun4u platform", | |
706 | .init = sun4u_init, | |
1bcee014 | 707 | .max_cpus = 1, // XXX for now |
0c257437 | 708 | .is_default = 1, |
3475187d | 709 | }; |
c7ba218d | 710 | |
f80f9ec9 | 711 | static QEMUMachine sun4v_machine = { |
66de733b BS |
712 | .name = "sun4v", |
713 | .desc = "Sun4v platform", | |
714 | .init = sun4v_init, | |
1bcee014 | 715 | .max_cpus = 1, // XXX for now |
c7ba218d | 716 | }; |
e87231d4 | 717 | |
f80f9ec9 | 718 | static QEMUMachine niagara_machine = { |
e87231d4 BS |
719 | .name = "Niagara", |
720 | .desc = "Sun4v platform, Niagara", | |
721 | .init = niagara_init, | |
1bcee014 | 722 | .max_cpus = 1, // XXX for now |
e87231d4 | 723 | }; |
f80f9ec9 AL |
724 | |
725 | static void sun4u_machine_init(void) | |
726 | { | |
727 | qemu_register_machine(&sun4u_machine); | |
728 | qemu_register_machine(&sun4v_machine); | |
729 | qemu_register_machine(&niagara_machine); | |
730 | } | |
731 | ||
732 | machine_init(sun4u_machine_init); |