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[mirror_qemu.git] / memory.c
CommitLineData
093bc2cd
AK		 1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB		 12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
AK		 14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879
PB		 18#include "qemu-common.h"
19#include "cpu.h"
022c62cb
PB		 20#include "exec/memory.h"
21#include "exec/address-spaces.h"
22#include "exec/ioport.h"
409ddd01 23#include "qapi/visitor.h"
1de7afc9 24#include "qemu/bitops.h"
8c56c1a5 25#include "qemu/error-report.h"
2c9b15ca 26#include "qom/object.h"
0ab8ed18 27#include "trace-root.h"
093bc2cd 28
022c62cb 29#include "exec/memory-internal.h"
220c3ebd 30#include "exec/ram_addr.h"
8c56c1a5 31#include "sysemu/kvm.h"
e1c57ab8 32#include "sysemu/sysemu.h"
c9356746
FK		 33#include "hw/misc/mmio_interface.h"
34#include "hw/qdev-properties.h"
b08199c6 35#include "migration/vmstate.h"
67d95c15 36
d197063f
PB		 37//#define DEBUG_UNASSIGNED
38
22bde714
JK		 39static unsigned memory_region_transaction_depth;
40static bool memory_region_update_pending;
4dc56152 41static bool ioeventfd_update_pending;
7664e80c
AK		 42static bool global_dirty_log = false;
43
72e22d2f
AK		 44static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
45 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 46
0d673e36
AK		 47static QTAILQ_HEAD(, AddressSpace) address_spaces
48 = QTAILQ_HEAD_INITIALIZER(address_spaces);
49
967dc9b1
AK		 50static GHashTable *flat_views;
51
093bc2cd
AK		 52typedef struct AddrRange AddrRange;
53
8417cebf 54/*
c9cdaa3a 55 * Note that signed integers are needed for negative offsetting in aliases
8417cebf
AK		 56 * (large MemoryRegion::alias_offset).
57 */
093bc2cd 58struct AddrRange {
08dafab4
AK		 59 Int128 start;
60 Int128 size;
093bc2cd
AK		 61};
62
08dafab4 63static AddrRange addrrange_make(Int128 start, Int128 size)
093bc2cd
AK		 64{
65 return (AddrRange) { start, size };
66}
67
68static bool addrrange_equal(AddrRange r1, AddrRange r2)
69{
08dafab4 70 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
093bc2cd
AK		 71}
72
08dafab4 73static Int128 addrrange_end(AddrRange r)
093bc2cd 74{
08dafab4 75 return int128_add(r.start, r.size);
093bc2cd
AK		 76}
77
08dafab4 78static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 79{
08dafab4 80 int128_addto(&range.start, delta);
093bc2cd
AK		 81 return range;
82}
83
08dafab4
AK		 84static bool addrrange_contains(AddrRange range, Int128 addr)
85{
86 return int128_ge(addr, range.start)
87 && int128_lt(addr, addrrange_end(range));
88}
89
093bc2cd
AK		 90static bool addrrange_intersects(AddrRange r1, AddrRange r2)
91{
08dafab4
AK		 92 return addrrange_contains(r1, r2.start)
93 || addrrange_contains(r2, r1.start);
093bc2cd
AK		 94}
95
96static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
97{
08dafab4
AK		 98 Int128 start = int128_max(r1.start, r2.start);
99 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
100 return addrrange_make(start, int128_sub(end, start));
093bc2cd
AK		 101}
102
0e0d36b4
AK		 103enum ListenerDirection { Forward, Reverse };
104
7376e582 105#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
AK		 106 do { \
107 MemoryListener *_listener; \
108 \
109 switch (_direction) { \
110 case Forward: \
111 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
AK		 112 if (_listener->_callback) { \
113 _listener->_callback(_listener, ##_args); \
114 } \
0e0d36b4
AK		 115 } \
116 break; \
117 case Reverse: \
118 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
119 memory_listeners, link) { \
975aefe0
AK		 120 if (_listener->_callback) { \
121 _listener->_callback(_listener, ##_args); \
122 } \
0e0d36b4
AK		 123 } \
124 break; \
125 default: \
126 abort(); \
127 } \
128 } while (0)
129
9a54635d 130#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
7376e582
AK		 131 do { \
132 MemoryListener *_listener; \
9a54635d 133 struct memory_listeners_as *list = &(_as)->listeners; \
7376e582
AK		 134 \
135 switch (_direction) { \
136 case Forward: \
9a54635d
PB		 137 QTAILQ_FOREACH(_listener, list, link_as) { \
138 if (_listener->_callback) { \
7376e582
AK		 139 _listener->_callback(_listener, _section, ##_args); \
140 } \
141 } \
142 break; \
143 case Reverse: \
9a54635d
PB		 144 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
145 link_as) { \
146 if (_listener->_callback) { \
7376e582
AK		 147 _listener->_callback(_listener, _section, ##_args); \
148 } \
149 } \
150 break; \
151 default: \
152 abort(); \
153 } \
154 } while (0)
155
dfde4e6e 156/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 157#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44 158 do { \
16620684
AK		 159 MemoryRegionSection mrs = section_from_flat_range(fr, \
160 address_space_to_flatview(as)); \
9a54635d 161 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 162 } while(0)
0e0d36b4 163
093bc2cd
AK		 164struct CoalescedMemoryRange {
165 AddrRange addr;
166 QTAILQ_ENTRY(CoalescedMemoryRange) link;
167};
168
3e9d69e7
AK		 169struct MemoryRegionIoeventfd {
170 AddrRange addr;
171 bool match_data;
172 uint64_t data;
753d5e14 173 EventNotifier *e;
3e9d69e7
AK		 174};
175
176static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
177 MemoryRegionIoeventfd b)
178{
08dafab4 179 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 180 return true;
08dafab4 181 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 182 return false;
08dafab4 183 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 184 return true;
08dafab4 185 } else if (int128_gt(a.addr.size, b.addr.size)) {
3e9d69e7
AK		 186 return false;
187 } else if (a.match_data < b.match_data) {
188 return true;
189 } else if (a.match_data > b.match_data) {
190 return false;
191 } else if (a.match_data) {
192 if (a.data < b.data) {
193 return true;
194 } else if (a.data > b.data) {
195 return false;
196 }
197 }
753d5e14 198 if (a.e < b.e) {
3e9d69e7 199 return true;
753d5e14 200 } else if (a.e > b.e) {
3e9d69e7
AK		 201 return false;
202 }
203 return false;
204}
205
206static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
207 MemoryRegionIoeventfd b)
208{
209 return !memory_region_ioeventfd_before(a, b)
210 && !memory_region_ioeventfd_before(b, a);
211}
212
093bc2cd 213typedef struct FlatRange FlatRange;
093bc2cd
AK		 214
215/* Range of memory in the global map. Addresses are absolute. */
216struct FlatRange {
217 MemoryRegion *mr;
a8170e5e 218 hwaddr offset_in_region;
093bc2cd 219 AddrRange addr;
5a583347 220 uint8_t dirty_log_mask;
b138e654 221 bool romd_mode;
fb1cd6f9 222 bool readonly;
093bc2cd
AK		 223};
224
225/* Flattened global view of current active memory hierarchy. Kept in sorted
226 * order.
227 */
228struct FlatView {
374f2981 229 struct rcu_head rcu;
856d7245 230 unsigned ref;
093bc2cd
AK		 231 FlatRange *ranges;
232 unsigned nr;
233 unsigned nr_allocated;
66a6df1d 234 struct AddressSpaceDispatch *dispatch;
89c177bb 235 MemoryRegion *root;
093bc2cd
AK		 236};
237
cc31e6e7
AK		 238typedef struct AddressSpaceOps AddressSpaceOps;
239
093bc2cd
AK		 240#define FOR_EACH_FLAT_RANGE(var, view) \
241 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
242
9c1f8f44 243static inline MemoryRegionSection
16620684 244section_from_flat_range(FlatRange *fr, FlatView *fv)
9c1f8f44
PB		 245{
246 return (MemoryRegionSection) {
247 .mr = fr->mr,
16620684 248 .fv = fv,
9c1f8f44
PB		 249 .offset_within_region = fr->offset_in_region,
250 .size = fr->addr.size,
251 .offset_within_address_space = int128_get64(fr->addr.start),
252 .readonly = fr->readonly,
253 };
254}
255
093bc2cd
AK		 256static bool flatrange_equal(FlatRange *a, FlatRange *b)
257{
258 return a->mr == b->mr
259 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 260 && a->offset_in_region == b->offset_in_region
b138e654 261 && a->romd_mode == b->romd_mode
fb1cd6f9 262 && a->readonly == b->readonly;
093bc2cd
AK		 263}
264
89c177bb 265static FlatView *flatview_new(MemoryRegion *mr_root)
093bc2cd 266{
cc94cd6d
AK		 267 FlatView *view;
268
269 view = g_new0(FlatView, 1);
856d7245 270 view->ref = 1;
89c177bb
AK		 271 view->root = mr_root;
272 memory_region_ref(mr_root);
02d9651d 273 trace_flatview_new(view, mr_root);
cc94cd6d
AK		 274
275 return view;
093bc2cd
AK		 276}
277
278/* Insert a range into a given position. Caller is responsible for maintaining
279 * sorting order.
280 */
281static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
282{
283 if (view->nr == view->nr_allocated) {
284 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 285 view->ranges = g_realloc(view->ranges,
093bc2cd
AK		 286 view->nr_allocated * sizeof(*view->ranges));
287 }
288 memmove(view->ranges + pos + 1, view->ranges + pos,
289 (view->nr - pos) * sizeof(FlatRange));
290 view->ranges[pos] = *range;
dfde4e6e 291 memory_region_ref(range->mr);
093bc2cd
AK		 292 ++view->nr;
293}
294
295static void flatview_destroy(FlatView *view)
296{
dfde4e6e
PB		 297 int i;
298
02d9651d 299 trace_flatview_destroy(view, view->root);
66a6df1d
AK		 300 if (view->dispatch) {
301 address_space_dispatch_free(view->dispatch);
302 }
dfde4e6e
PB		 303 for (i = 0; i < view->nr; i++) {
304 memory_region_unref(view->ranges[i].mr);
305 }
7267c094 306 g_free(view->ranges);
89c177bb 307 memory_region_unref(view->root);
a9a0c06d 308 g_free(view);
093bc2cd
AK		 309}
310
447b0d0b 311static bool flatview_ref(FlatView *view)
856d7245 312{
447b0d0b 313 return atomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB		 314}
315
316static void flatview_unref(FlatView *view)
317{
318 if (atomic_fetch_dec(&view->ref) == 1) {
02d9651d 319 trace_flatview_destroy_rcu(view, view->root);
092aa2fc 320 assert(view->root);
66a6df1d 321 call_rcu(view, flatview_destroy, rcu);
856d7245
PB		 322 }
323}
324
16620684 325FlatView *address_space_to_flatview(AddressSpace *as)
66a6df1d
AK		 326{
327 return atomic_rcu_read(&as->current_map);
328}
329
330AddressSpaceDispatch *flatview_to_dispatch(FlatView *fv)
331{
332 return fv->dispatch;
333}
334
335AddressSpaceDispatch *address_space_to_dispatch(AddressSpace *as)
336{
337 return flatview_to_dispatch(address_space_to_flatview(as));
338}
339
3d8e6bf9
AK		 340static bool can_merge(FlatRange *r1, FlatRange *r2)
341{
08dafab4 342 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 343 && r1->mr == r2->mr
08dafab4
AK		 344 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
345 r1->addr.size),
346 int128_make64(r2->offset_in_region))
d0a9b5bc 347 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 348 && r1->romd_mode == r2->romd_mode
fb1cd6f9 349 && r1->readonly == r2->readonly;
3d8e6bf9
AK		 350}
351
8508e024 352/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK		 353static void flatview_simplify(FlatView *view)
354{
355 unsigned i, j;
356
357 i = 0;
358 while (i < view->nr) {
359 j = i + 1;
360 while (j < view->nr
361 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 362 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
AK		 363 ++j;
364 }
365 ++i;
366 memmove(&view->ranges[i], &view->ranges[j],
367 (view->nr - j) * sizeof(view->ranges[j]));
368 view->nr -= j - i;
369 }
370}
371
e7342aa3
PB		 372static bool memory_region_big_endian(MemoryRegion *mr)
373{
374#ifdef TARGET_WORDS_BIGENDIAN
375 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
376#else
377 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
378#endif
379}
380
e11ef3d1
PB		 381static bool memory_region_wrong_endianness(MemoryRegion *mr)
382{
383#ifdef TARGET_WORDS_BIGENDIAN
384 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
385#else
386 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
387#endif
388}
389
390static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
391{
392 if (memory_region_wrong_endianness(mr)) {
393 switch (size) {
394 case 1:
395 break;
396 case 2:
397 *data = bswap16(*data);
398 break;
399 case 4:
400 *data = bswap32(*data);
401 break;
402 case 8:
403 *data = bswap64(*data);
404 break;
405 default:
406 abort();
407 }
408 }
409}
410
4779dc1d
HB		 411static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
412{
413 MemoryRegion *root;
414 hwaddr abs_addr = offset;
415
416 abs_addr += mr->addr;
417 for (root = mr; root->container; ) {
418 root = root->container;
419 abs_addr += root->addr;
420 }
421
422 return abs_addr;
423}
424
5a68be94
HB		 425static int get_cpu_index(void)
426{
427 if (current_cpu) {
428 return current_cpu->cpu_index;
429 }
430 return -1;
431}
432
cc05c43a
PM		 433static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
434 hwaddr addr,
435 uint64_t *value,
436 unsigned size,
437 unsigned shift,
438 uint64_t mask,
439 MemTxAttrs attrs)
440{
441 uint64_t tmp;
442
443 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
23d92d68 444 if (mr->subpage) {
5a68be94 445 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 446 } else if (mr == &io_mem_notdirty) {
447 /* Accesses to code which has previously been translated into a TB show
448 * up in the MMIO path, as accesses to the io_mem_notdirty
449 * MemoryRegion. */
450 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 451 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
452 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 453 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 454 }
cc05c43a
PM		 455 *value |= (tmp & mask) << shift;
456 return MEMTX_OK;
457}
458
459static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB		 460 hwaddr addr,
461 uint64_t *value,
462 unsigned size,
463 unsigned shift,
cc05c43a
PM		 464 uint64_t mask,
465 MemTxAttrs attrs)
ce5d2f33 466{
ce5d2f33
PB		 467 uint64_t tmp;
468
cc05c43a 469 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 470 if (mr->subpage) {
5a68be94 471 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 472 } else if (mr == &io_mem_notdirty) {
473 /* Accesses to code which has previously been translated into a TB show
474 * up in the MMIO path, as accesses to the io_mem_notdirty
475 * MemoryRegion. */
476 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 477 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
478 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 479 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 480 }
ce5d2f33 481 *value |= (tmp & mask) << shift;
cc05c43a 482 return MEMTX_OK;
ce5d2f33
PB		 483}
484
cc05c43a
PM		 485static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
486 hwaddr addr,
487 uint64_t *value,
488 unsigned size,
489 unsigned shift,
490 uint64_t mask,
491 MemTxAttrs attrs)
164a4dcd 492{
cc05c43a
PM		 493 uint64_t tmp = 0;
494 MemTxResult r;
164a4dcd 495
cc05c43a 496 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 497 if (mr->subpage) {
5a68be94 498 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 499 } else if (mr == &io_mem_notdirty) {
500 /* Accesses to code which has previously been translated into a TB show
501 * up in the MMIO path, as accesses to the io_mem_notdirty
502 * MemoryRegion. */
503 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 504 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
505 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 506 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 507 }
164a4dcd 508 *value |= (tmp & mask) << shift;
cc05c43a 509 return r;
164a4dcd
AK		 510}
511
cc05c43a
PM		 512static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
513 hwaddr addr,
514 uint64_t *value,
515 unsigned size,
516 unsigned shift,
517 uint64_t mask,
518 MemTxAttrs attrs)
ce5d2f33 519{
ce5d2f33
PB		 520 uint64_t tmp;
521
522 tmp = (*value >> shift) & mask;
23d92d68 523 if (mr->subpage) {
5a68be94 524 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 525 } else if (mr == &io_mem_notdirty) {
526 /* Accesses to code which has previously been translated into a TB show
527 * up in the MMIO path, as accesses to the io_mem_notdirty
528 * MemoryRegion. */
529 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 530 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
531 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 532 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 533 }
ce5d2f33 534 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
cc05c43a 535 return MEMTX_OK;
ce5d2f33
PB		 536}
537
cc05c43a
PM		 538static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
539 hwaddr addr,
540 uint64_t *value,
541 unsigned size,
542 unsigned shift,
543 uint64_t mask,
544 MemTxAttrs attrs)
164a4dcd 545{
164a4dcd
AK		 546 uint64_t tmp;
547
548 tmp = (*value >> shift) & mask;
23d92d68 549 if (mr->subpage) {
5a68be94 550 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 551 } else if (mr == &io_mem_notdirty) {
552 /* Accesses to code which has previously been translated into a TB show
553 * up in the MMIO path, as accesses to the io_mem_notdirty
554 * MemoryRegion. */
555 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 556 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
557 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 558 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 559 }
164a4dcd 560 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 561 return MEMTX_OK;
164a4dcd
AK		 562}
563
cc05c43a
PM		 564static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
565 hwaddr addr,
566 uint64_t *value,
567 unsigned size,
568 unsigned shift,
569 uint64_t mask,
570 MemTxAttrs attrs)
571{
572 uint64_t tmp;
573
cc05c43a 574 tmp = (*value >> shift) & mask;
23d92d68 575 if (mr->subpage) {
5a68be94 576 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 577 } else if (mr == &io_mem_notdirty) {
578 /* Accesses to code which has previously been translated into a TB show
579 * up in the MMIO path, as accesses to the io_mem_notdirty
580 * MemoryRegion. */
581 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 582 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
583 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 584 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 585 }
cc05c43a
PM		 586 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
587}
588
589static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK		 590 uint64_t *value,
591 unsigned size,
592 unsigned access_size_min,
593 unsigned access_size_max,
05e015f7
KF		 594 MemTxResult (*access_fn)
595 (MemoryRegion *mr,
596 hwaddr addr,
597 uint64_t *value,
598 unsigned size,
599 unsigned shift,
600 uint64_t mask,
601 MemTxAttrs attrs),
cc05c43a
PM		 602 MemoryRegion *mr,
603 MemTxAttrs attrs)
164a4dcd
AK		 604{
605 uint64_t access_mask;
606 unsigned access_size;
607 unsigned i;
cc05c43a 608 MemTxResult r = MEMTX_OK;
164a4dcd
AK		 609
610 if (!access_size_min) {
611 access_size_min = 1;
612 }
613 if (!access_size_max) {
614 access_size_max = 4;
615 }
ce5d2f33
PB		 616
617 /* FIXME: support unaligned access? */
164a4dcd
AK		 618 access_size = MAX(MIN(size, access_size_max), access_size_min);
619 access_mask = -1ULL >> (64 - access_size * 8);
e7342aa3
PB		 620 if (memory_region_big_endian(mr)) {
621 for (i = 0; i < size; i += access_size) {
05e015f7 622 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 623 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB		 624 }
625 } else {
626 for (i = 0; i < size; i += access_size) {
05e015f7 627 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 628 access_mask, attrs);
e7342aa3 629 }
164a4dcd 630 }
cc05c43a 631 return r;
164a4dcd
AK		 632}
633
e2177955
AK		 634static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
635{
0d673e36
AK		 636 AddressSpace *as;
637
feca4ac1
PB		 638 while (mr->container) {
639 mr = mr->container;
e2177955 640 }
0d673e36
AK		 641 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
642 if (mr == as->root) {
643 return as;
644 }
e2177955 645 }
eed2bacf 646 return NULL;
e2177955
AK		 647}
648
093bc2cd
AK		 649/* Render a memory region into the global view. Ranges in @view obscure
650 * ranges in @mr.
651 */
652static void render_memory_region(FlatView *view,
653 MemoryRegion *mr,
08dafab4 654 Int128 base,
fb1cd6f9
AK		 655 AddrRange clip,
656 bool readonly)
093bc2cd
AK		 657{
658 MemoryRegion *subregion;
659 unsigned i;
a8170e5e 660 hwaddr offset_in_region;
08dafab4
AK		 661 Int128 remain;
662 Int128 now;
093bc2cd
AK		 663 FlatRange fr;
664 AddrRange tmp;
665
6bba19ba
AK		 666 if (!mr->enabled) {
667 return;
668 }
669
08dafab4 670 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 671 readonly |= mr->readonly;
093bc2cd
AK		 672
673 tmp = addrrange_make(base, mr->size);
674
675 if (!addrrange_intersects(tmp, clip)) {
676 return;
677 }
678
679 clip = addrrange_intersection(tmp, clip);
680
681 if (mr->alias) {
08dafab4
AK		 682 int128_subfrom(&base, int128_make64(mr->alias->addr));
683 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 684 render_memory_region(view, mr->alias, base, clip, readonly);
093bc2cd
AK		 685 return;
686 }
687
688 /* Render subregions in priority order. */
689 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 690 render_memory_region(view, subregion, base, clip, readonly);
093bc2cd
AK		 691 }
692
14a3c10a 693 if (!mr->terminates) {
093bc2cd
AK		 694 return;
695 }
696
08dafab4 697 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK		 698 base = clip.start;
699 remain = clip.size;
700
2eb74e1a 701 fr.mr = mr;
6f6a5ef3 702 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 703 fr.romd_mode = mr->romd_mode;
2eb74e1a
PC		 704 fr.readonly = readonly;
705
093bc2cd 706 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK		 707 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
708 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK		 709 continue;
710 }
08dafab4
AK		 711 if (int128_lt(base, view->ranges[i].addr.start)) {
712 now = int128_min(remain,
713 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK		 714 fr.offset_in_region = offset_in_region;
715 fr.addr = addrrange_make(base, now);
716 flatview_insert(view, i, &fr);
717 ++i;
08dafab4
AK		 718 int128_addto(&base, now);
719 offset_in_region += int128_get64(now);
720 int128_subfrom(&remain, now);
093bc2cd 721 }
d26a8cae
AK		 722 now = int128_sub(int128_min(int128_add(base, remain),
723 addrrange_end(view->ranges[i].addr)),
724 base);
725 int128_addto(&base, now);
726 offset_in_region += int128_get64(now);
727 int128_subfrom(&remain, now);
093bc2cd 728 }
08dafab4 729 if (int128_nz(remain)) {
093bc2cd
AK		 730 fr.offset_in_region = offset_in_region;
731 fr.addr = addrrange_make(base, remain);
732 flatview_insert(view, i, &fr);
733 }
734}
735
89c177bb
AK		 736static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
737{
e673ba9a
PB		 738 while (mr->enabled) {
739 if (mr->alias) {
740 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
741 /* The alias is included in its entirety. Use it as
742 * the "real" root, so that we can share more FlatViews.
743 */
744 mr = mr->alias;
745 continue;
746 }
747 } else if (!mr->terminates) {
748 unsigned int found = 0;
749 MemoryRegion *child, *next = NULL;
750 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
751 if (child->enabled) {
752 if (++found > 1) {
753 next = NULL;
754 break;
755 }
756 if (!child->addr && int128_ge(mr->size, child->size)) {
757 /* A child is included in its entirety. If it's the only
758 * enabled one, use it in the hope of finding an alias down the
759 * way. This will also let us share FlatViews.
760 */
761 next = child;
762 }
763 }
764 }
092aa2fc
AK		 765 if (found == 0) {
766 return NULL;
767 }
e673ba9a
PB		 768 if (next) {
769 mr = next;
770 continue;
771 }
772 }
773
092aa2fc 774 return mr;
89c177bb
AK		 775 }
776
092aa2fc 777 return NULL;
89c177bb
AK		 778}
779
093bc2cd 780/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 781static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 782{
9bf561e3 783 int i;
a9a0c06d 784 FlatView *view;
093bc2cd 785
89c177bb 786 view = flatview_new(mr);
093bc2cd 787
83f3c251 788 if (mr) {
a9a0c06d 789 render_memory_region(view, mr, int128_zero(),
83f3c251
AK		 790 addrrange_make(int128_zero(), int128_2_64()), false);
791 }
a9a0c06d 792 flatview_simplify(view);
093bc2cd 793
9bf561e3
AK		 794 view->dispatch = address_space_dispatch_new(view);
795 for (i = 0; i < view->nr; i++) {
796 MemoryRegionSection mrs =
797 section_from_flat_range(&view->ranges[i], view);
798 flatview_add_to_dispatch(view, &mrs);
799 }
800 address_space_dispatch_compact(view->dispatch);
967dc9b1 801 g_hash_table_replace(flat_views, mr, view);
9bf561e3 802
093bc2cd
AK		 803 return view;
804}
805
3e9d69e7
AK		 806static void address_space_add_del_ioeventfds(AddressSpace *as,
807 MemoryRegionIoeventfd *fds_new,
808 unsigned fds_new_nb,
809 MemoryRegionIoeventfd *fds_old,
810 unsigned fds_old_nb)
811{
812 unsigned iold, inew;
80a1ea37
AK		 813 MemoryRegionIoeventfd *fd;
814 MemoryRegionSection section;
3e9d69e7
AK		 815
816 /* Generate a symmetric difference of the old and new fd sets, adding
817 * and deleting as necessary.
818 */
819
820 iold = inew = 0;
821 while (iold < fds_old_nb || inew < fds_new_nb) {
822 if (iold < fds_old_nb
823 && (inew == fds_new_nb
824 || memory_region_ioeventfd_before(fds_old[iold],
825 fds_new[inew]))) {
80a1ea37
AK		 826 fd = &fds_old[iold];
827 section = (MemoryRegionSection) {
16620684 828 .fv = address_space_to_flatview(as),
80a1ea37 829 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 830 .size = fd->addr.size,
80a1ea37 831 };
9a54635d 832 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 833 fd->match_data, fd->data, fd->e);
3e9d69e7
AK		 834 ++iold;
835 } else if (inew < fds_new_nb
836 && (iold == fds_old_nb
837 || memory_region_ioeventfd_before(fds_new[inew],
838 fds_old[iold]))) {
80a1ea37
AK		 839 fd = &fds_new[inew];
840 section = (MemoryRegionSection) {
16620684 841 .fv = address_space_to_flatview(as),
80a1ea37 842 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 843 .size = fd->addr.size,
80a1ea37 844 };
9a54635d 845 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 846 fd->match_data, fd->data, fd->e);
3e9d69e7
AK		 847 ++inew;
848 } else {
849 ++iold;
850 ++inew;
851 }
852 }
853}
854
856d7245
PB		 855static FlatView *address_space_get_flatview(AddressSpace *as)
856{
857 FlatView *view;
858
374f2981 859 rcu_read_lock();
447b0d0b 860 do {
16620684 861 view = address_space_to_flatview(as);
447b0d0b
PB		 862 /* If somebody has replaced as->current_map concurrently,
863 * flatview_ref returns false.
864 */
865 } while (!flatview_ref(view));
374f2981 866 rcu_read_unlock();
856d7245
PB		 867 return view;
868}
869
3e9d69e7
AK		 870static void address_space_update_ioeventfds(AddressSpace *as)
871{
99e86347 872 FlatView *view;
3e9d69e7
AK		 873 FlatRange *fr;
874 unsigned ioeventfd_nb = 0;
875 MemoryRegionIoeventfd *ioeventfds = NULL;
876 AddrRange tmp;
877 unsigned i;
878
856d7245 879 view = address_space_get_flatview(as);
99e86347 880 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK		 881 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
882 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK		 883 int128_sub(fr->addr.start,
884 int128_make64(fr->offset_in_region)));
3e9d69e7
AK		 885 if (addrrange_intersects(fr->addr, tmp)) {
886 ++ioeventfd_nb;
7267c094 887 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK		 888 ioeventfd_nb * sizeof(*ioeventfds));
889 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
890 ioeventfds[ioeventfd_nb-1].addr = tmp;
891 }
892 }
893 }
894
895 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
896 as->ioeventfds, as->ioeventfd_nb);
897
7267c094 898 g_free(as->ioeventfds);
3e9d69e7
AK		 899 as->ioeventfds = ioeventfds;
900 as->ioeventfd_nb = ioeventfd_nb;
856d7245 901 flatview_unref(view);
3e9d69e7
AK		 902}
903
b8af1afb 904static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB		 905 const FlatView *old_view,
906 const FlatView *new_view,
b8af1afb 907 bool adding)
093bc2cd 908{
093bc2cd
AK		 909 unsigned iold, inew;
910 FlatRange *frold, *frnew;
093bc2cd
AK		 911
912 /* Generate a symmetric difference of the old and new memory maps.
913 * Kill ranges in the old map, and instantiate ranges in the new map.
914 */
915 iold = inew = 0;
a9a0c06d
PB		 916 while (iold < old_view->nr || inew < new_view->nr) {
917 if (iold < old_view->nr) {
918 frold = &old_view->ranges[iold];
093bc2cd
AK		 919 } else {
920 frold = NULL;
921 }
a9a0c06d
PB		 922 if (inew < new_view->nr) {
923 frnew = &new_view->ranges[inew];
093bc2cd
AK		 924 } else {
925 frnew = NULL;
926 }
927
928 if (frold
929 && (!frnew
08dafab4
AK		 930 || int128_lt(frold->addr.start, frnew->addr.start)
931 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 932 && !flatrange_equal(frold, frnew)))) {
41a6e477 933 /* In old but not in new, or in both but attributes changed. */
093bc2cd 934
b8af1afb 935 if (!adding) {
72e22d2f 936 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK		 937 }
938
093bc2cd
AK		 939 ++iold;
940 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 941 /* In both and unchanged (except logging may have changed) */
093bc2cd 942
b8af1afb 943 if (adding) {
50c1e149 944 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB		 945 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
946 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
947 frold->dirty_log_mask,
948 frnew->dirty_log_mask);
949 }
950 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
951 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
952 frold->dirty_log_mask,
953 frnew->dirty_log_mask);
b8af1afb 954 }
5a583347
AK		 955 }
956
093bc2cd
AK		 957 ++iold;
958 ++inew;
093bc2cd
AK		 959 } else {
960 /* In new */
961
b8af1afb 962 if (adding) {
72e22d2f 963 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK		 964 }
965
093bc2cd
AK		 966 ++inew;
967 }
968 }
b8af1afb
AK		 969}
970
967dc9b1
AK		 971static void flatviews_init(void)
972{
092aa2fc
AK		 973 static FlatView *empty_view;
974
967dc9b1
AK		 975 if (flat_views) {
976 return;
977 }
978
979 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
980 (GDestroyNotify) flatview_unref);
092aa2fc
AK		 981 if (!empty_view) {
982 empty_view = generate_memory_topology(NULL);
983 /* We keep it alive forever in the global variable. */
984 flatview_ref(empty_view);
985 } else {
986 g_hash_table_replace(flat_views, NULL, empty_view);
987 flatview_ref(empty_view);
988 }
967dc9b1
AK		 989}
990
991static void flatviews_reset(void)
992{
993 AddressSpace *as;
994
995 if (flat_views) {
996 g_hash_table_unref(flat_views);
997 flat_views = NULL;
998 }
999 flatviews_init();
1000
1001 /* Render unique FVs */
1002 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1003 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1004
1005 if (g_hash_table_lookup(flat_views, physmr)) {
1006 continue;
1007 }
1008
1009 generate_memory_topology(physmr);
1010 }
1011}
1012
1013static void address_space_set_flatview(AddressSpace *as)
b8af1afb 1014{
67ace39b 1015 FlatView *old_view = address_space_to_flatview(as);
967dc9b1
AK		 1016 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1017 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1018
1019 assert(new_view);
1020
67ace39b
AK		 1021 if (old_view == new_view) {
1022 return;
1023 }
1024
1025 if (old_view) {
1026 flatview_ref(old_view);
1027 }
1028
967dc9b1 1029 flatview_ref(new_view);
9a62e24f
AK		 1030
1031 if (!QTAILQ_EMPTY(&as->listeners)) {
67ace39b
AK		 1032 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1033
1034 if (!old_view2) {
1035 old_view2 = &tmpview;
1036 }
1037 address_space_update_topology_pass(as, old_view2, new_view, false);
1038 address_space_update_topology_pass(as, old_view2, new_view, true);
9a62e24f 1039 }
b8af1afb 1040
374f2981
PB		 1041 /* Writes are protected by the BQL. */
1042 atomic_rcu_set(&as->current_map, new_view);
67ace39b
AK		 1043 if (old_view) {
1044 flatview_unref(old_view);
1045 }
856d7245
PB		 1046
1047 /* Note that all the old MemoryRegions are still alive up to this
1048 * point. This relieves most MemoryListeners from the need to
1049 * ref/unref the MemoryRegions they get---unless they use them
1050 * outside the iothread mutex, in which case precise reference
1051 * counting is necessary.
1052 */
67ace39b
AK		 1053 if (old_view) {
1054 flatview_unref(old_view);
1055 }
093bc2cd
AK		 1056}
1057
202fc01b
AK		 1058static void address_space_update_topology(AddressSpace *as)
1059{
1060 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1061
1062 flatviews_init();
1063 if (!g_hash_table_lookup(flat_views, physmr)) {
1064 generate_memory_topology(physmr);
1065 }
1066 address_space_set_flatview(as);
1067}
1068
4ef4db86
AK		 1069void memory_region_transaction_begin(void)
1070{
bb880ded 1071 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK		 1072 ++memory_region_transaction_depth;
1073}
1074
1075void memory_region_transaction_commit(void)
1076{
0d673e36
AK		 1077 AddressSpace *as;
1078
4ef4db86 1079 assert(memory_region_transaction_depth);
8d04fb55
JK		 1080 assert(qemu_mutex_iothread_locked());
1081
4ef4db86 1082 --memory_region_transaction_depth;
4dc56152
GA		 1083 if (!memory_region_transaction_depth) {
1084 if (memory_region_update_pending) {
967dc9b1
AK		 1085 flatviews_reset();
1086
4dc56152 1087 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 1088
4dc56152 1089 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
967dc9b1 1090 address_space_set_flatview(as);
02218487 1091 address_space_update_ioeventfds(as);
4dc56152 1092 }
ade9c1aa 1093 memory_region_update_pending = false;
4dc56152
GA		 1094 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1095 } else if (ioeventfd_update_pending) {
1096 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1097 address_space_update_ioeventfds(as);
1098 }
ade9c1aa 1099 ioeventfd_update_pending = false;
4dc56152 1100 }
4dc56152 1101 }
4ef4db86
AK		 1102}
1103
545e92e0
AK		 1104static void memory_region_destructor_none(MemoryRegion *mr)
1105{
1106}
1107
1108static void memory_region_destructor_ram(MemoryRegion *mr)
1109{
f1060c55 1110 qemu_ram_free(mr->ram_block);
545e92e0
AK		 1111}
1112
b4fefef9
PC		 1113static bool memory_region_need_escape(char c)
1114{
1115 return c == '/' || c == '[' || c == '\\' || c == ']';
1116}
1117
1118static char *memory_region_escape_name(const char *name)
1119{
1120 const char *p;
1121 char *escaped, *q;
1122 uint8_t c;
1123 size_t bytes = 0;
1124
1125 for (p = name; *p; p++) {
1126 bytes += memory_region_need_escape(*p) ? 4 : 1;
1127 }
1128 if (bytes == p - name) {
1129 return g_memdup(name, bytes + 1);
1130 }
1131
1132 escaped = g_malloc(bytes + 1);
1133 for (p = name, q = escaped; *p; p++) {
1134 c = *p;
1135 if (unlikely(memory_region_need_escape(c))) {
1136 *q++ = '\\';
1137 *q++ = 'x';
1138 *q++ = "0123456789abcdef"[c >> 4];
1139 c = "0123456789abcdef"[c & 15];
1140 }
1141 *q++ = c;
1142 }
1143 *q = 0;
1144 return escaped;
1145}
1146
3df9d748
AK		 1147static void memory_region_do_init(MemoryRegion *mr,
1148 Object *owner,
1149 const char *name,
1150 uint64_t size)
093bc2cd 1151{
08dafab4
AK		 1152 mr->size = int128_make64(size);
1153 if (size == UINT64_MAX) {
1154 mr->size = int128_2_64();
1155 }
302fa283 1156 mr->name = g_strdup(name);
612263cf 1157 mr->owner = owner;
58eaa217 1158 mr->ram_block = NULL;
b4fefef9
PC		 1159
1160 if (name) {
843ef73a
PC		 1161 char *escaped_name = memory_region_escape_name(name);
1162 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB		 1163
1164 if (!owner) {
1165 owner = container_get(qdev_get_machine(), "/unattached");
1166 }
1167
843ef73a 1168 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1169 object_unref(OBJECT(mr));
843ef73a
PC		 1170 g_free(name_array);
1171 g_free(escaped_name);
b4fefef9
PC		 1172 }
1173}
1174
3df9d748
AK		 1175void memory_region_init(MemoryRegion *mr,
1176 Object *owner,
1177 const char *name,
1178 uint64_t size)
1179{
1180 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1181 memory_region_do_init(mr, owner, name, size);
1182}
1183
d7bce999
EB		 1184static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1185 void *opaque, Error **errp)
409ddd01
PC		 1186{
1187 MemoryRegion *mr = MEMORY_REGION(obj);
1188 uint64_t value = mr->addr;
1189
51e72bc1 1190 visit_type_uint64(v, name, &value, errp);
409ddd01
PC		 1191}
1192
d7bce999
EB		 1193static void memory_region_get_container(Object *obj, Visitor *v,
1194 const char *name, void *opaque,
1195 Error **errp)
409ddd01
PC		 1196{
1197 MemoryRegion *mr = MEMORY_REGION(obj);
1198 gchar *path = (gchar *)"";
1199
1200 if (mr->container) {
1201 path = object_get_canonical_path(OBJECT(mr->container));
1202 }
51e72bc1 1203 visit_type_str(v, name, &path, errp);
409ddd01
PC		 1204 if (mr->container) {
1205 g_free(path);
1206 }
1207}
1208
1209static Object *memory_region_resolve_container(Object *obj, void *opaque,
1210 const char *part)
1211{
1212 MemoryRegion *mr = MEMORY_REGION(obj);
1213
1214 return OBJECT(mr->container);
1215}
1216
d7bce999
EB		 1217static void memory_region_get_priority(Object *obj, Visitor *v,
1218 const char *name, void *opaque,
1219 Error **errp)
d33382da
PC		 1220{
1221 MemoryRegion *mr = MEMORY_REGION(obj);
1222 int32_t value = mr->priority;
1223
51e72bc1 1224 visit_type_int32(v, name, &value, errp);
d33382da
PC		 1225}
1226
d7bce999
EB		 1227static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1228 void *opaque, Error **errp)
52aef7bb
PC		 1229{
1230 MemoryRegion *mr = MEMORY_REGION(obj);
1231 uint64_t value = memory_region_size(mr);
1232
51e72bc1 1233 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC		 1234}
1235
b4fefef9
PC		 1236static void memory_region_initfn(Object *obj)
1237{
1238 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1239 ObjectProperty *op;
b4fefef9
PC		 1240
1241 mr->ops = &unassigned_mem_ops;
6bba19ba 1242 mr->enabled = true;
5f9a5ea1 1243 mr->romd_mode = true;
196ea131 1244 mr->global_locking = true;
545e92e0 1245 mr->destructor = memory_region_destructor_none;
093bc2cd 1246 QTAILQ_INIT(&mr->subregions);
093bc2cd 1247 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC		 1248
1249 op = object_property_add(OBJECT(mr), "container",
1250 "link<" TYPE_MEMORY_REGION ">",
1251 memory_region_get_container,
1252 NULL, /* memory_region_set_container */
1253 NULL, NULL, &error_abort);
1254 op->resolve = memory_region_resolve_container;
1255
1256 object_property_add(OBJECT(mr), "addr", "uint64",
1257 memory_region_get_addr,
1258 NULL, /* memory_region_set_addr */
1259 NULL, NULL, &error_abort);
d33382da
PC		 1260 object_property_add(OBJECT(mr), "priority", "uint32",
1261 memory_region_get_priority,
1262 NULL, /* memory_region_set_priority */
1263 NULL, NULL, &error_abort);
52aef7bb
PC		 1264 object_property_add(OBJECT(mr), "size", "uint64",
1265 memory_region_get_size,
1266 NULL, /* memory_region_set_size, */
1267 NULL, NULL, &error_abort);
093bc2cd
AK		 1268}
1269
3df9d748
AK		 1270static void iommu_memory_region_initfn(Object *obj)
1271{
1272 MemoryRegion *mr = MEMORY_REGION(obj);
1273
1274 mr->is_iommu = true;
1275}
1276
b018ddf6
PB		 1277static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1278 unsigned size)
1279{
1280#ifdef DEBUG_UNASSIGNED
1281 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1282#endif
4917cf44
AF		 1283 if (current_cpu != NULL) {
1284 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
c658b94f 1285 }
68a7439a 1286 return 0;
b018ddf6
PB		 1287}
1288
1289static void unassigned_mem_write(void *opaque, hwaddr addr,
1290 uint64_t val, unsigned size)
1291{
1292#ifdef DEBUG_UNASSIGNED
1293 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1294#endif
4917cf44
AF		 1295 if (current_cpu != NULL) {
1296 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1297 }
b018ddf6
PB		 1298}
1299
d197063f
PB		 1300static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1301 unsigned size, bool is_write)
1302{
1303 return false;
1304}
1305
1306const MemoryRegionOps unassigned_mem_ops = {
1307 .valid.accepts = unassigned_mem_accepts,
1308 .endianness = DEVICE_NATIVE_ENDIAN,
1309};
1310
4a2e242b
AW		 1311static uint64_t memory_region_ram_device_read(void *opaque,
1312 hwaddr addr, unsigned size)
1313{
1314 MemoryRegion *mr = opaque;
1315 uint64_t data = (uint64_t)~0;
1316
1317 switch (size) {
1318 case 1:
1319 data = *(uint8_t *)(mr->ram_block->host + addr);
1320 break;
1321 case 2:
1322 data = *(uint16_t *)(mr->ram_block->host + addr);
1323 break;
1324 case 4:
1325 data = *(uint32_t *)(mr->ram_block->host + addr);
1326 break;
1327 case 8:
1328 data = *(uint64_t *)(mr->ram_block->host + addr);
1329 break;
1330 }
1331
1332 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1333
1334 return data;
1335}
1336
1337static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1338 uint64_t data, unsigned size)
1339{
1340 MemoryRegion *mr = opaque;
1341
1342 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1343
1344 switch (size) {
1345 case 1:
1346 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1347 break;
1348 case 2:
1349 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1350 break;
1351 case 4:
1352 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1353 break;
1354 case 8:
1355 *(uint64_t *)(mr->ram_block->host + addr) = data;
1356 break;
1357 }
1358}
1359
1360static const MemoryRegionOps ram_device_mem_ops = {
1361 .read = memory_region_ram_device_read,
1362 .write = memory_region_ram_device_write,
c99a29e7 1363 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW		 1364 .valid = {
1365 .min_access_size = 1,
1366 .max_access_size = 8,
1367 .unaligned = true,
1368 },
1369 .impl = {
1370 .min_access_size = 1,
1371 .max_access_size = 8,
1372 .unaligned = true,
1373 },
1374};
1375
d2702032
PB		 1376bool memory_region_access_valid(MemoryRegion *mr,
1377 hwaddr addr,
1378 unsigned size,
1379 bool is_write)
093bc2cd 1380{
a014ed07
PB		 1381 int access_size_min, access_size_max;
1382 int access_size, i;
897fa7cf 1383
093bc2cd
AK		 1384 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1385 return false;
1386 }
1387
a014ed07 1388 if (!mr->ops->valid.accepts) {
093bc2cd
AK		 1389 return true;
1390 }
1391
a014ed07
PB		 1392 access_size_min = mr->ops->valid.min_access_size;
1393 if (!mr->ops->valid.min_access_size) {
1394 access_size_min = 1;
1395 }
1396
1397 access_size_max = mr->ops->valid.max_access_size;
1398 if (!mr->ops->valid.max_access_size) {
1399 access_size_max = 4;
1400 }
1401
1402 access_size = MAX(MIN(size, access_size_max), access_size_min);
1403 for (i = 0; i < size; i += access_size) {
1404 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1405 is_write)) {
1406 return false;
1407 }
093bc2cd 1408 }
a014ed07 1409
093bc2cd
AK		 1410 return true;
1411}
1412
cc05c43a
PM		 1413static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1414 hwaddr addr,
1415 uint64_t *pval,
1416 unsigned size,
1417 MemTxAttrs attrs)
093bc2cd 1418{
cc05c43a 1419 *pval = 0;
093bc2cd 1420
ce5d2f33 1421 if (mr->ops->read) {
cc05c43a
PM		 1422 return access_with_adjusted_size(addr, pval, size,
1423 mr->ops->impl.min_access_size,
1424 mr->ops->impl.max_access_size,
1425 memory_region_read_accessor,
1426 mr, attrs);
1427 } else if (mr->ops->read_with_attrs) {
1428 return access_with_adjusted_size(addr, pval, size,
1429 mr->ops->impl.min_access_size,
1430 mr->ops->impl.max_access_size,
1431 memory_region_read_with_attrs_accessor,
1432 mr, attrs);
ce5d2f33 1433 } else {
cc05c43a
PM		 1434 return access_with_adjusted_size(addr, pval, size, 1, 4,
1435 memory_region_oldmmio_read_accessor,
1436 mr, attrs);
74901c3b 1437 }
093bc2cd
AK		 1438}
1439
3b643495
PM		 1440MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1441 hwaddr addr,
1442 uint64_t *pval,
1443 unsigned size,
1444 MemTxAttrs attrs)
a621f38d 1445{
cc05c43a
PM		 1446 MemTxResult r;
1447
791af8c8
PB		 1448 if (!memory_region_access_valid(mr, addr, size, false)) {
1449 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1450 return MEMTX_DECODE_ERROR;
791af8c8 1451 }
a621f38d 1452
cc05c43a 1453 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1454 adjust_endianness(mr, pval, size);
cc05c43a 1455 return r;
a621f38d 1456}
093bc2cd 1457
8c56c1a5
PF		 1458/* Return true if an eventfd was signalled */
1459static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1460 hwaddr addr,
1461 uint64_t data,
1462 unsigned size,
1463 MemTxAttrs attrs)
1464{
1465 MemoryRegionIoeventfd ioeventfd = {
1466 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1467 .data = data,
1468 };
1469 unsigned i;
1470
1471 for (i = 0; i < mr->ioeventfd_nb; i++) {
1472 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1473 ioeventfd.e = mr->ioeventfds[i].e;
1474
1475 if (memory_region_ioeventfd_equal(ioeventfd, mr->ioeventfds[i])) {
1476 event_notifier_set(ioeventfd.e);
1477 return true;
1478 }
1479 }
1480
1481 return false;
1482}
1483
3b643495
PM		 1484MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1485 hwaddr addr,
1486 uint64_t data,
1487 unsigned size,
1488 MemTxAttrs attrs)
a621f38d 1489{
897fa7cf 1490 if (!memory_region_access_valid(mr, addr, size, true)) {
b018ddf6 1491 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1492 return MEMTX_DECODE_ERROR;
093bc2cd
AK		 1493 }
1494
a621f38d
AK		 1495 adjust_endianness(mr, &data, size);
1496
8c56c1a5
PF		 1497 if ((!kvm_eventfds_enabled()) &&
1498 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1499 return MEMTX_OK;
1500 }
1501
ce5d2f33 1502 if (mr->ops->write) {
cc05c43a
PM		 1503 return access_with_adjusted_size(addr, &data, size,
1504 mr->ops->impl.min_access_size,
1505 mr->ops->impl.max_access_size,
1506 memory_region_write_accessor, mr,
1507 attrs);
1508 } else if (mr->ops->write_with_attrs) {
1509 return
1510 access_with_adjusted_size(addr, &data, size,
1511 mr->ops->impl.min_access_size,
1512 mr->ops->impl.max_access_size,
1513 memory_region_write_with_attrs_accessor,
1514 mr, attrs);
ce5d2f33 1515 } else {
cc05c43a
PM		 1516 return access_with_adjusted_size(addr, &data, size, 1, 4,
1517 memory_region_oldmmio_write_accessor,
1518 mr, attrs);
74901c3b 1519 }
093bc2cd
AK		 1520}
1521
093bc2cd 1522void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1523 Object *owner,
093bc2cd
AK		 1524 const MemoryRegionOps *ops,
1525 void *opaque,
1526 const char *name,
1527 uint64_t size)
1528{
2c9b15ca 1529 memory_region_init(mr, owner, name, size);
6d6d2abf 1530 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1531 mr->opaque = opaque;
14a3c10a 1532 mr->terminates = true;
093bc2cd
AK		 1533}
1534
1cfe48c1
PM		 1535void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1536 Object *owner,
1537 const char *name,
1538 uint64_t size,
1539 Error **errp)
093bc2cd 1540{
2c9b15ca 1541 memory_region_init(mr, owner, name, size);
8ea9252a 1542 mr->ram = true;
14a3c10a 1543 mr->terminates = true;
545e92e0 1544 mr->destructor = memory_region_destructor_ram;
8e41fb63 1545 mr->ram_block = qemu_ram_alloc(size, mr, errp);
677e7805 1546 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
0b183fc8
PB		 1547}
1548
60786ef3
MT		 1549void memory_region_init_resizeable_ram(MemoryRegion *mr,
1550 Object *owner,
1551 const char *name,
1552 uint64_t size,
1553 uint64_t max_size,
1554 void (*resized)(const char*,
1555 uint64_t length,
1556 void *host),
1557 Error **errp)
1558{
1559 memory_region_init(mr, owner, name, size);
1560 mr->ram = true;
1561 mr->terminates = true;
1562 mr->destructor = memory_region_destructor_ram;
8e41fb63
FZ		 1563 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1564 mr, errp);
677e7805 1565 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
60786ef3
MT		 1566}
1567
0b183fc8
PB		 1568#ifdef __linux__
1569void memory_region_init_ram_from_file(MemoryRegion *mr,
1570 struct Object *owner,
1571 const char *name,
1572 uint64_t size,
98376843 1573 uint64_t align,
dbcb8981 1574 bool share,
7f56e740
PB		 1575 const char *path,
1576 Error **errp)
0b183fc8
PB		 1577{
1578 memory_region_init(mr, owner, name, size);
1579 mr->ram = true;
1580 mr->terminates = true;
1581 mr->destructor = memory_region_destructor_ram;
98376843 1582 mr->align = align;
8e41fb63 1583 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
677e7805 1584 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
093bc2cd 1585}
fea617c5
MAL		 1586
1587void memory_region_init_ram_from_fd(MemoryRegion *mr,
1588 struct Object *owner,
1589 const char *name,
1590 uint64_t size,
1591 bool share,
1592 int fd,
1593 Error **errp)
1594{
1595 memory_region_init(mr, owner, name, size);
1596 mr->ram = true;
1597 mr->terminates = true;
1598 mr->destructor = memory_region_destructor_ram;
1599 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1600 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1601}
0b183fc8 1602#endif
093bc2cd
AK		 1603
1604void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1605 Object *owner,
093bc2cd
AK		 1606 const char *name,
1607 uint64_t size,
1608 void *ptr)
1609{
2c9b15ca 1610 memory_region_init(mr, owner, name, size);
8ea9252a 1611 mr->ram = true;
14a3c10a 1612 mr->terminates = true;
fc3e7665 1613 mr->destructor = memory_region_destructor_ram;
677e7805 1614 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT		 1615
1616 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1617 assert(ptr != NULL);
8e41fb63 1618 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK		 1619}
1620
21e00fa5
AW		 1621void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1622 Object *owner,
1623 const char *name,
1624 uint64_t size,
1625 void *ptr)
e4dc3f59 1626{
21e00fa5
AW		 1627 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1628 mr->ram_device = true;
4a2e242b
AW		 1629 mr->ops = &ram_device_mem_ops;
1630 mr->opaque = mr;
e4dc3f59
ND		 1631}
1632
093bc2cd 1633void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1634 Object *owner,
093bc2cd
AK		 1635 const char *name,
1636 MemoryRegion *orig,
a8170e5e 1637 hwaddr offset,
093bc2cd
AK		 1638 uint64_t size)
1639{
2c9b15ca 1640 memory_region_init(mr, owner, name, size);
093bc2cd
AK		 1641 mr->alias = orig;
1642 mr->alias_offset = offset;
1643}
1644
b59821a9
PM		 1645void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1646 struct Object *owner,
1647 const char *name,
1648 uint64_t size,
1649 Error **errp)
a1777f7f
PM		 1650{
1651 memory_region_init(mr, owner, name, size);
1652 mr->ram = true;
1653 mr->readonly = true;
1654 mr->terminates = true;
1655 mr->destructor = memory_region_destructor_ram;
1656 mr->ram_block = qemu_ram_alloc(size, mr, errp);
1657 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1658}
1659
b59821a9
PM		 1660void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1661 Object *owner,
1662 const MemoryRegionOps *ops,
1663 void *opaque,
1664 const char *name,
1665 uint64_t size,
1666 Error **errp)
d0a9b5bc 1667{
39e0b03d 1668 assert(ops);
2c9b15ca 1669 memory_region_init(mr, owner, name, size);
7bc2b9cd 1670 mr->ops = ops;
75f5941c 1671 mr->opaque = opaque;
d0a9b5bc 1672 mr->terminates = true;
75c578dc 1673 mr->rom_device = true;
58268c8d 1674 mr->destructor = memory_region_destructor_ram;
8e41fb63 1675 mr->ram_block = qemu_ram_alloc(size, mr, errp);
d0a9b5bc
AK		 1676}
1677
1221a474
AK		 1678void memory_region_init_iommu(void *_iommu_mr,
1679 size_t instance_size,
1680 const char *mrtypename,
2c9b15ca 1681 Object *owner,
30951157
AK		 1682 const char *name,
1683 uint64_t size)
1684{
1221a474 1685 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK		 1686 struct MemoryRegion *mr;
1687
1221a474
AK		 1688 object_initialize(_iommu_mr, instance_size, mrtypename);
1689 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK		 1690 memory_region_do_init(mr, owner, name, size);
1691 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1692 mr->terminates = true; /* then re-forwards */
3df9d748
AK		 1693 QLIST_INIT(&iommu_mr->iommu_notify);
1694 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK		 1695}
1696
b4fefef9 1697static void memory_region_finalize(Object *obj)
093bc2cd 1698{
b4fefef9
PC		 1699 MemoryRegion *mr = MEMORY_REGION(obj);
1700
2e2b8eb7
PB		 1701 assert(!mr->container);
1702
1703 /* We know the region is not visible in any address space (it
1704 * does not have a container and cannot be a root either because
1705 * it has no references, so we can blindly clear mr->enabled.
1706 * memory_region_set_enabled instead could trigger a transaction
1707 * and cause an infinite loop.
1708 */
1709 mr->enabled = false;
1710 memory_region_transaction_begin();
1711 while (!QTAILQ_EMPTY(&mr->subregions)) {
1712 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1713 memory_region_del_subregion(mr, subregion);
1714 }
1715 memory_region_transaction_commit();
1716
545e92e0 1717 mr->destructor(mr);
093bc2cd 1718 memory_region_clear_coalescing(mr);
302fa283 1719 g_free((char *)mr->name);
7267c094 1720 g_free(mr->ioeventfds);
093bc2cd
AK		 1721}
1722
803c0816
PB		 1723Object *memory_region_owner(MemoryRegion *mr)
1724{
22a893e4
PB		 1725 Object *obj = OBJECT(mr);
1726 return obj->parent;
803c0816
PB		 1727}
1728
46637be2
PB		 1729void memory_region_ref(MemoryRegion *mr)
1730{
22a893e4
PB		 1731 /* MMIO callbacks most likely will access data that belongs
1732 * to the owner, hence the need to ref/unref the owner whenever
1733 * the memory region is in use.
1734 *
1735 * The memory region is a child of its owner. As long as the
1736 * owner doesn't call unparent itself on the memory region,
1737 * ref-ing the owner will also keep the memory region alive.
612263cf
PB		 1738 * Memory regions without an owner are supposed to never go away;
1739 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1740 */
612263cf
PB		 1741 if (mr && mr->owner) {
1742 object_ref(mr->owner);
46637be2
PB		 1743 }
1744}
1745
1746void memory_region_unref(MemoryRegion *mr)
1747{
612263cf
PB		 1748 if (mr && mr->owner) {
1749 object_unref(mr->owner);
46637be2
PB		 1750 }
1751}
1752
093bc2cd
AK		 1753uint64_t memory_region_size(MemoryRegion *mr)
1754{
08dafab4
AK		 1755 if (int128_eq(mr->size, int128_2_64())) {
1756 return UINT64_MAX;
1757 }
1758 return int128_get64(mr->size);
093bc2cd
AK		 1759}
1760
5d546d4b 1761const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1762{
d1dd32af
PC		 1763 if (!mr->name) {
1764 ((MemoryRegion *)mr)->name =
1765 object_get_canonical_path_component(OBJECT(mr));
1766 }
302fa283 1767 return mr->name;
8991c79b
AK		 1768}
1769
21e00fa5 1770bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1771{
21e00fa5 1772 return mr->ram_device;
e4dc3f59
ND		 1773}
1774
2d1a35be 1775uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1776{
6f6a5ef3 1777 uint8_t mask = mr->dirty_log_mask;
adaad61c 1778 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB		 1779 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1780 }
1781 return mask;
55043ba3
AK		 1782}
1783
2d1a35be
PB		 1784bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1785{
1786 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1787}
1788
3df9d748 1789static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
5bf3d319
PX		 1790{
1791 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1792 IOMMUNotifier *iommu_notifier;
1221a474 1793 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
5bf3d319 1794
3df9d748 1795 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX		 1796 flags |= iommu_notifier->notifier_flags;
1797 }
1798
1221a474
AK		 1799 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1800 imrc->notify_flag_changed(iommu_mr,
1801 iommu_mr->iommu_notify_flags,
1802 flags);
5bf3d319
PX		 1803 }
1804
3df9d748 1805 iommu_mr->iommu_notify_flags = flags;
5bf3d319
PX		 1806}
1807
cdb30812
PX		 1808void memory_region_register_iommu_notifier(MemoryRegion *mr,
1809 IOMMUNotifier *n)
06866575 1810{
3df9d748
AK		 1811 IOMMUMemoryRegion *iommu_mr;
1812
efcd38c5
JW		 1813 if (mr->alias) {
1814 memory_region_register_iommu_notifier(mr->alias, n);
1815 return;
1816 }
1817
cdb30812 1818 /* We need to register for at least one bitfield */
3df9d748 1819 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1820 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1821 assert(n->start <= n->end);
3df9d748
AK		 1822 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1823 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG		 1824}
1825
3df9d748 1826uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1827{
1221a474
AK		 1828 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1829
1830 if (imrc->get_min_page_size) {
1831 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK		 1832 }
1833 return TARGET_PAGE_SIZE;
1834}
1835
3df9d748 1836void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1837{
3df9d748 1838 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1839 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1840 hwaddr addr, granularity;
a788f227
DG		 1841 IOMMUTLBEntry iotlb;
1842
faa362e3 1843 /* If the IOMMU has its own replay callback, override */
1221a474
AK		 1844 if (imrc->replay) {
1845 imrc->replay(iommu_mr, n);
faa362e3
PX		 1846 return;
1847 }
1848
3df9d748 1849 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1850
a788f227 1851 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1221a474 1852 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE);
a788f227
DG		 1853 if (iotlb.perm != IOMMU_NONE) {
1854 n->notify(n, &iotlb);
1855 }
1856
1857 /* if (2^64 - MR size) < granularity, it's possible to get an
1858 * infinite loop here. This should catch such a wraparound */
1859 if ((addr + granularity) < addr) {
1860 break;
1861 }
1862 }
1863}
1864
3df9d748 1865void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
de472e4a
PX		 1866{
1867 IOMMUNotifier *notifier;
1868
3df9d748
AK		 1869 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1870 memory_region_iommu_replay(iommu_mr, notifier);
de472e4a
PX		 1871 }
1872}
1873
cdb30812
PX		 1874void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1875 IOMMUNotifier *n)
06866575 1876{
3df9d748
AK		 1877 IOMMUMemoryRegion *iommu_mr;
1878
efcd38c5
JW		 1879 if (mr->alias) {
1880 memory_region_unregister_iommu_notifier(mr->alias, n);
1881 return;
1882 }
cdb30812 1883 QLIST_REMOVE(n, node);
3df9d748
AK		 1884 iommu_mr = IOMMU_MEMORY_REGION(mr);
1885 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG		 1886}
1887
bd2bfa4c
PX		 1888void memory_region_notify_one(IOMMUNotifier *notifier,
1889 IOMMUTLBEntry *entry)
06866575 1890{
cdb30812
PX		 1891 IOMMUNotifierFlag request_flags;
1892
bd2bfa4c
PX		 1893 /*
1894 * Skip the notification if the notification does not overlap
1895 * with registered range.
1896 */
b021d1c0 1897 if (notifier->start > entry->iova + entry->addr_mask ||
bd2bfa4c
PX		 1898 notifier->end < entry->iova) {
1899 return;
1900 }
cdb30812 1901
bd2bfa4c 1902 if (entry->perm & IOMMU_RW) {
cdb30812
PX		 1903 request_flags = IOMMU_NOTIFIER_MAP;
1904 } else {
1905 request_flags = IOMMU_NOTIFIER_UNMAP;
1906 }
1907
bd2bfa4c
PX		 1908 if (notifier->notifier_flags & request_flags) {
1909 notifier->notify(notifier, entry);
1910 }
1911}
1912
3df9d748 1913void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
bd2bfa4c
PX		 1914 IOMMUTLBEntry entry)
1915{
1916 IOMMUNotifier *iommu_notifier;
1917
3df9d748 1918 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1919
3df9d748 1920 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
bd2bfa4c 1921 memory_region_notify_one(iommu_notifier, &entry);
cdb30812 1922 }
06866575
DG		 1923}
1924
f1334de6
AK		 1925int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1926 enum IOMMUMemoryRegionAttr attr,
1927 void *data)
1928{
1929 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1930
1931 if (!imrc->get_attr) {
1932 return -EINVAL;
1933 }
1934
1935 return imrc->get_attr(iommu_mr, attr, data);
1936}
1937
093bc2cd
AK		 1938void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1939{
5a583347 1940 uint8_t mask = 1 << client;
deb809ed 1941 uint8_t old_logging;
5a583347 1942
dbddac6d 1943 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB		 1944 old_logging = mr->vga_logging_count;
1945 mr->vga_logging_count += log ? 1 : -1;
1946 if (!!old_logging == !!mr->vga_logging_count) {
1947 return;
1948 }
1949
59023ef4 1950 memory_region_transaction_begin();
5a583347 1951 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1952 memory_region_update_pending |= mr->enabled;
59023ef4 1953 memory_region_transaction_commit();
093bc2cd
AK		 1954}
1955
a8170e5e
AK		 1956bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1957 hwaddr size, unsigned client)
093bc2cd 1958{
8e41fb63
FZ		 1959 assert(mr->ram_block);
1960 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1961 size, client);
093bc2cd
AK		 1962}
1963
a8170e5e
AK		 1964void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1965 hwaddr size)
093bc2cd 1966{
8e41fb63
FZ		 1967 assert(mr->ram_block);
1968 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1969 size,
58d2707e 1970 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK		 1971}
1972
6c279db8
JQ		 1973bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1974 hwaddr size, unsigned client)
1975{
8e41fb63
FZ		 1976 assert(mr->ram_block);
1977 return cpu_physical_memory_test_and_clear_dirty(
1978 memory_region_get_ram_addr(mr) + addr, size, client);
6c279db8
JQ		 1979}
1980
8deaf12c
GH		 1981DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
1982 hwaddr addr,
1983 hwaddr size,
1984 unsigned client)
1985{
1986 assert(mr->ram_block);
1987 return cpu_physical_memory_snapshot_and_clear_dirty(
1988 memory_region_get_ram_addr(mr) + addr, size, client);
1989}
1990
1991bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
1992 hwaddr addr, hwaddr size)
1993{
1994 assert(mr->ram_block);
1995 return cpu_physical_memory_snapshot_get_dirty(snap,
1996 memory_region_get_ram_addr(mr) + addr, size);
1997}
6c279db8 1998
093bc2cd
AK		 1999void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
2000{
0a752eee 2001 MemoryListener *listener;
0d673e36 2002 AddressSpace *as;
0a752eee 2003 FlatView *view;
5a583347
AK		 2004 FlatRange *fr;
2005
0a752eee
PB		 2006 /* If the same address space has multiple log_sync listeners, we
2007 * visit that address space's FlatView multiple times. But because
2008 * log_sync listeners are rare, it's still cheaper than walking each
2009 * address space once.
2010 */
2011 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2012 if (!listener->log_sync) {
2013 continue;
2014 }
2015 as = listener->address_space;
2016 view = address_space_get_flatview(as);
99e86347 2017 FOR_EACH_FLAT_RANGE(fr, view) {
0d673e36 2018 if (fr->mr == mr) {
16620684 2019 MemoryRegionSection mrs = section_from_flat_range(fr, view);
0a752eee 2020 listener->log_sync(listener, &mrs);
0d673e36 2021 }
5a583347 2022 }
856d7245 2023 flatview_unref(view);
5a583347 2024 }
093bc2cd
AK		 2025}
2026
2027void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2028{
fb1cd6f9 2029 if (mr->readonly != readonly) {
59023ef4 2030 memory_region_transaction_begin();
fb1cd6f9 2031 mr->readonly = readonly;
22bde714 2032 memory_region_update_pending |= mr->enabled;
59023ef4 2033 memory_region_transaction_commit();
fb1cd6f9 2034 }
093bc2cd
AK		 2035}
2036
5f9a5ea1 2037void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 2038{
5f9a5ea1 2039 if (mr->romd_mode != romd_mode) {
59023ef4 2040 memory_region_transaction_begin();
5f9a5ea1 2041 mr->romd_mode = romd_mode;
22bde714 2042 memory_region_update_pending |= mr->enabled;
59023ef4 2043 memory_region_transaction_commit();
d0a9b5bc
AK		 2044 }
2045}
2046
a8170e5e
AK		 2047void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2048 hwaddr size, unsigned client)
093bc2cd 2049{
8e41fb63
FZ		 2050 assert(mr->ram_block);
2051 cpu_physical_memory_test_and_clear_dirty(
2052 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK		 2053}
2054
a35ba7be
PB		 2055int memory_region_get_fd(MemoryRegion *mr)
2056{
4ff87573
PB		 2057 int fd;
2058
2059 rcu_read_lock();
2060 while (mr->alias) {
2061 mr = mr->alias;
a35ba7be 2062 }
4ff87573
PB		 2063 fd = mr->ram_block->fd;
2064 rcu_read_unlock();
a35ba7be 2065
4ff87573
PB		 2066 return fd;
2067}
a35ba7be 2068
093bc2cd
AK		 2069void *memory_region_get_ram_ptr(MemoryRegion *mr)
2070{
49b24afc
PB		 2071 void *ptr;
2072 uint64_t offset = 0;
093bc2cd 2073
49b24afc
PB		 2074 rcu_read_lock();
2075 while (mr->alias) {
2076 offset += mr->alias_offset;
2077 mr = mr->alias;
2078 }
8e41fb63 2079 assert(mr->ram_block);
0878d0e1 2080 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
49b24afc 2081 rcu_read_unlock();
093bc2cd 2082
0878d0e1 2083 return ptr;
093bc2cd
AK		 2084}
2085
07bdaa41
PB		 2086MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2087{
2088 RAMBlock *block;
2089
2090 block = qemu_ram_block_from_host(ptr, false, offset);
2091 if (!block) {
2092 return NULL;
2093 }
2094
2095 return block->mr;
2096}
2097
7ebb2745
FZ		 2098ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2099{
2100 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2101}
2102
37d7c084
PB		 2103void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2104{
8e41fb63 2105 assert(mr->ram_block);
37d7c084 2106
fa53a0e5 2107 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB		 2108}
2109
0d673e36 2110static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 2111{
99e86347 2112 FlatView *view;
093bc2cd
AK		 2113 FlatRange *fr;
2114 CoalescedMemoryRange *cmr;
2115 AddrRange tmp;
95d2994a 2116 MemoryRegionSection section;
093bc2cd 2117
856d7245 2118 view = address_space_get_flatview(as);
99e86347 2119 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 2120 if (fr->mr == mr) {
95d2994a 2121 section = (MemoryRegionSection) {
16620684 2122 .fv = view,
95d2994a 2123 .offset_within_address_space = int128_get64(fr->addr.start),
052e87b0 2124 .size = fr->addr.size,
95d2994a
AK		 2125 };
2126
9a54635d 2127 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
95d2994a
AK		 2128 int128_get64(fr->addr.start),
2129 int128_get64(fr->addr.size));
093bc2cd
AK		 2130 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
2131 tmp = addrrange_shift(cmr->addr,
08dafab4
AK		 2132 int128_sub(fr->addr.start,
2133 int128_make64(fr->offset_in_region)));
093bc2cd
AK		 2134 if (!addrrange_intersects(tmp, fr->addr)) {
2135 continue;
2136 }
2137 tmp = addrrange_intersection(tmp, fr->addr);
9a54635d 2138 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
95d2994a
AK		 2139 int128_get64(tmp.start),
2140 int128_get64(tmp.size));
093bc2cd
AK		 2141 }
2142 }
2143 }
856d7245 2144 flatview_unref(view);
093bc2cd
AK		 2145}
2146
0d673e36
AK		 2147static void memory_region_update_coalesced_range(MemoryRegion *mr)
2148{
2149 AddressSpace *as;
2150
2151 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2152 memory_region_update_coalesced_range_as(mr, as);
2153 }
2154}
2155
093bc2cd
AK		 2156void memory_region_set_coalescing(MemoryRegion *mr)
2157{
2158 memory_region_clear_coalescing(mr);
08dafab4 2159 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK		 2160}
2161
2162void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 2163 hwaddr offset,
093bc2cd
AK		 2164 uint64_t size)
2165{
7267c094 2166 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2167
08dafab4 2168 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK		 2169 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2170 memory_region_update_coalesced_range(mr);
d410515e 2171 memory_region_set_flush_coalesced(mr);
093bc2cd
AK		 2172}
2173
2174void memory_region_clear_coalescing(MemoryRegion *mr)
2175{
2176 CoalescedMemoryRange *cmr;
ab5b3db5 2177 bool updated = false;
093bc2cd 2178
d410515e
JK		 2179 qemu_flush_coalesced_mmio_buffer();
2180 mr->flush_coalesced_mmio = false;
2181
093bc2cd
AK		 2182 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2183 cmr = QTAILQ_FIRST(&mr->coalesced);
2184 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 2185 g_free(cmr);
ab5b3db5
FZ		 2186 updated = true;
2187 }
2188
2189 if (updated) {
2190 memory_region_update_coalesced_range(mr);
093bc2cd 2191 }
093bc2cd
AK		 2192}
2193
d410515e
JK		 2194void memory_region_set_flush_coalesced(MemoryRegion *mr)
2195{
2196 mr->flush_coalesced_mmio = true;
2197}
2198
2199void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2200{
2201 qemu_flush_coalesced_mmio_buffer();
2202 if (QTAILQ_EMPTY(&mr->coalesced)) {
2203 mr->flush_coalesced_mmio = false;
2204 }
2205}
2206
196ea131
JK		 2207void memory_region_clear_global_locking(MemoryRegion *mr)
2208{
2209 mr->global_locking = false;
2210}
2211
8c56c1a5
PF		 2212static bool userspace_eventfd_warning;
2213
3e9d69e7 2214void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2215 hwaddr addr,
3e9d69e7
AK		 2216 unsigned size,
2217 bool match_data,
2218 uint64_t data,
753d5e14 2219 EventNotifier *e)
3e9d69e7
AK		 2220{
2221 MemoryRegionIoeventfd mrfd = {
08dafab4
AK		 2222 .addr.start = int128_make64(addr),
2223 .addr.size = int128_make64(size),
3e9d69e7
AK		 2224 .match_data = match_data,
2225 .data = data,
753d5e14 2226 .e = e,
3e9d69e7
AK		 2227 };
2228 unsigned i;
2229
8c56c1a5
PF		 2230 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2231 userspace_eventfd_warning))) {
2232 userspace_eventfd_warning = true;
2233 error_report("Using eventfd without MMIO binding in KVM. "
2234 "Suboptimal performance expected");
2235 }
2236
b8aecea2
JW		 2237 if (size) {
2238 adjust_endianness(mr, &mrfd.data, size);
2239 }
59023ef4 2240 memory_region_transaction_begin();
3e9d69e7
AK		 2241 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2242 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
2243 break;
2244 }
2245 }
2246 ++mr->ioeventfd_nb;
7267c094 2247 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK		 2248 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2249 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2250 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2251 mr->ioeventfds[i] = mrfd;
4dc56152 2252 ioeventfd_update_pending |= mr->enabled;
59023ef4 2253 memory_region_transaction_commit();
3e9d69e7
AK		 2254}
2255
2256void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2257 hwaddr addr,
3e9d69e7
AK		 2258 unsigned size,
2259 bool match_data,
2260 uint64_t data,
753d5e14 2261 EventNotifier *e)
3e9d69e7
AK		 2262{
2263 MemoryRegionIoeventfd mrfd = {
08dafab4
AK		 2264 .addr.start = int128_make64(addr),
2265 .addr.size = int128_make64(size),
3e9d69e7
AK		 2266 .match_data = match_data,
2267 .data = data,
753d5e14 2268 .e = e,
3e9d69e7
AK		 2269 };
2270 unsigned i;
2271
b8aecea2
JW		 2272 if (size) {
2273 adjust_endianness(mr, &mrfd.data, size);
2274 }
59023ef4 2275 memory_region_transaction_begin();
3e9d69e7
AK		 2276 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2277 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
2278 break;
2279 }
2280 }
2281 assert(i != mr->ioeventfd_nb);
2282 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2283 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2284 --mr->ioeventfd_nb;
7267c094 2285 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2286 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2287 ioeventfd_update_pending |= mr->enabled;
59023ef4 2288 memory_region_transaction_commit();
3e9d69e7
AK		 2289}
2290
feca4ac1 2291static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2292{
feca4ac1 2293 MemoryRegion *mr = subregion->container;
093bc2cd
AK		 2294 MemoryRegion *other;
2295
59023ef4
JK		 2296 memory_region_transaction_begin();
2297
dfde4e6e 2298 memory_region_ref(subregion);
093bc2cd
AK		 2299 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2300 if (subregion->priority >= other->priority) {
2301 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2302 goto done;
2303 }
2304 }
2305 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2306done:
22bde714 2307 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2308 memory_region_transaction_commit();
093bc2cd
AK		 2309}
2310
0598701a
PC		 2311static void memory_region_add_subregion_common(MemoryRegion *mr,
2312 hwaddr offset,
2313 MemoryRegion *subregion)
2314{
feca4ac1
PB		 2315 assert(!subregion->container);
2316 subregion->container = mr;
0598701a 2317 subregion->addr = offset;
feca4ac1 2318 memory_region_update_container_subregions(subregion);
0598701a 2319}
093bc2cd
AK		 2320
2321void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2322 hwaddr offset,
093bc2cd
AK		 2323 MemoryRegion *subregion)
2324{
093bc2cd
AK		 2325 subregion->priority = 0;
2326 memory_region_add_subregion_common(mr, offset, subregion);
2327}
2328
2329void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2330 hwaddr offset,
093bc2cd 2331 MemoryRegion *subregion,
a1ff8ae0 2332 int priority)
093bc2cd 2333{
093bc2cd
AK		 2334 subregion->priority = priority;
2335 memory_region_add_subregion_common(mr, offset, subregion);
2336}
2337
2338void memory_region_del_subregion(MemoryRegion *mr,
2339 MemoryRegion *subregion)
2340{
59023ef4 2341 memory_region_transaction_begin();
feca4ac1
PB		 2342 assert(subregion->container == mr);
2343 subregion->container = NULL;
093bc2cd 2344 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2345 memory_region_unref(subregion);
22bde714 2346 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2347 memory_region_transaction_commit();
6bba19ba
AK		 2348}
2349
2350void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2351{
2352 if (enabled == mr->enabled) {
2353 return;
2354 }
59023ef4 2355 memory_region_transaction_begin();
6bba19ba 2356 mr->enabled = enabled;
22bde714 2357 memory_region_update_pending = true;
59023ef4 2358 memory_region_transaction_commit();
093bc2cd 2359}
1c0ffa58 2360
e7af4c67
MT		 2361void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2362{
2363 Int128 s = int128_make64(size);
2364
2365 if (size == UINT64_MAX) {
2366 s = int128_2_64();
2367 }
2368 if (int128_eq(s, mr->size)) {
2369 return;
2370 }
2371 memory_region_transaction_begin();
2372 mr->size = s;
2373 memory_region_update_pending = true;
2374 memory_region_transaction_commit();
2375}
2376
67891b8a 2377static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2378{
feca4ac1 2379 MemoryRegion *container = mr->container;
2282e1af 2380
feca4ac1 2381 if (container) {
67891b8a
PC		 2382 memory_region_transaction_begin();
2383 memory_region_ref(mr);
feca4ac1
PB		 2384 memory_region_del_subregion(container, mr);
2385 mr->container = container;
2386 memory_region_update_container_subregions(mr);
67891b8a
PC		 2387 memory_region_unref(mr);
2388 memory_region_transaction_commit();
2282e1af 2389 }
67891b8a 2390}
2282e1af 2391
67891b8a
PC		 2392void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2393{
2394 if (addr != mr->addr) {
2395 mr->addr = addr;
2396 memory_region_readd_subregion(mr);
2397 }
2282e1af
AK		 2398}
2399
a8170e5e 2400void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2401{
4703359e 2402 assert(mr->alias);
4703359e 2403
59023ef4 2404 if (offset == mr->alias_offset) {
4703359e
AK		 2405 return;
2406 }
2407
59023ef4
JK		 2408 memory_region_transaction_begin();
2409 mr->alias_offset = offset;
22bde714 2410 memory_region_update_pending |= mr->enabled;
59023ef4 2411 memory_region_transaction_commit();
4703359e
AK		 2412}
2413
a2b257d6
IM		 2414uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2415{
2416 return mr->align;
2417}
2418
e2177955
AK		 2419static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2420{
2421 const AddrRange *addr = addr_;
2422 const FlatRange *fr = fr_;
2423
2424 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2425 return -1;
2426 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2427 return 1;
2428 }
2429 return 0;
2430}
2431
99e86347 2432static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2433{
99e86347 2434 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK		 2435 sizeof(FlatRange), cmp_flatrange_addr);
2436}
2437
eed2bacf
IM		 2438bool memory_region_is_mapped(MemoryRegion *mr)
2439{
2440 return mr->container ? true : false;
2441}
2442
c6742b14
PB		 2443/* Same as memory_region_find, but it does not add a reference to the
2444 * returned region. It must be called from an RCU critical section.
2445 */
2446static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2447 hwaddr addr, uint64_t size)
e2177955 2448{
052e87b0 2449 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB		 2450 MemoryRegion *root;
2451 AddressSpace *as;
2452 AddrRange range;
99e86347 2453 FlatView *view;
73034e9e
PB		 2454 FlatRange *fr;
2455
2456 addr += mr->addr;
feca4ac1
PB		 2457 for (root = mr; root->container; ) {
2458 root = root->container;
73034e9e
PB		 2459 addr += root->addr;
2460 }
e2177955 2461
73034e9e 2462 as = memory_region_to_address_space(root);
eed2bacf
IM		 2463 if (!as) {
2464 return ret;
2465 }
73034e9e 2466 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2467
16620684 2468 view = address_space_to_flatview(as);
99e86347 2469 fr = flatview_lookup(view, range);
e2177955 2470 if (!fr) {
c6742b14 2471 return ret;
e2177955
AK		 2472 }
2473
99e86347 2474 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK		 2475 --fr;
2476 }
2477
2478 ret.mr = fr->mr;
16620684 2479 ret.fv = view;
e2177955
AK		 2480 range = addrrange_intersection(range, fr->addr);
2481 ret.offset_within_region = fr->offset_in_region;
2482 ret.offset_within_region += int128_get64(int128_sub(range.start,
2483 fr->addr.start));
052e87b0 2484 ret.size = range.size;
e2177955 2485 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2486 ret.readonly = fr->readonly;
c6742b14
PB		 2487 return ret;
2488}
2489
2490MemoryRegionSection memory_region_find(MemoryRegion *mr,
2491 hwaddr addr, uint64_t size)
2492{
2493 MemoryRegionSection ret;
2494 rcu_read_lock();
2495 ret = memory_region_find_rcu(mr, addr, size);
2496 if (ret.mr) {
2497 memory_region_ref(ret.mr);
2498 }
2b647668 2499 rcu_read_unlock();
e2177955
AK		 2500 return ret;
2501}
2502
c6742b14
PB		 2503bool memory_region_present(MemoryRegion *container, hwaddr addr)
2504{
2505 MemoryRegion *mr;
2506
2507 rcu_read_lock();
2508 mr = memory_region_find_rcu(container, addr, 1).mr;
2509 rcu_read_unlock();
2510 return mr && mr != container;
2511}
2512
9c1f8f44 2513void memory_global_dirty_log_sync(void)
86e775c6 2514{
9c1f8f44
PB		 2515 MemoryListener *listener;
2516 AddressSpace *as;
99e86347 2517 FlatView *view;
7664e80c
AK		 2518 FlatRange *fr;
2519
9c1f8f44
PB		 2520 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2521 if (!listener->log_sync) {
2522 continue;
2523 }
d45fa784 2524 as = listener->address_space;
9c1f8f44
PB		 2525 view = address_space_get_flatview(as);
2526 FOR_EACH_FLAT_RANGE(fr, view) {
adaad61c 2527 if (fr->dirty_log_mask) {
16620684
AK		 2528 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2529
adaad61c
PB		 2530 listener->log_sync(listener, &mrs);
2531 }
9c1f8f44
PB		 2532 }
2533 flatview_unref(view);
7664e80c
AK		 2534 }
2535}
2536
19310760
JZ		 2537static VMChangeStateEntry *vmstate_change;
2538
7664e80c
AK		 2539void memory_global_dirty_log_start(void)
2540{
19310760
JZ		 2541 if (vmstate_change) {
2542 qemu_del_vm_change_state_handler(vmstate_change);
2543 vmstate_change = NULL;
2544 }
2545
7664e80c 2546 global_dirty_log = true;
6f6a5ef3 2547
7376e582 2548 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3
PB		 2549
2550 /* Refresh DIRTY_LOG_MIGRATION bit. */
2551 memory_region_transaction_begin();
2552 memory_region_update_pending = true;
2553 memory_region_transaction_commit();
7664e80c
AK		 2554}
2555
19310760 2556static void memory_global_dirty_log_do_stop(void)
7664e80c 2557{
7664e80c 2558 global_dirty_log = false;
6f6a5ef3
PB		 2559
2560 /* Refresh DIRTY_LOG_MIGRATION bit. */
2561 memory_region_transaction_begin();
2562 memory_region_update_pending = true;
2563 memory_region_transaction_commit();
2564
7376e582 2565 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK		 2566}
2567
19310760
JZ		 2568static void memory_vm_change_state_handler(void *opaque, int running,
2569 RunState state)
2570{
2571 if (running) {
2572 memory_global_dirty_log_do_stop();
2573
2574 if (vmstate_change) {
2575 qemu_del_vm_change_state_handler(vmstate_change);
2576 vmstate_change = NULL;
2577 }
2578 }
2579}
2580
2581void memory_global_dirty_log_stop(void)
2582{
2583 if (!runstate_is_running()) {
2584 if (vmstate_change) {
2585 return;
2586 }
2587 vmstate_change = qemu_add_vm_change_state_handler(
2588 memory_vm_change_state_handler, NULL);
2589 return;
2590 }
2591
2592 memory_global_dirty_log_do_stop();
2593}
2594
7664e80c
AK		 2595static void listener_add_address_space(MemoryListener *listener,
2596 AddressSpace *as)
2597{
99e86347 2598 FlatView *view;
7664e80c
AK		 2599 FlatRange *fr;
2600
680a4783
PB		 2601 if (listener->begin) {
2602 listener->begin(listener);
2603 }
7664e80c 2604 if (global_dirty_log) {
975aefe0
AK		 2605 if (listener->log_global_start) {
2606 listener->log_global_start(listener);
2607 }
7664e80c 2608 }
975aefe0 2609
856d7245 2610 view = address_space_get_flatview(as);
99e86347 2611 FOR_EACH_FLAT_RANGE(fr, view) {
279836f8
DH		 2612 MemoryRegionSection section = section_from_flat_range(fr, view);
2613
975aefe0
AK		 2614 if (listener->region_add) {
2615 listener->region_add(listener, &section);
2616 }
ae990e6c
DH		 2617 if (fr->dirty_log_mask && listener->log_start) {
2618 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2619 }
7664e80c 2620 }
680a4783
PB		 2621 if (listener->commit) {
2622 listener->commit(listener);
2623 }
856d7245 2624 flatview_unref(view);
7664e80c
AK		 2625}
2626
d45fa784 2627void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2628{
72e22d2f
AK		 2629 MemoryListener *other = NULL;
2630
d45fa784 2631 listener->address_space = as;
72e22d2f
AK		 2632 if (QTAILQ_EMPTY(&memory_listeners)
2633 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2634 memory_listeners)->priority) {
2635 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2636 } else {
2637 QTAILQ_FOREACH(other, &memory_listeners, link) {
2638 if (listener->priority < other->priority) {
2639 break;
2640 }
2641 }
2642 QTAILQ_INSERT_BEFORE(other, listener, link);
2643 }
0d673e36 2644
9a54635d
PB		 2645 if (QTAILQ_EMPTY(&as->listeners)
2646 || listener->priority >= QTAILQ_LAST(&as->listeners,
2647 memory_listeners)->priority) {
2648 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2649 } else {
2650 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2651 if (listener->priority < other->priority) {
2652 break;
2653 }
2654 }
2655 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2656 }
2657
d45fa784 2658 listener_add_address_space(listener, as);
7664e80c
AK		 2659}
2660
2661void memory_listener_unregister(MemoryListener *listener)
2662{
1d8280c1
PB		 2663 if (!listener->address_space) {
2664 return;
2665 }
2666
72e22d2f 2667 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2668 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2669 listener->address_space = NULL;
86e775c6 2670}
e2177955 2671
c9356746
FK		 2672bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2673{
2674 void *host;
2675 unsigned size = 0;
2676 unsigned offset = 0;
2677 Object *new_interface;
2678
2679 if (!mr || !mr->ops->request_ptr) {
2680 return false;
2681 }
2682
2683 /*
2684 * Avoid an update if the request_ptr call
2685 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2686 * a cache.
2687 */
2688 memory_region_transaction_begin();
2689
2690 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2691
2692 if (!host || !size) {
2693 memory_region_transaction_commit();
2694 return false;
2695 }
2696
2697 new_interface = object_new("mmio_interface");
2698 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2699 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2700 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2701 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2702 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2703 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2704
2705 memory_region_transaction_commit();
2706 return true;
2707}
2708
2709typedef struct MMIOPtrInvalidate {
2710 MemoryRegion *mr;
2711 hwaddr offset;
2712 unsigned size;
2713 int busy;
2714 int allocated;
2715} MMIOPtrInvalidate;
2716
2717#define MAX_MMIO_INVALIDATE 10
2718static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2719
2720static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2721 run_on_cpu_data data)
2722{
2723 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2724 MemoryRegion *mr = invalidate_data->mr;
2725 hwaddr offset = invalidate_data->offset;
2726 unsigned size = invalidate_data->size;
2727 MemoryRegionSection section = memory_region_find(mr, offset, size);
2728
2729 qemu_mutex_lock_iothread();
2730
2731 /* Reset dirty so this doesn't happen later. */
2732 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2733
2734 if (section.mr != mr) {
2735 /* memory_region_find add a ref on section.mr */
2736 memory_region_unref(section.mr);
2737 if (MMIO_INTERFACE(section.mr->owner)) {
2738 /* We found the interface just drop it. */
2739 object_property_set_bool(section.mr->owner, false, "realized",
2740 NULL);
2741 object_unref(section.mr->owner);
2742 object_unparent(section.mr->owner);
2743 }
2744 }
2745
2746 qemu_mutex_unlock_iothread();
2747
2748 if (invalidate_data->allocated) {
2749 g_free(invalidate_data);
2750 } else {
2751 invalidate_data->busy = 0;
2752 }
2753}
2754
2755void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2756 unsigned size)
2757{
2758 size_t i;
2759 MMIOPtrInvalidate *invalidate_data = NULL;
2760
2761 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2762 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2763 invalidate_data = &mmio_ptr_invalidate_list[i];
2764 break;
2765 }
2766 }
2767
2768 if (!invalidate_data) {
2769 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2770 invalidate_data->allocated = 1;
2771 }
2772
2773 invalidate_data->mr = mr;
2774 invalidate_data->offset = offset;
2775 invalidate_data->size = size;
2776
2777 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2778 RUN_ON_CPU_HOST_PTR(invalidate_data));
2779}
2780
7dca8043 2781void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2782{
ac95190e 2783 memory_region_ref(root);
8786db7c 2784 as->root = root;
67ace39b 2785 as->current_map = NULL;
4c19eb72
AK		 2786 as->ioeventfd_nb = 0;
2787 as->ioeventfds = NULL;
9a54635d 2788 QTAILQ_INIT(&as->listeners);
0d673e36 2789 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2790 as->name = g_strdup(name ? name : "anonymous");
202fc01b
AK		 2791 address_space_update_topology(as);
2792 address_space_update_ioeventfds(as);
1c0ffa58 2793}
658b2224 2794
374f2981 2795static void do_address_space_destroy(AddressSpace *as)
83f3c251 2796{
9a54635d 2797 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2798
856d7245 2799 flatview_unref(as->current_map);
7dca8043 2800 g_free(as->name);
4c19eb72 2801 g_free(as->ioeventfds);
ac95190e 2802 memory_region_unref(as->root);
83f3c251
AK		 2803}
2804
374f2981
PB		 2805void address_space_destroy(AddressSpace *as)
2806{
ac95190e
PB		 2807 MemoryRegion *root = as->root;
2808
374f2981
PB		 2809 /* Flush out anything from MemoryListeners listening in on this */
2810 memory_region_transaction_begin();
2811 as->root = NULL;
2812 memory_region_transaction_commit();
2813 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2814
2815 /* At this point, as->dispatch and as->current_map are dummy
2816 * entries that the guest should never use. Wait for the old
2817 * values to expire before freeing the data.
2818 */
ac95190e 2819 as->root = root;
374f2981
PB		 2820 call_rcu(as, do_address_space_destroy, rcu);
2821}
2822
4e831901
PX		 2823static const char *memory_region_type(MemoryRegion *mr)
2824{
2825 if (memory_region_is_ram_device(mr)) {
2826 return "ramd";
2827 } else if (memory_region_is_romd(mr)) {
2828 return "romd";
2829 } else if (memory_region_is_rom(mr)) {
2830 return "rom";
2831 } else if (memory_region_is_ram(mr)) {
2832 return "ram";
2833 } else {
2834 return "i/o";
2835 }
2836}
2837
314e2987
BS		 2838typedef struct MemoryRegionList MemoryRegionList;
2839
2840struct MemoryRegionList {
2841 const MemoryRegion *mr;
a16878d2 2842 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS		 2843};
2844
a16878d2 2845typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
314e2987 2846
4e831901
PX		 2847#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2848 int128_sub((size), int128_one())) : 0)
2849#define MTREE_INDENT " "
2850
314e2987
BS		 2851static void mtree_print_mr(fprintf_function mon_printf, void *f,
2852 const MemoryRegion *mr, unsigned int level,
a8170e5e 2853 hwaddr base,
9479c57a 2854 MemoryRegionListHead *alias_print_queue)
314e2987 2855{
9479c57a
JK		 2856 MemoryRegionList *new_ml, *ml, *next_ml;
2857 MemoryRegionListHead submr_print_queue;
314e2987
BS		 2858 const MemoryRegion *submr;
2859 unsigned int i;
b31f8412 2860 hwaddr cur_start, cur_end;
314e2987 2861
f8a9f720 2862 if (!mr) {
314e2987
BS		 2863 return;
2864 }
2865
2866 for (i = 0; i < level; i++) {
4e831901 2867 mon_printf(f, MTREE_INDENT);
314e2987
BS		 2868 }
2869
b31f8412
PX		 2870 cur_start = base + mr->addr;
2871 cur_end = cur_start + MR_SIZE(mr->size);
2872
2873 /*
2874 * Try to detect overflow of memory region. This should never
2875 * happen normally. When it happens, we dump something to warn the
2876 * user who is observing this.
2877 */
2878 if (cur_start < base || cur_end < cur_start) {
2879 mon_printf(f, "[DETECTED OVERFLOW!] ");
2880 }
2881
314e2987
BS		 2882 if (mr->alias) {
2883 MemoryRegionList *ml;
2884 bool found = false;
2885
2886 /* check if the alias is already in the queue */
a16878d2 2887 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2888 if (ml->mr == mr->alias) {
314e2987
BS		 2889 found = true;
2890 }
2891 }
2892
2893 if (!found) {
2894 ml = g_new(MemoryRegionList, 1);
2895 ml->mr = mr->alias;
a16878d2 2896 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2897 }
4896d74b 2898 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
4e831901 2899 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
f8a9f720 2900 "-" TARGET_FMT_plx "%s\n",
b31f8412 2901 cur_start, cur_end,
4b474ba7 2902 mr->priority,
4e831901 2903 memory_region_type((MemoryRegion *)mr),
3fb18b4d
PC		 2904 memory_region_name(mr),
2905 memory_region_name(mr->alias),
314e2987 2906 mr->alias_offset,
4e831901 2907 mr->alias_offset + MR_SIZE(mr->size),
f8a9f720 2908 mr->enabled ? "" : " [disabled]");
314e2987 2909 } else {
4896d74b 2910 mon_printf(f,
4e831901 2911 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
b31f8412 2912 cur_start, cur_end,
4b474ba7 2913 mr->priority,
4e831901 2914 memory_region_type((MemoryRegion *)mr),
f8a9f720
GH		 2915 memory_region_name(mr),
2916 mr->enabled ? "" : " [disabled]");
314e2987 2917 }
9479c57a
JK		 2918
2919 QTAILQ_INIT(&submr_print_queue);
2920
314e2987 2921 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK		 2922 new_ml = g_new(MemoryRegionList, 1);
2923 new_ml->mr = submr;
a16878d2 2924 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK		 2925 if (new_ml->mr->addr < ml->mr->addr ||
2926 (new_ml->mr->addr == ml->mr->addr &&
2927 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 2928 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK		 2929 new_ml = NULL;
2930 break;
2931 }
2932 }
2933 if (new_ml) {
a16878d2 2934 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK		 2935 }
2936 }
2937
a16878d2 2938 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b31f8412 2939 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
9479c57a
JK		 2940 alias_print_queue);
2941 }
2942
a16878d2 2943 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 2944 g_free(ml);
314e2987
BS		 2945 }
2946}
2947
5e8fd947
AK		 2948struct FlatViewInfo {
2949 fprintf_function mon_printf;
2950 void *f;
2951 int counter;
2952 bool dispatch_tree;
2953};
2954
2955static void mtree_print_flatview(gpointer key, gpointer value,
2956 gpointer user_data)
57bb40c9 2957{
5e8fd947
AK		 2958 FlatView *view = key;
2959 GArray *fv_address_spaces = value;
2960 struct FlatViewInfo *fvi = user_data;
2961 fprintf_function p = fvi->mon_printf;
2962 void *f = fvi->f;
57bb40c9
PX		 2963 FlatRange *range = &view->ranges[0];
2964 MemoryRegion *mr;
2965 int n = view->nr;
5e8fd947
AK		 2966 int i;
2967 AddressSpace *as;
2968
2969 p(f, "FlatView #%d\n", fvi->counter);
2970 ++fvi->counter;
2971
2972 for (i = 0; i < fv_address_spaces->len; ++i) {
2973 as = g_array_index(fv_address_spaces, AddressSpace*, i);
2974 p(f, " AS \"%s\", root: %s", as->name, memory_region_name(as->root));
2975 if (as->root->alias) {
2976 p(f, ", alias %s", memory_region_name(as->root->alias));
2977 }
2978 p(f, "\n");
2979 }
2980
2981 p(f, " Root memory region: %s\n",
2982 view->root ? memory_region_name(view->root) : "(none)");
57bb40c9
PX		 2983
2984 if (n <= 0) {
5e8fd947 2985 p(f, MTREE_INDENT "No rendered FlatView\n\n");
57bb40c9
PX		 2986 return;
2987 }
2988
2989 while (n--) {
2990 mr = range->mr;
377a07aa
PB		 2991 if (range->offset_in_region) {
2992 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2993 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
2994 int128_get64(range->addr.start),
2995 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2996 mr->priority,
2997 range->readonly ? "rom" : memory_region_type(mr),
2998 memory_region_name(mr),
2999 range->offset_in_region);
3000 } else {
3001 p(f, MTREE_INDENT TARGET_FMT_plx "-"
3002 TARGET_FMT_plx " (prio %d, %s): %s\n",
3003 int128_get64(range->addr.start),
3004 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
3005 mr->priority,
3006 range->readonly ? "rom" : memory_region_type(mr),
3007 memory_region_name(mr));
3008 }
57bb40c9
PX		 3009 range++;
3010 }
3011
5e8fd947
AK		 3012#if !defined(CONFIG_USER_ONLY)
3013 if (fvi->dispatch_tree && view->root) {
3014 mtree_print_dispatch(p, f, view->dispatch, view->root);
3015 }
3016#endif
3017
3018 p(f, "\n");
3019}
3020
3021static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3022 gpointer user_data)
3023{
3024 FlatView *view = key;
3025 GArray *fv_address_spaces = value;
3026
3027 g_array_unref(fv_address_spaces);
57bb40c9 3028 flatview_unref(view);
5e8fd947
AK		 3029
3030 return true;
57bb40c9
PX		 3031}
3032
5e8fd947
AK		 3033void mtree_info(fprintf_function mon_printf, void *f, bool flatview,
3034 bool dispatch_tree)
314e2987
BS		 3035{
3036 MemoryRegionListHead ml_head;
3037 MemoryRegionList *ml, *ml2;
0d673e36 3038 AddressSpace *as;
314e2987 3039
57bb40c9 3040 if (flatview) {
5e8fd947
AK		 3041 FlatView *view;
3042 struct FlatViewInfo fvi = {
3043 .mon_printf = mon_printf,
3044 .f = f,
3045 .counter = 0,
3046 .dispatch_tree = dispatch_tree
3047 };
3048 GArray *fv_address_spaces;
3049 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3050
3051 /* Gather all FVs in one table */
57bb40c9 3052 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
5e8fd947
AK		 3053 view = address_space_get_flatview(as);
3054
3055 fv_address_spaces = g_hash_table_lookup(views, view);
3056 if (!fv_address_spaces) {
3057 fv_address_spaces = g_array_new(false, false, sizeof(as));
3058 g_hash_table_insert(views, view, fv_address_spaces);
3059 }
3060
3061 g_array_append_val(fv_address_spaces, as);
57bb40c9 3062 }
5e8fd947
AK		 3063
3064 /* Print */
3065 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3066
3067 /* Free */
3068 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3069 g_hash_table_unref(views);
3070
57bb40c9
PX		 3071 return;
3072 }
3073
314e2987
BS		 3074 QTAILQ_INIT(&ml_head);
3075
0d673e36 3076 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
e48816aa
GH		 3077 mon_printf(f, "address-space: %s\n", as->name);
3078 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
3079 mon_printf(f, "\n");
b9f9be88
BS		 3080 }
3081
314e2987 3082 /* print aliased regions */
a16878d2 3083 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
e48816aa
GH		 3084 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
3085 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
3086 mon_printf(f, "\n");
314e2987
BS		 3087 }
3088
a16878d2 3089 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 3090 g_free(ml);
314e2987 3091 }
314e2987 3092}
b4fefef9 3093
b08199c6
PM		 3094void memory_region_init_ram(MemoryRegion *mr,
3095 struct Object *owner,
3096 const char *name,
3097 uint64_t size,
3098 Error **errp)
3099{
3100 DeviceState *owner_dev;
3101 Error *err = NULL;
3102
3103 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3104 if (err) {
3105 error_propagate(errp, err);
3106 return;
3107 }
3108 /* This will assert if owner is neither NULL nor a DeviceState.
3109 * We only want the owner here for the purposes of defining a
3110 * unique name for migration. TODO: Ideally we should implement
3111 * a naming scheme for Objects which are not DeviceStates, in
3112 * which case we can relax this restriction.
3113 */
3114 owner_dev = DEVICE(owner);
3115 vmstate_register_ram(mr, owner_dev);
3116}
3117
3118void memory_region_init_rom(MemoryRegion *mr,
3119 struct Object *owner,
3120 const char *name,
3121 uint64_t size,
3122 Error **errp)
3123{
3124 DeviceState *owner_dev;
3125 Error *err = NULL;
3126
3127 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3128 if (err) {
3129 error_propagate(errp, err);
3130 return;
3131 }
3132 /* This will assert if owner is neither NULL nor a DeviceState.
3133 * We only want the owner here for the purposes of defining a
3134 * unique name for migration. TODO: Ideally we should implement
3135 * a naming scheme for Objects which are not DeviceStates, in
3136 * which case we can relax this restriction.
3137 */
3138 owner_dev = DEVICE(owner);
3139 vmstate_register_ram(mr, owner_dev);
3140}
3141
3142void memory_region_init_rom_device(MemoryRegion *mr,
3143 struct Object *owner,
3144 const MemoryRegionOps *ops,
3145 void *opaque,
3146 const char *name,
3147 uint64_t size,
3148 Error **errp)
3149{
3150 DeviceState *owner_dev;
3151 Error *err = NULL;
3152
3153 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3154 name, size, &err);
3155 if (err) {
3156 error_propagate(errp, err);
3157 return;
3158 }
3159 /* This will assert if owner is neither NULL nor a DeviceState.
3160 * We only want the owner here for the purposes of defining a
3161 * unique name for migration. TODO: Ideally we should implement
3162 * a naming scheme for Objects which are not DeviceStates, in
3163 * which case we can relax this restriction.
3164 */
3165 owner_dev = DEVICE(owner);
3166 vmstate_register_ram(mr, owner_dev);
3167}
3168
b4fefef9
PC		 3169static const TypeInfo memory_region_info = {
3170 .parent = TYPE_OBJECT,
3171 .name = TYPE_MEMORY_REGION,
3172 .instance_size = sizeof(MemoryRegion),
3173 .instance_init = memory_region_initfn,
3174 .instance_finalize = memory_region_finalize,
3175};
3176
3df9d748
AK		 3177static const TypeInfo iommu_memory_region_info = {
3178 .parent = TYPE_MEMORY_REGION,
3179 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 3180 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK		 3181 .instance_size = sizeof(IOMMUMemoryRegion),
3182 .instance_init = iommu_memory_region_initfn,
1221a474 3183 .abstract = true,
3df9d748
AK		 3184};
3185
b4fefef9
PC		 3186static void memory_register_types(void)
3187{
3188 type_register_static(&memory_region_info);
3df9d748 3189 type_register_static(&iommu_memory_region_info);
b4fefef9
PC		 3190}
3191
3192type_init(memory_register_types)
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