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i.MX: Fix Coding style for GPT emulator
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CommitLineData
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1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
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14 */
15
022c62cb
PB
16#include "exec/memory.h"
17#include "exec/address-spaces.h"
18#include "exec/ioport.h"
409ddd01 19#include "qapi/visitor.h"
1de7afc9 20#include "qemu/bitops.h"
2c9b15ca 21#include "qom/object.h"
55d5d048 22#include "trace.h"
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23#include <assert.h>
24
022c62cb 25#include "exec/memory-internal.h"
220c3ebd 26#include "exec/ram_addr.h"
e1c57ab8 27#include "sysemu/sysemu.h"
67d95c15 28
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PB
29//#define DEBUG_UNASSIGNED
30
ec05ec26
PB
31#define RAM_ADDR_INVALID (~(ram_addr_t)0)
32
22bde714
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33static unsigned memory_region_transaction_depth;
34static bool memory_region_update_pending;
4dc56152 35static bool ioeventfd_update_pending;
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36static bool global_dirty_log = false;
37
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38static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
39 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 40
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41static QTAILQ_HEAD(, AddressSpace) address_spaces
42 = QTAILQ_HEAD_INITIALIZER(address_spaces);
43
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44typedef struct AddrRange AddrRange;
45
8417cebf 46/*
c9cdaa3a 47 * Note that signed integers are needed for negative offsetting in aliases
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48 * (large MemoryRegion::alias_offset).
49 */
093bc2cd 50struct AddrRange {
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51 Int128 start;
52 Int128 size;
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53};
54
08dafab4 55static AddrRange addrrange_make(Int128 start, Int128 size)
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56{
57 return (AddrRange) { start, size };
58}
59
60static bool addrrange_equal(AddrRange r1, AddrRange r2)
61{
08dafab4 62 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
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63}
64
08dafab4 65static Int128 addrrange_end(AddrRange r)
093bc2cd 66{
08dafab4 67 return int128_add(r.start, r.size);
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68}
69
08dafab4 70static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 71{
08dafab4 72 int128_addto(&range.start, delta);
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73 return range;
74}
75
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76static bool addrrange_contains(AddrRange range, Int128 addr)
77{
78 return int128_ge(addr, range.start)
79 && int128_lt(addr, addrrange_end(range));
80}
81
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82static bool addrrange_intersects(AddrRange r1, AddrRange r2)
83{
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84 return addrrange_contains(r1, r2.start)
85 || addrrange_contains(r2, r1.start);
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86}
87
88static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
89{
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90 Int128 start = int128_max(r1.start, r2.start);
91 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
92 return addrrange_make(start, int128_sub(end, start));
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93}
94
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95enum ListenerDirection { Forward, Reverse };
96
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97static bool memory_listener_match(MemoryListener *listener,
98 MemoryRegionSection *section)
99{
100 return !listener->address_space_filter
101 || listener->address_space_filter == section->address_space;
102}
103
104#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
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105 do { \
106 MemoryListener *_listener; \
107 \
108 switch (_direction) { \
109 case Forward: \
110 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
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111 if (_listener->_callback) { \
112 _listener->_callback(_listener, ##_args); \
113 } \
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114 } \
115 break; \
116 case Reverse: \
117 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
118 memory_listeners, link) { \
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119 if (_listener->_callback) { \
120 _listener->_callback(_listener, ##_args); \
121 } \
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122 } \
123 break; \
124 default: \
125 abort(); \
126 } \
127 } while (0)
128
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129#define MEMORY_LISTENER_CALL(_callback, _direction, _section, _args...) \
130 do { \
131 MemoryListener *_listener; \
132 \
133 switch (_direction) { \
134 case Forward: \
135 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
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136 if (_listener->_callback \
137 && memory_listener_match(_listener, _section)) { \
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138 _listener->_callback(_listener, _section, ##_args); \
139 } \
140 } \
141 break; \
142 case Reverse: \
143 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
144 memory_listeners, link) { \
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145 if (_listener->_callback \
146 && memory_listener_match(_listener, _section)) { \
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147 _listener->_callback(_listener, _section, ##_args); \
148 } \
149 } \
150 break; \
151 default: \
152 abort(); \
153 } \
154 } while (0)
155
dfde4e6e 156/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 157#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
7376e582 158 MEMORY_LISTENER_CALL(callback, dir, (&(MemoryRegionSection) { \
0e0d36b4 159 .mr = (fr)->mr, \
f6790af6 160 .address_space = (as), \
0e0d36b4 161 .offset_within_region = (fr)->offset_in_region, \
052e87b0 162 .size = (fr)->addr.size, \
0e0d36b4 163 .offset_within_address_space = int128_get64((fr)->addr.start), \
7a8499e8 164 .readonly = (fr)->readonly, \
b2dfd71c 165 }), ##_args)
0e0d36b4 166
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167struct CoalescedMemoryRange {
168 AddrRange addr;
169 QTAILQ_ENTRY(CoalescedMemoryRange) link;
170};
171
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172struct MemoryRegionIoeventfd {
173 AddrRange addr;
174 bool match_data;
175 uint64_t data;
753d5e14 176 EventNotifier *e;
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177};
178
179static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
180 MemoryRegionIoeventfd b)
181{
08dafab4 182 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 183 return true;
08dafab4 184 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 185 return false;
08dafab4 186 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 187 return true;
08dafab4 188 } else if (int128_gt(a.addr.size, b.addr.size)) {
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189 return false;
190 } else if (a.match_data < b.match_data) {
191 return true;
192 } else if (a.match_data > b.match_data) {
193 return false;
194 } else if (a.match_data) {
195 if (a.data < b.data) {
196 return true;
197 } else if (a.data > b.data) {
198 return false;
199 }
200 }
753d5e14 201 if (a.e < b.e) {
3e9d69e7 202 return true;
753d5e14 203 } else if (a.e > b.e) {
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204 return false;
205 }
206 return false;
207}
208
209static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
210 MemoryRegionIoeventfd b)
211{
212 return !memory_region_ioeventfd_before(a, b)
213 && !memory_region_ioeventfd_before(b, a);
214}
215
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216typedef struct FlatRange FlatRange;
217typedef struct FlatView FlatView;
218
219/* Range of memory in the global map. Addresses are absolute. */
220struct FlatRange {
221 MemoryRegion *mr;
a8170e5e 222 hwaddr offset_in_region;
093bc2cd 223 AddrRange addr;
5a583347 224 uint8_t dirty_log_mask;
5f9a5ea1 225 bool romd_mode;
fb1cd6f9 226 bool readonly;
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227};
228
229/* Flattened global view of current active memory hierarchy. Kept in sorted
230 * order.
231 */
232struct FlatView {
374f2981 233 struct rcu_head rcu;
856d7245 234 unsigned ref;
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235 FlatRange *ranges;
236 unsigned nr;
237 unsigned nr_allocated;
238};
239
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240typedef struct AddressSpaceOps AddressSpaceOps;
241
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242#define FOR_EACH_FLAT_RANGE(var, view) \
243 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
244
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245static bool flatrange_equal(FlatRange *a, FlatRange *b)
246{
247 return a->mr == b->mr
248 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 249 && a->offset_in_region == b->offset_in_region
5f9a5ea1 250 && a->romd_mode == b->romd_mode
fb1cd6f9 251 && a->readonly == b->readonly;
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252}
253
254static void flatview_init(FlatView *view)
255{
856d7245 256 view->ref = 1;
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257 view->ranges = NULL;
258 view->nr = 0;
259 view->nr_allocated = 0;
260}
261
262/* Insert a range into a given position. Caller is responsible for maintaining
263 * sorting order.
264 */
265static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
266{
267 if (view->nr == view->nr_allocated) {
268 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 269 view->ranges = g_realloc(view->ranges,
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270 view->nr_allocated * sizeof(*view->ranges));
271 }
272 memmove(view->ranges + pos + 1, view->ranges + pos,
273 (view->nr - pos) * sizeof(FlatRange));
274 view->ranges[pos] = *range;
dfde4e6e 275 memory_region_ref(range->mr);
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276 ++view->nr;
277}
278
279static void flatview_destroy(FlatView *view)
280{
dfde4e6e
PB
281 int i;
282
283 for (i = 0; i < view->nr; i++) {
284 memory_region_unref(view->ranges[i].mr);
285 }
7267c094 286 g_free(view->ranges);
a9a0c06d 287 g_free(view);
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288}
289
856d7245
PB
290static void flatview_ref(FlatView *view)
291{
292 atomic_inc(&view->ref);
293}
294
295static void flatview_unref(FlatView *view)
296{
297 if (atomic_fetch_dec(&view->ref) == 1) {
298 flatview_destroy(view);
299 }
300}
301
3d8e6bf9
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302static bool can_merge(FlatRange *r1, FlatRange *r2)
303{
08dafab4 304 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 305 && r1->mr == r2->mr
08dafab4
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306 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
307 r1->addr.size),
308 int128_make64(r2->offset_in_region))
d0a9b5bc 309 && r1->dirty_log_mask == r2->dirty_log_mask
5f9a5ea1 310 && r1->romd_mode == r2->romd_mode
fb1cd6f9 311 && r1->readonly == r2->readonly;
3d8e6bf9
AK
312}
313
8508e024 314/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
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315static void flatview_simplify(FlatView *view)
316{
317 unsigned i, j;
318
319 i = 0;
320 while (i < view->nr) {
321 j = i + 1;
322 while (j < view->nr
323 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 324 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
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325 ++j;
326 }
327 ++i;
328 memmove(&view->ranges[i], &view->ranges[j],
329 (view->nr - j) * sizeof(view->ranges[j]));
330 view->nr -= j - i;
331 }
332}
333
e7342aa3
PB
334static bool memory_region_big_endian(MemoryRegion *mr)
335{
336#ifdef TARGET_WORDS_BIGENDIAN
337 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
338#else
339 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
340#endif
341}
342
e11ef3d1
PB
343static bool memory_region_wrong_endianness(MemoryRegion *mr)
344{
345#ifdef TARGET_WORDS_BIGENDIAN
346 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
347#else
348 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
349#endif
350}
351
352static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
353{
354 if (memory_region_wrong_endianness(mr)) {
355 switch (size) {
356 case 1:
357 break;
358 case 2:
359 *data = bswap16(*data);
360 break;
361 case 4:
362 *data = bswap32(*data);
363 break;
364 case 8:
365 *data = bswap64(*data);
366 break;
367 default:
368 abort();
369 }
370 }
371}
372
cc05c43a
PM
373static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
374 hwaddr addr,
375 uint64_t *value,
376 unsigned size,
377 unsigned shift,
378 uint64_t mask,
379 MemTxAttrs attrs)
380{
381 uint64_t tmp;
382
383 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
384 trace_memory_region_ops_read(mr, addr, tmp, size);
385 *value |= (tmp & mask) << shift;
386 return MEMTX_OK;
387}
388
389static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB
390 hwaddr addr,
391 uint64_t *value,
392 unsigned size,
393 unsigned shift,
cc05c43a
PM
394 uint64_t mask,
395 MemTxAttrs attrs)
ce5d2f33 396{
ce5d2f33
PB
397 uint64_t tmp;
398
cc05c43a 399 tmp = mr->ops->read(mr->opaque, addr, size);
55d5d048 400 trace_memory_region_ops_read(mr, addr, tmp, size);
ce5d2f33 401 *value |= (tmp & mask) << shift;
cc05c43a 402 return MEMTX_OK;
ce5d2f33
PB
403}
404
cc05c43a
PM
405static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
406 hwaddr addr,
407 uint64_t *value,
408 unsigned size,
409 unsigned shift,
410 uint64_t mask,
411 MemTxAttrs attrs)
164a4dcd 412{
cc05c43a
PM
413 uint64_t tmp = 0;
414 MemTxResult r;
164a4dcd 415
cc05c43a 416 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
55d5d048 417 trace_memory_region_ops_read(mr, addr, tmp, size);
164a4dcd 418 *value |= (tmp & mask) << shift;
cc05c43a 419 return r;
164a4dcd
AK
420}
421
cc05c43a
PM
422static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
423 hwaddr addr,
424 uint64_t *value,
425 unsigned size,
426 unsigned shift,
427 uint64_t mask,
428 MemTxAttrs attrs)
ce5d2f33 429{
ce5d2f33
PB
430 uint64_t tmp;
431
432 tmp = (*value >> shift) & mask;
55d5d048 433 trace_memory_region_ops_write(mr, addr, tmp, size);
ce5d2f33 434 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
cc05c43a 435 return MEMTX_OK;
ce5d2f33
PB
436}
437
cc05c43a
PM
438static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
439 hwaddr addr,
440 uint64_t *value,
441 unsigned size,
442 unsigned shift,
443 uint64_t mask,
444 MemTxAttrs attrs)
164a4dcd 445{
164a4dcd
AK
446 uint64_t tmp;
447
448 tmp = (*value >> shift) & mask;
55d5d048 449 trace_memory_region_ops_write(mr, addr, tmp, size);
164a4dcd 450 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 451 return MEMTX_OK;
164a4dcd
AK
452}
453
cc05c43a
PM
454static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
455 hwaddr addr,
456 uint64_t *value,
457 unsigned size,
458 unsigned shift,
459 uint64_t mask,
460 MemTxAttrs attrs)
461{
462 uint64_t tmp;
463
cc05c43a
PM
464 tmp = (*value >> shift) & mask;
465 trace_memory_region_ops_write(mr, addr, tmp, size);
466 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
467}
468
469static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
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470 uint64_t *value,
471 unsigned size,
472 unsigned access_size_min,
473 unsigned access_size_max,
cc05c43a
PM
474 MemTxResult (*access)(MemoryRegion *mr,
475 hwaddr addr,
476 uint64_t *value,
477 unsigned size,
478 unsigned shift,
479 uint64_t mask,
480 MemTxAttrs attrs),
481 MemoryRegion *mr,
482 MemTxAttrs attrs)
164a4dcd
AK
483{
484 uint64_t access_mask;
485 unsigned access_size;
486 unsigned i;
cc05c43a 487 MemTxResult r = MEMTX_OK;
164a4dcd
AK
488
489 if (!access_size_min) {
490 access_size_min = 1;
491 }
492 if (!access_size_max) {
493 access_size_max = 4;
494 }
ce5d2f33
PB
495
496 /* FIXME: support unaligned access? */
164a4dcd
AK
497 access_size = MAX(MIN(size, access_size_max), access_size_min);
498 access_mask = -1ULL >> (64 - access_size * 8);
e7342aa3
PB
499 if (memory_region_big_endian(mr)) {
500 for (i = 0; i < size; i += access_size) {
cc05c43a
PM
501 r |= access(mr, addr + i, value, access_size,
502 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB
503 }
504 } else {
505 for (i = 0; i < size; i += access_size) {
cc05c43a
PM
506 r |= access(mr, addr + i, value, access_size, i * 8,
507 access_mask, attrs);
e7342aa3 508 }
164a4dcd 509 }
cc05c43a 510 return r;
164a4dcd
AK
511}
512
e2177955
AK
513static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
514{
0d673e36
AK
515 AddressSpace *as;
516
feca4ac1
PB
517 while (mr->container) {
518 mr = mr->container;
e2177955 519 }
0d673e36
AK
520 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
521 if (mr == as->root) {
522 return as;
523 }
e2177955 524 }
eed2bacf 525 return NULL;
e2177955
AK
526}
527
093bc2cd
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528/* Render a memory region into the global view. Ranges in @view obscure
529 * ranges in @mr.
530 */
531static void render_memory_region(FlatView *view,
532 MemoryRegion *mr,
08dafab4 533 Int128 base,
fb1cd6f9
AK
534 AddrRange clip,
535 bool readonly)
093bc2cd
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536{
537 MemoryRegion *subregion;
538 unsigned i;
a8170e5e 539 hwaddr offset_in_region;
08dafab4
AK
540 Int128 remain;
541 Int128 now;
093bc2cd
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542 FlatRange fr;
543 AddrRange tmp;
544
6bba19ba
AK
545 if (!mr->enabled) {
546 return;
547 }
548
08dafab4 549 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 550 readonly |= mr->readonly;
093bc2cd
AK
551
552 tmp = addrrange_make(base, mr->size);
553
554 if (!addrrange_intersects(tmp, clip)) {
555 return;
556 }
557
558 clip = addrrange_intersection(tmp, clip);
559
560 if (mr->alias) {
08dafab4
AK
561 int128_subfrom(&base, int128_make64(mr->alias->addr));
562 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 563 render_memory_region(view, mr->alias, base, clip, readonly);
093bc2cd
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564 return;
565 }
566
567 /* Render subregions in priority order. */
568 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 569 render_memory_region(view, subregion, base, clip, readonly);
093bc2cd
AK
570 }
571
14a3c10a 572 if (!mr->terminates) {
093bc2cd
AK
573 return;
574 }
575
08dafab4 576 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK
577 base = clip.start;
578 remain = clip.size;
579
2eb74e1a 580 fr.mr = mr;
6f6a5ef3 581 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
2eb74e1a
PC
582 fr.romd_mode = mr->romd_mode;
583 fr.readonly = readonly;
584
093bc2cd 585 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK
586 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
587 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK
588 continue;
589 }
08dafab4
AK
590 if (int128_lt(base, view->ranges[i].addr.start)) {
591 now = int128_min(remain,
592 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK
593 fr.offset_in_region = offset_in_region;
594 fr.addr = addrrange_make(base, now);
595 flatview_insert(view, i, &fr);
596 ++i;
08dafab4
AK
597 int128_addto(&base, now);
598 offset_in_region += int128_get64(now);
599 int128_subfrom(&remain, now);
093bc2cd 600 }
d26a8cae
AK
601 now = int128_sub(int128_min(int128_add(base, remain),
602 addrrange_end(view->ranges[i].addr)),
603 base);
604 int128_addto(&base, now);
605 offset_in_region += int128_get64(now);
606 int128_subfrom(&remain, now);
093bc2cd 607 }
08dafab4 608 if (int128_nz(remain)) {
093bc2cd
AK
609 fr.offset_in_region = offset_in_region;
610 fr.addr = addrrange_make(base, remain);
611 flatview_insert(view, i, &fr);
612 }
613}
614
615/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 616static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 617{
a9a0c06d 618 FlatView *view;
093bc2cd 619
a9a0c06d
PB
620 view = g_new(FlatView, 1);
621 flatview_init(view);
093bc2cd 622
83f3c251 623 if (mr) {
a9a0c06d 624 render_memory_region(view, mr, int128_zero(),
83f3c251
AK
625 addrrange_make(int128_zero(), int128_2_64()), false);
626 }
a9a0c06d 627 flatview_simplify(view);
093bc2cd
AK
628
629 return view;
630}
631
3e9d69e7
AK
632static void address_space_add_del_ioeventfds(AddressSpace *as,
633 MemoryRegionIoeventfd *fds_new,
634 unsigned fds_new_nb,
635 MemoryRegionIoeventfd *fds_old,
636 unsigned fds_old_nb)
637{
638 unsigned iold, inew;
80a1ea37
AK
639 MemoryRegionIoeventfd *fd;
640 MemoryRegionSection section;
3e9d69e7
AK
641
642 /* Generate a symmetric difference of the old and new fd sets, adding
643 * and deleting as necessary.
644 */
645
646 iold = inew = 0;
647 while (iold < fds_old_nb || inew < fds_new_nb) {
648 if (iold < fds_old_nb
649 && (inew == fds_new_nb
650 || memory_region_ioeventfd_before(fds_old[iold],
651 fds_new[inew]))) {
80a1ea37
AK
652 fd = &fds_old[iold];
653 section = (MemoryRegionSection) {
f6790af6 654 .address_space = as,
80a1ea37 655 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 656 .size = fd->addr.size,
80a1ea37
AK
657 };
658 MEMORY_LISTENER_CALL(eventfd_del, Forward, &section,
753d5e14 659 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
660 ++iold;
661 } else if (inew < fds_new_nb
662 && (iold == fds_old_nb
663 || memory_region_ioeventfd_before(fds_new[inew],
664 fds_old[iold]))) {
80a1ea37
AK
665 fd = &fds_new[inew];
666 section = (MemoryRegionSection) {
f6790af6 667 .address_space = as,
80a1ea37 668 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 669 .size = fd->addr.size,
80a1ea37
AK
670 };
671 MEMORY_LISTENER_CALL(eventfd_add, Reverse, &section,
753d5e14 672 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
673 ++inew;
674 } else {
675 ++iold;
676 ++inew;
677 }
678 }
679}
680
856d7245
PB
681static FlatView *address_space_get_flatview(AddressSpace *as)
682{
683 FlatView *view;
684
374f2981
PB
685 rcu_read_lock();
686 view = atomic_rcu_read(&as->current_map);
856d7245 687 flatview_ref(view);
374f2981 688 rcu_read_unlock();
856d7245
PB
689 return view;
690}
691
3e9d69e7
AK
692static void address_space_update_ioeventfds(AddressSpace *as)
693{
99e86347 694 FlatView *view;
3e9d69e7
AK
695 FlatRange *fr;
696 unsigned ioeventfd_nb = 0;
697 MemoryRegionIoeventfd *ioeventfds = NULL;
698 AddrRange tmp;
699 unsigned i;
700
856d7245 701 view = address_space_get_flatview(as);
99e86347 702 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK
703 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
704 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK
705 int128_sub(fr->addr.start,
706 int128_make64(fr->offset_in_region)));
3e9d69e7
AK
707 if (addrrange_intersects(fr->addr, tmp)) {
708 ++ioeventfd_nb;
7267c094 709 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK
710 ioeventfd_nb * sizeof(*ioeventfds));
711 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
712 ioeventfds[ioeventfd_nb-1].addr = tmp;
713 }
714 }
715 }
716
717 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
718 as->ioeventfds, as->ioeventfd_nb);
719
7267c094 720 g_free(as->ioeventfds);
3e9d69e7
AK
721 as->ioeventfds = ioeventfds;
722 as->ioeventfd_nb = ioeventfd_nb;
856d7245 723 flatview_unref(view);
3e9d69e7
AK
724}
725
b8af1afb 726static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB
727 const FlatView *old_view,
728 const FlatView *new_view,
b8af1afb 729 bool adding)
093bc2cd 730{
093bc2cd
AK
731 unsigned iold, inew;
732 FlatRange *frold, *frnew;
093bc2cd
AK
733
734 /* Generate a symmetric difference of the old and new memory maps.
735 * Kill ranges in the old map, and instantiate ranges in the new map.
736 */
737 iold = inew = 0;
a9a0c06d
PB
738 while (iold < old_view->nr || inew < new_view->nr) {
739 if (iold < old_view->nr) {
740 frold = &old_view->ranges[iold];
093bc2cd
AK
741 } else {
742 frold = NULL;
743 }
a9a0c06d
PB
744 if (inew < new_view->nr) {
745 frnew = &new_view->ranges[inew];
093bc2cd
AK
746 } else {
747 frnew = NULL;
748 }
749
750 if (frold
751 && (!frnew
08dafab4
AK
752 || int128_lt(frold->addr.start, frnew->addr.start)
753 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 754 && !flatrange_equal(frold, frnew)))) {
41a6e477 755 /* In old but not in new, or in both but attributes changed. */
093bc2cd 756
b8af1afb 757 if (!adding) {
72e22d2f 758 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK
759 }
760
093bc2cd
AK
761 ++iold;
762 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 763 /* In both and unchanged (except logging may have changed) */
093bc2cd 764
b8af1afb 765 if (adding) {
50c1e149 766 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB
767 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
768 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
769 frold->dirty_log_mask,
770 frnew->dirty_log_mask);
771 }
772 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
773 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
774 frold->dirty_log_mask,
775 frnew->dirty_log_mask);
b8af1afb 776 }
5a583347
AK
777 }
778
093bc2cd
AK
779 ++iold;
780 ++inew;
093bc2cd
AK
781 } else {
782 /* In new */
783
b8af1afb 784 if (adding) {
72e22d2f 785 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK
786 }
787
093bc2cd
AK
788 ++inew;
789 }
790 }
b8af1afb
AK
791}
792
793
794static void address_space_update_topology(AddressSpace *as)
795{
856d7245 796 FlatView *old_view = address_space_get_flatview(as);
a9a0c06d 797 FlatView *new_view = generate_memory_topology(as->root);
b8af1afb
AK
798
799 address_space_update_topology_pass(as, old_view, new_view, false);
800 address_space_update_topology_pass(as, old_view, new_view, true);
801
374f2981
PB
802 /* Writes are protected by the BQL. */
803 atomic_rcu_set(&as->current_map, new_view);
804 call_rcu(old_view, flatview_unref, rcu);
856d7245
PB
805
806 /* Note that all the old MemoryRegions are still alive up to this
807 * point. This relieves most MemoryListeners from the need to
808 * ref/unref the MemoryRegions they get---unless they use them
809 * outside the iothread mutex, in which case precise reference
810 * counting is necessary.
811 */
812 flatview_unref(old_view);
813
3e9d69e7 814 address_space_update_ioeventfds(as);
093bc2cd
AK
815}
816
4ef4db86
AK
817void memory_region_transaction_begin(void)
818{
bb880ded 819 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK
820 ++memory_region_transaction_depth;
821}
822
4dc56152
GA
823static void memory_region_clear_pending(void)
824{
825 memory_region_update_pending = false;
826 ioeventfd_update_pending = false;
827}
828
4ef4db86
AK
829void memory_region_transaction_commit(void)
830{
0d673e36
AK
831 AddressSpace *as;
832
4ef4db86
AK
833 assert(memory_region_transaction_depth);
834 --memory_region_transaction_depth;
4dc56152
GA
835 if (!memory_region_transaction_depth) {
836 if (memory_region_update_pending) {
837 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 838
4dc56152
GA
839 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
840 address_space_update_topology(as);
841 }
02e2b95f 842
4dc56152
GA
843 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
844 } else if (ioeventfd_update_pending) {
845 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
846 address_space_update_ioeventfds(as);
847 }
848 }
849 memory_region_clear_pending();
850 }
4ef4db86
AK
851}
852
545e92e0
AK
853static void memory_region_destructor_none(MemoryRegion *mr)
854{
855}
856
857static void memory_region_destructor_ram(MemoryRegion *mr)
858{
859 qemu_ram_free(mr->ram_addr);
860}
861
862static void memory_region_destructor_ram_from_ptr(MemoryRegion *mr)
863{
864 qemu_ram_free_from_ptr(mr->ram_addr);
865}
866
d0a9b5bc
AK
867static void memory_region_destructor_rom_device(MemoryRegion *mr)
868{
869 qemu_ram_free(mr->ram_addr & TARGET_PAGE_MASK);
d0a9b5bc
AK
870}
871
b4fefef9
PC
872static bool memory_region_need_escape(char c)
873{
874 return c == '/' || c == '[' || c == '\\' || c == ']';
875}
876
877static char *memory_region_escape_name(const char *name)
878{
879 const char *p;
880 char *escaped, *q;
881 uint8_t c;
882 size_t bytes = 0;
883
884 for (p = name; *p; p++) {
885 bytes += memory_region_need_escape(*p) ? 4 : 1;
886 }
887 if (bytes == p - name) {
888 return g_memdup(name, bytes + 1);
889 }
890
891 escaped = g_malloc(bytes + 1);
892 for (p = name, q = escaped; *p; p++) {
893 c = *p;
894 if (unlikely(memory_region_need_escape(c))) {
895 *q++ = '\\';
896 *q++ = 'x';
897 *q++ = "0123456789abcdef"[c >> 4];
898 c = "0123456789abcdef"[c & 15];
899 }
900 *q++ = c;
901 }
902 *q = 0;
903 return escaped;
904}
905
093bc2cd 906void memory_region_init(MemoryRegion *mr,
2c9b15ca 907 Object *owner,
093bc2cd
AK
908 const char *name,
909 uint64_t size)
910{
22a893e4 911 if (!owner) {
210eb936 912 owner = container_get(qdev_get_machine(), "/unattached");
22a893e4 913 }
b4fefef9 914
22a893e4 915 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
08dafab4
AK
916 mr->size = int128_make64(size);
917 if (size == UINT64_MAX) {
918 mr->size = int128_2_64();
919 }
302fa283 920 mr->name = g_strdup(name);
b4fefef9
PC
921
922 if (name) {
843ef73a
PC
923 char *escaped_name = memory_region_escape_name(name);
924 char *name_array = g_strdup_printf("%s[*]", escaped_name);
925 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 926 object_unref(OBJECT(mr));
843ef73a
PC
927 g_free(name_array);
928 g_free(escaped_name);
b4fefef9
PC
929 }
930}
931
409ddd01
PC
932static void memory_region_get_addr(Object *obj, Visitor *v, void *opaque,
933 const char *name, Error **errp)
934{
935 MemoryRegion *mr = MEMORY_REGION(obj);
936 uint64_t value = mr->addr;
937
938 visit_type_uint64(v, &value, name, errp);
939}
940
941static void memory_region_get_container(Object *obj, Visitor *v, void *opaque,
942 const char *name, Error **errp)
943{
944 MemoryRegion *mr = MEMORY_REGION(obj);
945 gchar *path = (gchar *)"";
946
947 if (mr->container) {
948 path = object_get_canonical_path(OBJECT(mr->container));
949 }
950 visit_type_str(v, &path, name, errp);
951 if (mr->container) {
952 g_free(path);
953 }
954}
955
956static Object *memory_region_resolve_container(Object *obj, void *opaque,
957 const char *part)
958{
959 MemoryRegion *mr = MEMORY_REGION(obj);
960
961 return OBJECT(mr->container);
962}
963
d33382da
PC
964static void memory_region_get_priority(Object *obj, Visitor *v, void *opaque,
965 const char *name, Error **errp)
966{
967 MemoryRegion *mr = MEMORY_REGION(obj);
968 int32_t value = mr->priority;
969
970 visit_type_int32(v, &value, name, errp);
971}
972
973static bool memory_region_get_may_overlap(Object *obj, Error **errp)
974{
975 MemoryRegion *mr = MEMORY_REGION(obj);
976
977 return mr->may_overlap;
978}
979
52aef7bb
PC
980static void memory_region_get_size(Object *obj, Visitor *v, void *opaque,
981 const char *name, Error **errp)
982{
983 MemoryRegion *mr = MEMORY_REGION(obj);
984 uint64_t value = memory_region_size(mr);
985
986 visit_type_uint64(v, &value, name, errp);
987}
988
b4fefef9
PC
989static void memory_region_initfn(Object *obj)
990{
991 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 992 ObjectProperty *op;
b4fefef9
PC
993
994 mr->ops = &unassigned_mem_ops;
ec05ec26 995 mr->ram_addr = RAM_ADDR_INVALID;
6bba19ba 996 mr->enabled = true;
5f9a5ea1 997 mr->romd_mode = true;
196ea131 998 mr->global_locking = true;
545e92e0 999 mr->destructor = memory_region_destructor_none;
093bc2cd 1000 QTAILQ_INIT(&mr->subregions);
093bc2cd 1001 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC
1002
1003 op = object_property_add(OBJECT(mr), "container",
1004 "link<" TYPE_MEMORY_REGION ">",
1005 memory_region_get_container,
1006 NULL, /* memory_region_set_container */
1007 NULL, NULL, &error_abort);
1008 op->resolve = memory_region_resolve_container;
1009
1010 object_property_add(OBJECT(mr), "addr", "uint64",
1011 memory_region_get_addr,
1012 NULL, /* memory_region_set_addr */
1013 NULL, NULL, &error_abort);
d33382da
PC
1014 object_property_add(OBJECT(mr), "priority", "uint32",
1015 memory_region_get_priority,
1016 NULL, /* memory_region_set_priority */
1017 NULL, NULL, &error_abort);
1018 object_property_add_bool(OBJECT(mr), "may-overlap",
1019 memory_region_get_may_overlap,
1020 NULL, /* memory_region_set_may_overlap */
1021 &error_abort);
52aef7bb
PC
1022 object_property_add(OBJECT(mr), "size", "uint64",
1023 memory_region_get_size,
1024 NULL, /* memory_region_set_size, */
1025 NULL, NULL, &error_abort);
093bc2cd
AK
1026}
1027
b018ddf6
PB
1028static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1029 unsigned size)
1030{
1031#ifdef DEBUG_UNASSIGNED
1032 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1033#endif
4917cf44
AF
1034 if (current_cpu != NULL) {
1035 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
c658b94f 1036 }
68a7439a 1037 return 0;
b018ddf6
PB
1038}
1039
1040static void unassigned_mem_write(void *opaque, hwaddr addr,
1041 uint64_t val, unsigned size)
1042{
1043#ifdef DEBUG_UNASSIGNED
1044 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1045#endif
4917cf44
AF
1046 if (current_cpu != NULL) {
1047 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1048 }
b018ddf6
PB
1049}
1050
d197063f
PB
1051static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1052 unsigned size, bool is_write)
1053{
1054 return false;
1055}
1056
1057const MemoryRegionOps unassigned_mem_ops = {
1058 .valid.accepts = unassigned_mem_accepts,
1059 .endianness = DEVICE_NATIVE_ENDIAN,
1060};
1061
d2702032
PB
1062bool memory_region_access_valid(MemoryRegion *mr,
1063 hwaddr addr,
1064 unsigned size,
1065 bool is_write)
093bc2cd 1066{
a014ed07
PB
1067 int access_size_min, access_size_max;
1068 int access_size, i;
897fa7cf 1069
093bc2cd
AK
1070 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1071 return false;
1072 }
1073
a014ed07 1074 if (!mr->ops->valid.accepts) {
093bc2cd
AK
1075 return true;
1076 }
1077
a014ed07
PB
1078 access_size_min = mr->ops->valid.min_access_size;
1079 if (!mr->ops->valid.min_access_size) {
1080 access_size_min = 1;
1081 }
1082
1083 access_size_max = mr->ops->valid.max_access_size;
1084 if (!mr->ops->valid.max_access_size) {
1085 access_size_max = 4;
1086 }
1087
1088 access_size = MAX(MIN(size, access_size_max), access_size_min);
1089 for (i = 0; i < size; i += access_size) {
1090 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1091 is_write)) {
1092 return false;
1093 }
093bc2cd 1094 }
a014ed07 1095
093bc2cd
AK
1096 return true;
1097}
1098
cc05c43a
PM
1099static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1100 hwaddr addr,
1101 uint64_t *pval,
1102 unsigned size,
1103 MemTxAttrs attrs)
093bc2cd 1104{
cc05c43a 1105 *pval = 0;
093bc2cd 1106
ce5d2f33 1107 if (mr->ops->read) {
cc05c43a
PM
1108 return access_with_adjusted_size(addr, pval, size,
1109 mr->ops->impl.min_access_size,
1110 mr->ops->impl.max_access_size,
1111 memory_region_read_accessor,
1112 mr, attrs);
1113 } else if (mr->ops->read_with_attrs) {
1114 return access_with_adjusted_size(addr, pval, size,
1115 mr->ops->impl.min_access_size,
1116 mr->ops->impl.max_access_size,
1117 memory_region_read_with_attrs_accessor,
1118 mr, attrs);
ce5d2f33 1119 } else {
cc05c43a
PM
1120 return access_with_adjusted_size(addr, pval, size, 1, 4,
1121 memory_region_oldmmio_read_accessor,
1122 mr, attrs);
74901c3b 1123 }
093bc2cd
AK
1124}
1125
3b643495
PM
1126MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1127 hwaddr addr,
1128 uint64_t *pval,
1129 unsigned size,
1130 MemTxAttrs attrs)
a621f38d 1131{
cc05c43a
PM
1132 MemTxResult r;
1133
791af8c8
PB
1134 if (!memory_region_access_valid(mr, addr, size, false)) {
1135 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1136 return MEMTX_DECODE_ERROR;
791af8c8 1137 }
a621f38d 1138
cc05c43a 1139 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1140 adjust_endianness(mr, pval, size);
cc05c43a 1141 return r;
a621f38d 1142}
093bc2cd 1143
3b643495
PM
1144MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1145 hwaddr addr,
1146 uint64_t data,
1147 unsigned size,
1148 MemTxAttrs attrs)
a621f38d 1149{
897fa7cf 1150 if (!memory_region_access_valid(mr, addr, size, true)) {
b018ddf6 1151 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1152 return MEMTX_DECODE_ERROR;
093bc2cd
AK
1153 }
1154
a621f38d
AK
1155 adjust_endianness(mr, &data, size);
1156
ce5d2f33 1157 if (mr->ops->write) {
cc05c43a
PM
1158 return access_with_adjusted_size(addr, &data, size,
1159 mr->ops->impl.min_access_size,
1160 mr->ops->impl.max_access_size,
1161 memory_region_write_accessor, mr,
1162 attrs);
1163 } else if (mr->ops->write_with_attrs) {
1164 return
1165 access_with_adjusted_size(addr, &data, size,
1166 mr->ops->impl.min_access_size,
1167 mr->ops->impl.max_access_size,
1168 memory_region_write_with_attrs_accessor,
1169 mr, attrs);
ce5d2f33 1170 } else {
cc05c43a
PM
1171 return access_with_adjusted_size(addr, &data, size, 1, 4,
1172 memory_region_oldmmio_write_accessor,
1173 mr, attrs);
74901c3b 1174 }
093bc2cd
AK
1175}
1176
093bc2cd 1177void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1178 Object *owner,
093bc2cd
AK
1179 const MemoryRegionOps *ops,
1180 void *opaque,
1181 const char *name,
1182 uint64_t size)
1183{
2c9b15ca 1184 memory_region_init(mr, owner, name, size);
093bc2cd
AK
1185 mr->ops = ops;
1186 mr->opaque = opaque;
14a3c10a 1187 mr->terminates = true;
093bc2cd
AK
1188}
1189
1190void memory_region_init_ram(MemoryRegion *mr,
2c9b15ca 1191 Object *owner,
093bc2cd 1192 const char *name,
49946538
HT
1193 uint64_t size,
1194 Error **errp)
093bc2cd 1195{
2c9b15ca 1196 memory_region_init(mr, owner, name, size);
8ea9252a 1197 mr->ram = true;
14a3c10a 1198 mr->terminates = true;
545e92e0 1199 mr->destructor = memory_region_destructor_ram;
49946538 1200 mr->ram_addr = qemu_ram_alloc(size, mr, errp);
677e7805 1201 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
0b183fc8
PB
1202}
1203
60786ef3
MT
1204void memory_region_init_resizeable_ram(MemoryRegion *mr,
1205 Object *owner,
1206 const char *name,
1207 uint64_t size,
1208 uint64_t max_size,
1209 void (*resized)(const char*,
1210 uint64_t length,
1211 void *host),
1212 Error **errp)
1213{
1214 memory_region_init(mr, owner, name, size);
1215 mr->ram = true;
1216 mr->terminates = true;
1217 mr->destructor = memory_region_destructor_ram;
1218 mr->ram_addr = qemu_ram_alloc_resizeable(size, max_size, resized, mr, errp);
677e7805 1219 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
60786ef3
MT
1220}
1221
0b183fc8
PB
1222#ifdef __linux__
1223void memory_region_init_ram_from_file(MemoryRegion *mr,
1224 struct Object *owner,
1225 const char *name,
1226 uint64_t size,
dbcb8981 1227 bool share,
7f56e740
PB
1228 const char *path,
1229 Error **errp)
0b183fc8
PB
1230{
1231 memory_region_init(mr, owner, name, size);
1232 mr->ram = true;
1233 mr->terminates = true;
1234 mr->destructor = memory_region_destructor_ram;
dbcb8981 1235 mr->ram_addr = qemu_ram_alloc_from_file(size, mr, share, path, errp);
677e7805 1236 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
093bc2cd 1237}
0b183fc8 1238#endif
093bc2cd
AK
1239
1240void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1241 Object *owner,
093bc2cd
AK
1242 const char *name,
1243 uint64_t size,
1244 void *ptr)
1245{
2c9b15ca 1246 memory_region_init(mr, owner, name, size);
8ea9252a 1247 mr->ram = true;
14a3c10a 1248 mr->terminates = true;
545e92e0 1249 mr->destructor = memory_region_destructor_ram_from_ptr;
677e7805 1250 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT
1251
1252 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1253 assert(ptr != NULL);
1254 mr->ram_addr = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_abort);
093bc2cd
AK
1255}
1256
e4dc3f59
ND
1257void memory_region_set_skip_dump(MemoryRegion *mr)
1258{
1259 mr->skip_dump = true;
1260}
1261
093bc2cd 1262void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1263 Object *owner,
093bc2cd
AK
1264 const char *name,
1265 MemoryRegion *orig,
a8170e5e 1266 hwaddr offset,
093bc2cd
AK
1267 uint64_t size)
1268{
2c9b15ca 1269 memory_region_init(mr, owner, name, size);
093bc2cd
AK
1270 mr->alias = orig;
1271 mr->alias_offset = offset;
1272}
1273
d0a9b5bc 1274void memory_region_init_rom_device(MemoryRegion *mr,
2c9b15ca 1275 Object *owner,
d0a9b5bc 1276 const MemoryRegionOps *ops,
75f5941c 1277 void *opaque,
d0a9b5bc 1278 const char *name,
33e0eb52
HT
1279 uint64_t size,
1280 Error **errp)
d0a9b5bc 1281{
2c9b15ca 1282 memory_region_init(mr, owner, name, size);
7bc2b9cd 1283 mr->ops = ops;
75f5941c 1284 mr->opaque = opaque;
d0a9b5bc 1285 mr->terminates = true;
75c578dc 1286 mr->rom_device = true;
d0a9b5bc 1287 mr->destructor = memory_region_destructor_rom_device;
33e0eb52 1288 mr->ram_addr = qemu_ram_alloc(size, mr, errp);
d0a9b5bc
AK
1289}
1290
30951157 1291void memory_region_init_iommu(MemoryRegion *mr,
2c9b15ca 1292 Object *owner,
30951157
AK
1293 const MemoryRegionIOMMUOps *ops,
1294 const char *name,
1295 uint64_t size)
1296{
2c9b15ca 1297 memory_region_init(mr, owner, name, size);
30951157
AK
1298 mr->iommu_ops = ops,
1299 mr->terminates = true; /* then re-forwards */
06866575 1300 notifier_list_init(&mr->iommu_notify);
30951157
AK
1301}
1302
1660e72d 1303void memory_region_init_reservation(MemoryRegion *mr,
2c9b15ca 1304 Object *owner,
1660e72d
JK
1305 const char *name,
1306 uint64_t size)
1307{
2c9b15ca 1308 memory_region_init_io(mr, owner, &unassigned_mem_ops, mr, name, size);
1660e72d
JK
1309}
1310
b4fefef9 1311static void memory_region_finalize(Object *obj)
093bc2cd 1312{
b4fefef9
PC
1313 MemoryRegion *mr = MEMORY_REGION(obj);
1314
093bc2cd 1315 assert(QTAILQ_EMPTY(&mr->subregions));
545e92e0 1316 mr->destructor(mr);
093bc2cd 1317 memory_region_clear_coalescing(mr);
302fa283 1318 g_free((char *)mr->name);
7267c094 1319 g_free(mr->ioeventfds);
093bc2cd
AK
1320}
1321
803c0816
PB
1322Object *memory_region_owner(MemoryRegion *mr)
1323{
22a893e4
PB
1324 Object *obj = OBJECT(mr);
1325 return obj->parent;
803c0816
PB
1326}
1327
46637be2
PB
1328void memory_region_ref(MemoryRegion *mr)
1329{
22a893e4
PB
1330 /* MMIO callbacks most likely will access data that belongs
1331 * to the owner, hence the need to ref/unref the owner whenever
1332 * the memory region is in use.
1333 *
1334 * The memory region is a child of its owner. As long as the
1335 * owner doesn't call unparent itself on the memory region,
1336 * ref-ing the owner will also keep the memory region alive.
1337 * Memory regions without an owner are supposed to never go away,
1338 * but we still ref/unref them for debugging purposes.
1339 */
1340 Object *obj = OBJECT(mr);
1341 if (obj && obj->parent) {
1342 object_ref(obj->parent);
b4fefef9 1343 } else {
22a893e4 1344 object_ref(obj);
46637be2
PB
1345 }
1346}
1347
1348void memory_region_unref(MemoryRegion *mr)
1349{
22a893e4
PB
1350 Object *obj = OBJECT(mr);
1351 if (obj && obj->parent) {
1352 object_unref(obj->parent);
b4fefef9 1353 } else {
22a893e4 1354 object_unref(obj);
46637be2
PB
1355 }
1356}
1357
093bc2cd
AK
1358uint64_t memory_region_size(MemoryRegion *mr)
1359{
08dafab4
AK
1360 if (int128_eq(mr->size, int128_2_64())) {
1361 return UINT64_MAX;
1362 }
1363 return int128_get64(mr->size);
093bc2cd
AK
1364}
1365
5d546d4b 1366const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1367{
d1dd32af
PC
1368 if (!mr->name) {
1369 ((MemoryRegion *)mr)->name =
1370 object_get_canonical_path_component(OBJECT(mr));
1371 }
302fa283 1372 return mr->name;
8991c79b
AK
1373}
1374
8ea9252a
AK
1375bool memory_region_is_ram(MemoryRegion *mr)
1376{
1377 return mr->ram;
1378}
1379
e4dc3f59
ND
1380bool memory_region_is_skip_dump(MemoryRegion *mr)
1381{
1382 return mr->skip_dump;
1383}
1384
2d1a35be 1385uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1386{
6f6a5ef3
PB
1387 uint8_t mask = mr->dirty_log_mask;
1388 if (global_dirty_log) {
1389 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1390 }
1391 return mask;
55043ba3
AK
1392}
1393
2d1a35be
PB
1394bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1395{
1396 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1397}
1398
ce7923da
AK
1399bool memory_region_is_rom(MemoryRegion *mr)
1400{
1401 return mr->ram && mr->readonly;
1402}
1403
30951157
AK
1404bool memory_region_is_iommu(MemoryRegion *mr)
1405{
1406 return mr->iommu_ops;
1407}
1408
06866575
DG
1409void memory_region_register_iommu_notifier(MemoryRegion *mr, Notifier *n)
1410{
1411 notifier_list_add(&mr->iommu_notify, n);
1412}
1413
1414void memory_region_unregister_iommu_notifier(Notifier *n)
1415{
1416 notifier_remove(n);
1417}
1418
1419void memory_region_notify_iommu(MemoryRegion *mr,
1420 IOMMUTLBEntry entry)
1421{
1422 assert(memory_region_is_iommu(mr));
1423 notifier_list_notify(&mr->iommu_notify, &entry);
1424}
1425
093bc2cd
AK
1426void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1427{
5a583347 1428 uint8_t mask = 1 << client;
deb809ed 1429 uint8_t old_logging;
5a583347 1430
dbddac6d 1431 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB
1432 old_logging = mr->vga_logging_count;
1433 mr->vga_logging_count += log ? 1 : -1;
1434 if (!!old_logging == !!mr->vga_logging_count) {
1435 return;
1436 }
1437
59023ef4 1438 memory_region_transaction_begin();
5a583347 1439 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1440 memory_region_update_pending |= mr->enabled;
59023ef4 1441 memory_region_transaction_commit();
093bc2cd
AK
1442}
1443
a8170e5e
AK
1444bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1445 hwaddr size, unsigned client)
093bc2cd 1446{
ec05ec26 1447 assert(mr->ram_addr != RAM_ADDR_INVALID);
52159192 1448 return cpu_physical_memory_get_dirty(mr->ram_addr + addr, size, client);
093bc2cd
AK
1449}
1450
a8170e5e
AK
1451void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1452 hwaddr size)
093bc2cd 1453{
ec05ec26 1454 assert(mr->ram_addr != RAM_ADDR_INVALID);
58d2707e
PB
1455 cpu_physical_memory_set_dirty_range(mr->ram_addr + addr, size,
1456 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK
1457}
1458
6c279db8
JQ
1459bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1460 hwaddr size, unsigned client)
1461{
ec05ec26 1462 assert(mr->ram_addr != RAM_ADDR_INVALID);
03eebc9e
SH
1463 return cpu_physical_memory_test_and_clear_dirty(mr->ram_addr + addr,
1464 size, client);
6c279db8
JQ
1465}
1466
1467
093bc2cd
AK
1468void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1469{
0d673e36 1470 AddressSpace *as;
5a583347
AK
1471 FlatRange *fr;
1472
0d673e36 1473 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
856d7245 1474 FlatView *view = address_space_get_flatview(as);
99e86347 1475 FOR_EACH_FLAT_RANGE(fr, view) {
0d673e36
AK
1476 if (fr->mr == mr) {
1477 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, log_sync);
1478 }
5a583347 1479 }
856d7245 1480 flatview_unref(view);
5a583347 1481 }
093bc2cd
AK
1482}
1483
1484void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1485{
fb1cd6f9 1486 if (mr->readonly != readonly) {
59023ef4 1487 memory_region_transaction_begin();
fb1cd6f9 1488 mr->readonly = readonly;
22bde714 1489 memory_region_update_pending |= mr->enabled;
59023ef4 1490 memory_region_transaction_commit();
fb1cd6f9 1491 }
093bc2cd
AK
1492}
1493
5f9a5ea1 1494void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 1495{
5f9a5ea1 1496 if (mr->romd_mode != romd_mode) {
59023ef4 1497 memory_region_transaction_begin();
5f9a5ea1 1498 mr->romd_mode = romd_mode;
22bde714 1499 memory_region_update_pending |= mr->enabled;
59023ef4 1500 memory_region_transaction_commit();
d0a9b5bc
AK
1501 }
1502}
1503
a8170e5e
AK
1504void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
1505 hwaddr size, unsigned client)
093bc2cd 1506{
ec05ec26 1507 assert(mr->ram_addr != RAM_ADDR_INVALID);
03eebc9e
SH
1508 cpu_physical_memory_test_and_clear_dirty(mr->ram_addr + addr, size,
1509 client);
093bc2cd
AK
1510}
1511
a35ba7be
PB
1512int memory_region_get_fd(MemoryRegion *mr)
1513{
1514 if (mr->alias) {
1515 return memory_region_get_fd(mr->alias);
1516 }
1517
ec05ec26 1518 assert(mr->ram_addr != RAM_ADDR_INVALID);
a35ba7be
PB
1519
1520 return qemu_get_ram_fd(mr->ram_addr & TARGET_PAGE_MASK);
1521}
1522
093bc2cd
AK
1523void *memory_region_get_ram_ptr(MemoryRegion *mr)
1524{
1525 if (mr->alias) {
1526 return memory_region_get_ram_ptr(mr->alias) + mr->alias_offset;
1527 }
1528
ec05ec26 1529 assert(mr->ram_addr != RAM_ADDR_INVALID);
093bc2cd 1530
021d26d1 1531 return qemu_get_ram_ptr(mr->ram_addr & TARGET_PAGE_MASK);
093bc2cd
AK
1532}
1533
37d7c084
PB
1534void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
1535{
ec05ec26 1536 assert(mr->ram_addr != RAM_ADDR_INVALID);
37d7c084
PB
1537
1538 qemu_ram_resize(mr->ram_addr, newsize, errp);
1539}
1540
0d673e36 1541static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 1542{
99e86347 1543 FlatView *view;
093bc2cd
AK
1544 FlatRange *fr;
1545 CoalescedMemoryRange *cmr;
1546 AddrRange tmp;
95d2994a 1547 MemoryRegionSection section;
093bc2cd 1548
856d7245 1549 view = address_space_get_flatview(as);
99e86347 1550 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 1551 if (fr->mr == mr) {
95d2994a 1552 section = (MemoryRegionSection) {
f6790af6 1553 .address_space = as,
95d2994a 1554 .offset_within_address_space = int128_get64(fr->addr.start),
052e87b0 1555 .size = fr->addr.size,
95d2994a
AK
1556 };
1557
1558 MEMORY_LISTENER_CALL(coalesced_mmio_del, Reverse, &section,
1559 int128_get64(fr->addr.start),
1560 int128_get64(fr->addr.size));
093bc2cd
AK
1561 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
1562 tmp = addrrange_shift(cmr->addr,
08dafab4
AK
1563 int128_sub(fr->addr.start,
1564 int128_make64(fr->offset_in_region)));
093bc2cd
AK
1565 if (!addrrange_intersects(tmp, fr->addr)) {
1566 continue;
1567 }
1568 tmp = addrrange_intersection(tmp, fr->addr);
95d2994a
AK
1569 MEMORY_LISTENER_CALL(coalesced_mmio_add, Forward, &section,
1570 int128_get64(tmp.start),
1571 int128_get64(tmp.size));
093bc2cd
AK
1572 }
1573 }
1574 }
856d7245 1575 flatview_unref(view);
093bc2cd
AK
1576}
1577
0d673e36
AK
1578static void memory_region_update_coalesced_range(MemoryRegion *mr)
1579{
1580 AddressSpace *as;
1581
1582 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1583 memory_region_update_coalesced_range_as(mr, as);
1584 }
1585}
1586
093bc2cd
AK
1587void memory_region_set_coalescing(MemoryRegion *mr)
1588{
1589 memory_region_clear_coalescing(mr);
08dafab4 1590 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK
1591}
1592
1593void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 1594 hwaddr offset,
093bc2cd
AK
1595 uint64_t size)
1596{
7267c094 1597 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 1598
08dafab4 1599 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK
1600 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
1601 memory_region_update_coalesced_range(mr);
d410515e 1602 memory_region_set_flush_coalesced(mr);
093bc2cd
AK
1603}
1604
1605void memory_region_clear_coalescing(MemoryRegion *mr)
1606{
1607 CoalescedMemoryRange *cmr;
ab5b3db5 1608 bool updated = false;
093bc2cd 1609
d410515e
JK
1610 qemu_flush_coalesced_mmio_buffer();
1611 mr->flush_coalesced_mmio = false;
1612
093bc2cd
AK
1613 while (!QTAILQ_EMPTY(&mr->coalesced)) {
1614 cmr = QTAILQ_FIRST(&mr->coalesced);
1615 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 1616 g_free(cmr);
ab5b3db5
FZ
1617 updated = true;
1618 }
1619
1620 if (updated) {
1621 memory_region_update_coalesced_range(mr);
093bc2cd 1622 }
093bc2cd
AK
1623}
1624
d410515e
JK
1625void memory_region_set_flush_coalesced(MemoryRegion *mr)
1626{
1627 mr->flush_coalesced_mmio = true;
1628}
1629
1630void memory_region_clear_flush_coalesced(MemoryRegion *mr)
1631{
1632 qemu_flush_coalesced_mmio_buffer();
1633 if (QTAILQ_EMPTY(&mr->coalesced)) {
1634 mr->flush_coalesced_mmio = false;
1635 }
1636}
1637
196ea131
JK
1638void memory_region_set_global_locking(MemoryRegion *mr)
1639{
1640 mr->global_locking = true;
1641}
1642
1643void memory_region_clear_global_locking(MemoryRegion *mr)
1644{
1645 mr->global_locking = false;
1646}
1647
3e9d69e7 1648void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 1649 hwaddr addr,
3e9d69e7
AK
1650 unsigned size,
1651 bool match_data,
1652 uint64_t data,
753d5e14 1653 EventNotifier *e)
3e9d69e7
AK
1654{
1655 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
1656 .addr.start = int128_make64(addr),
1657 .addr.size = int128_make64(size),
3e9d69e7
AK
1658 .match_data = match_data,
1659 .data = data,
753d5e14 1660 .e = e,
3e9d69e7
AK
1661 };
1662 unsigned i;
1663
28f362be 1664 adjust_endianness(mr, &mrfd.data, size);
59023ef4 1665 memory_region_transaction_begin();
3e9d69e7
AK
1666 for (i = 0; i < mr->ioeventfd_nb; ++i) {
1667 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
1668 break;
1669 }
1670 }
1671 ++mr->ioeventfd_nb;
7267c094 1672 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK
1673 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
1674 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
1675 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
1676 mr->ioeventfds[i] = mrfd;
4dc56152 1677 ioeventfd_update_pending |= mr->enabled;
59023ef4 1678 memory_region_transaction_commit();
3e9d69e7
AK
1679}
1680
1681void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 1682 hwaddr addr,
3e9d69e7
AK
1683 unsigned size,
1684 bool match_data,
1685 uint64_t data,
753d5e14 1686 EventNotifier *e)
3e9d69e7
AK
1687{
1688 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
1689 .addr.start = int128_make64(addr),
1690 .addr.size = int128_make64(size),
3e9d69e7
AK
1691 .match_data = match_data,
1692 .data = data,
753d5e14 1693 .e = e,
3e9d69e7
AK
1694 };
1695 unsigned i;
1696
28f362be 1697 adjust_endianness(mr, &mrfd.data, size);
59023ef4 1698 memory_region_transaction_begin();
3e9d69e7
AK
1699 for (i = 0; i < mr->ioeventfd_nb; ++i) {
1700 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
1701 break;
1702 }
1703 }
1704 assert(i != mr->ioeventfd_nb);
1705 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
1706 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
1707 --mr->ioeventfd_nb;
7267c094 1708 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 1709 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 1710 ioeventfd_update_pending |= mr->enabled;
59023ef4 1711 memory_region_transaction_commit();
3e9d69e7
AK
1712}
1713
feca4ac1 1714static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 1715{
0598701a 1716 hwaddr offset = subregion->addr;
feca4ac1 1717 MemoryRegion *mr = subregion->container;
093bc2cd
AK
1718 MemoryRegion *other;
1719
59023ef4
JK
1720 memory_region_transaction_begin();
1721
dfde4e6e 1722 memory_region_ref(subregion);
093bc2cd
AK
1723 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
1724 if (subregion->may_overlap || other->may_overlap) {
1725 continue;
1726 }
2c7cfd65 1727 if (int128_ge(int128_make64(offset),
08dafab4
AK
1728 int128_add(int128_make64(other->addr), other->size))
1729 || int128_le(int128_add(int128_make64(offset), subregion->size),
1730 int128_make64(other->addr))) {
093bc2cd
AK
1731 continue;
1732 }
a5e1cbc8 1733#if 0
860329b2
MW
1734 printf("warning: subregion collision %llx/%llx (%s) "
1735 "vs %llx/%llx (%s)\n",
093bc2cd 1736 (unsigned long long)offset,
08dafab4 1737 (unsigned long long)int128_get64(subregion->size),
860329b2
MW
1738 subregion->name,
1739 (unsigned long long)other->addr,
08dafab4 1740 (unsigned long long)int128_get64(other->size),
860329b2 1741 other->name);
a5e1cbc8 1742#endif
093bc2cd
AK
1743 }
1744 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
1745 if (subregion->priority >= other->priority) {
1746 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
1747 goto done;
1748 }
1749 }
1750 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
1751done:
22bde714 1752 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 1753 memory_region_transaction_commit();
093bc2cd
AK
1754}
1755
0598701a
PC
1756static void memory_region_add_subregion_common(MemoryRegion *mr,
1757 hwaddr offset,
1758 MemoryRegion *subregion)
1759{
feca4ac1
PB
1760 assert(!subregion->container);
1761 subregion->container = mr;
0598701a 1762 subregion->addr = offset;
feca4ac1 1763 memory_region_update_container_subregions(subregion);
0598701a 1764}
093bc2cd
AK
1765
1766void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 1767 hwaddr offset,
093bc2cd
AK
1768 MemoryRegion *subregion)
1769{
1770 subregion->may_overlap = false;
1771 subregion->priority = 0;
1772 memory_region_add_subregion_common(mr, offset, subregion);
1773}
1774
1775void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 1776 hwaddr offset,
093bc2cd 1777 MemoryRegion *subregion,
a1ff8ae0 1778 int priority)
093bc2cd
AK
1779{
1780 subregion->may_overlap = true;
1781 subregion->priority = priority;
1782 memory_region_add_subregion_common(mr, offset, subregion);
1783}
1784
1785void memory_region_del_subregion(MemoryRegion *mr,
1786 MemoryRegion *subregion)
1787{
59023ef4 1788 memory_region_transaction_begin();
feca4ac1
PB
1789 assert(subregion->container == mr);
1790 subregion->container = NULL;
093bc2cd 1791 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 1792 memory_region_unref(subregion);
22bde714 1793 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 1794 memory_region_transaction_commit();
6bba19ba
AK
1795}
1796
1797void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
1798{
1799 if (enabled == mr->enabled) {
1800 return;
1801 }
59023ef4 1802 memory_region_transaction_begin();
6bba19ba 1803 mr->enabled = enabled;
22bde714 1804 memory_region_update_pending = true;
59023ef4 1805 memory_region_transaction_commit();
093bc2cd 1806}
1c0ffa58 1807
e7af4c67
MT
1808void memory_region_set_size(MemoryRegion *mr, uint64_t size)
1809{
1810 Int128 s = int128_make64(size);
1811
1812 if (size == UINT64_MAX) {
1813 s = int128_2_64();
1814 }
1815 if (int128_eq(s, mr->size)) {
1816 return;
1817 }
1818 memory_region_transaction_begin();
1819 mr->size = s;
1820 memory_region_update_pending = true;
1821 memory_region_transaction_commit();
1822}
1823
67891b8a 1824static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 1825{
feca4ac1 1826 MemoryRegion *container = mr->container;
2282e1af 1827
feca4ac1 1828 if (container) {
67891b8a
PC
1829 memory_region_transaction_begin();
1830 memory_region_ref(mr);
feca4ac1
PB
1831 memory_region_del_subregion(container, mr);
1832 mr->container = container;
1833 memory_region_update_container_subregions(mr);
67891b8a
PC
1834 memory_region_unref(mr);
1835 memory_region_transaction_commit();
2282e1af 1836 }
67891b8a 1837}
2282e1af 1838
67891b8a
PC
1839void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
1840{
1841 if (addr != mr->addr) {
1842 mr->addr = addr;
1843 memory_region_readd_subregion(mr);
1844 }
2282e1af
AK
1845}
1846
a8170e5e 1847void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 1848{
4703359e 1849 assert(mr->alias);
4703359e 1850
59023ef4 1851 if (offset == mr->alias_offset) {
4703359e
AK
1852 return;
1853 }
1854
59023ef4
JK
1855 memory_region_transaction_begin();
1856 mr->alias_offset = offset;
22bde714 1857 memory_region_update_pending |= mr->enabled;
59023ef4 1858 memory_region_transaction_commit();
4703359e
AK
1859}
1860
e34911c4
AK
1861ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
1862{
e34911c4
AK
1863 return mr->ram_addr;
1864}
1865
a2b257d6
IM
1866uint64_t memory_region_get_alignment(const MemoryRegion *mr)
1867{
1868 return mr->align;
1869}
1870
e2177955
AK
1871static int cmp_flatrange_addr(const void *addr_, const void *fr_)
1872{
1873 const AddrRange *addr = addr_;
1874 const FlatRange *fr = fr_;
1875
1876 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
1877 return -1;
1878 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
1879 return 1;
1880 }
1881 return 0;
1882}
1883
99e86347 1884static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 1885{
99e86347 1886 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK
1887 sizeof(FlatRange), cmp_flatrange_addr);
1888}
1889
eed2bacf
IM
1890bool memory_region_is_mapped(MemoryRegion *mr)
1891{
1892 return mr->container ? true : false;
1893}
1894
c6742b14
PB
1895/* Same as memory_region_find, but it does not add a reference to the
1896 * returned region. It must be called from an RCU critical section.
1897 */
1898static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
1899 hwaddr addr, uint64_t size)
e2177955 1900{
052e87b0 1901 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB
1902 MemoryRegion *root;
1903 AddressSpace *as;
1904 AddrRange range;
99e86347 1905 FlatView *view;
73034e9e
PB
1906 FlatRange *fr;
1907
1908 addr += mr->addr;
feca4ac1
PB
1909 for (root = mr; root->container; ) {
1910 root = root->container;
73034e9e
PB
1911 addr += root->addr;
1912 }
e2177955 1913
73034e9e 1914 as = memory_region_to_address_space(root);
eed2bacf
IM
1915 if (!as) {
1916 return ret;
1917 }
73034e9e 1918 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 1919
2b647668 1920 view = atomic_rcu_read(&as->current_map);
99e86347 1921 fr = flatview_lookup(view, range);
e2177955 1922 if (!fr) {
c6742b14 1923 return ret;
e2177955
AK
1924 }
1925
99e86347 1926 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK
1927 --fr;
1928 }
1929
1930 ret.mr = fr->mr;
73034e9e 1931 ret.address_space = as;
e2177955
AK
1932 range = addrrange_intersection(range, fr->addr);
1933 ret.offset_within_region = fr->offset_in_region;
1934 ret.offset_within_region += int128_get64(int128_sub(range.start,
1935 fr->addr.start));
052e87b0 1936 ret.size = range.size;
e2177955 1937 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 1938 ret.readonly = fr->readonly;
c6742b14
PB
1939 return ret;
1940}
1941
1942MemoryRegionSection memory_region_find(MemoryRegion *mr,
1943 hwaddr addr, uint64_t size)
1944{
1945 MemoryRegionSection ret;
1946 rcu_read_lock();
1947 ret = memory_region_find_rcu(mr, addr, size);
1948 if (ret.mr) {
1949 memory_region_ref(ret.mr);
1950 }
2b647668 1951 rcu_read_unlock();
e2177955
AK
1952 return ret;
1953}
1954
c6742b14
PB
1955bool memory_region_present(MemoryRegion *container, hwaddr addr)
1956{
1957 MemoryRegion *mr;
1958
1959 rcu_read_lock();
1960 mr = memory_region_find_rcu(container, addr, 1).mr;
1961 rcu_read_unlock();
1962 return mr && mr != container;
1963}
1964
1d671369 1965void address_space_sync_dirty_bitmap(AddressSpace *as)
86e775c6 1966{
99e86347 1967 FlatView *view;
7664e80c
AK
1968 FlatRange *fr;
1969
856d7245 1970 view = address_space_get_flatview(as);
99e86347 1971 FOR_EACH_FLAT_RANGE(fr, view) {
72e22d2f 1972 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, log_sync);
7664e80c 1973 }
856d7245 1974 flatview_unref(view);
7664e80c
AK
1975}
1976
1977void memory_global_dirty_log_start(void)
1978{
7664e80c 1979 global_dirty_log = true;
6f6a5ef3 1980
7376e582 1981 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3
PB
1982
1983 /* Refresh DIRTY_LOG_MIGRATION bit. */
1984 memory_region_transaction_begin();
1985 memory_region_update_pending = true;
1986 memory_region_transaction_commit();
7664e80c
AK
1987}
1988
1989void memory_global_dirty_log_stop(void)
1990{
7664e80c 1991 global_dirty_log = false;
6f6a5ef3
PB
1992
1993 /* Refresh DIRTY_LOG_MIGRATION bit. */
1994 memory_region_transaction_begin();
1995 memory_region_update_pending = true;
1996 memory_region_transaction_commit();
1997
7376e582 1998 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK
1999}
2000
2001static void listener_add_address_space(MemoryListener *listener,
2002 AddressSpace *as)
2003{
99e86347 2004 FlatView *view;
7664e80c
AK
2005 FlatRange *fr;
2006
221b3a3f 2007 if (listener->address_space_filter
f6790af6 2008 && listener->address_space_filter != as) {
221b3a3f
JG
2009 return;
2010 }
2011
7664e80c 2012 if (global_dirty_log) {
975aefe0
AK
2013 if (listener->log_global_start) {
2014 listener->log_global_start(listener);
2015 }
7664e80c 2016 }
975aefe0 2017
856d7245 2018 view = address_space_get_flatview(as);
99e86347 2019 FOR_EACH_FLAT_RANGE(fr, view) {
7664e80c
AK
2020 MemoryRegionSection section = {
2021 .mr = fr->mr,
f6790af6 2022 .address_space = as,
7664e80c 2023 .offset_within_region = fr->offset_in_region,
052e87b0 2024 .size = fr->addr.size,
7664e80c 2025 .offset_within_address_space = int128_get64(fr->addr.start),
7a8499e8 2026 .readonly = fr->readonly,
7664e80c 2027 };
975aefe0
AK
2028 if (listener->region_add) {
2029 listener->region_add(listener, &section);
2030 }
7664e80c 2031 }
856d7245 2032 flatview_unref(view);
7664e80c
AK
2033}
2034
f6790af6 2035void memory_listener_register(MemoryListener *listener, AddressSpace *filter)
7664e80c 2036{
72e22d2f 2037 MemoryListener *other = NULL;
0d673e36 2038 AddressSpace *as;
72e22d2f 2039
7376e582 2040 listener->address_space_filter = filter;
72e22d2f
AK
2041 if (QTAILQ_EMPTY(&memory_listeners)
2042 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2043 memory_listeners)->priority) {
2044 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2045 } else {
2046 QTAILQ_FOREACH(other, &memory_listeners, link) {
2047 if (listener->priority < other->priority) {
2048 break;
2049 }
2050 }
2051 QTAILQ_INSERT_BEFORE(other, listener, link);
2052 }
0d673e36
AK
2053
2054 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2055 listener_add_address_space(listener, as);
2056 }
7664e80c
AK
2057}
2058
2059void memory_listener_unregister(MemoryListener *listener)
2060{
72e22d2f 2061 QTAILQ_REMOVE(&memory_listeners, listener, link);
86e775c6 2062}
e2177955 2063
7dca8043 2064void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2065{
ac95190e 2066 memory_region_ref(root);
59023ef4 2067 memory_region_transaction_begin();
8786db7c
AK
2068 as->root = root;
2069 as->current_map = g_new(FlatView, 1);
2070 flatview_init(as->current_map);
4c19eb72
AK
2071 as->ioeventfd_nb = 0;
2072 as->ioeventfds = NULL;
0d673e36 2073 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2074 as->name = g_strdup(name ? name : "anonymous");
ac1970fb 2075 address_space_init_dispatch(as);
f43793c7
PB
2076 memory_region_update_pending |= root->enabled;
2077 memory_region_transaction_commit();
1c0ffa58 2078}
658b2224 2079
374f2981 2080static void do_address_space_destroy(AddressSpace *as)
83f3c251 2081{
078c44f4
DG
2082 MemoryListener *listener;
2083
83f3c251 2084 address_space_destroy_dispatch(as);
078c44f4
DG
2085
2086 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2087 assert(listener->address_space_filter != as);
2088 }
2089
856d7245 2090 flatview_unref(as->current_map);
7dca8043 2091 g_free(as->name);
4c19eb72 2092 g_free(as->ioeventfds);
ac95190e 2093 memory_region_unref(as->root);
83f3c251
AK
2094}
2095
374f2981
PB
2096void address_space_destroy(AddressSpace *as)
2097{
ac95190e
PB
2098 MemoryRegion *root = as->root;
2099
374f2981
PB
2100 /* Flush out anything from MemoryListeners listening in on this */
2101 memory_region_transaction_begin();
2102 as->root = NULL;
2103 memory_region_transaction_commit();
2104 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
6e48e8f9 2105 address_space_unregister(as);
374f2981
PB
2106
2107 /* At this point, as->dispatch and as->current_map are dummy
2108 * entries that the guest should never use. Wait for the old
2109 * values to expire before freeing the data.
2110 */
ac95190e 2111 as->root = root;
374f2981
PB
2112 call_rcu(as, do_address_space_destroy, rcu);
2113}
2114
314e2987
BS
2115typedef struct MemoryRegionList MemoryRegionList;
2116
2117struct MemoryRegionList {
2118 const MemoryRegion *mr;
314e2987
BS
2119 QTAILQ_ENTRY(MemoryRegionList) queue;
2120};
2121
2122typedef QTAILQ_HEAD(queue, MemoryRegionList) MemoryRegionListHead;
2123
2124static void mtree_print_mr(fprintf_function mon_printf, void *f,
2125 const MemoryRegion *mr, unsigned int level,
a8170e5e 2126 hwaddr base,
9479c57a 2127 MemoryRegionListHead *alias_print_queue)
314e2987 2128{
9479c57a
JK
2129 MemoryRegionList *new_ml, *ml, *next_ml;
2130 MemoryRegionListHead submr_print_queue;
314e2987
BS
2131 const MemoryRegion *submr;
2132 unsigned int i;
2133
f8a9f720 2134 if (!mr) {
314e2987
BS
2135 return;
2136 }
2137
2138 for (i = 0; i < level; i++) {
2139 mon_printf(f, " ");
2140 }
2141
2142 if (mr->alias) {
2143 MemoryRegionList *ml;
2144 bool found = false;
2145
2146 /* check if the alias is already in the queue */
9479c57a 2147 QTAILQ_FOREACH(ml, alias_print_queue, queue) {
f54bb15f 2148 if (ml->mr == mr->alias) {
314e2987
BS
2149 found = true;
2150 }
2151 }
2152
2153 if (!found) {
2154 ml = g_new(MemoryRegionList, 1);
2155 ml->mr = mr->alias;
9479c57a 2156 QTAILQ_INSERT_TAIL(alias_print_queue, ml, queue);
314e2987 2157 }
4896d74b
JK
2158 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
2159 " (prio %d, %c%c): alias %s @%s " TARGET_FMT_plx
f8a9f720 2160 "-" TARGET_FMT_plx "%s\n",
314e2987 2161 base + mr->addr,
08dafab4 2162 base + mr->addr
fd1d9926
AW
2163 + (int128_nz(mr->size) ?
2164 (hwaddr)int128_get64(int128_sub(mr->size,
2165 int128_one())) : 0),
4b474ba7 2166 mr->priority,
5f9a5ea1
JK
2167 mr->romd_mode ? 'R' : '-',
2168 !mr->readonly && !(mr->rom_device && mr->romd_mode) ? 'W'
2169 : '-',
3fb18b4d
PC
2170 memory_region_name(mr),
2171 memory_region_name(mr->alias),
314e2987 2172 mr->alias_offset,
08dafab4 2173 mr->alias_offset
a66670c7
AK
2174 + (int128_nz(mr->size) ?
2175 (hwaddr)int128_get64(int128_sub(mr->size,
f8a9f720
GH
2176 int128_one())) : 0),
2177 mr->enabled ? "" : " [disabled]");
314e2987 2178 } else {
4896d74b 2179 mon_printf(f,
f8a9f720 2180 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %c%c): %s%s\n",
314e2987 2181 base + mr->addr,
08dafab4 2182 base + mr->addr
fd1d9926
AW
2183 + (int128_nz(mr->size) ?
2184 (hwaddr)int128_get64(int128_sub(mr->size,
2185 int128_one())) : 0),
4b474ba7 2186 mr->priority,
5f9a5ea1
JK
2187 mr->romd_mode ? 'R' : '-',
2188 !mr->readonly && !(mr->rom_device && mr->romd_mode) ? 'W'
2189 : '-',
f8a9f720
GH
2190 memory_region_name(mr),
2191 mr->enabled ? "" : " [disabled]");
314e2987 2192 }
9479c57a
JK
2193
2194 QTAILQ_INIT(&submr_print_queue);
2195
314e2987 2196 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
2197 new_ml = g_new(MemoryRegionList, 1);
2198 new_ml->mr = submr;
2199 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
2200 if (new_ml->mr->addr < ml->mr->addr ||
2201 (new_ml->mr->addr == ml->mr->addr &&
2202 new_ml->mr->priority > ml->mr->priority)) {
2203 QTAILQ_INSERT_BEFORE(ml, new_ml, queue);
2204 new_ml = NULL;
2205 break;
2206 }
2207 }
2208 if (new_ml) {
2209 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, queue);
2210 }
2211 }
2212
2213 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
2214 mtree_print_mr(mon_printf, f, ml->mr, level + 1, base + mr->addr,
2215 alias_print_queue);
2216 }
2217
88365e47 2218 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, queue, next_ml) {
9479c57a 2219 g_free(ml);
314e2987
BS
2220 }
2221}
2222
2223void mtree_info(fprintf_function mon_printf, void *f)
2224{
2225 MemoryRegionListHead ml_head;
2226 MemoryRegionList *ml, *ml2;
0d673e36 2227 AddressSpace *as;
314e2987
BS
2228
2229 QTAILQ_INIT(&ml_head);
2230
0d673e36 2231 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
e48816aa
GH
2232 mon_printf(f, "address-space: %s\n", as->name);
2233 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
2234 mon_printf(f, "\n");
b9f9be88
BS
2235 }
2236
314e2987
BS
2237 /* print aliased regions */
2238 QTAILQ_FOREACH(ml, &ml_head, queue) {
e48816aa
GH
2239 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
2240 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
2241 mon_printf(f, "\n");
314e2987
BS
2242 }
2243
2244 QTAILQ_FOREACH_SAFE(ml, &ml_head, queue, ml2) {
88365e47 2245 g_free(ml);
314e2987 2246 }
314e2987 2247}
b4fefef9
PC
2248
2249static const TypeInfo memory_region_info = {
2250 .parent = TYPE_OBJECT,
2251 .name = TYPE_MEMORY_REGION,
2252 .instance_size = sizeof(MemoryRegion),
2253 .instance_init = memory_region_initfn,
2254 .instance_finalize = memory_region_finalize,
2255};
2256
2257static void memory_register_types(void)
2258{
2259 type_register_static(&memory_region_info);
2260}
2261
2262type_init(memory_register_types)