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memory: Move address_space_update_ioeventfds
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CommitLineData
093bc2cd
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1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
AK
14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879
PB
18#include "qemu-common.h"
19#include "cpu.h"
022c62cb
PB
20#include "exec/memory.h"
21#include "exec/address-spaces.h"
22#include "exec/ioport.h"
409ddd01 23#include "qapi/visitor.h"
1de7afc9 24#include "qemu/bitops.h"
8c56c1a5 25#include "qemu/error-report.h"
2c9b15ca 26#include "qom/object.h"
0ab8ed18 27#include "trace-root.h"
093bc2cd 28
022c62cb 29#include "exec/memory-internal.h"
220c3ebd 30#include "exec/ram_addr.h"
8c56c1a5 31#include "sysemu/kvm.h"
e1c57ab8 32#include "sysemu/sysemu.h"
c9356746
FK
33#include "hw/misc/mmio_interface.h"
34#include "hw/qdev-properties.h"
b08199c6 35#include "migration/vmstate.h"
67d95c15 36
d197063f
PB
37//#define DEBUG_UNASSIGNED
38
22bde714
JK
39static unsigned memory_region_transaction_depth;
40static bool memory_region_update_pending;
4dc56152 41static bool ioeventfd_update_pending;
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42static bool global_dirty_log = false;
43
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44static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
45 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 46
0d673e36
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47static QTAILQ_HEAD(, AddressSpace) address_spaces
48 = QTAILQ_HEAD_INITIALIZER(address_spaces);
49
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50typedef struct AddrRange AddrRange;
51
8417cebf 52/*
c9cdaa3a 53 * Note that signed integers are needed for negative offsetting in aliases
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54 * (large MemoryRegion::alias_offset).
55 */
093bc2cd 56struct AddrRange {
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57 Int128 start;
58 Int128 size;
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59};
60
08dafab4 61static AddrRange addrrange_make(Int128 start, Int128 size)
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62{
63 return (AddrRange) { start, size };
64}
65
66static bool addrrange_equal(AddrRange r1, AddrRange r2)
67{
08dafab4 68 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
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69}
70
08dafab4 71static Int128 addrrange_end(AddrRange r)
093bc2cd 72{
08dafab4 73 return int128_add(r.start, r.size);
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74}
75
08dafab4 76static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 77{
08dafab4 78 int128_addto(&range.start, delta);
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79 return range;
80}
81
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82static bool addrrange_contains(AddrRange range, Int128 addr)
83{
84 return int128_ge(addr, range.start)
85 && int128_lt(addr, addrrange_end(range));
86}
87
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88static bool addrrange_intersects(AddrRange r1, AddrRange r2)
89{
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90 return addrrange_contains(r1, r2.start)
91 || addrrange_contains(r2, r1.start);
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92}
93
94static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
95{
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96 Int128 start = int128_max(r1.start, r2.start);
97 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
98 return addrrange_make(start, int128_sub(end, start));
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99}
100
0e0d36b4
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101enum ListenerDirection { Forward, Reverse };
102
7376e582 103#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
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104 do { \
105 MemoryListener *_listener; \
106 \
107 switch (_direction) { \
108 case Forward: \
109 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
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110 if (_listener->_callback) { \
111 _listener->_callback(_listener, ##_args); \
112 } \
0e0d36b4
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113 } \
114 break; \
115 case Reverse: \
116 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
117 memory_listeners, link) { \
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118 if (_listener->_callback) { \
119 _listener->_callback(_listener, ##_args); \
120 } \
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121 } \
122 break; \
123 default: \
124 abort(); \
125 } \
126 } while (0)
127
9a54635d 128#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
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129 do { \
130 MemoryListener *_listener; \
9a54635d 131 struct memory_listeners_as *list = &(_as)->listeners; \
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132 \
133 switch (_direction) { \
134 case Forward: \
9a54635d
PB
135 QTAILQ_FOREACH(_listener, list, link_as) { \
136 if (_listener->_callback) { \
7376e582
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137 _listener->_callback(_listener, _section, ##_args); \
138 } \
139 } \
140 break; \
141 case Reverse: \
9a54635d
PB
142 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
143 link_as) { \
144 if (_listener->_callback) { \
7376e582
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145 _listener->_callback(_listener, _section, ##_args); \
146 } \
147 } \
148 break; \
149 default: \
150 abort(); \
151 } \
152 } while (0)
153
dfde4e6e 154/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 155#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44 156 do { \
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157 MemoryRegionSection mrs = section_from_flat_range(fr, \
158 address_space_to_flatview(as)); \
9a54635d 159 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 160 } while(0)
0e0d36b4 161
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162struct CoalescedMemoryRange {
163 AddrRange addr;
164 QTAILQ_ENTRY(CoalescedMemoryRange) link;
165};
166
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167struct MemoryRegionIoeventfd {
168 AddrRange addr;
169 bool match_data;
170 uint64_t data;
753d5e14 171 EventNotifier *e;
3e9d69e7
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172};
173
174static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
175 MemoryRegionIoeventfd b)
176{
08dafab4 177 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 178 return true;
08dafab4 179 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 180 return false;
08dafab4 181 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 182 return true;
08dafab4 183 } else if (int128_gt(a.addr.size, b.addr.size)) {
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184 return false;
185 } else if (a.match_data < b.match_data) {
186 return true;
187 } else if (a.match_data > b.match_data) {
188 return false;
189 } else if (a.match_data) {
190 if (a.data < b.data) {
191 return true;
192 } else if (a.data > b.data) {
193 return false;
194 }
195 }
753d5e14 196 if (a.e < b.e) {
3e9d69e7 197 return true;
753d5e14 198 } else if (a.e > b.e) {
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199 return false;
200 }
201 return false;
202}
203
204static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
205 MemoryRegionIoeventfd b)
206{
207 return !memory_region_ioeventfd_before(a, b)
208 && !memory_region_ioeventfd_before(b, a);
209}
210
093bc2cd 211typedef struct FlatRange FlatRange;
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212
213/* Range of memory in the global map. Addresses are absolute. */
214struct FlatRange {
215 MemoryRegion *mr;
a8170e5e 216 hwaddr offset_in_region;
093bc2cd 217 AddrRange addr;
5a583347 218 uint8_t dirty_log_mask;
b138e654 219 bool romd_mode;
fb1cd6f9 220 bool readonly;
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221};
222
223/* Flattened global view of current active memory hierarchy. Kept in sorted
224 * order.
225 */
226struct FlatView {
374f2981 227 struct rcu_head rcu;
856d7245 228 unsigned ref;
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229 FlatRange *ranges;
230 unsigned nr;
231 unsigned nr_allocated;
66a6df1d 232 struct AddressSpaceDispatch *dispatch;
89c177bb 233 MemoryRegion *root;
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234};
235
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236typedef struct AddressSpaceOps AddressSpaceOps;
237
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238#define FOR_EACH_FLAT_RANGE(var, view) \
239 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
240
9c1f8f44 241static inline MemoryRegionSection
16620684 242section_from_flat_range(FlatRange *fr, FlatView *fv)
9c1f8f44
PB
243{
244 return (MemoryRegionSection) {
245 .mr = fr->mr,
16620684 246 .fv = fv,
9c1f8f44
PB
247 .offset_within_region = fr->offset_in_region,
248 .size = fr->addr.size,
249 .offset_within_address_space = int128_get64(fr->addr.start),
250 .readonly = fr->readonly,
251 };
252}
253
093bc2cd
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254static bool flatrange_equal(FlatRange *a, FlatRange *b)
255{
256 return a->mr == b->mr
257 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 258 && a->offset_in_region == b->offset_in_region
b138e654 259 && a->romd_mode == b->romd_mode
fb1cd6f9 260 && a->readonly == b->readonly;
093bc2cd
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261}
262
89c177bb 263static FlatView *flatview_new(MemoryRegion *mr_root)
093bc2cd 264{
cc94cd6d
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265 FlatView *view;
266
267 view = g_new0(FlatView, 1);
856d7245 268 view->ref = 1;
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269 view->root = mr_root;
270 memory_region_ref(mr_root);
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271
272 return view;
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273}
274
275/* Insert a range into a given position. Caller is responsible for maintaining
276 * sorting order.
277 */
278static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
279{
280 if (view->nr == view->nr_allocated) {
281 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 282 view->ranges = g_realloc(view->ranges,
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283 view->nr_allocated * sizeof(*view->ranges));
284 }
285 memmove(view->ranges + pos + 1, view->ranges + pos,
286 (view->nr - pos) * sizeof(FlatRange));
287 view->ranges[pos] = *range;
dfde4e6e 288 memory_region_ref(range->mr);
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289 ++view->nr;
290}
291
292static void flatview_destroy(FlatView *view)
293{
dfde4e6e
PB
294 int i;
295
66a6df1d
AK
296 if (view->dispatch) {
297 address_space_dispatch_free(view->dispatch);
298 }
dfde4e6e
PB
299 for (i = 0; i < view->nr; i++) {
300 memory_region_unref(view->ranges[i].mr);
301 }
7267c094 302 g_free(view->ranges);
89c177bb 303 memory_region_unref(view->root);
a9a0c06d 304 g_free(view);
093bc2cd
AK
305}
306
447b0d0b 307static bool flatview_ref(FlatView *view)
856d7245 308{
447b0d0b 309 return atomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB
310}
311
312static void flatview_unref(FlatView *view)
313{
314 if (atomic_fetch_dec(&view->ref) == 1) {
66a6df1d 315 call_rcu(view, flatview_destroy, rcu);
856d7245
PB
316 }
317}
318
16620684 319FlatView *address_space_to_flatview(AddressSpace *as)
66a6df1d
AK
320{
321 return atomic_rcu_read(&as->current_map);
322}
323
324AddressSpaceDispatch *flatview_to_dispatch(FlatView *fv)
325{
326 return fv->dispatch;
327}
328
329AddressSpaceDispatch *address_space_to_dispatch(AddressSpace *as)
330{
331 return flatview_to_dispatch(address_space_to_flatview(as));
332}
333
3d8e6bf9
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334static bool can_merge(FlatRange *r1, FlatRange *r2)
335{
08dafab4 336 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 337 && r1->mr == r2->mr
08dafab4
AK
338 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
339 r1->addr.size),
340 int128_make64(r2->offset_in_region))
d0a9b5bc 341 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 342 && r1->romd_mode == r2->romd_mode
fb1cd6f9 343 && r1->readonly == r2->readonly;
3d8e6bf9
AK
344}
345
8508e024 346/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK
347static void flatview_simplify(FlatView *view)
348{
349 unsigned i, j;
350
351 i = 0;
352 while (i < view->nr) {
353 j = i + 1;
354 while (j < view->nr
355 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 356 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
AK
357 ++j;
358 }
359 ++i;
360 memmove(&view->ranges[i], &view->ranges[j],
361 (view->nr - j) * sizeof(view->ranges[j]));
362 view->nr -= j - i;
363 }
364}
365
e7342aa3
PB
366static bool memory_region_big_endian(MemoryRegion *mr)
367{
368#ifdef TARGET_WORDS_BIGENDIAN
369 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
370#else
371 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
372#endif
373}
374
e11ef3d1
PB
375static bool memory_region_wrong_endianness(MemoryRegion *mr)
376{
377#ifdef TARGET_WORDS_BIGENDIAN
378 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
379#else
380 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
381#endif
382}
383
384static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
385{
386 if (memory_region_wrong_endianness(mr)) {
387 switch (size) {
388 case 1:
389 break;
390 case 2:
391 *data = bswap16(*data);
392 break;
393 case 4:
394 *data = bswap32(*data);
395 break;
396 case 8:
397 *data = bswap64(*data);
398 break;
399 default:
400 abort();
401 }
402 }
403}
404
4779dc1d
HB
405static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
406{
407 MemoryRegion *root;
408 hwaddr abs_addr = offset;
409
410 abs_addr += mr->addr;
411 for (root = mr; root->container; ) {
412 root = root->container;
413 abs_addr += root->addr;
414 }
415
416 return abs_addr;
417}
418
5a68be94
HB
419static int get_cpu_index(void)
420{
421 if (current_cpu) {
422 return current_cpu->cpu_index;
423 }
424 return -1;
425}
426
cc05c43a
PM
427static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
428 hwaddr addr,
429 uint64_t *value,
430 unsigned size,
431 unsigned shift,
432 uint64_t mask,
433 MemTxAttrs attrs)
434{
435 uint64_t tmp;
436
437 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
23d92d68 438 if (mr->subpage) {
5a68be94 439 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
440 } else if (mr == &io_mem_notdirty) {
441 /* Accesses to code which has previously been translated into a TB show
442 * up in the MMIO path, as accesses to the io_mem_notdirty
443 * MemoryRegion. */
444 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
445 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
446 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 447 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 448 }
cc05c43a
PM
449 *value |= (tmp & mask) << shift;
450 return MEMTX_OK;
451}
452
453static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB
454 hwaddr addr,
455 uint64_t *value,
456 unsigned size,
457 unsigned shift,
cc05c43a
PM
458 uint64_t mask,
459 MemTxAttrs attrs)
ce5d2f33 460{
ce5d2f33
PB
461 uint64_t tmp;
462
cc05c43a 463 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 464 if (mr->subpage) {
5a68be94 465 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
466 } else if (mr == &io_mem_notdirty) {
467 /* Accesses to code which has previously been translated into a TB show
468 * up in the MMIO path, as accesses to the io_mem_notdirty
469 * MemoryRegion. */
470 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
471 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
472 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 473 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 474 }
ce5d2f33 475 *value |= (tmp & mask) << shift;
cc05c43a 476 return MEMTX_OK;
ce5d2f33
PB
477}
478
cc05c43a
PM
479static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
480 hwaddr addr,
481 uint64_t *value,
482 unsigned size,
483 unsigned shift,
484 uint64_t mask,
485 MemTxAttrs attrs)
164a4dcd 486{
cc05c43a
PM
487 uint64_t tmp = 0;
488 MemTxResult r;
164a4dcd 489
cc05c43a 490 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 491 if (mr->subpage) {
5a68be94 492 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
493 } else if (mr == &io_mem_notdirty) {
494 /* Accesses to code which has previously been translated into a TB show
495 * up in the MMIO path, as accesses to the io_mem_notdirty
496 * MemoryRegion. */
497 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
498 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
499 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 500 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 501 }
164a4dcd 502 *value |= (tmp & mask) << shift;
cc05c43a 503 return r;
164a4dcd
AK
504}
505
cc05c43a
PM
506static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
507 hwaddr addr,
508 uint64_t *value,
509 unsigned size,
510 unsigned shift,
511 uint64_t mask,
512 MemTxAttrs attrs)
ce5d2f33 513{
ce5d2f33
PB
514 uint64_t tmp;
515
516 tmp = (*value >> shift) & mask;
23d92d68 517 if (mr->subpage) {
5a68be94 518 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
519 } else if (mr == &io_mem_notdirty) {
520 /* Accesses to code which has previously been translated into a TB show
521 * up in the MMIO path, as accesses to the io_mem_notdirty
522 * MemoryRegion. */
523 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
524 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
525 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 526 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 527 }
ce5d2f33 528 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
cc05c43a 529 return MEMTX_OK;
ce5d2f33
PB
530}
531
cc05c43a
PM
532static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
533 hwaddr addr,
534 uint64_t *value,
535 unsigned size,
536 unsigned shift,
537 uint64_t mask,
538 MemTxAttrs attrs)
164a4dcd 539{
164a4dcd
AK
540 uint64_t tmp;
541
542 tmp = (*value >> shift) & mask;
23d92d68 543 if (mr->subpage) {
5a68be94 544 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
545 } else if (mr == &io_mem_notdirty) {
546 /* Accesses to code which has previously been translated into a TB show
547 * up in the MMIO path, as accesses to the io_mem_notdirty
548 * MemoryRegion. */
549 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
550 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
551 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 552 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 553 }
164a4dcd 554 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 555 return MEMTX_OK;
164a4dcd
AK
556}
557
cc05c43a
PM
558static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
559 hwaddr addr,
560 uint64_t *value,
561 unsigned size,
562 unsigned shift,
563 uint64_t mask,
564 MemTxAttrs attrs)
565{
566 uint64_t tmp;
567
cc05c43a 568 tmp = (*value >> shift) & mask;
23d92d68 569 if (mr->subpage) {
5a68be94 570 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
571 } else if (mr == &io_mem_notdirty) {
572 /* Accesses to code which has previously been translated into a TB show
573 * up in the MMIO path, as accesses to the io_mem_notdirty
574 * MemoryRegion. */
575 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
576 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
577 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 578 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 579 }
cc05c43a
PM
580 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
581}
582
583static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK
584 uint64_t *value,
585 unsigned size,
586 unsigned access_size_min,
587 unsigned access_size_max,
05e015f7
KF
588 MemTxResult (*access_fn)
589 (MemoryRegion *mr,
590 hwaddr addr,
591 uint64_t *value,
592 unsigned size,
593 unsigned shift,
594 uint64_t mask,
595 MemTxAttrs attrs),
cc05c43a
PM
596 MemoryRegion *mr,
597 MemTxAttrs attrs)
164a4dcd
AK
598{
599 uint64_t access_mask;
600 unsigned access_size;
601 unsigned i;
cc05c43a 602 MemTxResult r = MEMTX_OK;
164a4dcd
AK
603
604 if (!access_size_min) {
605 access_size_min = 1;
606 }
607 if (!access_size_max) {
608 access_size_max = 4;
609 }
ce5d2f33
PB
610
611 /* FIXME: support unaligned access? */
164a4dcd
AK
612 access_size = MAX(MIN(size, access_size_max), access_size_min);
613 access_mask = -1ULL >> (64 - access_size * 8);
e7342aa3
PB
614 if (memory_region_big_endian(mr)) {
615 for (i = 0; i < size; i += access_size) {
05e015f7 616 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 617 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB
618 }
619 } else {
620 for (i = 0; i < size; i += access_size) {
05e015f7 621 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 622 access_mask, attrs);
e7342aa3 623 }
164a4dcd 624 }
cc05c43a 625 return r;
164a4dcd
AK
626}
627
e2177955
AK
628static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
629{
0d673e36
AK
630 AddressSpace *as;
631
feca4ac1
PB
632 while (mr->container) {
633 mr = mr->container;
e2177955 634 }
0d673e36
AK
635 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
636 if (mr == as->root) {
637 return as;
638 }
e2177955 639 }
eed2bacf 640 return NULL;
e2177955
AK
641}
642
093bc2cd
AK
643/* Render a memory region into the global view. Ranges in @view obscure
644 * ranges in @mr.
645 */
646static void render_memory_region(FlatView *view,
647 MemoryRegion *mr,
08dafab4 648 Int128 base,
fb1cd6f9
AK
649 AddrRange clip,
650 bool readonly)
093bc2cd
AK
651{
652 MemoryRegion *subregion;
653 unsigned i;
a8170e5e 654 hwaddr offset_in_region;
08dafab4
AK
655 Int128 remain;
656 Int128 now;
093bc2cd
AK
657 FlatRange fr;
658 AddrRange tmp;
659
6bba19ba
AK
660 if (!mr->enabled) {
661 return;
662 }
663
08dafab4 664 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 665 readonly |= mr->readonly;
093bc2cd
AK
666
667 tmp = addrrange_make(base, mr->size);
668
669 if (!addrrange_intersects(tmp, clip)) {
670 return;
671 }
672
673 clip = addrrange_intersection(tmp, clip);
674
675 if (mr->alias) {
08dafab4
AK
676 int128_subfrom(&base, int128_make64(mr->alias->addr));
677 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 678 render_memory_region(view, mr->alias, base, clip, readonly);
093bc2cd
AK
679 return;
680 }
681
682 /* Render subregions in priority order. */
683 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 684 render_memory_region(view, subregion, base, clip, readonly);
093bc2cd
AK
685 }
686
14a3c10a 687 if (!mr->terminates) {
093bc2cd
AK
688 return;
689 }
690
08dafab4 691 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK
692 base = clip.start;
693 remain = clip.size;
694
2eb74e1a 695 fr.mr = mr;
6f6a5ef3 696 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 697 fr.romd_mode = mr->romd_mode;
2eb74e1a
PC
698 fr.readonly = readonly;
699
093bc2cd 700 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK
701 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
702 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK
703 continue;
704 }
08dafab4
AK
705 if (int128_lt(base, view->ranges[i].addr.start)) {
706 now = int128_min(remain,
707 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK
708 fr.offset_in_region = offset_in_region;
709 fr.addr = addrrange_make(base, now);
710 flatview_insert(view, i, &fr);
711 ++i;
08dafab4
AK
712 int128_addto(&base, now);
713 offset_in_region += int128_get64(now);
714 int128_subfrom(&remain, now);
093bc2cd 715 }
d26a8cae
AK
716 now = int128_sub(int128_min(int128_add(base, remain),
717 addrrange_end(view->ranges[i].addr)),
718 base);
719 int128_addto(&base, now);
720 offset_in_region += int128_get64(now);
721 int128_subfrom(&remain, now);
093bc2cd 722 }
08dafab4 723 if (int128_nz(remain)) {
093bc2cd
AK
724 fr.offset_in_region = offset_in_region;
725 fr.addr = addrrange_make(base, remain);
726 flatview_insert(view, i, &fr);
727 }
728}
729
89c177bb
AK
730static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
731{
732 while (mr->alias && !mr->alias_offset &&
733 int128_ge(mr->size, mr->alias->size)) {
734 /* The alias is included in its entirety. Use it as
735 * the "real" root, so that we can share more FlatViews.
736 */
737 mr = mr->alias;
738 }
739
740 return mr;
741}
742
093bc2cd 743/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 744static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 745{
9bf561e3 746 int i;
a9a0c06d 747 FlatView *view;
093bc2cd 748
89c177bb 749 view = flatview_new(mr);
093bc2cd 750
83f3c251 751 if (mr) {
a9a0c06d 752 render_memory_region(view, mr, int128_zero(),
83f3c251
AK
753 addrrange_make(int128_zero(), int128_2_64()), false);
754 }
a9a0c06d 755 flatview_simplify(view);
093bc2cd 756
9bf561e3
AK
757 view->dispatch = address_space_dispatch_new(view);
758 for (i = 0; i < view->nr; i++) {
759 MemoryRegionSection mrs =
760 section_from_flat_range(&view->ranges[i], view);
761 flatview_add_to_dispatch(view, &mrs);
762 }
763 address_space_dispatch_compact(view->dispatch);
764
093bc2cd
AK
765 return view;
766}
767
3e9d69e7
AK
768static void address_space_add_del_ioeventfds(AddressSpace *as,
769 MemoryRegionIoeventfd *fds_new,
770 unsigned fds_new_nb,
771 MemoryRegionIoeventfd *fds_old,
772 unsigned fds_old_nb)
773{
774 unsigned iold, inew;
80a1ea37
AK
775 MemoryRegionIoeventfd *fd;
776 MemoryRegionSection section;
3e9d69e7
AK
777
778 /* Generate a symmetric difference of the old and new fd sets, adding
779 * and deleting as necessary.
780 */
781
782 iold = inew = 0;
783 while (iold < fds_old_nb || inew < fds_new_nb) {
784 if (iold < fds_old_nb
785 && (inew == fds_new_nb
786 || memory_region_ioeventfd_before(fds_old[iold],
787 fds_new[inew]))) {
80a1ea37
AK
788 fd = &fds_old[iold];
789 section = (MemoryRegionSection) {
16620684 790 .fv = address_space_to_flatview(as),
80a1ea37 791 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 792 .size = fd->addr.size,
80a1ea37 793 };
9a54635d 794 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 795 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
796 ++iold;
797 } else if (inew < fds_new_nb
798 && (iold == fds_old_nb
799 || memory_region_ioeventfd_before(fds_new[inew],
800 fds_old[iold]))) {
80a1ea37
AK
801 fd = &fds_new[inew];
802 section = (MemoryRegionSection) {
16620684 803 .fv = address_space_to_flatview(as),
80a1ea37 804 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 805 .size = fd->addr.size,
80a1ea37 806 };
9a54635d 807 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 808 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
809 ++inew;
810 } else {
811 ++iold;
812 ++inew;
813 }
814 }
815}
816
856d7245
PB
817static FlatView *address_space_get_flatview(AddressSpace *as)
818{
819 FlatView *view;
820
374f2981 821 rcu_read_lock();
447b0d0b 822 do {
16620684 823 view = address_space_to_flatview(as);
447b0d0b
PB
824 /* If somebody has replaced as->current_map concurrently,
825 * flatview_ref returns false.
826 */
827 } while (!flatview_ref(view));
374f2981 828 rcu_read_unlock();
856d7245
PB
829 return view;
830}
831
3e9d69e7
AK
832static void address_space_update_ioeventfds(AddressSpace *as)
833{
99e86347 834 FlatView *view;
3e9d69e7
AK
835 FlatRange *fr;
836 unsigned ioeventfd_nb = 0;
837 MemoryRegionIoeventfd *ioeventfds = NULL;
838 AddrRange tmp;
839 unsigned i;
840
856d7245 841 view = address_space_get_flatview(as);
99e86347 842 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK
843 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
844 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK
845 int128_sub(fr->addr.start,
846 int128_make64(fr->offset_in_region)));
3e9d69e7
AK
847 if (addrrange_intersects(fr->addr, tmp)) {
848 ++ioeventfd_nb;
7267c094 849 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK
850 ioeventfd_nb * sizeof(*ioeventfds));
851 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
852 ioeventfds[ioeventfd_nb-1].addr = tmp;
853 }
854 }
855 }
856
857 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
858 as->ioeventfds, as->ioeventfd_nb);
859
7267c094 860 g_free(as->ioeventfds);
3e9d69e7
AK
861 as->ioeventfds = ioeventfds;
862 as->ioeventfd_nb = ioeventfd_nb;
856d7245 863 flatview_unref(view);
3e9d69e7
AK
864}
865
b8af1afb 866static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB
867 const FlatView *old_view,
868 const FlatView *new_view,
b8af1afb 869 bool adding)
093bc2cd 870{
093bc2cd
AK
871 unsigned iold, inew;
872 FlatRange *frold, *frnew;
093bc2cd
AK
873
874 /* Generate a symmetric difference of the old and new memory maps.
875 * Kill ranges in the old map, and instantiate ranges in the new map.
876 */
877 iold = inew = 0;
a9a0c06d
PB
878 while (iold < old_view->nr || inew < new_view->nr) {
879 if (iold < old_view->nr) {
880 frold = &old_view->ranges[iold];
093bc2cd
AK
881 } else {
882 frold = NULL;
883 }
a9a0c06d
PB
884 if (inew < new_view->nr) {
885 frnew = &new_view->ranges[inew];
093bc2cd
AK
886 } else {
887 frnew = NULL;
888 }
889
890 if (frold
891 && (!frnew
08dafab4
AK
892 || int128_lt(frold->addr.start, frnew->addr.start)
893 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 894 && !flatrange_equal(frold, frnew)))) {
41a6e477 895 /* In old but not in new, or in both but attributes changed. */
093bc2cd 896
b8af1afb 897 if (!adding) {
72e22d2f 898 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK
899 }
900
093bc2cd
AK
901 ++iold;
902 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 903 /* In both and unchanged (except logging may have changed) */
093bc2cd 904
b8af1afb 905 if (adding) {
50c1e149 906 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB
907 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
908 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
909 frold->dirty_log_mask,
910 frnew->dirty_log_mask);
911 }
912 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
913 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
914 frold->dirty_log_mask,
915 frnew->dirty_log_mask);
b8af1afb 916 }
5a583347
AK
917 }
918
093bc2cd
AK
919 ++iold;
920 ++inew;
093bc2cd
AK
921 } else {
922 /* In new */
923
b8af1afb 924 if (adding) {
72e22d2f 925 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK
926 }
927
093bc2cd
AK
928 ++inew;
929 }
930 }
b8af1afb
AK
931}
932
b8af1afb
AK
933static void address_space_update_topology(AddressSpace *as)
934{
856d7245 935 FlatView *old_view = address_space_get_flatview(as);
89c177bb
AK
936 MemoryRegion *physmr = memory_region_get_flatview_root(old_view->root);
937 FlatView *new_view = generate_memory_topology(physmr);
9a62e24f
AK
938
939 if (!QTAILQ_EMPTY(&as->listeners)) {
940 address_space_update_topology_pass(as, old_view, new_view, false);
941 address_space_update_topology_pass(as, old_view, new_view, true);
942 }
b8af1afb 943
374f2981
PB
944 /* Writes are protected by the BQL. */
945 atomic_rcu_set(&as->current_map, new_view);
66a6df1d 946 flatview_unref(old_view);
856d7245
PB
947
948 /* Note that all the old MemoryRegions are still alive up to this
949 * point. This relieves most MemoryListeners from the need to
950 * ref/unref the MemoryRegions they get---unless they use them
951 * outside the iothread mutex, in which case precise reference
952 * counting is necessary.
953 */
954 flatview_unref(old_view);
093bc2cd
AK
955}
956
4ef4db86
AK
957void memory_region_transaction_begin(void)
958{
bb880ded 959 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK
960 ++memory_region_transaction_depth;
961}
962
963void memory_region_transaction_commit(void)
964{
0d673e36
AK
965 AddressSpace *as;
966
4ef4db86 967 assert(memory_region_transaction_depth);
8d04fb55
JK
968 assert(qemu_mutex_iothread_locked());
969
4ef4db86 970 --memory_region_transaction_depth;
4dc56152
GA
971 if (!memory_region_transaction_depth) {
972 if (memory_region_update_pending) {
973 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 974
4dc56152
GA
975 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
976 address_space_update_topology(as);
02218487 977 address_space_update_ioeventfds(as);
4dc56152 978 }
ade9c1aa 979 memory_region_update_pending = false;
4dc56152
GA
980 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
981 } else if (ioeventfd_update_pending) {
982 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
983 address_space_update_ioeventfds(as);
984 }
ade9c1aa 985 ioeventfd_update_pending = false;
4dc56152 986 }
4dc56152 987 }
4ef4db86
AK
988}
989
545e92e0
AK
990static void memory_region_destructor_none(MemoryRegion *mr)
991{
992}
993
994static void memory_region_destructor_ram(MemoryRegion *mr)
995{
f1060c55 996 qemu_ram_free(mr->ram_block);
545e92e0
AK
997}
998
b4fefef9
PC
999static bool memory_region_need_escape(char c)
1000{
1001 return c == '/' || c == '[' || c == '\\' || c == ']';
1002}
1003
1004static char *memory_region_escape_name(const char *name)
1005{
1006 const char *p;
1007 char *escaped, *q;
1008 uint8_t c;
1009 size_t bytes = 0;
1010
1011 for (p = name; *p; p++) {
1012 bytes += memory_region_need_escape(*p) ? 4 : 1;
1013 }
1014 if (bytes == p - name) {
1015 return g_memdup(name, bytes + 1);
1016 }
1017
1018 escaped = g_malloc(bytes + 1);
1019 for (p = name, q = escaped; *p; p++) {
1020 c = *p;
1021 if (unlikely(memory_region_need_escape(c))) {
1022 *q++ = '\\';
1023 *q++ = 'x';
1024 *q++ = "0123456789abcdef"[c >> 4];
1025 c = "0123456789abcdef"[c & 15];
1026 }
1027 *q++ = c;
1028 }
1029 *q = 0;
1030 return escaped;
1031}
1032
3df9d748
AK
1033static void memory_region_do_init(MemoryRegion *mr,
1034 Object *owner,
1035 const char *name,
1036 uint64_t size)
093bc2cd 1037{
08dafab4
AK
1038 mr->size = int128_make64(size);
1039 if (size == UINT64_MAX) {
1040 mr->size = int128_2_64();
1041 }
302fa283 1042 mr->name = g_strdup(name);
612263cf 1043 mr->owner = owner;
58eaa217 1044 mr->ram_block = NULL;
b4fefef9
PC
1045
1046 if (name) {
843ef73a
PC
1047 char *escaped_name = memory_region_escape_name(name);
1048 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB
1049
1050 if (!owner) {
1051 owner = container_get(qdev_get_machine(), "/unattached");
1052 }
1053
843ef73a 1054 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1055 object_unref(OBJECT(mr));
843ef73a
PC
1056 g_free(name_array);
1057 g_free(escaped_name);
b4fefef9
PC
1058 }
1059}
1060
3df9d748
AK
1061void memory_region_init(MemoryRegion *mr,
1062 Object *owner,
1063 const char *name,
1064 uint64_t size)
1065{
1066 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1067 memory_region_do_init(mr, owner, name, size);
1068}
1069
d7bce999
EB
1070static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1071 void *opaque, Error **errp)
409ddd01
PC
1072{
1073 MemoryRegion *mr = MEMORY_REGION(obj);
1074 uint64_t value = mr->addr;
1075
51e72bc1 1076 visit_type_uint64(v, name, &value, errp);
409ddd01
PC
1077}
1078
d7bce999
EB
1079static void memory_region_get_container(Object *obj, Visitor *v,
1080 const char *name, void *opaque,
1081 Error **errp)
409ddd01
PC
1082{
1083 MemoryRegion *mr = MEMORY_REGION(obj);
1084 gchar *path = (gchar *)"";
1085
1086 if (mr->container) {
1087 path = object_get_canonical_path(OBJECT(mr->container));
1088 }
51e72bc1 1089 visit_type_str(v, name, &path, errp);
409ddd01
PC
1090 if (mr->container) {
1091 g_free(path);
1092 }
1093}
1094
1095static Object *memory_region_resolve_container(Object *obj, void *opaque,
1096 const char *part)
1097{
1098 MemoryRegion *mr = MEMORY_REGION(obj);
1099
1100 return OBJECT(mr->container);
1101}
1102
d7bce999
EB
1103static void memory_region_get_priority(Object *obj, Visitor *v,
1104 const char *name, void *opaque,
1105 Error **errp)
d33382da
PC
1106{
1107 MemoryRegion *mr = MEMORY_REGION(obj);
1108 int32_t value = mr->priority;
1109
51e72bc1 1110 visit_type_int32(v, name, &value, errp);
d33382da
PC
1111}
1112
d7bce999
EB
1113static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1114 void *opaque, Error **errp)
52aef7bb
PC
1115{
1116 MemoryRegion *mr = MEMORY_REGION(obj);
1117 uint64_t value = memory_region_size(mr);
1118
51e72bc1 1119 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC
1120}
1121
b4fefef9
PC
1122static void memory_region_initfn(Object *obj)
1123{
1124 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1125 ObjectProperty *op;
b4fefef9
PC
1126
1127 mr->ops = &unassigned_mem_ops;
6bba19ba 1128 mr->enabled = true;
5f9a5ea1 1129 mr->romd_mode = true;
196ea131 1130 mr->global_locking = true;
545e92e0 1131 mr->destructor = memory_region_destructor_none;
093bc2cd 1132 QTAILQ_INIT(&mr->subregions);
093bc2cd 1133 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC
1134
1135 op = object_property_add(OBJECT(mr), "container",
1136 "link<" TYPE_MEMORY_REGION ">",
1137 memory_region_get_container,
1138 NULL, /* memory_region_set_container */
1139 NULL, NULL, &error_abort);
1140 op->resolve = memory_region_resolve_container;
1141
1142 object_property_add(OBJECT(mr), "addr", "uint64",
1143 memory_region_get_addr,
1144 NULL, /* memory_region_set_addr */
1145 NULL, NULL, &error_abort);
d33382da
PC
1146 object_property_add(OBJECT(mr), "priority", "uint32",
1147 memory_region_get_priority,
1148 NULL, /* memory_region_set_priority */
1149 NULL, NULL, &error_abort);
52aef7bb
PC
1150 object_property_add(OBJECT(mr), "size", "uint64",
1151 memory_region_get_size,
1152 NULL, /* memory_region_set_size, */
1153 NULL, NULL, &error_abort);
093bc2cd
AK
1154}
1155
3df9d748
AK
1156static void iommu_memory_region_initfn(Object *obj)
1157{
1158 MemoryRegion *mr = MEMORY_REGION(obj);
1159
1160 mr->is_iommu = true;
1161}
1162
b018ddf6
PB
1163static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1164 unsigned size)
1165{
1166#ifdef DEBUG_UNASSIGNED
1167 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1168#endif
4917cf44
AF
1169 if (current_cpu != NULL) {
1170 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
c658b94f 1171 }
68a7439a 1172 return 0;
b018ddf6
PB
1173}
1174
1175static void unassigned_mem_write(void *opaque, hwaddr addr,
1176 uint64_t val, unsigned size)
1177{
1178#ifdef DEBUG_UNASSIGNED
1179 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1180#endif
4917cf44
AF
1181 if (current_cpu != NULL) {
1182 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1183 }
b018ddf6
PB
1184}
1185
d197063f
PB
1186static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1187 unsigned size, bool is_write)
1188{
1189 return false;
1190}
1191
1192const MemoryRegionOps unassigned_mem_ops = {
1193 .valid.accepts = unassigned_mem_accepts,
1194 .endianness = DEVICE_NATIVE_ENDIAN,
1195};
1196
4a2e242b
AW
1197static uint64_t memory_region_ram_device_read(void *opaque,
1198 hwaddr addr, unsigned size)
1199{
1200 MemoryRegion *mr = opaque;
1201 uint64_t data = (uint64_t)~0;
1202
1203 switch (size) {
1204 case 1:
1205 data = *(uint8_t *)(mr->ram_block->host + addr);
1206 break;
1207 case 2:
1208 data = *(uint16_t *)(mr->ram_block->host + addr);
1209 break;
1210 case 4:
1211 data = *(uint32_t *)(mr->ram_block->host + addr);
1212 break;
1213 case 8:
1214 data = *(uint64_t *)(mr->ram_block->host + addr);
1215 break;
1216 }
1217
1218 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1219
1220 return data;
1221}
1222
1223static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1224 uint64_t data, unsigned size)
1225{
1226 MemoryRegion *mr = opaque;
1227
1228 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1229
1230 switch (size) {
1231 case 1:
1232 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1233 break;
1234 case 2:
1235 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1236 break;
1237 case 4:
1238 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1239 break;
1240 case 8:
1241 *(uint64_t *)(mr->ram_block->host + addr) = data;
1242 break;
1243 }
1244}
1245
1246static const MemoryRegionOps ram_device_mem_ops = {
1247 .read = memory_region_ram_device_read,
1248 .write = memory_region_ram_device_write,
c99a29e7 1249 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW
1250 .valid = {
1251 .min_access_size = 1,
1252 .max_access_size = 8,
1253 .unaligned = true,
1254 },
1255 .impl = {
1256 .min_access_size = 1,
1257 .max_access_size = 8,
1258 .unaligned = true,
1259 },
1260};
1261
d2702032
PB
1262bool memory_region_access_valid(MemoryRegion *mr,
1263 hwaddr addr,
1264 unsigned size,
1265 bool is_write)
093bc2cd 1266{
a014ed07
PB
1267 int access_size_min, access_size_max;
1268 int access_size, i;
897fa7cf 1269
093bc2cd
AK
1270 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1271 return false;
1272 }
1273
a014ed07 1274 if (!mr->ops->valid.accepts) {
093bc2cd
AK
1275 return true;
1276 }
1277
a014ed07
PB
1278 access_size_min = mr->ops->valid.min_access_size;
1279 if (!mr->ops->valid.min_access_size) {
1280 access_size_min = 1;
1281 }
1282
1283 access_size_max = mr->ops->valid.max_access_size;
1284 if (!mr->ops->valid.max_access_size) {
1285 access_size_max = 4;
1286 }
1287
1288 access_size = MAX(MIN(size, access_size_max), access_size_min);
1289 for (i = 0; i < size; i += access_size) {
1290 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1291 is_write)) {
1292 return false;
1293 }
093bc2cd 1294 }
a014ed07 1295
093bc2cd
AK
1296 return true;
1297}
1298
cc05c43a
PM
1299static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1300 hwaddr addr,
1301 uint64_t *pval,
1302 unsigned size,
1303 MemTxAttrs attrs)
093bc2cd 1304{
cc05c43a 1305 *pval = 0;
093bc2cd 1306
ce5d2f33 1307 if (mr->ops->read) {
cc05c43a
PM
1308 return access_with_adjusted_size(addr, pval, size,
1309 mr->ops->impl.min_access_size,
1310 mr->ops->impl.max_access_size,
1311 memory_region_read_accessor,
1312 mr, attrs);
1313 } else if (mr->ops->read_with_attrs) {
1314 return access_with_adjusted_size(addr, pval, size,
1315 mr->ops->impl.min_access_size,
1316 mr->ops->impl.max_access_size,
1317 memory_region_read_with_attrs_accessor,
1318 mr, attrs);
ce5d2f33 1319 } else {
cc05c43a
PM
1320 return access_with_adjusted_size(addr, pval, size, 1, 4,
1321 memory_region_oldmmio_read_accessor,
1322 mr, attrs);
74901c3b 1323 }
093bc2cd
AK
1324}
1325
3b643495
PM
1326MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1327 hwaddr addr,
1328 uint64_t *pval,
1329 unsigned size,
1330 MemTxAttrs attrs)
a621f38d 1331{
cc05c43a
PM
1332 MemTxResult r;
1333
791af8c8
PB
1334 if (!memory_region_access_valid(mr, addr, size, false)) {
1335 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1336 return MEMTX_DECODE_ERROR;
791af8c8 1337 }
a621f38d 1338
cc05c43a 1339 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1340 adjust_endianness(mr, pval, size);
cc05c43a 1341 return r;
a621f38d 1342}
093bc2cd 1343
8c56c1a5
PF
1344/* Return true if an eventfd was signalled */
1345static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1346 hwaddr addr,
1347 uint64_t data,
1348 unsigned size,
1349 MemTxAttrs attrs)
1350{
1351 MemoryRegionIoeventfd ioeventfd = {
1352 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1353 .data = data,
1354 };
1355 unsigned i;
1356
1357 for (i = 0; i < mr->ioeventfd_nb; i++) {
1358 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1359 ioeventfd.e = mr->ioeventfds[i].e;
1360
1361 if (memory_region_ioeventfd_equal(ioeventfd, mr->ioeventfds[i])) {
1362 event_notifier_set(ioeventfd.e);
1363 return true;
1364 }
1365 }
1366
1367 return false;
1368}
1369
3b643495
PM
1370MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1371 hwaddr addr,
1372 uint64_t data,
1373 unsigned size,
1374 MemTxAttrs attrs)
a621f38d 1375{
897fa7cf 1376 if (!memory_region_access_valid(mr, addr, size, true)) {
b018ddf6 1377 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1378 return MEMTX_DECODE_ERROR;
093bc2cd
AK
1379 }
1380
a621f38d
AK
1381 adjust_endianness(mr, &data, size);
1382
8c56c1a5
PF
1383 if ((!kvm_eventfds_enabled()) &&
1384 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1385 return MEMTX_OK;
1386 }
1387
ce5d2f33 1388 if (mr->ops->write) {
cc05c43a
PM
1389 return access_with_adjusted_size(addr, &data, size,
1390 mr->ops->impl.min_access_size,
1391 mr->ops->impl.max_access_size,
1392 memory_region_write_accessor, mr,
1393 attrs);
1394 } else if (mr->ops->write_with_attrs) {
1395 return
1396 access_with_adjusted_size(addr, &data, size,
1397 mr->ops->impl.min_access_size,
1398 mr->ops->impl.max_access_size,
1399 memory_region_write_with_attrs_accessor,
1400 mr, attrs);
ce5d2f33 1401 } else {
cc05c43a
PM
1402 return access_with_adjusted_size(addr, &data, size, 1, 4,
1403 memory_region_oldmmio_write_accessor,
1404 mr, attrs);
74901c3b 1405 }
093bc2cd
AK
1406}
1407
093bc2cd 1408void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1409 Object *owner,
093bc2cd
AK
1410 const MemoryRegionOps *ops,
1411 void *opaque,
1412 const char *name,
1413 uint64_t size)
1414{
2c9b15ca 1415 memory_region_init(mr, owner, name, size);
6d6d2abf 1416 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1417 mr->opaque = opaque;
14a3c10a 1418 mr->terminates = true;
093bc2cd
AK
1419}
1420
1cfe48c1
PM
1421void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1422 Object *owner,
1423 const char *name,
1424 uint64_t size,
1425 Error **errp)
093bc2cd 1426{
2c9b15ca 1427 memory_region_init(mr, owner, name, size);
8ea9252a 1428 mr->ram = true;
14a3c10a 1429 mr->terminates = true;
545e92e0 1430 mr->destructor = memory_region_destructor_ram;
8e41fb63 1431 mr->ram_block = qemu_ram_alloc(size, mr, errp);
677e7805 1432 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
0b183fc8
PB
1433}
1434
60786ef3
MT
1435void memory_region_init_resizeable_ram(MemoryRegion *mr,
1436 Object *owner,
1437 const char *name,
1438 uint64_t size,
1439 uint64_t max_size,
1440 void (*resized)(const char*,
1441 uint64_t length,
1442 void *host),
1443 Error **errp)
1444{
1445 memory_region_init(mr, owner, name, size);
1446 mr->ram = true;
1447 mr->terminates = true;
1448 mr->destructor = memory_region_destructor_ram;
8e41fb63
FZ
1449 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1450 mr, errp);
677e7805 1451 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
60786ef3
MT
1452}
1453
0b183fc8
PB
1454#ifdef __linux__
1455void memory_region_init_ram_from_file(MemoryRegion *mr,
1456 struct Object *owner,
1457 const char *name,
1458 uint64_t size,
dbcb8981 1459 bool share,
7f56e740
PB
1460 const char *path,
1461 Error **errp)
0b183fc8
PB
1462{
1463 memory_region_init(mr, owner, name, size);
1464 mr->ram = true;
1465 mr->terminates = true;
1466 mr->destructor = memory_region_destructor_ram;
8e41fb63 1467 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
677e7805 1468 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
093bc2cd 1469}
fea617c5
MAL
1470
1471void memory_region_init_ram_from_fd(MemoryRegion *mr,
1472 struct Object *owner,
1473 const char *name,
1474 uint64_t size,
1475 bool share,
1476 int fd,
1477 Error **errp)
1478{
1479 memory_region_init(mr, owner, name, size);
1480 mr->ram = true;
1481 mr->terminates = true;
1482 mr->destructor = memory_region_destructor_ram;
1483 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1484 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1485}
0b183fc8 1486#endif
093bc2cd
AK
1487
1488void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1489 Object *owner,
093bc2cd
AK
1490 const char *name,
1491 uint64_t size,
1492 void *ptr)
1493{
2c9b15ca 1494 memory_region_init(mr, owner, name, size);
8ea9252a 1495 mr->ram = true;
14a3c10a 1496 mr->terminates = true;
fc3e7665 1497 mr->destructor = memory_region_destructor_ram;
677e7805 1498 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT
1499
1500 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1501 assert(ptr != NULL);
8e41fb63 1502 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK
1503}
1504
21e00fa5
AW
1505void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1506 Object *owner,
1507 const char *name,
1508 uint64_t size,
1509 void *ptr)
e4dc3f59 1510{
21e00fa5
AW
1511 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1512 mr->ram_device = true;
4a2e242b
AW
1513 mr->ops = &ram_device_mem_ops;
1514 mr->opaque = mr;
e4dc3f59
ND
1515}
1516
093bc2cd 1517void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1518 Object *owner,
093bc2cd
AK
1519 const char *name,
1520 MemoryRegion *orig,
a8170e5e 1521 hwaddr offset,
093bc2cd
AK
1522 uint64_t size)
1523{
2c9b15ca 1524 memory_region_init(mr, owner, name, size);
093bc2cd
AK
1525 mr->alias = orig;
1526 mr->alias_offset = offset;
1527}
1528
b59821a9
PM
1529void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1530 struct Object *owner,
1531 const char *name,
1532 uint64_t size,
1533 Error **errp)
a1777f7f
PM
1534{
1535 memory_region_init(mr, owner, name, size);
1536 mr->ram = true;
1537 mr->readonly = true;
1538 mr->terminates = true;
1539 mr->destructor = memory_region_destructor_ram;
1540 mr->ram_block = qemu_ram_alloc(size, mr, errp);
1541 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1542}
1543
b59821a9
PM
1544void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1545 Object *owner,
1546 const MemoryRegionOps *ops,
1547 void *opaque,
1548 const char *name,
1549 uint64_t size,
1550 Error **errp)
d0a9b5bc 1551{
39e0b03d 1552 assert(ops);
2c9b15ca 1553 memory_region_init(mr, owner, name, size);
7bc2b9cd 1554 mr->ops = ops;
75f5941c 1555 mr->opaque = opaque;
d0a9b5bc 1556 mr->terminates = true;
75c578dc 1557 mr->rom_device = true;
58268c8d 1558 mr->destructor = memory_region_destructor_ram;
8e41fb63 1559 mr->ram_block = qemu_ram_alloc(size, mr, errp);
d0a9b5bc
AK
1560}
1561
1221a474
AK
1562void memory_region_init_iommu(void *_iommu_mr,
1563 size_t instance_size,
1564 const char *mrtypename,
2c9b15ca 1565 Object *owner,
30951157
AK
1566 const char *name,
1567 uint64_t size)
1568{
1221a474 1569 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK
1570 struct MemoryRegion *mr;
1571
1221a474
AK
1572 object_initialize(_iommu_mr, instance_size, mrtypename);
1573 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK
1574 memory_region_do_init(mr, owner, name, size);
1575 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1576 mr->terminates = true; /* then re-forwards */
3df9d748
AK
1577 QLIST_INIT(&iommu_mr->iommu_notify);
1578 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK
1579}
1580
b4fefef9 1581static void memory_region_finalize(Object *obj)
093bc2cd 1582{
b4fefef9
PC
1583 MemoryRegion *mr = MEMORY_REGION(obj);
1584
2e2b8eb7
PB
1585 assert(!mr->container);
1586
1587 /* We know the region is not visible in any address space (it
1588 * does not have a container and cannot be a root either because
1589 * it has no references, so we can blindly clear mr->enabled.
1590 * memory_region_set_enabled instead could trigger a transaction
1591 * and cause an infinite loop.
1592 */
1593 mr->enabled = false;
1594 memory_region_transaction_begin();
1595 while (!QTAILQ_EMPTY(&mr->subregions)) {
1596 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1597 memory_region_del_subregion(mr, subregion);
1598 }
1599 memory_region_transaction_commit();
1600
545e92e0 1601 mr->destructor(mr);
093bc2cd 1602 memory_region_clear_coalescing(mr);
302fa283 1603 g_free((char *)mr->name);
7267c094 1604 g_free(mr->ioeventfds);
093bc2cd
AK
1605}
1606
803c0816
PB
1607Object *memory_region_owner(MemoryRegion *mr)
1608{
22a893e4
PB
1609 Object *obj = OBJECT(mr);
1610 return obj->parent;
803c0816
PB
1611}
1612
46637be2
PB
1613void memory_region_ref(MemoryRegion *mr)
1614{
22a893e4
PB
1615 /* MMIO callbacks most likely will access data that belongs
1616 * to the owner, hence the need to ref/unref the owner whenever
1617 * the memory region is in use.
1618 *
1619 * The memory region is a child of its owner. As long as the
1620 * owner doesn't call unparent itself on the memory region,
1621 * ref-ing the owner will also keep the memory region alive.
612263cf
PB
1622 * Memory regions without an owner are supposed to never go away;
1623 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1624 */
612263cf
PB
1625 if (mr && mr->owner) {
1626 object_ref(mr->owner);
46637be2
PB
1627 }
1628}
1629
1630void memory_region_unref(MemoryRegion *mr)
1631{
612263cf
PB
1632 if (mr && mr->owner) {
1633 object_unref(mr->owner);
46637be2
PB
1634 }
1635}
1636
093bc2cd
AK
1637uint64_t memory_region_size(MemoryRegion *mr)
1638{
08dafab4
AK
1639 if (int128_eq(mr->size, int128_2_64())) {
1640 return UINT64_MAX;
1641 }
1642 return int128_get64(mr->size);
093bc2cd
AK
1643}
1644
5d546d4b 1645const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1646{
d1dd32af
PC
1647 if (!mr->name) {
1648 ((MemoryRegion *)mr)->name =
1649 object_get_canonical_path_component(OBJECT(mr));
1650 }
302fa283 1651 return mr->name;
8991c79b
AK
1652}
1653
21e00fa5 1654bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1655{
21e00fa5 1656 return mr->ram_device;
e4dc3f59
ND
1657}
1658
2d1a35be 1659uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1660{
6f6a5ef3 1661 uint8_t mask = mr->dirty_log_mask;
adaad61c 1662 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB
1663 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1664 }
1665 return mask;
55043ba3
AK
1666}
1667
2d1a35be
PB
1668bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1669{
1670 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1671}
1672
3df9d748 1673static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
5bf3d319
PX
1674{
1675 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1676 IOMMUNotifier *iommu_notifier;
1221a474 1677 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
5bf3d319 1678
3df9d748 1679 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX
1680 flags |= iommu_notifier->notifier_flags;
1681 }
1682
1221a474
AK
1683 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1684 imrc->notify_flag_changed(iommu_mr,
1685 iommu_mr->iommu_notify_flags,
1686 flags);
5bf3d319
PX
1687 }
1688
3df9d748 1689 iommu_mr->iommu_notify_flags = flags;
5bf3d319
PX
1690}
1691
cdb30812
PX
1692void memory_region_register_iommu_notifier(MemoryRegion *mr,
1693 IOMMUNotifier *n)
06866575 1694{
3df9d748
AK
1695 IOMMUMemoryRegion *iommu_mr;
1696
efcd38c5
JW
1697 if (mr->alias) {
1698 memory_region_register_iommu_notifier(mr->alias, n);
1699 return;
1700 }
1701
cdb30812 1702 /* We need to register for at least one bitfield */
3df9d748 1703 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1704 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1705 assert(n->start <= n->end);
3df9d748
AK
1706 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1707 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1708}
1709
3df9d748 1710uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1711{
1221a474
AK
1712 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1713
1714 if (imrc->get_min_page_size) {
1715 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK
1716 }
1717 return TARGET_PAGE_SIZE;
1718}
1719
3df9d748 1720void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1721{
3df9d748 1722 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1723 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1724 hwaddr addr, granularity;
a788f227
DG
1725 IOMMUTLBEntry iotlb;
1726
faa362e3 1727 /* If the IOMMU has its own replay callback, override */
1221a474
AK
1728 if (imrc->replay) {
1729 imrc->replay(iommu_mr, n);
faa362e3
PX
1730 return;
1731 }
1732
3df9d748 1733 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1734
a788f227 1735 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1221a474 1736 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE);
a788f227
DG
1737 if (iotlb.perm != IOMMU_NONE) {
1738 n->notify(n, &iotlb);
1739 }
1740
1741 /* if (2^64 - MR size) < granularity, it's possible to get an
1742 * infinite loop here. This should catch such a wraparound */
1743 if ((addr + granularity) < addr) {
1744 break;
1745 }
1746 }
1747}
1748
3df9d748 1749void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
de472e4a
PX
1750{
1751 IOMMUNotifier *notifier;
1752
3df9d748
AK
1753 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1754 memory_region_iommu_replay(iommu_mr, notifier);
de472e4a
PX
1755 }
1756}
1757
cdb30812
PX
1758void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1759 IOMMUNotifier *n)
06866575 1760{
3df9d748
AK
1761 IOMMUMemoryRegion *iommu_mr;
1762
efcd38c5
JW
1763 if (mr->alias) {
1764 memory_region_unregister_iommu_notifier(mr->alias, n);
1765 return;
1766 }
cdb30812 1767 QLIST_REMOVE(n, node);
3df9d748
AK
1768 iommu_mr = IOMMU_MEMORY_REGION(mr);
1769 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1770}
1771
bd2bfa4c
PX
1772void memory_region_notify_one(IOMMUNotifier *notifier,
1773 IOMMUTLBEntry *entry)
06866575 1774{
cdb30812
PX
1775 IOMMUNotifierFlag request_flags;
1776
bd2bfa4c
PX
1777 /*
1778 * Skip the notification if the notification does not overlap
1779 * with registered range.
1780 */
1781 if (notifier->start > entry->iova + entry->addr_mask + 1 ||
1782 notifier->end < entry->iova) {
1783 return;
1784 }
cdb30812 1785
bd2bfa4c 1786 if (entry->perm & IOMMU_RW) {
cdb30812
PX
1787 request_flags = IOMMU_NOTIFIER_MAP;
1788 } else {
1789 request_flags = IOMMU_NOTIFIER_UNMAP;
1790 }
1791
bd2bfa4c
PX
1792 if (notifier->notifier_flags & request_flags) {
1793 notifier->notify(notifier, entry);
1794 }
1795}
1796
3df9d748 1797void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
bd2bfa4c
PX
1798 IOMMUTLBEntry entry)
1799{
1800 IOMMUNotifier *iommu_notifier;
1801
3df9d748 1802 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1803
3df9d748 1804 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
bd2bfa4c 1805 memory_region_notify_one(iommu_notifier, &entry);
cdb30812 1806 }
06866575
DG
1807}
1808
093bc2cd
AK
1809void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1810{
5a583347 1811 uint8_t mask = 1 << client;
deb809ed 1812 uint8_t old_logging;
5a583347 1813
dbddac6d 1814 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB
1815 old_logging = mr->vga_logging_count;
1816 mr->vga_logging_count += log ? 1 : -1;
1817 if (!!old_logging == !!mr->vga_logging_count) {
1818 return;
1819 }
1820
59023ef4 1821 memory_region_transaction_begin();
5a583347 1822 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1823 memory_region_update_pending |= mr->enabled;
59023ef4 1824 memory_region_transaction_commit();
093bc2cd
AK
1825}
1826
a8170e5e
AK
1827bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1828 hwaddr size, unsigned client)
093bc2cd 1829{
8e41fb63
FZ
1830 assert(mr->ram_block);
1831 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1832 size, client);
093bc2cd
AK
1833}
1834
a8170e5e
AK
1835void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1836 hwaddr size)
093bc2cd 1837{
8e41fb63
FZ
1838 assert(mr->ram_block);
1839 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1840 size,
58d2707e 1841 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK
1842}
1843
6c279db8
JQ
1844bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1845 hwaddr size, unsigned client)
1846{
8e41fb63
FZ
1847 assert(mr->ram_block);
1848 return cpu_physical_memory_test_and_clear_dirty(
1849 memory_region_get_ram_addr(mr) + addr, size, client);
6c279db8
JQ
1850}
1851
8deaf12c
GH
1852DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
1853 hwaddr addr,
1854 hwaddr size,
1855 unsigned client)
1856{
1857 assert(mr->ram_block);
1858 return cpu_physical_memory_snapshot_and_clear_dirty(
1859 memory_region_get_ram_addr(mr) + addr, size, client);
1860}
1861
1862bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
1863 hwaddr addr, hwaddr size)
1864{
1865 assert(mr->ram_block);
1866 return cpu_physical_memory_snapshot_get_dirty(snap,
1867 memory_region_get_ram_addr(mr) + addr, size);
1868}
6c279db8 1869
093bc2cd
AK
1870void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1871{
0a752eee 1872 MemoryListener *listener;
0d673e36 1873 AddressSpace *as;
0a752eee 1874 FlatView *view;
5a583347
AK
1875 FlatRange *fr;
1876
0a752eee
PB
1877 /* If the same address space has multiple log_sync listeners, we
1878 * visit that address space's FlatView multiple times. But because
1879 * log_sync listeners are rare, it's still cheaper than walking each
1880 * address space once.
1881 */
1882 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1883 if (!listener->log_sync) {
1884 continue;
1885 }
1886 as = listener->address_space;
1887 view = address_space_get_flatview(as);
99e86347 1888 FOR_EACH_FLAT_RANGE(fr, view) {
0d673e36 1889 if (fr->mr == mr) {
16620684 1890 MemoryRegionSection mrs = section_from_flat_range(fr, view);
0a752eee 1891 listener->log_sync(listener, &mrs);
0d673e36 1892 }
5a583347 1893 }
856d7245 1894 flatview_unref(view);
5a583347 1895 }
093bc2cd
AK
1896}
1897
1898void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1899{
fb1cd6f9 1900 if (mr->readonly != readonly) {
59023ef4 1901 memory_region_transaction_begin();
fb1cd6f9 1902 mr->readonly = readonly;
22bde714 1903 memory_region_update_pending |= mr->enabled;
59023ef4 1904 memory_region_transaction_commit();
fb1cd6f9 1905 }
093bc2cd
AK
1906}
1907
5f9a5ea1 1908void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 1909{
5f9a5ea1 1910 if (mr->romd_mode != romd_mode) {
59023ef4 1911 memory_region_transaction_begin();
5f9a5ea1 1912 mr->romd_mode = romd_mode;
22bde714 1913 memory_region_update_pending |= mr->enabled;
59023ef4 1914 memory_region_transaction_commit();
d0a9b5bc
AK
1915 }
1916}
1917
a8170e5e
AK
1918void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
1919 hwaddr size, unsigned client)
093bc2cd 1920{
8e41fb63
FZ
1921 assert(mr->ram_block);
1922 cpu_physical_memory_test_and_clear_dirty(
1923 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK
1924}
1925
a35ba7be
PB
1926int memory_region_get_fd(MemoryRegion *mr)
1927{
4ff87573
PB
1928 int fd;
1929
1930 rcu_read_lock();
1931 while (mr->alias) {
1932 mr = mr->alias;
a35ba7be 1933 }
4ff87573
PB
1934 fd = mr->ram_block->fd;
1935 rcu_read_unlock();
a35ba7be 1936
4ff87573
PB
1937 return fd;
1938}
a35ba7be 1939
093bc2cd
AK
1940void *memory_region_get_ram_ptr(MemoryRegion *mr)
1941{
49b24afc
PB
1942 void *ptr;
1943 uint64_t offset = 0;
093bc2cd 1944
49b24afc
PB
1945 rcu_read_lock();
1946 while (mr->alias) {
1947 offset += mr->alias_offset;
1948 mr = mr->alias;
1949 }
8e41fb63 1950 assert(mr->ram_block);
0878d0e1 1951 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
49b24afc 1952 rcu_read_unlock();
093bc2cd 1953
0878d0e1 1954 return ptr;
093bc2cd
AK
1955}
1956
07bdaa41
PB
1957MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
1958{
1959 RAMBlock *block;
1960
1961 block = qemu_ram_block_from_host(ptr, false, offset);
1962 if (!block) {
1963 return NULL;
1964 }
1965
1966 return block->mr;
1967}
1968
7ebb2745
FZ
1969ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
1970{
1971 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
1972}
1973
37d7c084
PB
1974void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
1975{
8e41fb63 1976 assert(mr->ram_block);
37d7c084 1977
fa53a0e5 1978 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB
1979}
1980
0d673e36 1981static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 1982{
99e86347 1983 FlatView *view;
093bc2cd
AK
1984 FlatRange *fr;
1985 CoalescedMemoryRange *cmr;
1986 AddrRange tmp;
95d2994a 1987 MemoryRegionSection section;
093bc2cd 1988
856d7245 1989 view = address_space_get_flatview(as);
99e86347 1990 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 1991 if (fr->mr == mr) {
95d2994a 1992 section = (MemoryRegionSection) {
16620684 1993 .fv = view,
95d2994a 1994 .offset_within_address_space = int128_get64(fr->addr.start),
052e87b0 1995 .size = fr->addr.size,
95d2994a
AK
1996 };
1997
9a54635d 1998 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
95d2994a
AK
1999 int128_get64(fr->addr.start),
2000 int128_get64(fr->addr.size));
093bc2cd
AK
2001 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
2002 tmp = addrrange_shift(cmr->addr,
08dafab4
AK
2003 int128_sub(fr->addr.start,
2004 int128_make64(fr->offset_in_region)));
093bc2cd
AK
2005 if (!addrrange_intersects(tmp, fr->addr)) {
2006 continue;
2007 }
2008 tmp = addrrange_intersection(tmp, fr->addr);
9a54635d 2009 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
95d2994a
AK
2010 int128_get64(tmp.start),
2011 int128_get64(tmp.size));
093bc2cd
AK
2012 }
2013 }
2014 }
856d7245 2015 flatview_unref(view);
093bc2cd
AK
2016}
2017
0d673e36
AK
2018static void memory_region_update_coalesced_range(MemoryRegion *mr)
2019{
2020 AddressSpace *as;
2021
2022 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2023 memory_region_update_coalesced_range_as(mr, as);
2024 }
2025}
2026
093bc2cd
AK
2027void memory_region_set_coalescing(MemoryRegion *mr)
2028{
2029 memory_region_clear_coalescing(mr);
08dafab4 2030 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK
2031}
2032
2033void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 2034 hwaddr offset,
093bc2cd
AK
2035 uint64_t size)
2036{
7267c094 2037 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2038
08dafab4 2039 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK
2040 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2041 memory_region_update_coalesced_range(mr);
d410515e 2042 memory_region_set_flush_coalesced(mr);
093bc2cd
AK
2043}
2044
2045void memory_region_clear_coalescing(MemoryRegion *mr)
2046{
2047 CoalescedMemoryRange *cmr;
ab5b3db5 2048 bool updated = false;
093bc2cd 2049
d410515e
JK
2050 qemu_flush_coalesced_mmio_buffer();
2051 mr->flush_coalesced_mmio = false;
2052
093bc2cd
AK
2053 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2054 cmr = QTAILQ_FIRST(&mr->coalesced);
2055 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 2056 g_free(cmr);
ab5b3db5
FZ
2057 updated = true;
2058 }
2059
2060 if (updated) {
2061 memory_region_update_coalesced_range(mr);
093bc2cd 2062 }
093bc2cd
AK
2063}
2064
d410515e
JK
2065void memory_region_set_flush_coalesced(MemoryRegion *mr)
2066{
2067 mr->flush_coalesced_mmio = true;
2068}
2069
2070void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2071{
2072 qemu_flush_coalesced_mmio_buffer();
2073 if (QTAILQ_EMPTY(&mr->coalesced)) {
2074 mr->flush_coalesced_mmio = false;
2075 }
2076}
2077
196ea131
JK
2078void memory_region_set_global_locking(MemoryRegion *mr)
2079{
2080 mr->global_locking = true;
2081}
2082
2083void memory_region_clear_global_locking(MemoryRegion *mr)
2084{
2085 mr->global_locking = false;
2086}
2087
8c56c1a5
PF
2088static bool userspace_eventfd_warning;
2089
3e9d69e7 2090void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2091 hwaddr addr,
3e9d69e7
AK
2092 unsigned size,
2093 bool match_data,
2094 uint64_t data,
753d5e14 2095 EventNotifier *e)
3e9d69e7
AK
2096{
2097 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2098 .addr.start = int128_make64(addr),
2099 .addr.size = int128_make64(size),
3e9d69e7
AK
2100 .match_data = match_data,
2101 .data = data,
753d5e14 2102 .e = e,
3e9d69e7
AK
2103 };
2104 unsigned i;
2105
8c56c1a5
PF
2106 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2107 userspace_eventfd_warning))) {
2108 userspace_eventfd_warning = true;
2109 error_report("Using eventfd without MMIO binding in KVM. "
2110 "Suboptimal performance expected");
2111 }
2112
b8aecea2
JW
2113 if (size) {
2114 adjust_endianness(mr, &mrfd.data, size);
2115 }
59023ef4 2116 memory_region_transaction_begin();
3e9d69e7
AK
2117 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2118 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
2119 break;
2120 }
2121 }
2122 ++mr->ioeventfd_nb;
7267c094 2123 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK
2124 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2125 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2126 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2127 mr->ioeventfds[i] = mrfd;
4dc56152 2128 ioeventfd_update_pending |= mr->enabled;
59023ef4 2129 memory_region_transaction_commit();
3e9d69e7
AK
2130}
2131
2132void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2133 hwaddr addr,
3e9d69e7
AK
2134 unsigned size,
2135 bool match_data,
2136 uint64_t data,
753d5e14 2137 EventNotifier *e)
3e9d69e7
AK
2138{
2139 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2140 .addr.start = int128_make64(addr),
2141 .addr.size = int128_make64(size),
3e9d69e7
AK
2142 .match_data = match_data,
2143 .data = data,
753d5e14 2144 .e = e,
3e9d69e7
AK
2145 };
2146 unsigned i;
2147
b8aecea2
JW
2148 if (size) {
2149 adjust_endianness(mr, &mrfd.data, size);
2150 }
59023ef4 2151 memory_region_transaction_begin();
3e9d69e7
AK
2152 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2153 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
2154 break;
2155 }
2156 }
2157 assert(i != mr->ioeventfd_nb);
2158 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2159 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2160 --mr->ioeventfd_nb;
7267c094 2161 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2162 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2163 ioeventfd_update_pending |= mr->enabled;
59023ef4 2164 memory_region_transaction_commit();
3e9d69e7
AK
2165}
2166
feca4ac1 2167static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2168{
feca4ac1 2169 MemoryRegion *mr = subregion->container;
093bc2cd
AK
2170 MemoryRegion *other;
2171
59023ef4
JK
2172 memory_region_transaction_begin();
2173
dfde4e6e 2174 memory_region_ref(subregion);
093bc2cd
AK
2175 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2176 if (subregion->priority >= other->priority) {
2177 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2178 goto done;
2179 }
2180 }
2181 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2182done:
22bde714 2183 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2184 memory_region_transaction_commit();
093bc2cd
AK
2185}
2186
0598701a
PC
2187static void memory_region_add_subregion_common(MemoryRegion *mr,
2188 hwaddr offset,
2189 MemoryRegion *subregion)
2190{
feca4ac1
PB
2191 assert(!subregion->container);
2192 subregion->container = mr;
0598701a 2193 subregion->addr = offset;
feca4ac1 2194 memory_region_update_container_subregions(subregion);
0598701a 2195}
093bc2cd
AK
2196
2197void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2198 hwaddr offset,
093bc2cd
AK
2199 MemoryRegion *subregion)
2200{
093bc2cd
AK
2201 subregion->priority = 0;
2202 memory_region_add_subregion_common(mr, offset, subregion);
2203}
2204
2205void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2206 hwaddr offset,
093bc2cd 2207 MemoryRegion *subregion,
a1ff8ae0 2208 int priority)
093bc2cd 2209{
093bc2cd
AK
2210 subregion->priority = priority;
2211 memory_region_add_subregion_common(mr, offset, subregion);
2212}
2213
2214void memory_region_del_subregion(MemoryRegion *mr,
2215 MemoryRegion *subregion)
2216{
59023ef4 2217 memory_region_transaction_begin();
feca4ac1
PB
2218 assert(subregion->container == mr);
2219 subregion->container = NULL;
093bc2cd 2220 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2221 memory_region_unref(subregion);
22bde714 2222 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2223 memory_region_transaction_commit();
6bba19ba
AK
2224}
2225
2226void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2227{
2228 if (enabled == mr->enabled) {
2229 return;
2230 }
59023ef4 2231 memory_region_transaction_begin();
6bba19ba 2232 mr->enabled = enabled;
22bde714 2233 memory_region_update_pending = true;
59023ef4 2234 memory_region_transaction_commit();
093bc2cd 2235}
1c0ffa58 2236
e7af4c67
MT
2237void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2238{
2239 Int128 s = int128_make64(size);
2240
2241 if (size == UINT64_MAX) {
2242 s = int128_2_64();
2243 }
2244 if (int128_eq(s, mr->size)) {
2245 return;
2246 }
2247 memory_region_transaction_begin();
2248 mr->size = s;
2249 memory_region_update_pending = true;
2250 memory_region_transaction_commit();
2251}
2252
67891b8a 2253static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2254{
feca4ac1 2255 MemoryRegion *container = mr->container;
2282e1af 2256
feca4ac1 2257 if (container) {
67891b8a
PC
2258 memory_region_transaction_begin();
2259 memory_region_ref(mr);
feca4ac1
PB
2260 memory_region_del_subregion(container, mr);
2261 mr->container = container;
2262 memory_region_update_container_subregions(mr);
67891b8a
PC
2263 memory_region_unref(mr);
2264 memory_region_transaction_commit();
2282e1af 2265 }
67891b8a 2266}
2282e1af 2267
67891b8a
PC
2268void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2269{
2270 if (addr != mr->addr) {
2271 mr->addr = addr;
2272 memory_region_readd_subregion(mr);
2273 }
2282e1af
AK
2274}
2275
a8170e5e 2276void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2277{
4703359e 2278 assert(mr->alias);
4703359e 2279
59023ef4 2280 if (offset == mr->alias_offset) {
4703359e
AK
2281 return;
2282 }
2283
59023ef4
JK
2284 memory_region_transaction_begin();
2285 mr->alias_offset = offset;
22bde714 2286 memory_region_update_pending |= mr->enabled;
59023ef4 2287 memory_region_transaction_commit();
4703359e
AK
2288}
2289
a2b257d6
IM
2290uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2291{
2292 return mr->align;
2293}
2294
e2177955
AK
2295static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2296{
2297 const AddrRange *addr = addr_;
2298 const FlatRange *fr = fr_;
2299
2300 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2301 return -1;
2302 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2303 return 1;
2304 }
2305 return 0;
2306}
2307
99e86347 2308static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2309{
99e86347 2310 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK
2311 sizeof(FlatRange), cmp_flatrange_addr);
2312}
2313
eed2bacf
IM
2314bool memory_region_is_mapped(MemoryRegion *mr)
2315{
2316 return mr->container ? true : false;
2317}
2318
c6742b14
PB
2319/* Same as memory_region_find, but it does not add a reference to the
2320 * returned region. It must be called from an RCU critical section.
2321 */
2322static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2323 hwaddr addr, uint64_t size)
e2177955 2324{
052e87b0 2325 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB
2326 MemoryRegion *root;
2327 AddressSpace *as;
2328 AddrRange range;
99e86347 2329 FlatView *view;
73034e9e
PB
2330 FlatRange *fr;
2331
2332 addr += mr->addr;
feca4ac1
PB
2333 for (root = mr; root->container; ) {
2334 root = root->container;
73034e9e
PB
2335 addr += root->addr;
2336 }
e2177955 2337
73034e9e 2338 as = memory_region_to_address_space(root);
eed2bacf
IM
2339 if (!as) {
2340 return ret;
2341 }
73034e9e 2342 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2343
16620684 2344 view = address_space_to_flatview(as);
99e86347 2345 fr = flatview_lookup(view, range);
e2177955 2346 if (!fr) {
c6742b14 2347 return ret;
e2177955
AK
2348 }
2349
99e86347 2350 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK
2351 --fr;
2352 }
2353
2354 ret.mr = fr->mr;
16620684 2355 ret.fv = view;
e2177955
AK
2356 range = addrrange_intersection(range, fr->addr);
2357 ret.offset_within_region = fr->offset_in_region;
2358 ret.offset_within_region += int128_get64(int128_sub(range.start,
2359 fr->addr.start));
052e87b0 2360 ret.size = range.size;
e2177955 2361 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2362 ret.readonly = fr->readonly;
c6742b14
PB
2363 return ret;
2364}
2365
2366MemoryRegionSection memory_region_find(MemoryRegion *mr,
2367 hwaddr addr, uint64_t size)
2368{
2369 MemoryRegionSection ret;
2370 rcu_read_lock();
2371 ret = memory_region_find_rcu(mr, addr, size);
2372 if (ret.mr) {
2373 memory_region_ref(ret.mr);
2374 }
2b647668 2375 rcu_read_unlock();
e2177955
AK
2376 return ret;
2377}
2378
c6742b14
PB
2379bool memory_region_present(MemoryRegion *container, hwaddr addr)
2380{
2381 MemoryRegion *mr;
2382
2383 rcu_read_lock();
2384 mr = memory_region_find_rcu(container, addr, 1).mr;
2385 rcu_read_unlock();
2386 return mr && mr != container;
2387}
2388
9c1f8f44 2389void memory_global_dirty_log_sync(void)
86e775c6 2390{
9c1f8f44
PB
2391 MemoryListener *listener;
2392 AddressSpace *as;
99e86347 2393 FlatView *view;
7664e80c
AK
2394 FlatRange *fr;
2395
9c1f8f44
PB
2396 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2397 if (!listener->log_sync) {
2398 continue;
2399 }
d45fa784 2400 as = listener->address_space;
9c1f8f44
PB
2401 view = address_space_get_flatview(as);
2402 FOR_EACH_FLAT_RANGE(fr, view) {
adaad61c 2403 if (fr->dirty_log_mask) {
16620684
AK
2404 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2405
adaad61c
PB
2406 listener->log_sync(listener, &mrs);
2407 }
9c1f8f44
PB
2408 }
2409 flatview_unref(view);
7664e80c
AK
2410 }
2411}
2412
19310760
JZ
2413static VMChangeStateEntry *vmstate_change;
2414
7664e80c
AK
2415void memory_global_dirty_log_start(void)
2416{
19310760
JZ
2417 if (vmstate_change) {
2418 qemu_del_vm_change_state_handler(vmstate_change);
2419 vmstate_change = NULL;
2420 }
2421
7664e80c 2422 global_dirty_log = true;
6f6a5ef3 2423
7376e582 2424 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3
PB
2425
2426 /* Refresh DIRTY_LOG_MIGRATION bit. */
2427 memory_region_transaction_begin();
2428 memory_region_update_pending = true;
2429 memory_region_transaction_commit();
7664e80c
AK
2430}
2431
19310760 2432static void memory_global_dirty_log_do_stop(void)
7664e80c 2433{
7664e80c 2434 global_dirty_log = false;
6f6a5ef3
PB
2435
2436 /* Refresh DIRTY_LOG_MIGRATION bit. */
2437 memory_region_transaction_begin();
2438 memory_region_update_pending = true;
2439 memory_region_transaction_commit();
2440
7376e582 2441 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK
2442}
2443
19310760
JZ
2444static void memory_vm_change_state_handler(void *opaque, int running,
2445 RunState state)
2446{
2447 if (running) {
2448 memory_global_dirty_log_do_stop();
2449
2450 if (vmstate_change) {
2451 qemu_del_vm_change_state_handler(vmstate_change);
2452 vmstate_change = NULL;
2453 }
2454 }
2455}
2456
2457void memory_global_dirty_log_stop(void)
2458{
2459 if (!runstate_is_running()) {
2460 if (vmstate_change) {
2461 return;
2462 }
2463 vmstate_change = qemu_add_vm_change_state_handler(
2464 memory_vm_change_state_handler, NULL);
2465 return;
2466 }
2467
2468 memory_global_dirty_log_do_stop();
2469}
2470
7664e80c
AK
2471static void listener_add_address_space(MemoryListener *listener,
2472 AddressSpace *as)
2473{
99e86347 2474 FlatView *view;
7664e80c
AK
2475 FlatRange *fr;
2476
680a4783
PB
2477 if (listener->begin) {
2478 listener->begin(listener);
2479 }
7664e80c 2480 if (global_dirty_log) {
975aefe0
AK
2481 if (listener->log_global_start) {
2482 listener->log_global_start(listener);
2483 }
7664e80c 2484 }
975aefe0 2485
856d7245 2486 view = address_space_get_flatview(as);
99e86347 2487 FOR_EACH_FLAT_RANGE(fr, view) {
7664e80c
AK
2488 MemoryRegionSection section = {
2489 .mr = fr->mr,
16620684 2490 .fv = view,
7664e80c 2491 .offset_within_region = fr->offset_in_region,
052e87b0 2492 .size = fr->addr.size,
7664e80c 2493 .offset_within_address_space = int128_get64(fr->addr.start),
7a8499e8 2494 .readonly = fr->readonly,
7664e80c 2495 };
680a4783
PB
2496 if (fr->dirty_log_mask && listener->log_start) {
2497 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2498 }
975aefe0
AK
2499 if (listener->region_add) {
2500 listener->region_add(listener, &section);
2501 }
7664e80c 2502 }
680a4783
PB
2503 if (listener->commit) {
2504 listener->commit(listener);
2505 }
856d7245 2506 flatview_unref(view);
7664e80c
AK
2507}
2508
d45fa784 2509void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2510{
72e22d2f
AK
2511 MemoryListener *other = NULL;
2512
d45fa784 2513 listener->address_space = as;
72e22d2f
AK
2514 if (QTAILQ_EMPTY(&memory_listeners)
2515 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2516 memory_listeners)->priority) {
2517 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2518 } else {
2519 QTAILQ_FOREACH(other, &memory_listeners, link) {
2520 if (listener->priority < other->priority) {
2521 break;
2522 }
2523 }
2524 QTAILQ_INSERT_BEFORE(other, listener, link);
2525 }
0d673e36 2526
9a54635d
PB
2527 if (QTAILQ_EMPTY(&as->listeners)
2528 || listener->priority >= QTAILQ_LAST(&as->listeners,
2529 memory_listeners)->priority) {
2530 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2531 } else {
2532 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2533 if (listener->priority < other->priority) {
2534 break;
2535 }
2536 }
2537 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2538 }
2539
d45fa784 2540 listener_add_address_space(listener, as);
7664e80c
AK
2541}
2542
2543void memory_listener_unregister(MemoryListener *listener)
2544{
1d8280c1
PB
2545 if (!listener->address_space) {
2546 return;
2547 }
2548
72e22d2f 2549 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2550 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2551 listener->address_space = NULL;
86e775c6 2552}
e2177955 2553
c9356746
FK
2554bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2555{
2556 void *host;
2557 unsigned size = 0;
2558 unsigned offset = 0;
2559 Object *new_interface;
2560
2561 if (!mr || !mr->ops->request_ptr) {
2562 return false;
2563 }
2564
2565 /*
2566 * Avoid an update if the request_ptr call
2567 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2568 * a cache.
2569 */
2570 memory_region_transaction_begin();
2571
2572 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2573
2574 if (!host || !size) {
2575 memory_region_transaction_commit();
2576 return false;
2577 }
2578
2579 new_interface = object_new("mmio_interface");
2580 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2581 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2582 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2583 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2584 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2585 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2586
2587 memory_region_transaction_commit();
2588 return true;
2589}
2590
2591typedef struct MMIOPtrInvalidate {
2592 MemoryRegion *mr;
2593 hwaddr offset;
2594 unsigned size;
2595 int busy;
2596 int allocated;
2597} MMIOPtrInvalidate;
2598
2599#define MAX_MMIO_INVALIDATE 10
2600static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2601
2602static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2603 run_on_cpu_data data)
2604{
2605 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2606 MemoryRegion *mr = invalidate_data->mr;
2607 hwaddr offset = invalidate_data->offset;
2608 unsigned size = invalidate_data->size;
2609 MemoryRegionSection section = memory_region_find(mr, offset, size);
2610
2611 qemu_mutex_lock_iothread();
2612
2613 /* Reset dirty so this doesn't happen later. */
2614 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2615
2616 if (section.mr != mr) {
2617 /* memory_region_find add a ref on section.mr */
2618 memory_region_unref(section.mr);
2619 if (MMIO_INTERFACE(section.mr->owner)) {
2620 /* We found the interface just drop it. */
2621 object_property_set_bool(section.mr->owner, false, "realized",
2622 NULL);
2623 object_unref(section.mr->owner);
2624 object_unparent(section.mr->owner);
2625 }
2626 }
2627
2628 qemu_mutex_unlock_iothread();
2629
2630 if (invalidate_data->allocated) {
2631 g_free(invalidate_data);
2632 } else {
2633 invalidate_data->busy = 0;
2634 }
2635}
2636
2637void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2638 unsigned size)
2639{
2640 size_t i;
2641 MMIOPtrInvalidate *invalidate_data = NULL;
2642
2643 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2644 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2645 invalidate_data = &mmio_ptr_invalidate_list[i];
2646 break;
2647 }
2648 }
2649
2650 if (!invalidate_data) {
2651 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2652 invalidate_data->allocated = 1;
2653 }
2654
2655 invalidate_data->mr = mr;
2656 invalidate_data->offset = offset;
2657 invalidate_data->size = size;
2658
2659 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2660 RUN_ON_CPU_HOST_PTR(invalidate_data));
2661}
2662
7dca8043 2663void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2664{
ac95190e 2665 memory_region_ref(root);
59023ef4 2666 memory_region_transaction_begin();
f0c02d15 2667 as->ref_count = 1;
8786db7c 2668 as->root = root;
f0c02d15 2669 as->malloced = false;
89c177bb 2670 as->current_map = flatview_new(root);
4c19eb72
AK
2671 as->ioeventfd_nb = 0;
2672 as->ioeventfds = NULL;
9a54635d 2673 QTAILQ_INIT(&as->listeners);
0d673e36 2674 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2675 as->name = g_strdup(name ? name : "anonymous");
f43793c7
PB
2676 memory_region_update_pending |= root->enabled;
2677 memory_region_transaction_commit();
1c0ffa58 2678}
658b2224 2679
374f2981 2680static void do_address_space_destroy(AddressSpace *as)
83f3c251 2681{
f0c02d15 2682 bool do_free = as->malloced;
078c44f4 2683
9a54635d 2684 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2685
856d7245 2686 flatview_unref(as->current_map);
7dca8043 2687 g_free(as->name);
4c19eb72 2688 g_free(as->ioeventfds);
ac95190e 2689 memory_region_unref(as->root);
f0c02d15
PC
2690 if (do_free) {
2691 g_free(as);
2692 }
2693}
2694
2695AddressSpace *address_space_init_shareable(MemoryRegion *root, const char *name)
2696{
2697 AddressSpace *as;
2698
2699 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2700 if (root == as->root && as->malloced) {
2701 as->ref_count++;
2702 return as;
2703 }
2704 }
2705
2706 as = g_malloc0(sizeof *as);
2707 address_space_init(as, root, name);
2708 as->malloced = true;
2709 return as;
83f3c251
AK
2710}
2711
374f2981
PB
2712void address_space_destroy(AddressSpace *as)
2713{
ac95190e
PB
2714 MemoryRegion *root = as->root;
2715
f0c02d15
PC
2716 as->ref_count--;
2717 if (as->ref_count) {
2718 return;
2719 }
374f2981
PB
2720 /* Flush out anything from MemoryListeners listening in on this */
2721 memory_region_transaction_begin();
2722 as->root = NULL;
2723 memory_region_transaction_commit();
2724 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2725
2726 /* At this point, as->dispatch and as->current_map are dummy
2727 * entries that the guest should never use. Wait for the old
2728 * values to expire before freeing the data.
2729 */
ac95190e 2730 as->root = root;
374f2981
PB
2731 call_rcu(as, do_address_space_destroy, rcu);
2732}
2733
4e831901
PX
2734static const char *memory_region_type(MemoryRegion *mr)
2735{
2736 if (memory_region_is_ram_device(mr)) {
2737 return "ramd";
2738 } else if (memory_region_is_romd(mr)) {
2739 return "romd";
2740 } else if (memory_region_is_rom(mr)) {
2741 return "rom";
2742 } else if (memory_region_is_ram(mr)) {
2743 return "ram";
2744 } else {
2745 return "i/o";
2746 }
2747}
2748
314e2987
BS
2749typedef struct MemoryRegionList MemoryRegionList;
2750
2751struct MemoryRegionList {
2752 const MemoryRegion *mr;
a16878d2 2753 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS
2754};
2755
a16878d2 2756typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
314e2987 2757
4e831901
PX
2758#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2759 int128_sub((size), int128_one())) : 0)
2760#define MTREE_INDENT " "
2761
314e2987
BS
2762static void mtree_print_mr(fprintf_function mon_printf, void *f,
2763 const MemoryRegion *mr, unsigned int level,
a8170e5e 2764 hwaddr base,
9479c57a 2765 MemoryRegionListHead *alias_print_queue)
314e2987 2766{
9479c57a
JK
2767 MemoryRegionList *new_ml, *ml, *next_ml;
2768 MemoryRegionListHead submr_print_queue;
314e2987
BS
2769 const MemoryRegion *submr;
2770 unsigned int i;
b31f8412 2771 hwaddr cur_start, cur_end;
314e2987 2772
f8a9f720 2773 if (!mr) {
314e2987
BS
2774 return;
2775 }
2776
2777 for (i = 0; i < level; i++) {
4e831901 2778 mon_printf(f, MTREE_INDENT);
314e2987
BS
2779 }
2780
b31f8412
PX
2781 cur_start = base + mr->addr;
2782 cur_end = cur_start + MR_SIZE(mr->size);
2783
2784 /*
2785 * Try to detect overflow of memory region. This should never
2786 * happen normally. When it happens, we dump something to warn the
2787 * user who is observing this.
2788 */
2789 if (cur_start < base || cur_end < cur_start) {
2790 mon_printf(f, "[DETECTED OVERFLOW!] ");
2791 }
2792
314e2987
BS
2793 if (mr->alias) {
2794 MemoryRegionList *ml;
2795 bool found = false;
2796
2797 /* check if the alias is already in the queue */
a16878d2 2798 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2799 if (ml->mr == mr->alias) {
314e2987
BS
2800 found = true;
2801 }
2802 }
2803
2804 if (!found) {
2805 ml = g_new(MemoryRegionList, 1);
2806 ml->mr = mr->alias;
a16878d2 2807 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2808 }
4896d74b 2809 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
4e831901 2810 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
f8a9f720 2811 "-" TARGET_FMT_plx "%s\n",
b31f8412 2812 cur_start, cur_end,
4b474ba7 2813 mr->priority,
4e831901 2814 memory_region_type((MemoryRegion *)mr),
3fb18b4d
PC
2815 memory_region_name(mr),
2816 memory_region_name(mr->alias),
314e2987 2817 mr->alias_offset,
4e831901 2818 mr->alias_offset + MR_SIZE(mr->size),
f8a9f720 2819 mr->enabled ? "" : " [disabled]");
314e2987 2820 } else {
4896d74b 2821 mon_printf(f,
4e831901 2822 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
b31f8412 2823 cur_start, cur_end,
4b474ba7 2824 mr->priority,
4e831901 2825 memory_region_type((MemoryRegion *)mr),
f8a9f720
GH
2826 memory_region_name(mr),
2827 mr->enabled ? "" : " [disabled]");
314e2987 2828 }
9479c57a
JK
2829
2830 QTAILQ_INIT(&submr_print_queue);
2831
314e2987 2832 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
2833 new_ml = g_new(MemoryRegionList, 1);
2834 new_ml->mr = submr;
a16878d2 2835 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK
2836 if (new_ml->mr->addr < ml->mr->addr ||
2837 (new_ml->mr->addr == ml->mr->addr &&
2838 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 2839 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK
2840 new_ml = NULL;
2841 break;
2842 }
2843 }
2844 if (new_ml) {
a16878d2 2845 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK
2846 }
2847 }
2848
a16878d2 2849 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b31f8412 2850 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
9479c57a
JK
2851 alias_print_queue);
2852 }
2853
a16878d2 2854 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 2855 g_free(ml);
314e2987
BS
2856 }
2857}
2858
57bb40c9
PX
2859static void mtree_print_flatview(fprintf_function p, void *f,
2860 AddressSpace *as)
2861{
2862 FlatView *view = address_space_get_flatview(as);
2863 FlatRange *range = &view->ranges[0];
2864 MemoryRegion *mr;
2865 int n = view->nr;
2866
2867 if (n <= 0) {
2868 p(f, MTREE_INDENT "No rendered FlatView for "
2869 "address space '%s'\n", as->name);
2870 flatview_unref(view);
2871 return;
2872 }
2873
2874 while (n--) {
2875 mr = range->mr;
377a07aa
PB
2876 if (range->offset_in_region) {
2877 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2878 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
2879 int128_get64(range->addr.start),
2880 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2881 mr->priority,
2882 range->readonly ? "rom" : memory_region_type(mr),
2883 memory_region_name(mr),
2884 range->offset_in_region);
2885 } else {
2886 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2887 TARGET_FMT_plx " (prio %d, %s): %s\n",
2888 int128_get64(range->addr.start),
2889 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2890 mr->priority,
2891 range->readonly ? "rom" : memory_region_type(mr),
2892 memory_region_name(mr));
2893 }
57bb40c9
PX
2894 range++;
2895 }
2896
2897 flatview_unref(view);
2898}
2899
2900void mtree_info(fprintf_function mon_printf, void *f, bool flatview)
314e2987
BS
2901{
2902 MemoryRegionListHead ml_head;
2903 MemoryRegionList *ml, *ml2;
0d673e36 2904 AddressSpace *as;
314e2987 2905
57bb40c9
PX
2906 if (flatview) {
2907 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2908 mon_printf(f, "address-space (flat view): %s\n", as->name);
2909 mtree_print_flatview(mon_printf, f, as);
2910 mon_printf(f, "\n");
2911 }
2912 return;
2913 }
2914
314e2987
BS
2915 QTAILQ_INIT(&ml_head);
2916
0d673e36 2917 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
e48816aa
GH
2918 mon_printf(f, "address-space: %s\n", as->name);
2919 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
2920 mon_printf(f, "\n");
b9f9be88
BS
2921 }
2922
314e2987 2923 /* print aliased regions */
a16878d2 2924 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
e48816aa
GH
2925 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
2926 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
2927 mon_printf(f, "\n");
314e2987
BS
2928 }
2929
a16878d2 2930 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 2931 g_free(ml);
314e2987 2932 }
314e2987 2933}
b4fefef9 2934
b08199c6
PM
2935void memory_region_init_ram(MemoryRegion *mr,
2936 struct Object *owner,
2937 const char *name,
2938 uint64_t size,
2939 Error **errp)
2940{
2941 DeviceState *owner_dev;
2942 Error *err = NULL;
2943
2944 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
2945 if (err) {
2946 error_propagate(errp, err);
2947 return;
2948 }
2949 /* This will assert if owner is neither NULL nor a DeviceState.
2950 * We only want the owner here for the purposes of defining a
2951 * unique name for migration. TODO: Ideally we should implement
2952 * a naming scheme for Objects which are not DeviceStates, in
2953 * which case we can relax this restriction.
2954 */
2955 owner_dev = DEVICE(owner);
2956 vmstate_register_ram(mr, owner_dev);
2957}
2958
2959void memory_region_init_rom(MemoryRegion *mr,
2960 struct Object *owner,
2961 const char *name,
2962 uint64_t size,
2963 Error **errp)
2964{
2965 DeviceState *owner_dev;
2966 Error *err = NULL;
2967
2968 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
2969 if (err) {
2970 error_propagate(errp, err);
2971 return;
2972 }
2973 /* This will assert if owner is neither NULL nor a DeviceState.
2974 * We only want the owner here for the purposes of defining a
2975 * unique name for migration. TODO: Ideally we should implement
2976 * a naming scheme for Objects which are not DeviceStates, in
2977 * which case we can relax this restriction.
2978 */
2979 owner_dev = DEVICE(owner);
2980 vmstate_register_ram(mr, owner_dev);
2981}
2982
2983void memory_region_init_rom_device(MemoryRegion *mr,
2984 struct Object *owner,
2985 const MemoryRegionOps *ops,
2986 void *opaque,
2987 const char *name,
2988 uint64_t size,
2989 Error **errp)
2990{
2991 DeviceState *owner_dev;
2992 Error *err = NULL;
2993
2994 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
2995 name, size, &err);
2996 if (err) {
2997 error_propagate(errp, err);
2998 return;
2999 }
3000 /* This will assert if owner is neither NULL nor a DeviceState.
3001 * We only want the owner here for the purposes of defining a
3002 * unique name for migration. TODO: Ideally we should implement
3003 * a naming scheme for Objects which are not DeviceStates, in
3004 * which case we can relax this restriction.
3005 */
3006 owner_dev = DEVICE(owner);
3007 vmstate_register_ram(mr, owner_dev);
3008}
3009
b4fefef9
PC
3010static const TypeInfo memory_region_info = {
3011 .parent = TYPE_OBJECT,
3012 .name = TYPE_MEMORY_REGION,
3013 .instance_size = sizeof(MemoryRegion),
3014 .instance_init = memory_region_initfn,
3015 .instance_finalize = memory_region_finalize,
3016};
3017
3df9d748
AK
3018static const TypeInfo iommu_memory_region_info = {
3019 .parent = TYPE_MEMORY_REGION,
3020 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 3021 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK
3022 .instance_size = sizeof(IOMMUMemoryRegion),
3023 .instance_init = iommu_memory_region_initfn,
1221a474 3024 .abstract = true,
3df9d748
AK
3025};
3026
b4fefef9
PC
3027static void memory_register_types(void)
3028{
3029 type_register_static(&memory_region_info);
3df9d748 3030 type_register_static(&iommu_memory_region_info);
b4fefef9
PC
3031}
3032
3033type_init(memory_register_types)