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memory: trace FlatView creation and destruction
[mirror_qemu.git] / memory.c
CommitLineData
093bc2cd
AK		 1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB		 12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
AK		 14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879
PB		 18#include "qemu-common.h"
19#include "cpu.h"
022c62cb
PB		 20#include "exec/memory.h"
21#include "exec/address-spaces.h"
22#include "exec/ioport.h"
409ddd01 23#include "qapi/visitor.h"
1de7afc9 24#include "qemu/bitops.h"
8c56c1a5 25#include "qemu/error-report.h"
2c9b15ca 26#include "qom/object.h"
0ab8ed18 27#include "trace-root.h"
093bc2cd 28
022c62cb 29#include "exec/memory-internal.h"
220c3ebd 30#include "exec/ram_addr.h"
8c56c1a5 31#include "sysemu/kvm.h"
e1c57ab8 32#include "sysemu/sysemu.h"
c9356746
FK		 33#include "hw/misc/mmio_interface.h"
34#include "hw/qdev-properties.h"
b08199c6 35#include "migration/vmstate.h"
67d95c15 36
d197063f
PB		 37//#define DEBUG_UNASSIGNED
38
22bde714
JK		 39static unsigned memory_region_transaction_depth;
40static bool memory_region_update_pending;
4dc56152 41static bool ioeventfd_update_pending;
7664e80c
AK		 42static bool global_dirty_log = false;
43
72e22d2f
AK		 44static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
45 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 46
0d673e36
AK		 47static QTAILQ_HEAD(, AddressSpace) address_spaces
48 = QTAILQ_HEAD_INITIALIZER(address_spaces);
49
967dc9b1
AK		 50static GHashTable *flat_views;
51
093bc2cd
AK		 52typedef struct AddrRange AddrRange;
53
8417cebf 54/*
c9cdaa3a 55 * Note that signed integers are needed for negative offsetting in aliases
8417cebf
AK		 56 * (large MemoryRegion::alias_offset).
57 */
093bc2cd 58struct AddrRange {
08dafab4
AK		 59 Int128 start;
60 Int128 size;
093bc2cd
AK		 61};
62
08dafab4 63static AddrRange addrrange_make(Int128 start, Int128 size)
093bc2cd
AK		 64{
65 return (AddrRange) { start, size };
66}
67
68static bool addrrange_equal(AddrRange r1, AddrRange r2)
69{
08dafab4 70 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
093bc2cd
AK		 71}
72
08dafab4 73static Int128 addrrange_end(AddrRange r)
093bc2cd 74{
08dafab4 75 return int128_add(r.start, r.size);
093bc2cd
AK		 76}
77
08dafab4 78static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 79{
08dafab4 80 int128_addto(&range.start, delta);
093bc2cd
AK		 81 return range;
82}
83
08dafab4
AK		 84static bool addrrange_contains(AddrRange range, Int128 addr)
85{
86 return int128_ge(addr, range.start)
87 && int128_lt(addr, addrrange_end(range));
88}
89
093bc2cd
AK		 90static bool addrrange_intersects(AddrRange r1, AddrRange r2)
91{
08dafab4
AK		 92 return addrrange_contains(r1, r2.start)
93 || addrrange_contains(r2, r1.start);
093bc2cd
AK		 94}
95
96static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
97{
08dafab4
AK		 98 Int128 start = int128_max(r1.start, r2.start);
99 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
100 return addrrange_make(start, int128_sub(end, start));
093bc2cd
AK		 101}
102
0e0d36b4
AK		 103enum ListenerDirection { Forward, Reverse };
104
7376e582 105#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
AK		 106 do { \
107 MemoryListener *_listener; \
108 \
109 switch (_direction) { \
110 case Forward: \
111 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
AK		 112 if (_listener->_callback) { \
113 _listener->_callback(_listener, ##_args); \
114 } \
0e0d36b4
AK		 115 } \
116 break; \
117 case Reverse: \
118 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
119 memory_listeners, link) { \
975aefe0
AK		 120 if (_listener->_callback) { \
121 _listener->_callback(_listener, ##_args); \
122 } \
0e0d36b4
AK		 123 } \
124 break; \
125 default: \
126 abort(); \
127 } \
128 } while (0)
129
9a54635d 130#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
7376e582
AK		 131 do { \
132 MemoryListener *_listener; \
9a54635d 133 struct memory_listeners_as *list = &(_as)->listeners; \
7376e582
AK		 134 \
135 switch (_direction) { \
136 case Forward: \
9a54635d
PB		 137 QTAILQ_FOREACH(_listener, list, link_as) { \
138 if (_listener->_callback) { \
7376e582
AK		 139 _listener->_callback(_listener, _section, ##_args); \
140 } \
141 } \
142 break; \
143 case Reverse: \
9a54635d
PB		 144 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
145 link_as) { \
146 if (_listener->_callback) { \
7376e582
AK		 147 _listener->_callback(_listener, _section, ##_args); \
148 } \
149 } \
150 break; \
151 default: \
152 abort(); \
153 } \
154 } while (0)
155
dfde4e6e 156/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 157#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44 158 do { \
16620684
AK		 159 MemoryRegionSection mrs = section_from_flat_range(fr, \
160 address_space_to_flatview(as)); \
9a54635d 161 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 162 } while(0)
0e0d36b4 163
093bc2cd
AK		 164struct CoalescedMemoryRange {
165 AddrRange addr;
166 QTAILQ_ENTRY(CoalescedMemoryRange) link;
167};
168
3e9d69e7
AK		 169struct MemoryRegionIoeventfd {
170 AddrRange addr;
171 bool match_data;
172 uint64_t data;
753d5e14 173 EventNotifier *e;
3e9d69e7
AK		 174};
175
176static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
177 MemoryRegionIoeventfd b)
178{
08dafab4 179 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 180 return true;
08dafab4 181 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 182 return false;
08dafab4 183 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 184 return true;
08dafab4 185 } else if (int128_gt(a.addr.size, b.addr.size)) {
3e9d69e7
AK		 186 return false;
187 } else if (a.match_data < b.match_data) {
188 return true;
189 } else if (a.match_data > b.match_data) {
190 return false;
191 } else if (a.match_data) {
192 if (a.data < b.data) {
193 return true;
194 } else if (a.data > b.data) {
195 return false;
196 }
197 }
753d5e14 198 if (a.e < b.e) {
3e9d69e7 199 return true;
753d5e14 200 } else if (a.e > b.e) {
3e9d69e7
AK		 201 return false;
202 }
203 return false;
204}
205
206static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
207 MemoryRegionIoeventfd b)
208{
209 return !memory_region_ioeventfd_before(a, b)
210 && !memory_region_ioeventfd_before(b, a);
211}
212
093bc2cd 213typedef struct FlatRange FlatRange;
093bc2cd
AK		 214
215/* Range of memory in the global map. Addresses are absolute. */
216struct FlatRange {
217 MemoryRegion *mr;
a8170e5e 218 hwaddr offset_in_region;
093bc2cd 219 AddrRange addr;
5a583347 220 uint8_t dirty_log_mask;
b138e654 221 bool romd_mode;
fb1cd6f9 222 bool readonly;
093bc2cd
AK		 223};
224
225/* Flattened global view of current active memory hierarchy. Kept in sorted
226 * order.
227 */
228struct FlatView {
374f2981 229 struct rcu_head rcu;
856d7245 230 unsigned ref;
093bc2cd
AK		 231 FlatRange *ranges;
232 unsigned nr;
233 unsigned nr_allocated;
66a6df1d 234 struct AddressSpaceDispatch *dispatch;
89c177bb 235 MemoryRegion *root;
093bc2cd
AK		 236};
237
cc31e6e7
AK		 238typedef struct AddressSpaceOps AddressSpaceOps;
239
093bc2cd
AK		 240#define FOR_EACH_FLAT_RANGE(var, view) \
241 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
242
9c1f8f44 243static inline MemoryRegionSection
16620684 244section_from_flat_range(FlatRange *fr, FlatView *fv)
9c1f8f44
PB		 245{
246 return (MemoryRegionSection) {
247 .mr = fr->mr,
16620684 248 .fv = fv,
9c1f8f44
PB		 249 .offset_within_region = fr->offset_in_region,
250 .size = fr->addr.size,
251 .offset_within_address_space = int128_get64(fr->addr.start),
252 .readonly = fr->readonly,
253 };
254}
255
093bc2cd
AK		 256static bool flatrange_equal(FlatRange *a, FlatRange *b)
257{
258 return a->mr == b->mr
259 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 260 && a->offset_in_region == b->offset_in_region
b138e654 261 && a->romd_mode == b->romd_mode
fb1cd6f9 262 && a->readonly == b->readonly;
093bc2cd
AK		 263}
264
89c177bb 265static FlatView *flatview_new(MemoryRegion *mr_root)
093bc2cd 266{
cc94cd6d
AK		 267 FlatView *view;
268
269 view = g_new0(FlatView, 1);
856d7245 270 view->ref = 1;
89c177bb
AK		 271 view->root = mr_root;
272 memory_region_ref(mr_root);
02d9651d 273 trace_flatview_new(view, mr_root);
cc94cd6d
AK		 274
275 return view;
093bc2cd
AK		 276}
277
278/* Insert a range into a given position. Caller is responsible for maintaining
279 * sorting order.
280 */
281static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
282{
283 if (view->nr == view->nr_allocated) {
284 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 285 view->ranges = g_realloc(view->ranges,
093bc2cd
AK		 286 view->nr_allocated * sizeof(*view->ranges));
287 }
288 memmove(view->ranges + pos + 1, view->ranges + pos,
289 (view->nr - pos) * sizeof(FlatRange));
290 view->ranges[pos] = *range;
dfde4e6e 291 memory_region_ref(range->mr);
093bc2cd
AK		 292 ++view->nr;
293}
294
295static void flatview_destroy(FlatView *view)
296{
dfde4e6e
PB		 297 int i;
298
02d9651d 299 trace_flatview_destroy(view, view->root);
66a6df1d
AK		 300 if (view->dispatch) {
301 address_space_dispatch_free(view->dispatch);
302 }
dfde4e6e
PB		 303 for (i = 0; i < view->nr; i++) {
304 memory_region_unref(view->ranges[i].mr);
305 }
7267c094 306 g_free(view->ranges);
89c177bb 307 memory_region_unref(view->root);
a9a0c06d 308 g_free(view);
093bc2cd
AK		 309}
310
447b0d0b 311static bool flatview_ref(FlatView *view)
856d7245 312{
447b0d0b 313 return atomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB		 314}
315
316static void flatview_unref(FlatView *view)
317{
318 if (atomic_fetch_dec(&view->ref) == 1) {
02d9651d 319 trace_flatview_destroy_rcu(view, view->root);
66a6df1d 320 call_rcu(view, flatview_destroy, rcu);
856d7245
PB		 321 }
322}
323
16620684 324FlatView *address_space_to_flatview(AddressSpace *as)
66a6df1d
AK		 325{
326 return atomic_rcu_read(&as->current_map);
327}
328
329AddressSpaceDispatch *flatview_to_dispatch(FlatView *fv)
330{
331 return fv->dispatch;
332}
333
334AddressSpaceDispatch *address_space_to_dispatch(AddressSpace *as)
335{
336 return flatview_to_dispatch(address_space_to_flatview(as));
337}
338
3d8e6bf9
AK		 339static bool can_merge(FlatRange *r1, FlatRange *r2)
340{
08dafab4 341 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 342 && r1->mr == r2->mr
08dafab4
AK		 343 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
344 r1->addr.size),
345 int128_make64(r2->offset_in_region))
d0a9b5bc 346 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 347 && r1->romd_mode == r2->romd_mode
fb1cd6f9 348 && r1->readonly == r2->readonly;
3d8e6bf9
AK		 349}
350
8508e024 351/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK		 352static void flatview_simplify(FlatView *view)
353{
354 unsigned i, j;
355
356 i = 0;
357 while (i < view->nr) {
358 j = i + 1;
359 while (j < view->nr
360 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 361 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
AK		 362 ++j;
363 }
364 ++i;
365 memmove(&view->ranges[i], &view->ranges[j],
366 (view->nr - j) * sizeof(view->ranges[j]));
367 view->nr -= j - i;
368 }
369}
370
e7342aa3
PB		 371static bool memory_region_big_endian(MemoryRegion *mr)
372{
373#ifdef TARGET_WORDS_BIGENDIAN
374 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
375#else
376 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
377#endif
378}
379
e11ef3d1
PB		 380static bool memory_region_wrong_endianness(MemoryRegion *mr)
381{
382#ifdef TARGET_WORDS_BIGENDIAN
383 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
384#else
385 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
386#endif
387}
388
389static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
390{
391 if (memory_region_wrong_endianness(mr)) {
392 switch (size) {
393 case 1:
394 break;
395 case 2:
396 *data = bswap16(*data);
397 break;
398 case 4:
399 *data = bswap32(*data);
400 break;
401 case 8:
402 *data = bswap64(*data);
403 break;
404 default:
405 abort();
406 }
407 }
408}
409
4779dc1d
HB		 410static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
411{
412 MemoryRegion *root;
413 hwaddr abs_addr = offset;
414
415 abs_addr += mr->addr;
416 for (root = mr; root->container; ) {
417 root = root->container;
418 abs_addr += root->addr;
419 }
420
421 return abs_addr;
422}
423
5a68be94
HB		 424static int get_cpu_index(void)
425{
426 if (current_cpu) {
427 return current_cpu->cpu_index;
428 }
429 return -1;
430}
431
cc05c43a
PM		 432static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
433 hwaddr addr,
434 uint64_t *value,
435 unsigned size,
436 unsigned shift,
437 uint64_t mask,
438 MemTxAttrs attrs)
439{
440 uint64_t tmp;
441
442 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
23d92d68 443 if (mr->subpage) {
5a68be94 444 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 445 } else if (mr == &io_mem_notdirty) {
446 /* Accesses to code which has previously been translated into a TB show
447 * up in the MMIO path, as accesses to the io_mem_notdirty
448 * MemoryRegion. */
449 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 450 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
451 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 452 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 453 }
cc05c43a
PM		 454 *value |= (tmp & mask) << shift;
455 return MEMTX_OK;
456}
457
458static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB		 459 hwaddr addr,
460 uint64_t *value,
461 unsigned size,
462 unsigned shift,
cc05c43a
PM		 463 uint64_t mask,
464 MemTxAttrs attrs)
ce5d2f33 465{
ce5d2f33
PB		 466 uint64_t tmp;
467
cc05c43a 468 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 469 if (mr->subpage) {
5a68be94 470 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 471 } else if (mr == &io_mem_notdirty) {
472 /* Accesses to code which has previously been translated into a TB show
473 * up in the MMIO path, as accesses to the io_mem_notdirty
474 * MemoryRegion. */
475 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 476 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
477 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 478 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 479 }
ce5d2f33 480 *value |= (tmp & mask) << shift;
cc05c43a 481 return MEMTX_OK;
ce5d2f33
PB		 482}
483
cc05c43a
PM		 484static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
485 hwaddr addr,
486 uint64_t *value,
487 unsigned size,
488 unsigned shift,
489 uint64_t mask,
490 MemTxAttrs attrs)
164a4dcd 491{
cc05c43a
PM		 492 uint64_t tmp = 0;
493 MemTxResult r;
164a4dcd 494
cc05c43a 495 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 496 if (mr->subpage) {
5a68be94 497 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 498 } else if (mr == &io_mem_notdirty) {
499 /* Accesses to code which has previously been translated into a TB show
500 * up in the MMIO path, as accesses to the io_mem_notdirty
501 * MemoryRegion. */
502 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 503 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
504 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 505 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 506 }
164a4dcd 507 *value |= (tmp & mask) << shift;
cc05c43a 508 return r;
164a4dcd
AK		 509}
510
cc05c43a
PM		 511static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
512 hwaddr addr,
513 uint64_t *value,
514 unsigned size,
515 unsigned shift,
516 uint64_t mask,
517 MemTxAttrs attrs)
ce5d2f33 518{
ce5d2f33
PB		 519 uint64_t tmp;
520
521 tmp = (*value >> shift) & mask;
23d92d68 522 if (mr->subpage) {
5a68be94 523 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 524 } else if (mr == &io_mem_notdirty) {
525 /* Accesses to code which has previously been translated into a TB show
526 * up in the MMIO path, as accesses to the io_mem_notdirty
527 * MemoryRegion. */
528 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 529 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
530 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 531 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 532 }
ce5d2f33 533 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
cc05c43a 534 return MEMTX_OK;
ce5d2f33
PB		 535}
536
cc05c43a
PM		 537static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
538 hwaddr addr,
539 uint64_t *value,
540 unsigned size,
541 unsigned shift,
542 uint64_t mask,
543 MemTxAttrs attrs)
164a4dcd 544{
164a4dcd
AK		 545 uint64_t tmp;
546
547 tmp = (*value >> shift) & mask;
23d92d68 548 if (mr->subpage) {
5a68be94 549 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 550 } else if (mr == &io_mem_notdirty) {
551 /* Accesses to code which has previously been translated into a TB show
552 * up in the MMIO path, as accesses to the io_mem_notdirty
553 * MemoryRegion. */
554 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 555 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
556 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 557 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 558 }
164a4dcd 559 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 560 return MEMTX_OK;
164a4dcd
AK		 561}
562
cc05c43a
PM		 563static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
564 hwaddr addr,
565 uint64_t *value,
566 unsigned size,
567 unsigned shift,
568 uint64_t mask,
569 MemTxAttrs attrs)
570{
571 uint64_t tmp;
572
cc05c43a 573 tmp = (*value >> shift) & mask;
23d92d68 574 if (mr->subpage) {
5a68be94 575 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 576 } else if (mr == &io_mem_notdirty) {
577 /* Accesses to code which has previously been translated into a TB show
578 * up in the MMIO path, as accesses to the io_mem_notdirty
579 * MemoryRegion. */
580 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 581 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
582 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 583 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 584 }
cc05c43a
PM		 585 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
586}
587
588static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK		 589 uint64_t *value,
590 unsigned size,
591 unsigned access_size_min,
592 unsigned access_size_max,
05e015f7
KF		 593 MemTxResult (*access_fn)
594 (MemoryRegion *mr,
595 hwaddr addr,
596 uint64_t *value,
597 unsigned size,
598 unsigned shift,
599 uint64_t mask,
600 MemTxAttrs attrs),
cc05c43a
PM		 601 MemoryRegion *mr,
602 MemTxAttrs attrs)
164a4dcd
AK		 603{
604 uint64_t access_mask;
605 unsigned access_size;
606 unsigned i;
cc05c43a 607 MemTxResult r = MEMTX_OK;
164a4dcd
AK		 608
609 if (!access_size_min) {
610 access_size_min = 1;
611 }
612 if (!access_size_max) {
613 access_size_max = 4;
614 }
ce5d2f33
PB		 615
616 /* FIXME: support unaligned access? */
164a4dcd
AK		 617 access_size = MAX(MIN(size, access_size_max), access_size_min);
618 access_mask = -1ULL >> (64 - access_size * 8);
e7342aa3
PB		 619 if (memory_region_big_endian(mr)) {
620 for (i = 0; i < size; i += access_size) {
05e015f7 621 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 622 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB		 623 }
624 } else {
625 for (i = 0; i < size; i += access_size) {
05e015f7 626 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 627 access_mask, attrs);
e7342aa3 628 }
164a4dcd 629 }
cc05c43a 630 return r;
164a4dcd
AK		 631}
632
e2177955
AK		 633static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
634{
0d673e36
AK		 635 AddressSpace *as;
636
feca4ac1
PB		 637 while (mr->container) {
638 mr = mr->container;
e2177955 639 }
0d673e36
AK		 640 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
641 if (mr == as->root) {
642 return as;
643 }
e2177955 644 }
eed2bacf 645 return NULL;
e2177955
AK		 646}
647
093bc2cd
AK		 648/* Render a memory region into the global view. Ranges in @view obscure
649 * ranges in @mr.
650 */
651static void render_memory_region(FlatView *view,
652 MemoryRegion *mr,
08dafab4 653 Int128 base,
fb1cd6f9
AK		 654 AddrRange clip,
655 bool readonly)
093bc2cd
AK		 656{
657 MemoryRegion *subregion;
658 unsigned i;
a8170e5e 659 hwaddr offset_in_region;
08dafab4
AK		 660 Int128 remain;
661 Int128 now;
093bc2cd
AK		 662 FlatRange fr;
663 AddrRange tmp;
664
6bba19ba
AK		 665 if (!mr->enabled) {
666 return;
667 }
668
08dafab4 669 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 670 readonly |= mr->readonly;
093bc2cd
AK		 671
672 tmp = addrrange_make(base, mr->size);
673
674 if (!addrrange_intersects(tmp, clip)) {
675 return;
676 }
677
678 clip = addrrange_intersection(tmp, clip);
679
680 if (mr->alias) {
08dafab4
AK		 681 int128_subfrom(&base, int128_make64(mr->alias->addr));
682 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 683 render_memory_region(view, mr->alias, base, clip, readonly);
093bc2cd
AK		 684 return;
685 }
686
687 /* Render subregions in priority order. */
688 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 689 render_memory_region(view, subregion, base, clip, readonly);
093bc2cd
AK		 690 }
691
14a3c10a 692 if (!mr->terminates) {
093bc2cd
AK		 693 return;
694 }
695
08dafab4 696 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK		 697 base = clip.start;
698 remain = clip.size;
699
2eb74e1a 700 fr.mr = mr;
6f6a5ef3 701 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 702 fr.romd_mode = mr->romd_mode;
2eb74e1a
PC		 703 fr.readonly = readonly;
704
093bc2cd 705 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK		 706 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
707 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK		 708 continue;
709 }
08dafab4
AK		 710 if (int128_lt(base, view->ranges[i].addr.start)) {
711 now = int128_min(remain,
712 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK		 713 fr.offset_in_region = offset_in_region;
714 fr.addr = addrrange_make(base, now);
715 flatview_insert(view, i, &fr);
716 ++i;
08dafab4
AK		 717 int128_addto(&base, now);
718 offset_in_region += int128_get64(now);
719 int128_subfrom(&remain, now);
093bc2cd 720 }
d26a8cae
AK		 721 now = int128_sub(int128_min(int128_add(base, remain),
722 addrrange_end(view->ranges[i].addr)),
723 base);
724 int128_addto(&base, now);
725 offset_in_region += int128_get64(now);
726 int128_subfrom(&remain, now);
093bc2cd 727 }
08dafab4 728 if (int128_nz(remain)) {
093bc2cd
AK		 729 fr.offset_in_region = offset_in_region;
730 fr.addr = addrrange_make(base, remain);
731 flatview_insert(view, i, &fr);
732 }
733}
734
89c177bb
AK		 735static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
736{
737 while (mr->alias && !mr->alias_offset &&
738 int128_ge(mr->size, mr->alias->size)) {
739 /* The alias is included in its entirety. Use it as
740 * the "real" root, so that we can share more FlatViews.
741 */
742 mr = mr->alias;
743 }
744
745 return mr;
746}
747
093bc2cd 748/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 749static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 750{
9bf561e3 751 int i;
a9a0c06d 752 FlatView *view;
093bc2cd 753
89c177bb 754 view = flatview_new(mr);
093bc2cd 755
83f3c251 756 if (mr) {
a9a0c06d 757 render_memory_region(view, mr, int128_zero(),
83f3c251
AK		 758 addrrange_make(int128_zero(), int128_2_64()), false);
759 }
a9a0c06d 760 flatview_simplify(view);
093bc2cd 761
9bf561e3
AK		 762 view->dispatch = address_space_dispatch_new(view);
763 for (i = 0; i < view->nr; i++) {
764 MemoryRegionSection mrs =
765 section_from_flat_range(&view->ranges[i], view);
766 flatview_add_to_dispatch(view, &mrs);
767 }
768 address_space_dispatch_compact(view->dispatch);
967dc9b1 769 g_hash_table_replace(flat_views, mr, view);
9bf561e3 770
093bc2cd
AK		 771 return view;
772}
773
3e9d69e7
AK		 774static void address_space_add_del_ioeventfds(AddressSpace *as,
775 MemoryRegionIoeventfd *fds_new,
776 unsigned fds_new_nb,
777 MemoryRegionIoeventfd *fds_old,
778 unsigned fds_old_nb)
779{
780 unsigned iold, inew;
80a1ea37
AK		 781 MemoryRegionIoeventfd *fd;
782 MemoryRegionSection section;
3e9d69e7
AK		 783
784 /* Generate a symmetric difference of the old and new fd sets, adding
785 * and deleting as necessary.
786 */
787
788 iold = inew = 0;
789 while (iold < fds_old_nb || inew < fds_new_nb) {
790 if (iold < fds_old_nb
791 && (inew == fds_new_nb
792 || memory_region_ioeventfd_before(fds_old[iold],
793 fds_new[inew]))) {
80a1ea37
AK		 794 fd = &fds_old[iold];
795 section = (MemoryRegionSection) {
16620684 796 .fv = address_space_to_flatview(as),
80a1ea37 797 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 798 .size = fd->addr.size,
80a1ea37 799 };
9a54635d 800 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 801 fd->match_data, fd->data, fd->e);
3e9d69e7
AK		 802 ++iold;
803 } else if (inew < fds_new_nb
804 && (iold == fds_old_nb
805 || memory_region_ioeventfd_before(fds_new[inew],
806 fds_old[iold]))) {
80a1ea37
AK		 807 fd = &fds_new[inew];
808 section = (MemoryRegionSection) {
16620684 809 .fv = address_space_to_flatview(as),
80a1ea37 810 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 811 .size = fd->addr.size,
80a1ea37 812 };
9a54635d 813 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 814 fd->match_data, fd->data, fd->e);
3e9d69e7
AK		 815 ++inew;
816 } else {
817 ++iold;
818 ++inew;
819 }
820 }
821}
822
856d7245
PB		 823static FlatView *address_space_get_flatview(AddressSpace *as)
824{
825 FlatView *view;
826
374f2981 827 rcu_read_lock();
447b0d0b 828 do {
16620684 829 view = address_space_to_flatview(as);
447b0d0b
PB		 830 /* If somebody has replaced as->current_map concurrently,
831 * flatview_ref returns false.
832 */
833 } while (!flatview_ref(view));
374f2981 834 rcu_read_unlock();
856d7245
PB		 835 return view;
836}
837
3e9d69e7
AK		 838static void address_space_update_ioeventfds(AddressSpace *as)
839{
99e86347 840 FlatView *view;
3e9d69e7
AK		 841 FlatRange *fr;
842 unsigned ioeventfd_nb = 0;
843 MemoryRegionIoeventfd *ioeventfds = NULL;
844 AddrRange tmp;
845 unsigned i;
846
856d7245 847 view = address_space_get_flatview(as);
99e86347 848 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK		 849 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
850 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK		 851 int128_sub(fr->addr.start,
852 int128_make64(fr->offset_in_region)));
3e9d69e7
AK		 853 if (addrrange_intersects(fr->addr, tmp)) {
854 ++ioeventfd_nb;
7267c094 855 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK		 856 ioeventfd_nb * sizeof(*ioeventfds));
857 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
858 ioeventfds[ioeventfd_nb-1].addr = tmp;
859 }
860 }
861 }
862
863 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
864 as->ioeventfds, as->ioeventfd_nb);
865
7267c094 866 g_free(as->ioeventfds);
3e9d69e7
AK		 867 as->ioeventfds = ioeventfds;
868 as->ioeventfd_nb = ioeventfd_nb;
856d7245 869 flatview_unref(view);
3e9d69e7
AK		 870}
871
b8af1afb 872static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB		 873 const FlatView *old_view,
874 const FlatView *new_view,
b8af1afb 875 bool adding)
093bc2cd 876{
093bc2cd
AK		 877 unsigned iold, inew;
878 FlatRange *frold, *frnew;
093bc2cd
AK		 879
880 /* Generate a symmetric difference of the old and new memory maps.
881 * Kill ranges in the old map, and instantiate ranges in the new map.
882 */
883 iold = inew = 0;
a9a0c06d
PB		 884 while (iold < old_view->nr || inew < new_view->nr) {
885 if (iold < old_view->nr) {
886 frold = &old_view->ranges[iold];
093bc2cd
AK		 887 } else {
888 frold = NULL;
889 }
a9a0c06d
PB		 890 if (inew < new_view->nr) {
891 frnew = &new_view->ranges[inew];
093bc2cd
AK		 892 } else {
893 frnew = NULL;
894 }
895
896 if (frold
897 && (!frnew
08dafab4
AK		 898 || int128_lt(frold->addr.start, frnew->addr.start)
899 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 900 && !flatrange_equal(frold, frnew)))) {
41a6e477 901 /* In old but not in new, or in both but attributes changed. */
093bc2cd 902
b8af1afb 903 if (!adding) {
72e22d2f 904 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK		 905 }
906
093bc2cd
AK		 907 ++iold;
908 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 909 /* In both and unchanged (except logging may have changed) */
093bc2cd 910
b8af1afb 911 if (adding) {
50c1e149 912 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB		 913 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
914 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
915 frold->dirty_log_mask,
916 frnew->dirty_log_mask);
917 }
918 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
919 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
920 frold->dirty_log_mask,
921 frnew->dirty_log_mask);
b8af1afb 922 }
5a583347
AK		 923 }
924
093bc2cd
AK		 925 ++iold;
926 ++inew;
093bc2cd
AK		 927 } else {
928 /* In new */
929
b8af1afb 930 if (adding) {
72e22d2f 931 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK		 932 }
933
093bc2cd
AK		 934 ++inew;
935 }
936 }
b8af1afb
AK		 937}
938
967dc9b1
AK		 939static void flatviews_init(void)
940{
941 if (flat_views) {
942 return;
943 }
944
945 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
946 (GDestroyNotify) flatview_unref);
947}
948
949static void flatviews_reset(void)
950{
951 AddressSpace *as;
952
953 if (flat_views) {
954 g_hash_table_unref(flat_views);
955 flat_views = NULL;
956 }
957 flatviews_init();
958
959 /* Render unique FVs */
960 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
961 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
962
963 if (g_hash_table_lookup(flat_views, physmr)) {
964 continue;
965 }
966
967 generate_memory_topology(physmr);
968 }
969}
970
971static void address_space_set_flatview(AddressSpace *as)
b8af1afb 972{
67ace39b 973 FlatView *old_view = address_space_to_flatview(as);
967dc9b1
AK		 974 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
975 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
976
977 assert(new_view);
978
67ace39b
AK		 979 if (old_view == new_view) {
980 return;
981 }
982
983 if (old_view) {
984 flatview_ref(old_view);
985 }
986
967dc9b1 987 flatview_ref(new_view);
9a62e24f
AK		 988
989 if (!QTAILQ_EMPTY(&as->listeners)) {
67ace39b
AK		 990 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
991
992 if (!old_view2) {
993 old_view2 = &tmpview;
994 }
995 address_space_update_topology_pass(as, old_view2, new_view, false);
996 address_space_update_topology_pass(as, old_view2, new_view, true);
9a62e24f 997 }
b8af1afb 998
374f2981
PB		 999 /* Writes are protected by the BQL. */
1000 atomic_rcu_set(&as->current_map, new_view);
67ace39b
AK		 1001 if (old_view) {
1002 flatview_unref(old_view);
1003 }
856d7245
PB		 1004
1005 /* Note that all the old MemoryRegions are still alive up to this
1006 * point. This relieves most MemoryListeners from the need to
1007 * ref/unref the MemoryRegions they get---unless they use them
1008 * outside the iothread mutex, in which case precise reference
1009 * counting is necessary.
1010 */
67ace39b
AK		 1011 if (old_view) {
1012 flatview_unref(old_view);
1013 }
093bc2cd
AK		 1014}
1015
202fc01b
AK		 1016static void address_space_update_topology(AddressSpace *as)
1017{
1018 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1019
1020 flatviews_init();
1021 if (!g_hash_table_lookup(flat_views, physmr)) {
1022 generate_memory_topology(physmr);
1023 }
1024 address_space_set_flatview(as);
1025}
1026
4ef4db86
AK		 1027void memory_region_transaction_begin(void)
1028{
bb880ded 1029 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK		 1030 ++memory_region_transaction_depth;
1031}
1032
1033void memory_region_transaction_commit(void)
1034{
0d673e36
AK		 1035 AddressSpace *as;
1036
4ef4db86 1037 assert(memory_region_transaction_depth);
8d04fb55
JK		 1038 assert(qemu_mutex_iothread_locked());
1039
4ef4db86 1040 --memory_region_transaction_depth;
4dc56152
GA		 1041 if (!memory_region_transaction_depth) {
1042 if (memory_region_update_pending) {
967dc9b1
AK		 1043 flatviews_reset();
1044
4dc56152 1045 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 1046
4dc56152 1047 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
967dc9b1 1048 address_space_set_flatview(as);
02218487 1049 address_space_update_ioeventfds(as);
4dc56152 1050 }
ade9c1aa 1051 memory_region_update_pending = false;
4dc56152
GA		 1052 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1053 } else if (ioeventfd_update_pending) {
1054 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1055 address_space_update_ioeventfds(as);
1056 }
ade9c1aa 1057 ioeventfd_update_pending = false;
4dc56152 1058 }
4dc56152 1059 }
4ef4db86
AK		 1060}
1061
545e92e0
AK		 1062static void memory_region_destructor_none(MemoryRegion *mr)
1063{
1064}
1065
1066static void memory_region_destructor_ram(MemoryRegion *mr)
1067{
f1060c55 1068 qemu_ram_free(mr->ram_block);
545e92e0
AK		 1069}
1070
b4fefef9
PC		 1071static bool memory_region_need_escape(char c)
1072{
1073 return c == '/' || c == '[' || c == '\\' || c == ']';
1074}
1075
1076static char *memory_region_escape_name(const char *name)
1077{
1078 const char *p;
1079 char *escaped, *q;
1080 uint8_t c;
1081 size_t bytes = 0;
1082
1083 for (p = name; *p; p++) {
1084 bytes += memory_region_need_escape(*p) ? 4 : 1;
1085 }
1086 if (bytes == p - name) {
1087 return g_memdup(name, bytes + 1);
1088 }
1089
1090 escaped = g_malloc(bytes + 1);
1091 for (p = name, q = escaped; *p; p++) {
1092 c = *p;
1093 if (unlikely(memory_region_need_escape(c))) {
1094 *q++ = '\\';
1095 *q++ = 'x';
1096 *q++ = "0123456789abcdef"[c >> 4];
1097 c = "0123456789abcdef"[c & 15];
1098 }
1099 *q++ = c;
1100 }
1101 *q = 0;
1102 return escaped;
1103}
1104
3df9d748
AK		 1105static void memory_region_do_init(MemoryRegion *mr,
1106 Object *owner,
1107 const char *name,
1108 uint64_t size)
093bc2cd 1109{
08dafab4
AK		 1110 mr->size = int128_make64(size);
1111 if (size == UINT64_MAX) {
1112 mr->size = int128_2_64();
1113 }
302fa283 1114 mr->name = g_strdup(name);
612263cf 1115 mr->owner = owner;
58eaa217 1116 mr->ram_block = NULL;
b4fefef9
PC		 1117
1118 if (name) {
843ef73a
PC		 1119 char *escaped_name = memory_region_escape_name(name);
1120 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB		 1121
1122 if (!owner) {
1123 owner = container_get(qdev_get_machine(), "/unattached");
1124 }
1125
843ef73a 1126 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1127 object_unref(OBJECT(mr));
843ef73a
PC		 1128 g_free(name_array);
1129 g_free(escaped_name);
b4fefef9
PC		 1130 }
1131}
1132
3df9d748
AK		 1133void memory_region_init(MemoryRegion *mr,
1134 Object *owner,
1135 const char *name,
1136 uint64_t size)
1137{
1138 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1139 memory_region_do_init(mr, owner, name, size);
1140}
1141
d7bce999
EB		 1142static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1143 void *opaque, Error **errp)
409ddd01
PC		 1144{
1145 MemoryRegion *mr = MEMORY_REGION(obj);
1146 uint64_t value = mr->addr;
1147
51e72bc1 1148 visit_type_uint64(v, name, &value, errp);
409ddd01
PC		 1149}
1150
d7bce999
EB		 1151static void memory_region_get_container(Object *obj, Visitor *v,
1152 const char *name, void *opaque,
1153 Error **errp)
409ddd01
PC		 1154{
1155 MemoryRegion *mr = MEMORY_REGION(obj);
1156 gchar *path = (gchar *)"";
1157
1158 if (mr->container) {
1159 path = object_get_canonical_path(OBJECT(mr->container));
1160 }
51e72bc1 1161 visit_type_str(v, name, &path, errp);
409ddd01
PC		 1162 if (mr->container) {
1163 g_free(path);
1164 }
1165}
1166
1167static Object *memory_region_resolve_container(Object *obj, void *opaque,
1168 const char *part)
1169{
1170 MemoryRegion *mr = MEMORY_REGION(obj);
1171
1172 return OBJECT(mr->container);
1173}
1174
d7bce999
EB		 1175static void memory_region_get_priority(Object *obj, Visitor *v,
1176 const char *name, void *opaque,
1177 Error **errp)
d33382da
PC		 1178{
1179 MemoryRegion *mr = MEMORY_REGION(obj);
1180 int32_t value = mr->priority;
1181
51e72bc1 1182 visit_type_int32(v, name, &value, errp);
d33382da
PC		 1183}
1184
d7bce999
EB		 1185static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1186 void *opaque, Error **errp)
52aef7bb
PC		 1187{
1188 MemoryRegion *mr = MEMORY_REGION(obj);
1189 uint64_t value = memory_region_size(mr);
1190
51e72bc1 1191 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC		 1192}
1193
b4fefef9
PC		 1194static void memory_region_initfn(Object *obj)
1195{
1196 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1197 ObjectProperty *op;
b4fefef9
PC		 1198
1199 mr->ops = &unassigned_mem_ops;
6bba19ba 1200 mr->enabled = true;
5f9a5ea1 1201 mr->romd_mode = true;
196ea131 1202 mr->global_locking = true;
545e92e0 1203 mr->destructor = memory_region_destructor_none;
093bc2cd 1204 QTAILQ_INIT(&mr->subregions);
093bc2cd 1205 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC		 1206
1207 op = object_property_add(OBJECT(mr), "container",
1208 "link<" TYPE_MEMORY_REGION ">",
1209 memory_region_get_container,
1210 NULL, /* memory_region_set_container */
1211 NULL, NULL, &error_abort);
1212 op->resolve = memory_region_resolve_container;
1213
1214 object_property_add(OBJECT(mr), "addr", "uint64",
1215 memory_region_get_addr,
1216 NULL, /* memory_region_set_addr */
1217 NULL, NULL, &error_abort);
d33382da
PC		 1218 object_property_add(OBJECT(mr), "priority", "uint32",
1219 memory_region_get_priority,
1220 NULL, /* memory_region_set_priority */
1221 NULL, NULL, &error_abort);
52aef7bb
PC		 1222 object_property_add(OBJECT(mr), "size", "uint64",
1223 memory_region_get_size,
1224 NULL, /* memory_region_set_size, */
1225 NULL, NULL, &error_abort);
093bc2cd
AK		 1226}
1227
3df9d748
AK		 1228static void iommu_memory_region_initfn(Object *obj)
1229{
1230 MemoryRegion *mr = MEMORY_REGION(obj);
1231
1232 mr->is_iommu = true;
1233}
1234
b018ddf6
PB		 1235static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1236 unsigned size)
1237{
1238#ifdef DEBUG_UNASSIGNED
1239 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1240#endif
4917cf44
AF		 1241 if (current_cpu != NULL) {
1242 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
c658b94f 1243 }
68a7439a 1244 return 0;
b018ddf6
PB		 1245}
1246
1247static void unassigned_mem_write(void *opaque, hwaddr addr,
1248 uint64_t val, unsigned size)
1249{
1250#ifdef DEBUG_UNASSIGNED
1251 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1252#endif
4917cf44
AF		 1253 if (current_cpu != NULL) {
1254 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1255 }
b018ddf6
PB		 1256}
1257
d197063f
PB		 1258static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1259 unsigned size, bool is_write)
1260{
1261 return false;
1262}
1263
1264const MemoryRegionOps unassigned_mem_ops = {
1265 .valid.accepts = unassigned_mem_accepts,
1266 .endianness = DEVICE_NATIVE_ENDIAN,
1267};
1268
4a2e242b
AW		 1269static uint64_t memory_region_ram_device_read(void *opaque,
1270 hwaddr addr, unsigned size)
1271{
1272 MemoryRegion *mr = opaque;
1273 uint64_t data = (uint64_t)~0;
1274
1275 switch (size) {
1276 case 1:
1277 data = *(uint8_t *)(mr->ram_block->host + addr);
1278 break;
1279 case 2:
1280 data = *(uint16_t *)(mr->ram_block->host + addr);
1281 break;
1282 case 4:
1283 data = *(uint32_t *)(mr->ram_block->host + addr);
1284 break;
1285 case 8:
1286 data = *(uint64_t *)(mr->ram_block->host + addr);
1287 break;
1288 }
1289
1290 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1291
1292 return data;
1293}
1294
1295static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1296 uint64_t data, unsigned size)
1297{
1298 MemoryRegion *mr = opaque;
1299
1300 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1301
1302 switch (size) {
1303 case 1:
1304 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1305 break;
1306 case 2:
1307 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1308 break;
1309 case 4:
1310 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1311 break;
1312 case 8:
1313 *(uint64_t *)(mr->ram_block->host + addr) = data;
1314 break;
1315 }
1316}
1317
1318static const MemoryRegionOps ram_device_mem_ops = {
1319 .read = memory_region_ram_device_read,
1320 .write = memory_region_ram_device_write,
c99a29e7 1321 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW		 1322 .valid = {
1323 .min_access_size = 1,
1324 .max_access_size = 8,
1325 .unaligned = true,
1326 },
1327 .impl = {
1328 .min_access_size = 1,
1329 .max_access_size = 8,
1330 .unaligned = true,
1331 },
1332};
1333
d2702032
PB		 1334bool memory_region_access_valid(MemoryRegion *mr,
1335 hwaddr addr,
1336 unsigned size,
1337 bool is_write)
093bc2cd 1338{
a014ed07
PB		 1339 int access_size_min, access_size_max;
1340 int access_size, i;
897fa7cf 1341
093bc2cd
AK		 1342 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1343 return false;
1344 }
1345
a014ed07 1346 if (!mr->ops->valid.accepts) {
093bc2cd
AK		 1347 return true;
1348 }
1349
a014ed07
PB		 1350 access_size_min = mr->ops->valid.min_access_size;
1351 if (!mr->ops->valid.min_access_size) {
1352 access_size_min = 1;
1353 }
1354
1355 access_size_max = mr->ops->valid.max_access_size;
1356 if (!mr->ops->valid.max_access_size) {
1357 access_size_max = 4;
1358 }
1359
1360 access_size = MAX(MIN(size, access_size_max), access_size_min);
1361 for (i = 0; i < size; i += access_size) {
1362 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1363 is_write)) {
1364 return false;
1365 }
093bc2cd 1366 }
a014ed07 1367
093bc2cd
AK		 1368 return true;
1369}
1370
cc05c43a
PM		 1371static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1372 hwaddr addr,
1373 uint64_t *pval,
1374 unsigned size,
1375 MemTxAttrs attrs)
093bc2cd 1376{
cc05c43a 1377 *pval = 0;
093bc2cd 1378
ce5d2f33 1379 if (mr->ops->read) {
cc05c43a
PM		 1380 return access_with_adjusted_size(addr, pval, size,
1381 mr->ops->impl.min_access_size,
1382 mr->ops->impl.max_access_size,
1383 memory_region_read_accessor,
1384 mr, attrs);
1385 } else if (mr->ops->read_with_attrs) {
1386 return access_with_adjusted_size(addr, pval, size,
1387 mr->ops->impl.min_access_size,
1388 mr->ops->impl.max_access_size,
1389 memory_region_read_with_attrs_accessor,
1390 mr, attrs);
ce5d2f33 1391 } else {
cc05c43a
PM		 1392 return access_with_adjusted_size(addr, pval, size, 1, 4,
1393 memory_region_oldmmio_read_accessor,
1394 mr, attrs);
74901c3b 1395 }
093bc2cd
AK		 1396}
1397
3b643495
PM		 1398MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1399 hwaddr addr,
1400 uint64_t *pval,
1401 unsigned size,
1402 MemTxAttrs attrs)
a621f38d 1403{
cc05c43a
PM		 1404 MemTxResult r;
1405
791af8c8
PB		 1406 if (!memory_region_access_valid(mr, addr, size, false)) {
1407 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1408 return MEMTX_DECODE_ERROR;
791af8c8 1409 }
a621f38d 1410
cc05c43a 1411 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1412 adjust_endianness(mr, pval, size);
cc05c43a 1413 return r;
a621f38d 1414}
093bc2cd 1415
8c56c1a5
PF		 1416/* Return true if an eventfd was signalled */
1417static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1418 hwaddr addr,
1419 uint64_t data,
1420 unsigned size,
1421 MemTxAttrs attrs)
1422{
1423 MemoryRegionIoeventfd ioeventfd = {
1424 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1425 .data = data,
1426 };
1427 unsigned i;
1428
1429 for (i = 0; i < mr->ioeventfd_nb; i++) {
1430 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1431 ioeventfd.e = mr->ioeventfds[i].e;
1432
1433 if (memory_region_ioeventfd_equal(ioeventfd, mr->ioeventfds[i])) {
1434 event_notifier_set(ioeventfd.e);
1435 return true;
1436 }
1437 }
1438
1439 return false;
1440}
1441
3b643495
PM		 1442MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1443 hwaddr addr,
1444 uint64_t data,
1445 unsigned size,
1446 MemTxAttrs attrs)
a621f38d 1447{
897fa7cf 1448 if (!memory_region_access_valid(mr, addr, size, true)) {
b018ddf6 1449 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1450 return MEMTX_DECODE_ERROR;
093bc2cd
AK		 1451 }
1452
a621f38d
AK		 1453 adjust_endianness(mr, &data, size);
1454
8c56c1a5
PF		 1455 if ((!kvm_eventfds_enabled()) &&
1456 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1457 return MEMTX_OK;
1458 }
1459
ce5d2f33 1460 if (mr->ops->write) {
cc05c43a
PM		 1461 return access_with_adjusted_size(addr, &data, size,
1462 mr->ops->impl.min_access_size,
1463 mr->ops->impl.max_access_size,
1464 memory_region_write_accessor, mr,
1465 attrs);
1466 } else if (mr->ops->write_with_attrs) {
1467 return
1468 access_with_adjusted_size(addr, &data, size,
1469 mr->ops->impl.min_access_size,
1470 mr->ops->impl.max_access_size,
1471 memory_region_write_with_attrs_accessor,
1472 mr, attrs);
ce5d2f33 1473 } else {
cc05c43a
PM		 1474 return access_with_adjusted_size(addr, &data, size, 1, 4,
1475 memory_region_oldmmio_write_accessor,
1476 mr, attrs);
74901c3b 1477 }
093bc2cd
AK		 1478}
1479
093bc2cd 1480void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1481 Object *owner,
093bc2cd
AK		 1482 const MemoryRegionOps *ops,
1483 void *opaque,
1484 const char *name,
1485 uint64_t size)
1486{
2c9b15ca 1487 memory_region_init(mr, owner, name, size);
6d6d2abf 1488 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1489 mr->opaque = opaque;
14a3c10a 1490 mr->terminates = true;
093bc2cd
AK		 1491}
1492
1cfe48c1
PM		 1493void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1494 Object *owner,
1495 const char *name,
1496 uint64_t size,
1497 Error **errp)
093bc2cd 1498{
2c9b15ca 1499 memory_region_init(mr, owner, name, size);
8ea9252a 1500 mr->ram = true;
14a3c10a 1501 mr->terminates = true;
545e92e0 1502 mr->destructor = memory_region_destructor_ram;
8e41fb63 1503 mr->ram_block = qemu_ram_alloc(size, mr, errp);
677e7805 1504 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
0b183fc8
PB		 1505}
1506
60786ef3
MT		 1507void memory_region_init_resizeable_ram(MemoryRegion *mr,
1508 Object *owner,
1509 const char *name,
1510 uint64_t size,
1511 uint64_t max_size,
1512 void (*resized)(const char*,
1513 uint64_t length,
1514 void *host),
1515 Error **errp)
1516{
1517 memory_region_init(mr, owner, name, size);
1518 mr->ram = true;
1519 mr->terminates = true;
1520 mr->destructor = memory_region_destructor_ram;
8e41fb63
FZ		 1521 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1522 mr, errp);
677e7805 1523 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
60786ef3
MT		 1524}
1525
0b183fc8
PB		 1526#ifdef __linux__
1527void memory_region_init_ram_from_file(MemoryRegion *mr,
1528 struct Object *owner,
1529 const char *name,
1530 uint64_t size,
dbcb8981 1531 bool share,
7f56e740
PB		 1532 const char *path,
1533 Error **errp)
0b183fc8
PB		 1534{
1535 memory_region_init(mr, owner, name, size);
1536 mr->ram = true;
1537 mr->terminates = true;
1538 mr->destructor = memory_region_destructor_ram;
8e41fb63 1539 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
677e7805 1540 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
093bc2cd 1541}
fea617c5
MAL		 1542
1543void memory_region_init_ram_from_fd(MemoryRegion *mr,
1544 struct Object *owner,
1545 const char *name,
1546 uint64_t size,
1547 bool share,
1548 int fd,
1549 Error **errp)
1550{
1551 memory_region_init(mr, owner, name, size);
1552 mr->ram = true;
1553 mr->terminates = true;
1554 mr->destructor = memory_region_destructor_ram;
1555 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1556 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1557}
0b183fc8 1558#endif
093bc2cd
AK		 1559
1560void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1561 Object *owner,
093bc2cd
AK		 1562 const char *name,
1563 uint64_t size,
1564 void *ptr)
1565{
2c9b15ca 1566 memory_region_init(mr, owner, name, size);
8ea9252a 1567 mr->ram = true;
14a3c10a 1568 mr->terminates = true;
fc3e7665 1569 mr->destructor = memory_region_destructor_ram;
677e7805 1570 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT		 1571
1572 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1573 assert(ptr != NULL);
8e41fb63 1574 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK		 1575}
1576
21e00fa5
AW		 1577void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1578 Object *owner,
1579 const char *name,
1580 uint64_t size,
1581 void *ptr)
e4dc3f59 1582{
21e00fa5
AW		 1583 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1584 mr->ram_device = true;
4a2e242b
AW		 1585 mr->ops = &ram_device_mem_ops;
1586 mr->opaque = mr;
e4dc3f59
ND		 1587}
1588
093bc2cd 1589void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1590 Object *owner,
093bc2cd
AK		 1591 const char *name,
1592 MemoryRegion *orig,
a8170e5e 1593 hwaddr offset,
093bc2cd
AK		 1594 uint64_t size)
1595{
2c9b15ca 1596 memory_region_init(mr, owner, name, size);
093bc2cd
AK		 1597 mr->alias = orig;
1598 mr->alias_offset = offset;
1599}
1600
b59821a9
PM		 1601void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1602 struct Object *owner,
1603 const char *name,
1604 uint64_t size,
1605 Error **errp)
a1777f7f
PM		 1606{
1607 memory_region_init(mr, owner, name, size);
1608 mr->ram = true;
1609 mr->readonly = true;
1610 mr->terminates = true;
1611 mr->destructor = memory_region_destructor_ram;
1612 mr->ram_block = qemu_ram_alloc(size, mr, errp);
1613 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1614}
1615
b59821a9
PM		 1616void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1617 Object *owner,
1618 const MemoryRegionOps *ops,
1619 void *opaque,
1620 const char *name,
1621 uint64_t size,
1622 Error **errp)
d0a9b5bc 1623{
39e0b03d 1624 assert(ops);
2c9b15ca 1625 memory_region_init(mr, owner, name, size);
7bc2b9cd 1626 mr->ops = ops;
75f5941c 1627 mr->opaque = opaque;
d0a9b5bc 1628 mr->terminates = true;
75c578dc 1629 mr->rom_device = true;
58268c8d 1630 mr->destructor = memory_region_destructor_ram;
8e41fb63 1631 mr->ram_block = qemu_ram_alloc(size, mr, errp);
d0a9b5bc
AK		 1632}
1633
1221a474
AK		 1634void memory_region_init_iommu(void *_iommu_mr,
1635 size_t instance_size,
1636 const char *mrtypename,
2c9b15ca 1637 Object *owner,
30951157
AK		 1638 const char *name,
1639 uint64_t size)
1640{
1221a474 1641 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK		 1642 struct MemoryRegion *mr;
1643
1221a474
AK		 1644 object_initialize(_iommu_mr, instance_size, mrtypename);
1645 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK		 1646 memory_region_do_init(mr, owner, name, size);
1647 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1648 mr->terminates = true; /* then re-forwards */
3df9d748
AK		 1649 QLIST_INIT(&iommu_mr->iommu_notify);
1650 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK		 1651}
1652
b4fefef9 1653static void memory_region_finalize(Object *obj)
093bc2cd 1654{
b4fefef9
PC		 1655 MemoryRegion *mr = MEMORY_REGION(obj);
1656
2e2b8eb7
PB		 1657 assert(!mr->container);
1658
1659 /* We know the region is not visible in any address space (it
1660 * does not have a container and cannot be a root either because
1661 * it has no references, so we can blindly clear mr->enabled.
1662 * memory_region_set_enabled instead could trigger a transaction
1663 * and cause an infinite loop.
1664 */
1665 mr->enabled = false;
1666 memory_region_transaction_begin();
1667 while (!QTAILQ_EMPTY(&mr->subregions)) {
1668 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1669 memory_region_del_subregion(mr, subregion);
1670 }
1671 memory_region_transaction_commit();
1672
545e92e0 1673 mr->destructor(mr);
093bc2cd 1674 memory_region_clear_coalescing(mr);
302fa283 1675 g_free((char *)mr->name);
7267c094 1676 g_free(mr->ioeventfds);
093bc2cd
AK		 1677}
1678
803c0816
PB		 1679Object *memory_region_owner(MemoryRegion *mr)
1680{
22a893e4
PB		 1681 Object *obj = OBJECT(mr);
1682 return obj->parent;
803c0816
PB		 1683}
1684
46637be2
PB		 1685void memory_region_ref(MemoryRegion *mr)
1686{
22a893e4
PB		 1687 /* MMIO callbacks most likely will access data that belongs
1688 * to the owner, hence the need to ref/unref the owner whenever
1689 * the memory region is in use.
1690 *
1691 * The memory region is a child of its owner. As long as the
1692 * owner doesn't call unparent itself on the memory region,
1693 * ref-ing the owner will also keep the memory region alive.
612263cf
PB		 1694 * Memory regions without an owner are supposed to never go away;
1695 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1696 */
612263cf
PB		 1697 if (mr && mr->owner) {
1698 object_ref(mr->owner);
46637be2
PB		 1699 }
1700}
1701
1702void memory_region_unref(MemoryRegion *mr)
1703{
612263cf
PB		 1704 if (mr && mr->owner) {
1705 object_unref(mr->owner);
46637be2
PB		 1706 }
1707}
1708
093bc2cd
AK		 1709uint64_t memory_region_size(MemoryRegion *mr)
1710{
08dafab4
AK		 1711 if (int128_eq(mr->size, int128_2_64())) {
1712 return UINT64_MAX;
1713 }
1714 return int128_get64(mr->size);
093bc2cd
AK		 1715}
1716
5d546d4b 1717const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1718{
d1dd32af
PC		 1719 if (!mr->name) {
1720 ((MemoryRegion *)mr)->name =
1721 object_get_canonical_path_component(OBJECT(mr));
1722 }
302fa283 1723 return mr->name;
8991c79b
AK		 1724}
1725
21e00fa5 1726bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1727{
21e00fa5 1728 return mr->ram_device;
e4dc3f59
ND		 1729}
1730
2d1a35be 1731uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1732{
6f6a5ef3 1733 uint8_t mask = mr->dirty_log_mask;
adaad61c 1734 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB		 1735 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1736 }
1737 return mask;
55043ba3
AK		 1738}
1739
2d1a35be
PB		 1740bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1741{
1742 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1743}
1744
3df9d748 1745static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
5bf3d319
PX		 1746{
1747 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1748 IOMMUNotifier *iommu_notifier;
1221a474 1749 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
5bf3d319 1750
3df9d748 1751 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX		 1752 flags |= iommu_notifier->notifier_flags;
1753 }
1754
1221a474
AK		 1755 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1756 imrc->notify_flag_changed(iommu_mr,
1757 iommu_mr->iommu_notify_flags,
1758 flags);
5bf3d319
PX		 1759 }
1760
3df9d748 1761 iommu_mr->iommu_notify_flags = flags;
5bf3d319
PX		 1762}
1763
cdb30812
PX		 1764void memory_region_register_iommu_notifier(MemoryRegion *mr,
1765 IOMMUNotifier *n)
06866575 1766{
3df9d748
AK		 1767 IOMMUMemoryRegion *iommu_mr;
1768
efcd38c5
JW		 1769 if (mr->alias) {
1770 memory_region_register_iommu_notifier(mr->alias, n);
1771 return;
1772 }
1773
cdb30812 1774 /* We need to register for at least one bitfield */
3df9d748 1775 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1776 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1777 assert(n->start <= n->end);
3df9d748
AK		 1778 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1779 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG		 1780}
1781
3df9d748 1782uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1783{
1221a474
AK		 1784 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1785
1786 if (imrc->get_min_page_size) {
1787 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK		 1788 }
1789 return TARGET_PAGE_SIZE;
1790}
1791
3df9d748 1792void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1793{
3df9d748 1794 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1795 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1796 hwaddr addr, granularity;
a788f227
DG		 1797 IOMMUTLBEntry iotlb;
1798
faa362e3 1799 /* If the IOMMU has its own replay callback, override */
1221a474
AK		 1800 if (imrc->replay) {
1801 imrc->replay(iommu_mr, n);
faa362e3
PX		 1802 return;
1803 }
1804
3df9d748 1805 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1806
a788f227 1807 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1221a474 1808 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE);
a788f227
DG		 1809 if (iotlb.perm != IOMMU_NONE) {
1810 n->notify(n, &iotlb);
1811 }
1812
1813 /* if (2^64 - MR size) < granularity, it's possible to get an
1814 * infinite loop here. This should catch such a wraparound */
1815 if ((addr + granularity) < addr) {
1816 break;
1817 }
1818 }
1819}
1820
3df9d748 1821void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
de472e4a
PX		 1822{
1823 IOMMUNotifier *notifier;
1824
3df9d748
AK		 1825 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1826 memory_region_iommu_replay(iommu_mr, notifier);
de472e4a
PX		 1827 }
1828}
1829
cdb30812
PX		 1830void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1831 IOMMUNotifier *n)
06866575 1832{
3df9d748
AK		 1833 IOMMUMemoryRegion *iommu_mr;
1834
efcd38c5
JW		 1835 if (mr->alias) {
1836 memory_region_unregister_iommu_notifier(mr->alias, n);
1837 return;
1838 }
cdb30812 1839 QLIST_REMOVE(n, node);
3df9d748
AK		 1840 iommu_mr = IOMMU_MEMORY_REGION(mr);
1841 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG		 1842}
1843
bd2bfa4c
PX		 1844void memory_region_notify_one(IOMMUNotifier *notifier,
1845 IOMMUTLBEntry *entry)
06866575 1846{
cdb30812
PX		 1847 IOMMUNotifierFlag request_flags;
1848
bd2bfa4c
PX		 1849 /*
1850 * Skip the notification if the notification does not overlap
1851 * with registered range.
1852 */
1853 if (notifier->start > entry->iova + entry->addr_mask + 1 ||
1854 notifier->end < entry->iova) {
1855 return;
1856 }
cdb30812 1857
bd2bfa4c 1858 if (entry->perm & IOMMU_RW) {
cdb30812
PX		 1859 request_flags = IOMMU_NOTIFIER_MAP;
1860 } else {
1861 request_flags = IOMMU_NOTIFIER_UNMAP;
1862 }
1863
bd2bfa4c
PX		 1864 if (notifier->notifier_flags & request_flags) {
1865 notifier->notify(notifier, entry);
1866 }
1867}
1868
3df9d748 1869void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
bd2bfa4c
PX		 1870 IOMMUTLBEntry entry)
1871{
1872 IOMMUNotifier *iommu_notifier;
1873
3df9d748 1874 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1875
3df9d748 1876 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
bd2bfa4c 1877 memory_region_notify_one(iommu_notifier, &entry);
cdb30812 1878 }
06866575
DG		 1879}
1880
093bc2cd
AK		 1881void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1882{
5a583347 1883 uint8_t mask = 1 << client;
deb809ed 1884 uint8_t old_logging;
5a583347 1885
dbddac6d 1886 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB		 1887 old_logging = mr->vga_logging_count;
1888 mr->vga_logging_count += log ? 1 : -1;
1889 if (!!old_logging == !!mr->vga_logging_count) {
1890 return;
1891 }
1892
59023ef4 1893 memory_region_transaction_begin();
5a583347 1894 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1895 memory_region_update_pending |= mr->enabled;
59023ef4 1896 memory_region_transaction_commit();
093bc2cd
AK		 1897}
1898
a8170e5e
AK		 1899bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1900 hwaddr size, unsigned client)
093bc2cd 1901{
8e41fb63
FZ		 1902 assert(mr->ram_block);
1903 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1904 size, client);
093bc2cd
AK		 1905}
1906
a8170e5e
AK		 1907void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1908 hwaddr size)
093bc2cd 1909{
8e41fb63
FZ		 1910 assert(mr->ram_block);
1911 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1912 size,
58d2707e 1913 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK		 1914}
1915
6c279db8
JQ		 1916bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1917 hwaddr size, unsigned client)
1918{
8e41fb63
FZ		 1919 assert(mr->ram_block);
1920 return cpu_physical_memory_test_and_clear_dirty(
1921 memory_region_get_ram_addr(mr) + addr, size, client);
6c279db8
JQ		 1922}
1923
8deaf12c
GH		 1924DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
1925 hwaddr addr,
1926 hwaddr size,
1927 unsigned client)
1928{
1929 assert(mr->ram_block);
1930 return cpu_physical_memory_snapshot_and_clear_dirty(
1931 memory_region_get_ram_addr(mr) + addr, size, client);
1932}
1933
1934bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
1935 hwaddr addr, hwaddr size)
1936{
1937 assert(mr->ram_block);
1938 return cpu_physical_memory_snapshot_get_dirty(snap,
1939 memory_region_get_ram_addr(mr) + addr, size);
1940}
6c279db8 1941
093bc2cd
AK		 1942void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1943{
0a752eee 1944 MemoryListener *listener;
0d673e36 1945 AddressSpace *as;
0a752eee 1946 FlatView *view;
5a583347
AK		 1947 FlatRange *fr;
1948
0a752eee
PB		 1949 /* If the same address space has multiple log_sync listeners, we
1950 * visit that address space's FlatView multiple times. But because
1951 * log_sync listeners are rare, it's still cheaper than walking each
1952 * address space once.
1953 */
1954 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1955 if (!listener->log_sync) {
1956 continue;
1957 }
1958 as = listener->address_space;
1959 view = address_space_get_flatview(as);
99e86347 1960 FOR_EACH_FLAT_RANGE(fr, view) {
0d673e36 1961 if (fr->mr == mr) {
16620684 1962 MemoryRegionSection mrs = section_from_flat_range(fr, view);
0a752eee 1963 listener->log_sync(listener, &mrs);
0d673e36 1964 }
5a583347 1965 }
856d7245 1966 flatview_unref(view);
5a583347 1967 }
093bc2cd
AK		 1968}
1969
1970void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1971{
fb1cd6f9 1972 if (mr->readonly != readonly) {
59023ef4 1973 memory_region_transaction_begin();
fb1cd6f9 1974 mr->readonly = readonly;
22bde714 1975 memory_region_update_pending |= mr->enabled;
59023ef4 1976 memory_region_transaction_commit();
fb1cd6f9 1977 }
093bc2cd
AK		 1978}
1979
5f9a5ea1 1980void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 1981{
5f9a5ea1 1982 if (mr->romd_mode != romd_mode) {
59023ef4 1983 memory_region_transaction_begin();
5f9a5ea1 1984 mr->romd_mode = romd_mode;
22bde714 1985 memory_region_update_pending |= mr->enabled;
59023ef4 1986 memory_region_transaction_commit();
d0a9b5bc
AK		 1987 }
1988}
1989
a8170e5e
AK		 1990void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
1991 hwaddr size, unsigned client)
093bc2cd 1992{
8e41fb63
FZ		 1993 assert(mr->ram_block);
1994 cpu_physical_memory_test_and_clear_dirty(
1995 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK		 1996}
1997
a35ba7be
PB		 1998int memory_region_get_fd(MemoryRegion *mr)
1999{
4ff87573
PB		 2000 int fd;
2001
2002 rcu_read_lock();
2003 while (mr->alias) {
2004 mr = mr->alias;
a35ba7be 2005 }
4ff87573
PB		 2006 fd = mr->ram_block->fd;
2007 rcu_read_unlock();
a35ba7be 2008
4ff87573
PB		 2009 return fd;
2010}
a35ba7be 2011
093bc2cd
AK		 2012void *memory_region_get_ram_ptr(MemoryRegion *mr)
2013{
49b24afc
PB		 2014 void *ptr;
2015 uint64_t offset = 0;
093bc2cd 2016
49b24afc
PB		 2017 rcu_read_lock();
2018 while (mr->alias) {
2019 offset += mr->alias_offset;
2020 mr = mr->alias;
2021 }
8e41fb63 2022 assert(mr->ram_block);
0878d0e1 2023 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
49b24afc 2024 rcu_read_unlock();
093bc2cd 2025
0878d0e1 2026 return ptr;
093bc2cd
AK		 2027}
2028
07bdaa41
PB		 2029MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2030{
2031 RAMBlock *block;
2032
2033 block = qemu_ram_block_from_host(ptr, false, offset);
2034 if (!block) {
2035 return NULL;
2036 }
2037
2038 return block->mr;
2039}
2040
7ebb2745
FZ		 2041ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2042{
2043 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2044}
2045
37d7c084
PB		 2046void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2047{
8e41fb63 2048 assert(mr->ram_block);
37d7c084 2049
fa53a0e5 2050 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB		 2051}
2052
0d673e36 2053static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 2054{
99e86347 2055 FlatView *view;
093bc2cd
AK		 2056 FlatRange *fr;
2057 CoalescedMemoryRange *cmr;
2058 AddrRange tmp;
95d2994a 2059 MemoryRegionSection section;
093bc2cd 2060
856d7245 2061 view = address_space_get_flatview(as);
99e86347 2062 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 2063 if (fr->mr == mr) {
95d2994a 2064 section = (MemoryRegionSection) {
16620684 2065 .fv = view,
95d2994a 2066 .offset_within_address_space = int128_get64(fr->addr.start),
052e87b0 2067 .size = fr->addr.size,
95d2994a
AK		 2068 };
2069
9a54635d 2070 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
95d2994a
AK		 2071 int128_get64(fr->addr.start),
2072 int128_get64(fr->addr.size));
093bc2cd
AK		 2073 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
2074 tmp = addrrange_shift(cmr->addr,
08dafab4
AK		 2075 int128_sub(fr->addr.start,
2076 int128_make64(fr->offset_in_region)));
093bc2cd
AK		 2077 if (!addrrange_intersects(tmp, fr->addr)) {
2078 continue;
2079 }
2080 tmp = addrrange_intersection(tmp, fr->addr);
9a54635d 2081 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
95d2994a
AK		 2082 int128_get64(tmp.start),
2083 int128_get64(tmp.size));
093bc2cd
AK		 2084 }
2085 }
2086 }
856d7245 2087 flatview_unref(view);
093bc2cd
AK		 2088}
2089
0d673e36
AK		 2090static void memory_region_update_coalesced_range(MemoryRegion *mr)
2091{
2092 AddressSpace *as;
2093
2094 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2095 memory_region_update_coalesced_range_as(mr, as);
2096 }
2097}
2098
093bc2cd
AK		 2099void memory_region_set_coalescing(MemoryRegion *mr)
2100{
2101 memory_region_clear_coalescing(mr);
08dafab4 2102 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK		 2103}
2104
2105void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 2106 hwaddr offset,
093bc2cd
AK		 2107 uint64_t size)
2108{
7267c094 2109 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2110
08dafab4 2111 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK		 2112 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2113 memory_region_update_coalesced_range(mr);
d410515e 2114 memory_region_set_flush_coalesced(mr);
093bc2cd
AK		 2115}
2116
2117void memory_region_clear_coalescing(MemoryRegion *mr)
2118{
2119 CoalescedMemoryRange *cmr;
ab5b3db5 2120 bool updated = false;
093bc2cd 2121
d410515e
JK		 2122 qemu_flush_coalesced_mmio_buffer();
2123 mr->flush_coalesced_mmio = false;
2124
093bc2cd
AK		 2125 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2126 cmr = QTAILQ_FIRST(&mr->coalesced);
2127 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 2128 g_free(cmr);
ab5b3db5
FZ		 2129 updated = true;
2130 }
2131
2132 if (updated) {
2133 memory_region_update_coalesced_range(mr);
093bc2cd 2134 }
093bc2cd
AK		 2135}
2136
d410515e
JK		 2137void memory_region_set_flush_coalesced(MemoryRegion *mr)
2138{
2139 mr->flush_coalesced_mmio = true;
2140}
2141
2142void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2143{
2144 qemu_flush_coalesced_mmio_buffer();
2145 if (QTAILQ_EMPTY(&mr->coalesced)) {
2146 mr->flush_coalesced_mmio = false;
2147 }
2148}
2149
196ea131
JK		 2150void memory_region_set_global_locking(MemoryRegion *mr)
2151{
2152 mr->global_locking = true;
2153}
2154
2155void memory_region_clear_global_locking(MemoryRegion *mr)
2156{
2157 mr->global_locking = false;
2158}
2159
8c56c1a5
PF		 2160static bool userspace_eventfd_warning;
2161
3e9d69e7 2162void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2163 hwaddr addr,
3e9d69e7
AK		 2164 unsigned size,
2165 bool match_data,
2166 uint64_t data,
753d5e14 2167 EventNotifier *e)
3e9d69e7
AK		 2168{
2169 MemoryRegionIoeventfd mrfd = {
08dafab4
AK		 2170 .addr.start = int128_make64(addr),
2171 .addr.size = int128_make64(size),
3e9d69e7
AK		 2172 .match_data = match_data,
2173 .data = data,
753d5e14 2174 .e = e,
3e9d69e7
AK		 2175 };
2176 unsigned i;
2177
8c56c1a5
PF		 2178 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2179 userspace_eventfd_warning))) {
2180 userspace_eventfd_warning = true;
2181 error_report("Using eventfd without MMIO binding in KVM. "
2182 "Suboptimal performance expected");
2183 }
2184
b8aecea2
JW		 2185 if (size) {
2186 adjust_endianness(mr, &mrfd.data, size);
2187 }
59023ef4 2188 memory_region_transaction_begin();
3e9d69e7
AK		 2189 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2190 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
2191 break;
2192 }
2193 }
2194 ++mr->ioeventfd_nb;
7267c094 2195 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK		 2196 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2197 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2198 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2199 mr->ioeventfds[i] = mrfd;
4dc56152 2200 ioeventfd_update_pending |= mr->enabled;
59023ef4 2201 memory_region_transaction_commit();
3e9d69e7
AK		 2202}
2203
2204void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2205 hwaddr addr,
3e9d69e7
AK		 2206 unsigned size,
2207 bool match_data,
2208 uint64_t data,
753d5e14 2209 EventNotifier *e)
3e9d69e7
AK		 2210{
2211 MemoryRegionIoeventfd mrfd = {
08dafab4
AK		 2212 .addr.start = int128_make64(addr),
2213 .addr.size = int128_make64(size),
3e9d69e7
AK		 2214 .match_data = match_data,
2215 .data = data,
753d5e14 2216 .e = e,
3e9d69e7
AK		 2217 };
2218 unsigned i;
2219
b8aecea2
JW		 2220 if (size) {
2221 adjust_endianness(mr, &mrfd.data, size);
2222 }
59023ef4 2223 memory_region_transaction_begin();
3e9d69e7
AK		 2224 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2225 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
2226 break;
2227 }
2228 }
2229 assert(i != mr->ioeventfd_nb);
2230 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2231 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2232 --mr->ioeventfd_nb;
7267c094 2233 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2234 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2235 ioeventfd_update_pending |= mr->enabled;
59023ef4 2236 memory_region_transaction_commit();
3e9d69e7
AK		 2237}
2238
feca4ac1 2239static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2240{
feca4ac1 2241 MemoryRegion *mr = subregion->container;
093bc2cd
AK		 2242 MemoryRegion *other;
2243
59023ef4
JK		 2244 memory_region_transaction_begin();
2245
dfde4e6e 2246 memory_region_ref(subregion);
093bc2cd
AK		 2247 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2248 if (subregion->priority >= other->priority) {
2249 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2250 goto done;
2251 }
2252 }
2253 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2254done:
22bde714 2255 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2256 memory_region_transaction_commit();
093bc2cd
AK		 2257}
2258
0598701a
PC		 2259static void memory_region_add_subregion_common(MemoryRegion *mr,
2260 hwaddr offset,
2261 MemoryRegion *subregion)
2262{
feca4ac1
PB		 2263 assert(!subregion->container);
2264 subregion->container = mr;
0598701a 2265 subregion->addr = offset;
feca4ac1 2266 memory_region_update_container_subregions(subregion);
0598701a 2267}
093bc2cd
AK		 2268
2269void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2270 hwaddr offset,
093bc2cd
AK		 2271 MemoryRegion *subregion)
2272{
093bc2cd
AK		 2273 subregion->priority = 0;
2274 memory_region_add_subregion_common(mr, offset, subregion);
2275}
2276
2277void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2278 hwaddr offset,
093bc2cd 2279 MemoryRegion *subregion,
a1ff8ae0 2280 int priority)
093bc2cd 2281{
093bc2cd
AK		 2282 subregion->priority = priority;
2283 memory_region_add_subregion_common(mr, offset, subregion);
2284}
2285
2286void memory_region_del_subregion(MemoryRegion *mr,
2287 MemoryRegion *subregion)
2288{
59023ef4 2289 memory_region_transaction_begin();
feca4ac1
PB		 2290 assert(subregion->container == mr);
2291 subregion->container = NULL;
093bc2cd 2292 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2293 memory_region_unref(subregion);
22bde714 2294 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2295 memory_region_transaction_commit();
6bba19ba
AK		 2296}
2297
2298void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2299{
2300 if (enabled == mr->enabled) {
2301 return;
2302 }
59023ef4 2303 memory_region_transaction_begin();
6bba19ba 2304 mr->enabled = enabled;
22bde714 2305 memory_region_update_pending = true;
59023ef4 2306 memory_region_transaction_commit();
093bc2cd 2307}
1c0ffa58 2308
e7af4c67
MT		 2309void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2310{
2311 Int128 s = int128_make64(size);
2312
2313 if (size == UINT64_MAX) {
2314 s = int128_2_64();
2315 }
2316 if (int128_eq(s, mr->size)) {
2317 return;
2318 }
2319 memory_region_transaction_begin();
2320 mr->size = s;
2321 memory_region_update_pending = true;
2322 memory_region_transaction_commit();
2323}
2324
67891b8a 2325static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2326{
feca4ac1 2327 MemoryRegion *container = mr->container;
2282e1af 2328
feca4ac1 2329 if (container) {
67891b8a
PC		 2330 memory_region_transaction_begin();
2331 memory_region_ref(mr);
feca4ac1
PB		 2332 memory_region_del_subregion(container, mr);
2333 mr->container = container;
2334 memory_region_update_container_subregions(mr);
67891b8a
PC		 2335 memory_region_unref(mr);
2336 memory_region_transaction_commit();
2282e1af 2337 }
67891b8a 2338}
2282e1af 2339
67891b8a
PC		 2340void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2341{
2342 if (addr != mr->addr) {
2343 mr->addr = addr;
2344 memory_region_readd_subregion(mr);
2345 }
2282e1af
AK		 2346}
2347
a8170e5e 2348void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2349{
4703359e 2350 assert(mr->alias);
4703359e 2351
59023ef4 2352 if (offset == mr->alias_offset) {
4703359e
AK		 2353 return;
2354 }
2355
59023ef4
JK		 2356 memory_region_transaction_begin();
2357 mr->alias_offset = offset;
22bde714 2358 memory_region_update_pending |= mr->enabled;
59023ef4 2359 memory_region_transaction_commit();
4703359e
AK		 2360}
2361
a2b257d6
IM		 2362uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2363{
2364 return mr->align;
2365}
2366
e2177955
AK		 2367static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2368{
2369 const AddrRange *addr = addr_;
2370 const FlatRange *fr = fr_;
2371
2372 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2373 return -1;
2374 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2375 return 1;
2376 }
2377 return 0;
2378}
2379
99e86347 2380static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2381{
99e86347 2382 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK		 2383 sizeof(FlatRange), cmp_flatrange_addr);
2384}
2385
eed2bacf
IM		 2386bool memory_region_is_mapped(MemoryRegion *mr)
2387{
2388 return mr->container ? true : false;
2389}
2390
c6742b14
PB		 2391/* Same as memory_region_find, but it does not add a reference to the
2392 * returned region. It must be called from an RCU critical section.
2393 */
2394static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2395 hwaddr addr, uint64_t size)
e2177955 2396{
052e87b0 2397 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB		 2398 MemoryRegion *root;
2399 AddressSpace *as;
2400 AddrRange range;
99e86347 2401 FlatView *view;
73034e9e
PB		 2402 FlatRange *fr;
2403
2404 addr += mr->addr;
feca4ac1
PB		 2405 for (root = mr; root->container; ) {
2406 root = root->container;
73034e9e
PB		 2407 addr += root->addr;
2408 }
e2177955 2409
73034e9e 2410 as = memory_region_to_address_space(root);
eed2bacf
IM		 2411 if (!as) {
2412 return ret;
2413 }
73034e9e 2414 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2415
16620684 2416 view = address_space_to_flatview(as);
99e86347 2417 fr = flatview_lookup(view, range);
e2177955 2418 if (!fr) {
c6742b14 2419 return ret;
e2177955
AK		 2420 }
2421
99e86347 2422 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK		 2423 --fr;
2424 }
2425
2426 ret.mr = fr->mr;
16620684 2427 ret.fv = view;
e2177955
AK		 2428 range = addrrange_intersection(range, fr->addr);
2429 ret.offset_within_region = fr->offset_in_region;
2430 ret.offset_within_region += int128_get64(int128_sub(range.start,
2431 fr->addr.start));
052e87b0 2432 ret.size = range.size;
e2177955 2433 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2434 ret.readonly = fr->readonly;
c6742b14
PB		 2435 return ret;
2436}
2437
2438MemoryRegionSection memory_region_find(MemoryRegion *mr,
2439 hwaddr addr, uint64_t size)
2440{
2441 MemoryRegionSection ret;
2442 rcu_read_lock();
2443 ret = memory_region_find_rcu(mr, addr, size);
2444 if (ret.mr) {
2445 memory_region_ref(ret.mr);
2446 }
2b647668 2447 rcu_read_unlock();
e2177955
AK		 2448 return ret;
2449}
2450
c6742b14
PB		 2451bool memory_region_present(MemoryRegion *container, hwaddr addr)
2452{
2453 MemoryRegion *mr;
2454
2455 rcu_read_lock();
2456 mr = memory_region_find_rcu(container, addr, 1).mr;
2457 rcu_read_unlock();
2458 return mr && mr != container;
2459}
2460
9c1f8f44 2461void memory_global_dirty_log_sync(void)
86e775c6 2462{
9c1f8f44
PB		 2463 MemoryListener *listener;
2464 AddressSpace *as;
99e86347 2465 FlatView *view;
7664e80c
AK		 2466 FlatRange *fr;
2467
9c1f8f44
PB		 2468 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2469 if (!listener->log_sync) {
2470 continue;
2471 }
d45fa784 2472 as = listener->address_space;
9c1f8f44
PB		 2473 view = address_space_get_flatview(as);
2474 FOR_EACH_FLAT_RANGE(fr, view) {
adaad61c 2475 if (fr->dirty_log_mask) {
16620684
AK		 2476 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2477
adaad61c
PB		 2478 listener->log_sync(listener, &mrs);
2479 }
9c1f8f44
PB		 2480 }
2481 flatview_unref(view);
7664e80c
AK		 2482 }
2483}
2484
19310760
JZ		 2485static VMChangeStateEntry *vmstate_change;
2486
7664e80c
AK		 2487void memory_global_dirty_log_start(void)
2488{
19310760
JZ		 2489 if (vmstate_change) {
2490 qemu_del_vm_change_state_handler(vmstate_change);
2491 vmstate_change = NULL;
2492 }
2493
7664e80c 2494 global_dirty_log = true;
6f6a5ef3 2495
7376e582 2496 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3
PB		 2497
2498 /* Refresh DIRTY_LOG_MIGRATION bit. */
2499 memory_region_transaction_begin();
2500 memory_region_update_pending = true;
2501 memory_region_transaction_commit();
7664e80c
AK		 2502}
2503
19310760 2504static void memory_global_dirty_log_do_stop(void)
7664e80c 2505{
7664e80c 2506 global_dirty_log = false;
6f6a5ef3
PB		 2507
2508 /* Refresh DIRTY_LOG_MIGRATION bit. */
2509 memory_region_transaction_begin();
2510 memory_region_update_pending = true;
2511 memory_region_transaction_commit();
2512
7376e582 2513 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK		 2514}
2515
19310760
JZ		 2516static void memory_vm_change_state_handler(void *opaque, int running,
2517 RunState state)
2518{
2519 if (running) {
2520 memory_global_dirty_log_do_stop();
2521
2522 if (vmstate_change) {
2523 qemu_del_vm_change_state_handler(vmstate_change);
2524 vmstate_change = NULL;
2525 }
2526 }
2527}
2528
2529void memory_global_dirty_log_stop(void)
2530{
2531 if (!runstate_is_running()) {
2532 if (vmstate_change) {
2533 return;
2534 }
2535 vmstate_change = qemu_add_vm_change_state_handler(
2536 memory_vm_change_state_handler, NULL);
2537 return;
2538 }
2539
2540 memory_global_dirty_log_do_stop();
2541}
2542
7664e80c
AK		 2543static void listener_add_address_space(MemoryListener *listener,
2544 AddressSpace *as)
2545{
99e86347 2546 FlatView *view;
7664e80c
AK		 2547 FlatRange *fr;
2548
680a4783
PB		 2549 if (listener->begin) {
2550 listener->begin(listener);
2551 }
7664e80c 2552 if (global_dirty_log) {
975aefe0
AK		 2553 if (listener->log_global_start) {
2554 listener->log_global_start(listener);
2555 }
7664e80c 2556 }
975aefe0 2557
856d7245 2558 view = address_space_get_flatview(as);
99e86347 2559 FOR_EACH_FLAT_RANGE(fr, view) {
7664e80c
AK		 2560 MemoryRegionSection section = {
2561 .mr = fr->mr,
16620684 2562 .fv = view,
7664e80c 2563 .offset_within_region = fr->offset_in_region,
052e87b0 2564 .size = fr->addr.size,
7664e80c 2565 .offset_within_address_space = int128_get64(fr->addr.start),
7a8499e8 2566 .readonly = fr->readonly,
7664e80c 2567 };
680a4783
PB		 2568 if (fr->dirty_log_mask && listener->log_start) {
2569 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2570 }
975aefe0
AK		 2571 if (listener->region_add) {
2572 listener->region_add(listener, &section);
2573 }
7664e80c 2574 }
680a4783
PB		 2575 if (listener->commit) {
2576 listener->commit(listener);
2577 }
856d7245 2578 flatview_unref(view);
7664e80c
AK		 2579}
2580
d45fa784 2581void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2582{
72e22d2f
AK		 2583 MemoryListener *other = NULL;
2584
d45fa784 2585 listener->address_space = as;
72e22d2f
AK		 2586 if (QTAILQ_EMPTY(&memory_listeners)
2587 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2588 memory_listeners)->priority) {
2589 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2590 } else {
2591 QTAILQ_FOREACH(other, &memory_listeners, link) {
2592 if (listener->priority < other->priority) {
2593 break;
2594 }
2595 }
2596 QTAILQ_INSERT_BEFORE(other, listener, link);
2597 }
0d673e36 2598
9a54635d
PB		 2599 if (QTAILQ_EMPTY(&as->listeners)
2600 || listener->priority >= QTAILQ_LAST(&as->listeners,
2601 memory_listeners)->priority) {
2602 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2603 } else {
2604 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2605 if (listener->priority < other->priority) {
2606 break;
2607 }
2608 }
2609 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2610 }
2611
d45fa784 2612 listener_add_address_space(listener, as);
7664e80c
AK		 2613}
2614
2615void memory_listener_unregister(MemoryListener *listener)
2616{
1d8280c1
PB		 2617 if (!listener->address_space) {
2618 return;
2619 }
2620
72e22d2f 2621 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2622 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2623 listener->address_space = NULL;
86e775c6 2624}
e2177955 2625
c9356746
FK		 2626bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2627{
2628 void *host;
2629 unsigned size = 0;
2630 unsigned offset = 0;
2631 Object *new_interface;
2632
2633 if (!mr || !mr->ops->request_ptr) {
2634 return false;
2635 }
2636
2637 /*
2638 * Avoid an update if the request_ptr call
2639 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2640 * a cache.
2641 */
2642 memory_region_transaction_begin();
2643
2644 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2645
2646 if (!host || !size) {
2647 memory_region_transaction_commit();
2648 return false;
2649 }
2650
2651 new_interface = object_new("mmio_interface");
2652 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2653 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2654 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2655 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2656 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2657 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2658
2659 memory_region_transaction_commit();
2660 return true;
2661}
2662
2663typedef struct MMIOPtrInvalidate {
2664 MemoryRegion *mr;
2665 hwaddr offset;
2666 unsigned size;
2667 int busy;
2668 int allocated;
2669} MMIOPtrInvalidate;
2670
2671#define MAX_MMIO_INVALIDATE 10
2672static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2673
2674static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2675 run_on_cpu_data data)
2676{
2677 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2678 MemoryRegion *mr = invalidate_data->mr;
2679 hwaddr offset = invalidate_data->offset;
2680 unsigned size = invalidate_data->size;
2681 MemoryRegionSection section = memory_region_find(mr, offset, size);
2682
2683 qemu_mutex_lock_iothread();
2684
2685 /* Reset dirty so this doesn't happen later. */
2686 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2687
2688 if (section.mr != mr) {
2689 /* memory_region_find add a ref on section.mr */
2690 memory_region_unref(section.mr);
2691 if (MMIO_INTERFACE(section.mr->owner)) {
2692 /* We found the interface just drop it. */
2693 object_property_set_bool(section.mr->owner, false, "realized",
2694 NULL);
2695 object_unref(section.mr->owner);
2696 object_unparent(section.mr->owner);
2697 }
2698 }
2699
2700 qemu_mutex_unlock_iothread();
2701
2702 if (invalidate_data->allocated) {
2703 g_free(invalidate_data);
2704 } else {
2705 invalidate_data->busy = 0;
2706 }
2707}
2708
2709void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2710 unsigned size)
2711{
2712 size_t i;
2713 MMIOPtrInvalidate *invalidate_data = NULL;
2714
2715 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2716 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2717 invalidate_data = &mmio_ptr_invalidate_list[i];
2718 break;
2719 }
2720 }
2721
2722 if (!invalidate_data) {
2723 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2724 invalidate_data->allocated = 1;
2725 }
2726
2727 invalidate_data->mr = mr;
2728 invalidate_data->offset = offset;
2729 invalidate_data->size = size;
2730
2731 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2732 RUN_ON_CPU_HOST_PTR(invalidate_data));
2733}
2734
7dca8043 2735void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2736{
ac95190e 2737 memory_region_ref(root);
8786db7c 2738 as->root = root;
67ace39b 2739 as->current_map = NULL;
4c19eb72
AK		 2740 as->ioeventfd_nb = 0;
2741 as->ioeventfds = NULL;
9a54635d 2742 QTAILQ_INIT(&as->listeners);
0d673e36 2743 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2744 as->name = g_strdup(name ? name : "anonymous");
202fc01b
AK		 2745 address_space_update_topology(as);
2746 address_space_update_ioeventfds(as);
1c0ffa58 2747}
658b2224 2748
374f2981 2749static void do_address_space_destroy(AddressSpace *as)
83f3c251 2750{
9a54635d 2751 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2752
856d7245 2753 flatview_unref(as->current_map);
7dca8043 2754 g_free(as->name);
4c19eb72 2755 g_free(as->ioeventfds);
ac95190e 2756 memory_region_unref(as->root);
83f3c251
AK		 2757}
2758
374f2981
PB		 2759void address_space_destroy(AddressSpace *as)
2760{
ac95190e
PB		 2761 MemoryRegion *root = as->root;
2762
374f2981
PB		 2763 /* Flush out anything from MemoryListeners listening in on this */
2764 memory_region_transaction_begin();
2765 as->root = NULL;
2766 memory_region_transaction_commit();
2767 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2768
2769 /* At this point, as->dispatch and as->current_map are dummy
2770 * entries that the guest should never use. Wait for the old
2771 * values to expire before freeing the data.
2772 */
ac95190e 2773 as->root = root;
374f2981
PB		 2774 call_rcu(as, do_address_space_destroy, rcu);
2775}
2776
4e831901
PX		 2777static const char *memory_region_type(MemoryRegion *mr)
2778{
2779 if (memory_region_is_ram_device(mr)) {
2780 return "ramd";
2781 } else if (memory_region_is_romd(mr)) {
2782 return "romd";
2783 } else if (memory_region_is_rom(mr)) {
2784 return "rom";
2785 } else if (memory_region_is_ram(mr)) {
2786 return "ram";
2787 } else {
2788 return "i/o";
2789 }
2790}
2791
314e2987
BS		 2792typedef struct MemoryRegionList MemoryRegionList;
2793
2794struct MemoryRegionList {
2795 const MemoryRegion *mr;
a16878d2 2796 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS		 2797};
2798
a16878d2 2799typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
314e2987 2800
4e831901
PX		 2801#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2802 int128_sub((size), int128_one())) : 0)
2803#define MTREE_INDENT " "
2804
314e2987
BS		 2805static void mtree_print_mr(fprintf_function mon_printf, void *f,
2806 const MemoryRegion *mr, unsigned int level,
a8170e5e 2807 hwaddr base,
9479c57a 2808 MemoryRegionListHead *alias_print_queue)
314e2987 2809{
9479c57a
JK		 2810 MemoryRegionList *new_ml, *ml, *next_ml;
2811 MemoryRegionListHead submr_print_queue;
314e2987
BS		 2812 const MemoryRegion *submr;
2813 unsigned int i;
b31f8412 2814 hwaddr cur_start, cur_end;
314e2987 2815
f8a9f720 2816 if (!mr) {
314e2987
BS		 2817 return;
2818 }
2819
2820 for (i = 0; i < level; i++) {
4e831901 2821 mon_printf(f, MTREE_INDENT);
314e2987
BS		 2822 }
2823
b31f8412
PX		 2824 cur_start = base + mr->addr;
2825 cur_end = cur_start + MR_SIZE(mr->size);
2826
2827 /*
2828 * Try to detect overflow of memory region. This should never
2829 * happen normally. When it happens, we dump something to warn the
2830 * user who is observing this.
2831 */
2832 if (cur_start < base || cur_end < cur_start) {
2833 mon_printf(f, "[DETECTED OVERFLOW!] ");
2834 }
2835
314e2987
BS		 2836 if (mr->alias) {
2837 MemoryRegionList *ml;
2838 bool found = false;
2839
2840 /* check if the alias is already in the queue */
a16878d2 2841 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2842 if (ml->mr == mr->alias) {
314e2987
BS		 2843 found = true;
2844 }
2845 }
2846
2847 if (!found) {
2848 ml = g_new(MemoryRegionList, 1);
2849 ml->mr = mr->alias;
a16878d2 2850 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2851 }
4896d74b 2852 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
4e831901 2853 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
f8a9f720 2854 "-" TARGET_FMT_plx "%s\n",
b31f8412 2855 cur_start, cur_end,
4b474ba7 2856 mr->priority,
4e831901 2857 memory_region_type((MemoryRegion *)mr),
3fb18b4d
PC		 2858 memory_region_name(mr),
2859 memory_region_name(mr->alias),
314e2987 2860 mr->alias_offset,
4e831901 2861 mr->alias_offset + MR_SIZE(mr->size),
f8a9f720 2862 mr->enabled ? "" : " [disabled]");
314e2987 2863 } else {
4896d74b 2864 mon_printf(f,
4e831901 2865 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
b31f8412 2866 cur_start, cur_end,
4b474ba7 2867 mr->priority,
4e831901 2868 memory_region_type((MemoryRegion *)mr),
f8a9f720
GH		 2869 memory_region_name(mr),
2870 mr->enabled ? "" : " [disabled]");
314e2987 2871 }
9479c57a
JK		 2872
2873 QTAILQ_INIT(&submr_print_queue);
2874
314e2987 2875 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK		 2876 new_ml = g_new(MemoryRegionList, 1);
2877 new_ml->mr = submr;
a16878d2 2878 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK		 2879 if (new_ml->mr->addr < ml->mr->addr ||
2880 (new_ml->mr->addr == ml->mr->addr &&
2881 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 2882 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK		 2883 new_ml = NULL;
2884 break;
2885 }
2886 }
2887 if (new_ml) {
a16878d2 2888 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK		 2889 }
2890 }
2891
a16878d2 2892 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b31f8412 2893 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
9479c57a
JK		 2894 alias_print_queue);
2895 }
2896
a16878d2 2897 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 2898 g_free(ml);
314e2987
BS		 2899 }
2900}
2901
5e8fd947
AK		 2902struct FlatViewInfo {
2903 fprintf_function mon_printf;
2904 void *f;
2905 int counter;
2906 bool dispatch_tree;
2907};
2908
2909static void mtree_print_flatview(gpointer key, gpointer value,
2910 gpointer user_data)
57bb40c9 2911{
5e8fd947
AK		 2912 FlatView *view = key;
2913 GArray *fv_address_spaces = value;
2914 struct FlatViewInfo *fvi = user_data;
2915 fprintf_function p = fvi->mon_printf;
2916 void *f = fvi->f;
57bb40c9
PX		 2917 FlatRange *range = &view->ranges[0];
2918 MemoryRegion *mr;
2919 int n = view->nr;
5e8fd947
AK		 2920 int i;
2921 AddressSpace *as;
2922
2923 p(f, "FlatView #%d\n", fvi->counter);
2924 ++fvi->counter;
2925
2926 for (i = 0; i < fv_address_spaces->len; ++i) {
2927 as = g_array_index(fv_address_spaces, AddressSpace*, i);
2928 p(f, " AS \"%s\", root: %s", as->name, memory_region_name(as->root));
2929 if (as->root->alias) {
2930 p(f, ", alias %s", memory_region_name(as->root->alias));
2931 }
2932 p(f, "\n");
2933 }
2934
2935 p(f, " Root memory region: %s\n",
2936 view->root ? memory_region_name(view->root) : "(none)");
57bb40c9
PX		 2937
2938 if (n <= 0) {
5e8fd947 2939 p(f, MTREE_INDENT "No rendered FlatView\n\n");
57bb40c9
PX		 2940 return;
2941 }
2942
2943 while (n--) {
2944 mr = range->mr;
377a07aa
PB		 2945 if (range->offset_in_region) {
2946 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2947 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
2948 int128_get64(range->addr.start),
2949 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2950 mr->priority,
2951 range->readonly ? "rom" : memory_region_type(mr),
2952 memory_region_name(mr),
2953 range->offset_in_region);
2954 } else {
2955 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2956 TARGET_FMT_plx " (prio %d, %s): %s\n",
2957 int128_get64(range->addr.start),
2958 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2959 mr->priority,
2960 range->readonly ? "rom" : memory_region_type(mr),
2961 memory_region_name(mr));
2962 }
57bb40c9
PX		 2963 range++;
2964 }
2965
5e8fd947
AK		 2966#if !defined(CONFIG_USER_ONLY)
2967 if (fvi->dispatch_tree && view->root) {
2968 mtree_print_dispatch(p, f, view->dispatch, view->root);
2969 }
2970#endif
2971
2972 p(f, "\n");
2973}
2974
2975static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
2976 gpointer user_data)
2977{
2978 FlatView *view = key;
2979 GArray *fv_address_spaces = value;
2980
2981 g_array_unref(fv_address_spaces);
57bb40c9 2982 flatview_unref(view);
5e8fd947
AK		 2983
2984 return true;
57bb40c9
PX		 2985}
2986
5e8fd947
AK		 2987void mtree_info(fprintf_function mon_printf, void *f, bool flatview,
2988 bool dispatch_tree)
314e2987
BS		 2989{
2990 MemoryRegionListHead ml_head;
2991 MemoryRegionList *ml, *ml2;
0d673e36 2992 AddressSpace *as;
314e2987 2993
57bb40c9 2994 if (flatview) {
5e8fd947
AK		 2995 FlatView *view;
2996 struct FlatViewInfo fvi = {
2997 .mon_printf = mon_printf,
2998 .f = f,
2999 .counter = 0,
3000 .dispatch_tree = dispatch_tree
3001 };
3002 GArray *fv_address_spaces;
3003 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3004
3005 /* Gather all FVs in one table */
57bb40c9 3006 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
5e8fd947
AK		 3007 view = address_space_get_flatview(as);
3008
3009 fv_address_spaces = g_hash_table_lookup(views, view);
3010 if (!fv_address_spaces) {
3011 fv_address_spaces = g_array_new(false, false, sizeof(as));
3012 g_hash_table_insert(views, view, fv_address_spaces);
3013 }
3014
3015 g_array_append_val(fv_address_spaces, as);
57bb40c9 3016 }
5e8fd947
AK		 3017
3018 /* Print */
3019 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3020
3021 /* Free */
3022 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3023 g_hash_table_unref(views);
3024
57bb40c9
PX		 3025 return;
3026 }
3027
314e2987
BS		 3028 QTAILQ_INIT(&ml_head);
3029
0d673e36 3030 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
e48816aa
GH		 3031 mon_printf(f, "address-space: %s\n", as->name);
3032 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
3033 mon_printf(f, "\n");
b9f9be88
BS		 3034 }
3035
314e2987 3036 /* print aliased regions */
a16878d2 3037 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
e48816aa
GH		 3038 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
3039 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
3040 mon_printf(f, "\n");
314e2987
BS		 3041 }
3042
a16878d2 3043 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 3044 g_free(ml);
314e2987 3045 }
314e2987 3046}
b4fefef9 3047
b08199c6
PM		 3048void memory_region_init_ram(MemoryRegion *mr,
3049 struct Object *owner,
3050 const char *name,
3051 uint64_t size,
3052 Error **errp)
3053{
3054 DeviceState *owner_dev;
3055 Error *err = NULL;
3056
3057 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3058 if (err) {
3059 error_propagate(errp, err);
3060 return;
3061 }
3062 /* This will assert if owner is neither NULL nor a DeviceState.
3063 * We only want the owner here for the purposes of defining a
3064 * unique name for migration. TODO: Ideally we should implement
3065 * a naming scheme for Objects which are not DeviceStates, in
3066 * which case we can relax this restriction.
3067 */
3068 owner_dev = DEVICE(owner);
3069 vmstate_register_ram(mr, owner_dev);
3070}
3071
3072void memory_region_init_rom(MemoryRegion *mr,
3073 struct Object *owner,
3074 const char *name,
3075 uint64_t size,
3076 Error **errp)
3077{
3078 DeviceState *owner_dev;
3079 Error *err = NULL;
3080
3081 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3082 if (err) {
3083 error_propagate(errp, err);
3084 return;
3085 }
3086 /* This will assert if owner is neither NULL nor a DeviceState.
3087 * We only want the owner here for the purposes of defining a
3088 * unique name for migration. TODO: Ideally we should implement
3089 * a naming scheme for Objects which are not DeviceStates, in
3090 * which case we can relax this restriction.
3091 */
3092 owner_dev = DEVICE(owner);
3093 vmstate_register_ram(mr, owner_dev);
3094}
3095
3096void memory_region_init_rom_device(MemoryRegion *mr,
3097 struct Object *owner,
3098 const MemoryRegionOps *ops,
3099 void *opaque,
3100 const char *name,
3101 uint64_t size,
3102 Error **errp)
3103{
3104 DeviceState *owner_dev;
3105 Error *err = NULL;
3106
3107 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3108 name, size, &err);
3109 if (err) {
3110 error_propagate(errp, err);
3111 return;
3112 }
3113 /* This will assert if owner is neither NULL nor a DeviceState.
3114 * We only want the owner here for the purposes of defining a
3115 * unique name for migration. TODO: Ideally we should implement
3116 * a naming scheme for Objects which are not DeviceStates, in
3117 * which case we can relax this restriction.
3118 */
3119 owner_dev = DEVICE(owner);
3120 vmstate_register_ram(mr, owner_dev);
3121}
3122
b4fefef9
PC		 3123static const TypeInfo memory_region_info = {
3124 .parent = TYPE_OBJECT,
3125 .name = TYPE_MEMORY_REGION,
3126 .instance_size = sizeof(MemoryRegion),
3127 .instance_init = memory_region_initfn,
3128 .instance_finalize = memory_region_finalize,
3129};
3130
3df9d748
AK		 3131static const TypeInfo iommu_memory_region_info = {
3132 .parent = TYPE_MEMORY_REGION,
3133 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 3134 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK		 3135 .instance_size = sizeof(IOMMUMemoryRegion),
3136 .instance_init = iommu_memory_region_initfn,
1221a474 3137 .abstract = true,
3df9d748
AK		 3138};
3139
b4fefef9
PC		 3140static void memory_register_types(void)
3141{
3142 type_register_static(&memory_region_info);
3df9d748 3143 type_register_static(&iommu_memory_region_info);
b4fefef9
PC		 3144}
3145
3146type_init(memory_register_types)
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