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[mirror_qemu.git] / memory.c
CommitLineData
093bc2cd
AK		 1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB		 12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
AK		 14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879
PB		 18#include "qemu-common.h"
19#include "cpu.h"
022c62cb
PB		 20#include "exec/memory.h"
21#include "exec/address-spaces.h"
409ddd01 22#include "qapi/visitor.h"
1de7afc9 23#include "qemu/bitops.h"
8c56c1a5 24#include "qemu/error-report.h"
2c9b15ca 25#include "qom/object.h"
0ab8ed18 26#include "trace-root.h"
093bc2cd 27
022c62cb 28#include "exec/memory-internal.h"
220c3ebd 29#include "exec/ram_addr.h"
8c56c1a5 30#include "sysemu/kvm.h"
e1c57ab8 31#include "sysemu/sysemu.h"
c9356746
FK		 32#include "hw/misc/mmio_interface.h"
33#include "hw/qdev-properties.h"
b08199c6 34#include "migration/vmstate.h"
67d95c15 35
d197063f
PB		 36//#define DEBUG_UNASSIGNED
37
22bde714
JK		 38static unsigned memory_region_transaction_depth;
39static bool memory_region_update_pending;
4dc56152 40static bool ioeventfd_update_pending;
7664e80c
AK		 41static bool global_dirty_log = false;
42
72e22d2f
AK		 43static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
44 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 45
0d673e36
AK		 46static QTAILQ_HEAD(, AddressSpace) address_spaces
47 = QTAILQ_HEAD_INITIALIZER(address_spaces);
48
967dc9b1
AK		 49static GHashTable *flat_views;
50
093bc2cd
AK		 51typedef struct AddrRange AddrRange;
52
8417cebf 53/*
c9cdaa3a 54 * Note that signed integers are needed for negative offsetting in aliases
8417cebf
AK		 55 * (large MemoryRegion::alias_offset).
56 */
093bc2cd 57struct AddrRange {
08dafab4
AK		 58 Int128 start;
59 Int128 size;
093bc2cd
AK		 60};
61
08dafab4 62static AddrRange addrrange_make(Int128 start, Int128 size)
093bc2cd
AK		 63{
64 return (AddrRange) { start, size };
65}
66
67static bool addrrange_equal(AddrRange r1, AddrRange r2)
68{
08dafab4 69 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
093bc2cd
AK		 70}
71
08dafab4 72static Int128 addrrange_end(AddrRange r)
093bc2cd 73{
08dafab4 74 return int128_add(r.start, r.size);
093bc2cd
AK		 75}
76
08dafab4 77static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 78{
08dafab4 79 int128_addto(&range.start, delta);
093bc2cd
AK		 80 return range;
81}
82
08dafab4
AK		 83static bool addrrange_contains(AddrRange range, Int128 addr)
84{
85 return int128_ge(addr, range.start)
86 && int128_lt(addr, addrrange_end(range));
87}
88
093bc2cd
AK		 89static bool addrrange_intersects(AddrRange r1, AddrRange r2)
90{
08dafab4
AK		 91 return addrrange_contains(r1, r2.start)
92 || addrrange_contains(r2, r1.start);
093bc2cd
AK		 93}
94
95static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
96{
08dafab4
AK		 97 Int128 start = int128_max(r1.start, r2.start);
98 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
99 return addrrange_make(start, int128_sub(end, start));
093bc2cd
AK		 100}
101
0e0d36b4
AK		 102enum ListenerDirection { Forward, Reverse };
103
7376e582 104#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
AK		 105 do { \
106 MemoryListener *_listener; \
107 \
108 switch (_direction) { \
109 case Forward: \
110 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
AK		 111 if (_listener->_callback) { \
112 _listener->_callback(_listener, ##_args); \
113 } \
0e0d36b4
AK		 114 } \
115 break; \
116 case Reverse: \
117 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
118 memory_listeners, link) { \
975aefe0
AK		 119 if (_listener->_callback) { \
120 _listener->_callback(_listener, ##_args); \
121 } \
0e0d36b4
AK		 122 } \
123 break; \
124 default: \
125 abort(); \
126 } \
127 } while (0)
128
9a54635d 129#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
7376e582
AK		 130 do { \
131 MemoryListener *_listener; \
9a54635d 132 struct memory_listeners_as *list = &(_as)->listeners; \
7376e582
AK		 133 \
134 switch (_direction) { \
135 case Forward: \
9a54635d
PB		 136 QTAILQ_FOREACH(_listener, list, link_as) { \
137 if (_listener->_callback) { \
7376e582
AK		 138 _listener->_callback(_listener, _section, ##_args); \
139 } \
140 } \
141 break; \
142 case Reverse: \
9a54635d
PB		 143 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
144 link_as) { \
145 if (_listener->_callback) { \
7376e582
AK		 146 _listener->_callback(_listener, _section, ##_args); \
147 } \
148 } \
149 break; \
150 default: \
151 abort(); \
152 } \
153 } while (0)
154
dfde4e6e 155/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 156#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44 157 do { \
16620684
AK		 158 MemoryRegionSection mrs = section_from_flat_range(fr, \
159 address_space_to_flatview(as)); \
9a54635d 160 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 161 } while(0)
0e0d36b4 162
093bc2cd
AK		 163struct CoalescedMemoryRange {
164 AddrRange addr;
165 QTAILQ_ENTRY(CoalescedMemoryRange) link;
166};
167
3e9d69e7
AK		 168struct MemoryRegionIoeventfd {
169 AddrRange addr;
170 bool match_data;
171 uint64_t data;
753d5e14 172 EventNotifier *e;
3e9d69e7
AK		 173};
174
175static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
176 MemoryRegionIoeventfd b)
177{
08dafab4 178 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 179 return true;
08dafab4 180 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 181 return false;
08dafab4 182 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 183 return true;
08dafab4 184 } else if (int128_gt(a.addr.size, b.addr.size)) {
3e9d69e7
AK		 185 return false;
186 } else if (a.match_data < b.match_data) {
187 return true;
188 } else if (a.match_data > b.match_data) {
189 return false;
190 } else if (a.match_data) {
191 if (a.data < b.data) {
192 return true;
193 } else if (a.data > b.data) {
194 return false;
195 }
196 }
753d5e14 197 if (a.e < b.e) {
3e9d69e7 198 return true;
753d5e14 199 } else if (a.e > b.e) {
3e9d69e7
AK		 200 return false;
201 }
202 return false;
203}
204
205static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
206 MemoryRegionIoeventfd b)
207{
208 return !memory_region_ioeventfd_before(a, b)
209 && !memory_region_ioeventfd_before(b, a);
210}
211
093bc2cd
AK		 212/* Range of memory in the global map. Addresses are absolute. */
213struct FlatRange {
214 MemoryRegion *mr;
a8170e5e 215 hwaddr offset_in_region;
093bc2cd 216 AddrRange addr;
5a583347 217 uint8_t dirty_log_mask;
b138e654 218 bool romd_mode;
fb1cd6f9 219 bool readonly;
093bc2cd
AK		 220};
221
093bc2cd
AK		 222#define FOR_EACH_FLAT_RANGE(var, view) \
223 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
224
9c1f8f44 225static inline MemoryRegionSection
16620684 226section_from_flat_range(FlatRange *fr, FlatView *fv)
9c1f8f44
PB		 227{
228 return (MemoryRegionSection) {
229 .mr = fr->mr,
16620684 230 .fv = fv,
9c1f8f44
PB		 231 .offset_within_region = fr->offset_in_region,
232 .size = fr->addr.size,
233 .offset_within_address_space = int128_get64(fr->addr.start),
234 .readonly = fr->readonly,
235 };
236}
237
093bc2cd
AK		 238static bool flatrange_equal(FlatRange *a, FlatRange *b)
239{
240 return a->mr == b->mr
241 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 242 && a->offset_in_region == b->offset_in_region
b138e654 243 && a->romd_mode == b->romd_mode
fb1cd6f9 244 && a->readonly == b->readonly;
093bc2cd
AK		 245}
246
89c177bb 247static FlatView *flatview_new(MemoryRegion *mr_root)
093bc2cd 248{
cc94cd6d
AK		 249 FlatView *view;
250
251 view = g_new0(FlatView, 1);
856d7245 252 view->ref = 1;
89c177bb
AK		 253 view->root = mr_root;
254 memory_region_ref(mr_root);
02d9651d 255 trace_flatview_new(view, mr_root);
cc94cd6d
AK		 256
257 return view;
093bc2cd
AK		 258}
259
260/* Insert a range into a given position. Caller is responsible for maintaining
261 * sorting order.
262 */
263static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
264{
265 if (view->nr == view->nr_allocated) {
266 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 267 view->ranges = g_realloc(view->ranges,
093bc2cd
AK		 268 view->nr_allocated * sizeof(*view->ranges));
269 }
270 memmove(view->ranges + pos + 1, view->ranges + pos,
271 (view->nr - pos) * sizeof(FlatRange));
272 view->ranges[pos] = *range;
dfde4e6e 273 memory_region_ref(range->mr);
093bc2cd
AK		 274 ++view->nr;
275}
276
277static void flatview_destroy(FlatView *view)
278{
dfde4e6e
PB		 279 int i;
280
02d9651d 281 trace_flatview_destroy(view, view->root);
66a6df1d
AK		 282 if (view->dispatch) {
283 address_space_dispatch_free(view->dispatch);
284 }
dfde4e6e
PB		 285 for (i = 0; i < view->nr; i++) {
286 memory_region_unref(view->ranges[i].mr);
287 }
7267c094 288 g_free(view->ranges);
89c177bb 289 memory_region_unref(view->root);
a9a0c06d 290 g_free(view);
093bc2cd
AK		 291}
292
447b0d0b 293static bool flatview_ref(FlatView *view)
856d7245 294{
447b0d0b 295 return atomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB		 296}
297
48564041 298void flatview_unref(FlatView *view)
856d7245
PB		 299{
300 if (atomic_fetch_dec(&view->ref) == 1) {
02d9651d 301 trace_flatview_destroy_rcu(view, view->root);
092aa2fc 302 assert(view->root);
66a6df1d 303 call_rcu(view, flatview_destroy, rcu);
856d7245
PB		 304 }
305}
306
3d8e6bf9
AK		 307static bool can_merge(FlatRange *r1, FlatRange *r2)
308{
08dafab4 309 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 310 && r1->mr == r2->mr
08dafab4
AK		 311 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
312 r1->addr.size),
313 int128_make64(r2->offset_in_region))
d0a9b5bc 314 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 315 && r1->romd_mode == r2->romd_mode
fb1cd6f9 316 && r1->readonly == r2->readonly;
3d8e6bf9
AK		 317}
318
8508e024 319/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK		 320static void flatview_simplify(FlatView *view)
321{
322 unsigned i, j;
323
324 i = 0;
325 while (i < view->nr) {
326 j = i + 1;
327 while (j < view->nr
328 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 329 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
AK		 330 ++j;
331 }
332 ++i;
333 memmove(&view->ranges[i], &view->ranges[j],
334 (view->nr - j) * sizeof(view->ranges[j]));
335 view->nr -= j - i;
336 }
337}
338
e7342aa3
PB		 339static bool memory_region_big_endian(MemoryRegion *mr)
340{
341#ifdef TARGET_WORDS_BIGENDIAN
342 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
343#else
344 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
345#endif
346}
347
e11ef3d1
PB		 348static bool memory_region_wrong_endianness(MemoryRegion *mr)
349{
350#ifdef TARGET_WORDS_BIGENDIAN
351 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
352#else
353 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
354#endif
355}
356
357static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
358{
359 if (memory_region_wrong_endianness(mr)) {
360 switch (size) {
361 case 1:
362 break;
363 case 2:
364 *data = bswap16(*data);
365 break;
366 case 4:
367 *data = bswap32(*data);
368 break;
369 case 8:
370 *data = bswap64(*data);
371 break;
372 default:
373 abort();
374 }
375 }
376}
377
4779dc1d
HB		 378static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
379{
380 MemoryRegion *root;
381 hwaddr abs_addr = offset;
382
383 abs_addr += mr->addr;
384 for (root = mr; root->container; ) {
385 root = root->container;
386 abs_addr += root->addr;
387 }
388
389 return abs_addr;
390}
391
5a68be94
HB		 392static int get_cpu_index(void)
393{
394 if (current_cpu) {
395 return current_cpu->cpu_index;
396 }
397 return -1;
398}
399
cc05c43a
PM		 400static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
401 hwaddr addr,
402 uint64_t *value,
403 unsigned size,
404 unsigned shift,
405 uint64_t mask,
406 MemTxAttrs attrs)
407{
408 uint64_t tmp;
409
410 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
23d92d68 411 if (mr->subpage) {
5a68be94 412 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 413 } else if (mr == &io_mem_notdirty) {
414 /* Accesses to code which has previously been translated into a TB show
415 * up in the MMIO path, as accesses to the io_mem_notdirty
416 * MemoryRegion. */
417 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 418 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
419 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 420 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 421 }
cc05c43a
PM		 422 *value |= (tmp & mask) << shift;
423 return MEMTX_OK;
424}
425
426static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB		 427 hwaddr addr,
428 uint64_t *value,
429 unsigned size,
430 unsigned shift,
cc05c43a
PM		 431 uint64_t mask,
432 MemTxAttrs attrs)
ce5d2f33 433{
ce5d2f33
PB		 434 uint64_t tmp;
435
cc05c43a 436 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 437 if (mr->subpage) {
5a68be94 438 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 439 } else if (mr == &io_mem_notdirty) {
440 /* Accesses to code which has previously been translated into a TB show
441 * up in the MMIO path, as accesses to the io_mem_notdirty
442 * MemoryRegion. */
443 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 444 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
445 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 446 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 447 }
ce5d2f33 448 *value |= (tmp & mask) << shift;
cc05c43a 449 return MEMTX_OK;
ce5d2f33
PB		 450}
451
cc05c43a
PM		 452static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
453 hwaddr addr,
454 uint64_t *value,
455 unsigned size,
456 unsigned shift,
457 uint64_t mask,
458 MemTxAttrs attrs)
164a4dcd 459{
cc05c43a
PM		 460 uint64_t tmp = 0;
461 MemTxResult r;
164a4dcd 462
cc05c43a 463 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 464 if (mr->subpage) {
5a68be94 465 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 466 } else if (mr == &io_mem_notdirty) {
467 /* Accesses to code which has previously been translated into a TB show
468 * up in the MMIO path, as accesses to the io_mem_notdirty
469 * MemoryRegion. */
470 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 471 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
472 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 473 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 474 }
164a4dcd 475 *value |= (tmp & mask) << shift;
cc05c43a 476 return r;
164a4dcd
AK		 477}
478
cc05c43a
PM		 479static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
480 hwaddr addr,
481 uint64_t *value,
482 unsigned size,
483 unsigned shift,
484 uint64_t mask,
485 MemTxAttrs attrs)
ce5d2f33 486{
ce5d2f33
PB		 487 uint64_t tmp;
488
489 tmp = (*value >> shift) & mask;
23d92d68 490 if (mr->subpage) {
5a68be94 491 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 492 } else if (mr == &io_mem_notdirty) {
493 /* Accesses to code which has previously been translated into a TB show
494 * up in the MMIO path, as accesses to the io_mem_notdirty
495 * MemoryRegion. */
496 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 497 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
498 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 499 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 500 }
ce5d2f33 501 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
cc05c43a 502 return MEMTX_OK;
ce5d2f33
PB		 503}
504
cc05c43a
PM		 505static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
506 hwaddr addr,
507 uint64_t *value,
508 unsigned size,
509 unsigned shift,
510 uint64_t mask,
511 MemTxAttrs attrs)
164a4dcd 512{
164a4dcd
AK		 513 uint64_t tmp;
514
515 tmp = (*value >> shift) & mask;
23d92d68 516 if (mr->subpage) {
5a68be94 517 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 518 } else if (mr == &io_mem_notdirty) {
519 /* Accesses to code which has previously been translated into a TB show
520 * up in the MMIO path, as accesses to the io_mem_notdirty
521 * MemoryRegion. */
522 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 523 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
524 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 525 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 526 }
164a4dcd 527 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 528 return MEMTX_OK;
164a4dcd
AK		 529}
530
cc05c43a
PM		 531static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
532 hwaddr addr,
533 uint64_t *value,
534 unsigned size,
535 unsigned shift,
536 uint64_t mask,
537 MemTxAttrs attrs)
538{
539 uint64_t tmp;
540
cc05c43a 541 tmp = (*value >> shift) & mask;
23d92d68 542 if (mr->subpage) {
5a68be94 543 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 544 } else if (mr == &io_mem_notdirty) {
545 /* Accesses to code which has previously been translated into a TB show
546 * up in the MMIO path, as accesses to the io_mem_notdirty
547 * MemoryRegion. */
548 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 549 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
550 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 551 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 552 }
cc05c43a
PM		 553 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
554}
555
556static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK		 557 uint64_t *value,
558 unsigned size,
559 unsigned access_size_min,
560 unsigned access_size_max,
05e015f7
KF		 561 MemTxResult (*access_fn)
562 (MemoryRegion *mr,
563 hwaddr addr,
564 uint64_t *value,
565 unsigned size,
566 unsigned shift,
567 uint64_t mask,
568 MemTxAttrs attrs),
cc05c43a
PM		 569 MemoryRegion *mr,
570 MemTxAttrs attrs)
164a4dcd
AK		 571{
572 uint64_t access_mask;
573 unsigned access_size;
574 unsigned i;
cc05c43a 575 MemTxResult r = MEMTX_OK;
164a4dcd
AK		 576
577 if (!access_size_min) {
578 access_size_min = 1;
579 }
580 if (!access_size_max) {
581 access_size_max = 4;
582 }
ce5d2f33
PB		 583
584 /* FIXME: support unaligned access? */
164a4dcd
AK		 585 access_size = MAX(MIN(size, access_size_max), access_size_min);
586 access_mask = -1ULL >> (64 - access_size * 8);
e7342aa3
PB		 587 if (memory_region_big_endian(mr)) {
588 for (i = 0; i < size; i += access_size) {
05e015f7 589 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 590 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB		 591 }
592 } else {
593 for (i = 0; i < size; i += access_size) {
05e015f7 594 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 595 access_mask, attrs);
e7342aa3 596 }
164a4dcd 597 }
cc05c43a 598 return r;
164a4dcd
AK		 599}
600
e2177955
AK		 601static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
602{
0d673e36
AK		 603 AddressSpace *as;
604
feca4ac1
PB		 605 while (mr->container) {
606 mr = mr->container;
e2177955 607 }
0d673e36
AK		 608 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
609 if (mr == as->root) {
610 return as;
611 }
e2177955 612 }
eed2bacf 613 return NULL;
e2177955
AK		 614}
615
093bc2cd
AK		 616/* Render a memory region into the global view. Ranges in @view obscure
617 * ranges in @mr.
618 */
619static void render_memory_region(FlatView *view,
620 MemoryRegion *mr,
08dafab4 621 Int128 base,
fb1cd6f9
AK		 622 AddrRange clip,
623 bool readonly)
093bc2cd
AK		 624{
625 MemoryRegion *subregion;
626 unsigned i;
a8170e5e 627 hwaddr offset_in_region;
08dafab4
AK		 628 Int128 remain;
629 Int128 now;
093bc2cd
AK		 630 FlatRange fr;
631 AddrRange tmp;
632
6bba19ba
AK		 633 if (!mr->enabled) {
634 return;
635 }
636
08dafab4 637 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 638 readonly |= mr->readonly;
093bc2cd
AK		 639
640 tmp = addrrange_make(base, mr->size);
641
642 if (!addrrange_intersects(tmp, clip)) {
643 return;
644 }
645
646 clip = addrrange_intersection(tmp, clip);
647
648 if (mr->alias) {
08dafab4
AK		 649 int128_subfrom(&base, int128_make64(mr->alias->addr));
650 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 651 render_memory_region(view, mr->alias, base, clip, readonly);
093bc2cd
AK		 652 return;
653 }
654
655 /* Render subregions in priority order. */
656 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 657 render_memory_region(view, subregion, base, clip, readonly);
093bc2cd
AK		 658 }
659
14a3c10a 660 if (!mr->terminates) {
093bc2cd
AK		 661 return;
662 }
663
08dafab4 664 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK		 665 base = clip.start;
666 remain = clip.size;
667
2eb74e1a 668 fr.mr = mr;
6f6a5ef3 669 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 670 fr.romd_mode = mr->romd_mode;
2eb74e1a
PC		 671 fr.readonly = readonly;
672
093bc2cd 673 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK		 674 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
675 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK		 676 continue;
677 }
08dafab4
AK		 678 if (int128_lt(base, view->ranges[i].addr.start)) {
679 now = int128_min(remain,
680 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK		 681 fr.offset_in_region = offset_in_region;
682 fr.addr = addrrange_make(base, now);
683 flatview_insert(view, i, &fr);
684 ++i;
08dafab4
AK		 685 int128_addto(&base, now);
686 offset_in_region += int128_get64(now);
687 int128_subfrom(&remain, now);
093bc2cd 688 }
d26a8cae
AK		 689 now = int128_sub(int128_min(int128_add(base, remain),
690 addrrange_end(view->ranges[i].addr)),
691 base);
692 int128_addto(&base, now);
693 offset_in_region += int128_get64(now);
694 int128_subfrom(&remain, now);
093bc2cd 695 }
08dafab4 696 if (int128_nz(remain)) {
093bc2cd
AK		 697 fr.offset_in_region = offset_in_region;
698 fr.addr = addrrange_make(base, remain);
699 flatview_insert(view, i, &fr);
700 }
701}
702
89c177bb
AK		 703static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
704{
e673ba9a
PB		 705 while (mr->enabled) {
706 if (mr->alias) {
707 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
708 /* The alias is included in its entirety. Use it as
709 * the "real" root, so that we can share more FlatViews.
710 */
711 mr = mr->alias;
712 continue;
713 }
714 } else if (!mr->terminates) {
715 unsigned int found = 0;
716 MemoryRegion *child, *next = NULL;
717 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
718 if (child->enabled) {
719 if (++found > 1) {
720 next = NULL;
721 break;
722 }
723 if (!child->addr && int128_ge(mr->size, child->size)) {
724 /* A child is included in its entirety. If it's the only
725 * enabled one, use it in the hope of finding an alias down the
726 * way. This will also let us share FlatViews.
727 */
728 next = child;
729 }
730 }
731 }
092aa2fc
AK		 732 if (found == 0) {
733 return NULL;
734 }
e673ba9a
PB		 735 if (next) {
736 mr = next;
737 continue;
738 }
739 }
740
092aa2fc 741 return mr;
89c177bb
AK		 742 }
743
092aa2fc 744 return NULL;
89c177bb
AK		 745}
746
093bc2cd 747/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 748static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 749{
9bf561e3 750 int i;
a9a0c06d 751 FlatView *view;
093bc2cd 752
89c177bb 753 view = flatview_new(mr);
093bc2cd 754
83f3c251 755 if (mr) {
a9a0c06d 756 render_memory_region(view, mr, int128_zero(),
83f3c251
AK		 757 addrrange_make(int128_zero(), int128_2_64()), false);
758 }
a9a0c06d 759 flatview_simplify(view);
093bc2cd 760
9bf561e3
AK		 761 view->dispatch = address_space_dispatch_new(view);
762 for (i = 0; i < view->nr; i++) {
763 MemoryRegionSection mrs =
764 section_from_flat_range(&view->ranges[i], view);
765 flatview_add_to_dispatch(view, &mrs);
766 }
767 address_space_dispatch_compact(view->dispatch);
967dc9b1 768 g_hash_table_replace(flat_views, mr, view);
9bf561e3 769
093bc2cd
AK		 770 return view;
771}
772
3e9d69e7
AK		 773static void address_space_add_del_ioeventfds(AddressSpace *as,
774 MemoryRegionIoeventfd *fds_new,
775 unsigned fds_new_nb,
776 MemoryRegionIoeventfd *fds_old,
777 unsigned fds_old_nb)
778{
779 unsigned iold, inew;
80a1ea37
AK		 780 MemoryRegionIoeventfd *fd;
781 MemoryRegionSection section;
3e9d69e7
AK		 782
783 /* Generate a symmetric difference of the old and new fd sets, adding
784 * and deleting as necessary.
785 */
786
787 iold = inew = 0;
788 while (iold < fds_old_nb || inew < fds_new_nb) {
789 if (iold < fds_old_nb
790 && (inew == fds_new_nb
791 || memory_region_ioeventfd_before(fds_old[iold],
792 fds_new[inew]))) {
80a1ea37
AK		 793 fd = &fds_old[iold];
794 section = (MemoryRegionSection) {
16620684 795 .fv = address_space_to_flatview(as),
80a1ea37 796 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 797 .size = fd->addr.size,
80a1ea37 798 };
9a54635d 799 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 800 fd->match_data, fd->data, fd->e);
3e9d69e7
AK		 801 ++iold;
802 } else if (inew < fds_new_nb
803 && (iold == fds_old_nb
804 || memory_region_ioeventfd_before(fds_new[inew],
805 fds_old[iold]))) {
80a1ea37
AK		 806 fd = &fds_new[inew];
807 section = (MemoryRegionSection) {
16620684 808 .fv = address_space_to_flatview(as),
80a1ea37 809 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 810 .size = fd->addr.size,
80a1ea37 811 };
9a54635d 812 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 813 fd->match_data, fd->data, fd->e);
3e9d69e7
AK		 814 ++inew;
815 } else {
816 ++iold;
817 ++inew;
818 }
819 }
820}
821
48564041 822FlatView *address_space_get_flatview(AddressSpace *as)
856d7245
PB		 823{
824 FlatView *view;
825
374f2981 826 rcu_read_lock();
447b0d0b 827 do {
16620684 828 view = address_space_to_flatview(as);
447b0d0b
PB		 829 /* If somebody has replaced as->current_map concurrently,
830 * flatview_ref returns false.
831 */
832 } while (!flatview_ref(view));
374f2981 833 rcu_read_unlock();
856d7245
PB		 834 return view;
835}
836
3e9d69e7
AK		 837static void address_space_update_ioeventfds(AddressSpace *as)
838{
99e86347 839 FlatView *view;
3e9d69e7
AK		 840 FlatRange *fr;
841 unsigned ioeventfd_nb = 0;
842 MemoryRegionIoeventfd *ioeventfds = NULL;
843 AddrRange tmp;
844 unsigned i;
845
856d7245 846 view = address_space_get_flatview(as);
99e86347 847 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK		 848 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
849 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK		 850 int128_sub(fr->addr.start,
851 int128_make64(fr->offset_in_region)));
3e9d69e7
AK		 852 if (addrrange_intersects(fr->addr, tmp)) {
853 ++ioeventfd_nb;
7267c094 854 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK		 855 ioeventfd_nb * sizeof(*ioeventfds));
856 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
857 ioeventfds[ioeventfd_nb-1].addr = tmp;
858 }
859 }
860 }
861
862 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
863 as->ioeventfds, as->ioeventfd_nb);
864
7267c094 865 g_free(as->ioeventfds);
3e9d69e7
AK		 866 as->ioeventfds = ioeventfds;
867 as->ioeventfd_nb = ioeventfd_nb;
856d7245 868 flatview_unref(view);
3e9d69e7
AK		 869}
870
b8af1afb 871static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB		 872 const FlatView *old_view,
873 const FlatView *new_view,
b8af1afb 874 bool adding)
093bc2cd 875{
093bc2cd
AK		 876 unsigned iold, inew;
877 FlatRange *frold, *frnew;
093bc2cd
AK		 878
879 /* Generate a symmetric difference of the old and new memory maps.
880 * Kill ranges in the old map, and instantiate ranges in the new map.
881 */
882 iold = inew = 0;
a9a0c06d
PB		 883 while (iold < old_view->nr || inew < new_view->nr) {
884 if (iold < old_view->nr) {
885 frold = &old_view->ranges[iold];
093bc2cd
AK		 886 } else {
887 frold = NULL;
888 }
a9a0c06d
PB		 889 if (inew < new_view->nr) {
890 frnew = &new_view->ranges[inew];
093bc2cd
AK		 891 } else {
892 frnew = NULL;
893 }
894
895 if (frold
896 && (!frnew
08dafab4
AK		 897 || int128_lt(frold->addr.start, frnew->addr.start)
898 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 899 && !flatrange_equal(frold, frnew)))) {
41a6e477 900 /* In old but not in new, or in both but attributes changed. */
093bc2cd 901
b8af1afb 902 if (!adding) {
72e22d2f 903 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK		 904 }
905
093bc2cd
AK		 906 ++iold;
907 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 908 /* In both and unchanged (except logging may have changed) */
093bc2cd 909
b8af1afb 910 if (adding) {
50c1e149 911 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB		 912 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
913 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
914 frold->dirty_log_mask,
915 frnew->dirty_log_mask);
916 }
917 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
918 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
919 frold->dirty_log_mask,
920 frnew->dirty_log_mask);
b8af1afb 921 }
5a583347
AK		 922 }
923
093bc2cd
AK		 924 ++iold;
925 ++inew;
093bc2cd
AK		 926 } else {
927 /* In new */
928
b8af1afb 929 if (adding) {
72e22d2f 930 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK		 931 }
932
093bc2cd
AK		 933 ++inew;
934 }
935 }
b8af1afb
AK		 936}
937
967dc9b1
AK		 938static void flatviews_init(void)
939{
092aa2fc
AK		 940 static FlatView *empty_view;
941
967dc9b1
AK		 942 if (flat_views) {
943 return;
944 }
945
946 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
947 (GDestroyNotify) flatview_unref);
092aa2fc
AK		 948 if (!empty_view) {
949 empty_view = generate_memory_topology(NULL);
950 /* We keep it alive forever in the global variable. */
951 flatview_ref(empty_view);
952 } else {
953 g_hash_table_replace(flat_views, NULL, empty_view);
954 flatview_ref(empty_view);
955 }
967dc9b1
AK		 956}
957
958static void flatviews_reset(void)
959{
960 AddressSpace *as;
961
962 if (flat_views) {
963 g_hash_table_unref(flat_views);
964 flat_views = NULL;
965 }
966 flatviews_init();
967
968 /* Render unique FVs */
969 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
970 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
971
972 if (g_hash_table_lookup(flat_views, physmr)) {
973 continue;
974 }
975
976 generate_memory_topology(physmr);
977 }
978}
979
980static void address_space_set_flatview(AddressSpace *as)
b8af1afb 981{
67ace39b 982 FlatView *old_view = address_space_to_flatview(as);
967dc9b1
AK		 983 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
984 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
985
986 assert(new_view);
987
67ace39b
AK		 988 if (old_view == new_view) {
989 return;
990 }
991
992 if (old_view) {
993 flatview_ref(old_view);
994 }
995
967dc9b1 996 flatview_ref(new_view);
9a62e24f
AK		 997
998 if (!QTAILQ_EMPTY(&as->listeners)) {
67ace39b
AK		 999 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1000
1001 if (!old_view2) {
1002 old_view2 = &tmpview;
1003 }
1004 address_space_update_topology_pass(as, old_view2, new_view, false);
1005 address_space_update_topology_pass(as, old_view2, new_view, true);
9a62e24f 1006 }
b8af1afb 1007
374f2981
PB		 1008 /* Writes are protected by the BQL. */
1009 atomic_rcu_set(&as->current_map, new_view);
67ace39b
AK		 1010 if (old_view) {
1011 flatview_unref(old_view);
1012 }
856d7245
PB		 1013
1014 /* Note that all the old MemoryRegions are still alive up to this
1015 * point. This relieves most MemoryListeners from the need to
1016 * ref/unref the MemoryRegions they get---unless they use them
1017 * outside the iothread mutex, in which case precise reference
1018 * counting is necessary.
1019 */
67ace39b
AK		 1020 if (old_view) {
1021 flatview_unref(old_view);
1022 }
093bc2cd
AK		 1023}
1024
202fc01b
AK		 1025static void address_space_update_topology(AddressSpace *as)
1026{
1027 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1028
1029 flatviews_init();
1030 if (!g_hash_table_lookup(flat_views, physmr)) {
1031 generate_memory_topology(physmr);
1032 }
1033 address_space_set_flatview(as);
1034}
1035
4ef4db86
AK		 1036void memory_region_transaction_begin(void)
1037{
bb880ded 1038 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK		 1039 ++memory_region_transaction_depth;
1040}
1041
1042void memory_region_transaction_commit(void)
1043{
0d673e36
AK		 1044 AddressSpace *as;
1045
4ef4db86 1046 assert(memory_region_transaction_depth);
8d04fb55
JK		 1047 assert(qemu_mutex_iothread_locked());
1048
4ef4db86 1049 --memory_region_transaction_depth;
4dc56152
GA		 1050 if (!memory_region_transaction_depth) {
1051 if (memory_region_update_pending) {
967dc9b1
AK		 1052 flatviews_reset();
1053
4dc56152 1054 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 1055
4dc56152 1056 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
967dc9b1 1057 address_space_set_flatview(as);
02218487 1058 address_space_update_ioeventfds(as);
4dc56152 1059 }
ade9c1aa 1060 memory_region_update_pending = false;
0b152095 1061 ioeventfd_update_pending = false;
4dc56152
GA		 1062 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1063 } else if (ioeventfd_update_pending) {
1064 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1065 address_space_update_ioeventfds(as);
1066 }
ade9c1aa 1067 ioeventfd_update_pending = false;
4dc56152 1068 }
4dc56152 1069 }
4ef4db86
AK		 1070}
1071
545e92e0
AK		 1072static void memory_region_destructor_none(MemoryRegion *mr)
1073{
1074}
1075
1076static void memory_region_destructor_ram(MemoryRegion *mr)
1077{
f1060c55 1078 qemu_ram_free(mr->ram_block);
545e92e0
AK		 1079}
1080
b4fefef9
PC		 1081static bool memory_region_need_escape(char c)
1082{
1083 return c == '/' || c == '[' || c == '\\' || c == ']';
1084}
1085
1086static char *memory_region_escape_name(const char *name)
1087{
1088 const char *p;
1089 char *escaped, *q;
1090 uint8_t c;
1091 size_t bytes = 0;
1092
1093 for (p = name; *p; p++) {
1094 bytes += memory_region_need_escape(*p) ? 4 : 1;
1095 }
1096 if (bytes == p - name) {
1097 return g_memdup(name, bytes + 1);
1098 }
1099
1100 escaped = g_malloc(bytes + 1);
1101 for (p = name, q = escaped; *p; p++) {
1102 c = *p;
1103 if (unlikely(memory_region_need_escape(c))) {
1104 *q++ = '\\';
1105 *q++ = 'x';
1106 *q++ = "0123456789abcdef"[c >> 4];
1107 c = "0123456789abcdef"[c & 15];
1108 }
1109 *q++ = c;
1110 }
1111 *q = 0;
1112 return escaped;
1113}
1114
3df9d748
AK		 1115static void memory_region_do_init(MemoryRegion *mr,
1116 Object *owner,
1117 const char *name,
1118 uint64_t size)
093bc2cd 1119{
08dafab4
AK		 1120 mr->size = int128_make64(size);
1121 if (size == UINT64_MAX) {
1122 mr->size = int128_2_64();
1123 }
302fa283 1124 mr->name = g_strdup(name);
612263cf 1125 mr->owner = owner;
58eaa217 1126 mr->ram_block = NULL;
b4fefef9
PC		 1127
1128 if (name) {
843ef73a
PC		 1129 char *escaped_name = memory_region_escape_name(name);
1130 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB		 1131
1132 if (!owner) {
1133 owner = container_get(qdev_get_machine(), "/unattached");
1134 }
1135
843ef73a 1136 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1137 object_unref(OBJECT(mr));
843ef73a
PC		 1138 g_free(name_array);
1139 g_free(escaped_name);
b4fefef9
PC		 1140 }
1141}
1142
3df9d748
AK		 1143void memory_region_init(MemoryRegion *mr,
1144 Object *owner,
1145 const char *name,
1146 uint64_t size)
1147{
1148 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1149 memory_region_do_init(mr, owner, name, size);
1150}
1151
d7bce999
EB		 1152static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1153 void *opaque, Error **errp)
409ddd01
PC		 1154{
1155 MemoryRegion *mr = MEMORY_REGION(obj);
1156 uint64_t value = mr->addr;
1157
51e72bc1 1158 visit_type_uint64(v, name, &value, errp);
409ddd01
PC		 1159}
1160
d7bce999
EB		 1161static void memory_region_get_container(Object *obj, Visitor *v,
1162 const char *name, void *opaque,
1163 Error **errp)
409ddd01
PC		 1164{
1165 MemoryRegion *mr = MEMORY_REGION(obj);
1166 gchar *path = (gchar *)"";
1167
1168 if (mr->container) {
1169 path = object_get_canonical_path(OBJECT(mr->container));
1170 }
51e72bc1 1171 visit_type_str(v, name, &path, errp);
409ddd01
PC		 1172 if (mr->container) {
1173 g_free(path);
1174 }
1175}
1176
1177static Object *memory_region_resolve_container(Object *obj, void *opaque,
1178 const char *part)
1179{
1180 MemoryRegion *mr = MEMORY_REGION(obj);
1181
1182 return OBJECT(mr->container);
1183}
1184
d7bce999
EB		 1185static void memory_region_get_priority(Object *obj, Visitor *v,
1186 const char *name, void *opaque,
1187 Error **errp)
d33382da
PC		 1188{
1189 MemoryRegion *mr = MEMORY_REGION(obj);
1190 int32_t value = mr->priority;
1191
51e72bc1 1192 visit_type_int32(v, name, &value, errp);
d33382da
PC		 1193}
1194
d7bce999
EB		 1195static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1196 void *opaque, Error **errp)
52aef7bb
PC		 1197{
1198 MemoryRegion *mr = MEMORY_REGION(obj);
1199 uint64_t value = memory_region_size(mr);
1200
51e72bc1 1201 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC		 1202}
1203
b4fefef9
PC		 1204static void memory_region_initfn(Object *obj)
1205{
1206 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1207 ObjectProperty *op;
b4fefef9
PC		 1208
1209 mr->ops = &unassigned_mem_ops;
6bba19ba 1210 mr->enabled = true;
5f9a5ea1 1211 mr->romd_mode = true;
196ea131 1212 mr->global_locking = true;
545e92e0 1213 mr->destructor = memory_region_destructor_none;
093bc2cd 1214 QTAILQ_INIT(&mr->subregions);
093bc2cd 1215 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC		 1216
1217 op = object_property_add(OBJECT(mr), "container",
1218 "link<" TYPE_MEMORY_REGION ">",
1219 memory_region_get_container,
1220 NULL, /* memory_region_set_container */
1221 NULL, NULL, &error_abort);
1222 op->resolve = memory_region_resolve_container;
1223
1224 object_property_add(OBJECT(mr), "addr", "uint64",
1225 memory_region_get_addr,
1226 NULL, /* memory_region_set_addr */
1227 NULL, NULL, &error_abort);
d33382da
PC		 1228 object_property_add(OBJECT(mr), "priority", "uint32",
1229 memory_region_get_priority,
1230 NULL, /* memory_region_set_priority */
1231 NULL, NULL, &error_abort);
52aef7bb
PC		 1232 object_property_add(OBJECT(mr), "size", "uint64",
1233 memory_region_get_size,
1234 NULL, /* memory_region_set_size, */
1235 NULL, NULL, &error_abort);
093bc2cd
AK		 1236}
1237
3df9d748
AK		 1238static void iommu_memory_region_initfn(Object *obj)
1239{
1240 MemoryRegion *mr = MEMORY_REGION(obj);
1241
1242 mr->is_iommu = true;
1243}
1244
b018ddf6
PB		 1245static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1246 unsigned size)
1247{
1248#ifdef DEBUG_UNASSIGNED
1249 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1250#endif
4917cf44
AF		 1251 if (current_cpu != NULL) {
1252 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
c658b94f 1253 }
68a7439a 1254 return 0;
b018ddf6
PB		 1255}
1256
1257static void unassigned_mem_write(void *opaque, hwaddr addr,
1258 uint64_t val, unsigned size)
1259{
1260#ifdef DEBUG_UNASSIGNED
1261 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1262#endif
4917cf44
AF		 1263 if (current_cpu != NULL) {
1264 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1265 }
b018ddf6
PB		 1266}
1267
d197063f
PB		 1268static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1269 unsigned size, bool is_write)
1270{
1271 return false;
1272}
1273
1274const MemoryRegionOps unassigned_mem_ops = {
1275 .valid.accepts = unassigned_mem_accepts,
1276 .endianness = DEVICE_NATIVE_ENDIAN,
1277};
1278
4a2e242b
AW		 1279static uint64_t memory_region_ram_device_read(void *opaque,
1280 hwaddr addr, unsigned size)
1281{
1282 MemoryRegion *mr = opaque;
1283 uint64_t data = (uint64_t)~0;
1284
1285 switch (size) {
1286 case 1:
1287 data = *(uint8_t *)(mr->ram_block->host + addr);
1288 break;
1289 case 2:
1290 data = *(uint16_t *)(mr->ram_block->host + addr);
1291 break;
1292 case 4:
1293 data = *(uint32_t *)(mr->ram_block->host + addr);
1294 break;
1295 case 8:
1296 data = *(uint64_t *)(mr->ram_block->host + addr);
1297 break;
1298 }
1299
1300 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1301
1302 return data;
1303}
1304
1305static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1306 uint64_t data, unsigned size)
1307{
1308 MemoryRegion *mr = opaque;
1309
1310 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1311
1312 switch (size) {
1313 case 1:
1314 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1315 break;
1316 case 2:
1317 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1318 break;
1319 case 4:
1320 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1321 break;
1322 case 8:
1323 *(uint64_t *)(mr->ram_block->host + addr) = data;
1324 break;
1325 }
1326}
1327
1328static const MemoryRegionOps ram_device_mem_ops = {
1329 .read = memory_region_ram_device_read,
1330 .write = memory_region_ram_device_write,
c99a29e7 1331 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW		 1332 .valid = {
1333 .min_access_size = 1,
1334 .max_access_size = 8,
1335 .unaligned = true,
1336 },
1337 .impl = {
1338 .min_access_size = 1,
1339 .max_access_size = 8,
1340 .unaligned = true,
1341 },
1342};
1343
d2702032
PB		 1344bool memory_region_access_valid(MemoryRegion *mr,
1345 hwaddr addr,
1346 unsigned size,
1347 bool is_write)
093bc2cd 1348{
a014ed07
PB		 1349 int access_size_min, access_size_max;
1350 int access_size, i;
897fa7cf 1351
093bc2cd
AK		 1352 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1353 return false;
1354 }
1355
a014ed07 1356 if (!mr->ops->valid.accepts) {
093bc2cd
AK		 1357 return true;
1358 }
1359
a014ed07
PB		 1360 access_size_min = mr->ops->valid.min_access_size;
1361 if (!mr->ops->valid.min_access_size) {
1362 access_size_min = 1;
1363 }
1364
1365 access_size_max = mr->ops->valid.max_access_size;
1366 if (!mr->ops->valid.max_access_size) {
1367 access_size_max = 4;
1368 }
1369
1370 access_size = MAX(MIN(size, access_size_max), access_size_min);
1371 for (i = 0; i < size; i += access_size) {
1372 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1373 is_write)) {
1374 return false;
1375 }
093bc2cd 1376 }
a014ed07 1377
093bc2cd
AK		 1378 return true;
1379}
1380
cc05c43a
PM		 1381static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1382 hwaddr addr,
1383 uint64_t *pval,
1384 unsigned size,
1385 MemTxAttrs attrs)
093bc2cd 1386{
cc05c43a 1387 *pval = 0;
093bc2cd 1388
ce5d2f33 1389 if (mr->ops->read) {
cc05c43a
PM		 1390 return access_with_adjusted_size(addr, pval, size,
1391 mr->ops->impl.min_access_size,
1392 mr->ops->impl.max_access_size,
1393 memory_region_read_accessor,
1394 mr, attrs);
1395 } else if (mr->ops->read_with_attrs) {
1396 return access_with_adjusted_size(addr, pval, size,
1397 mr->ops->impl.min_access_size,
1398 mr->ops->impl.max_access_size,
1399 memory_region_read_with_attrs_accessor,
1400 mr, attrs);
ce5d2f33 1401 } else {
cc05c43a
PM		 1402 return access_with_adjusted_size(addr, pval, size, 1, 4,
1403 memory_region_oldmmio_read_accessor,
1404 mr, attrs);
74901c3b 1405 }
093bc2cd
AK		 1406}
1407
3b643495
PM		 1408MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1409 hwaddr addr,
1410 uint64_t *pval,
1411 unsigned size,
1412 MemTxAttrs attrs)
a621f38d 1413{
cc05c43a
PM		 1414 MemTxResult r;
1415
791af8c8
PB		 1416 if (!memory_region_access_valid(mr, addr, size, false)) {
1417 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1418 return MEMTX_DECODE_ERROR;
791af8c8 1419 }
a621f38d 1420
cc05c43a 1421 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1422 adjust_endianness(mr, pval, size);
cc05c43a 1423 return r;
a621f38d 1424}
093bc2cd 1425
8c56c1a5
PF		 1426/* Return true if an eventfd was signalled */
1427static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1428 hwaddr addr,
1429 uint64_t data,
1430 unsigned size,
1431 MemTxAttrs attrs)
1432{
1433 MemoryRegionIoeventfd ioeventfd = {
1434 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1435 .data = data,
1436 };
1437 unsigned i;
1438
1439 for (i = 0; i < mr->ioeventfd_nb; i++) {
1440 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1441 ioeventfd.e = mr->ioeventfds[i].e;
1442
1443 if (memory_region_ioeventfd_equal(ioeventfd, mr->ioeventfds[i])) {
1444 event_notifier_set(ioeventfd.e);
1445 return true;
1446 }
1447 }
1448
1449 return false;
1450}
1451
3b643495
PM		 1452MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1453 hwaddr addr,
1454 uint64_t data,
1455 unsigned size,
1456 MemTxAttrs attrs)
a621f38d 1457{
897fa7cf 1458 if (!memory_region_access_valid(mr, addr, size, true)) {
b018ddf6 1459 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1460 return MEMTX_DECODE_ERROR;
093bc2cd
AK		 1461 }
1462
a621f38d
AK		 1463 adjust_endianness(mr, &data, size);
1464
8c56c1a5
PF		 1465 if ((!kvm_eventfds_enabled()) &&
1466 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1467 return MEMTX_OK;
1468 }
1469
ce5d2f33 1470 if (mr->ops->write) {
cc05c43a
PM		 1471 return access_with_adjusted_size(addr, &data, size,
1472 mr->ops->impl.min_access_size,
1473 mr->ops->impl.max_access_size,
1474 memory_region_write_accessor, mr,
1475 attrs);
1476 } else if (mr->ops->write_with_attrs) {
1477 return
1478 access_with_adjusted_size(addr, &data, size,
1479 mr->ops->impl.min_access_size,
1480 mr->ops->impl.max_access_size,
1481 memory_region_write_with_attrs_accessor,
1482 mr, attrs);
ce5d2f33 1483 } else {
cc05c43a
PM		 1484 return access_with_adjusted_size(addr, &data, size, 1, 4,
1485 memory_region_oldmmio_write_accessor,
1486 mr, attrs);
74901c3b 1487 }
093bc2cd
AK		 1488}
1489
093bc2cd 1490void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1491 Object *owner,
093bc2cd
AK		 1492 const MemoryRegionOps *ops,
1493 void *opaque,
1494 const char *name,
1495 uint64_t size)
1496{
2c9b15ca 1497 memory_region_init(mr, owner, name, size);
6d6d2abf 1498 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1499 mr->opaque = opaque;
14a3c10a 1500 mr->terminates = true;
093bc2cd
AK		 1501}
1502
1cfe48c1
PM		 1503void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1504 Object *owner,
1505 const char *name,
1506 uint64_t size,
1507 Error **errp)
06329cce
MA		 1508{
1509 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1510}
1511
1512void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1513 Object *owner,
1514 const char *name,
1515 uint64_t size,
1516 bool share,
1517 Error **errp)
093bc2cd 1518{
2c9b15ca 1519 memory_region_init(mr, owner, name, size);
8ea9252a 1520 mr->ram = true;
14a3c10a 1521 mr->terminates = true;
545e92e0 1522 mr->destructor = memory_region_destructor_ram;
06329cce 1523 mr->ram_block = qemu_ram_alloc(size, share, mr, errp);
677e7805 1524 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
0b183fc8
PB		 1525}
1526
60786ef3
MT		 1527void memory_region_init_resizeable_ram(MemoryRegion *mr,
1528 Object *owner,
1529 const char *name,
1530 uint64_t size,
1531 uint64_t max_size,
1532 void (*resized)(const char*,
1533 uint64_t length,
1534 void *host),
1535 Error **errp)
1536{
1537 memory_region_init(mr, owner, name, size);
1538 mr->ram = true;
1539 mr->terminates = true;
1540 mr->destructor = memory_region_destructor_ram;
8e41fb63
FZ		 1541 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1542 mr, errp);
677e7805 1543 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
60786ef3
MT		 1544}
1545
0b183fc8
PB		 1546#ifdef __linux__
1547void memory_region_init_ram_from_file(MemoryRegion *mr,
1548 struct Object *owner,
1549 const char *name,
1550 uint64_t size,
98376843 1551 uint64_t align,
dbcb8981 1552 bool share,
7f56e740
PB		 1553 const char *path,
1554 Error **errp)
0b183fc8
PB		 1555{
1556 memory_region_init(mr, owner, name, size);
1557 mr->ram = true;
1558 mr->terminates = true;
1559 mr->destructor = memory_region_destructor_ram;
98376843 1560 mr->align = align;
8e41fb63 1561 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
677e7805 1562 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
093bc2cd 1563}
fea617c5
MAL		 1564
1565void memory_region_init_ram_from_fd(MemoryRegion *mr,
1566 struct Object *owner,
1567 const char *name,
1568 uint64_t size,
1569 bool share,
1570 int fd,
1571 Error **errp)
1572{
1573 memory_region_init(mr, owner, name, size);
1574 mr->ram = true;
1575 mr->terminates = true;
1576 mr->destructor = memory_region_destructor_ram;
1577 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1578 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1579}
0b183fc8 1580#endif
093bc2cd
AK		 1581
1582void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1583 Object *owner,
093bc2cd
AK		 1584 const char *name,
1585 uint64_t size,
1586 void *ptr)
1587{
2c9b15ca 1588 memory_region_init(mr, owner, name, size);
8ea9252a 1589 mr->ram = true;
14a3c10a 1590 mr->terminates = true;
fc3e7665 1591 mr->destructor = memory_region_destructor_ram;
677e7805 1592 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT		 1593
1594 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1595 assert(ptr != NULL);
8e41fb63 1596 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK		 1597}
1598
21e00fa5
AW		 1599void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1600 Object *owner,
1601 const char *name,
1602 uint64_t size,
1603 void *ptr)
e4dc3f59 1604{
21e00fa5
AW		 1605 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1606 mr->ram_device = true;
4a2e242b
AW		 1607 mr->ops = &ram_device_mem_ops;
1608 mr->opaque = mr;
e4dc3f59
ND		 1609}
1610
093bc2cd 1611void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1612 Object *owner,
093bc2cd
AK		 1613 const char *name,
1614 MemoryRegion *orig,
a8170e5e 1615 hwaddr offset,
093bc2cd
AK		 1616 uint64_t size)
1617{
2c9b15ca 1618 memory_region_init(mr, owner, name, size);
093bc2cd
AK		 1619 mr->alias = orig;
1620 mr->alias_offset = offset;
1621}
1622
b59821a9
PM		 1623void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1624 struct Object *owner,
1625 const char *name,
1626 uint64_t size,
1627 Error **errp)
a1777f7f
PM		 1628{
1629 memory_region_init(mr, owner, name, size);
1630 mr->ram = true;
1631 mr->readonly = true;
1632 mr->terminates = true;
1633 mr->destructor = memory_region_destructor_ram;
06329cce 1634 mr->ram_block = qemu_ram_alloc(size, false, mr, errp);
a1777f7f
PM		 1635 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1636}
1637
b59821a9
PM		 1638void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1639 Object *owner,
1640 const MemoryRegionOps *ops,
1641 void *opaque,
1642 const char *name,
1643 uint64_t size,
1644 Error **errp)
d0a9b5bc 1645{
39e0b03d 1646 assert(ops);
2c9b15ca 1647 memory_region_init(mr, owner, name, size);
7bc2b9cd 1648 mr->ops = ops;
75f5941c 1649 mr->opaque = opaque;
d0a9b5bc 1650 mr->terminates = true;
75c578dc 1651 mr->rom_device = true;
58268c8d 1652 mr->destructor = memory_region_destructor_ram;
06329cce 1653 mr->ram_block = qemu_ram_alloc(size, false, mr, errp);
d0a9b5bc
AK		 1654}
1655
1221a474
AK		 1656void memory_region_init_iommu(void *_iommu_mr,
1657 size_t instance_size,
1658 const char *mrtypename,
2c9b15ca 1659 Object *owner,
30951157
AK		 1660 const char *name,
1661 uint64_t size)
1662{
1221a474 1663 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK		 1664 struct MemoryRegion *mr;
1665
1221a474
AK		 1666 object_initialize(_iommu_mr, instance_size, mrtypename);
1667 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK		 1668 memory_region_do_init(mr, owner, name, size);
1669 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1670 mr->terminates = true; /* then re-forwards */
3df9d748
AK		 1671 QLIST_INIT(&iommu_mr->iommu_notify);
1672 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK		 1673}
1674
b4fefef9 1675static void memory_region_finalize(Object *obj)
093bc2cd 1676{
b4fefef9
PC		 1677 MemoryRegion *mr = MEMORY_REGION(obj);
1678
2e2b8eb7
PB		 1679 assert(!mr->container);
1680
1681 /* We know the region is not visible in any address space (it
1682 * does not have a container and cannot be a root either because
1683 * it has no references, so we can blindly clear mr->enabled.
1684 * memory_region_set_enabled instead could trigger a transaction
1685 * and cause an infinite loop.
1686 */
1687 mr->enabled = false;
1688 memory_region_transaction_begin();
1689 while (!QTAILQ_EMPTY(&mr->subregions)) {
1690 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1691 memory_region_del_subregion(mr, subregion);
1692 }
1693 memory_region_transaction_commit();
1694
545e92e0 1695 mr->destructor(mr);
093bc2cd 1696 memory_region_clear_coalescing(mr);
302fa283 1697 g_free((char *)mr->name);
7267c094 1698 g_free(mr->ioeventfds);
093bc2cd
AK		 1699}
1700
803c0816
PB		 1701Object *memory_region_owner(MemoryRegion *mr)
1702{
22a893e4
PB		 1703 Object *obj = OBJECT(mr);
1704 return obj->parent;
803c0816
PB		 1705}
1706
46637be2
PB		 1707void memory_region_ref(MemoryRegion *mr)
1708{
22a893e4
PB		 1709 /* MMIO callbacks most likely will access data that belongs
1710 * to the owner, hence the need to ref/unref the owner whenever
1711 * the memory region is in use.
1712 *
1713 * The memory region is a child of its owner. As long as the
1714 * owner doesn't call unparent itself on the memory region,
1715 * ref-ing the owner will also keep the memory region alive.
612263cf
PB		 1716 * Memory regions without an owner are supposed to never go away;
1717 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1718 */
612263cf
PB		 1719 if (mr && mr->owner) {
1720 object_ref(mr->owner);
46637be2
PB		 1721 }
1722}
1723
1724void memory_region_unref(MemoryRegion *mr)
1725{
612263cf
PB		 1726 if (mr && mr->owner) {
1727 object_unref(mr->owner);
46637be2
PB		 1728 }
1729}
1730
093bc2cd
AK		 1731uint64_t memory_region_size(MemoryRegion *mr)
1732{
08dafab4
AK		 1733 if (int128_eq(mr->size, int128_2_64())) {
1734 return UINT64_MAX;
1735 }
1736 return int128_get64(mr->size);
093bc2cd
AK		 1737}
1738
5d546d4b 1739const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1740{
d1dd32af
PC		 1741 if (!mr->name) {
1742 ((MemoryRegion *)mr)->name =
1743 object_get_canonical_path_component(OBJECT(mr));
1744 }
302fa283 1745 return mr->name;
8991c79b
AK		 1746}
1747
21e00fa5 1748bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1749{
21e00fa5 1750 return mr->ram_device;
e4dc3f59
ND		 1751}
1752
2d1a35be 1753uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1754{
6f6a5ef3 1755 uint8_t mask = mr->dirty_log_mask;
adaad61c 1756 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB		 1757 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1758 }
1759 return mask;
55043ba3
AK		 1760}
1761
2d1a35be
PB		 1762bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1763{
1764 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1765}
1766
3df9d748 1767static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
5bf3d319
PX		 1768{
1769 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1770 IOMMUNotifier *iommu_notifier;
1221a474 1771 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
5bf3d319 1772
3df9d748 1773 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX		 1774 flags |= iommu_notifier->notifier_flags;
1775 }
1776
1221a474
AK		 1777 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1778 imrc->notify_flag_changed(iommu_mr,
1779 iommu_mr->iommu_notify_flags,
1780 flags);
5bf3d319
PX		 1781 }
1782
3df9d748 1783 iommu_mr->iommu_notify_flags = flags;
5bf3d319
PX		 1784}
1785
cdb30812
PX		 1786void memory_region_register_iommu_notifier(MemoryRegion *mr,
1787 IOMMUNotifier *n)
06866575 1788{
3df9d748
AK		 1789 IOMMUMemoryRegion *iommu_mr;
1790
efcd38c5
JW		 1791 if (mr->alias) {
1792 memory_region_register_iommu_notifier(mr->alias, n);
1793 return;
1794 }
1795
cdb30812 1796 /* We need to register for at least one bitfield */
3df9d748 1797 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1798 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1799 assert(n->start <= n->end);
3df9d748
AK		 1800 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1801 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG		 1802}
1803
3df9d748 1804uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1805{
1221a474
AK		 1806 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1807
1808 if (imrc->get_min_page_size) {
1809 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK		 1810 }
1811 return TARGET_PAGE_SIZE;
1812}
1813
3df9d748 1814void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1815{
3df9d748 1816 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1817 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1818 hwaddr addr, granularity;
a788f227
DG		 1819 IOMMUTLBEntry iotlb;
1820
faa362e3 1821 /* If the IOMMU has its own replay callback, override */
1221a474
AK		 1822 if (imrc->replay) {
1823 imrc->replay(iommu_mr, n);
faa362e3
PX		 1824 return;
1825 }
1826
3df9d748 1827 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1828
a788f227 1829 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1221a474 1830 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE);
a788f227
DG		 1831 if (iotlb.perm != IOMMU_NONE) {
1832 n->notify(n, &iotlb);
1833 }
1834
1835 /* if (2^64 - MR size) < granularity, it's possible to get an
1836 * infinite loop here. This should catch such a wraparound */
1837 if ((addr + granularity) < addr) {
1838 break;
1839 }
1840 }
1841}
1842
3df9d748 1843void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
de472e4a
PX		 1844{
1845 IOMMUNotifier *notifier;
1846
3df9d748
AK		 1847 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1848 memory_region_iommu_replay(iommu_mr, notifier);
de472e4a
PX		 1849 }
1850}
1851
cdb30812
PX		 1852void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1853 IOMMUNotifier *n)
06866575 1854{
3df9d748
AK		 1855 IOMMUMemoryRegion *iommu_mr;
1856
efcd38c5
JW		 1857 if (mr->alias) {
1858 memory_region_unregister_iommu_notifier(mr->alias, n);
1859 return;
1860 }
cdb30812 1861 QLIST_REMOVE(n, node);
3df9d748
AK		 1862 iommu_mr = IOMMU_MEMORY_REGION(mr);
1863 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG		 1864}
1865
bd2bfa4c
PX		 1866void memory_region_notify_one(IOMMUNotifier *notifier,
1867 IOMMUTLBEntry *entry)
06866575 1868{
cdb30812
PX		 1869 IOMMUNotifierFlag request_flags;
1870
bd2bfa4c
PX		 1871 /*
1872 * Skip the notification if the notification does not overlap
1873 * with registered range.
1874 */
b021d1c0 1875 if (notifier->start > entry->iova + entry->addr_mask ||
bd2bfa4c
PX		 1876 notifier->end < entry->iova) {
1877 return;
1878 }
cdb30812 1879
bd2bfa4c 1880 if (entry->perm & IOMMU_RW) {
cdb30812
PX		 1881 request_flags = IOMMU_NOTIFIER_MAP;
1882 } else {
1883 request_flags = IOMMU_NOTIFIER_UNMAP;
1884 }
1885
bd2bfa4c
PX		 1886 if (notifier->notifier_flags & request_flags) {
1887 notifier->notify(notifier, entry);
1888 }
1889}
1890
3df9d748 1891void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
bd2bfa4c
PX		 1892 IOMMUTLBEntry entry)
1893{
1894 IOMMUNotifier *iommu_notifier;
1895
3df9d748 1896 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1897
3df9d748 1898 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
bd2bfa4c 1899 memory_region_notify_one(iommu_notifier, &entry);
cdb30812 1900 }
06866575
DG		 1901}
1902
f1334de6
AK		 1903int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1904 enum IOMMUMemoryRegionAttr attr,
1905 void *data)
1906{
1907 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1908
1909 if (!imrc->get_attr) {
1910 return -EINVAL;
1911 }
1912
1913 return imrc->get_attr(iommu_mr, attr, data);
1914}
1915
093bc2cd
AK		 1916void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1917{
5a583347 1918 uint8_t mask = 1 << client;
deb809ed 1919 uint8_t old_logging;
5a583347 1920
dbddac6d 1921 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB		 1922 old_logging = mr->vga_logging_count;
1923 mr->vga_logging_count += log ? 1 : -1;
1924 if (!!old_logging == !!mr->vga_logging_count) {
1925 return;
1926 }
1927
59023ef4 1928 memory_region_transaction_begin();
5a583347 1929 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1930 memory_region_update_pending |= mr->enabled;
59023ef4 1931 memory_region_transaction_commit();
093bc2cd
AK		 1932}
1933
a8170e5e
AK		 1934bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1935 hwaddr size, unsigned client)
093bc2cd 1936{
8e41fb63
FZ		 1937 assert(mr->ram_block);
1938 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1939 size, client);
093bc2cd
AK		 1940}
1941
a8170e5e
AK		 1942void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1943 hwaddr size)
093bc2cd 1944{
8e41fb63
FZ		 1945 assert(mr->ram_block);
1946 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1947 size,
58d2707e 1948 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK		 1949}
1950
0fe1eca7 1951static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
093bc2cd 1952{
0a752eee 1953 MemoryListener *listener;
0d673e36 1954 AddressSpace *as;
0a752eee 1955 FlatView *view;
5a583347
AK		 1956 FlatRange *fr;
1957
0a752eee
PB		 1958 /* If the same address space has multiple log_sync listeners, we
1959 * visit that address space's FlatView multiple times. But because
1960 * log_sync listeners are rare, it's still cheaper than walking each
1961 * address space once.
1962 */
1963 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1964 if (!listener->log_sync) {
1965 continue;
1966 }
1967 as = listener->address_space;
1968 view = address_space_get_flatview(as);
99e86347 1969 FOR_EACH_FLAT_RANGE(fr, view) {
3ebb1817 1970 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
16620684 1971 MemoryRegionSection mrs = section_from_flat_range(fr, view);
0a752eee 1972 listener->log_sync(listener, &mrs);
0d673e36 1973 }
5a583347 1974 }
856d7245 1975 flatview_unref(view);
5a583347 1976 }
093bc2cd
AK		 1977}
1978
0fe1eca7
PB		 1979DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
1980 hwaddr addr,
1981 hwaddr size,
1982 unsigned client)
1983{
1984 assert(mr->ram_block);
1985 memory_region_sync_dirty_bitmap(mr);
1986 return cpu_physical_memory_snapshot_and_clear_dirty(
1987 memory_region_get_ram_addr(mr) + addr, size, client);
1988}
1989
1990bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
1991 hwaddr addr, hwaddr size)
1992{
1993 assert(mr->ram_block);
1994 return cpu_physical_memory_snapshot_get_dirty(snap,
1995 memory_region_get_ram_addr(mr) + addr, size);
1996}
1997
093bc2cd
AK		 1998void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1999{
fb1cd6f9 2000 if (mr->readonly != readonly) {
59023ef4 2001 memory_region_transaction_begin();
fb1cd6f9 2002 mr->readonly = readonly;
22bde714 2003 memory_region_update_pending |= mr->enabled;
59023ef4 2004 memory_region_transaction_commit();
fb1cd6f9 2005 }
093bc2cd
AK		 2006}
2007
5f9a5ea1 2008void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 2009{
5f9a5ea1 2010 if (mr->romd_mode != romd_mode) {
59023ef4 2011 memory_region_transaction_begin();
5f9a5ea1 2012 mr->romd_mode = romd_mode;
22bde714 2013 memory_region_update_pending |= mr->enabled;
59023ef4 2014 memory_region_transaction_commit();
d0a9b5bc
AK		 2015 }
2016}
2017
a8170e5e
AK		 2018void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2019 hwaddr size, unsigned client)
093bc2cd 2020{
8e41fb63
FZ		 2021 assert(mr->ram_block);
2022 cpu_physical_memory_test_and_clear_dirty(
2023 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK		 2024}
2025
a35ba7be
PB		 2026int memory_region_get_fd(MemoryRegion *mr)
2027{
4ff87573
PB		 2028 int fd;
2029
2030 rcu_read_lock();
2031 while (mr->alias) {
2032 mr = mr->alias;
a35ba7be 2033 }
4ff87573
PB		 2034 fd = mr->ram_block->fd;
2035 rcu_read_unlock();
a35ba7be 2036
4ff87573
PB		 2037 return fd;
2038}
a35ba7be 2039
093bc2cd
AK		 2040void *memory_region_get_ram_ptr(MemoryRegion *mr)
2041{
49b24afc
PB		 2042 void *ptr;
2043 uint64_t offset = 0;
093bc2cd 2044
49b24afc
PB		 2045 rcu_read_lock();
2046 while (mr->alias) {
2047 offset += mr->alias_offset;
2048 mr = mr->alias;
2049 }
8e41fb63 2050 assert(mr->ram_block);
0878d0e1 2051 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
49b24afc 2052 rcu_read_unlock();
093bc2cd 2053
0878d0e1 2054 return ptr;
093bc2cd
AK		 2055}
2056
07bdaa41
PB		 2057MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2058{
2059 RAMBlock *block;
2060
2061 block = qemu_ram_block_from_host(ptr, false, offset);
2062 if (!block) {
2063 return NULL;
2064 }
2065
2066 return block->mr;
2067}
2068
7ebb2745
FZ		 2069ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2070{
2071 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2072}
2073
37d7c084
PB		 2074void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2075{
8e41fb63 2076 assert(mr->ram_block);
37d7c084 2077
fa53a0e5 2078 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB		 2079}
2080
0d673e36 2081static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 2082{
99e86347 2083 FlatView *view;
093bc2cd
AK		 2084 FlatRange *fr;
2085 CoalescedMemoryRange *cmr;
2086 AddrRange tmp;
95d2994a 2087 MemoryRegionSection section;
093bc2cd 2088
856d7245 2089 view = address_space_get_flatview(as);
99e86347 2090 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 2091 if (fr->mr == mr) {
95d2994a 2092 section = (MemoryRegionSection) {
16620684 2093 .fv = view,
95d2994a 2094 .offset_within_address_space = int128_get64(fr->addr.start),
052e87b0 2095 .size = fr->addr.size,
95d2994a
AK		 2096 };
2097
9a54635d 2098 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
95d2994a
AK		 2099 int128_get64(fr->addr.start),
2100 int128_get64(fr->addr.size));
093bc2cd
AK		 2101 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
2102 tmp = addrrange_shift(cmr->addr,
08dafab4
AK		 2103 int128_sub(fr->addr.start,
2104 int128_make64(fr->offset_in_region)));
093bc2cd
AK		 2105 if (!addrrange_intersects(tmp, fr->addr)) {
2106 continue;
2107 }
2108 tmp = addrrange_intersection(tmp, fr->addr);
9a54635d 2109 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
95d2994a
AK		 2110 int128_get64(tmp.start),
2111 int128_get64(tmp.size));
093bc2cd
AK		 2112 }
2113 }
2114 }
856d7245 2115 flatview_unref(view);
093bc2cd
AK		 2116}
2117
0d673e36
AK		 2118static void memory_region_update_coalesced_range(MemoryRegion *mr)
2119{
2120 AddressSpace *as;
2121
2122 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2123 memory_region_update_coalesced_range_as(mr, as);
2124 }
2125}
2126
093bc2cd
AK		 2127void memory_region_set_coalescing(MemoryRegion *mr)
2128{
2129 memory_region_clear_coalescing(mr);
08dafab4 2130 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK		 2131}
2132
2133void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 2134 hwaddr offset,
093bc2cd
AK		 2135 uint64_t size)
2136{
7267c094 2137 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2138
08dafab4 2139 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK		 2140 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2141 memory_region_update_coalesced_range(mr);
d410515e 2142 memory_region_set_flush_coalesced(mr);
093bc2cd
AK		 2143}
2144
2145void memory_region_clear_coalescing(MemoryRegion *mr)
2146{
2147 CoalescedMemoryRange *cmr;
ab5b3db5 2148 bool updated = false;
093bc2cd 2149
d410515e
JK		 2150 qemu_flush_coalesced_mmio_buffer();
2151 mr->flush_coalesced_mmio = false;
2152
093bc2cd
AK		 2153 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2154 cmr = QTAILQ_FIRST(&mr->coalesced);
2155 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 2156 g_free(cmr);
ab5b3db5
FZ		 2157 updated = true;
2158 }
2159
2160 if (updated) {
2161 memory_region_update_coalesced_range(mr);
093bc2cd 2162 }
093bc2cd
AK		 2163}
2164
d410515e
JK		 2165void memory_region_set_flush_coalesced(MemoryRegion *mr)
2166{
2167 mr->flush_coalesced_mmio = true;
2168}
2169
2170void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2171{
2172 qemu_flush_coalesced_mmio_buffer();
2173 if (QTAILQ_EMPTY(&mr->coalesced)) {
2174 mr->flush_coalesced_mmio = false;
2175 }
2176}
2177
196ea131
JK		 2178void memory_region_clear_global_locking(MemoryRegion *mr)
2179{
2180 mr->global_locking = false;
2181}
2182
8c56c1a5
PF		 2183static bool userspace_eventfd_warning;
2184
3e9d69e7 2185void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2186 hwaddr addr,
3e9d69e7
AK		 2187 unsigned size,
2188 bool match_data,
2189 uint64_t data,
753d5e14 2190 EventNotifier *e)
3e9d69e7
AK		 2191{
2192 MemoryRegionIoeventfd mrfd = {
08dafab4
AK		 2193 .addr.start = int128_make64(addr),
2194 .addr.size = int128_make64(size),
3e9d69e7
AK		 2195 .match_data = match_data,
2196 .data = data,
753d5e14 2197 .e = e,
3e9d69e7
AK		 2198 };
2199 unsigned i;
2200
8c56c1a5
PF		 2201 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2202 userspace_eventfd_warning))) {
2203 userspace_eventfd_warning = true;
2204 error_report("Using eventfd without MMIO binding in KVM. "
2205 "Suboptimal performance expected");
2206 }
2207
b8aecea2
JW		 2208 if (size) {
2209 adjust_endianness(mr, &mrfd.data, size);
2210 }
59023ef4 2211 memory_region_transaction_begin();
3e9d69e7
AK		 2212 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2213 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
2214 break;
2215 }
2216 }
2217 ++mr->ioeventfd_nb;
7267c094 2218 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK		 2219 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2220 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2221 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2222 mr->ioeventfds[i] = mrfd;
4dc56152 2223 ioeventfd_update_pending |= mr->enabled;
59023ef4 2224 memory_region_transaction_commit();
3e9d69e7
AK		 2225}
2226
2227void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2228 hwaddr addr,
3e9d69e7
AK		 2229 unsigned size,
2230 bool match_data,
2231 uint64_t data,
753d5e14 2232 EventNotifier *e)
3e9d69e7
AK		 2233{
2234 MemoryRegionIoeventfd mrfd = {
08dafab4
AK		 2235 .addr.start = int128_make64(addr),
2236 .addr.size = int128_make64(size),
3e9d69e7
AK		 2237 .match_data = match_data,
2238 .data = data,
753d5e14 2239 .e = e,
3e9d69e7
AK		 2240 };
2241 unsigned i;
2242
b8aecea2
JW		 2243 if (size) {
2244 adjust_endianness(mr, &mrfd.data, size);
2245 }
59023ef4 2246 memory_region_transaction_begin();
3e9d69e7
AK		 2247 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2248 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
2249 break;
2250 }
2251 }
2252 assert(i != mr->ioeventfd_nb);
2253 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2254 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2255 --mr->ioeventfd_nb;
7267c094 2256 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2257 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2258 ioeventfd_update_pending |= mr->enabled;
59023ef4 2259 memory_region_transaction_commit();
3e9d69e7
AK		 2260}
2261
feca4ac1 2262static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2263{
feca4ac1 2264 MemoryRegion *mr = subregion->container;
093bc2cd
AK		 2265 MemoryRegion *other;
2266
59023ef4
JK		 2267 memory_region_transaction_begin();
2268
dfde4e6e 2269 memory_region_ref(subregion);
093bc2cd
AK		 2270 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2271 if (subregion->priority >= other->priority) {
2272 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2273 goto done;
2274 }
2275 }
2276 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2277done:
22bde714 2278 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2279 memory_region_transaction_commit();
093bc2cd
AK		 2280}
2281
0598701a
PC		 2282static void memory_region_add_subregion_common(MemoryRegion *mr,
2283 hwaddr offset,
2284 MemoryRegion *subregion)
2285{
feca4ac1
PB		 2286 assert(!subregion->container);
2287 subregion->container = mr;
0598701a 2288 subregion->addr = offset;
feca4ac1 2289 memory_region_update_container_subregions(subregion);
0598701a 2290}
093bc2cd
AK		 2291
2292void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2293 hwaddr offset,
093bc2cd
AK		 2294 MemoryRegion *subregion)
2295{
093bc2cd
AK		 2296 subregion->priority = 0;
2297 memory_region_add_subregion_common(mr, offset, subregion);
2298}
2299
2300void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2301 hwaddr offset,
093bc2cd 2302 MemoryRegion *subregion,
a1ff8ae0 2303 int priority)
093bc2cd 2304{
093bc2cd
AK		 2305 subregion->priority = priority;
2306 memory_region_add_subregion_common(mr, offset, subregion);
2307}
2308
2309void memory_region_del_subregion(MemoryRegion *mr,
2310 MemoryRegion *subregion)
2311{
59023ef4 2312 memory_region_transaction_begin();
feca4ac1
PB		 2313 assert(subregion->container == mr);
2314 subregion->container = NULL;
093bc2cd 2315 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2316 memory_region_unref(subregion);
22bde714 2317 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2318 memory_region_transaction_commit();
6bba19ba
AK		 2319}
2320
2321void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2322{
2323 if (enabled == mr->enabled) {
2324 return;
2325 }
59023ef4 2326 memory_region_transaction_begin();
6bba19ba 2327 mr->enabled = enabled;
22bde714 2328 memory_region_update_pending = true;
59023ef4 2329 memory_region_transaction_commit();
093bc2cd 2330}
1c0ffa58 2331
e7af4c67
MT		 2332void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2333{
2334 Int128 s = int128_make64(size);
2335
2336 if (size == UINT64_MAX) {
2337 s = int128_2_64();
2338 }
2339 if (int128_eq(s, mr->size)) {
2340 return;
2341 }
2342 memory_region_transaction_begin();
2343 mr->size = s;
2344 memory_region_update_pending = true;
2345 memory_region_transaction_commit();
2346}
2347
67891b8a 2348static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2349{
feca4ac1 2350 MemoryRegion *container = mr->container;
2282e1af 2351
feca4ac1 2352 if (container) {
67891b8a
PC		 2353 memory_region_transaction_begin();
2354 memory_region_ref(mr);
feca4ac1
PB		 2355 memory_region_del_subregion(container, mr);
2356 mr->container = container;
2357 memory_region_update_container_subregions(mr);
67891b8a
PC		 2358 memory_region_unref(mr);
2359 memory_region_transaction_commit();
2282e1af 2360 }
67891b8a 2361}
2282e1af 2362
67891b8a
PC		 2363void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2364{
2365 if (addr != mr->addr) {
2366 mr->addr = addr;
2367 memory_region_readd_subregion(mr);
2368 }
2282e1af
AK		 2369}
2370
a8170e5e 2371void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2372{
4703359e 2373 assert(mr->alias);
4703359e 2374
59023ef4 2375 if (offset == mr->alias_offset) {
4703359e
AK		 2376 return;
2377 }
2378
59023ef4
JK		 2379 memory_region_transaction_begin();
2380 mr->alias_offset = offset;
22bde714 2381 memory_region_update_pending |= mr->enabled;
59023ef4 2382 memory_region_transaction_commit();
4703359e
AK		 2383}
2384
a2b257d6
IM		 2385uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2386{
2387 return mr->align;
2388}
2389
e2177955
AK		 2390static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2391{
2392 const AddrRange *addr = addr_;
2393 const FlatRange *fr = fr_;
2394
2395 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2396 return -1;
2397 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2398 return 1;
2399 }
2400 return 0;
2401}
2402
99e86347 2403static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2404{
99e86347 2405 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK		 2406 sizeof(FlatRange), cmp_flatrange_addr);
2407}
2408
eed2bacf
IM		 2409bool memory_region_is_mapped(MemoryRegion *mr)
2410{
2411 return mr->container ? true : false;
2412}
2413
c6742b14
PB		 2414/* Same as memory_region_find, but it does not add a reference to the
2415 * returned region. It must be called from an RCU critical section.
2416 */
2417static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2418 hwaddr addr, uint64_t size)
e2177955 2419{
052e87b0 2420 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB		 2421 MemoryRegion *root;
2422 AddressSpace *as;
2423 AddrRange range;
99e86347 2424 FlatView *view;
73034e9e
PB		 2425 FlatRange *fr;
2426
2427 addr += mr->addr;
feca4ac1
PB		 2428 for (root = mr; root->container; ) {
2429 root = root->container;
73034e9e
PB		 2430 addr += root->addr;
2431 }
e2177955 2432
73034e9e 2433 as = memory_region_to_address_space(root);
eed2bacf
IM		 2434 if (!as) {
2435 return ret;
2436 }
73034e9e 2437 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2438
16620684 2439 view = address_space_to_flatview(as);
99e86347 2440 fr = flatview_lookup(view, range);
e2177955 2441 if (!fr) {
c6742b14 2442 return ret;
e2177955
AK		 2443 }
2444
99e86347 2445 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK		 2446 --fr;
2447 }
2448
2449 ret.mr = fr->mr;
16620684 2450 ret.fv = view;
e2177955
AK		 2451 range = addrrange_intersection(range, fr->addr);
2452 ret.offset_within_region = fr->offset_in_region;
2453 ret.offset_within_region += int128_get64(int128_sub(range.start,
2454 fr->addr.start));
052e87b0 2455 ret.size = range.size;
e2177955 2456 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2457 ret.readonly = fr->readonly;
c6742b14
PB		 2458 return ret;
2459}
2460
2461MemoryRegionSection memory_region_find(MemoryRegion *mr,
2462 hwaddr addr, uint64_t size)
2463{
2464 MemoryRegionSection ret;
2465 rcu_read_lock();
2466 ret = memory_region_find_rcu(mr, addr, size);
2467 if (ret.mr) {
2468 memory_region_ref(ret.mr);
2469 }
2b647668 2470 rcu_read_unlock();
e2177955
AK		 2471 return ret;
2472}
2473
c6742b14
PB		 2474bool memory_region_present(MemoryRegion *container, hwaddr addr)
2475{
2476 MemoryRegion *mr;
2477
2478 rcu_read_lock();
2479 mr = memory_region_find_rcu(container, addr, 1).mr;
2480 rcu_read_unlock();
2481 return mr && mr != container;
2482}
2483
9c1f8f44 2484void memory_global_dirty_log_sync(void)
86e775c6 2485{
3ebb1817 2486 memory_region_sync_dirty_bitmap(NULL);
7664e80c
AK		 2487}
2488
19310760
JZ		 2489static VMChangeStateEntry *vmstate_change;
2490
7664e80c
AK		 2491void memory_global_dirty_log_start(void)
2492{
19310760
JZ		 2493 if (vmstate_change) {
2494 qemu_del_vm_change_state_handler(vmstate_change);
2495 vmstate_change = NULL;
2496 }
2497
7664e80c 2498 global_dirty_log = true;
6f6a5ef3 2499
7376e582 2500 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3
PB		 2501
2502 /* Refresh DIRTY_LOG_MIGRATION bit. */
2503 memory_region_transaction_begin();
2504 memory_region_update_pending = true;
2505 memory_region_transaction_commit();
7664e80c
AK		 2506}
2507
19310760 2508static void memory_global_dirty_log_do_stop(void)
7664e80c 2509{
7664e80c 2510 global_dirty_log = false;
6f6a5ef3
PB		 2511
2512 /* Refresh DIRTY_LOG_MIGRATION bit. */
2513 memory_region_transaction_begin();
2514 memory_region_update_pending = true;
2515 memory_region_transaction_commit();
2516
7376e582 2517 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK		 2518}
2519
19310760
JZ		 2520static void memory_vm_change_state_handler(void *opaque, int running,
2521 RunState state)
2522{
2523 if (running) {
2524 memory_global_dirty_log_do_stop();
2525
2526 if (vmstate_change) {
2527 qemu_del_vm_change_state_handler(vmstate_change);
2528 vmstate_change = NULL;
2529 }
2530 }
2531}
2532
2533void memory_global_dirty_log_stop(void)
2534{
2535 if (!runstate_is_running()) {
2536 if (vmstate_change) {
2537 return;
2538 }
2539 vmstate_change = qemu_add_vm_change_state_handler(
2540 memory_vm_change_state_handler, NULL);
2541 return;
2542 }
2543
2544 memory_global_dirty_log_do_stop();
2545}
2546
7664e80c
AK		 2547static void listener_add_address_space(MemoryListener *listener,
2548 AddressSpace *as)
2549{
99e86347 2550 FlatView *view;
7664e80c
AK		 2551 FlatRange *fr;
2552
680a4783
PB		 2553 if (listener->begin) {
2554 listener->begin(listener);
2555 }
7664e80c 2556 if (global_dirty_log) {
975aefe0
AK		 2557 if (listener->log_global_start) {
2558 listener->log_global_start(listener);
2559 }
7664e80c 2560 }
975aefe0 2561
856d7245 2562 view = address_space_get_flatview(as);
99e86347 2563 FOR_EACH_FLAT_RANGE(fr, view) {
279836f8
DH		 2564 MemoryRegionSection section = section_from_flat_range(fr, view);
2565
975aefe0
AK		 2566 if (listener->region_add) {
2567 listener->region_add(listener, &section);
2568 }
ae990e6c
DH		 2569 if (fr->dirty_log_mask && listener->log_start) {
2570 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2571 }
7664e80c 2572 }
680a4783
PB		 2573 if (listener->commit) {
2574 listener->commit(listener);
2575 }
856d7245 2576 flatview_unref(view);
7664e80c
AK		 2577}
2578
d25836ca
PX		 2579static void listener_del_address_space(MemoryListener *listener,
2580 AddressSpace *as)
2581{
2582 FlatView *view;
2583 FlatRange *fr;
2584
2585 if (listener->begin) {
2586 listener->begin(listener);
2587 }
2588 view = address_space_get_flatview(as);
2589 FOR_EACH_FLAT_RANGE(fr, view) {
2590 MemoryRegionSection section = section_from_flat_range(fr, view);
2591
2592 if (fr->dirty_log_mask && listener->log_stop) {
2593 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2594 }
2595 if (listener->region_del) {
2596 listener->region_del(listener, &section);
2597 }
2598 }
2599 if (listener->commit) {
2600 listener->commit(listener);
2601 }
2602 flatview_unref(view);
2603}
2604
d45fa784 2605void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2606{
72e22d2f
AK		 2607 MemoryListener *other = NULL;
2608
d45fa784 2609 listener->address_space = as;
72e22d2f
AK		 2610 if (QTAILQ_EMPTY(&memory_listeners)
2611 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2612 memory_listeners)->priority) {
2613 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2614 } else {
2615 QTAILQ_FOREACH(other, &memory_listeners, link) {
2616 if (listener->priority < other->priority) {
2617 break;
2618 }
2619 }
2620 QTAILQ_INSERT_BEFORE(other, listener, link);
2621 }
0d673e36 2622
9a54635d
PB		 2623 if (QTAILQ_EMPTY(&as->listeners)
2624 || listener->priority >= QTAILQ_LAST(&as->listeners,
2625 memory_listeners)->priority) {
2626 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2627 } else {
2628 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2629 if (listener->priority < other->priority) {
2630 break;
2631 }
2632 }
2633 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2634 }
2635
d45fa784 2636 listener_add_address_space(listener, as);
7664e80c
AK		 2637}
2638
2639void memory_listener_unregister(MemoryListener *listener)
2640{
1d8280c1
PB		 2641 if (!listener->address_space) {
2642 return;
2643 }
2644
d25836ca 2645 listener_del_address_space(listener, listener->address_space);
72e22d2f 2646 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2647 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2648 listener->address_space = NULL;
86e775c6 2649}
e2177955 2650
c9356746
FK		 2651bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2652{
2653 void *host;
2654 unsigned size = 0;
2655 unsigned offset = 0;
2656 Object *new_interface;
2657
2658 if (!mr || !mr->ops->request_ptr) {
2659 return false;
2660 }
2661
2662 /*
2663 * Avoid an update if the request_ptr call
2664 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2665 * a cache.
2666 */
2667 memory_region_transaction_begin();
2668
2669 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2670
2671 if (!host || !size) {
2672 memory_region_transaction_commit();
2673 return false;
2674 }
2675
2676 new_interface = object_new("mmio_interface");
2677 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2678 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2679 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2680 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2681 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2682 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2683
2684 memory_region_transaction_commit();
2685 return true;
2686}
2687
2688typedef struct MMIOPtrInvalidate {
2689 MemoryRegion *mr;
2690 hwaddr offset;
2691 unsigned size;
2692 int busy;
2693 int allocated;
2694} MMIOPtrInvalidate;
2695
2696#define MAX_MMIO_INVALIDATE 10
2697static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2698
2699static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2700 run_on_cpu_data data)
2701{
2702 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2703 MemoryRegion *mr = invalidate_data->mr;
2704 hwaddr offset = invalidate_data->offset;
2705 unsigned size = invalidate_data->size;
2706 MemoryRegionSection section = memory_region_find(mr, offset, size);
2707
2708 qemu_mutex_lock_iothread();
2709
2710 /* Reset dirty so this doesn't happen later. */
2711 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2712
2713 if (section.mr != mr) {
2714 /* memory_region_find add a ref on section.mr */
2715 memory_region_unref(section.mr);
2716 if (MMIO_INTERFACE(section.mr->owner)) {
2717 /* We found the interface just drop it. */
2718 object_property_set_bool(section.mr->owner, false, "realized",
2719 NULL);
2720 object_unref(section.mr->owner);
2721 object_unparent(section.mr->owner);
2722 }
2723 }
2724
2725 qemu_mutex_unlock_iothread();
2726
2727 if (invalidate_data->allocated) {
2728 g_free(invalidate_data);
2729 } else {
2730 invalidate_data->busy = 0;
2731 }
2732}
2733
2734void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2735 unsigned size)
2736{
2737 size_t i;
2738 MMIOPtrInvalidate *invalidate_data = NULL;
2739
2740 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2741 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2742 invalidate_data = &mmio_ptr_invalidate_list[i];
2743 break;
2744 }
2745 }
2746
2747 if (!invalidate_data) {
2748 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2749 invalidate_data->allocated = 1;
2750 }
2751
2752 invalidate_data->mr = mr;
2753 invalidate_data->offset = offset;
2754 invalidate_data->size = size;
2755
2756 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2757 RUN_ON_CPU_HOST_PTR(invalidate_data));
2758}
2759
7dca8043 2760void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2761{
ac95190e 2762 memory_region_ref(root);
8786db7c 2763 as->root = root;
67ace39b 2764 as->current_map = NULL;
4c19eb72
AK		 2765 as->ioeventfd_nb = 0;
2766 as->ioeventfds = NULL;
9a54635d 2767 QTAILQ_INIT(&as->listeners);
0d673e36 2768 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2769 as->name = g_strdup(name ? name : "anonymous");
202fc01b
AK		 2770 address_space_update_topology(as);
2771 address_space_update_ioeventfds(as);
1c0ffa58 2772}
658b2224 2773
374f2981 2774static void do_address_space_destroy(AddressSpace *as)
83f3c251 2775{
9a54635d 2776 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2777
856d7245 2778 flatview_unref(as->current_map);
7dca8043 2779 g_free(as->name);
4c19eb72 2780 g_free(as->ioeventfds);
ac95190e 2781 memory_region_unref(as->root);
83f3c251
AK		 2782}
2783
374f2981
PB		 2784void address_space_destroy(AddressSpace *as)
2785{
ac95190e
PB		 2786 MemoryRegion *root = as->root;
2787
374f2981
PB		 2788 /* Flush out anything from MemoryListeners listening in on this */
2789 memory_region_transaction_begin();
2790 as->root = NULL;
2791 memory_region_transaction_commit();
2792 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2793
2794 /* At this point, as->dispatch and as->current_map are dummy
2795 * entries that the guest should never use. Wait for the old
2796 * values to expire before freeing the data.
2797 */
ac95190e 2798 as->root = root;
374f2981
PB		 2799 call_rcu(as, do_address_space_destroy, rcu);
2800}
2801
4e831901
PX		 2802static const char *memory_region_type(MemoryRegion *mr)
2803{
2804 if (memory_region_is_ram_device(mr)) {
2805 return "ramd";
2806 } else if (memory_region_is_romd(mr)) {
2807 return "romd";
2808 } else if (memory_region_is_rom(mr)) {
2809 return "rom";
2810 } else if (memory_region_is_ram(mr)) {
2811 return "ram";
2812 } else {
2813 return "i/o";
2814 }
2815}
2816
314e2987
BS		 2817typedef struct MemoryRegionList MemoryRegionList;
2818
2819struct MemoryRegionList {
2820 const MemoryRegion *mr;
a16878d2 2821 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS		 2822};
2823
a16878d2 2824typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
314e2987 2825
4e831901
PX		 2826#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2827 int128_sub((size), int128_one())) : 0)
2828#define MTREE_INDENT " "
2829
314e2987
BS		 2830static void mtree_print_mr(fprintf_function mon_printf, void *f,
2831 const MemoryRegion *mr, unsigned int level,
a8170e5e 2832 hwaddr base,
9479c57a 2833 MemoryRegionListHead *alias_print_queue)
314e2987 2834{
9479c57a
JK		 2835 MemoryRegionList *new_ml, *ml, *next_ml;
2836 MemoryRegionListHead submr_print_queue;
314e2987
BS		 2837 const MemoryRegion *submr;
2838 unsigned int i;
b31f8412 2839 hwaddr cur_start, cur_end;
314e2987 2840
f8a9f720 2841 if (!mr) {
314e2987
BS		 2842 return;
2843 }
2844
2845 for (i = 0; i < level; i++) {
4e831901 2846 mon_printf(f, MTREE_INDENT);
314e2987
BS		 2847 }
2848
b31f8412
PX		 2849 cur_start = base + mr->addr;
2850 cur_end = cur_start + MR_SIZE(mr->size);
2851
2852 /*
2853 * Try to detect overflow of memory region. This should never
2854 * happen normally. When it happens, we dump something to warn the
2855 * user who is observing this.
2856 */
2857 if (cur_start < base || cur_end < cur_start) {
2858 mon_printf(f, "[DETECTED OVERFLOW!] ");
2859 }
2860
314e2987
BS		 2861 if (mr->alias) {
2862 MemoryRegionList *ml;
2863 bool found = false;
2864
2865 /* check if the alias is already in the queue */
a16878d2 2866 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2867 if (ml->mr == mr->alias) {
314e2987
BS		 2868 found = true;
2869 }
2870 }
2871
2872 if (!found) {
2873 ml = g_new(MemoryRegionList, 1);
2874 ml->mr = mr->alias;
a16878d2 2875 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2876 }
4896d74b 2877 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
4e831901 2878 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
f8a9f720 2879 "-" TARGET_FMT_plx "%s\n",
b31f8412 2880 cur_start, cur_end,
4b474ba7 2881 mr->priority,
4e831901 2882 memory_region_type((MemoryRegion *)mr),
3fb18b4d
PC		 2883 memory_region_name(mr),
2884 memory_region_name(mr->alias),
314e2987 2885 mr->alias_offset,
4e831901 2886 mr->alias_offset + MR_SIZE(mr->size),
f8a9f720 2887 mr->enabled ? "" : " [disabled]");
314e2987 2888 } else {
4896d74b 2889 mon_printf(f,
4e831901 2890 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
b31f8412 2891 cur_start, cur_end,
4b474ba7 2892 mr->priority,
4e831901 2893 memory_region_type((MemoryRegion *)mr),
f8a9f720
GH		 2894 memory_region_name(mr),
2895 mr->enabled ? "" : " [disabled]");
314e2987 2896 }
9479c57a
JK		 2897
2898 QTAILQ_INIT(&submr_print_queue);
2899
314e2987 2900 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK		 2901 new_ml = g_new(MemoryRegionList, 1);
2902 new_ml->mr = submr;
a16878d2 2903 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK		 2904 if (new_ml->mr->addr < ml->mr->addr ||
2905 (new_ml->mr->addr == ml->mr->addr &&
2906 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 2907 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK		 2908 new_ml = NULL;
2909 break;
2910 }
2911 }
2912 if (new_ml) {
a16878d2 2913 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK		 2914 }
2915 }
2916
a16878d2 2917 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b31f8412 2918 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
9479c57a
JK		 2919 alias_print_queue);
2920 }
2921
a16878d2 2922 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 2923 g_free(ml);
314e2987
BS		 2924 }
2925}
2926
5e8fd947
AK		 2927struct FlatViewInfo {
2928 fprintf_function mon_printf;
2929 void *f;
2930 int counter;
2931 bool dispatch_tree;
2932};
2933
2934static void mtree_print_flatview(gpointer key, gpointer value,
2935 gpointer user_data)
57bb40c9 2936{
5e8fd947
AK		 2937 FlatView *view = key;
2938 GArray *fv_address_spaces = value;
2939 struct FlatViewInfo *fvi = user_data;
2940 fprintf_function p = fvi->mon_printf;
2941 void *f = fvi->f;
57bb40c9
PX		 2942 FlatRange *range = &view->ranges[0];
2943 MemoryRegion *mr;
2944 int n = view->nr;
5e8fd947
AK		 2945 int i;
2946 AddressSpace *as;
2947
2948 p(f, "FlatView #%d\n", fvi->counter);
2949 ++fvi->counter;
2950
2951 for (i = 0; i < fv_address_spaces->len; ++i) {
2952 as = g_array_index(fv_address_spaces, AddressSpace*, i);
2953 p(f, " AS \"%s\", root: %s", as->name, memory_region_name(as->root));
2954 if (as->root->alias) {
2955 p(f, ", alias %s", memory_region_name(as->root->alias));
2956 }
2957 p(f, "\n");
2958 }
2959
2960 p(f, " Root memory region: %s\n",
2961 view->root ? memory_region_name(view->root) : "(none)");
57bb40c9
PX		 2962
2963 if (n <= 0) {
5e8fd947 2964 p(f, MTREE_INDENT "No rendered FlatView\n\n");
57bb40c9
PX		 2965 return;
2966 }
2967
2968 while (n--) {
2969 mr = range->mr;
377a07aa
PB		 2970 if (range->offset_in_region) {
2971 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2972 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
2973 int128_get64(range->addr.start),
2974 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2975 mr->priority,
2976 range->readonly ? "rom" : memory_region_type(mr),
2977 memory_region_name(mr),
2978 range->offset_in_region);
2979 } else {
2980 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2981 TARGET_FMT_plx " (prio %d, %s): %s\n",
2982 int128_get64(range->addr.start),
2983 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2984 mr->priority,
2985 range->readonly ? "rom" : memory_region_type(mr),
2986 memory_region_name(mr));
2987 }
57bb40c9
PX		 2988 range++;
2989 }
2990
5e8fd947
AK		 2991#if !defined(CONFIG_USER_ONLY)
2992 if (fvi->dispatch_tree && view->root) {
2993 mtree_print_dispatch(p, f, view->dispatch, view->root);
2994 }
2995#endif
2996
2997 p(f, "\n");
2998}
2999
3000static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3001 gpointer user_data)
3002{
3003 FlatView *view = key;
3004 GArray *fv_address_spaces = value;
3005
3006 g_array_unref(fv_address_spaces);
57bb40c9 3007 flatview_unref(view);
5e8fd947
AK		 3008
3009 return true;
57bb40c9
PX		 3010}
3011
5e8fd947
AK		 3012void mtree_info(fprintf_function mon_printf, void *f, bool flatview,
3013 bool dispatch_tree)
314e2987
BS		 3014{
3015 MemoryRegionListHead ml_head;
3016 MemoryRegionList *ml, *ml2;
0d673e36 3017 AddressSpace *as;
314e2987 3018
57bb40c9 3019 if (flatview) {
5e8fd947
AK		 3020 FlatView *view;
3021 struct FlatViewInfo fvi = {
3022 .mon_printf = mon_printf,
3023 .f = f,
3024 .counter = 0,
3025 .dispatch_tree = dispatch_tree
3026 };
3027 GArray *fv_address_spaces;
3028 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3029
3030 /* Gather all FVs in one table */
57bb40c9 3031 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
5e8fd947
AK		 3032 view = address_space_get_flatview(as);
3033
3034 fv_address_spaces = g_hash_table_lookup(views, view);
3035 if (!fv_address_spaces) {
3036 fv_address_spaces = g_array_new(false, false, sizeof(as));
3037 g_hash_table_insert(views, view, fv_address_spaces);
3038 }
3039
3040 g_array_append_val(fv_address_spaces, as);
57bb40c9 3041 }
5e8fd947
AK		 3042
3043 /* Print */
3044 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3045
3046 /* Free */
3047 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3048 g_hash_table_unref(views);
3049
57bb40c9
PX		 3050 return;
3051 }
3052
314e2987
BS		 3053 QTAILQ_INIT(&ml_head);
3054
0d673e36 3055 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
e48816aa
GH		 3056 mon_printf(f, "address-space: %s\n", as->name);
3057 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
3058 mon_printf(f, "\n");
b9f9be88
BS		 3059 }
3060
314e2987 3061 /* print aliased regions */
a16878d2 3062 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
e48816aa
GH		 3063 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
3064 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
3065 mon_printf(f, "\n");
314e2987
BS		 3066 }
3067
a16878d2 3068 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 3069 g_free(ml);
314e2987 3070 }
314e2987 3071}
b4fefef9 3072
b08199c6
PM		 3073void memory_region_init_ram(MemoryRegion *mr,
3074 struct Object *owner,
3075 const char *name,
3076 uint64_t size,
3077 Error **errp)
3078{
3079 DeviceState *owner_dev;
3080 Error *err = NULL;
3081
3082 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3083 if (err) {
3084 error_propagate(errp, err);
3085 return;
3086 }
3087 /* This will assert if owner is neither NULL nor a DeviceState.
3088 * We only want the owner here for the purposes of defining a
3089 * unique name for migration. TODO: Ideally we should implement
3090 * a naming scheme for Objects which are not DeviceStates, in
3091 * which case we can relax this restriction.
3092 */
3093 owner_dev = DEVICE(owner);
3094 vmstate_register_ram(mr, owner_dev);
3095}
3096
3097void memory_region_init_rom(MemoryRegion *mr,
3098 struct Object *owner,
3099 const char *name,
3100 uint64_t size,
3101 Error **errp)
3102{
3103 DeviceState *owner_dev;
3104 Error *err = NULL;
3105
3106 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3107 if (err) {
3108 error_propagate(errp, err);
3109 return;
3110 }
3111 /* This will assert if owner is neither NULL nor a DeviceState.
3112 * We only want the owner here for the purposes of defining a
3113 * unique name for migration. TODO: Ideally we should implement
3114 * a naming scheme for Objects which are not DeviceStates, in
3115 * which case we can relax this restriction.
3116 */
3117 owner_dev = DEVICE(owner);
3118 vmstate_register_ram(mr, owner_dev);
3119}
3120
3121void memory_region_init_rom_device(MemoryRegion *mr,
3122 struct Object *owner,
3123 const MemoryRegionOps *ops,
3124 void *opaque,
3125 const char *name,
3126 uint64_t size,
3127 Error **errp)
3128{
3129 DeviceState *owner_dev;
3130 Error *err = NULL;
3131
3132 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3133 name, size, &err);
3134 if (err) {
3135 error_propagate(errp, err);
3136 return;
3137 }
3138 /* This will assert if owner is neither NULL nor a DeviceState.
3139 * We only want the owner here for the purposes of defining a
3140 * unique name for migration. TODO: Ideally we should implement
3141 * a naming scheme for Objects which are not DeviceStates, in
3142 * which case we can relax this restriction.
3143 */
3144 owner_dev = DEVICE(owner);
3145 vmstate_register_ram(mr, owner_dev);
3146}
3147
b4fefef9
PC		 3148static const TypeInfo memory_region_info = {
3149 .parent = TYPE_OBJECT,
3150 .name = TYPE_MEMORY_REGION,
3151 .instance_size = sizeof(MemoryRegion),
3152 .instance_init = memory_region_initfn,
3153 .instance_finalize = memory_region_finalize,
3154};
3155
3df9d748
AK		 3156static const TypeInfo iommu_memory_region_info = {
3157 .parent = TYPE_MEMORY_REGION,
3158 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 3159 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK		 3160 .instance_size = sizeof(IOMMUMemoryRegion),
3161 .instance_init = iommu_memory_region_initfn,
1221a474 3162 .abstract = true,
3df9d748
AK		 3163};
3164
b4fefef9
PC		 3165static void memory_register_types(void)
3166{
3167 type_register_static(&memory_region_info);
3df9d748 3168 type_register_static(&iommu_memory_region_info);
b4fefef9
PC		 3169}
3170
3171type_init(memory_register_types)
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