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memory: Rename mem_begin/mem_commit/mem_add helpers
[mirror_qemu.git] / memory.c
CommitLineData
093bc2cd
AK		 1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB		 12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
AK		 14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879
PB		 18#include "qemu-common.h"
19#include "cpu.h"
022c62cb
PB		 20#include "exec/memory.h"
21#include "exec/address-spaces.h"
22#include "exec/ioport.h"
409ddd01 23#include "qapi/visitor.h"
1de7afc9 24#include "qemu/bitops.h"
8c56c1a5 25#include "qemu/error-report.h"
2c9b15ca 26#include "qom/object.h"
0ab8ed18 27#include "trace-root.h"
093bc2cd 28
022c62cb 29#include "exec/memory-internal.h"
220c3ebd 30#include "exec/ram_addr.h"
8c56c1a5 31#include "sysemu/kvm.h"
e1c57ab8 32#include "sysemu/sysemu.h"
c9356746
FK		 33#include "hw/misc/mmio_interface.h"
34#include "hw/qdev-properties.h"
b08199c6 35#include "migration/vmstate.h"
67d95c15 36
d197063f
PB		 37//#define DEBUG_UNASSIGNED
38
22bde714
JK		 39static unsigned memory_region_transaction_depth;
40static bool memory_region_update_pending;
4dc56152 41static bool ioeventfd_update_pending;
7664e80c
AK		 42static bool global_dirty_log = false;
43
72e22d2f
AK		 44static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
45 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 46
0d673e36
AK		 47static QTAILQ_HEAD(, AddressSpace) address_spaces
48 = QTAILQ_HEAD_INITIALIZER(address_spaces);
49
093bc2cd
AK		 50typedef struct AddrRange AddrRange;
51
8417cebf 52/*
c9cdaa3a 53 * Note that signed integers are needed for negative offsetting in aliases
8417cebf
AK		 54 * (large MemoryRegion::alias_offset).
55 */
093bc2cd 56struct AddrRange {
08dafab4
AK		 57 Int128 start;
58 Int128 size;
093bc2cd
AK		 59};
60
08dafab4 61static AddrRange addrrange_make(Int128 start, Int128 size)
093bc2cd
AK		 62{
63 return (AddrRange) { start, size };
64}
65
66static bool addrrange_equal(AddrRange r1, AddrRange r2)
67{
08dafab4 68 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
093bc2cd
AK		 69}
70
08dafab4 71static Int128 addrrange_end(AddrRange r)
093bc2cd 72{
08dafab4 73 return int128_add(r.start, r.size);
093bc2cd
AK		 74}
75
08dafab4 76static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 77{
08dafab4 78 int128_addto(&range.start, delta);
093bc2cd
AK		 79 return range;
80}
81
08dafab4
AK		 82static bool addrrange_contains(AddrRange range, Int128 addr)
83{
84 return int128_ge(addr, range.start)
85 && int128_lt(addr, addrrange_end(range));
86}
87
093bc2cd
AK		 88static bool addrrange_intersects(AddrRange r1, AddrRange r2)
89{
08dafab4
AK		 90 return addrrange_contains(r1, r2.start)
91 || addrrange_contains(r2, r1.start);
093bc2cd
AK		 92}
93
94static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
95{
08dafab4
AK		 96 Int128 start = int128_max(r1.start, r2.start);
97 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
98 return addrrange_make(start, int128_sub(end, start));
093bc2cd
AK		 99}
100
0e0d36b4
AK		 101enum ListenerDirection { Forward, Reverse };
102
7376e582 103#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
AK		 104 do { \
105 MemoryListener *_listener; \
106 \
107 switch (_direction) { \
108 case Forward: \
109 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
AK		 110 if (_listener->_callback) { \
111 _listener->_callback(_listener, ##_args); \
112 } \
0e0d36b4
AK		 113 } \
114 break; \
115 case Reverse: \
116 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
117 memory_listeners, link) { \
975aefe0
AK		 118 if (_listener->_callback) { \
119 _listener->_callback(_listener, ##_args); \
120 } \
0e0d36b4
AK		 121 } \
122 break; \
123 default: \
124 abort(); \
125 } \
126 } while (0)
127
9a54635d 128#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
7376e582
AK		 129 do { \
130 MemoryListener *_listener; \
9a54635d 131 struct memory_listeners_as *list = &(_as)->listeners; \
7376e582
AK		 132 \
133 switch (_direction) { \
134 case Forward: \
9a54635d
PB		 135 QTAILQ_FOREACH(_listener, list, link_as) { \
136 if (_listener->_callback) { \
7376e582
AK		 137 _listener->_callback(_listener, _section, ##_args); \
138 } \
139 } \
140 break; \
141 case Reverse: \
9a54635d
PB		 142 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
143 link_as) { \
144 if (_listener->_callback) { \
7376e582
AK		 145 _listener->_callback(_listener, _section, ##_args); \
146 } \
147 } \
148 break; \
149 default: \
150 abort(); \
151 } \
152 } while (0)
153
dfde4e6e 154/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 155#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44 156 do { \
16620684
AK		 157 MemoryRegionSection mrs = section_from_flat_range(fr, \
158 address_space_to_flatview(as)); \
9a54635d 159 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 160 } while(0)
0e0d36b4 161
093bc2cd
AK		 162struct CoalescedMemoryRange {
163 AddrRange addr;
164 QTAILQ_ENTRY(CoalescedMemoryRange) link;
165};
166
3e9d69e7
AK		 167struct MemoryRegionIoeventfd {
168 AddrRange addr;
169 bool match_data;
170 uint64_t data;
753d5e14 171 EventNotifier *e;
3e9d69e7
AK		 172};
173
174static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
175 MemoryRegionIoeventfd b)
176{
08dafab4 177 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 178 return true;
08dafab4 179 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 180 return false;
08dafab4 181 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 182 return true;
08dafab4 183 } else if (int128_gt(a.addr.size, b.addr.size)) {
3e9d69e7
AK		 184 return false;
185 } else if (a.match_data < b.match_data) {
186 return true;
187 } else if (a.match_data > b.match_data) {
188 return false;
189 } else if (a.match_data) {
190 if (a.data < b.data) {
191 return true;
192 } else if (a.data > b.data) {
193 return false;
194 }
195 }
753d5e14 196 if (a.e < b.e) {
3e9d69e7 197 return true;
753d5e14 198 } else if (a.e > b.e) {
3e9d69e7
AK		 199 return false;
200 }
201 return false;
202}
203
204static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
205 MemoryRegionIoeventfd b)
206{
207 return !memory_region_ioeventfd_before(a, b)
208 && !memory_region_ioeventfd_before(b, a);
209}
210
093bc2cd 211typedef struct FlatRange FlatRange;
093bc2cd
AK		 212
213/* Range of memory in the global map. Addresses are absolute. */
214struct FlatRange {
215 MemoryRegion *mr;
a8170e5e 216 hwaddr offset_in_region;
093bc2cd 217 AddrRange addr;
5a583347 218 uint8_t dirty_log_mask;
b138e654 219 bool romd_mode;
fb1cd6f9 220 bool readonly;
093bc2cd
AK		 221};
222
223/* Flattened global view of current active memory hierarchy. Kept in sorted
224 * order.
225 */
226struct FlatView {
374f2981 227 struct rcu_head rcu;
856d7245 228 unsigned ref;
093bc2cd
AK		 229 FlatRange *ranges;
230 unsigned nr;
231 unsigned nr_allocated;
66a6df1d 232 struct AddressSpaceDispatch *dispatch;
093bc2cd
AK		 233};
234
cc31e6e7
AK		 235typedef struct AddressSpaceOps AddressSpaceOps;
236
093bc2cd
AK		 237#define FOR_EACH_FLAT_RANGE(var, view) \
238 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
239
9c1f8f44 240static inline MemoryRegionSection
16620684 241section_from_flat_range(FlatRange *fr, FlatView *fv)
9c1f8f44
PB		 242{
243 return (MemoryRegionSection) {
244 .mr = fr->mr,
16620684 245 .fv = fv,
9c1f8f44
PB		 246 .offset_within_region = fr->offset_in_region,
247 .size = fr->addr.size,
248 .offset_within_address_space = int128_get64(fr->addr.start),
249 .readonly = fr->readonly,
250 };
251}
252
093bc2cd
AK		 253static bool flatrange_equal(FlatRange *a, FlatRange *b)
254{
255 return a->mr == b->mr
256 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 257 && a->offset_in_region == b->offset_in_region
b138e654 258 && a->romd_mode == b->romd_mode
fb1cd6f9 259 && a->readonly == b->readonly;
093bc2cd
AK		 260}
261
cc94cd6d 262static FlatView *flatview_new(void)
093bc2cd 263{
cc94cd6d
AK		 264 FlatView *view;
265
266 view = g_new0(FlatView, 1);
856d7245 267 view->ref = 1;
cc94cd6d
AK		 268
269 return view;
093bc2cd
AK		 270}
271
272/* Insert a range into a given position. Caller is responsible for maintaining
273 * sorting order.
274 */
275static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
276{
277 if (view->nr == view->nr_allocated) {
278 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 279 view->ranges = g_realloc(view->ranges,
093bc2cd
AK		 280 view->nr_allocated * sizeof(*view->ranges));
281 }
282 memmove(view->ranges + pos + 1, view->ranges + pos,
283 (view->nr - pos) * sizeof(FlatRange));
284 view->ranges[pos] = *range;
dfde4e6e 285 memory_region_ref(range->mr);
093bc2cd
AK		 286 ++view->nr;
287}
288
289static void flatview_destroy(FlatView *view)
290{
dfde4e6e
PB		 291 int i;
292
66a6df1d
AK		 293 if (view->dispatch) {
294 address_space_dispatch_free(view->dispatch);
295 }
dfde4e6e
PB		 296 for (i = 0; i < view->nr; i++) {
297 memory_region_unref(view->ranges[i].mr);
298 }
7267c094 299 g_free(view->ranges);
a9a0c06d 300 g_free(view);
093bc2cd
AK		 301}
302
447b0d0b 303static bool flatview_ref(FlatView *view)
856d7245 304{
447b0d0b 305 return atomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB		 306}
307
308static void flatview_unref(FlatView *view)
309{
310 if (atomic_fetch_dec(&view->ref) == 1) {
66a6df1d 311 call_rcu(view, flatview_destroy, rcu);
856d7245
PB		 312 }
313}
314
16620684 315FlatView *address_space_to_flatview(AddressSpace *as)
66a6df1d
AK		 316{
317 return atomic_rcu_read(&as->current_map);
318}
319
320AddressSpaceDispatch *flatview_to_dispatch(FlatView *fv)
321{
322 return fv->dispatch;
323}
324
325AddressSpaceDispatch *address_space_to_dispatch(AddressSpace *as)
326{
327 return flatview_to_dispatch(address_space_to_flatview(as));
328}
329
3d8e6bf9
AK		 330static bool can_merge(FlatRange *r1, FlatRange *r2)
331{
08dafab4 332 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 333 && r1->mr == r2->mr
08dafab4
AK		 334 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
335 r1->addr.size),
336 int128_make64(r2->offset_in_region))
d0a9b5bc 337 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 338 && r1->romd_mode == r2->romd_mode
fb1cd6f9 339 && r1->readonly == r2->readonly;
3d8e6bf9
AK		 340}
341
8508e024 342/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK		 343static void flatview_simplify(FlatView *view)
344{
345 unsigned i, j;
346
347 i = 0;
348 while (i < view->nr) {
349 j = i + 1;
350 while (j < view->nr
351 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 352 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
AK		 353 ++j;
354 }
355 ++i;
356 memmove(&view->ranges[i], &view->ranges[j],
357 (view->nr - j) * sizeof(view->ranges[j]));
358 view->nr -= j - i;
359 }
360}
361
e7342aa3
PB		 362static bool memory_region_big_endian(MemoryRegion *mr)
363{
364#ifdef TARGET_WORDS_BIGENDIAN
365 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
366#else
367 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
368#endif
369}
370
e11ef3d1
PB		 371static bool memory_region_wrong_endianness(MemoryRegion *mr)
372{
373#ifdef TARGET_WORDS_BIGENDIAN
374 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
375#else
376 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
377#endif
378}
379
380static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
381{
382 if (memory_region_wrong_endianness(mr)) {
383 switch (size) {
384 case 1:
385 break;
386 case 2:
387 *data = bswap16(*data);
388 break;
389 case 4:
390 *data = bswap32(*data);
391 break;
392 case 8:
393 *data = bswap64(*data);
394 break;
395 default:
396 abort();
397 }
398 }
399}
400
4779dc1d
HB		 401static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
402{
403 MemoryRegion *root;
404 hwaddr abs_addr = offset;
405
406 abs_addr += mr->addr;
407 for (root = mr; root->container; ) {
408 root = root->container;
409 abs_addr += root->addr;
410 }
411
412 return abs_addr;
413}
414
5a68be94
HB		 415static int get_cpu_index(void)
416{
417 if (current_cpu) {
418 return current_cpu->cpu_index;
419 }
420 return -1;
421}
422
cc05c43a
PM		 423static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
424 hwaddr addr,
425 uint64_t *value,
426 unsigned size,
427 unsigned shift,
428 uint64_t mask,
429 MemTxAttrs attrs)
430{
431 uint64_t tmp;
432
433 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
23d92d68 434 if (mr->subpage) {
5a68be94 435 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 436 } else if (mr == &io_mem_notdirty) {
437 /* Accesses to code which has previously been translated into a TB show
438 * up in the MMIO path, as accesses to the io_mem_notdirty
439 * MemoryRegion. */
440 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 441 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
442 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 443 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 444 }
cc05c43a
PM		 445 *value |= (tmp & mask) << shift;
446 return MEMTX_OK;
447}
448
449static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB		 450 hwaddr addr,
451 uint64_t *value,
452 unsigned size,
453 unsigned shift,
cc05c43a
PM		 454 uint64_t mask,
455 MemTxAttrs attrs)
ce5d2f33 456{
ce5d2f33
PB		 457 uint64_t tmp;
458
cc05c43a 459 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 460 if (mr->subpage) {
5a68be94 461 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 462 } else if (mr == &io_mem_notdirty) {
463 /* Accesses to code which has previously been translated into a TB show
464 * up in the MMIO path, as accesses to the io_mem_notdirty
465 * MemoryRegion. */
466 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 467 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
468 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 469 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 470 }
ce5d2f33 471 *value |= (tmp & mask) << shift;
cc05c43a 472 return MEMTX_OK;
ce5d2f33
PB		 473}
474
cc05c43a
PM		 475static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
476 hwaddr addr,
477 uint64_t *value,
478 unsigned size,
479 unsigned shift,
480 uint64_t mask,
481 MemTxAttrs attrs)
164a4dcd 482{
cc05c43a
PM		 483 uint64_t tmp = 0;
484 MemTxResult r;
164a4dcd 485
cc05c43a 486 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 487 if (mr->subpage) {
5a68be94 488 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 489 } else if (mr == &io_mem_notdirty) {
490 /* Accesses to code which has previously been translated into a TB show
491 * up in the MMIO path, as accesses to the io_mem_notdirty
492 * MemoryRegion. */
493 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 494 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
495 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 496 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 497 }
164a4dcd 498 *value |= (tmp & mask) << shift;
cc05c43a 499 return r;
164a4dcd
AK		 500}
501
cc05c43a
PM		 502static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
503 hwaddr addr,
504 uint64_t *value,
505 unsigned size,
506 unsigned shift,
507 uint64_t mask,
508 MemTxAttrs attrs)
ce5d2f33 509{
ce5d2f33
PB		 510 uint64_t tmp;
511
512 tmp = (*value >> shift) & mask;
23d92d68 513 if (mr->subpage) {
5a68be94 514 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 515 } else if (mr == &io_mem_notdirty) {
516 /* Accesses to code which has previously been translated into a TB show
517 * up in the MMIO path, as accesses to the io_mem_notdirty
518 * MemoryRegion. */
519 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 520 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
521 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 522 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 523 }
ce5d2f33 524 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
cc05c43a 525 return MEMTX_OK;
ce5d2f33
PB		 526}
527
cc05c43a
PM		 528static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
529 hwaddr addr,
530 uint64_t *value,
531 unsigned size,
532 unsigned shift,
533 uint64_t mask,
534 MemTxAttrs attrs)
164a4dcd 535{
164a4dcd
AK		 536 uint64_t tmp;
537
538 tmp = (*value >> shift) & mask;
23d92d68 539 if (mr->subpage) {
5a68be94 540 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 541 } else if (mr == &io_mem_notdirty) {
542 /* Accesses to code which has previously been translated into a TB show
543 * up in the MMIO path, as accesses to the io_mem_notdirty
544 * MemoryRegion. */
545 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 546 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
547 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 548 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 549 }
164a4dcd 550 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 551 return MEMTX_OK;
164a4dcd
AK		 552}
553
cc05c43a
PM		 554static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
555 hwaddr addr,
556 uint64_t *value,
557 unsigned size,
558 unsigned shift,
559 uint64_t mask,
560 MemTxAttrs attrs)
561{
562 uint64_t tmp;
563
cc05c43a 564 tmp = (*value >> shift) & mask;
23d92d68 565 if (mr->subpage) {
5a68be94 566 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 567 } else if (mr == &io_mem_notdirty) {
568 /* Accesses to code which has previously been translated into a TB show
569 * up in the MMIO path, as accesses to the io_mem_notdirty
570 * MemoryRegion. */
571 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 572 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
573 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 574 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 575 }
cc05c43a
PM		 576 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
577}
578
579static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK		 580 uint64_t *value,
581 unsigned size,
582 unsigned access_size_min,
583 unsigned access_size_max,
05e015f7
KF		 584 MemTxResult (*access_fn)
585 (MemoryRegion *mr,
586 hwaddr addr,
587 uint64_t *value,
588 unsigned size,
589 unsigned shift,
590 uint64_t mask,
591 MemTxAttrs attrs),
cc05c43a
PM		 592 MemoryRegion *mr,
593 MemTxAttrs attrs)
164a4dcd
AK		 594{
595 uint64_t access_mask;
596 unsigned access_size;
597 unsigned i;
cc05c43a 598 MemTxResult r = MEMTX_OK;
164a4dcd
AK		 599
600 if (!access_size_min) {
601 access_size_min = 1;
602 }
603 if (!access_size_max) {
604 access_size_max = 4;
605 }
ce5d2f33
PB		 606
607 /* FIXME: support unaligned access? */
164a4dcd
AK		 608 access_size = MAX(MIN(size, access_size_max), access_size_min);
609 access_mask = -1ULL >> (64 - access_size * 8);
e7342aa3
PB		 610 if (memory_region_big_endian(mr)) {
611 for (i = 0; i < size; i += access_size) {
05e015f7 612 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 613 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB		 614 }
615 } else {
616 for (i = 0; i < size; i += access_size) {
05e015f7 617 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 618 access_mask, attrs);
e7342aa3 619 }
164a4dcd 620 }
cc05c43a 621 return r;
164a4dcd
AK		 622}
623
e2177955
AK		 624static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
625{
0d673e36
AK		 626 AddressSpace *as;
627
feca4ac1
PB		 628 while (mr->container) {
629 mr = mr->container;
e2177955 630 }
0d673e36
AK		 631 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
632 if (mr == as->root) {
633 return as;
634 }
e2177955 635 }
eed2bacf 636 return NULL;
e2177955
AK		 637}
638
093bc2cd
AK		 639/* Render a memory region into the global view. Ranges in @view obscure
640 * ranges in @mr.
641 */
642static void render_memory_region(FlatView *view,
643 MemoryRegion *mr,
08dafab4 644 Int128 base,
fb1cd6f9
AK		 645 AddrRange clip,
646 bool readonly)
093bc2cd
AK		 647{
648 MemoryRegion *subregion;
649 unsigned i;
a8170e5e 650 hwaddr offset_in_region;
08dafab4
AK		 651 Int128 remain;
652 Int128 now;
093bc2cd
AK		 653 FlatRange fr;
654 AddrRange tmp;
655
6bba19ba
AK		 656 if (!mr->enabled) {
657 return;
658 }
659
08dafab4 660 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 661 readonly |= mr->readonly;
093bc2cd
AK		 662
663 tmp = addrrange_make(base, mr->size);
664
665 if (!addrrange_intersects(tmp, clip)) {
666 return;
667 }
668
669 clip = addrrange_intersection(tmp, clip);
670
671 if (mr->alias) {
08dafab4
AK		 672 int128_subfrom(&base, int128_make64(mr->alias->addr));
673 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 674 render_memory_region(view, mr->alias, base, clip, readonly);
093bc2cd
AK		 675 return;
676 }
677
678 /* Render subregions in priority order. */
679 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 680 render_memory_region(view, subregion, base, clip, readonly);
093bc2cd
AK		 681 }
682
14a3c10a 683 if (!mr->terminates) {
093bc2cd
AK		 684 return;
685 }
686
08dafab4 687 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK		 688 base = clip.start;
689 remain = clip.size;
690
2eb74e1a 691 fr.mr = mr;
6f6a5ef3 692 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 693 fr.romd_mode = mr->romd_mode;
2eb74e1a
PC		 694 fr.readonly = readonly;
695
093bc2cd 696 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK		 697 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
698 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK		 699 continue;
700 }
08dafab4
AK		 701 if (int128_lt(base, view->ranges[i].addr.start)) {
702 now = int128_min(remain,
703 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK		 704 fr.offset_in_region = offset_in_region;
705 fr.addr = addrrange_make(base, now);
706 flatview_insert(view, i, &fr);
707 ++i;
08dafab4
AK		 708 int128_addto(&base, now);
709 offset_in_region += int128_get64(now);
710 int128_subfrom(&remain, now);
093bc2cd 711 }
d26a8cae
AK		 712 now = int128_sub(int128_min(int128_add(base, remain),
713 addrrange_end(view->ranges[i].addr)),
714 base);
715 int128_addto(&base, now);
716 offset_in_region += int128_get64(now);
717 int128_subfrom(&remain, now);
093bc2cd 718 }
08dafab4 719 if (int128_nz(remain)) {
093bc2cd
AK		 720 fr.offset_in_region = offset_in_region;
721 fr.addr = addrrange_make(base, remain);
722 flatview_insert(view, i, &fr);
723 }
724}
725
726/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 727static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 728{
a9a0c06d 729 FlatView *view;
093bc2cd 730
cc94cd6d 731 view = flatview_new();
093bc2cd 732
83f3c251 733 if (mr) {
a9a0c06d 734 render_memory_region(view, mr, int128_zero(),
83f3c251
AK		 735 addrrange_make(int128_zero(), int128_2_64()), false);
736 }
a9a0c06d 737 flatview_simplify(view);
093bc2cd
AK		 738
739 return view;
740}
741
3e9d69e7
AK		 742static void address_space_add_del_ioeventfds(AddressSpace *as,
743 MemoryRegionIoeventfd *fds_new,
744 unsigned fds_new_nb,
745 MemoryRegionIoeventfd *fds_old,
746 unsigned fds_old_nb)
747{
748 unsigned iold, inew;
80a1ea37
AK		 749 MemoryRegionIoeventfd *fd;
750 MemoryRegionSection section;
3e9d69e7
AK		 751
752 /* Generate a symmetric difference of the old and new fd sets, adding
753 * and deleting as necessary.
754 */
755
756 iold = inew = 0;
757 while (iold < fds_old_nb || inew < fds_new_nb) {
758 if (iold < fds_old_nb
759 && (inew == fds_new_nb
760 || memory_region_ioeventfd_before(fds_old[iold],
761 fds_new[inew]))) {
80a1ea37
AK		 762 fd = &fds_old[iold];
763 section = (MemoryRegionSection) {
16620684 764 .fv = address_space_to_flatview(as),
80a1ea37 765 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 766 .size = fd->addr.size,
80a1ea37 767 };
9a54635d 768 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 769 fd->match_data, fd->data, fd->e);
3e9d69e7
AK		 770 ++iold;
771 } else if (inew < fds_new_nb
772 && (iold == fds_old_nb
773 || memory_region_ioeventfd_before(fds_new[inew],
774 fds_old[iold]))) {
80a1ea37
AK		 775 fd = &fds_new[inew];
776 section = (MemoryRegionSection) {
16620684 777 .fv = address_space_to_flatview(as),
80a1ea37 778 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 779 .size = fd->addr.size,
80a1ea37 780 };
9a54635d 781 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 782 fd->match_data, fd->data, fd->e);
3e9d69e7
AK		 783 ++inew;
784 } else {
785 ++iold;
786 ++inew;
787 }
788 }
789}
790
856d7245
PB		 791static FlatView *address_space_get_flatview(AddressSpace *as)
792{
793 FlatView *view;
794
374f2981 795 rcu_read_lock();
447b0d0b 796 do {
16620684 797 view = address_space_to_flatview(as);
447b0d0b
PB		 798 /* If somebody has replaced as->current_map concurrently,
799 * flatview_ref returns false.
800 */
801 } while (!flatview_ref(view));
374f2981 802 rcu_read_unlock();
856d7245
PB		 803 return view;
804}
805
3e9d69e7
AK		 806static void address_space_update_ioeventfds(AddressSpace *as)
807{
99e86347 808 FlatView *view;
3e9d69e7
AK		 809 FlatRange *fr;
810 unsigned ioeventfd_nb = 0;
811 MemoryRegionIoeventfd *ioeventfds = NULL;
812 AddrRange tmp;
813 unsigned i;
814
856d7245 815 view = address_space_get_flatview(as);
99e86347 816 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK		 817 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
818 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK		 819 int128_sub(fr->addr.start,
820 int128_make64(fr->offset_in_region)));
3e9d69e7
AK		 821 if (addrrange_intersects(fr->addr, tmp)) {
822 ++ioeventfd_nb;
7267c094 823 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK		 824 ioeventfd_nb * sizeof(*ioeventfds));
825 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
826 ioeventfds[ioeventfd_nb-1].addr = tmp;
827 }
828 }
829 }
830
831 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
832 as->ioeventfds, as->ioeventfd_nb);
833
7267c094 834 g_free(as->ioeventfds);
3e9d69e7
AK		 835 as->ioeventfds = ioeventfds;
836 as->ioeventfd_nb = ioeventfd_nb;
856d7245 837 flatview_unref(view);
3e9d69e7
AK		 838}
839
b8af1afb 840static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB		 841 const FlatView *old_view,
842 const FlatView *new_view,
b8af1afb 843 bool adding)
093bc2cd 844{
093bc2cd
AK		 845 unsigned iold, inew;
846 FlatRange *frold, *frnew;
093bc2cd
AK		 847
848 /* Generate a symmetric difference of the old and new memory maps.
849 * Kill ranges in the old map, and instantiate ranges in the new map.
850 */
851 iold = inew = 0;
a9a0c06d
PB		 852 while (iold < old_view->nr || inew < new_view->nr) {
853 if (iold < old_view->nr) {
854 frold = &old_view->ranges[iold];
093bc2cd
AK		 855 } else {
856 frold = NULL;
857 }
a9a0c06d
PB		 858 if (inew < new_view->nr) {
859 frnew = &new_view->ranges[inew];
093bc2cd
AK		 860 } else {
861 frnew = NULL;
862 }
863
864 if (frold
865 && (!frnew
08dafab4
AK		 866 || int128_lt(frold->addr.start, frnew->addr.start)
867 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 868 && !flatrange_equal(frold, frnew)))) {
41a6e477 869 /* In old but not in new, or in both but attributes changed. */
093bc2cd 870
b8af1afb 871 if (!adding) {
72e22d2f 872 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK		 873 }
874
093bc2cd
AK		 875 ++iold;
876 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 877 /* In both and unchanged (except logging may have changed) */
093bc2cd 878
b8af1afb 879 if (adding) {
50c1e149 880 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB		 881 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
882 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
883 frold->dirty_log_mask,
884 frnew->dirty_log_mask);
885 }
886 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
887 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
888 frold->dirty_log_mask,
889 frnew->dirty_log_mask);
b8af1afb 890 }
5a583347
AK		 891 }
892
093bc2cd
AK		 893 ++iold;
894 ++inew;
093bc2cd
AK		 895 } else {
896 /* In new */
897
b8af1afb 898 if (adding) {
72e22d2f 899 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK		 900 }
901
093bc2cd
AK		 902 ++inew;
903 }
904 }
b8af1afb
AK		 905}
906
b8af1afb
AK		 907static void address_space_update_topology(AddressSpace *as)
908{
856d7245 909 FlatView *old_view = address_space_get_flatview(as);
a9a0c06d 910 FlatView *new_view = generate_memory_topology(as->root);
9a62e24f 911 int i;
b8af1afb 912
8629d3fc 913 new_view->dispatch = address_space_dispatch_new(new_view);
9a62e24f
AK		 914 for (i = 0; i < new_view->nr; i++) {
915 MemoryRegionSection mrs =
16620684 916 section_from_flat_range(&new_view->ranges[i], new_view);
8629d3fc 917 flatview_add_to_dispatch(new_view, &mrs);
9a62e24f 918 }
8629d3fc 919 address_space_dispatch_compact(new_view->dispatch);
9a62e24f
AK		 920
921 if (!QTAILQ_EMPTY(&as->listeners)) {
922 address_space_update_topology_pass(as, old_view, new_view, false);
923 address_space_update_topology_pass(as, old_view, new_view, true);
924 }
b8af1afb 925
374f2981
PB		 926 /* Writes are protected by the BQL. */
927 atomic_rcu_set(&as->current_map, new_view);
66a6df1d 928 flatview_unref(old_view);
856d7245
PB		 929
930 /* Note that all the old MemoryRegions are still alive up to this
931 * point. This relieves most MemoryListeners from the need to
932 * ref/unref the MemoryRegions they get---unless they use them
933 * outside the iothread mutex, in which case precise reference
934 * counting is necessary.
935 */
936 flatview_unref(old_view);
937
3e9d69e7 938 address_space_update_ioeventfds(as);
093bc2cd
AK		 939}
940
4ef4db86
AK		 941void memory_region_transaction_begin(void)
942{
bb880ded 943 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK		 944 ++memory_region_transaction_depth;
945}
946
947void memory_region_transaction_commit(void)
948{
0d673e36
AK		 949 AddressSpace *as;
950
4ef4db86 951 assert(memory_region_transaction_depth);
8d04fb55
JK		 952 assert(qemu_mutex_iothread_locked());
953
4ef4db86 954 --memory_region_transaction_depth;
4dc56152
GA		 955 if (!memory_region_transaction_depth) {
956 if (memory_region_update_pending) {
957 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 958
4dc56152
GA		 959 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
960 address_space_update_topology(as);
961 }
ade9c1aa 962 memory_region_update_pending = false;
4dc56152
GA		 963 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
964 } else if (ioeventfd_update_pending) {
965 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
966 address_space_update_ioeventfds(as);
967 }
ade9c1aa 968 ioeventfd_update_pending = false;
4dc56152 969 }
4dc56152 970 }
4ef4db86
AK		 971}
972
545e92e0
AK		 973static void memory_region_destructor_none(MemoryRegion *mr)
974{
975}
976
977static void memory_region_destructor_ram(MemoryRegion *mr)
978{
f1060c55 979 qemu_ram_free(mr->ram_block);
545e92e0
AK		 980}
981
b4fefef9
PC		 982static bool memory_region_need_escape(char c)
983{
984 return c == '/' || c == '[' || c == '\\' || c == ']';
985}
986
987static char *memory_region_escape_name(const char *name)
988{
989 const char *p;
990 char *escaped, *q;
991 uint8_t c;
992 size_t bytes = 0;
993
994 for (p = name; *p; p++) {
995 bytes += memory_region_need_escape(*p) ? 4 : 1;
996 }
997 if (bytes == p - name) {
998 return g_memdup(name, bytes + 1);
999 }
1000
1001 escaped = g_malloc(bytes + 1);
1002 for (p = name, q = escaped; *p; p++) {
1003 c = *p;
1004 if (unlikely(memory_region_need_escape(c))) {
1005 *q++ = '\\';
1006 *q++ = 'x';
1007 *q++ = "0123456789abcdef"[c >> 4];
1008 c = "0123456789abcdef"[c & 15];
1009 }
1010 *q++ = c;
1011 }
1012 *q = 0;
1013 return escaped;
1014}
1015
3df9d748
AK		 1016static void memory_region_do_init(MemoryRegion *mr,
1017 Object *owner,
1018 const char *name,
1019 uint64_t size)
093bc2cd 1020{
08dafab4
AK		 1021 mr->size = int128_make64(size);
1022 if (size == UINT64_MAX) {
1023 mr->size = int128_2_64();
1024 }
302fa283 1025 mr->name = g_strdup(name);
612263cf 1026 mr->owner = owner;
58eaa217 1027 mr->ram_block = NULL;
b4fefef9
PC		 1028
1029 if (name) {
843ef73a
PC		 1030 char *escaped_name = memory_region_escape_name(name);
1031 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB		 1032
1033 if (!owner) {
1034 owner = container_get(qdev_get_machine(), "/unattached");
1035 }
1036
843ef73a 1037 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1038 object_unref(OBJECT(mr));
843ef73a
PC		 1039 g_free(name_array);
1040 g_free(escaped_name);
b4fefef9
PC		 1041 }
1042}
1043
3df9d748
AK		 1044void memory_region_init(MemoryRegion *mr,
1045 Object *owner,
1046 const char *name,
1047 uint64_t size)
1048{
1049 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1050 memory_region_do_init(mr, owner, name, size);
1051}
1052
d7bce999
EB		 1053static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1054 void *opaque, Error **errp)
409ddd01
PC		 1055{
1056 MemoryRegion *mr = MEMORY_REGION(obj);
1057 uint64_t value = mr->addr;
1058
51e72bc1 1059 visit_type_uint64(v, name, &value, errp);
409ddd01
PC		 1060}
1061
d7bce999
EB		 1062static void memory_region_get_container(Object *obj, Visitor *v,
1063 const char *name, void *opaque,
1064 Error **errp)
409ddd01
PC		 1065{
1066 MemoryRegion *mr = MEMORY_REGION(obj);
1067 gchar *path = (gchar *)"";
1068
1069 if (mr->container) {
1070 path = object_get_canonical_path(OBJECT(mr->container));
1071 }
51e72bc1 1072 visit_type_str(v, name, &path, errp);
409ddd01
PC		 1073 if (mr->container) {
1074 g_free(path);
1075 }
1076}
1077
1078static Object *memory_region_resolve_container(Object *obj, void *opaque,
1079 const char *part)
1080{
1081 MemoryRegion *mr = MEMORY_REGION(obj);
1082
1083 return OBJECT(mr->container);
1084}
1085
d7bce999
EB		 1086static void memory_region_get_priority(Object *obj, Visitor *v,
1087 const char *name, void *opaque,
1088 Error **errp)
d33382da
PC		 1089{
1090 MemoryRegion *mr = MEMORY_REGION(obj);
1091 int32_t value = mr->priority;
1092
51e72bc1 1093 visit_type_int32(v, name, &value, errp);
d33382da
PC		 1094}
1095
d7bce999
EB		 1096static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1097 void *opaque, Error **errp)
52aef7bb
PC		 1098{
1099 MemoryRegion *mr = MEMORY_REGION(obj);
1100 uint64_t value = memory_region_size(mr);
1101
51e72bc1 1102 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC		 1103}
1104
b4fefef9
PC		 1105static void memory_region_initfn(Object *obj)
1106{
1107 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1108 ObjectProperty *op;
b4fefef9
PC		 1109
1110 mr->ops = &unassigned_mem_ops;
6bba19ba 1111 mr->enabled = true;
5f9a5ea1 1112 mr->romd_mode = true;
196ea131 1113 mr->global_locking = true;
545e92e0 1114 mr->destructor = memory_region_destructor_none;
093bc2cd 1115 QTAILQ_INIT(&mr->subregions);
093bc2cd 1116 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC		 1117
1118 op = object_property_add(OBJECT(mr), "container",
1119 "link<" TYPE_MEMORY_REGION ">",
1120 memory_region_get_container,
1121 NULL, /* memory_region_set_container */
1122 NULL, NULL, &error_abort);
1123 op->resolve = memory_region_resolve_container;
1124
1125 object_property_add(OBJECT(mr), "addr", "uint64",
1126 memory_region_get_addr,
1127 NULL, /* memory_region_set_addr */
1128 NULL, NULL, &error_abort);
d33382da
PC		 1129 object_property_add(OBJECT(mr), "priority", "uint32",
1130 memory_region_get_priority,
1131 NULL, /* memory_region_set_priority */
1132 NULL, NULL, &error_abort);
52aef7bb
PC		 1133 object_property_add(OBJECT(mr), "size", "uint64",
1134 memory_region_get_size,
1135 NULL, /* memory_region_set_size, */
1136 NULL, NULL, &error_abort);
093bc2cd
AK		 1137}
1138
3df9d748
AK		 1139static void iommu_memory_region_initfn(Object *obj)
1140{
1141 MemoryRegion *mr = MEMORY_REGION(obj);
1142
1143 mr->is_iommu = true;
1144}
1145
b018ddf6
PB		 1146static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1147 unsigned size)
1148{
1149#ifdef DEBUG_UNASSIGNED
1150 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1151#endif
4917cf44
AF		 1152 if (current_cpu != NULL) {
1153 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
c658b94f 1154 }
68a7439a 1155 return 0;
b018ddf6
PB		 1156}
1157
1158static void unassigned_mem_write(void *opaque, hwaddr addr,
1159 uint64_t val, unsigned size)
1160{
1161#ifdef DEBUG_UNASSIGNED
1162 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1163#endif
4917cf44
AF		 1164 if (current_cpu != NULL) {
1165 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1166 }
b018ddf6
PB		 1167}
1168
d197063f
PB		 1169static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1170 unsigned size, bool is_write)
1171{
1172 return false;
1173}
1174
1175const MemoryRegionOps unassigned_mem_ops = {
1176 .valid.accepts = unassigned_mem_accepts,
1177 .endianness = DEVICE_NATIVE_ENDIAN,
1178};
1179
4a2e242b
AW		 1180static uint64_t memory_region_ram_device_read(void *opaque,
1181 hwaddr addr, unsigned size)
1182{
1183 MemoryRegion *mr = opaque;
1184 uint64_t data = (uint64_t)~0;
1185
1186 switch (size) {
1187 case 1:
1188 data = *(uint8_t *)(mr->ram_block->host + addr);
1189 break;
1190 case 2:
1191 data = *(uint16_t *)(mr->ram_block->host + addr);
1192 break;
1193 case 4:
1194 data = *(uint32_t *)(mr->ram_block->host + addr);
1195 break;
1196 case 8:
1197 data = *(uint64_t *)(mr->ram_block->host + addr);
1198 break;
1199 }
1200
1201 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1202
1203 return data;
1204}
1205
1206static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1207 uint64_t data, unsigned size)
1208{
1209 MemoryRegion *mr = opaque;
1210
1211 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1212
1213 switch (size) {
1214 case 1:
1215 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1216 break;
1217 case 2:
1218 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1219 break;
1220 case 4:
1221 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1222 break;
1223 case 8:
1224 *(uint64_t *)(mr->ram_block->host + addr) = data;
1225 break;
1226 }
1227}
1228
1229static const MemoryRegionOps ram_device_mem_ops = {
1230 .read = memory_region_ram_device_read,
1231 .write = memory_region_ram_device_write,
c99a29e7 1232 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW		 1233 .valid = {
1234 .min_access_size = 1,
1235 .max_access_size = 8,
1236 .unaligned = true,
1237 },
1238 .impl = {
1239 .min_access_size = 1,
1240 .max_access_size = 8,
1241 .unaligned = true,
1242 },
1243};
1244
d2702032
PB		 1245bool memory_region_access_valid(MemoryRegion *mr,
1246 hwaddr addr,
1247 unsigned size,
1248 bool is_write)
093bc2cd 1249{
a014ed07
PB		 1250 int access_size_min, access_size_max;
1251 int access_size, i;
897fa7cf 1252
093bc2cd
AK		 1253 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1254 return false;
1255 }
1256
a014ed07 1257 if (!mr->ops->valid.accepts) {
093bc2cd
AK		 1258 return true;
1259 }
1260
a014ed07
PB		 1261 access_size_min = mr->ops->valid.min_access_size;
1262 if (!mr->ops->valid.min_access_size) {
1263 access_size_min = 1;
1264 }
1265
1266 access_size_max = mr->ops->valid.max_access_size;
1267 if (!mr->ops->valid.max_access_size) {
1268 access_size_max = 4;
1269 }
1270
1271 access_size = MAX(MIN(size, access_size_max), access_size_min);
1272 for (i = 0; i < size; i += access_size) {
1273 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1274 is_write)) {
1275 return false;
1276 }
093bc2cd 1277 }
a014ed07 1278
093bc2cd
AK		 1279 return true;
1280}
1281
cc05c43a
PM		 1282static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1283 hwaddr addr,
1284 uint64_t *pval,
1285 unsigned size,
1286 MemTxAttrs attrs)
093bc2cd 1287{
cc05c43a 1288 *pval = 0;
093bc2cd 1289
ce5d2f33 1290 if (mr->ops->read) {
cc05c43a
PM		 1291 return access_with_adjusted_size(addr, pval, size,
1292 mr->ops->impl.min_access_size,
1293 mr->ops->impl.max_access_size,
1294 memory_region_read_accessor,
1295 mr, attrs);
1296 } else if (mr->ops->read_with_attrs) {
1297 return access_with_adjusted_size(addr, pval, size,
1298 mr->ops->impl.min_access_size,
1299 mr->ops->impl.max_access_size,
1300 memory_region_read_with_attrs_accessor,
1301 mr, attrs);
ce5d2f33 1302 } else {
cc05c43a
PM		 1303 return access_with_adjusted_size(addr, pval, size, 1, 4,
1304 memory_region_oldmmio_read_accessor,
1305 mr, attrs);
74901c3b 1306 }
093bc2cd
AK		 1307}
1308
3b643495
PM		 1309MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1310 hwaddr addr,
1311 uint64_t *pval,
1312 unsigned size,
1313 MemTxAttrs attrs)
a621f38d 1314{
cc05c43a
PM		 1315 MemTxResult r;
1316
791af8c8
PB		 1317 if (!memory_region_access_valid(mr, addr, size, false)) {
1318 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1319 return MEMTX_DECODE_ERROR;
791af8c8 1320 }
a621f38d 1321
cc05c43a 1322 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1323 adjust_endianness(mr, pval, size);
cc05c43a 1324 return r;
a621f38d 1325}
093bc2cd 1326
8c56c1a5
PF		 1327/* Return true if an eventfd was signalled */
1328static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1329 hwaddr addr,
1330 uint64_t data,
1331 unsigned size,
1332 MemTxAttrs attrs)
1333{
1334 MemoryRegionIoeventfd ioeventfd = {
1335 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1336 .data = data,
1337 };
1338 unsigned i;
1339
1340 for (i = 0; i < mr->ioeventfd_nb; i++) {
1341 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1342 ioeventfd.e = mr->ioeventfds[i].e;
1343
1344 if (memory_region_ioeventfd_equal(ioeventfd, mr->ioeventfds[i])) {
1345 event_notifier_set(ioeventfd.e);
1346 return true;
1347 }
1348 }
1349
1350 return false;
1351}
1352
3b643495
PM		 1353MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1354 hwaddr addr,
1355 uint64_t data,
1356 unsigned size,
1357 MemTxAttrs attrs)
a621f38d 1358{
897fa7cf 1359 if (!memory_region_access_valid(mr, addr, size, true)) {
b018ddf6 1360 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1361 return MEMTX_DECODE_ERROR;
093bc2cd
AK		 1362 }
1363
a621f38d
AK		 1364 adjust_endianness(mr, &data, size);
1365
8c56c1a5
PF		 1366 if ((!kvm_eventfds_enabled()) &&
1367 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1368 return MEMTX_OK;
1369 }
1370
ce5d2f33 1371 if (mr->ops->write) {
cc05c43a
PM		 1372 return access_with_adjusted_size(addr, &data, size,
1373 mr->ops->impl.min_access_size,
1374 mr->ops->impl.max_access_size,
1375 memory_region_write_accessor, mr,
1376 attrs);
1377 } else if (mr->ops->write_with_attrs) {
1378 return
1379 access_with_adjusted_size(addr, &data, size,
1380 mr->ops->impl.min_access_size,
1381 mr->ops->impl.max_access_size,
1382 memory_region_write_with_attrs_accessor,
1383 mr, attrs);
ce5d2f33 1384 } else {
cc05c43a
PM		 1385 return access_with_adjusted_size(addr, &data, size, 1, 4,
1386 memory_region_oldmmio_write_accessor,
1387 mr, attrs);
74901c3b 1388 }
093bc2cd
AK		 1389}
1390
093bc2cd 1391void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1392 Object *owner,
093bc2cd
AK		 1393 const MemoryRegionOps *ops,
1394 void *opaque,
1395 const char *name,
1396 uint64_t size)
1397{
2c9b15ca 1398 memory_region_init(mr, owner, name, size);
6d6d2abf 1399 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1400 mr->opaque = opaque;
14a3c10a 1401 mr->terminates = true;
093bc2cd
AK		 1402}
1403
1cfe48c1
PM		 1404void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1405 Object *owner,
1406 const char *name,
1407 uint64_t size,
1408 Error **errp)
093bc2cd 1409{
2c9b15ca 1410 memory_region_init(mr, owner, name, size);
8ea9252a 1411 mr->ram = true;
14a3c10a 1412 mr->terminates = true;
545e92e0 1413 mr->destructor = memory_region_destructor_ram;
8e41fb63 1414 mr->ram_block = qemu_ram_alloc(size, mr, errp);
677e7805 1415 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
0b183fc8
PB		 1416}
1417
60786ef3
MT		 1418void memory_region_init_resizeable_ram(MemoryRegion *mr,
1419 Object *owner,
1420 const char *name,
1421 uint64_t size,
1422 uint64_t max_size,
1423 void (*resized)(const char*,
1424 uint64_t length,
1425 void *host),
1426 Error **errp)
1427{
1428 memory_region_init(mr, owner, name, size);
1429 mr->ram = true;
1430 mr->terminates = true;
1431 mr->destructor = memory_region_destructor_ram;
8e41fb63
FZ		 1432 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1433 mr, errp);
677e7805 1434 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
60786ef3
MT		 1435}
1436
0b183fc8
PB		 1437#ifdef __linux__
1438void memory_region_init_ram_from_file(MemoryRegion *mr,
1439 struct Object *owner,
1440 const char *name,
1441 uint64_t size,
dbcb8981 1442 bool share,
7f56e740
PB		 1443 const char *path,
1444 Error **errp)
0b183fc8
PB		 1445{
1446 memory_region_init(mr, owner, name, size);
1447 mr->ram = true;
1448 mr->terminates = true;
1449 mr->destructor = memory_region_destructor_ram;
8e41fb63 1450 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
677e7805 1451 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
093bc2cd 1452}
fea617c5
MAL		 1453
1454void memory_region_init_ram_from_fd(MemoryRegion *mr,
1455 struct Object *owner,
1456 const char *name,
1457 uint64_t size,
1458 bool share,
1459 int fd,
1460 Error **errp)
1461{
1462 memory_region_init(mr, owner, name, size);
1463 mr->ram = true;
1464 mr->terminates = true;
1465 mr->destructor = memory_region_destructor_ram;
1466 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1467 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1468}
0b183fc8 1469#endif
093bc2cd
AK		 1470
1471void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1472 Object *owner,
093bc2cd
AK		 1473 const char *name,
1474 uint64_t size,
1475 void *ptr)
1476{
2c9b15ca 1477 memory_region_init(mr, owner, name, size);
8ea9252a 1478 mr->ram = true;
14a3c10a 1479 mr->terminates = true;
fc3e7665 1480 mr->destructor = memory_region_destructor_ram;
677e7805 1481 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT		 1482
1483 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1484 assert(ptr != NULL);
8e41fb63 1485 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK		 1486}
1487
21e00fa5
AW		 1488void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1489 Object *owner,
1490 const char *name,
1491 uint64_t size,
1492 void *ptr)
e4dc3f59 1493{
21e00fa5
AW		 1494 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1495 mr->ram_device = true;
4a2e242b
AW		 1496 mr->ops = &ram_device_mem_ops;
1497 mr->opaque = mr;
e4dc3f59
ND		 1498}
1499
093bc2cd 1500void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1501 Object *owner,
093bc2cd
AK		 1502 const char *name,
1503 MemoryRegion *orig,
a8170e5e 1504 hwaddr offset,
093bc2cd
AK		 1505 uint64_t size)
1506{
2c9b15ca 1507 memory_region_init(mr, owner, name, size);
093bc2cd
AK		 1508 mr->alias = orig;
1509 mr->alias_offset = offset;
1510}
1511
b59821a9
PM		 1512void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1513 struct Object *owner,
1514 const char *name,
1515 uint64_t size,
1516 Error **errp)
a1777f7f
PM		 1517{
1518 memory_region_init(mr, owner, name, size);
1519 mr->ram = true;
1520 mr->readonly = true;
1521 mr->terminates = true;
1522 mr->destructor = memory_region_destructor_ram;
1523 mr->ram_block = qemu_ram_alloc(size, mr, errp);
1524 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1525}
1526
b59821a9
PM		 1527void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1528 Object *owner,
1529 const MemoryRegionOps *ops,
1530 void *opaque,
1531 const char *name,
1532 uint64_t size,
1533 Error **errp)
d0a9b5bc 1534{
39e0b03d 1535 assert(ops);
2c9b15ca 1536 memory_region_init(mr, owner, name, size);
7bc2b9cd 1537 mr->ops = ops;
75f5941c 1538 mr->opaque = opaque;
d0a9b5bc 1539 mr->terminates = true;
75c578dc 1540 mr->rom_device = true;
58268c8d 1541 mr->destructor = memory_region_destructor_ram;
8e41fb63 1542 mr->ram_block = qemu_ram_alloc(size, mr, errp);
d0a9b5bc
AK		 1543}
1544
1221a474
AK		 1545void memory_region_init_iommu(void *_iommu_mr,
1546 size_t instance_size,
1547 const char *mrtypename,
2c9b15ca 1548 Object *owner,
30951157
AK		 1549 const char *name,
1550 uint64_t size)
1551{
1221a474 1552 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK		 1553 struct MemoryRegion *mr;
1554
1221a474
AK		 1555 object_initialize(_iommu_mr, instance_size, mrtypename);
1556 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK		 1557 memory_region_do_init(mr, owner, name, size);
1558 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1559 mr->terminates = true; /* then re-forwards */
3df9d748
AK		 1560 QLIST_INIT(&iommu_mr->iommu_notify);
1561 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK		 1562}
1563
b4fefef9 1564static void memory_region_finalize(Object *obj)
093bc2cd 1565{
b4fefef9
PC		 1566 MemoryRegion *mr = MEMORY_REGION(obj);
1567
2e2b8eb7
PB		 1568 assert(!mr->container);
1569
1570 /* We know the region is not visible in any address space (it
1571 * does not have a container and cannot be a root either because
1572 * it has no references, so we can blindly clear mr->enabled.
1573 * memory_region_set_enabled instead could trigger a transaction
1574 * and cause an infinite loop.
1575 */
1576 mr->enabled = false;
1577 memory_region_transaction_begin();
1578 while (!QTAILQ_EMPTY(&mr->subregions)) {
1579 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1580 memory_region_del_subregion(mr, subregion);
1581 }
1582 memory_region_transaction_commit();
1583
545e92e0 1584 mr->destructor(mr);
093bc2cd 1585 memory_region_clear_coalescing(mr);
302fa283 1586 g_free((char *)mr->name);
7267c094 1587 g_free(mr->ioeventfds);
093bc2cd
AK		 1588}
1589
803c0816
PB		 1590Object *memory_region_owner(MemoryRegion *mr)
1591{
22a893e4
PB		 1592 Object *obj = OBJECT(mr);
1593 return obj->parent;
803c0816
PB		 1594}
1595
46637be2
PB		 1596void memory_region_ref(MemoryRegion *mr)
1597{
22a893e4
PB		 1598 /* MMIO callbacks most likely will access data that belongs
1599 * to the owner, hence the need to ref/unref the owner whenever
1600 * the memory region is in use.
1601 *
1602 * The memory region is a child of its owner. As long as the
1603 * owner doesn't call unparent itself on the memory region,
1604 * ref-ing the owner will also keep the memory region alive.
612263cf
PB		 1605 * Memory regions without an owner are supposed to never go away;
1606 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1607 */
612263cf
PB		 1608 if (mr && mr->owner) {
1609 object_ref(mr->owner);
46637be2
PB		 1610 }
1611}
1612
1613void memory_region_unref(MemoryRegion *mr)
1614{
612263cf
PB		 1615 if (mr && mr->owner) {
1616 object_unref(mr->owner);
46637be2
PB		 1617 }
1618}
1619
093bc2cd
AK		 1620uint64_t memory_region_size(MemoryRegion *mr)
1621{
08dafab4
AK		 1622 if (int128_eq(mr->size, int128_2_64())) {
1623 return UINT64_MAX;
1624 }
1625 return int128_get64(mr->size);
093bc2cd
AK		 1626}
1627
5d546d4b 1628const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1629{
d1dd32af
PC		 1630 if (!mr->name) {
1631 ((MemoryRegion *)mr)->name =
1632 object_get_canonical_path_component(OBJECT(mr));
1633 }
302fa283 1634 return mr->name;
8991c79b
AK		 1635}
1636
21e00fa5 1637bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1638{
21e00fa5 1639 return mr->ram_device;
e4dc3f59
ND		 1640}
1641
2d1a35be 1642uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1643{
6f6a5ef3 1644 uint8_t mask = mr->dirty_log_mask;
adaad61c 1645 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB		 1646 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1647 }
1648 return mask;
55043ba3
AK		 1649}
1650
2d1a35be
PB		 1651bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1652{
1653 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1654}
1655
3df9d748 1656static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
5bf3d319
PX		 1657{
1658 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1659 IOMMUNotifier *iommu_notifier;
1221a474 1660 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
5bf3d319 1661
3df9d748 1662 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX		 1663 flags |= iommu_notifier->notifier_flags;
1664 }
1665
1221a474
AK		 1666 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1667 imrc->notify_flag_changed(iommu_mr,
1668 iommu_mr->iommu_notify_flags,
1669 flags);
5bf3d319
PX		 1670 }
1671
3df9d748 1672 iommu_mr->iommu_notify_flags = flags;
5bf3d319
PX		 1673}
1674
cdb30812
PX		 1675void memory_region_register_iommu_notifier(MemoryRegion *mr,
1676 IOMMUNotifier *n)
06866575 1677{
3df9d748
AK		 1678 IOMMUMemoryRegion *iommu_mr;
1679
efcd38c5
JW		 1680 if (mr->alias) {
1681 memory_region_register_iommu_notifier(mr->alias, n);
1682 return;
1683 }
1684
cdb30812 1685 /* We need to register for at least one bitfield */
3df9d748 1686 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1687 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1688 assert(n->start <= n->end);
3df9d748
AK		 1689 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1690 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG		 1691}
1692
3df9d748 1693uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1694{
1221a474
AK		 1695 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1696
1697 if (imrc->get_min_page_size) {
1698 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK		 1699 }
1700 return TARGET_PAGE_SIZE;
1701}
1702
3df9d748 1703void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1704{
3df9d748 1705 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1706 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1707 hwaddr addr, granularity;
a788f227
DG		 1708 IOMMUTLBEntry iotlb;
1709
faa362e3 1710 /* If the IOMMU has its own replay callback, override */
1221a474
AK		 1711 if (imrc->replay) {
1712 imrc->replay(iommu_mr, n);
faa362e3
PX		 1713 return;
1714 }
1715
3df9d748 1716 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1717
a788f227 1718 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1221a474 1719 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE);
a788f227
DG		 1720 if (iotlb.perm != IOMMU_NONE) {
1721 n->notify(n, &iotlb);
1722 }
1723
1724 /* if (2^64 - MR size) < granularity, it's possible to get an
1725 * infinite loop here. This should catch such a wraparound */
1726 if ((addr + granularity) < addr) {
1727 break;
1728 }
1729 }
1730}
1731
3df9d748 1732void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
de472e4a
PX		 1733{
1734 IOMMUNotifier *notifier;
1735
3df9d748
AK		 1736 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1737 memory_region_iommu_replay(iommu_mr, notifier);
de472e4a
PX		 1738 }
1739}
1740
cdb30812
PX		 1741void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1742 IOMMUNotifier *n)
06866575 1743{
3df9d748
AK		 1744 IOMMUMemoryRegion *iommu_mr;
1745
efcd38c5
JW		 1746 if (mr->alias) {
1747 memory_region_unregister_iommu_notifier(mr->alias, n);
1748 return;
1749 }
cdb30812 1750 QLIST_REMOVE(n, node);
3df9d748
AK		 1751 iommu_mr = IOMMU_MEMORY_REGION(mr);
1752 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG		 1753}
1754
bd2bfa4c
PX		 1755void memory_region_notify_one(IOMMUNotifier *notifier,
1756 IOMMUTLBEntry *entry)
06866575 1757{
cdb30812
PX		 1758 IOMMUNotifierFlag request_flags;
1759
bd2bfa4c
PX		 1760 /*
1761 * Skip the notification if the notification does not overlap
1762 * with registered range.
1763 */
1764 if (notifier->start > entry->iova + entry->addr_mask + 1 ||
1765 notifier->end < entry->iova) {
1766 return;
1767 }
cdb30812 1768
bd2bfa4c 1769 if (entry->perm & IOMMU_RW) {
cdb30812
PX		 1770 request_flags = IOMMU_NOTIFIER_MAP;
1771 } else {
1772 request_flags = IOMMU_NOTIFIER_UNMAP;
1773 }
1774
bd2bfa4c
PX		 1775 if (notifier->notifier_flags & request_flags) {
1776 notifier->notify(notifier, entry);
1777 }
1778}
1779
3df9d748 1780void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
bd2bfa4c
PX		 1781 IOMMUTLBEntry entry)
1782{
1783 IOMMUNotifier *iommu_notifier;
1784
3df9d748 1785 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1786
3df9d748 1787 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
bd2bfa4c 1788 memory_region_notify_one(iommu_notifier, &entry);
cdb30812 1789 }
06866575
DG		 1790}
1791
093bc2cd
AK		 1792void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1793{
5a583347 1794 uint8_t mask = 1 << client;
deb809ed 1795 uint8_t old_logging;
5a583347 1796
dbddac6d 1797 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB		 1798 old_logging = mr->vga_logging_count;
1799 mr->vga_logging_count += log ? 1 : -1;
1800 if (!!old_logging == !!mr->vga_logging_count) {
1801 return;
1802 }
1803
59023ef4 1804 memory_region_transaction_begin();
5a583347 1805 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1806 memory_region_update_pending |= mr->enabled;
59023ef4 1807 memory_region_transaction_commit();
093bc2cd
AK		 1808}
1809
a8170e5e
AK		 1810bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1811 hwaddr size, unsigned client)
093bc2cd 1812{
8e41fb63
FZ		 1813 assert(mr->ram_block);
1814 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1815 size, client);
093bc2cd
AK		 1816}
1817
a8170e5e
AK		 1818void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1819 hwaddr size)
093bc2cd 1820{
8e41fb63
FZ		 1821 assert(mr->ram_block);
1822 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1823 size,
58d2707e 1824 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK		 1825}
1826
6c279db8
JQ		 1827bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1828 hwaddr size, unsigned client)
1829{
8e41fb63
FZ		 1830 assert(mr->ram_block);
1831 return cpu_physical_memory_test_and_clear_dirty(
1832 memory_region_get_ram_addr(mr) + addr, size, client);
6c279db8
JQ		 1833}
1834
8deaf12c
GH		 1835DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
1836 hwaddr addr,
1837 hwaddr size,
1838 unsigned client)
1839{
1840 assert(mr->ram_block);
1841 return cpu_physical_memory_snapshot_and_clear_dirty(
1842 memory_region_get_ram_addr(mr) + addr, size, client);
1843}
1844
1845bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
1846 hwaddr addr, hwaddr size)
1847{
1848 assert(mr->ram_block);
1849 return cpu_physical_memory_snapshot_get_dirty(snap,
1850 memory_region_get_ram_addr(mr) + addr, size);
1851}
6c279db8 1852
093bc2cd
AK		 1853void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1854{
0a752eee 1855 MemoryListener *listener;
0d673e36 1856 AddressSpace *as;
0a752eee 1857 FlatView *view;
5a583347
AK		 1858 FlatRange *fr;
1859
0a752eee
PB		 1860 /* If the same address space has multiple log_sync listeners, we
1861 * visit that address space's FlatView multiple times. But because
1862 * log_sync listeners are rare, it's still cheaper than walking each
1863 * address space once.
1864 */
1865 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1866 if (!listener->log_sync) {
1867 continue;
1868 }
1869 as = listener->address_space;
1870 view = address_space_get_flatview(as);
99e86347 1871 FOR_EACH_FLAT_RANGE(fr, view) {
0d673e36 1872 if (fr->mr == mr) {
16620684 1873 MemoryRegionSection mrs = section_from_flat_range(fr, view);
0a752eee 1874 listener->log_sync(listener, &mrs);
0d673e36 1875 }
5a583347 1876 }
856d7245 1877 flatview_unref(view);
5a583347 1878 }
093bc2cd
AK		 1879}
1880
1881void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1882{
fb1cd6f9 1883 if (mr->readonly != readonly) {
59023ef4 1884 memory_region_transaction_begin();
fb1cd6f9 1885 mr->readonly = readonly;
22bde714 1886 memory_region_update_pending |= mr->enabled;
59023ef4 1887 memory_region_transaction_commit();
fb1cd6f9 1888 }
093bc2cd
AK		 1889}
1890
5f9a5ea1 1891void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 1892{
5f9a5ea1 1893 if (mr->romd_mode != romd_mode) {
59023ef4 1894 memory_region_transaction_begin();
5f9a5ea1 1895 mr->romd_mode = romd_mode;
22bde714 1896 memory_region_update_pending |= mr->enabled;
59023ef4 1897 memory_region_transaction_commit();
d0a9b5bc
AK		 1898 }
1899}
1900
a8170e5e
AK		 1901void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
1902 hwaddr size, unsigned client)
093bc2cd 1903{
8e41fb63
FZ		 1904 assert(mr->ram_block);
1905 cpu_physical_memory_test_and_clear_dirty(
1906 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK		 1907}
1908
a35ba7be
PB		 1909int memory_region_get_fd(MemoryRegion *mr)
1910{
4ff87573
PB		 1911 int fd;
1912
1913 rcu_read_lock();
1914 while (mr->alias) {
1915 mr = mr->alias;
a35ba7be 1916 }
4ff87573
PB		 1917 fd = mr->ram_block->fd;
1918 rcu_read_unlock();
a35ba7be 1919
4ff87573
PB		 1920 return fd;
1921}
a35ba7be 1922
093bc2cd
AK		 1923void *memory_region_get_ram_ptr(MemoryRegion *mr)
1924{
49b24afc
PB		 1925 void *ptr;
1926 uint64_t offset = 0;
093bc2cd 1927
49b24afc
PB		 1928 rcu_read_lock();
1929 while (mr->alias) {
1930 offset += mr->alias_offset;
1931 mr = mr->alias;
1932 }
8e41fb63 1933 assert(mr->ram_block);
0878d0e1 1934 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
49b24afc 1935 rcu_read_unlock();
093bc2cd 1936
0878d0e1 1937 return ptr;
093bc2cd
AK		 1938}
1939
07bdaa41
PB		 1940MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
1941{
1942 RAMBlock *block;
1943
1944 block = qemu_ram_block_from_host(ptr, false, offset);
1945 if (!block) {
1946 return NULL;
1947 }
1948
1949 return block->mr;
1950}
1951
7ebb2745
FZ		 1952ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
1953{
1954 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
1955}
1956
37d7c084
PB		 1957void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
1958{
8e41fb63 1959 assert(mr->ram_block);
37d7c084 1960
fa53a0e5 1961 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB		 1962}
1963
0d673e36 1964static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 1965{
99e86347 1966 FlatView *view;
093bc2cd
AK		 1967 FlatRange *fr;
1968 CoalescedMemoryRange *cmr;
1969 AddrRange tmp;
95d2994a 1970 MemoryRegionSection section;
093bc2cd 1971
856d7245 1972 view = address_space_get_flatview(as);
99e86347 1973 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 1974 if (fr->mr == mr) {
95d2994a 1975 section = (MemoryRegionSection) {
16620684 1976 .fv = view,
95d2994a 1977 .offset_within_address_space = int128_get64(fr->addr.start),
052e87b0 1978 .size = fr->addr.size,
95d2994a
AK		 1979 };
1980
9a54635d 1981 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
95d2994a
AK		 1982 int128_get64(fr->addr.start),
1983 int128_get64(fr->addr.size));
093bc2cd
AK		 1984 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
1985 tmp = addrrange_shift(cmr->addr,
08dafab4
AK		 1986 int128_sub(fr->addr.start,
1987 int128_make64(fr->offset_in_region)));
093bc2cd
AK		 1988 if (!addrrange_intersects(tmp, fr->addr)) {
1989 continue;
1990 }
1991 tmp = addrrange_intersection(tmp, fr->addr);
9a54635d 1992 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
95d2994a
AK		 1993 int128_get64(tmp.start),
1994 int128_get64(tmp.size));
093bc2cd
AK		 1995 }
1996 }
1997 }
856d7245 1998 flatview_unref(view);
093bc2cd
AK		 1999}
2000
0d673e36
AK		 2001static void memory_region_update_coalesced_range(MemoryRegion *mr)
2002{
2003 AddressSpace *as;
2004
2005 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2006 memory_region_update_coalesced_range_as(mr, as);
2007 }
2008}
2009
093bc2cd
AK		 2010void memory_region_set_coalescing(MemoryRegion *mr)
2011{
2012 memory_region_clear_coalescing(mr);
08dafab4 2013 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK		 2014}
2015
2016void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 2017 hwaddr offset,
093bc2cd
AK		 2018 uint64_t size)
2019{
7267c094 2020 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2021
08dafab4 2022 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK		 2023 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2024 memory_region_update_coalesced_range(mr);
d410515e 2025 memory_region_set_flush_coalesced(mr);
093bc2cd
AK		 2026}
2027
2028void memory_region_clear_coalescing(MemoryRegion *mr)
2029{
2030 CoalescedMemoryRange *cmr;
ab5b3db5 2031 bool updated = false;
093bc2cd 2032
d410515e
JK		 2033 qemu_flush_coalesced_mmio_buffer();
2034 mr->flush_coalesced_mmio = false;
2035
093bc2cd
AK		 2036 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2037 cmr = QTAILQ_FIRST(&mr->coalesced);
2038 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 2039 g_free(cmr);
ab5b3db5
FZ		 2040 updated = true;
2041 }
2042
2043 if (updated) {
2044 memory_region_update_coalesced_range(mr);
093bc2cd 2045 }
093bc2cd
AK		 2046}
2047
d410515e
JK		 2048void memory_region_set_flush_coalesced(MemoryRegion *mr)
2049{
2050 mr->flush_coalesced_mmio = true;
2051}
2052
2053void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2054{
2055 qemu_flush_coalesced_mmio_buffer();
2056 if (QTAILQ_EMPTY(&mr->coalesced)) {
2057 mr->flush_coalesced_mmio = false;
2058 }
2059}
2060
196ea131
JK		 2061void memory_region_set_global_locking(MemoryRegion *mr)
2062{
2063 mr->global_locking = true;
2064}
2065
2066void memory_region_clear_global_locking(MemoryRegion *mr)
2067{
2068 mr->global_locking = false;
2069}
2070
8c56c1a5
PF		 2071static bool userspace_eventfd_warning;
2072
3e9d69e7 2073void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2074 hwaddr addr,
3e9d69e7
AK		 2075 unsigned size,
2076 bool match_data,
2077 uint64_t data,
753d5e14 2078 EventNotifier *e)
3e9d69e7
AK		 2079{
2080 MemoryRegionIoeventfd mrfd = {
08dafab4
AK		 2081 .addr.start = int128_make64(addr),
2082 .addr.size = int128_make64(size),
3e9d69e7
AK		 2083 .match_data = match_data,
2084 .data = data,
753d5e14 2085 .e = e,
3e9d69e7
AK		 2086 };
2087 unsigned i;
2088
8c56c1a5
PF		 2089 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2090 userspace_eventfd_warning))) {
2091 userspace_eventfd_warning = true;
2092 error_report("Using eventfd without MMIO binding in KVM. "
2093 "Suboptimal performance expected");
2094 }
2095
b8aecea2
JW		 2096 if (size) {
2097 adjust_endianness(mr, &mrfd.data, size);
2098 }
59023ef4 2099 memory_region_transaction_begin();
3e9d69e7
AK		 2100 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2101 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
2102 break;
2103 }
2104 }
2105 ++mr->ioeventfd_nb;
7267c094 2106 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK		 2107 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2108 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2109 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2110 mr->ioeventfds[i] = mrfd;
4dc56152 2111 ioeventfd_update_pending |= mr->enabled;
59023ef4 2112 memory_region_transaction_commit();
3e9d69e7
AK		 2113}
2114
2115void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2116 hwaddr addr,
3e9d69e7
AK		 2117 unsigned size,
2118 bool match_data,
2119 uint64_t data,
753d5e14 2120 EventNotifier *e)
3e9d69e7
AK		 2121{
2122 MemoryRegionIoeventfd mrfd = {
08dafab4
AK		 2123 .addr.start = int128_make64(addr),
2124 .addr.size = int128_make64(size),
3e9d69e7
AK		 2125 .match_data = match_data,
2126 .data = data,
753d5e14 2127 .e = e,
3e9d69e7
AK		 2128 };
2129 unsigned i;
2130
b8aecea2
JW		 2131 if (size) {
2132 adjust_endianness(mr, &mrfd.data, size);
2133 }
59023ef4 2134 memory_region_transaction_begin();
3e9d69e7
AK		 2135 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2136 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
2137 break;
2138 }
2139 }
2140 assert(i != mr->ioeventfd_nb);
2141 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2142 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2143 --mr->ioeventfd_nb;
7267c094 2144 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2145 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2146 ioeventfd_update_pending |= mr->enabled;
59023ef4 2147 memory_region_transaction_commit();
3e9d69e7
AK		 2148}
2149
feca4ac1 2150static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2151{
feca4ac1 2152 MemoryRegion *mr = subregion->container;
093bc2cd
AK		 2153 MemoryRegion *other;
2154
59023ef4
JK		 2155 memory_region_transaction_begin();
2156
dfde4e6e 2157 memory_region_ref(subregion);
093bc2cd
AK		 2158 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2159 if (subregion->priority >= other->priority) {
2160 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2161 goto done;
2162 }
2163 }
2164 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2165done:
22bde714 2166 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2167 memory_region_transaction_commit();
093bc2cd
AK		 2168}
2169
0598701a
PC		 2170static void memory_region_add_subregion_common(MemoryRegion *mr,
2171 hwaddr offset,
2172 MemoryRegion *subregion)
2173{
feca4ac1
PB		 2174 assert(!subregion->container);
2175 subregion->container = mr;
0598701a 2176 subregion->addr = offset;
feca4ac1 2177 memory_region_update_container_subregions(subregion);
0598701a 2178}
093bc2cd
AK		 2179
2180void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2181 hwaddr offset,
093bc2cd
AK		 2182 MemoryRegion *subregion)
2183{
093bc2cd
AK		 2184 subregion->priority = 0;
2185 memory_region_add_subregion_common(mr, offset, subregion);
2186}
2187
2188void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2189 hwaddr offset,
093bc2cd 2190 MemoryRegion *subregion,
a1ff8ae0 2191 int priority)
093bc2cd 2192{
093bc2cd
AK		 2193 subregion->priority = priority;
2194 memory_region_add_subregion_common(mr, offset, subregion);
2195}
2196
2197void memory_region_del_subregion(MemoryRegion *mr,
2198 MemoryRegion *subregion)
2199{
59023ef4 2200 memory_region_transaction_begin();
feca4ac1
PB		 2201 assert(subregion->container == mr);
2202 subregion->container = NULL;
093bc2cd 2203 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2204 memory_region_unref(subregion);
22bde714 2205 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2206 memory_region_transaction_commit();
6bba19ba
AK		 2207}
2208
2209void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2210{
2211 if (enabled == mr->enabled) {
2212 return;
2213 }
59023ef4 2214 memory_region_transaction_begin();
6bba19ba 2215 mr->enabled = enabled;
22bde714 2216 memory_region_update_pending = true;
59023ef4 2217 memory_region_transaction_commit();
093bc2cd 2218}
1c0ffa58 2219
e7af4c67
MT		 2220void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2221{
2222 Int128 s = int128_make64(size);
2223
2224 if (size == UINT64_MAX) {
2225 s = int128_2_64();
2226 }
2227 if (int128_eq(s, mr->size)) {
2228 return;
2229 }
2230 memory_region_transaction_begin();
2231 mr->size = s;
2232 memory_region_update_pending = true;
2233 memory_region_transaction_commit();
2234}
2235
67891b8a 2236static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2237{
feca4ac1 2238 MemoryRegion *container = mr->container;
2282e1af 2239
feca4ac1 2240 if (container) {
67891b8a
PC		 2241 memory_region_transaction_begin();
2242 memory_region_ref(mr);
feca4ac1
PB		 2243 memory_region_del_subregion(container, mr);
2244 mr->container = container;
2245 memory_region_update_container_subregions(mr);
67891b8a
PC		 2246 memory_region_unref(mr);
2247 memory_region_transaction_commit();
2282e1af 2248 }
67891b8a 2249}
2282e1af 2250
67891b8a
PC		 2251void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2252{
2253 if (addr != mr->addr) {
2254 mr->addr = addr;
2255 memory_region_readd_subregion(mr);
2256 }
2282e1af
AK		 2257}
2258
a8170e5e 2259void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2260{
4703359e 2261 assert(mr->alias);
4703359e 2262
59023ef4 2263 if (offset == mr->alias_offset) {
4703359e
AK		 2264 return;
2265 }
2266
59023ef4
JK		 2267 memory_region_transaction_begin();
2268 mr->alias_offset = offset;
22bde714 2269 memory_region_update_pending |= mr->enabled;
59023ef4 2270 memory_region_transaction_commit();
4703359e
AK		 2271}
2272
a2b257d6
IM		 2273uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2274{
2275 return mr->align;
2276}
2277
e2177955
AK		 2278static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2279{
2280 const AddrRange *addr = addr_;
2281 const FlatRange *fr = fr_;
2282
2283 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2284 return -1;
2285 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2286 return 1;
2287 }
2288 return 0;
2289}
2290
99e86347 2291static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2292{
99e86347 2293 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK		 2294 sizeof(FlatRange), cmp_flatrange_addr);
2295}
2296
eed2bacf
IM		 2297bool memory_region_is_mapped(MemoryRegion *mr)
2298{
2299 return mr->container ? true : false;
2300}
2301
c6742b14
PB		 2302/* Same as memory_region_find, but it does not add a reference to the
2303 * returned region. It must be called from an RCU critical section.
2304 */
2305static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2306 hwaddr addr, uint64_t size)
e2177955 2307{
052e87b0 2308 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB		 2309 MemoryRegion *root;
2310 AddressSpace *as;
2311 AddrRange range;
99e86347 2312 FlatView *view;
73034e9e
PB		 2313 FlatRange *fr;
2314
2315 addr += mr->addr;
feca4ac1
PB		 2316 for (root = mr; root->container; ) {
2317 root = root->container;
73034e9e
PB		 2318 addr += root->addr;
2319 }
e2177955 2320
73034e9e 2321 as = memory_region_to_address_space(root);
eed2bacf
IM		 2322 if (!as) {
2323 return ret;
2324 }
73034e9e 2325 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2326
16620684 2327 view = address_space_to_flatview(as);
99e86347 2328 fr = flatview_lookup(view, range);
e2177955 2329 if (!fr) {
c6742b14 2330 return ret;
e2177955
AK		 2331 }
2332
99e86347 2333 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK		 2334 --fr;
2335 }
2336
2337 ret.mr = fr->mr;
16620684 2338 ret.fv = view;
e2177955
AK		 2339 range = addrrange_intersection(range, fr->addr);
2340 ret.offset_within_region = fr->offset_in_region;
2341 ret.offset_within_region += int128_get64(int128_sub(range.start,
2342 fr->addr.start));
052e87b0 2343 ret.size = range.size;
e2177955 2344 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2345 ret.readonly = fr->readonly;
c6742b14
PB		 2346 return ret;
2347}
2348
2349MemoryRegionSection memory_region_find(MemoryRegion *mr,
2350 hwaddr addr, uint64_t size)
2351{
2352 MemoryRegionSection ret;
2353 rcu_read_lock();
2354 ret = memory_region_find_rcu(mr, addr, size);
2355 if (ret.mr) {
2356 memory_region_ref(ret.mr);
2357 }
2b647668 2358 rcu_read_unlock();
e2177955
AK		 2359 return ret;
2360}
2361
c6742b14
PB		 2362bool memory_region_present(MemoryRegion *container, hwaddr addr)
2363{
2364 MemoryRegion *mr;
2365
2366 rcu_read_lock();
2367 mr = memory_region_find_rcu(container, addr, 1).mr;
2368 rcu_read_unlock();
2369 return mr && mr != container;
2370}
2371
9c1f8f44 2372void memory_global_dirty_log_sync(void)
86e775c6 2373{
9c1f8f44
PB		 2374 MemoryListener *listener;
2375 AddressSpace *as;
99e86347 2376 FlatView *view;
7664e80c
AK		 2377 FlatRange *fr;
2378
9c1f8f44
PB		 2379 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2380 if (!listener->log_sync) {
2381 continue;
2382 }
d45fa784 2383 as = listener->address_space;
9c1f8f44
PB		 2384 view = address_space_get_flatview(as);
2385 FOR_EACH_FLAT_RANGE(fr, view) {
adaad61c 2386 if (fr->dirty_log_mask) {
16620684
AK		 2387 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2388
adaad61c
PB		 2389 listener->log_sync(listener, &mrs);
2390 }
9c1f8f44
PB		 2391 }
2392 flatview_unref(view);
7664e80c
AK		 2393 }
2394}
2395
19310760
JZ		 2396static VMChangeStateEntry *vmstate_change;
2397
7664e80c
AK		 2398void memory_global_dirty_log_start(void)
2399{
19310760
JZ		 2400 if (vmstate_change) {
2401 qemu_del_vm_change_state_handler(vmstate_change);
2402 vmstate_change = NULL;
2403 }
2404
7664e80c 2405 global_dirty_log = true;
6f6a5ef3 2406
7376e582 2407 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3
PB		 2408
2409 /* Refresh DIRTY_LOG_MIGRATION bit. */
2410 memory_region_transaction_begin();
2411 memory_region_update_pending = true;
2412 memory_region_transaction_commit();
7664e80c
AK		 2413}
2414
19310760 2415static void memory_global_dirty_log_do_stop(void)
7664e80c 2416{
7664e80c 2417 global_dirty_log = false;
6f6a5ef3
PB		 2418
2419 /* Refresh DIRTY_LOG_MIGRATION bit. */
2420 memory_region_transaction_begin();
2421 memory_region_update_pending = true;
2422 memory_region_transaction_commit();
2423
7376e582 2424 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK		 2425}
2426
19310760
JZ		 2427static void memory_vm_change_state_handler(void *opaque, int running,
2428 RunState state)
2429{
2430 if (running) {
2431 memory_global_dirty_log_do_stop();
2432
2433 if (vmstate_change) {
2434 qemu_del_vm_change_state_handler(vmstate_change);
2435 vmstate_change = NULL;
2436 }
2437 }
2438}
2439
2440void memory_global_dirty_log_stop(void)
2441{
2442 if (!runstate_is_running()) {
2443 if (vmstate_change) {
2444 return;
2445 }
2446 vmstate_change = qemu_add_vm_change_state_handler(
2447 memory_vm_change_state_handler, NULL);
2448 return;
2449 }
2450
2451 memory_global_dirty_log_do_stop();
2452}
2453
7664e80c
AK		 2454static void listener_add_address_space(MemoryListener *listener,
2455 AddressSpace *as)
2456{
99e86347 2457 FlatView *view;
7664e80c
AK		 2458 FlatRange *fr;
2459
680a4783
PB		 2460 if (listener->begin) {
2461 listener->begin(listener);
2462 }
7664e80c 2463 if (global_dirty_log) {
975aefe0
AK		 2464 if (listener->log_global_start) {
2465 listener->log_global_start(listener);
2466 }
7664e80c 2467 }
975aefe0 2468
856d7245 2469 view = address_space_get_flatview(as);
99e86347 2470 FOR_EACH_FLAT_RANGE(fr, view) {
7664e80c
AK		 2471 MemoryRegionSection section = {
2472 .mr = fr->mr,
16620684 2473 .fv = view,
7664e80c 2474 .offset_within_region = fr->offset_in_region,
052e87b0 2475 .size = fr->addr.size,
7664e80c 2476 .offset_within_address_space = int128_get64(fr->addr.start),
7a8499e8 2477 .readonly = fr->readonly,
7664e80c 2478 };
680a4783
PB		 2479 if (fr->dirty_log_mask && listener->log_start) {
2480 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2481 }
975aefe0
AK		 2482 if (listener->region_add) {
2483 listener->region_add(listener, &section);
2484 }
7664e80c 2485 }
680a4783
PB		 2486 if (listener->commit) {
2487 listener->commit(listener);
2488 }
856d7245 2489 flatview_unref(view);
7664e80c
AK		 2490}
2491
d45fa784 2492void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2493{
72e22d2f
AK		 2494 MemoryListener *other = NULL;
2495
d45fa784 2496 listener->address_space = as;
72e22d2f
AK		 2497 if (QTAILQ_EMPTY(&memory_listeners)
2498 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2499 memory_listeners)->priority) {
2500 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2501 } else {
2502 QTAILQ_FOREACH(other, &memory_listeners, link) {
2503 if (listener->priority < other->priority) {
2504 break;
2505 }
2506 }
2507 QTAILQ_INSERT_BEFORE(other, listener, link);
2508 }
0d673e36 2509
9a54635d
PB		 2510 if (QTAILQ_EMPTY(&as->listeners)
2511 || listener->priority >= QTAILQ_LAST(&as->listeners,
2512 memory_listeners)->priority) {
2513 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2514 } else {
2515 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2516 if (listener->priority < other->priority) {
2517 break;
2518 }
2519 }
2520 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2521 }
2522
d45fa784 2523 listener_add_address_space(listener, as);
7664e80c
AK		 2524}
2525
2526void memory_listener_unregister(MemoryListener *listener)
2527{
1d8280c1
PB		 2528 if (!listener->address_space) {
2529 return;
2530 }
2531
72e22d2f 2532 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2533 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2534 listener->address_space = NULL;
86e775c6 2535}
e2177955 2536
c9356746
FK		 2537bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2538{
2539 void *host;
2540 unsigned size = 0;
2541 unsigned offset = 0;
2542 Object *new_interface;
2543
2544 if (!mr || !mr->ops->request_ptr) {
2545 return false;
2546 }
2547
2548 /*
2549 * Avoid an update if the request_ptr call
2550 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2551 * a cache.
2552 */
2553 memory_region_transaction_begin();
2554
2555 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2556
2557 if (!host || !size) {
2558 memory_region_transaction_commit();
2559 return false;
2560 }
2561
2562 new_interface = object_new("mmio_interface");
2563 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2564 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2565 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2566 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2567 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2568 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2569
2570 memory_region_transaction_commit();
2571 return true;
2572}
2573
2574typedef struct MMIOPtrInvalidate {
2575 MemoryRegion *mr;
2576 hwaddr offset;
2577 unsigned size;
2578 int busy;
2579 int allocated;
2580} MMIOPtrInvalidate;
2581
2582#define MAX_MMIO_INVALIDATE 10
2583static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2584
2585static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2586 run_on_cpu_data data)
2587{
2588 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2589 MemoryRegion *mr = invalidate_data->mr;
2590 hwaddr offset = invalidate_data->offset;
2591 unsigned size = invalidate_data->size;
2592 MemoryRegionSection section = memory_region_find(mr, offset, size);
2593
2594 qemu_mutex_lock_iothread();
2595
2596 /* Reset dirty so this doesn't happen later. */
2597 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2598
2599 if (section.mr != mr) {
2600 /* memory_region_find add a ref on section.mr */
2601 memory_region_unref(section.mr);
2602 if (MMIO_INTERFACE(section.mr->owner)) {
2603 /* We found the interface just drop it. */
2604 object_property_set_bool(section.mr->owner, false, "realized",
2605 NULL);
2606 object_unref(section.mr->owner);
2607 object_unparent(section.mr->owner);
2608 }
2609 }
2610
2611 qemu_mutex_unlock_iothread();
2612
2613 if (invalidate_data->allocated) {
2614 g_free(invalidate_data);
2615 } else {
2616 invalidate_data->busy = 0;
2617 }
2618}
2619
2620void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2621 unsigned size)
2622{
2623 size_t i;
2624 MMIOPtrInvalidate *invalidate_data = NULL;
2625
2626 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2627 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2628 invalidate_data = &mmio_ptr_invalidate_list[i];
2629 break;
2630 }
2631 }
2632
2633 if (!invalidate_data) {
2634 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2635 invalidate_data->allocated = 1;
2636 }
2637
2638 invalidate_data->mr = mr;
2639 invalidate_data->offset = offset;
2640 invalidate_data->size = size;
2641
2642 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2643 RUN_ON_CPU_HOST_PTR(invalidate_data));
2644}
2645
7dca8043 2646void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2647{
ac95190e 2648 memory_region_ref(root);
59023ef4 2649 memory_region_transaction_begin();
f0c02d15 2650 as->ref_count = 1;
8786db7c 2651 as->root = root;
f0c02d15 2652 as->malloced = false;
cc94cd6d 2653 as->current_map = flatview_new();
4c19eb72
AK		 2654 as->ioeventfd_nb = 0;
2655 as->ioeventfds = NULL;
9a54635d 2656 QTAILQ_INIT(&as->listeners);
0d673e36 2657 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2658 as->name = g_strdup(name ? name : "anonymous");
f43793c7
PB		 2659 memory_region_update_pending |= root->enabled;
2660 memory_region_transaction_commit();
1c0ffa58 2661}
658b2224 2662
374f2981 2663static void do_address_space_destroy(AddressSpace *as)
83f3c251 2664{
f0c02d15 2665 bool do_free = as->malloced;
078c44f4 2666
9a54635d 2667 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2668
856d7245 2669 flatview_unref(as->current_map);
7dca8043 2670 g_free(as->name);
4c19eb72 2671 g_free(as->ioeventfds);
ac95190e 2672 memory_region_unref(as->root);
f0c02d15
PC		 2673 if (do_free) {
2674 g_free(as);
2675 }
2676}
2677
2678AddressSpace *address_space_init_shareable(MemoryRegion *root, const char *name)
2679{
2680 AddressSpace *as;
2681
2682 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2683 if (root == as->root && as->malloced) {
2684 as->ref_count++;
2685 return as;
2686 }
2687 }
2688
2689 as = g_malloc0(sizeof *as);
2690 address_space_init(as, root, name);
2691 as->malloced = true;
2692 return as;
83f3c251
AK		 2693}
2694
374f2981
PB		 2695void address_space_destroy(AddressSpace *as)
2696{
ac95190e
PB		 2697 MemoryRegion *root = as->root;
2698
f0c02d15
PC		 2699 as->ref_count--;
2700 if (as->ref_count) {
2701 return;
2702 }
374f2981
PB		 2703 /* Flush out anything from MemoryListeners listening in on this */
2704 memory_region_transaction_begin();
2705 as->root = NULL;
2706 memory_region_transaction_commit();
2707 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2708
2709 /* At this point, as->dispatch and as->current_map are dummy
2710 * entries that the guest should never use. Wait for the old
2711 * values to expire before freeing the data.
2712 */
ac95190e 2713 as->root = root;
374f2981
PB		 2714 call_rcu(as, do_address_space_destroy, rcu);
2715}
2716
4e831901
PX		 2717static const char *memory_region_type(MemoryRegion *mr)
2718{
2719 if (memory_region_is_ram_device(mr)) {
2720 return "ramd";
2721 } else if (memory_region_is_romd(mr)) {
2722 return "romd";
2723 } else if (memory_region_is_rom(mr)) {
2724 return "rom";
2725 } else if (memory_region_is_ram(mr)) {
2726 return "ram";
2727 } else {
2728 return "i/o";
2729 }
2730}
2731
314e2987
BS		 2732typedef struct MemoryRegionList MemoryRegionList;
2733
2734struct MemoryRegionList {
2735 const MemoryRegion *mr;
a16878d2 2736 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS		 2737};
2738
a16878d2 2739typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
314e2987 2740
4e831901
PX		 2741#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2742 int128_sub((size), int128_one())) : 0)
2743#define MTREE_INDENT " "
2744
314e2987
BS		 2745static void mtree_print_mr(fprintf_function mon_printf, void *f,
2746 const MemoryRegion *mr, unsigned int level,
a8170e5e 2747 hwaddr base,
9479c57a 2748 MemoryRegionListHead *alias_print_queue)
314e2987 2749{
9479c57a
JK		 2750 MemoryRegionList *new_ml, *ml, *next_ml;
2751 MemoryRegionListHead submr_print_queue;
314e2987
BS		 2752 const MemoryRegion *submr;
2753 unsigned int i;
b31f8412 2754 hwaddr cur_start, cur_end;
314e2987 2755
f8a9f720 2756 if (!mr) {
314e2987
BS		 2757 return;
2758 }
2759
2760 for (i = 0; i < level; i++) {
4e831901 2761 mon_printf(f, MTREE_INDENT);
314e2987
BS		 2762 }
2763
b31f8412
PX		 2764 cur_start = base + mr->addr;
2765 cur_end = cur_start + MR_SIZE(mr->size);
2766
2767 /*
2768 * Try to detect overflow of memory region. This should never
2769 * happen normally. When it happens, we dump something to warn the
2770 * user who is observing this.
2771 */
2772 if (cur_start < base || cur_end < cur_start) {
2773 mon_printf(f, "[DETECTED OVERFLOW!] ");
2774 }
2775
314e2987
BS		 2776 if (mr->alias) {
2777 MemoryRegionList *ml;
2778 bool found = false;
2779
2780 /* check if the alias is already in the queue */
a16878d2 2781 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2782 if (ml->mr == mr->alias) {
314e2987
BS		 2783 found = true;
2784 }
2785 }
2786
2787 if (!found) {
2788 ml = g_new(MemoryRegionList, 1);
2789 ml->mr = mr->alias;
a16878d2 2790 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2791 }
4896d74b 2792 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
4e831901 2793 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
f8a9f720 2794 "-" TARGET_FMT_plx "%s\n",
b31f8412 2795 cur_start, cur_end,
4b474ba7 2796 mr->priority,
4e831901 2797 memory_region_type((MemoryRegion *)mr),
3fb18b4d
PC		 2798 memory_region_name(mr),
2799 memory_region_name(mr->alias),
314e2987 2800 mr->alias_offset,
4e831901 2801 mr->alias_offset + MR_SIZE(mr->size),
f8a9f720 2802 mr->enabled ? "" : " [disabled]");
314e2987 2803 } else {
4896d74b 2804 mon_printf(f,
4e831901 2805 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
b31f8412 2806 cur_start, cur_end,
4b474ba7 2807 mr->priority,
4e831901 2808 memory_region_type((MemoryRegion *)mr),
f8a9f720
GH		 2809 memory_region_name(mr),
2810 mr->enabled ? "" : " [disabled]");
314e2987 2811 }
9479c57a
JK		 2812
2813 QTAILQ_INIT(&submr_print_queue);
2814
314e2987 2815 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK		 2816 new_ml = g_new(MemoryRegionList, 1);
2817 new_ml->mr = submr;
a16878d2 2818 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK		 2819 if (new_ml->mr->addr < ml->mr->addr ||
2820 (new_ml->mr->addr == ml->mr->addr &&
2821 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 2822 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK		 2823 new_ml = NULL;
2824 break;
2825 }
2826 }
2827 if (new_ml) {
a16878d2 2828 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK		 2829 }
2830 }
2831
a16878d2 2832 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b31f8412 2833 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
9479c57a
JK		 2834 alias_print_queue);
2835 }
2836
a16878d2 2837 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 2838 g_free(ml);
314e2987
BS		 2839 }
2840}
2841
57bb40c9
PX		 2842static void mtree_print_flatview(fprintf_function p, void *f,
2843 AddressSpace *as)
2844{
2845 FlatView *view = address_space_get_flatview(as);
2846 FlatRange *range = &view->ranges[0];
2847 MemoryRegion *mr;
2848 int n = view->nr;
2849
2850 if (n <= 0) {
2851 p(f, MTREE_INDENT "No rendered FlatView for "
2852 "address space '%s'\n", as->name);
2853 flatview_unref(view);
2854 return;
2855 }
2856
2857 while (n--) {
2858 mr = range->mr;
377a07aa
PB		 2859 if (range->offset_in_region) {
2860 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2861 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
2862 int128_get64(range->addr.start),
2863 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2864 mr->priority,
2865 range->readonly ? "rom" : memory_region_type(mr),
2866 memory_region_name(mr),
2867 range->offset_in_region);
2868 } else {
2869 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2870 TARGET_FMT_plx " (prio %d, %s): %s\n",
2871 int128_get64(range->addr.start),
2872 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2873 mr->priority,
2874 range->readonly ? "rom" : memory_region_type(mr),
2875 memory_region_name(mr));
2876 }
57bb40c9
PX		 2877 range++;
2878 }
2879
2880 flatview_unref(view);
2881}
2882
2883void mtree_info(fprintf_function mon_printf, void *f, bool flatview)
314e2987
BS		 2884{
2885 MemoryRegionListHead ml_head;
2886 MemoryRegionList *ml, *ml2;
0d673e36 2887 AddressSpace *as;
314e2987 2888
57bb40c9
PX		 2889 if (flatview) {
2890 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2891 mon_printf(f, "address-space (flat view): %s\n", as->name);
2892 mtree_print_flatview(mon_printf, f, as);
2893 mon_printf(f, "\n");
2894 }
2895 return;
2896 }
2897
314e2987
BS		 2898 QTAILQ_INIT(&ml_head);
2899
0d673e36 2900 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
e48816aa
GH		 2901 mon_printf(f, "address-space: %s\n", as->name);
2902 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
2903 mon_printf(f, "\n");
b9f9be88
BS		 2904 }
2905
314e2987 2906 /* print aliased regions */
a16878d2 2907 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
e48816aa
GH		 2908 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
2909 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
2910 mon_printf(f, "\n");
314e2987
BS		 2911 }
2912
a16878d2 2913 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 2914 g_free(ml);
314e2987 2915 }
314e2987 2916}
b4fefef9 2917
b08199c6
PM		 2918void memory_region_init_ram(MemoryRegion *mr,
2919 struct Object *owner,
2920 const char *name,
2921 uint64_t size,
2922 Error **errp)
2923{
2924 DeviceState *owner_dev;
2925 Error *err = NULL;
2926
2927 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
2928 if (err) {
2929 error_propagate(errp, err);
2930 return;
2931 }
2932 /* This will assert if owner is neither NULL nor a DeviceState.
2933 * We only want the owner here for the purposes of defining a
2934 * unique name for migration. TODO: Ideally we should implement
2935 * a naming scheme for Objects which are not DeviceStates, in
2936 * which case we can relax this restriction.
2937 */
2938 owner_dev = DEVICE(owner);
2939 vmstate_register_ram(mr, owner_dev);
2940}
2941
2942void memory_region_init_rom(MemoryRegion *mr,
2943 struct Object *owner,
2944 const char *name,
2945 uint64_t size,
2946 Error **errp)
2947{
2948 DeviceState *owner_dev;
2949 Error *err = NULL;
2950
2951 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
2952 if (err) {
2953 error_propagate(errp, err);
2954 return;
2955 }
2956 /* This will assert if owner is neither NULL nor a DeviceState.
2957 * We only want the owner here for the purposes of defining a
2958 * unique name for migration. TODO: Ideally we should implement
2959 * a naming scheme for Objects which are not DeviceStates, in
2960 * which case we can relax this restriction.
2961 */
2962 owner_dev = DEVICE(owner);
2963 vmstate_register_ram(mr, owner_dev);
2964}
2965
2966void memory_region_init_rom_device(MemoryRegion *mr,
2967 struct Object *owner,
2968 const MemoryRegionOps *ops,
2969 void *opaque,
2970 const char *name,
2971 uint64_t size,
2972 Error **errp)
2973{
2974 DeviceState *owner_dev;
2975 Error *err = NULL;
2976
2977 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
2978 name, size, &err);
2979 if (err) {
2980 error_propagate(errp, err);
2981 return;
2982 }
2983 /* This will assert if owner is neither NULL nor a DeviceState.
2984 * We only want the owner here for the purposes of defining a
2985 * unique name for migration. TODO: Ideally we should implement
2986 * a naming scheme for Objects which are not DeviceStates, in
2987 * which case we can relax this restriction.
2988 */
2989 owner_dev = DEVICE(owner);
2990 vmstate_register_ram(mr, owner_dev);
2991}
2992
b4fefef9
PC		 2993static const TypeInfo memory_region_info = {
2994 .parent = TYPE_OBJECT,
2995 .name = TYPE_MEMORY_REGION,
2996 .instance_size = sizeof(MemoryRegion),
2997 .instance_init = memory_region_initfn,
2998 .instance_finalize = memory_region_finalize,
2999};
3000
3df9d748
AK		 3001static const TypeInfo iommu_memory_region_info = {
3002 .parent = TYPE_MEMORY_REGION,
3003 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 3004 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK		 3005 .instance_size = sizeof(IOMMUMemoryRegion),
3006 .instance_init = iommu_memory_region_initfn,
1221a474 3007 .abstract = true,
3df9d748
AK		 3008};
3009
b4fefef9
PC		 3010static void memory_register_types(void)
3011{
3012 type_register_static(&memory_region_info);
3df9d748 3013 type_register_static(&iommu_memory_region_info);
b4fefef9
PC		 3014}
3015
3016type_init(memory_register_types)
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