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memory: extract flat_range_coalesced_io_{del,add}
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CommitLineData
093bc2cd
AK
1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
AK
14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879
PB
18#include "qemu-common.h"
19#include "cpu.h"
022c62cb
PB
20#include "exec/memory.h"
21#include "exec/address-spaces.h"
409ddd01 22#include "qapi/visitor.h"
1de7afc9 23#include "qemu/bitops.h"
8c56c1a5 24#include "qemu/error-report.h"
2c9b15ca 25#include "qom/object.h"
0ab8ed18 26#include "trace-root.h"
093bc2cd 27
022c62cb 28#include "exec/memory-internal.h"
220c3ebd 29#include "exec/ram_addr.h"
8c56c1a5 30#include "sysemu/kvm.h"
e1c57ab8 31#include "sysemu/sysemu.h"
c9356746 32#include "hw/qdev-properties.h"
b08199c6 33#include "migration/vmstate.h"
67d95c15 34
d197063f
PB
35//#define DEBUG_UNASSIGNED
36
22bde714
JK
37static unsigned memory_region_transaction_depth;
38static bool memory_region_update_pending;
4dc56152 39static bool ioeventfd_update_pending;
7664e80c
AK
40static bool global_dirty_log = false;
41
72e22d2f
AK
42static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
43 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 44
0d673e36
AK
45static QTAILQ_HEAD(, AddressSpace) address_spaces
46 = QTAILQ_HEAD_INITIALIZER(address_spaces);
47
967dc9b1
AK
48static GHashTable *flat_views;
49
093bc2cd
AK
50typedef struct AddrRange AddrRange;
51
8417cebf 52/*
c9cdaa3a 53 * Note that signed integers are needed for negative offsetting in aliases
8417cebf
AK
54 * (large MemoryRegion::alias_offset).
55 */
093bc2cd 56struct AddrRange {
08dafab4
AK
57 Int128 start;
58 Int128 size;
093bc2cd
AK
59};
60
08dafab4 61static AddrRange addrrange_make(Int128 start, Int128 size)
093bc2cd
AK
62{
63 return (AddrRange) { start, size };
64}
65
66static bool addrrange_equal(AddrRange r1, AddrRange r2)
67{
08dafab4 68 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
093bc2cd
AK
69}
70
08dafab4 71static Int128 addrrange_end(AddrRange r)
093bc2cd 72{
08dafab4 73 return int128_add(r.start, r.size);
093bc2cd
AK
74}
75
08dafab4 76static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 77{
08dafab4 78 int128_addto(&range.start, delta);
093bc2cd
AK
79 return range;
80}
81
08dafab4
AK
82static bool addrrange_contains(AddrRange range, Int128 addr)
83{
84 return int128_ge(addr, range.start)
85 && int128_lt(addr, addrrange_end(range));
86}
87
093bc2cd
AK
88static bool addrrange_intersects(AddrRange r1, AddrRange r2)
89{
08dafab4
AK
90 return addrrange_contains(r1, r2.start)
91 || addrrange_contains(r2, r1.start);
093bc2cd
AK
92}
93
94static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
95{
08dafab4
AK
96 Int128 start = int128_max(r1.start, r2.start);
97 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
98 return addrrange_make(start, int128_sub(end, start));
093bc2cd
AK
99}
100
0e0d36b4
AK
101enum ListenerDirection { Forward, Reverse };
102
7376e582 103#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
AK
104 do { \
105 MemoryListener *_listener; \
106 \
107 switch (_direction) { \
108 case Forward: \
109 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
AK
110 if (_listener->_callback) { \
111 _listener->_callback(_listener, ##_args); \
112 } \
0e0d36b4
AK
113 } \
114 break; \
115 case Reverse: \
116 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
117 memory_listeners, link) { \
975aefe0
AK
118 if (_listener->_callback) { \
119 _listener->_callback(_listener, ##_args); \
120 } \
0e0d36b4
AK
121 } \
122 break; \
123 default: \
124 abort(); \
125 } \
126 } while (0)
127
9a54635d 128#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
7376e582
AK
129 do { \
130 MemoryListener *_listener; \
9a54635d 131 struct memory_listeners_as *list = &(_as)->listeners; \
7376e582
AK
132 \
133 switch (_direction) { \
134 case Forward: \
9a54635d
PB
135 QTAILQ_FOREACH(_listener, list, link_as) { \
136 if (_listener->_callback) { \
7376e582
AK
137 _listener->_callback(_listener, _section, ##_args); \
138 } \
139 } \
140 break; \
141 case Reverse: \
9a54635d
PB
142 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
143 link_as) { \
144 if (_listener->_callback) { \
7376e582
AK
145 _listener->_callback(_listener, _section, ##_args); \
146 } \
147 } \
148 break; \
149 default: \
150 abort(); \
151 } \
152 } while (0)
153
dfde4e6e 154/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 155#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44 156 do { \
16620684
AK
157 MemoryRegionSection mrs = section_from_flat_range(fr, \
158 address_space_to_flatview(as)); \
9a54635d 159 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 160 } while(0)
0e0d36b4 161
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AK
162struct CoalescedMemoryRange {
163 AddrRange addr;
164 QTAILQ_ENTRY(CoalescedMemoryRange) link;
165};
166
3e9d69e7
AK
167struct MemoryRegionIoeventfd {
168 AddrRange addr;
169 bool match_data;
170 uint64_t data;
753d5e14 171 EventNotifier *e;
3e9d69e7
AK
172};
173
73bb753d
TB
174static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
175 MemoryRegionIoeventfd *b)
3e9d69e7 176{
73bb753d 177 if (int128_lt(a->addr.start, b->addr.start)) {
3e9d69e7 178 return true;
73bb753d 179 } else if (int128_gt(a->addr.start, b->addr.start)) {
3e9d69e7 180 return false;
73bb753d 181 } else if (int128_lt(a->addr.size, b->addr.size)) {
3e9d69e7 182 return true;
73bb753d 183 } else if (int128_gt(a->addr.size, b->addr.size)) {
3e9d69e7 184 return false;
73bb753d 185 } else if (a->match_data < b->match_data) {
3e9d69e7 186 return true;
73bb753d 187 } else if (a->match_data > b->match_data) {
3e9d69e7 188 return false;
73bb753d
TB
189 } else if (a->match_data) {
190 if (a->data < b->data) {
3e9d69e7 191 return true;
73bb753d 192 } else if (a->data > b->data) {
3e9d69e7
AK
193 return false;
194 }
195 }
73bb753d 196 if (a->e < b->e) {
3e9d69e7 197 return true;
73bb753d 198 } else if (a->e > b->e) {
3e9d69e7
AK
199 return false;
200 }
201 return false;
202}
203
73bb753d
TB
204static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
205 MemoryRegionIoeventfd *b)
3e9d69e7
AK
206{
207 return !memory_region_ioeventfd_before(a, b)
208 && !memory_region_ioeventfd_before(b, a);
209}
210
093bc2cd
AK
211/* Range of memory in the global map. Addresses are absolute. */
212struct FlatRange {
213 MemoryRegion *mr;
a8170e5e 214 hwaddr offset_in_region;
093bc2cd 215 AddrRange addr;
5a583347 216 uint8_t dirty_log_mask;
b138e654 217 bool romd_mode;
fb1cd6f9 218 bool readonly;
c26763f8 219 bool nonvolatile;
093bc2cd
AK
220};
221
093bc2cd
AK
222#define FOR_EACH_FLAT_RANGE(var, view) \
223 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
224
9c1f8f44 225static inline MemoryRegionSection
16620684 226section_from_flat_range(FlatRange *fr, FlatView *fv)
9c1f8f44
PB
227{
228 return (MemoryRegionSection) {
229 .mr = fr->mr,
16620684 230 .fv = fv,
9c1f8f44
PB
231 .offset_within_region = fr->offset_in_region,
232 .size = fr->addr.size,
233 .offset_within_address_space = int128_get64(fr->addr.start),
234 .readonly = fr->readonly,
c26763f8 235 .nonvolatile = fr->nonvolatile,
9c1f8f44
PB
236 };
237}
238
093bc2cd
AK
239static bool flatrange_equal(FlatRange *a, FlatRange *b)
240{
241 return a->mr == b->mr
242 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 243 && a->offset_in_region == b->offset_in_region
b138e654 244 && a->romd_mode == b->romd_mode
c26763f8
MAL
245 && a->readonly == b->readonly
246 && a->nonvolatile == b->nonvolatile;
093bc2cd
AK
247}
248
89c177bb 249static FlatView *flatview_new(MemoryRegion *mr_root)
093bc2cd 250{
cc94cd6d
AK
251 FlatView *view;
252
253 view = g_new0(FlatView, 1);
856d7245 254 view->ref = 1;
89c177bb
AK
255 view->root = mr_root;
256 memory_region_ref(mr_root);
02d9651d 257 trace_flatview_new(view, mr_root);
cc94cd6d
AK
258
259 return view;
093bc2cd
AK
260}
261
262/* Insert a range into a given position. Caller is responsible for maintaining
263 * sorting order.
264 */
265static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
266{
267 if (view->nr == view->nr_allocated) {
268 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 269 view->ranges = g_realloc(view->ranges,
093bc2cd
AK
270 view->nr_allocated * sizeof(*view->ranges));
271 }
272 memmove(view->ranges + pos + 1, view->ranges + pos,
273 (view->nr - pos) * sizeof(FlatRange));
274 view->ranges[pos] = *range;
dfde4e6e 275 memory_region_ref(range->mr);
093bc2cd
AK
276 ++view->nr;
277}
278
279static void flatview_destroy(FlatView *view)
280{
dfde4e6e
PB
281 int i;
282
02d9651d 283 trace_flatview_destroy(view, view->root);
66a6df1d
AK
284 if (view->dispatch) {
285 address_space_dispatch_free(view->dispatch);
286 }
dfde4e6e
PB
287 for (i = 0; i < view->nr; i++) {
288 memory_region_unref(view->ranges[i].mr);
289 }
7267c094 290 g_free(view->ranges);
89c177bb 291 memory_region_unref(view->root);
a9a0c06d 292 g_free(view);
093bc2cd
AK
293}
294
447b0d0b 295static bool flatview_ref(FlatView *view)
856d7245 296{
447b0d0b 297 return atomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB
298}
299
48564041 300void flatview_unref(FlatView *view)
856d7245
PB
301{
302 if (atomic_fetch_dec(&view->ref) == 1) {
02d9651d 303 trace_flatview_destroy_rcu(view, view->root);
092aa2fc 304 assert(view->root);
66a6df1d 305 call_rcu(view, flatview_destroy, rcu);
856d7245
PB
306 }
307}
308
3d8e6bf9
AK
309static bool can_merge(FlatRange *r1, FlatRange *r2)
310{
08dafab4 311 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 312 && r1->mr == r2->mr
08dafab4
AK
313 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
314 r1->addr.size),
315 int128_make64(r2->offset_in_region))
d0a9b5bc 316 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 317 && r1->romd_mode == r2->romd_mode
c26763f8
MAL
318 && r1->readonly == r2->readonly
319 && r1->nonvolatile == r2->nonvolatile;
3d8e6bf9
AK
320}
321
8508e024 322/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK
323static void flatview_simplify(FlatView *view)
324{
325 unsigned i, j;
326
327 i = 0;
328 while (i < view->nr) {
329 j = i + 1;
330 while (j < view->nr
331 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 332 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
AK
333 ++j;
334 }
335 ++i;
336 memmove(&view->ranges[i], &view->ranges[j],
337 (view->nr - j) * sizeof(view->ranges[j]));
338 view->nr -= j - i;
339 }
340}
341
e7342aa3
PB
342static bool memory_region_big_endian(MemoryRegion *mr)
343{
344#ifdef TARGET_WORDS_BIGENDIAN
345 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
346#else
347 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
348#endif
349}
350
e11ef3d1
PB
351static bool memory_region_wrong_endianness(MemoryRegion *mr)
352{
353#ifdef TARGET_WORDS_BIGENDIAN
354 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
355#else
356 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
357#endif
358}
359
360static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
361{
362 if (memory_region_wrong_endianness(mr)) {
363 switch (size) {
364 case 1:
365 break;
366 case 2:
367 *data = bswap16(*data);
368 break;
369 case 4:
370 *data = bswap32(*data);
371 break;
372 case 8:
373 *data = bswap64(*data);
374 break;
375 default:
376 abort();
377 }
378 }
379}
380
3c754a93 381static inline void memory_region_shift_read_access(uint64_t *value,
98f52cdb 382 signed shift,
3c754a93
PMD
383 uint64_t mask,
384 uint64_t tmp)
385{
98f52cdb
PMD
386 if (shift >= 0) {
387 *value |= (tmp & mask) << shift;
388 } else {
389 *value |= (tmp & mask) >> -shift;
390 }
3c754a93
PMD
391}
392
393static inline uint64_t memory_region_shift_write_access(uint64_t *value,
98f52cdb 394 signed shift,
3c754a93
PMD
395 uint64_t mask)
396{
98f52cdb
PMD
397 uint64_t tmp;
398
399 if (shift >= 0) {
400 tmp = (*value >> shift) & mask;
401 } else {
402 tmp = (*value << -shift) & mask;
403 }
404
405 return tmp;
3c754a93
PMD
406}
407
4779dc1d
HB
408static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
409{
410 MemoryRegion *root;
411 hwaddr abs_addr = offset;
412
413 abs_addr += mr->addr;
414 for (root = mr; root->container; ) {
415 root = root->container;
416 abs_addr += root->addr;
417 }
418
419 return abs_addr;
420}
421
5a68be94
HB
422static int get_cpu_index(void)
423{
424 if (current_cpu) {
425 return current_cpu->cpu_index;
426 }
427 return -1;
428}
429
cc05c43a 430static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB
431 hwaddr addr,
432 uint64_t *value,
433 unsigned size,
98f52cdb 434 signed shift,
cc05c43a
PM
435 uint64_t mask,
436 MemTxAttrs attrs)
ce5d2f33 437{
ce5d2f33
PB
438 uint64_t tmp;
439
cc05c43a 440 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 441 if (mr->subpage) {
5a68be94 442 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
443 } else if (mr == &io_mem_notdirty) {
444 /* Accesses to code which has previously been translated into a TB show
445 * up in the MMIO path, as accesses to the io_mem_notdirty
446 * MemoryRegion. */
447 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
448 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
449 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 450 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 451 }
3c754a93 452 memory_region_shift_read_access(value, shift, mask, tmp);
cc05c43a 453 return MEMTX_OK;
ce5d2f33
PB
454}
455
cc05c43a
PM
456static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
457 hwaddr addr,
458 uint64_t *value,
459 unsigned size,
98f52cdb 460 signed shift,
cc05c43a
PM
461 uint64_t mask,
462 MemTxAttrs attrs)
164a4dcd 463{
cc05c43a
PM
464 uint64_t tmp = 0;
465 MemTxResult r;
164a4dcd 466
cc05c43a 467 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 468 if (mr->subpage) {
5a68be94 469 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
470 } else if (mr == &io_mem_notdirty) {
471 /* Accesses to code which has previously been translated into a TB show
472 * up in the MMIO path, as accesses to the io_mem_notdirty
473 * MemoryRegion. */
474 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
475 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
476 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 477 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 478 }
3c754a93 479 memory_region_shift_read_access(value, shift, mask, tmp);
cc05c43a 480 return r;
164a4dcd
AK
481}
482
cc05c43a
PM
483static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
484 hwaddr addr,
485 uint64_t *value,
486 unsigned size,
98f52cdb 487 signed shift,
cc05c43a
PM
488 uint64_t mask,
489 MemTxAttrs attrs)
164a4dcd 490{
3c754a93 491 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
164a4dcd 492
23d92d68 493 if (mr->subpage) {
5a68be94 494 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
495 } else if (mr == &io_mem_notdirty) {
496 /* Accesses to code which has previously been translated into a TB show
497 * up in the MMIO path, as accesses to the io_mem_notdirty
498 * MemoryRegion. */
499 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
500 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
501 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 502 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 503 }
164a4dcd 504 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 505 return MEMTX_OK;
164a4dcd
AK
506}
507
cc05c43a
PM
508static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
509 hwaddr addr,
510 uint64_t *value,
511 unsigned size,
98f52cdb 512 signed shift,
cc05c43a
PM
513 uint64_t mask,
514 MemTxAttrs attrs)
515{
3c754a93 516 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
cc05c43a 517
23d92d68 518 if (mr->subpage) {
5a68be94 519 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
520 } else if (mr == &io_mem_notdirty) {
521 /* Accesses to code which has previously been translated into a TB show
522 * up in the MMIO path, as accesses to the io_mem_notdirty
523 * MemoryRegion. */
524 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
525 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
526 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 527 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 528 }
cc05c43a
PM
529 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
530}
531
532static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK
533 uint64_t *value,
534 unsigned size,
535 unsigned access_size_min,
536 unsigned access_size_max,
05e015f7
KF
537 MemTxResult (*access_fn)
538 (MemoryRegion *mr,
539 hwaddr addr,
540 uint64_t *value,
541 unsigned size,
98f52cdb 542 signed shift,
05e015f7
KF
543 uint64_t mask,
544 MemTxAttrs attrs),
cc05c43a
PM
545 MemoryRegion *mr,
546 MemTxAttrs attrs)
164a4dcd
AK
547{
548 uint64_t access_mask;
549 unsigned access_size;
550 unsigned i;
cc05c43a 551 MemTxResult r = MEMTX_OK;
164a4dcd
AK
552
553 if (!access_size_min) {
554 access_size_min = 1;
555 }
556 if (!access_size_max) {
557 access_size_max = 4;
558 }
ce5d2f33
PB
559
560 /* FIXME: support unaligned access? */
164a4dcd 561 access_size = MAX(MIN(size, access_size_max), access_size_min);
36960b4d 562 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
e7342aa3
PB
563 if (memory_region_big_endian(mr)) {
564 for (i = 0; i < size; i += access_size) {
05e015f7 565 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 566 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB
567 }
568 } else {
569 for (i = 0; i < size; i += access_size) {
05e015f7 570 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 571 access_mask, attrs);
e7342aa3 572 }
164a4dcd 573 }
cc05c43a 574 return r;
164a4dcd
AK
575}
576
e2177955
AK
577static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
578{
0d673e36
AK
579 AddressSpace *as;
580
feca4ac1
PB
581 while (mr->container) {
582 mr = mr->container;
e2177955 583 }
0d673e36
AK
584 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
585 if (mr == as->root) {
586 return as;
587 }
e2177955 588 }
eed2bacf 589 return NULL;
e2177955
AK
590}
591
093bc2cd
AK
592/* Render a memory region into the global view. Ranges in @view obscure
593 * ranges in @mr.
594 */
595static void render_memory_region(FlatView *view,
596 MemoryRegion *mr,
08dafab4 597 Int128 base,
fb1cd6f9 598 AddrRange clip,
c26763f8
MAL
599 bool readonly,
600 bool nonvolatile)
093bc2cd
AK
601{
602 MemoryRegion *subregion;
603 unsigned i;
a8170e5e 604 hwaddr offset_in_region;
08dafab4
AK
605 Int128 remain;
606 Int128 now;
093bc2cd
AK
607 FlatRange fr;
608 AddrRange tmp;
609
6bba19ba
AK
610 if (!mr->enabled) {
611 return;
612 }
613
08dafab4 614 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 615 readonly |= mr->readonly;
c26763f8 616 nonvolatile |= mr->nonvolatile;
093bc2cd
AK
617
618 tmp = addrrange_make(base, mr->size);
619
620 if (!addrrange_intersects(tmp, clip)) {
621 return;
622 }
623
624 clip = addrrange_intersection(tmp, clip);
625
626 if (mr->alias) {
08dafab4
AK
627 int128_subfrom(&base, int128_make64(mr->alias->addr));
628 int128_subfrom(&base, int128_make64(mr->alias_offset));
c26763f8
MAL
629 render_memory_region(view, mr->alias, base, clip,
630 readonly, nonvolatile);
093bc2cd
AK
631 return;
632 }
633
634 /* Render subregions in priority order. */
635 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
c26763f8
MAL
636 render_memory_region(view, subregion, base, clip,
637 readonly, nonvolatile);
093bc2cd
AK
638 }
639
14a3c10a 640 if (!mr->terminates) {
093bc2cd
AK
641 return;
642 }
643
08dafab4 644 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK
645 base = clip.start;
646 remain = clip.size;
647
2eb74e1a 648 fr.mr = mr;
6f6a5ef3 649 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 650 fr.romd_mode = mr->romd_mode;
2eb74e1a 651 fr.readonly = readonly;
c26763f8 652 fr.nonvolatile = nonvolatile;
2eb74e1a 653
093bc2cd 654 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK
655 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
656 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK
657 continue;
658 }
08dafab4
AK
659 if (int128_lt(base, view->ranges[i].addr.start)) {
660 now = int128_min(remain,
661 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK
662 fr.offset_in_region = offset_in_region;
663 fr.addr = addrrange_make(base, now);
664 flatview_insert(view, i, &fr);
665 ++i;
08dafab4
AK
666 int128_addto(&base, now);
667 offset_in_region += int128_get64(now);
668 int128_subfrom(&remain, now);
093bc2cd 669 }
d26a8cae
AK
670 now = int128_sub(int128_min(int128_add(base, remain),
671 addrrange_end(view->ranges[i].addr)),
672 base);
673 int128_addto(&base, now);
674 offset_in_region += int128_get64(now);
675 int128_subfrom(&remain, now);
093bc2cd 676 }
08dafab4 677 if (int128_nz(remain)) {
093bc2cd
AK
678 fr.offset_in_region = offset_in_region;
679 fr.addr = addrrange_make(base, remain);
680 flatview_insert(view, i, &fr);
681 }
682}
683
89c177bb
AK
684static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
685{
e673ba9a
PB
686 while (mr->enabled) {
687 if (mr->alias) {
688 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
689 /* The alias is included in its entirety. Use it as
690 * the "real" root, so that we can share more FlatViews.
691 */
692 mr = mr->alias;
693 continue;
694 }
695 } else if (!mr->terminates) {
696 unsigned int found = 0;
697 MemoryRegion *child, *next = NULL;
698 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
699 if (child->enabled) {
700 if (++found > 1) {
701 next = NULL;
702 break;
703 }
704 if (!child->addr && int128_ge(mr->size, child->size)) {
705 /* A child is included in its entirety. If it's the only
706 * enabled one, use it in the hope of finding an alias down the
707 * way. This will also let us share FlatViews.
708 */
709 next = child;
710 }
711 }
712 }
092aa2fc
AK
713 if (found == 0) {
714 return NULL;
715 }
e673ba9a
PB
716 if (next) {
717 mr = next;
718 continue;
719 }
720 }
721
092aa2fc 722 return mr;
89c177bb
AK
723 }
724
092aa2fc 725 return NULL;
89c177bb
AK
726}
727
093bc2cd 728/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 729static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 730{
9bf561e3 731 int i;
a9a0c06d 732 FlatView *view;
093bc2cd 733
89c177bb 734 view = flatview_new(mr);
093bc2cd 735
83f3c251 736 if (mr) {
a9a0c06d 737 render_memory_region(view, mr, int128_zero(),
c26763f8
MAL
738 addrrange_make(int128_zero(), int128_2_64()),
739 false, false);
83f3c251 740 }
a9a0c06d 741 flatview_simplify(view);
093bc2cd 742
9bf561e3
AK
743 view->dispatch = address_space_dispatch_new(view);
744 for (i = 0; i < view->nr; i++) {
745 MemoryRegionSection mrs =
746 section_from_flat_range(&view->ranges[i], view);
747 flatview_add_to_dispatch(view, &mrs);
748 }
749 address_space_dispatch_compact(view->dispatch);
967dc9b1 750 g_hash_table_replace(flat_views, mr, view);
9bf561e3 751
093bc2cd
AK
752 return view;
753}
754
3e9d69e7
AK
755static void address_space_add_del_ioeventfds(AddressSpace *as,
756 MemoryRegionIoeventfd *fds_new,
757 unsigned fds_new_nb,
758 MemoryRegionIoeventfd *fds_old,
759 unsigned fds_old_nb)
760{
761 unsigned iold, inew;
80a1ea37
AK
762 MemoryRegionIoeventfd *fd;
763 MemoryRegionSection section;
3e9d69e7
AK
764
765 /* Generate a symmetric difference of the old and new fd sets, adding
766 * and deleting as necessary.
767 */
768
769 iold = inew = 0;
770 while (iold < fds_old_nb || inew < fds_new_nb) {
771 if (iold < fds_old_nb
772 && (inew == fds_new_nb
73bb753d
TB
773 || memory_region_ioeventfd_before(&fds_old[iold],
774 &fds_new[inew]))) {
80a1ea37
AK
775 fd = &fds_old[iold];
776 section = (MemoryRegionSection) {
16620684 777 .fv = address_space_to_flatview(as),
80a1ea37 778 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 779 .size = fd->addr.size,
80a1ea37 780 };
9a54635d 781 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 782 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
783 ++iold;
784 } else if (inew < fds_new_nb
785 && (iold == fds_old_nb
73bb753d
TB
786 || memory_region_ioeventfd_before(&fds_new[inew],
787 &fds_old[iold]))) {
80a1ea37
AK
788 fd = &fds_new[inew];
789 section = (MemoryRegionSection) {
16620684 790 .fv = address_space_to_flatview(as),
80a1ea37 791 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 792 .size = fd->addr.size,
80a1ea37 793 };
9a54635d 794 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 795 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
796 ++inew;
797 } else {
798 ++iold;
799 ++inew;
800 }
801 }
802}
803
48564041 804FlatView *address_space_get_flatview(AddressSpace *as)
856d7245
PB
805{
806 FlatView *view;
807
374f2981 808 rcu_read_lock();
447b0d0b 809 do {
16620684 810 view = address_space_to_flatview(as);
447b0d0b
PB
811 /* If somebody has replaced as->current_map concurrently,
812 * flatview_ref returns false.
813 */
814 } while (!flatview_ref(view));
374f2981 815 rcu_read_unlock();
856d7245
PB
816 return view;
817}
818
3e9d69e7
AK
819static void address_space_update_ioeventfds(AddressSpace *as)
820{
99e86347 821 FlatView *view;
3e9d69e7
AK
822 FlatRange *fr;
823 unsigned ioeventfd_nb = 0;
824 MemoryRegionIoeventfd *ioeventfds = NULL;
825 AddrRange tmp;
826 unsigned i;
827
856d7245 828 view = address_space_get_flatview(as);
99e86347 829 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK
830 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
831 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK
832 int128_sub(fr->addr.start,
833 int128_make64(fr->offset_in_region)));
3e9d69e7
AK
834 if (addrrange_intersects(fr->addr, tmp)) {
835 ++ioeventfd_nb;
7267c094 836 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK
837 ioeventfd_nb * sizeof(*ioeventfds));
838 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
839 ioeventfds[ioeventfd_nb-1].addr = tmp;
840 }
841 }
842 }
843
844 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
845 as->ioeventfds, as->ioeventfd_nb);
846
7267c094 847 g_free(as->ioeventfds);
3e9d69e7
AK
848 as->ioeventfds = ioeventfds;
849 as->ioeventfd_nb = ioeventfd_nb;
856d7245 850 flatview_unref(view);
3e9d69e7
AK
851}
852
909bf763
PB
853static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
854{
855 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
856 int128_get64(fr->addr.start),
857 int128_get64(fr->addr.size));
858}
859
860static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
861{
862 MemoryRegion *mr = fr->mr;
863 CoalescedMemoryRange *cmr;
864 AddrRange tmp;
865
866 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
867 tmp = addrrange_shift(cmr->addr,
868 int128_sub(fr->addr.start,
869 int128_make64(fr->offset_in_region)));
870 if (!addrrange_intersects(tmp, fr->addr)) {
871 continue;
872 }
873 tmp = addrrange_intersection(tmp, fr->addr);
874 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
875 int128_get64(tmp.start),
876 int128_get64(tmp.size));
877 }
878}
879
b8af1afb 880static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB
881 const FlatView *old_view,
882 const FlatView *new_view,
b8af1afb 883 bool adding)
093bc2cd 884{
093bc2cd
AK
885 unsigned iold, inew;
886 FlatRange *frold, *frnew;
093bc2cd
AK
887
888 /* Generate a symmetric difference of the old and new memory maps.
889 * Kill ranges in the old map, and instantiate ranges in the new map.
890 */
891 iold = inew = 0;
a9a0c06d
PB
892 while (iold < old_view->nr || inew < new_view->nr) {
893 if (iold < old_view->nr) {
894 frold = &old_view->ranges[iold];
093bc2cd
AK
895 } else {
896 frold = NULL;
897 }
a9a0c06d
PB
898 if (inew < new_view->nr) {
899 frnew = &new_view->ranges[inew];
093bc2cd
AK
900 } else {
901 frnew = NULL;
902 }
903
904 if (frold
905 && (!frnew
08dafab4
AK
906 || int128_lt(frold->addr.start, frnew->addr.start)
907 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 908 && !flatrange_equal(frold, frnew)))) {
41a6e477 909 /* In old but not in new, or in both but attributes changed. */
093bc2cd 910
b8af1afb 911 if (!adding) {
72e22d2f 912 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK
913 }
914
093bc2cd
AK
915 ++iold;
916 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 917 /* In both and unchanged (except logging may have changed) */
093bc2cd 918
b8af1afb 919 if (adding) {
50c1e149 920 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB
921 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
922 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
923 frold->dirty_log_mask,
924 frnew->dirty_log_mask);
925 }
926 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
927 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
928 frold->dirty_log_mask,
929 frnew->dirty_log_mask);
b8af1afb 930 }
5a583347
AK
931 }
932
093bc2cd
AK
933 ++iold;
934 ++inew;
093bc2cd
AK
935 } else {
936 /* In new */
937
b8af1afb 938 if (adding) {
72e22d2f 939 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK
940 }
941
093bc2cd
AK
942 ++inew;
943 }
944 }
b8af1afb
AK
945}
946
967dc9b1
AK
947static void flatviews_init(void)
948{
092aa2fc
AK
949 static FlatView *empty_view;
950
967dc9b1
AK
951 if (flat_views) {
952 return;
953 }
954
955 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
956 (GDestroyNotify) flatview_unref);
092aa2fc
AK
957 if (!empty_view) {
958 empty_view = generate_memory_topology(NULL);
959 /* We keep it alive forever in the global variable. */
960 flatview_ref(empty_view);
961 } else {
962 g_hash_table_replace(flat_views, NULL, empty_view);
963 flatview_ref(empty_view);
964 }
967dc9b1
AK
965}
966
967static void flatviews_reset(void)
968{
969 AddressSpace *as;
970
971 if (flat_views) {
972 g_hash_table_unref(flat_views);
973 flat_views = NULL;
974 }
975 flatviews_init();
976
977 /* Render unique FVs */
978 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
979 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
980
981 if (g_hash_table_lookup(flat_views, physmr)) {
982 continue;
983 }
984
985 generate_memory_topology(physmr);
986 }
987}
988
989static void address_space_set_flatview(AddressSpace *as)
b8af1afb 990{
67ace39b 991 FlatView *old_view = address_space_to_flatview(as);
967dc9b1
AK
992 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
993 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
994
995 assert(new_view);
996
67ace39b
AK
997 if (old_view == new_view) {
998 return;
999 }
1000
1001 if (old_view) {
1002 flatview_ref(old_view);
1003 }
1004
967dc9b1 1005 flatview_ref(new_view);
9a62e24f
AK
1006
1007 if (!QTAILQ_EMPTY(&as->listeners)) {
67ace39b
AK
1008 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1009
1010 if (!old_view2) {
1011 old_view2 = &tmpview;
1012 }
1013 address_space_update_topology_pass(as, old_view2, new_view, false);
1014 address_space_update_topology_pass(as, old_view2, new_view, true);
9a62e24f 1015 }
b8af1afb 1016
374f2981
PB
1017 /* Writes are protected by the BQL. */
1018 atomic_rcu_set(&as->current_map, new_view);
67ace39b
AK
1019 if (old_view) {
1020 flatview_unref(old_view);
1021 }
856d7245
PB
1022
1023 /* Note that all the old MemoryRegions are still alive up to this
1024 * point. This relieves most MemoryListeners from the need to
1025 * ref/unref the MemoryRegions they get---unless they use them
1026 * outside the iothread mutex, in which case precise reference
1027 * counting is necessary.
1028 */
67ace39b
AK
1029 if (old_view) {
1030 flatview_unref(old_view);
1031 }
093bc2cd
AK
1032}
1033
202fc01b
AK
1034static void address_space_update_topology(AddressSpace *as)
1035{
1036 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1037
1038 flatviews_init();
1039 if (!g_hash_table_lookup(flat_views, physmr)) {
1040 generate_memory_topology(physmr);
1041 }
1042 address_space_set_flatview(as);
1043}
1044
4ef4db86
AK
1045void memory_region_transaction_begin(void)
1046{
bb880ded 1047 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK
1048 ++memory_region_transaction_depth;
1049}
1050
1051void memory_region_transaction_commit(void)
1052{
0d673e36
AK
1053 AddressSpace *as;
1054
4ef4db86 1055 assert(memory_region_transaction_depth);
8d04fb55
JK
1056 assert(qemu_mutex_iothread_locked());
1057
4ef4db86 1058 --memory_region_transaction_depth;
4dc56152
GA
1059 if (!memory_region_transaction_depth) {
1060 if (memory_region_update_pending) {
967dc9b1
AK
1061 flatviews_reset();
1062
4dc56152 1063 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 1064
4dc56152 1065 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
967dc9b1 1066 address_space_set_flatview(as);
02218487 1067 address_space_update_ioeventfds(as);
4dc56152 1068 }
ade9c1aa 1069 memory_region_update_pending = false;
0b152095 1070 ioeventfd_update_pending = false;
4dc56152
GA
1071 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1072 } else if (ioeventfd_update_pending) {
1073 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1074 address_space_update_ioeventfds(as);
1075 }
ade9c1aa 1076 ioeventfd_update_pending = false;
4dc56152 1077 }
4dc56152 1078 }
4ef4db86
AK
1079}
1080
545e92e0
AK
1081static void memory_region_destructor_none(MemoryRegion *mr)
1082{
1083}
1084
1085static void memory_region_destructor_ram(MemoryRegion *mr)
1086{
f1060c55 1087 qemu_ram_free(mr->ram_block);
545e92e0
AK
1088}
1089
b4fefef9
PC
1090static bool memory_region_need_escape(char c)
1091{
1092 return c == '/' || c == '[' || c == '\\' || c == ']';
1093}
1094
1095static char *memory_region_escape_name(const char *name)
1096{
1097 const char *p;
1098 char *escaped, *q;
1099 uint8_t c;
1100 size_t bytes = 0;
1101
1102 for (p = name; *p; p++) {
1103 bytes += memory_region_need_escape(*p) ? 4 : 1;
1104 }
1105 if (bytes == p - name) {
1106 return g_memdup(name, bytes + 1);
1107 }
1108
1109 escaped = g_malloc(bytes + 1);
1110 for (p = name, q = escaped; *p; p++) {
1111 c = *p;
1112 if (unlikely(memory_region_need_escape(c))) {
1113 *q++ = '\\';
1114 *q++ = 'x';
1115 *q++ = "0123456789abcdef"[c >> 4];
1116 c = "0123456789abcdef"[c & 15];
1117 }
1118 *q++ = c;
1119 }
1120 *q = 0;
1121 return escaped;
1122}
1123
3df9d748
AK
1124static void memory_region_do_init(MemoryRegion *mr,
1125 Object *owner,
1126 const char *name,
1127 uint64_t size)
093bc2cd 1128{
08dafab4
AK
1129 mr->size = int128_make64(size);
1130 if (size == UINT64_MAX) {
1131 mr->size = int128_2_64();
1132 }
302fa283 1133 mr->name = g_strdup(name);
612263cf 1134 mr->owner = owner;
58eaa217 1135 mr->ram_block = NULL;
b4fefef9
PC
1136
1137 if (name) {
843ef73a
PC
1138 char *escaped_name = memory_region_escape_name(name);
1139 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB
1140
1141 if (!owner) {
1142 owner = container_get(qdev_get_machine(), "/unattached");
1143 }
1144
843ef73a 1145 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1146 object_unref(OBJECT(mr));
843ef73a
PC
1147 g_free(name_array);
1148 g_free(escaped_name);
b4fefef9
PC
1149 }
1150}
1151
3df9d748
AK
1152void memory_region_init(MemoryRegion *mr,
1153 Object *owner,
1154 const char *name,
1155 uint64_t size)
1156{
1157 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1158 memory_region_do_init(mr, owner, name, size);
1159}
1160
d7bce999
EB
1161static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1162 void *opaque, Error **errp)
409ddd01
PC
1163{
1164 MemoryRegion *mr = MEMORY_REGION(obj);
1165 uint64_t value = mr->addr;
1166
51e72bc1 1167 visit_type_uint64(v, name, &value, errp);
409ddd01
PC
1168}
1169
d7bce999
EB
1170static void memory_region_get_container(Object *obj, Visitor *v,
1171 const char *name, void *opaque,
1172 Error **errp)
409ddd01
PC
1173{
1174 MemoryRegion *mr = MEMORY_REGION(obj);
1175 gchar *path = (gchar *)"";
1176
1177 if (mr->container) {
1178 path = object_get_canonical_path(OBJECT(mr->container));
1179 }
51e72bc1 1180 visit_type_str(v, name, &path, errp);
409ddd01
PC
1181 if (mr->container) {
1182 g_free(path);
1183 }
1184}
1185
1186static Object *memory_region_resolve_container(Object *obj, void *opaque,
1187 const char *part)
1188{
1189 MemoryRegion *mr = MEMORY_REGION(obj);
1190
1191 return OBJECT(mr->container);
1192}
1193
d7bce999
EB
1194static void memory_region_get_priority(Object *obj, Visitor *v,
1195 const char *name, void *opaque,
1196 Error **errp)
d33382da
PC
1197{
1198 MemoryRegion *mr = MEMORY_REGION(obj);
1199 int32_t value = mr->priority;
1200
51e72bc1 1201 visit_type_int32(v, name, &value, errp);
d33382da
PC
1202}
1203
d7bce999
EB
1204static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1205 void *opaque, Error **errp)
52aef7bb
PC
1206{
1207 MemoryRegion *mr = MEMORY_REGION(obj);
1208 uint64_t value = memory_region_size(mr);
1209
51e72bc1 1210 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC
1211}
1212
b4fefef9
PC
1213static void memory_region_initfn(Object *obj)
1214{
1215 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1216 ObjectProperty *op;
b4fefef9
PC
1217
1218 mr->ops = &unassigned_mem_ops;
6bba19ba 1219 mr->enabled = true;
5f9a5ea1 1220 mr->romd_mode = true;
196ea131 1221 mr->global_locking = true;
545e92e0 1222 mr->destructor = memory_region_destructor_none;
093bc2cd 1223 QTAILQ_INIT(&mr->subregions);
093bc2cd 1224 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC
1225
1226 op = object_property_add(OBJECT(mr), "container",
1227 "link<" TYPE_MEMORY_REGION ">",
1228 memory_region_get_container,
1229 NULL, /* memory_region_set_container */
1230 NULL, NULL, &error_abort);
1231 op->resolve = memory_region_resolve_container;
1232
1233 object_property_add(OBJECT(mr), "addr", "uint64",
1234 memory_region_get_addr,
1235 NULL, /* memory_region_set_addr */
1236 NULL, NULL, &error_abort);
d33382da
PC
1237 object_property_add(OBJECT(mr), "priority", "uint32",
1238 memory_region_get_priority,
1239 NULL, /* memory_region_set_priority */
1240 NULL, NULL, &error_abort);
52aef7bb
PC
1241 object_property_add(OBJECT(mr), "size", "uint64",
1242 memory_region_get_size,
1243 NULL, /* memory_region_set_size, */
1244 NULL, NULL, &error_abort);
093bc2cd
AK
1245}
1246
3df9d748
AK
1247static void iommu_memory_region_initfn(Object *obj)
1248{
1249 MemoryRegion *mr = MEMORY_REGION(obj);
1250
1251 mr->is_iommu = true;
1252}
1253
b018ddf6
PB
1254static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1255 unsigned size)
1256{
1257#ifdef DEBUG_UNASSIGNED
1258 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1259#endif
4917cf44 1260 if (current_cpu != NULL) {
dbea78a4
PM
1261 bool is_exec = current_cpu->mem_io_access_type == MMU_INST_FETCH;
1262 cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size);
c658b94f 1263 }
68a7439a 1264 return 0;
b018ddf6
PB
1265}
1266
1267static void unassigned_mem_write(void *opaque, hwaddr addr,
1268 uint64_t val, unsigned size)
1269{
1270#ifdef DEBUG_UNASSIGNED
1271 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1272#endif
4917cf44
AF
1273 if (current_cpu != NULL) {
1274 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1275 }
b018ddf6
PB
1276}
1277
d197063f 1278static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
8372d383
PM
1279 unsigned size, bool is_write,
1280 MemTxAttrs attrs)
d197063f
PB
1281{
1282 return false;
1283}
1284
1285const MemoryRegionOps unassigned_mem_ops = {
1286 .valid.accepts = unassigned_mem_accepts,
1287 .endianness = DEVICE_NATIVE_ENDIAN,
1288};
1289
4a2e242b
AW
1290static uint64_t memory_region_ram_device_read(void *opaque,
1291 hwaddr addr, unsigned size)
1292{
1293 MemoryRegion *mr = opaque;
1294 uint64_t data = (uint64_t)~0;
1295
1296 switch (size) {
1297 case 1:
1298 data = *(uint8_t *)(mr->ram_block->host + addr);
1299 break;
1300 case 2:
1301 data = *(uint16_t *)(mr->ram_block->host + addr);
1302 break;
1303 case 4:
1304 data = *(uint32_t *)(mr->ram_block->host + addr);
1305 break;
1306 case 8:
1307 data = *(uint64_t *)(mr->ram_block->host + addr);
1308 break;
1309 }
1310
1311 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1312
1313 return data;
1314}
1315
1316static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1317 uint64_t data, unsigned size)
1318{
1319 MemoryRegion *mr = opaque;
1320
1321 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1322
1323 switch (size) {
1324 case 1:
1325 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1326 break;
1327 case 2:
1328 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1329 break;
1330 case 4:
1331 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1332 break;
1333 case 8:
1334 *(uint64_t *)(mr->ram_block->host + addr) = data;
1335 break;
1336 }
1337}
1338
1339static const MemoryRegionOps ram_device_mem_ops = {
1340 .read = memory_region_ram_device_read,
1341 .write = memory_region_ram_device_write,
c99a29e7 1342 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW
1343 .valid = {
1344 .min_access_size = 1,
1345 .max_access_size = 8,
1346 .unaligned = true,
1347 },
1348 .impl = {
1349 .min_access_size = 1,
1350 .max_access_size = 8,
1351 .unaligned = true,
1352 },
1353};
1354
d2702032
PB
1355bool memory_region_access_valid(MemoryRegion *mr,
1356 hwaddr addr,
1357 unsigned size,
6d7b9a6c
PM
1358 bool is_write,
1359 MemTxAttrs attrs)
093bc2cd 1360{
a014ed07
PB
1361 int access_size_min, access_size_max;
1362 int access_size, i;
897fa7cf 1363
093bc2cd
AK
1364 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1365 return false;
1366 }
1367
a014ed07 1368 if (!mr->ops->valid.accepts) {
093bc2cd
AK
1369 return true;
1370 }
1371
a014ed07
PB
1372 access_size_min = mr->ops->valid.min_access_size;
1373 if (!mr->ops->valid.min_access_size) {
1374 access_size_min = 1;
1375 }
1376
1377 access_size_max = mr->ops->valid.max_access_size;
1378 if (!mr->ops->valid.max_access_size) {
1379 access_size_max = 4;
1380 }
1381
1382 access_size = MAX(MIN(size, access_size_max), access_size_min);
1383 for (i = 0; i < size; i += access_size) {
1384 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
8372d383 1385 is_write, attrs)) {
a014ed07
PB
1386 return false;
1387 }
093bc2cd 1388 }
a014ed07 1389
093bc2cd
AK
1390 return true;
1391}
1392
cc05c43a
PM
1393static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1394 hwaddr addr,
1395 uint64_t *pval,
1396 unsigned size,
1397 MemTxAttrs attrs)
093bc2cd 1398{
cc05c43a 1399 *pval = 0;
093bc2cd 1400
ce5d2f33 1401 if (mr->ops->read) {
cc05c43a
PM
1402 return access_with_adjusted_size(addr, pval, size,
1403 mr->ops->impl.min_access_size,
1404 mr->ops->impl.max_access_size,
1405 memory_region_read_accessor,
1406 mr, attrs);
62a0db94 1407 } else {
cc05c43a
PM
1408 return access_with_adjusted_size(addr, pval, size,
1409 mr->ops->impl.min_access_size,
1410 mr->ops->impl.max_access_size,
1411 memory_region_read_with_attrs_accessor,
1412 mr, attrs);
74901c3b 1413 }
093bc2cd
AK
1414}
1415
3b643495
PM
1416MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1417 hwaddr addr,
1418 uint64_t *pval,
1419 unsigned size,
1420 MemTxAttrs attrs)
a621f38d 1421{
cc05c43a
PM
1422 MemTxResult r;
1423
6d7b9a6c 1424 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
791af8c8 1425 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1426 return MEMTX_DECODE_ERROR;
791af8c8 1427 }
a621f38d 1428
cc05c43a 1429 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1430 adjust_endianness(mr, pval, size);
cc05c43a 1431 return r;
a621f38d 1432}
093bc2cd 1433
8c56c1a5
PF
1434/* Return true if an eventfd was signalled */
1435static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1436 hwaddr addr,
1437 uint64_t data,
1438 unsigned size,
1439 MemTxAttrs attrs)
1440{
1441 MemoryRegionIoeventfd ioeventfd = {
1442 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1443 .data = data,
1444 };
1445 unsigned i;
1446
1447 for (i = 0; i < mr->ioeventfd_nb; i++) {
1448 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1449 ioeventfd.e = mr->ioeventfds[i].e;
1450
73bb753d 1451 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
8c56c1a5
PF
1452 event_notifier_set(ioeventfd.e);
1453 return true;
1454 }
1455 }
1456
1457 return false;
1458}
1459
3b643495
PM
1460MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1461 hwaddr addr,
1462 uint64_t data,
1463 unsigned size,
1464 MemTxAttrs attrs)
a621f38d 1465{
6d7b9a6c 1466 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
b018ddf6 1467 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1468 return MEMTX_DECODE_ERROR;
093bc2cd
AK
1469 }
1470
a621f38d
AK
1471 adjust_endianness(mr, &data, size);
1472
8c56c1a5
PF
1473 if ((!kvm_eventfds_enabled()) &&
1474 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1475 return MEMTX_OK;
1476 }
1477
ce5d2f33 1478 if (mr->ops->write) {
cc05c43a
PM
1479 return access_with_adjusted_size(addr, &data, size,
1480 mr->ops->impl.min_access_size,
1481 mr->ops->impl.max_access_size,
1482 memory_region_write_accessor, mr,
1483 attrs);
62a0db94 1484 } else {
cc05c43a
PM
1485 return
1486 access_with_adjusted_size(addr, &data, size,
1487 mr->ops->impl.min_access_size,
1488 mr->ops->impl.max_access_size,
1489 memory_region_write_with_attrs_accessor,
1490 mr, attrs);
74901c3b 1491 }
093bc2cd
AK
1492}
1493
093bc2cd 1494void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1495 Object *owner,
093bc2cd
AK
1496 const MemoryRegionOps *ops,
1497 void *opaque,
1498 const char *name,
1499 uint64_t size)
1500{
2c9b15ca 1501 memory_region_init(mr, owner, name, size);
6d6d2abf 1502 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1503 mr->opaque = opaque;
14a3c10a 1504 mr->terminates = true;
093bc2cd
AK
1505}
1506
1cfe48c1
PM
1507void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1508 Object *owner,
1509 const char *name,
1510 uint64_t size,
1511 Error **errp)
06329cce
MA
1512{
1513 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1514}
1515
1516void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1517 Object *owner,
1518 const char *name,
1519 uint64_t size,
1520 bool share,
1521 Error **errp)
093bc2cd 1522{
1cd3d492 1523 Error *err = NULL;
2c9b15ca 1524 memory_region_init(mr, owner, name, size);
8ea9252a 1525 mr->ram = true;
14a3c10a 1526 mr->terminates = true;
545e92e0 1527 mr->destructor = memory_region_destructor_ram;
1cd3d492 1528 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
677e7805 1529 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1530 if (err) {
1531 mr->size = int128_zero();
1532 object_unparent(OBJECT(mr));
1533 error_propagate(errp, err);
1534 }
0b183fc8
PB
1535}
1536
60786ef3
MT
1537void memory_region_init_resizeable_ram(MemoryRegion *mr,
1538 Object *owner,
1539 const char *name,
1540 uint64_t size,
1541 uint64_t max_size,
1542 void (*resized)(const char*,
1543 uint64_t length,
1544 void *host),
1545 Error **errp)
1546{
1cd3d492 1547 Error *err = NULL;
60786ef3
MT
1548 memory_region_init(mr, owner, name, size);
1549 mr->ram = true;
1550 mr->terminates = true;
1551 mr->destructor = memory_region_destructor_ram;
8e41fb63 1552 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1cd3d492 1553 mr, &err);
677e7805 1554 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1555 if (err) {
1556 mr->size = int128_zero();
1557 object_unparent(OBJECT(mr));
1558 error_propagate(errp, err);
1559 }
60786ef3
MT
1560}
1561
d5dbde46 1562#ifdef CONFIG_POSIX
0b183fc8
PB
1563void memory_region_init_ram_from_file(MemoryRegion *mr,
1564 struct Object *owner,
1565 const char *name,
1566 uint64_t size,
98376843 1567 uint64_t align,
cbfc0171 1568 uint32_t ram_flags,
7f56e740
PB
1569 const char *path,
1570 Error **errp)
0b183fc8 1571{
1cd3d492 1572 Error *err = NULL;
0b183fc8
PB
1573 memory_region_init(mr, owner, name, size);
1574 mr->ram = true;
1575 mr->terminates = true;
1576 mr->destructor = memory_region_destructor_ram;
98376843 1577 mr->align = align;
1cd3d492 1578 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err);
677e7805 1579 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1580 if (err) {
1581 mr->size = int128_zero();
1582 object_unparent(OBJECT(mr));
1583 error_propagate(errp, err);
1584 }
093bc2cd 1585}
fea617c5
MAL
1586
1587void memory_region_init_ram_from_fd(MemoryRegion *mr,
1588 struct Object *owner,
1589 const char *name,
1590 uint64_t size,
1591 bool share,
1592 int fd,
1593 Error **errp)
1594{
1cd3d492 1595 Error *err = NULL;
fea617c5
MAL
1596 memory_region_init(mr, owner, name, size);
1597 mr->ram = true;
1598 mr->terminates = true;
1599 mr->destructor = memory_region_destructor_ram;
cbfc0171
JH
1600 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1601 share ? RAM_SHARED : 0,
1cd3d492 1602 fd, &err);
fea617c5 1603 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1604 if (err) {
1605 mr->size = int128_zero();
1606 object_unparent(OBJECT(mr));
1607 error_propagate(errp, err);
1608 }
fea617c5 1609}
0b183fc8 1610#endif
093bc2cd
AK
1611
1612void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1613 Object *owner,
093bc2cd
AK
1614 const char *name,
1615 uint64_t size,
1616 void *ptr)
1617{
2c9b15ca 1618 memory_region_init(mr, owner, name, size);
8ea9252a 1619 mr->ram = true;
14a3c10a 1620 mr->terminates = true;
fc3e7665 1621 mr->destructor = memory_region_destructor_ram;
677e7805 1622 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT
1623
1624 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1625 assert(ptr != NULL);
8e41fb63 1626 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK
1627}
1628
21e00fa5
AW
1629void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1630 Object *owner,
1631 const char *name,
1632 uint64_t size,
1633 void *ptr)
e4dc3f59 1634{
21e00fa5
AW
1635 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1636 mr->ram_device = true;
4a2e242b
AW
1637 mr->ops = &ram_device_mem_ops;
1638 mr->opaque = mr;
e4dc3f59
ND
1639}
1640
093bc2cd 1641void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1642 Object *owner,
093bc2cd
AK
1643 const char *name,
1644 MemoryRegion *orig,
a8170e5e 1645 hwaddr offset,
093bc2cd
AK
1646 uint64_t size)
1647{
2c9b15ca 1648 memory_region_init(mr, owner, name, size);
093bc2cd
AK
1649 mr->alias = orig;
1650 mr->alias_offset = offset;
1651}
1652
b59821a9
PM
1653void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1654 struct Object *owner,
1655 const char *name,
1656 uint64_t size,
1657 Error **errp)
a1777f7f 1658{
1cd3d492 1659 Error *err = NULL;
a1777f7f
PM
1660 memory_region_init(mr, owner, name, size);
1661 mr->ram = true;
1662 mr->readonly = true;
1663 mr->terminates = true;
1664 mr->destructor = memory_region_destructor_ram;
1cd3d492 1665 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
a1777f7f 1666 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1667 if (err) {
1668 mr->size = int128_zero();
1669 object_unparent(OBJECT(mr));
1670 error_propagate(errp, err);
1671 }
a1777f7f
PM
1672}
1673
b59821a9
PM
1674void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1675 Object *owner,
1676 const MemoryRegionOps *ops,
1677 void *opaque,
1678 const char *name,
1679 uint64_t size,
1680 Error **errp)
d0a9b5bc 1681{
1cd3d492 1682 Error *err = NULL;
39e0b03d 1683 assert(ops);
2c9b15ca 1684 memory_region_init(mr, owner, name, size);
7bc2b9cd 1685 mr->ops = ops;
75f5941c 1686 mr->opaque = opaque;
d0a9b5bc 1687 mr->terminates = true;
75c578dc 1688 mr->rom_device = true;
58268c8d 1689 mr->destructor = memory_region_destructor_ram;
1cd3d492
IM
1690 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1691 if (err) {
1692 mr->size = int128_zero();
1693 object_unparent(OBJECT(mr));
1694 error_propagate(errp, err);
1695 }
d0a9b5bc
AK
1696}
1697
1221a474
AK
1698void memory_region_init_iommu(void *_iommu_mr,
1699 size_t instance_size,
1700 const char *mrtypename,
2c9b15ca 1701 Object *owner,
30951157
AK
1702 const char *name,
1703 uint64_t size)
1704{
1221a474 1705 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK
1706 struct MemoryRegion *mr;
1707
1221a474
AK
1708 object_initialize(_iommu_mr, instance_size, mrtypename);
1709 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK
1710 memory_region_do_init(mr, owner, name, size);
1711 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1712 mr->terminates = true; /* then re-forwards */
3df9d748
AK
1713 QLIST_INIT(&iommu_mr->iommu_notify);
1714 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK
1715}
1716
b4fefef9 1717static void memory_region_finalize(Object *obj)
093bc2cd 1718{
b4fefef9
PC
1719 MemoryRegion *mr = MEMORY_REGION(obj);
1720
2e2b8eb7
PB
1721 assert(!mr->container);
1722
1723 /* We know the region is not visible in any address space (it
1724 * does not have a container and cannot be a root either because
1725 * it has no references, so we can blindly clear mr->enabled.
1726 * memory_region_set_enabled instead could trigger a transaction
1727 * and cause an infinite loop.
1728 */
1729 mr->enabled = false;
1730 memory_region_transaction_begin();
1731 while (!QTAILQ_EMPTY(&mr->subregions)) {
1732 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1733 memory_region_del_subregion(mr, subregion);
1734 }
1735 memory_region_transaction_commit();
1736
545e92e0 1737 mr->destructor(mr);
093bc2cd 1738 memory_region_clear_coalescing(mr);
302fa283 1739 g_free((char *)mr->name);
7267c094 1740 g_free(mr->ioeventfds);
093bc2cd
AK
1741}
1742
803c0816
PB
1743Object *memory_region_owner(MemoryRegion *mr)
1744{
22a893e4
PB
1745 Object *obj = OBJECT(mr);
1746 return obj->parent;
803c0816
PB
1747}
1748
46637be2
PB
1749void memory_region_ref(MemoryRegion *mr)
1750{
22a893e4
PB
1751 /* MMIO callbacks most likely will access data that belongs
1752 * to the owner, hence the need to ref/unref the owner whenever
1753 * the memory region is in use.
1754 *
1755 * The memory region is a child of its owner. As long as the
1756 * owner doesn't call unparent itself on the memory region,
1757 * ref-ing the owner will also keep the memory region alive.
612263cf
PB
1758 * Memory regions without an owner are supposed to never go away;
1759 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1760 */
612263cf
PB
1761 if (mr && mr->owner) {
1762 object_ref(mr->owner);
46637be2
PB
1763 }
1764}
1765
1766void memory_region_unref(MemoryRegion *mr)
1767{
612263cf
PB
1768 if (mr && mr->owner) {
1769 object_unref(mr->owner);
46637be2
PB
1770 }
1771}
1772
093bc2cd
AK
1773uint64_t memory_region_size(MemoryRegion *mr)
1774{
08dafab4
AK
1775 if (int128_eq(mr->size, int128_2_64())) {
1776 return UINT64_MAX;
1777 }
1778 return int128_get64(mr->size);
093bc2cd
AK
1779}
1780
5d546d4b 1781const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1782{
d1dd32af
PC
1783 if (!mr->name) {
1784 ((MemoryRegion *)mr)->name =
1785 object_get_canonical_path_component(OBJECT(mr));
1786 }
302fa283 1787 return mr->name;
8991c79b
AK
1788}
1789
21e00fa5 1790bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1791{
21e00fa5 1792 return mr->ram_device;
e4dc3f59
ND
1793}
1794
2d1a35be 1795uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1796{
6f6a5ef3 1797 uint8_t mask = mr->dirty_log_mask;
adaad61c 1798 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB
1799 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1800 }
1801 return mask;
55043ba3
AK
1802}
1803
2d1a35be
PB
1804bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1805{
1806 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1807}
1808
3df9d748 1809static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
5bf3d319
PX
1810{
1811 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1812 IOMMUNotifier *iommu_notifier;
1221a474 1813 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
5bf3d319 1814
3df9d748 1815 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX
1816 flags |= iommu_notifier->notifier_flags;
1817 }
1818
1221a474
AK
1819 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1820 imrc->notify_flag_changed(iommu_mr,
1821 iommu_mr->iommu_notify_flags,
1822 flags);
5bf3d319
PX
1823 }
1824
3df9d748 1825 iommu_mr->iommu_notify_flags = flags;
5bf3d319
PX
1826}
1827
cdb30812
PX
1828void memory_region_register_iommu_notifier(MemoryRegion *mr,
1829 IOMMUNotifier *n)
06866575 1830{
3df9d748
AK
1831 IOMMUMemoryRegion *iommu_mr;
1832
efcd38c5
JW
1833 if (mr->alias) {
1834 memory_region_register_iommu_notifier(mr->alias, n);
1835 return;
1836 }
1837
cdb30812 1838 /* We need to register for at least one bitfield */
3df9d748 1839 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1840 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1841 assert(n->start <= n->end);
cb1efcf4
PM
1842 assert(n->iommu_idx >= 0 &&
1843 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1844
3df9d748
AK
1845 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1846 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1847}
1848
3df9d748 1849uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1850{
1221a474
AK
1851 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1852
1853 if (imrc->get_min_page_size) {
1854 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK
1855 }
1856 return TARGET_PAGE_SIZE;
1857}
1858
3df9d748 1859void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1860{
3df9d748 1861 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1862 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1863 hwaddr addr, granularity;
a788f227
DG
1864 IOMMUTLBEntry iotlb;
1865
faa362e3 1866 /* If the IOMMU has its own replay callback, override */
1221a474
AK
1867 if (imrc->replay) {
1868 imrc->replay(iommu_mr, n);
faa362e3
PX
1869 return;
1870 }
1871
3df9d748 1872 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1873
a788f227 1874 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
2c91bcf2 1875 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
a788f227
DG
1876 if (iotlb.perm != IOMMU_NONE) {
1877 n->notify(n, &iotlb);
1878 }
1879
1880 /* if (2^64 - MR size) < granularity, it's possible to get an
1881 * infinite loop here. This should catch such a wraparound */
1882 if ((addr + granularity) < addr) {
1883 break;
1884 }
1885 }
1886}
1887
3df9d748 1888void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
de472e4a
PX
1889{
1890 IOMMUNotifier *notifier;
1891
3df9d748
AK
1892 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1893 memory_region_iommu_replay(iommu_mr, notifier);
de472e4a
PX
1894 }
1895}
1896
cdb30812
PX
1897void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1898 IOMMUNotifier *n)
06866575 1899{
3df9d748
AK
1900 IOMMUMemoryRegion *iommu_mr;
1901
efcd38c5
JW
1902 if (mr->alias) {
1903 memory_region_unregister_iommu_notifier(mr->alias, n);
1904 return;
1905 }
cdb30812 1906 QLIST_REMOVE(n, node);
3df9d748
AK
1907 iommu_mr = IOMMU_MEMORY_REGION(mr);
1908 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1909}
1910
bd2bfa4c
PX
1911void memory_region_notify_one(IOMMUNotifier *notifier,
1912 IOMMUTLBEntry *entry)
06866575 1913{
cdb30812
PX
1914 IOMMUNotifierFlag request_flags;
1915
bd2bfa4c
PX
1916 /*
1917 * Skip the notification if the notification does not overlap
1918 * with registered range.
1919 */
b021d1c0 1920 if (notifier->start > entry->iova + entry->addr_mask ||
bd2bfa4c
PX
1921 notifier->end < entry->iova) {
1922 return;
1923 }
cdb30812 1924
bd2bfa4c 1925 if (entry->perm & IOMMU_RW) {
cdb30812
PX
1926 request_flags = IOMMU_NOTIFIER_MAP;
1927 } else {
1928 request_flags = IOMMU_NOTIFIER_UNMAP;
1929 }
1930
bd2bfa4c
PX
1931 if (notifier->notifier_flags & request_flags) {
1932 notifier->notify(notifier, entry);
1933 }
1934}
1935
3df9d748 1936void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
cb1efcf4 1937 int iommu_idx,
bd2bfa4c
PX
1938 IOMMUTLBEntry entry)
1939{
1940 IOMMUNotifier *iommu_notifier;
1941
3df9d748 1942 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1943
3df9d748 1944 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
cb1efcf4
PM
1945 if (iommu_notifier->iommu_idx == iommu_idx) {
1946 memory_region_notify_one(iommu_notifier, &entry);
1947 }
cdb30812 1948 }
06866575
DG
1949}
1950
f1334de6
AK
1951int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1952 enum IOMMUMemoryRegionAttr attr,
1953 void *data)
1954{
1955 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1956
1957 if (!imrc->get_attr) {
1958 return -EINVAL;
1959 }
1960
1961 return imrc->get_attr(iommu_mr, attr, data);
1962}
1963
21f40209
PM
1964int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
1965 MemTxAttrs attrs)
1966{
1967 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1968
1969 if (!imrc->attrs_to_index) {
1970 return 0;
1971 }
1972
1973 return imrc->attrs_to_index(iommu_mr, attrs);
1974}
1975
1976int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
1977{
1978 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1979
1980 if (!imrc->num_indexes) {
1981 return 1;
1982 }
1983
1984 return imrc->num_indexes(iommu_mr);
1985}
1986
093bc2cd
AK
1987void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1988{
5a583347 1989 uint8_t mask = 1 << client;
deb809ed 1990 uint8_t old_logging;
5a583347 1991
dbddac6d 1992 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB
1993 old_logging = mr->vga_logging_count;
1994 mr->vga_logging_count += log ? 1 : -1;
1995 if (!!old_logging == !!mr->vga_logging_count) {
1996 return;
1997 }
1998
59023ef4 1999 memory_region_transaction_begin();
5a583347 2000 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 2001 memory_region_update_pending |= mr->enabled;
59023ef4 2002 memory_region_transaction_commit();
093bc2cd
AK
2003}
2004
a8170e5e
AK
2005bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
2006 hwaddr size, unsigned client)
093bc2cd 2007{
8e41fb63
FZ
2008 assert(mr->ram_block);
2009 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
2010 size, client);
093bc2cd
AK
2011}
2012
a8170e5e
AK
2013void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2014 hwaddr size)
093bc2cd 2015{
8e41fb63
FZ
2016 assert(mr->ram_block);
2017 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2018 size,
58d2707e 2019 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK
2020}
2021
0fe1eca7 2022static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
093bc2cd 2023{
0a752eee 2024 MemoryListener *listener;
0d673e36 2025 AddressSpace *as;
0a752eee 2026 FlatView *view;
5a583347
AK
2027 FlatRange *fr;
2028
0a752eee
PB
2029 /* If the same address space has multiple log_sync listeners, we
2030 * visit that address space's FlatView multiple times. But because
2031 * log_sync listeners are rare, it's still cheaper than walking each
2032 * address space once.
2033 */
2034 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2035 if (!listener->log_sync) {
2036 continue;
2037 }
2038 as = listener->address_space;
2039 view = address_space_get_flatview(as);
99e86347 2040 FOR_EACH_FLAT_RANGE(fr, view) {
3ebb1817 2041 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
16620684 2042 MemoryRegionSection mrs = section_from_flat_range(fr, view);
0a752eee 2043 listener->log_sync(listener, &mrs);
0d673e36 2044 }
5a583347 2045 }
856d7245 2046 flatview_unref(view);
5a583347 2047 }
093bc2cd
AK
2048}
2049
0fe1eca7
PB
2050DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2051 hwaddr addr,
2052 hwaddr size,
2053 unsigned client)
2054{
2055 assert(mr->ram_block);
2056 memory_region_sync_dirty_bitmap(mr);
2057 return cpu_physical_memory_snapshot_and_clear_dirty(
2058 memory_region_get_ram_addr(mr) + addr, size, client);
2059}
2060
2061bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2062 hwaddr addr, hwaddr size)
2063{
2064 assert(mr->ram_block);
2065 return cpu_physical_memory_snapshot_get_dirty(snap,
2066 memory_region_get_ram_addr(mr) + addr, size);
2067}
2068
093bc2cd
AK
2069void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2070{
fb1cd6f9 2071 if (mr->readonly != readonly) {
59023ef4 2072 memory_region_transaction_begin();
fb1cd6f9 2073 mr->readonly = readonly;
22bde714 2074 memory_region_update_pending |= mr->enabled;
59023ef4 2075 memory_region_transaction_commit();
fb1cd6f9 2076 }
093bc2cd
AK
2077}
2078
c26763f8
MAL
2079void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2080{
2081 if (mr->nonvolatile != nonvolatile) {
2082 memory_region_transaction_begin();
2083 mr->nonvolatile = nonvolatile;
2084 memory_region_update_pending |= mr->enabled;
2085 memory_region_transaction_commit();
2086 }
2087}
2088
5f9a5ea1 2089void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 2090{
5f9a5ea1 2091 if (mr->romd_mode != romd_mode) {
59023ef4 2092 memory_region_transaction_begin();
5f9a5ea1 2093 mr->romd_mode = romd_mode;
22bde714 2094 memory_region_update_pending |= mr->enabled;
59023ef4 2095 memory_region_transaction_commit();
d0a9b5bc
AK
2096 }
2097}
2098
a8170e5e
AK
2099void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2100 hwaddr size, unsigned client)
093bc2cd 2101{
8e41fb63
FZ
2102 assert(mr->ram_block);
2103 cpu_physical_memory_test_and_clear_dirty(
2104 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK
2105}
2106
a35ba7be
PB
2107int memory_region_get_fd(MemoryRegion *mr)
2108{
4ff87573
PB
2109 int fd;
2110
2111 rcu_read_lock();
2112 while (mr->alias) {
2113 mr = mr->alias;
a35ba7be 2114 }
4ff87573
PB
2115 fd = mr->ram_block->fd;
2116 rcu_read_unlock();
a35ba7be 2117
4ff87573
PB
2118 return fd;
2119}
a35ba7be 2120
093bc2cd
AK
2121void *memory_region_get_ram_ptr(MemoryRegion *mr)
2122{
49b24afc
PB
2123 void *ptr;
2124 uint64_t offset = 0;
093bc2cd 2125
49b24afc
PB
2126 rcu_read_lock();
2127 while (mr->alias) {
2128 offset += mr->alias_offset;
2129 mr = mr->alias;
2130 }
8e41fb63 2131 assert(mr->ram_block);
0878d0e1 2132 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
49b24afc 2133 rcu_read_unlock();
093bc2cd 2134
0878d0e1 2135 return ptr;
093bc2cd
AK
2136}
2137
07bdaa41
PB
2138MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2139{
2140 RAMBlock *block;
2141
2142 block = qemu_ram_block_from_host(ptr, false, offset);
2143 if (!block) {
2144 return NULL;
2145 }
2146
2147 return block->mr;
2148}
2149
7ebb2745
FZ
2150ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2151{
2152 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2153}
2154
37d7c084
PB
2155void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2156{
8e41fb63 2157 assert(mr->ram_block);
37d7c084 2158
fa53a0e5 2159 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB
2160}
2161
0d673e36 2162static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 2163{
99e86347 2164 FlatView *view;
093bc2cd 2165 FlatRange *fr;
093bc2cd 2166
856d7245 2167 view = address_space_get_flatview(as);
99e86347 2168 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 2169 if (fr->mr == mr) {
909bf763
PB
2170 flat_range_coalesced_io_del(fr, as);
2171 flat_range_coalesced_io_add(fr, as);
093bc2cd
AK
2172 }
2173 }
856d7245 2174 flatview_unref(view);
093bc2cd
AK
2175}
2176
0d673e36
AK
2177static void memory_region_update_coalesced_range(MemoryRegion *mr)
2178{
2179 AddressSpace *as;
2180
2181 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2182 memory_region_update_coalesced_range_as(mr, as);
2183 }
2184}
2185
093bc2cd
AK
2186void memory_region_set_coalescing(MemoryRegion *mr)
2187{
2188 memory_region_clear_coalescing(mr);
08dafab4 2189 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK
2190}
2191
2192void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 2193 hwaddr offset,
093bc2cd
AK
2194 uint64_t size)
2195{
7267c094 2196 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2197
08dafab4 2198 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK
2199 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2200 memory_region_update_coalesced_range(mr);
d410515e 2201 memory_region_set_flush_coalesced(mr);
093bc2cd
AK
2202}
2203
2204void memory_region_clear_coalescing(MemoryRegion *mr)
2205{
2206 CoalescedMemoryRange *cmr;
ab5b3db5 2207 bool updated = false;
093bc2cd 2208
d410515e
JK
2209 qemu_flush_coalesced_mmio_buffer();
2210 mr->flush_coalesced_mmio = false;
2211
093bc2cd
AK
2212 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2213 cmr = QTAILQ_FIRST(&mr->coalesced);
2214 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 2215 g_free(cmr);
ab5b3db5
FZ
2216 updated = true;
2217 }
2218
2219 if (updated) {
2220 memory_region_update_coalesced_range(mr);
093bc2cd 2221 }
093bc2cd
AK
2222}
2223
d410515e
JK
2224void memory_region_set_flush_coalesced(MemoryRegion *mr)
2225{
2226 mr->flush_coalesced_mmio = true;
2227}
2228
2229void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2230{
2231 qemu_flush_coalesced_mmio_buffer();
2232 if (QTAILQ_EMPTY(&mr->coalesced)) {
2233 mr->flush_coalesced_mmio = false;
2234 }
2235}
2236
196ea131
JK
2237void memory_region_clear_global_locking(MemoryRegion *mr)
2238{
2239 mr->global_locking = false;
2240}
2241
8c56c1a5
PF
2242static bool userspace_eventfd_warning;
2243
3e9d69e7 2244void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2245 hwaddr addr,
3e9d69e7
AK
2246 unsigned size,
2247 bool match_data,
2248 uint64_t data,
753d5e14 2249 EventNotifier *e)
3e9d69e7
AK
2250{
2251 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2252 .addr.start = int128_make64(addr),
2253 .addr.size = int128_make64(size),
3e9d69e7
AK
2254 .match_data = match_data,
2255 .data = data,
753d5e14 2256 .e = e,
3e9d69e7
AK
2257 };
2258 unsigned i;
2259
8c56c1a5
PF
2260 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2261 userspace_eventfd_warning))) {
2262 userspace_eventfd_warning = true;
2263 error_report("Using eventfd without MMIO binding in KVM. "
2264 "Suboptimal performance expected");
2265 }
2266
b8aecea2
JW
2267 if (size) {
2268 adjust_endianness(mr, &mrfd.data, size);
2269 }
59023ef4 2270 memory_region_transaction_begin();
3e9d69e7 2271 for (i = 0; i < mr->ioeventfd_nb; ++i) {
73bb753d 2272 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
3e9d69e7
AK
2273 break;
2274 }
2275 }
2276 ++mr->ioeventfd_nb;
7267c094 2277 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK
2278 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2279 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2280 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2281 mr->ioeventfds[i] = mrfd;
4dc56152 2282 ioeventfd_update_pending |= mr->enabled;
59023ef4 2283 memory_region_transaction_commit();
3e9d69e7
AK
2284}
2285
2286void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2287 hwaddr addr,
3e9d69e7
AK
2288 unsigned size,
2289 bool match_data,
2290 uint64_t data,
753d5e14 2291 EventNotifier *e)
3e9d69e7
AK
2292{
2293 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2294 .addr.start = int128_make64(addr),
2295 .addr.size = int128_make64(size),
3e9d69e7
AK
2296 .match_data = match_data,
2297 .data = data,
753d5e14 2298 .e = e,
3e9d69e7
AK
2299 };
2300 unsigned i;
2301
b8aecea2
JW
2302 if (size) {
2303 adjust_endianness(mr, &mrfd.data, size);
2304 }
59023ef4 2305 memory_region_transaction_begin();
3e9d69e7 2306 for (i = 0; i < mr->ioeventfd_nb; ++i) {
73bb753d 2307 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
3e9d69e7
AK
2308 break;
2309 }
2310 }
2311 assert(i != mr->ioeventfd_nb);
2312 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2313 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2314 --mr->ioeventfd_nb;
7267c094 2315 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2316 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2317 ioeventfd_update_pending |= mr->enabled;
59023ef4 2318 memory_region_transaction_commit();
3e9d69e7
AK
2319}
2320
feca4ac1 2321static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2322{
feca4ac1 2323 MemoryRegion *mr = subregion->container;
093bc2cd
AK
2324 MemoryRegion *other;
2325
59023ef4
JK
2326 memory_region_transaction_begin();
2327
dfde4e6e 2328 memory_region_ref(subregion);
093bc2cd
AK
2329 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2330 if (subregion->priority >= other->priority) {
2331 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2332 goto done;
2333 }
2334 }
2335 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2336done:
22bde714 2337 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2338 memory_region_transaction_commit();
093bc2cd
AK
2339}
2340
0598701a
PC
2341static void memory_region_add_subregion_common(MemoryRegion *mr,
2342 hwaddr offset,
2343 MemoryRegion *subregion)
2344{
feca4ac1
PB
2345 assert(!subregion->container);
2346 subregion->container = mr;
0598701a 2347 subregion->addr = offset;
feca4ac1 2348 memory_region_update_container_subregions(subregion);
0598701a 2349}
093bc2cd
AK
2350
2351void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2352 hwaddr offset,
093bc2cd
AK
2353 MemoryRegion *subregion)
2354{
093bc2cd
AK
2355 subregion->priority = 0;
2356 memory_region_add_subregion_common(mr, offset, subregion);
2357}
2358
2359void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2360 hwaddr offset,
093bc2cd 2361 MemoryRegion *subregion,
a1ff8ae0 2362 int priority)
093bc2cd 2363{
093bc2cd
AK
2364 subregion->priority = priority;
2365 memory_region_add_subregion_common(mr, offset, subregion);
2366}
2367
2368void memory_region_del_subregion(MemoryRegion *mr,
2369 MemoryRegion *subregion)
2370{
59023ef4 2371 memory_region_transaction_begin();
feca4ac1
PB
2372 assert(subregion->container == mr);
2373 subregion->container = NULL;
093bc2cd 2374 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2375 memory_region_unref(subregion);
22bde714 2376 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2377 memory_region_transaction_commit();
6bba19ba
AK
2378}
2379
2380void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2381{
2382 if (enabled == mr->enabled) {
2383 return;
2384 }
59023ef4 2385 memory_region_transaction_begin();
6bba19ba 2386 mr->enabled = enabled;
22bde714 2387 memory_region_update_pending = true;
59023ef4 2388 memory_region_transaction_commit();
093bc2cd 2389}
1c0ffa58 2390
e7af4c67
MT
2391void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2392{
2393 Int128 s = int128_make64(size);
2394
2395 if (size == UINT64_MAX) {
2396 s = int128_2_64();
2397 }
2398 if (int128_eq(s, mr->size)) {
2399 return;
2400 }
2401 memory_region_transaction_begin();
2402 mr->size = s;
2403 memory_region_update_pending = true;
2404 memory_region_transaction_commit();
2405}
2406
67891b8a 2407static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2408{
feca4ac1 2409 MemoryRegion *container = mr->container;
2282e1af 2410
feca4ac1 2411 if (container) {
67891b8a
PC
2412 memory_region_transaction_begin();
2413 memory_region_ref(mr);
feca4ac1
PB
2414 memory_region_del_subregion(container, mr);
2415 mr->container = container;
2416 memory_region_update_container_subregions(mr);
67891b8a
PC
2417 memory_region_unref(mr);
2418 memory_region_transaction_commit();
2282e1af 2419 }
67891b8a 2420}
2282e1af 2421
67891b8a
PC
2422void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2423{
2424 if (addr != mr->addr) {
2425 mr->addr = addr;
2426 memory_region_readd_subregion(mr);
2427 }
2282e1af
AK
2428}
2429
a8170e5e 2430void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2431{
4703359e 2432 assert(mr->alias);
4703359e 2433
59023ef4 2434 if (offset == mr->alias_offset) {
4703359e
AK
2435 return;
2436 }
2437
59023ef4
JK
2438 memory_region_transaction_begin();
2439 mr->alias_offset = offset;
22bde714 2440 memory_region_update_pending |= mr->enabled;
59023ef4 2441 memory_region_transaction_commit();
4703359e
AK
2442}
2443
a2b257d6
IM
2444uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2445{
2446 return mr->align;
2447}
2448
e2177955
AK
2449static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2450{
2451 const AddrRange *addr = addr_;
2452 const FlatRange *fr = fr_;
2453
2454 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2455 return -1;
2456 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2457 return 1;
2458 }
2459 return 0;
2460}
2461
99e86347 2462static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2463{
99e86347 2464 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK
2465 sizeof(FlatRange), cmp_flatrange_addr);
2466}
2467
eed2bacf
IM
2468bool memory_region_is_mapped(MemoryRegion *mr)
2469{
2470 return mr->container ? true : false;
2471}
2472
c6742b14
PB
2473/* Same as memory_region_find, but it does not add a reference to the
2474 * returned region. It must be called from an RCU critical section.
2475 */
2476static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2477 hwaddr addr, uint64_t size)
e2177955 2478{
052e87b0 2479 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB
2480 MemoryRegion *root;
2481 AddressSpace *as;
2482 AddrRange range;
99e86347 2483 FlatView *view;
73034e9e
PB
2484 FlatRange *fr;
2485
2486 addr += mr->addr;
feca4ac1
PB
2487 for (root = mr; root->container; ) {
2488 root = root->container;
73034e9e
PB
2489 addr += root->addr;
2490 }
e2177955 2491
73034e9e 2492 as = memory_region_to_address_space(root);
eed2bacf
IM
2493 if (!as) {
2494 return ret;
2495 }
73034e9e 2496 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2497
16620684 2498 view = address_space_to_flatview(as);
99e86347 2499 fr = flatview_lookup(view, range);
e2177955 2500 if (!fr) {
c6742b14 2501 return ret;
e2177955
AK
2502 }
2503
99e86347 2504 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK
2505 --fr;
2506 }
2507
2508 ret.mr = fr->mr;
16620684 2509 ret.fv = view;
e2177955
AK
2510 range = addrrange_intersection(range, fr->addr);
2511 ret.offset_within_region = fr->offset_in_region;
2512 ret.offset_within_region += int128_get64(int128_sub(range.start,
2513 fr->addr.start));
052e87b0 2514 ret.size = range.size;
e2177955 2515 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2516 ret.readonly = fr->readonly;
c26763f8 2517 ret.nonvolatile = fr->nonvolatile;
c6742b14
PB
2518 return ret;
2519}
2520
2521MemoryRegionSection memory_region_find(MemoryRegion *mr,
2522 hwaddr addr, uint64_t size)
2523{
2524 MemoryRegionSection ret;
2525 rcu_read_lock();
2526 ret = memory_region_find_rcu(mr, addr, size);
2527 if (ret.mr) {
2528 memory_region_ref(ret.mr);
2529 }
2b647668 2530 rcu_read_unlock();
e2177955
AK
2531 return ret;
2532}
2533
c6742b14
PB
2534bool memory_region_present(MemoryRegion *container, hwaddr addr)
2535{
2536 MemoryRegion *mr;
2537
2538 rcu_read_lock();
2539 mr = memory_region_find_rcu(container, addr, 1).mr;
2540 rcu_read_unlock();
2541 return mr && mr != container;
2542}
2543
9c1f8f44 2544void memory_global_dirty_log_sync(void)
86e775c6 2545{
3ebb1817 2546 memory_region_sync_dirty_bitmap(NULL);
7664e80c
AK
2547}
2548
19310760
JZ
2549static VMChangeStateEntry *vmstate_change;
2550
7664e80c
AK
2551void memory_global_dirty_log_start(void)
2552{
19310760
JZ
2553 if (vmstate_change) {
2554 qemu_del_vm_change_state_handler(vmstate_change);
2555 vmstate_change = NULL;
2556 }
2557
7664e80c 2558 global_dirty_log = true;
6f6a5ef3 2559
7376e582 2560 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3
PB
2561
2562 /* Refresh DIRTY_LOG_MIGRATION bit. */
2563 memory_region_transaction_begin();
2564 memory_region_update_pending = true;
2565 memory_region_transaction_commit();
7664e80c
AK
2566}
2567
19310760 2568static void memory_global_dirty_log_do_stop(void)
7664e80c 2569{
7664e80c 2570 global_dirty_log = false;
6f6a5ef3
PB
2571
2572 /* Refresh DIRTY_LOG_MIGRATION bit. */
2573 memory_region_transaction_begin();
2574 memory_region_update_pending = true;
2575 memory_region_transaction_commit();
2576
7376e582 2577 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK
2578}
2579
19310760
JZ
2580static void memory_vm_change_state_handler(void *opaque, int running,
2581 RunState state)
2582{
2583 if (running) {
2584 memory_global_dirty_log_do_stop();
2585
2586 if (vmstate_change) {
2587 qemu_del_vm_change_state_handler(vmstate_change);
2588 vmstate_change = NULL;
2589 }
2590 }
2591}
2592
2593void memory_global_dirty_log_stop(void)
2594{
2595 if (!runstate_is_running()) {
2596 if (vmstate_change) {
2597 return;
2598 }
2599 vmstate_change = qemu_add_vm_change_state_handler(
2600 memory_vm_change_state_handler, NULL);
2601 return;
2602 }
2603
2604 memory_global_dirty_log_do_stop();
2605}
2606
7664e80c
AK
2607static void listener_add_address_space(MemoryListener *listener,
2608 AddressSpace *as)
2609{
99e86347 2610 FlatView *view;
7664e80c
AK
2611 FlatRange *fr;
2612
680a4783
PB
2613 if (listener->begin) {
2614 listener->begin(listener);
2615 }
7664e80c 2616 if (global_dirty_log) {
975aefe0
AK
2617 if (listener->log_global_start) {
2618 listener->log_global_start(listener);
2619 }
7664e80c 2620 }
975aefe0 2621
856d7245 2622 view = address_space_get_flatview(as);
99e86347 2623 FOR_EACH_FLAT_RANGE(fr, view) {
279836f8
DH
2624 MemoryRegionSection section = section_from_flat_range(fr, view);
2625
975aefe0
AK
2626 if (listener->region_add) {
2627 listener->region_add(listener, &section);
2628 }
ae990e6c
DH
2629 if (fr->dirty_log_mask && listener->log_start) {
2630 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2631 }
7664e80c 2632 }
680a4783
PB
2633 if (listener->commit) {
2634 listener->commit(listener);
2635 }
856d7245 2636 flatview_unref(view);
7664e80c
AK
2637}
2638
d25836ca
PX
2639static void listener_del_address_space(MemoryListener *listener,
2640 AddressSpace *as)
2641{
2642 FlatView *view;
2643 FlatRange *fr;
2644
2645 if (listener->begin) {
2646 listener->begin(listener);
2647 }
2648 view = address_space_get_flatview(as);
2649 FOR_EACH_FLAT_RANGE(fr, view) {
2650 MemoryRegionSection section = section_from_flat_range(fr, view);
2651
2652 if (fr->dirty_log_mask && listener->log_stop) {
2653 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2654 }
2655 if (listener->region_del) {
2656 listener->region_del(listener, &section);
2657 }
2658 }
2659 if (listener->commit) {
2660 listener->commit(listener);
2661 }
2662 flatview_unref(view);
2663}
2664
d45fa784 2665void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2666{
72e22d2f
AK
2667 MemoryListener *other = NULL;
2668
d45fa784 2669 listener->address_space = as;
72e22d2f
AK
2670 if (QTAILQ_EMPTY(&memory_listeners)
2671 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2672 memory_listeners)->priority) {
2673 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2674 } else {
2675 QTAILQ_FOREACH(other, &memory_listeners, link) {
2676 if (listener->priority < other->priority) {
2677 break;
2678 }
2679 }
2680 QTAILQ_INSERT_BEFORE(other, listener, link);
2681 }
0d673e36 2682
9a54635d
PB
2683 if (QTAILQ_EMPTY(&as->listeners)
2684 || listener->priority >= QTAILQ_LAST(&as->listeners,
2685 memory_listeners)->priority) {
2686 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2687 } else {
2688 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2689 if (listener->priority < other->priority) {
2690 break;
2691 }
2692 }
2693 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2694 }
2695
d45fa784 2696 listener_add_address_space(listener, as);
7664e80c
AK
2697}
2698
2699void memory_listener_unregister(MemoryListener *listener)
2700{
1d8280c1
PB
2701 if (!listener->address_space) {
2702 return;
2703 }
2704
d25836ca 2705 listener_del_address_space(listener, listener->address_space);
72e22d2f 2706 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2707 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2708 listener->address_space = NULL;
86e775c6 2709}
e2177955 2710
7dca8043 2711void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2712{
ac95190e 2713 memory_region_ref(root);
8786db7c 2714 as->root = root;
67ace39b 2715 as->current_map = NULL;
4c19eb72
AK
2716 as->ioeventfd_nb = 0;
2717 as->ioeventfds = NULL;
9a54635d 2718 QTAILQ_INIT(&as->listeners);
0d673e36 2719 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2720 as->name = g_strdup(name ? name : "anonymous");
202fc01b
AK
2721 address_space_update_topology(as);
2722 address_space_update_ioeventfds(as);
1c0ffa58 2723}
658b2224 2724
374f2981 2725static void do_address_space_destroy(AddressSpace *as)
83f3c251 2726{
9a54635d 2727 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2728
856d7245 2729 flatview_unref(as->current_map);
7dca8043 2730 g_free(as->name);
4c19eb72 2731 g_free(as->ioeventfds);
ac95190e 2732 memory_region_unref(as->root);
83f3c251
AK
2733}
2734
374f2981
PB
2735void address_space_destroy(AddressSpace *as)
2736{
ac95190e
PB
2737 MemoryRegion *root = as->root;
2738
374f2981
PB
2739 /* Flush out anything from MemoryListeners listening in on this */
2740 memory_region_transaction_begin();
2741 as->root = NULL;
2742 memory_region_transaction_commit();
2743 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2744
2745 /* At this point, as->dispatch and as->current_map are dummy
2746 * entries that the guest should never use. Wait for the old
2747 * values to expire before freeing the data.
2748 */
ac95190e 2749 as->root = root;
374f2981
PB
2750 call_rcu(as, do_address_space_destroy, rcu);
2751}
2752
4e831901
PX
2753static const char *memory_region_type(MemoryRegion *mr)
2754{
2755 if (memory_region_is_ram_device(mr)) {
2756 return "ramd";
2757 } else if (memory_region_is_romd(mr)) {
2758 return "romd";
2759 } else if (memory_region_is_rom(mr)) {
2760 return "rom";
2761 } else if (memory_region_is_ram(mr)) {
2762 return "ram";
2763 } else {
2764 return "i/o";
2765 }
2766}
2767
314e2987
BS
2768typedef struct MemoryRegionList MemoryRegionList;
2769
2770struct MemoryRegionList {
2771 const MemoryRegion *mr;
a16878d2 2772 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS
2773};
2774
a16878d2 2775typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
314e2987 2776
4e831901
PX
2777#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2778 int128_sub((size), int128_one())) : 0)
2779#define MTREE_INDENT " "
2780
fc051ae6
AK
2781static void mtree_expand_owner(fprintf_function mon_printf, void *f,
2782 const char *label, Object *obj)
2783{
2784 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2785
2786 mon_printf(f, " %s:{%s", label, dev ? "dev" : "obj");
2787 if (dev && dev->id) {
2788 mon_printf(f, " id=%s", dev->id);
2789 } else {
2790 gchar *canonical_path = object_get_canonical_path(obj);
2791 if (canonical_path) {
2792 mon_printf(f, " path=%s", canonical_path);
2793 g_free(canonical_path);
2794 } else {
2795 mon_printf(f, " type=%s", object_get_typename(obj));
2796 }
2797 }
2798 mon_printf(f, "}");
2799}
2800
2801static void mtree_print_mr_owner(fprintf_function mon_printf, void *f,
2802 const MemoryRegion *mr)
2803{
2804 Object *owner = mr->owner;
2805 Object *parent = memory_region_owner((MemoryRegion *)mr);
2806
2807 if (!owner && !parent) {
2808 mon_printf(f, " orphan");
2809 return;
2810 }
2811 if (owner) {
2812 mtree_expand_owner(mon_printf, f, "owner", owner);
2813 }
2814 if (parent && parent != owner) {
2815 mtree_expand_owner(mon_printf, f, "parent", parent);
2816 }
2817}
2818
314e2987
BS
2819static void mtree_print_mr(fprintf_function mon_printf, void *f,
2820 const MemoryRegion *mr, unsigned int level,
a8170e5e 2821 hwaddr base,
fc051ae6
AK
2822 MemoryRegionListHead *alias_print_queue,
2823 bool owner)
314e2987 2824{
9479c57a
JK
2825 MemoryRegionList *new_ml, *ml, *next_ml;
2826 MemoryRegionListHead submr_print_queue;
314e2987
BS
2827 const MemoryRegion *submr;
2828 unsigned int i;
b31f8412 2829 hwaddr cur_start, cur_end;
314e2987 2830
f8a9f720 2831 if (!mr) {
314e2987
BS
2832 return;
2833 }
2834
2835 for (i = 0; i < level; i++) {
4e831901 2836 mon_printf(f, MTREE_INDENT);
314e2987
BS
2837 }
2838
b31f8412
PX
2839 cur_start = base + mr->addr;
2840 cur_end = cur_start + MR_SIZE(mr->size);
2841
2842 /*
2843 * Try to detect overflow of memory region. This should never
2844 * happen normally. When it happens, we dump something to warn the
2845 * user who is observing this.
2846 */
2847 if (cur_start < base || cur_end < cur_start) {
2848 mon_printf(f, "[DETECTED OVERFLOW!] ");
2849 }
2850
314e2987
BS
2851 if (mr->alias) {
2852 MemoryRegionList *ml;
2853 bool found = false;
2854
2855 /* check if the alias is already in the queue */
a16878d2 2856 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2857 if (ml->mr == mr->alias) {
314e2987
BS
2858 found = true;
2859 }
2860 }
2861
2862 if (!found) {
2863 ml = g_new(MemoryRegionList, 1);
2864 ml->mr = mr->alias;
a16878d2 2865 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2866 }
4896d74b 2867 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
c26763f8 2868 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
fc051ae6 2869 "-" TARGET_FMT_plx "%s",
b31f8412 2870 cur_start, cur_end,
4b474ba7 2871 mr->priority,
c26763f8 2872 mr->nonvolatile ? "nv-" : "",
4e831901 2873 memory_region_type((MemoryRegion *)mr),
3fb18b4d
PC
2874 memory_region_name(mr),
2875 memory_region_name(mr->alias),
314e2987 2876 mr->alias_offset,
4e831901 2877 mr->alias_offset + MR_SIZE(mr->size),
f8a9f720 2878 mr->enabled ? "" : " [disabled]");
fc051ae6
AK
2879 if (owner) {
2880 mtree_print_mr_owner(mon_printf, f, mr);
2881 }
314e2987 2882 } else {
4896d74b 2883 mon_printf(f,
c26763f8 2884 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s%s): %s%s",
b31f8412 2885 cur_start, cur_end,
4b474ba7 2886 mr->priority,
c26763f8 2887 mr->nonvolatile ? "nv-" : "",
4e831901 2888 memory_region_type((MemoryRegion *)mr),
f8a9f720
GH
2889 memory_region_name(mr),
2890 mr->enabled ? "" : " [disabled]");
fc051ae6
AK
2891 if (owner) {
2892 mtree_print_mr_owner(mon_printf, f, mr);
2893 }
314e2987 2894 }
fc051ae6 2895 mon_printf(f, "\n");
9479c57a
JK
2896
2897 QTAILQ_INIT(&submr_print_queue);
2898
314e2987 2899 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
2900 new_ml = g_new(MemoryRegionList, 1);
2901 new_ml->mr = submr;
a16878d2 2902 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK
2903 if (new_ml->mr->addr < ml->mr->addr ||
2904 (new_ml->mr->addr == ml->mr->addr &&
2905 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 2906 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK
2907 new_ml = NULL;
2908 break;
2909 }
2910 }
2911 if (new_ml) {
a16878d2 2912 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK
2913 }
2914 }
2915
a16878d2 2916 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b31f8412 2917 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
fc051ae6 2918 alias_print_queue, owner);
9479c57a
JK
2919 }
2920
a16878d2 2921 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 2922 g_free(ml);
314e2987
BS
2923 }
2924}
2925
5e8fd947
AK
2926struct FlatViewInfo {
2927 fprintf_function mon_printf;
2928 void *f;
2929 int counter;
2930 bool dispatch_tree;
fc051ae6 2931 bool owner;
5e8fd947
AK
2932};
2933
2934static void mtree_print_flatview(gpointer key, gpointer value,
2935 gpointer user_data)
57bb40c9 2936{
5e8fd947
AK
2937 FlatView *view = key;
2938 GArray *fv_address_spaces = value;
2939 struct FlatViewInfo *fvi = user_data;
2940 fprintf_function p = fvi->mon_printf;
2941 void *f = fvi->f;
57bb40c9
PX
2942 FlatRange *range = &view->ranges[0];
2943 MemoryRegion *mr;
2944 int n = view->nr;
5e8fd947
AK
2945 int i;
2946 AddressSpace *as;
2947
2948 p(f, "FlatView #%d\n", fvi->counter);
2949 ++fvi->counter;
2950
2951 for (i = 0; i < fv_address_spaces->len; ++i) {
2952 as = g_array_index(fv_address_spaces, AddressSpace*, i);
2953 p(f, " AS \"%s\", root: %s", as->name, memory_region_name(as->root));
2954 if (as->root->alias) {
2955 p(f, ", alias %s", memory_region_name(as->root->alias));
2956 }
2957 p(f, "\n");
2958 }
2959
2960 p(f, " Root memory region: %s\n",
2961 view->root ? memory_region_name(view->root) : "(none)");
57bb40c9
PX
2962
2963 if (n <= 0) {
5e8fd947 2964 p(f, MTREE_INDENT "No rendered FlatView\n\n");
57bb40c9
PX
2965 return;
2966 }
2967
2968 while (n--) {
2969 mr = range->mr;
377a07aa
PB
2970 if (range->offset_in_region) {
2971 p(f, MTREE_INDENT TARGET_FMT_plx "-"
c26763f8 2972 TARGET_FMT_plx " (prio %d, %s%s): %s @" TARGET_FMT_plx,
377a07aa
PB
2973 int128_get64(range->addr.start),
2974 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2975 mr->priority,
c26763f8 2976 range->nonvolatile ? "nv-" : "",
377a07aa
PB
2977 range->readonly ? "rom" : memory_region_type(mr),
2978 memory_region_name(mr),
2979 range->offset_in_region);
2980 } else {
2981 p(f, MTREE_INDENT TARGET_FMT_plx "-"
c26763f8 2982 TARGET_FMT_plx " (prio %d, %s%s): %s",
377a07aa
PB
2983 int128_get64(range->addr.start),
2984 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2985 mr->priority,
c26763f8 2986 range->nonvolatile ? "nv-" : "",
377a07aa
PB
2987 range->readonly ? "rom" : memory_region_type(mr),
2988 memory_region_name(mr));
2989 }
fc051ae6
AK
2990 if (fvi->owner) {
2991 mtree_print_mr_owner(p, f, mr);
2992 }
2993 p(f, "\n");
57bb40c9
PX
2994 range++;
2995 }
2996
5e8fd947
AK
2997#if !defined(CONFIG_USER_ONLY)
2998 if (fvi->dispatch_tree && view->root) {
2999 mtree_print_dispatch(p, f, view->dispatch, view->root);
3000 }
3001#endif
3002
3003 p(f, "\n");
3004}
3005
3006static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3007 gpointer user_data)
3008{
3009 FlatView *view = key;
3010 GArray *fv_address_spaces = value;
3011
3012 g_array_unref(fv_address_spaces);
57bb40c9 3013 flatview_unref(view);
5e8fd947
AK
3014
3015 return true;
57bb40c9
PX
3016}
3017
5e8fd947 3018void mtree_info(fprintf_function mon_printf, void *f, bool flatview,
fc051ae6 3019 bool dispatch_tree, bool owner)
314e2987
BS
3020{
3021 MemoryRegionListHead ml_head;
3022 MemoryRegionList *ml, *ml2;
0d673e36 3023 AddressSpace *as;
314e2987 3024
57bb40c9 3025 if (flatview) {
5e8fd947
AK
3026 FlatView *view;
3027 struct FlatViewInfo fvi = {
3028 .mon_printf = mon_printf,
3029 .f = f,
3030 .counter = 0,
fc051ae6
AK
3031 .dispatch_tree = dispatch_tree,
3032 .owner = owner,
5e8fd947
AK
3033 };
3034 GArray *fv_address_spaces;
3035 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3036
3037 /* Gather all FVs in one table */
57bb40c9 3038 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
5e8fd947
AK
3039 view = address_space_get_flatview(as);
3040
3041 fv_address_spaces = g_hash_table_lookup(views, view);
3042 if (!fv_address_spaces) {
3043 fv_address_spaces = g_array_new(false, false, sizeof(as));
3044 g_hash_table_insert(views, view, fv_address_spaces);
3045 }
3046
3047 g_array_append_val(fv_address_spaces, as);
57bb40c9 3048 }
5e8fd947
AK
3049
3050 /* Print */
3051 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3052
3053 /* Free */
3054 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3055 g_hash_table_unref(views);
3056
57bb40c9
PX
3057 return;
3058 }
3059
314e2987
BS
3060 QTAILQ_INIT(&ml_head);
3061
0d673e36 3062 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
e48816aa 3063 mon_printf(f, "address-space: %s\n", as->name);
fc051ae6 3064 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head, owner);
e48816aa 3065 mon_printf(f, "\n");
b9f9be88
BS
3066 }
3067
314e2987 3068 /* print aliased regions */
a16878d2 3069 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
e48816aa 3070 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
fc051ae6 3071 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head, owner);
e48816aa 3072 mon_printf(f, "\n");
314e2987
BS
3073 }
3074
a16878d2 3075 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 3076 g_free(ml);
314e2987 3077 }
314e2987 3078}
b4fefef9 3079
b08199c6
PM
3080void memory_region_init_ram(MemoryRegion *mr,
3081 struct Object *owner,
3082 const char *name,
3083 uint64_t size,
3084 Error **errp)
3085{
3086 DeviceState *owner_dev;
3087 Error *err = NULL;
3088
3089 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3090 if (err) {
3091 error_propagate(errp, err);
3092 return;
3093 }
3094 /* This will assert if owner is neither NULL nor a DeviceState.
3095 * We only want the owner here for the purposes of defining a
3096 * unique name for migration. TODO: Ideally we should implement
3097 * a naming scheme for Objects which are not DeviceStates, in
3098 * which case we can relax this restriction.
3099 */
3100 owner_dev = DEVICE(owner);
3101 vmstate_register_ram(mr, owner_dev);
3102}
3103
3104void memory_region_init_rom(MemoryRegion *mr,
3105 struct Object *owner,
3106 const char *name,
3107 uint64_t size,
3108 Error **errp)
3109{
3110 DeviceState *owner_dev;
3111 Error *err = NULL;
3112
3113 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3114 if (err) {
3115 error_propagate(errp, err);
3116 return;
3117 }
3118 /* This will assert if owner is neither NULL nor a DeviceState.
3119 * We only want the owner here for the purposes of defining a
3120 * unique name for migration. TODO: Ideally we should implement
3121 * a naming scheme for Objects which are not DeviceStates, in
3122 * which case we can relax this restriction.
3123 */
3124 owner_dev = DEVICE(owner);
3125 vmstate_register_ram(mr, owner_dev);
3126}
3127
3128void memory_region_init_rom_device(MemoryRegion *mr,
3129 struct Object *owner,
3130 const MemoryRegionOps *ops,
3131 void *opaque,
3132 const char *name,
3133 uint64_t size,
3134 Error **errp)
3135{
3136 DeviceState *owner_dev;
3137 Error *err = NULL;
3138
3139 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3140 name, size, &err);
3141 if (err) {
3142 error_propagate(errp, err);
3143 return;
3144 }
3145 /* This will assert if owner is neither NULL nor a DeviceState.
3146 * We only want the owner here for the purposes of defining a
3147 * unique name for migration. TODO: Ideally we should implement
3148 * a naming scheme for Objects which are not DeviceStates, in
3149 * which case we can relax this restriction.
3150 */
3151 owner_dev = DEVICE(owner);
3152 vmstate_register_ram(mr, owner_dev);
3153}
3154
b4fefef9
PC
3155static const TypeInfo memory_region_info = {
3156 .parent = TYPE_OBJECT,
3157 .name = TYPE_MEMORY_REGION,
3158 .instance_size = sizeof(MemoryRegion),
3159 .instance_init = memory_region_initfn,
3160 .instance_finalize = memory_region_finalize,
3161};
3162
3df9d748
AK
3163static const TypeInfo iommu_memory_region_info = {
3164 .parent = TYPE_MEMORY_REGION,
3165 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 3166 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK
3167 .instance_size = sizeof(IOMMUMemoryRegion),
3168 .instance_init = iommu_memory_region_initfn,
1221a474 3169 .abstract = true,
3df9d748
AK
3170};
3171
b4fefef9
PC
3172static void memory_register_types(void)
3173{
3174 type_register_static(&memory_region_info);
3df9d748 3175 type_register_static(&iommu_memory_region_info);
b4fefef9
PC
3176}
3177
3178type_init(memory_register_types)