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memory: Share FlatView's and dispatch trees between address spaces
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CommitLineData
093bc2cd
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1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
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14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879
PB
18#include "qemu-common.h"
19#include "cpu.h"
022c62cb
PB
20#include "exec/memory.h"
21#include "exec/address-spaces.h"
22#include "exec/ioport.h"
409ddd01 23#include "qapi/visitor.h"
1de7afc9 24#include "qemu/bitops.h"
8c56c1a5 25#include "qemu/error-report.h"
2c9b15ca 26#include "qom/object.h"
0ab8ed18 27#include "trace-root.h"
093bc2cd 28
022c62cb 29#include "exec/memory-internal.h"
220c3ebd 30#include "exec/ram_addr.h"
8c56c1a5 31#include "sysemu/kvm.h"
e1c57ab8 32#include "sysemu/sysemu.h"
c9356746
FK
33#include "hw/misc/mmio_interface.h"
34#include "hw/qdev-properties.h"
b08199c6 35#include "migration/vmstate.h"
67d95c15 36
d197063f
PB
37//#define DEBUG_UNASSIGNED
38
22bde714
JK
39static unsigned memory_region_transaction_depth;
40static bool memory_region_update_pending;
4dc56152 41static bool ioeventfd_update_pending;
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42static bool global_dirty_log = false;
43
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44static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
45 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 46
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47static QTAILQ_HEAD(, AddressSpace) address_spaces
48 = QTAILQ_HEAD_INITIALIZER(address_spaces);
49
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50static GHashTable *flat_views;
51
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52typedef struct AddrRange AddrRange;
53
8417cebf 54/*
c9cdaa3a 55 * Note that signed integers are needed for negative offsetting in aliases
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56 * (large MemoryRegion::alias_offset).
57 */
093bc2cd 58struct AddrRange {
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59 Int128 start;
60 Int128 size;
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61};
62
08dafab4 63static AddrRange addrrange_make(Int128 start, Int128 size)
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64{
65 return (AddrRange) { start, size };
66}
67
68static bool addrrange_equal(AddrRange r1, AddrRange r2)
69{
08dafab4 70 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
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71}
72
08dafab4 73static Int128 addrrange_end(AddrRange r)
093bc2cd 74{
08dafab4 75 return int128_add(r.start, r.size);
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76}
77
08dafab4 78static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 79{
08dafab4 80 int128_addto(&range.start, delta);
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81 return range;
82}
83
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84static bool addrrange_contains(AddrRange range, Int128 addr)
85{
86 return int128_ge(addr, range.start)
87 && int128_lt(addr, addrrange_end(range));
88}
89
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90static bool addrrange_intersects(AddrRange r1, AddrRange r2)
91{
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92 return addrrange_contains(r1, r2.start)
93 || addrrange_contains(r2, r1.start);
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94}
95
96static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
97{
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98 Int128 start = int128_max(r1.start, r2.start);
99 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
100 return addrrange_make(start, int128_sub(end, start));
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101}
102
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103enum ListenerDirection { Forward, Reverse };
104
7376e582 105#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
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106 do { \
107 MemoryListener *_listener; \
108 \
109 switch (_direction) { \
110 case Forward: \
111 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
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112 if (_listener->_callback) { \
113 _listener->_callback(_listener, ##_args); \
114 } \
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115 } \
116 break; \
117 case Reverse: \
118 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
119 memory_listeners, link) { \
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120 if (_listener->_callback) { \
121 _listener->_callback(_listener, ##_args); \
122 } \
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123 } \
124 break; \
125 default: \
126 abort(); \
127 } \
128 } while (0)
129
9a54635d 130#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
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131 do { \
132 MemoryListener *_listener; \
9a54635d 133 struct memory_listeners_as *list = &(_as)->listeners; \
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134 \
135 switch (_direction) { \
136 case Forward: \
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PB
137 QTAILQ_FOREACH(_listener, list, link_as) { \
138 if (_listener->_callback) { \
7376e582
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139 _listener->_callback(_listener, _section, ##_args); \
140 } \
141 } \
142 break; \
143 case Reverse: \
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PB
144 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
145 link_as) { \
146 if (_listener->_callback) { \
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147 _listener->_callback(_listener, _section, ##_args); \
148 } \
149 } \
150 break; \
151 default: \
152 abort(); \
153 } \
154 } while (0)
155
dfde4e6e 156/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 157#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44 158 do { \
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159 MemoryRegionSection mrs = section_from_flat_range(fr, \
160 address_space_to_flatview(as)); \
9a54635d 161 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 162 } while(0)
0e0d36b4 163
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164struct CoalescedMemoryRange {
165 AddrRange addr;
166 QTAILQ_ENTRY(CoalescedMemoryRange) link;
167};
168
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169struct MemoryRegionIoeventfd {
170 AddrRange addr;
171 bool match_data;
172 uint64_t data;
753d5e14 173 EventNotifier *e;
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174};
175
176static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
177 MemoryRegionIoeventfd b)
178{
08dafab4 179 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 180 return true;
08dafab4 181 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 182 return false;
08dafab4 183 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 184 return true;
08dafab4 185 } else if (int128_gt(a.addr.size, b.addr.size)) {
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186 return false;
187 } else if (a.match_data < b.match_data) {
188 return true;
189 } else if (a.match_data > b.match_data) {
190 return false;
191 } else if (a.match_data) {
192 if (a.data < b.data) {
193 return true;
194 } else if (a.data > b.data) {
195 return false;
196 }
197 }
753d5e14 198 if (a.e < b.e) {
3e9d69e7 199 return true;
753d5e14 200 } else if (a.e > b.e) {
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201 return false;
202 }
203 return false;
204}
205
206static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
207 MemoryRegionIoeventfd b)
208{
209 return !memory_region_ioeventfd_before(a, b)
210 && !memory_region_ioeventfd_before(b, a);
211}
212
093bc2cd 213typedef struct FlatRange FlatRange;
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214
215/* Range of memory in the global map. Addresses are absolute. */
216struct FlatRange {
217 MemoryRegion *mr;
a8170e5e 218 hwaddr offset_in_region;
093bc2cd 219 AddrRange addr;
5a583347 220 uint8_t dirty_log_mask;
b138e654 221 bool romd_mode;
fb1cd6f9 222 bool readonly;
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223};
224
225/* Flattened global view of current active memory hierarchy. Kept in sorted
226 * order.
227 */
228struct FlatView {
374f2981 229 struct rcu_head rcu;
856d7245 230 unsigned ref;
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231 FlatRange *ranges;
232 unsigned nr;
233 unsigned nr_allocated;
66a6df1d 234 struct AddressSpaceDispatch *dispatch;
89c177bb 235 MemoryRegion *root;
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236};
237
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238typedef struct AddressSpaceOps AddressSpaceOps;
239
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240#define FOR_EACH_FLAT_RANGE(var, view) \
241 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
242
9c1f8f44 243static inline MemoryRegionSection
16620684 244section_from_flat_range(FlatRange *fr, FlatView *fv)
9c1f8f44
PB
245{
246 return (MemoryRegionSection) {
247 .mr = fr->mr,
16620684 248 .fv = fv,
9c1f8f44
PB
249 .offset_within_region = fr->offset_in_region,
250 .size = fr->addr.size,
251 .offset_within_address_space = int128_get64(fr->addr.start),
252 .readonly = fr->readonly,
253 };
254}
255
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256static bool flatrange_equal(FlatRange *a, FlatRange *b)
257{
258 return a->mr == b->mr
259 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 260 && a->offset_in_region == b->offset_in_region
b138e654 261 && a->romd_mode == b->romd_mode
fb1cd6f9 262 && a->readonly == b->readonly;
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263}
264
89c177bb 265static FlatView *flatview_new(MemoryRegion *mr_root)
093bc2cd 266{
cc94cd6d
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267 FlatView *view;
268
269 view = g_new0(FlatView, 1);
856d7245 270 view->ref = 1;
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271 view->root = mr_root;
272 memory_region_ref(mr_root);
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273
274 return view;
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275}
276
277/* Insert a range into a given position. Caller is responsible for maintaining
278 * sorting order.
279 */
280static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
281{
282 if (view->nr == view->nr_allocated) {
283 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 284 view->ranges = g_realloc(view->ranges,
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285 view->nr_allocated * sizeof(*view->ranges));
286 }
287 memmove(view->ranges + pos + 1, view->ranges + pos,
288 (view->nr - pos) * sizeof(FlatRange));
289 view->ranges[pos] = *range;
dfde4e6e 290 memory_region_ref(range->mr);
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291 ++view->nr;
292}
293
294static void flatview_destroy(FlatView *view)
295{
dfde4e6e
PB
296 int i;
297
66a6df1d
AK
298 if (view->dispatch) {
299 address_space_dispatch_free(view->dispatch);
300 }
dfde4e6e
PB
301 for (i = 0; i < view->nr; i++) {
302 memory_region_unref(view->ranges[i].mr);
303 }
7267c094 304 g_free(view->ranges);
89c177bb 305 memory_region_unref(view->root);
a9a0c06d 306 g_free(view);
093bc2cd
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307}
308
447b0d0b 309static bool flatview_ref(FlatView *view)
856d7245 310{
447b0d0b 311 return atomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB
312}
313
314static void flatview_unref(FlatView *view)
315{
316 if (atomic_fetch_dec(&view->ref) == 1) {
66a6df1d 317 call_rcu(view, flatview_destroy, rcu);
856d7245
PB
318 }
319}
320
16620684 321FlatView *address_space_to_flatview(AddressSpace *as)
66a6df1d
AK
322{
323 return atomic_rcu_read(&as->current_map);
324}
325
326AddressSpaceDispatch *flatview_to_dispatch(FlatView *fv)
327{
328 return fv->dispatch;
329}
330
331AddressSpaceDispatch *address_space_to_dispatch(AddressSpace *as)
332{
333 return flatview_to_dispatch(address_space_to_flatview(as));
334}
335
3d8e6bf9
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336static bool can_merge(FlatRange *r1, FlatRange *r2)
337{
08dafab4 338 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 339 && r1->mr == r2->mr
08dafab4
AK
340 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
341 r1->addr.size),
342 int128_make64(r2->offset_in_region))
d0a9b5bc 343 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 344 && r1->romd_mode == r2->romd_mode
fb1cd6f9 345 && r1->readonly == r2->readonly;
3d8e6bf9
AK
346}
347
8508e024 348/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK
349static void flatview_simplify(FlatView *view)
350{
351 unsigned i, j;
352
353 i = 0;
354 while (i < view->nr) {
355 j = i + 1;
356 while (j < view->nr
357 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 358 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
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359 ++j;
360 }
361 ++i;
362 memmove(&view->ranges[i], &view->ranges[j],
363 (view->nr - j) * sizeof(view->ranges[j]));
364 view->nr -= j - i;
365 }
366}
367
e7342aa3
PB
368static bool memory_region_big_endian(MemoryRegion *mr)
369{
370#ifdef TARGET_WORDS_BIGENDIAN
371 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
372#else
373 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
374#endif
375}
376
e11ef3d1
PB
377static bool memory_region_wrong_endianness(MemoryRegion *mr)
378{
379#ifdef TARGET_WORDS_BIGENDIAN
380 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
381#else
382 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
383#endif
384}
385
386static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
387{
388 if (memory_region_wrong_endianness(mr)) {
389 switch (size) {
390 case 1:
391 break;
392 case 2:
393 *data = bswap16(*data);
394 break;
395 case 4:
396 *data = bswap32(*data);
397 break;
398 case 8:
399 *data = bswap64(*data);
400 break;
401 default:
402 abort();
403 }
404 }
405}
406
4779dc1d
HB
407static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
408{
409 MemoryRegion *root;
410 hwaddr abs_addr = offset;
411
412 abs_addr += mr->addr;
413 for (root = mr; root->container; ) {
414 root = root->container;
415 abs_addr += root->addr;
416 }
417
418 return abs_addr;
419}
420
5a68be94
HB
421static int get_cpu_index(void)
422{
423 if (current_cpu) {
424 return current_cpu->cpu_index;
425 }
426 return -1;
427}
428
cc05c43a
PM
429static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
430 hwaddr addr,
431 uint64_t *value,
432 unsigned size,
433 unsigned shift,
434 uint64_t mask,
435 MemTxAttrs attrs)
436{
437 uint64_t tmp;
438
439 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
23d92d68 440 if (mr->subpage) {
5a68be94 441 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
442 } else if (mr == &io_mem_notdirty) {
443 /* Accesses to code which has previously been translated into a TB show
444 * up in the MMIO path, as accesses to the io_mem_notdirty
445 * MemoryRegion. */
446 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
447 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
448 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 449 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 450 }
cc05c43a
PM
451 *value |= (tmp & mask) << shift;
452 return MEMTX_OK;
453}
454
455static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB
456 hwaddr addr,
457 uint64_t *value,
458 unsigned size,
459 unsigned shift,
cc05c43a
PM
460 uint64_t mask,
461 MemTxAttrs attrs)
ce5d2f33 462{
ce5d2f33
PB
463 uint64_t tmp;
464
cc05c43a 465 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 466 if (mr->subpage) {
5a68be94 467 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
468 } else if (mr == &io_mem_notdirty) {
469 /* Accesses to code which has previously been translated into a TB show
470 * up in the MMIO path, as accesses to the io_mem_notdirty
471 * MemoryRegion. */
472 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
473 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
474 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 475 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 476 }
ce5d2f33 477 *value |= (tmp & mask) << shift;
cc05c43a 478 return MEMTX_OK;
ce5d2f33
PB
479}
480
cc05c43a
PM
481static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
482 hwaddr addr,
483 uint64_t *value,
484 unsigned size,
485 unsigned shift,
486 uint64_t mask,
487 MemTxAttrs attrs)
164a4dcd 488{
cc05c43a
PM
489 uint64_t tmp = 0;
490 MemTxResult r;
164a4dcd 491
cc05c43a 492 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 493 if (mr->subpage) {
5a68be94 494 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
495 } else if (mr == &io_mem_notdirty) {
496 /* Accesses to code which has previously been translated into a TB show
497 * up in the MMIO path, as accesses to the io_mem_notdirty
498 * MemoryRegion. */
499 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
500 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
501 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 502 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 503 }
164a4dcd 504 *value |= (tmp & mask) << shift;
cc05c43a 505 return r;
164a4dcd
AK
506}
507
cc05c43a
PM
508static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
509 hwaddr addr,
510 uint64_t *value,
511 unsigned size,
512 unsigned shift,
513 uint64_t mask,
514 MemTxAttrs attrs)
ce5d2f33 515{
ce5d2f33
PB
516 uint64_t tmp;
517
518 tmp = (*value >> shift) & mask;
23d92d68 519 if (mr->subpage) {
5a68be94 520 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
521 } else if (mr == &io_mem_notdirty) {
522 /* Accesses to code which has previously been translated into a TB show
523 * up in the MMIO path, as accesses to the io_mem_notdirty
524 * MemoryRegion. */
525 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
526 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
527 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 528 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 529 }
ce5d2f33 530 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
cc05c43a 531 return MEMTX_OK;
ce5d2f33
PB
532}
533
cc05c43a
PM
534static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
535 hwaddr addr,
536 uint64_t *value,
537 unsigned size,
538 unsigned shift,
539 uint64_t mask,
540 MemTxAttrs attrs)
164a4dcd 541{
164a4dcd
AK
542 uint64_t tmp;
543
544 tmp = (*value >> shift) & mask;
23d92d68 545 if (mr->subpage) {
5a68be94 546 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
547 } else if (mr == &io_mem_notdirty) {
548 /* Accesses to code which has previously been translated into a TB show
549 * up in the MMIO path, as accesses to the io_mem_notdirty
550 * MemoryRegion. */
551 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
552 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
553 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 554 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 555 }
164a4dcd 556 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 557 return MEMTX_OK;
164a4dcd
AK
558}
559
cc05c43a
PM
560static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
561 hwaddr addr,
562 uint64_t *value,
563 unsigned size,
564 unsigned shift,
565 uint64_t mask,
566 MemTxAttrs attrs)
567{
568 uint64_t tmp;
569
cc05c43a 570 tmp = (*value >> shift) & mask;
23d92d68 571 if (mr->subpage) {
5a68be94 572 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
573 } else if (mr == &io_mem_notdirty) {
574 /* Accesses to code which has previously been translated into a TB show
575 * up in the MMIO path, as accesses to the io_mem_notdirty
576 * MemoryRegion. */
577 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
578 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
579 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 580 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 581 }
cc05c43a
PM
582 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
583}
584
585static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK
586 uint64_t *value,
587 unsigned size,
588 unsigned access_size_min,
589 unsigned access_size_max,
05e015f7
KF
590 MemTxResult (*access_fn)
591 (MemoryRegion *mr,
592 hwaddr addr,
593 uint64_t *value,
594 unsigned size,
595 unsigned shift,
596 uint64_t mask,
597 MemTxAttrs attrs),
cc05c43a
PM
598 MemoryRegion *mr,
599 MemTxAttrs attrs)
164a4dcd
AK
600{
601 uint64_t access_mask;
602 unsigned access_size;
603 unsigned i;
cc05c43a 604 MemTxResult r = MEMTX_OK;
164a4dcd
AK
605
606 if (!access_size_min) {
607 access_size_min = 1;
608 }
609 if (!access_size_max) {
610 access_size_max = 4;
611 }
ce5d2f33
PB
612
613 /* FIXME: support unaligned access? */
164a4dcd
AK
614 access_size = MAX(MIN(size, access_size_max), access_size_min);
615 access_mask = -1ULL >> (64 - access_size * 8);
e7342aa3
PB
616 if (memory_region_big_endian(mr)) {
617 for (i = 0; i < size; i += access_size) {
05e015f7 618 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 619 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB
620 }
621 } else {
622 for (i = 0; i < size; i += access_size) {
05e015f7 623 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 624 access_mask, attrs);
e7342aa3 625 }
164a4dcd 626 }
cc05c43a 627 return r;
164a4dcd
AK
628}
629
e2177955
AK
630static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
631{
0d673e36
AK
632 AddressSpace *as;
633
feca4ac1
PB
634 while (mr->container) {
635 mr = mr->container;
e2177955 636 }
0d673e36
AK
637 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
638 if (mr == as->root) {
639 return as;
640 }
e2177955 641 }
eed2bacf 642 return NULL;
e2177955
AK
643}
644
093bc2cd
AK
645/* Render a memory region into the global view. Ranges in @view obscure
646 * ranges in @mr.
647 */
648static void render_memory_region(FlatView *view,
649 MemoryRegion *mr,
08dafab4 650 Int128 base,
fb1cd6f9
AK
651 AddrRange clip,
652 bool readonly)
093bc2cd
AK
653{
654 MemoryRegion *subregion;
655 unsigned i;
a8170e5e 656 hwaddr offset_in_region;
08dafab4
AK
657 Int128 remain;
658 Int128 now;
093bc2cd
AK
659 FlatRange fr;
660 AddrRange tmp;
661
6bba19ba
AK
662 if (!mr->enabled) {
663 return;
664 }
665
08dafab4 666 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 667 readonly |= mr->readonly;
093bc2cd
AK
668
669 tmp = addrrange_make(base, mr->size);
670
671 if (!addrrange_intersects(tmp, clip)) {
672 return;
673 }
674
675 clip = addrrange_intersection(tmp, clip);
676
677 if (mr->alias) {
08dafab4
AK
678 int128_subfrom(&base, int128_make64(mr->alias->addr));
679 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 680 render_memory_region(view, mr->alias, base, clip, readonly);
093bc2cd
AK
681 return;
682 }
683
684 /* Render subregions in priority order. */
685 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 686 render_memory_region(view, subregion, base, clip, readonly);
093bc2cd
AK
687 }
688
14a3c10a 689 if (!mr->terminates) {
093bc2cd
AK
690 return;
691 }
692
08dafab4 693 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK
694 base = clip.start;
695 remain = clip.size;
696
2eb74e1a 697 fr.mr = mr;
6f6a5ef3 698 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 699 fr.romd_mode = mr->romd_mode;
2eb74e1a
PC
700 fr.readonly = readonly;
701
093bc2cd 702 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK
703 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
704 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK
705 continue;
706 }
08dafab4
AK
707 if (int128_lt(base, view->ranges[i].addr.start)) {
708 now = int128_min(remain,
709 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK
710 fr.offset_in_region = offset_in_region;
711 fr.addr = addrrange_make(base, now);
712 flatview_insert(view, i, &fr);
713 ++i;
08dafab4
AK
714 int128_addto(&base, now);
715 offset_in_region += int128_get64(now);
716 int128_subfrom(&remain, now);
093bc2cd 717 }
d26a8cae
AK
718 now = int128_sub(int128_min(int128_add(base, remain),
719 addrrange_end(view->ranges[i].addr)),
720 base);
721 int128_addto(&base, now);
722 offset_in_region += int128_get64(now);
723 int128_subfrom(&remain, now);
093bc2cd 724 }
08dafab4 725 if (int128_nz(remain)) {
093bc2cd
AK
726 fr.offset_in_region = offset_in_region;
727 fr.addr = addrrange_make(base, remain);
728 flatview_insert(view, i, &fr);
729 }
730}
731
89c177bb
AK
732static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
733{
734 while (mr->alias && !mr->alias_offset &&
735 int128_ge(mr->size, mr->alias->size)) {
736 /* The alias is included in its entirety. Use it as
737 * the "real" root, so that we can share more FlatViews.
738 */
739 mr = mr->alias;
740 }
741
742 return mr;
743}
744
093bc2cd 745/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 746static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 747{
9bf561e3 748 int i;
a9a0c06d 749 FlatView *view;
093bc2cd 750
89c177bb 751 view = flatview_new(mr);
093bc2cd 752
83f3c251 753 if (mr) {
a9a0c06d 754 render_memory_region(view, mr, int128_zero(),
83f3c251
AK
755 addrrange_make(int128_zero(), int128_2_64()), false);
756 }
a9a0c06d 757 flatview_simplify(view);
093bc2cd 758
9bf561e3
AK
759 view->dispatch = address_space_dispatch_new(view);
760 for (i = 0; i < view->nr; i++) {
761 MemoryRegionSection mrs =
762 section_from_flat_range(&view->ranges[i], view);
763 flatview_add_to_dispatch(view, &mrs);
764 }
765 address_space_dispatch_compact(view->dispatch);
967dc9b1 766 g_hash_table_replace(flat_views, mr, view);
9bf561e3 767
093bc2cd
AK
768 return view;
769}
770
3e9d69e7
AK
771static void address_space_add_del_ioeventfds(AddressSpace *as,
772 MemoryRegionIoeventfd *fds_new,
773 unsigned fds_new_nb,
774 MemoryRegionIoeventfd *fds_old,
775 unsigned fds_old_nb)
776{
777 unsigned iold, inew;
80a1ea37
AK
778 MemoryRegionIoeventfd *fd;
779 MemoryRegionSection section;
3e9d69e7
AK
780
781 /* Generate a symmetric difference of the old and new fd sets, adding
782 * and deleting as necessary.
783 */
784
785 iold = inew = 0;
786 while (iold < fds_old_nb || inew < fds_new_nb) {
787 if (iold < fds_old_nb
788 && (inew == fds_new_nb
789 || memory_region_ioeventfd_before(fds_old[iold],
790 fds_new[inew]))) {
80a1ea37
AK
791 fd = &fds_old[iold];
792 section = (MemoryRegionSection) {
16620684 793 .fv = address_space_to_flatview(as),
80a1ea37 794 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 795 .size = fd->addr.size,
80a1ea37 796 };
9a54635d 797 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 798 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
799 ++iold;
800 } else if (inew < fds_new_nb
801 && (iold == fds_old_nb
802 || memory_region_ioeventfd_before(fds_new[inew],
803 fds_old[iold]))) {
80a1ea37
AK
804 fd = &fds_new[inew];
805 section = (MemoryRegionSection) {
16620684 806 .fv = address_space_to_flatview(as),
80a1ea37 807 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 808 .size = fd->addr.size,
80a1ea37 809 };
9a54635d 810 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 811 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
812 ++inew;
813 } else {
814 ++iold;
815 ++inew;
816 }
817 }
818}
819
856d7245
PB
820static FlatView *address_space_get_flatview(AddressSpace *as)
821{
822 FlatView *view;
823
374f2981 824 rcu_read_lock();
447b0d0b 825 do {
16620684 826 view = address_space_to_flatview(as);
447b0d0b
PB
827 /* If somebody has replaced as->current_map concurrently,
828 * flatview_ref returns false.
829 */
830 } while (!flatview_ref(view));
374f2981 831 rcu_read_unlock();
856d7245
PB
832 return view;
833}
834
3e9d69e7
AK
835static void address_space_update_ioeventfds(AddressSpace *as)
836{
99e86347 837 FlatView *view;
3e9d69e7
AK
838 FlatRange *fr;
839 unsigned ioeventfd_nb = 0;
840 MemoryRegionIoeventfd *ioeventfds = NULL;
841 AddrRange tmp;
842 unsigned i;
843
856d7245 844 view = address_space_get_flatview(as);
99e86347 845 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK
846 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
847 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK
848 int128_sub(fr->addr.start,
849 int128_make64(fr->offset_in_region)));
3e9d69e7
AK
850 if (addrrange_intersects(fr->addr, tmp)) {
851 ++ioeventfd_nb;
7267c094 852 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK
853 ioeventfd_nb * sizeof(*ioeventfds));
854 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
855 ioeventfds[ioeventfd_nb-1].addr = tmp;
856 }
857 }
858 }
859
860 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
861 as->ioeventfds, as->ioeventfd_nb);
862
7267c094 863 g_free(as->ioeventfds);
3e9d69e7
AK
864 as->ioeventfds = ioeventfds;
865 as->ioeventfd_nb = ioeventfd_nb;
856d7245 866 flatview_unref(view);
3e9d69e7
AK
867}
868
b8af1afb 869static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB
870 const FlatView *old_view,
871 const FlatView *new_view,
b8af1afb 872 bool adding)
093bc2cd 873{
093bc2cd
AK
874 unsigned iold, inew;
875 FlatRange *frold, *frnew;
093bc2cd
AK
876
877 /* Generate a symmetric difference of the old and new memory maps.
878 * Kill ranges in the old map, and instantiate ranges in the new map.
879 */
880 iold = inew = 0;
a9a0c06d
PB
881 while (iold < old_view->nr || inew < new_view->nr) {
882 if (iold < old_view->nr) {
883 frold = &old_view->ranges[iold];
093bc2cd
AK
884 } else {
885 frold = NULL;
886 }
a9a0c06d
PB
887 if (inew < new_view->nr) {
888 frnew = &new_view->ranges[inew];
093bc2cd
AK
889 } else {
890 frnew = NULL;
891 }
892
893 if (frold
894 && (!frnew
08dafab4
AK
895 || int128_lt(frold->addr.start, frnew->addr.start)
896 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 897 && !flatrange_equal(frold, frnew)))) {
41a6e477 898 /* In old but not in new, or in both but attributes changed. */
093bc2cd 899
b8af1afb 900 if (!adding) {
72e22d2f 901 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK
902 }
903
093bc2cd
AK
904 ++iold;
905 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 906 /* In both and unchanged (except logging may have changed) */
093bc2cd 907
b8af1afb 908 if (adding) {
50c1e149 909 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB
910 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
911 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
912 frold->dirty_log_mask,
913 frnew->dirty_log_mask);
914 }
915 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
916 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
917 frold->dirty_log_mask,
918 frnew->dirty_log_mask);
b8af1afb 919 }
5a583347
AK
920 }
921
093bc2cd
AK
922 ++iold;
923 ++inew;
093bc2cd
AK
924 } else {
925 /* In new */
926
b8af1afb 927 if (adding) {
72e22d2f 928 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK
929 }
930
093bc2cd
AK
931 ++inew;
932 }
933 }
b8af1afb
AK
934}
935
967dc9b1
AK
936static void flatviews_init(void)
937{
938 if (flat_views) {
939 return;
940 }
941
942 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
943 (GDestroyNotify) flatview_unref);
944}
945
946static void flatviews_reset(void)
947{
948 AddressSpace *as;
949
950 if (flat_views) {
951 g_hash_table_unref(flat_views);
952 flat_views = NULL;
953 }
954 flatviews_init();
955
956 /* Render unique FVs */
957 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
958 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
959
960 if (g_hash_table_lookup(flat_views, physmr)) {
961 continue;
962 }
963
964 generate_memory_topology(physmr);
965 }
966}
967
968static void address_space_set_flatview(AddressSpace *as)
b8af1afb 969{
856d7245 970 FlatView *old_view = address_space_get_flatview(as);
967dc9b1
AK
971 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
972 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
973
974 assert(new_view);
975
976 flatview_ref(new_view);
9a62e24f
AK
977
978 if (!QTAILQ_EMPTY(&as->listeners)) {
979 address_space_update_topology_pass(as, old_view, new_view, false);
980 address_space_update_topology_pass(as, old_view, new_view, true);
981 }
b8af1afb 982
374f2981
PB
983 /* Writes are protected by the BQL. */
984 atomic_rcu_set(&as->current_map, new_view);
66a6df1d 985 flatview_unref(old_view);
856d7245
PB
986
987 /* Note that all the old MemoryRegions are still alive up to this
988 * point. This relieves most MemoryListeners from the need to
989 * ref/unref the MemoryRegions they get---unless they use them
990 * outside the iothread mutex, in which case precise reference
991 * counting is necessary.
992 */
993 flatview_unref(old_view);
093bc2cd
AK
994}
995
4ef4db86
AK
996void memory_region_transaction_begin(void)
997{
bb880ded 998 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK
999 ++memory_region_transaction_depth;
1000}
1001
1002void memory_region_transaction_commit(void)
1003{
0d673e36
AK
1004 AddressSpace *as;
1005
4ef4db86 1006 assert(memory_region_transaction_depth);
8d04fb55
JK
1007 assert(qemu_mutex_iothread_locked());
1008
4ef4db86 1009 --memory_region_transaction_depth;
4dc56152
GA
1010 if (!memory_region_transaction_depth) {
1011 if (memory_region_update_pending) {
967dc9b1
AK
1012 flatviews_reset();
1013
4dc56152 1014 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 1015
4dc56152 1016 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
967dc9b1 1017 address_space_set_flatview(as);
02218487 1018 address_space_update_ioeventfds(as);
4dc56152 1019 }
ade9c1aa 1020 memory_region_update_pending = false;
4dc56152
GA
1021 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1022 } else if (ioeventfd_update_pending) {
1023 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1024 address_space_update_ioeventfds(as);
1025 }
ade9c1aa 1026 ioeventfd_update_pending = false;
4dc56152 1027 }
4dc56152 1028 }
4ef4db86
AK
1029}
1030
545e92e0
AK
1031static void memory_region_destructor_none(MemoryRegion *mr)
1032{
1033}
1034
1035static void memory_region_destructor_ram(MemoryRegion *mr)
1036{
f1060c55 1037 qemu_ram_free(mr->ram_block);
545e92e0
AK
1038}
1039
b4fefef9
PC
1040static bool memory_region_need_escape(char c)
1041{
1042 return c == '/' || c == '[' || c == '\\' || c == ']';
1043}
1044
1045static char *memory_region_escape_name(const char *name)
1046{
1047 const char *p;
1048 char *escaped, *q;
1049 uint8_t c;
1050 size_t bytes = 0;
1051
1052 for (p = name; *p; p++) {
1053 bytes += memory_region_need_escape(*p) ? 4 : 1;
1054 }
1055 if (bytes == p - name) {
1056 return g_memdup(name, bytes + 1);
1057 }
1058
1059 escaped = g_malloc(bytes + 1);
1060 for (p = name, q = escaped; *p; p++) {
1061 c = *p;
1062 if (unlikely(memory_region_need_escape(c))) {
1063 *q++ = '\\';
1064 *q++ = 'x';
1065 *q++ = "0123456789abcdef"[c >> 4];
1066 c = "0123456789abcdef"[c & 15];
1067 }
1068 *q++ = c;
1069 }
1070 *q = 0;
1071 return escaped;
1072}
1073
3df9d748
AK
1074static void memory_region_do_init(MemoryRegion *mr,
1075 Object *owner,
1076 const char *name,
1077 uint64_t size)
093bc2cd 1078{
08dafab4
AK
1079 mr->size = int128_make64(size);
1080 if (size == UINT64_MAX) {
1081 mr->size = int128_2_64();
1082 }
302fa283 1083 mr->name = g_strdup(name);
612263cf 1084 mr->owner = owner;
58eaa217 1085 mr->ram_block = NULL;
b4fefef9
PC
1086
1087 if (name) {
843ef73a
PC
1088 char *escaped_name = memory_region_escape_name(name);
1089 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB
1090
1091 if (!owner) {
1092 owner = container_get(qdev_get_machine(), "/unattached");
1093 }
1094
843ef73a 1095 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1096 object_unref(OBJECT(mr));
843ef73a
PC
1097 g_free(name_array);
1098 g_free(escaped_name);
b4fefef9
PC
1099 }
1100}
1101
3df9d748
AK
1102void memory_region_init(MemoryRegion *mr,
1103 Object *owner,
1104 const char *name,
1105 uint64_t size)
1106{
1107 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1108 memory_region_do_init(mr, owner, name, size);
1109}
1110
d7bce999
EB
1111static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1112 void *opaque, Error **errp)
409ddd01
PC
1113{
1114 MemoryRegion *mr = MEMORY_REGION(obj);
1115 uint64_t value = mr->addr;
1116
51e72bc1 1117 visit_type_uint64(v, name, &value, errp);
409ddd01
PC
1118}
1119
d7bce999
EB
1120static void memory_region_get_container(Object *obj, Visitor *v,
1121 const char *name, void *opaque,
1122 Error **errp)
409ddd01
PC
1123{
1124 MemoryRegion *mr = MEMORY_REGION(obj);
1125 gchar *path = (gchar *)"";
1126
1127 if (mr->container) {
1128 path = object_get_canonical_path(OBJECT(mr->container));
1129 }
51e72bc1 1130 visit_type_str(v, name, &path, errp);
409ddd01
PC
1131 if (mr->container) {
1132 g_free(path);
1133 }
1134}
1135
1136static Object *memory_region_resolve_container(Object *obj, void *opaque,
1137 const char *part)
1138{
1139 MemoryRegion *mr = MEMORY_REGION(obj);
1140
1141 return OBJECT(mr->container);
1142}
1143
d7bce999
EB
1144static void memory_region_get_priority(Object *obj, Visitor *v,
1145 const char *name, void *opaque,
1146 Error **errp)
d33382da
PC
1147{
1148 MemoryRegion *mr = MEMORY_REGION(obj);
1149 int32_t value = mr->priority;
1150
51e72bc1 1151 visit_type_int32(v, name, &value, errp);
d33382da
PC
1152}
1153
d7bce999
EB
1154static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1155 void *opaque, Error **errp)
52aef7bb
PC
1156{
1157 MemoryRegion *mr = MEMORY_REGION(obj);
1158 uint64_t value = memory_region_size(mr);
1159
51e72bc1 1160 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC
1161}
1162
b4fefef9
PC
1163static void memory_region_initfn(Object *obj)
1164{
1165 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1166 ObjectProperty *op;
b4fefef9
PC
1167
1168 mr->ops = &unassigned_mem_ops;
6bba19ba 1169 mr->enabled = true;
5f9a5ea1 1170 mr->romd_mode = true;
196ea131 1171 mr->global_locking = true;
545e92e0 1172 mr->destructor = memory_region_destructor_none;
093bc2cd 1173 QTAILQ_INIT(&mr->subregions);
093bc2cd 1174 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC
1175
1176 op = object_property_add(OBJECT(mr), "container",
1177 "link<" TYPE_MEMORY_REGION ">",
1178 memory_region_get_container,
1179 NULL, /* memory_region_set_container */
1180 NULL, NULL, &error_abort);
1181 op->resolve = memory_region_resolve_container;
1182
1183 object_property_add(OBJECT(mr), "addr", "uint64",
1184 memory_region_get_addr,
1185 NULL, /* memory_region_set_addr */
1186 NULL, NULL, &error_abort);
d33382da
PC
1187 object_property_add(OBJECT(mr), "priority", "uint32",
1188 memory_region_get_priority,
1189 NULL, /* memory_region_set_priority */
1190 NULL, NULL, &error_abort);
52aef7bb
PC
1191 object_property_add(OBJECT(mr), "size", "uint64",
1192 memory_region_get_size,
1193 NULL, /* memory_region_set_size, */
1194 NULL, NULL, &error_abort);
093bc2cd
AK
1195}
1196
3df9d748
AK
1197static void iommu_memory_region_initfn(Object *obj)
1198{
1199 MemoryRegion *mr = MEMORY_REGION(obj);
1200
1201 mr->is_iommu = true;
1202}
1203
b018ddf6
PB
1204static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1205 unsigned size)
1206{
1207#ifdef DEBUG_UNASSIGNED
1208 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1209#endif
4917cf44
AF
1210 if (current_cpu != NULL) {
1211 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
c658b94f 1212 }
68a7439a 1213 return 0;
b018ddf6
PB
1214}
1215
1216static void unassigned_mem_write(void *opaque, hwaddr addr,
1217 uint64_t val, unsigned size)
1218{
1219#ifdef DEBUG_UNASSIGNED
1220 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1221#endif
4917cf44
AF
1222 if (current_cpu != NULL) {
1223 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1224 }
b018ddf6
PB
1225}
1226
d197063f
PB
1227static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1228 unsigned size, bool is_write)
1229{
1230 return false;
1231}
1232
1233const MemoryRegionOps unassigned_mem_ops = {
1234 .valid.accepts = unassigned_mem_accepts,
1235 .endianness = DEVICE_NATIVE_ENDIAN,
1236};
1237
4a2e242b
AW
1238static uint64_t memory_region_ram_device_read(void *opaque,
1239 hwaddr addr, unsigned size)
1240{
1241 MemoryRegion *mr = opaque;
1242 uint64_t data = (uint64_t)~0;
1243
1244 switch (size) {
1245 case 1:
1246 data = *(uint8_t *)(mr->ram_block->host + addr);
1247 break;
1248 case 2:
1249 data = *(uint16_t *)(mr->ram_block->host + addr);
1250 break;
1251 case 4:
1252 data = *(uint32_t *)(mr->ram_block->host + addr);
1253 break;
1254 case 8:
1255 data = *(uint64_t *)(mr->ram_block->host + addr);
1256 break;
1257 }
1258
1259 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1260
1261 return data;
1262}
1263
1264static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1265 uint64_t data, unsigned size)
1266{
1267 MemoryRegion *mr = opaque;
1268
1269 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1270
1271 switch (size) {
1272 case 1:
1273 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1274 break;
1275 case 2:
1276 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1277 break;
1278 case 4:
1279 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1280 break;
1281 case 8:
1282 *(uint64_t *)(mr->ram_block->host + addr) = data;
1283 break;
1284 }
1285}
1286
1287static const MemoryRegionOps ram_device_mem_ops = {
1288 .read = memory_region_ram_device_read,
1289 .write = memory_region_ram_device_write,
c99a29e7 1290 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW
1291 .valid = {
1292 .min_access_size = 1,
1293 .max_access_size = 8,
1294 .unaligned = true,
1295 },
1296 .impl = {
1297 .min_access_size = 1,
1298 .max_access_size = 8,
1299 .unaligned = true,
1300 },
1301};
1302
d2702032
PB
1303bool memory_region_access_valid(MemoryRegion *mr,
1304 hwaddr addr,
1305 unsigned size,
1306 bool is_write)
093bc2cd 1307{
a014ed07
PB
1308 int access_size_min, access_size_max;
1309 int access_size, i;
897fa7cf 1310
093bc2cd
AK
1311 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1312 return false;
1313 }
1314
a014ed07 1315 if (!mr->ops->valid.accepts) {
093bc2cd
AK
1316 return true;
1317 }
1318
a014ed07
PB
1319 access_size_min = mr->ops->valid.min_access_size;
1320 if (!mr->ops->valid.min_access_size) {
1321 access_size_min = 1;
1322 }
1323
1324 access_size_max = mr->ops->valid.max_access_size;
1325 if (!mr->ops->valid.max_access_size) {
1326 access_size_max = 4;
1327 }
1328
1329 access_size = MAX(MIN(size, access_size_max), access_size_min);
1330 for (i = 0; i < size; i += access_size) {
1331 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1332 is_write)) {
1333 return false;
1334 }
093bc2cd 1335 }
a014ed07 1336
093bc2cd
AK
1337 return true;
1338}
1339
cc05c43a
PM
1340static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1341 hwaddr addr,
1342 uint64_t *pval,
1343 unsigned size,
1344 MemTxAttrs attrs)
093bc2cd 1345{
cc05c43a 1346 *pval = 0;
093bc2cd 1347
ce5d2f33 1348 if (mr->ops->read) {
cc05c43a
PM
1349 return access_with_adjusted_size(addr, pval, size,
1350 mr->ops->impl.min_access_size,
1351 mr->ops->impl.max_access_size,
1352 memory_region_read_accessor,
1353 mr, attrs);
1354 } else if (mr->ops->read_with_attrs) {
1355 return access_with_adjusted_size(addr, pval, size,
1356 mr->ops->impl.min_access_size,
1357 mr->ops->impl.max_access_size,
1358 memory_region_read_with_attrs_accessor,
1359 mr, attrs);
ce5d2f33 1360 } else {
cc05c43a
PM
1361 return access_with_adjusted_size(addr, pval, size, 1, 4,
1362 memory_region_oldmmio_read_accessor,
1363 mr, attrs);
74901c3b 1364 }
093bc2cd
AK
1365}
1366
3b643495
PM
1367MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1368 hwaddr addr,
1369 uint64_t *pval,
1370 unsigned size,
1371 MemTxAttrs attrs)
a621f38d 1372{
cc05c43a
PM
1373 MemTxResult r;
1374
791af8c8
PB
1375 if (!memory_region_access_valid(mr, addr, size, false)) {
1376 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1377 return MEMTX_DECODE_ERROR;
791af8c8 1378 }
a621f38d 1379
cc05c43a 1380 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1381 adjust_endianness(mr, pval, size);
cc05c43a 1382 return r;
a621f38d 1383}
093bc2cd 1384
8c56c1a5
PF
1385/* Return true if an eventfd was signalled */
1386static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1387 hwaddr addr,
1388 uint64_t data,
1389 unsigned size,
1390 MemTxAttrs attrs)
1391{
1392 MemoryRegionIoeventfd ioeventfd = {
1393 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1394 .data = data,
1395 };
1396 unsigned i;
1397
1398 for (i = 0; i < mr->ioeventfd_nb; i++) {
1399 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1400 ioeventfd.e = mr->ioeventfds[i].e;
1401
1402 if (memory_region_ioeventfd_equal(ioeventfd, mr->ioeventfds[i])) {
1403 event_notifier_set(ioeventfd.e);
1404 return true;
1405 }
1406 }
1407
1408 return false;
1409}
1410
3b643495
PM
1411MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1412 hwaddr addr,
1413 uint64_t data,
1414 unsigned size,
1415 MemTxAttrs attrs)
a621f38d 1416{
897fa7cf 1417 if (!memory_region_access_valid(mr, addr, size, true)) {
b018ddf6 1418 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1419 return MEMTX_DECODE_ERROR;
093bc2cd
AK
1420 }
1421
a621f38d
AK
1422 adjust_endianness(mr, &data, size);
1423
8c56c1a5
PF
1424 if ((!kvm_eventfds_enabled()) &&
1425 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1426 return MEMTX_OK;
1427 }
1428
ce5d2f33 1429 if (mr->ops->write) {
cc05c43a
PM
1430 return access_with_adjusted_size(addr, &data, size,
1431 mr->ops->impl.min_access_size,
1432 mr->ops->impl.max_access_size,
1433 memory_region_write_accessor, mr,
1434 attrs);
1435 } else if (mr->ops->write_with_attrs) {
1436 return
1437 access_with_adjusted_size(addr, &data, size,
1438 mr->ops->impl.min_access_size,
1439 mr->ops->impl.max_access_size,
1440 memory_region_write_with_attrs_accessor,
1441 mr, attrs);
ce5d2f33 1442 } else {
cc05c43a
PM
1443 return access_with_adjusted_size(addr, &data, size, 1, 4,
1444 memory_region_oldmmio_write_accessor,
1445 mr, attrs);
74901c3b 1446 }
093bc2cd
AK
1447}
1448
093bc2cd 1449void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1450 Object *owner,
093bc2cd
AK
1451 const MemoryRegionOps *ops,
1452 void *opaque,
1453 const char *name,
1454 uint64_t size)
1455{
2c9b15ca 1456 memory_region_init(mr, owner, name, size);
6d6d2abf 1457 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1458 mr->opaque = opaque;
14a3c10a 1459 mr->terminates = true;
093bc2cd
AK
1460}
1461
1cfe48c1
PM
1462void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1463 Object *owner,
1464 const char *name,
1465 uint64_t size,
1466 Error **errp)
093bc2cd 1467{
2c9b15ca 1468 memory_region_init(mr, owner, name, size);
8ea9252a 1469 mr->ram = true;
14a3c10a 1470 mr->terminates = true;
545e92e0 1471 mr->destructor = memory_region_destructor_ram;
8e41fb63 1472 mr->ram_block = qemu_ram_alloc(size, mr, errp);
677e7805 1473 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
0b183fc8
PB
1474}
1475
60786ef3
MT
1476void memory_region_init_resizeable_ram(MemoryRegion *mr,
1477 Object *owner,
1478 const char *name,
1479 uint64_t size,
1480 uint64_t max_size,
1481 void (*resized)(const char*,
1482 uint64_t length,
1483 void *host),
1484 Error **errp)
1485{
1486 memory_region_init(mr, owner, name, size);
1487 mr->ram = true;
1488 mr->terminates = true;
1489 mr->destructor = memory_region_destructor_ram;
8e41fb63
FZ
1490 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1491 mr, errp);
677e7805 1492 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
60786ef3
MT
1493}
1494
0b183fc8
PB
1495#ifdef __linux__
1496void memory_region_init_ram_from_file(MemoryRegion *mr,
1497 struct Object *owner,
1498 const char *name,
1499 uint64_t size,
dbcb8981 1500 bool share,
7f56e740
PB
1501 const char *path,
1502 Error **errp)
0b183fc8
PB
1503{
1504 memory_region_init(mr, owner, name, size);
1505 mr->ram = true;
1506 mr->terminates = true;
1507 mr->destructor = memory_region_destructor_ram;
8e41fb63 1508 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
677e7805 1509 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
093bc2cd 1510}
fea617c5
MAL
1511
1512void memory_region_init_ram_from_fd(MemoryRegion *mr,
1513 struct Object *owner,
1514 const char *name,
1515 uint64_t size,
1516 bool share,
1517 int fd,
1518 Error **errp)
1519{
1520 memory_region_init(mr, owner, name, size);
1521 mr->ram = true;
1522 mr->terminates = true;
1523 mr->destructor = memory_region_destructor_ram;
1524 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1525 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1526}
0b183fc8 1527#endif
093bc2cd
AK
1528
1529void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1530 Object *owner,
093bc2cd
AK
1531 const char *name,
1532 uint64_t size,
1533 void *ptr)
1534{
2c9b15ca 1535 memory_region_init(mr, owner, name, size);
8ea9252a 1536 mr->ram = true;
14a3c10a 1537 mr->terminates = true;
fc3e7665 1538 mr->destructor = memory_region_destructor_ram;
677e7805 1539 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT
1540
1541 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1542 assert(ptr != NULL);
8e41fb63 1543 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK
1544}
1545
21e00fa5
AW
1546void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1547 Object *owner,
1548 const char *name,
1549 uint64_t size,
1550 void *ptr)
e4dc3f59 1551{
21e00fa5
AW
1552 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1553 mr->ram_device = true;
4a2e242b
AW
1554 mr->ops = &ram_device_mem_ops;
1555 mr->opaque = mr;
e4dc3f59
ND
1556}
1557
093bc2cd 1558void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1559 Object *owner,
093bc2cd
AK
1560 const char *name,
1561 MemoryRegion *orig,
a8170e5e 1562 hwaddr offset,
093bc2cd
AK
1563 uint64_t size)
1564{
2c9b15ca 1565 memory_region_init(mr, owner, name, size);
093bc2cd
AK
1566 mr->alias = orig;
1567 mr->alias_offset = offset;
1568}
1569
b59821a9
PM
1570void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1571 struct Object *owner,
1572 const char *name,
1573 uint64_t size,
1574 Error **errp)
a1777f7f
PM
1575{
1576 memory_region_init(mr, owner, name, size);
1577 mr->ram = true;
1578 mr->readonly = true;
1579 mr->terminates = true;
1580 mr->destructor = memory_region_destructor_ram;
1581 mr->ram_block = qemu_ram_alloc(size, mr, errp);
1582 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1583}
1584
b59821a9
PM
1585void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1586 Object *owner,
1587 const MemoryRegionOps *ops,
1588 void *opaque,
1589 const char *name,
1590 uint64_t size,
1591 Error **errp)
d0a9b5bc 1592{
39e0b03d 1593 assert(ops);
2c9b15ca 1594 memory_region_init(mr, owner, name, size);
7bc2b9cd 1595 mr->ops = ops;
75f5941c 1596 mr->opaque = opaque;
d0a9b5bc 1597 mr->terminates = true;
75c578dc 1598 mr->rom_device = true;
58268c8d 1599 mr->destructor = memory_region_destructor_ram;
8e41fb63 1600 mr->ram_block = qemu_ram_alloc(size, mr, errp);
d0a9b5bc
AK
1601}
1602
1221a474
AK
1603void memory_region_init_iommu(void *_iommu_mr,
1604 size_t instance_size,
1605 const char *mrtypename,
2c9b15ca 1606 Object *owner,
30951157
AK
1607 const char *name,
1608 uint64_t size)
1609{
1221a474 1610 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK
1611 struct MemoryRegion *mr;
1612
1221a474
AK
1613 object_initialize(_iommu_mr, instance_size, mrtypename);
1614 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK
1615 memory_region_do_init(mr, owner, name, size);
1616 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1617 mr->terminates = true; /* then re-forwards */
3df9d748
AK
1618 QLIST_INIT(&iommu_mr->iommu_notify);
1619 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK
1620}
1621
b4fefef9 1622static void memory_region_finalize(Object *obj)
093bc2cd 1623{
b4fefef9
PC
1624 MemoryRegion *mr = MEMORY_REGION(obj);
1625
2e2b8eb7
PB
1626 assert(!mr->container);
1627
1628 /* We know the region is not visible in any address space (it
1629 * does not have a container and cannot be a root either because
1630 * it has no references, so we can blindly clear mr->enabled.
1631 * memory_region_set_enabled instead could trigger a transaction
1632 * and cause an infinite loop.
1633 */
1634 mr->enabled = false;
1635 memory_region_transaction_begin();
1636 while (!QTAILQ_EMPTY(&mr->subregions)) {
1637 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1638 memory_region_del_subregion(mr, subregion);
1639 }
1640 memory_region_transaction_commit();
1641
545e92e0 1642 mr->destructor(mr);
093bc2cd 1643 memory_region_clear_coalescing(mr);
302fa283 1644 g_free((char *)mr->name);
7267c094 1645 g_free(mr->ioeventfds);
093bc2cd
AK
1646}
1647
803c0816
PB
1648Object *memory_region_owner(MemoryRegion *mr)
1649{
22a893e4
PB
1650 Object *obj = OBJECT(mr);
1651 return obj->parent;
803c0816
PB
1652}
1653
46637be2
PB
1654void memory_region_ref(MemoryRegion *mr)
1655{
22a893e4
PB
1656 /* MMIO callbacks most likely will access data that belongs
1657 * to the owner, hence the need to ref/unref the owner whenever
1658 * the memory region is in use.
1659 *
1660 * The memory region is a child of its owner. As long as the
1661 * owner doesn't call unparent itself on the memory region,
1662 * ref-ing the owner will also keep the memory region alive.
612263cf
PB
1663 * Memory regions without an owner are supposed to never go away;
1664 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1665 */
612263cf
PB
1666 if (mr && mr->owner) {
1667 object_ref(mr->owner);
46637be2
PB
1668 }
1669}
1670
1671void memory_region_unref(MemoryRegion *mr)
1672{
612263cf
PB
1673 if (mr && mr->owner) {
1674 object_unref(mr->owner);
46637be2
PB
1675 }
1676}
1677
093bc2cd
AK
1678uint64_t memory_region_size(MemoryRegion *mr)
1679{
08dafab4
AK
1680 if (int128_eq(mr->size, int128_2_64())) {
1681 return UINT64_MAX;
1682 }
1683 return int128_get64(mr->size);
093bc2cd
AK
1684}
1685
5d546d4b 1686const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1687{
d1dd32af
PC
1688 if (!mr->name) {
1689 ((MemoryRegion *)mr)->name =
1690 object_get_canonical_path_component(OBJECT(mr));
1691 }
302fa283 1692 return mr->name;
8991c79b
AK
1693}
1694
21e00fa5 1695bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1696{
21e00fa5 1697 return mr->ram_device;
e4dc3f59
ND
1698}
1699
2d1a35be 1700uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1701{
6f6a5ef3 1702 uint8_t mask = mr->dirty_log_mask;
adaad61c 1703 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB
1704 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1705 }
1706 return mask;
55043ba3
AK
1707}
1708
2d1a35be
PB
1709bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1710{
1711 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1712}
1713
3df9d748 1714static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
5bf3d319
PX
1715{
1716 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1717 IOMMUNotifier *iommu_notifier;
1221a474 1718 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
5bf3d319 1719
3df9d748 1720 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX
1721 flags |= iommu_notifier->notifier_flags;
1722 }
1723
1221a474
AK
1724 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1725 imrc->notify_flag_changed(iommu_mr,
1726 iommu_mr->iommu_notify_flags,
1727 flags);
5bf3d319
PX
1728 }
1729
3df9d748 1730 iommu_mr->iommu_notify_flags = flags;
5bf3d319
PX
1731}
1732
cdb30812
PX
1733void memory_region_register_iommu_notifier(MemoryRegion *mr,
1734 IOMMUNotifier *n)
06866575 1735{
3df9d748
AK
1736 IOMMUMemoryRegion *iommu_mr;
1737
efcd38c5
JW
1738 if (mr->alias) {
1739 memory_region_register_iommu_notifier(mr->alias, n);
1740 return;
1741 }
1742
cdb30812 1743 /* We need to register for at least one bitfield */
3df9d748 1744 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1745 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1746 assert(n->start <= n->end);
3df9d748
AK
1747 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1748 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1749}
1750
3df9d748 1751uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1752{
1221a474
AK
1753 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1754
1755 if (imrc->get_min_page_size) {
1756 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK
1757 }
1758 return TARGET_PAGE_SIZE;
1759}
1760
3df9d748 1761void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1762{
3df9d748 1763 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1764 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1765 hwaddr addr, granularity;
a788f227
DG
1766 IOMMUTLBEntry iotlb;
1767
faa362e3 1768 /* If the IOMMU has its own replay callback, override */
1221a474
AK
1769 if (imrc->replay) {
1770 imrc->replay(iommu_mr, n);
faa362e3
PX
1771 return;
1772 }
1773
3df9d748 1774 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1775
a788f227 1776 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1221a474 1777 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE);
a788f227
DG
1778 if (iotlb.perm != IOMMU_NONE) {
1779 n->notify(n, &iotlb);
1780 }
1781
1782 /* if (2^64 - MR size) < granularity, it's possible to get an
1783 * infinite loop here. This should catch such a wraparound */
1784 if ((addr + granularity) < addr) {
1785 break;
1786 }
1787 }
1788}
1789
3df9d748 1790void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
de472e4a
PX
1791{
1792 IOMMUNotifier *notifier;
1793
3df9d748
AK
1794 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1795 memory_region_iommu_replay(iommu_mr, notifier);
de472e4a
PX
1796 }
1797}
1798
cdb30812
PX
1799void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1800 IOMMUNotifier *n)
06866575 1801{
3df9d748
AK
1802 IOMMUMemoryRegion *iommu_mr;
1803
efcd38c5
JW
1804 if (mr->alias) {
1805 memory_region_unregister_iommu_notifier(mr->alias, n);
1806 return;
1807 }
cdb30812 1808 QLIST_REMOVE(n, node);
3df9d748
AK
1809 iommu_mr = IOMMU_MEMORY_REGION(mr);
1810 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1811}
1812
bd2bfa4c
PX
1813void memory_region_notify_one(IOMMUNotifier *notifier,
1814 IOMMUTLBEntry *entry)
06866575 1815{
cdb30812
PX
1816 IOMMUNotifierFlag request_flags;
1817
bd2bfa4c
PX
1818 /*
1819 * Skip the notification if the notification does not overlap
1820 * with registered range.
1821 */
1822 if (notifier->start > entry->iova + entry->addr_mask + 1 ||
1823 notifier->end < entry->iova) {
1824 return;
1825 }
cdb30812 1826
bd2bfa4c 1827 if (entry->perm & IOMMU_RW) {
cdb30812
PX
1828 request_flags = IOMMU_NOTIFIER_MAP;
1829 } else {
1830 request_flags = IOMMU_NOTIFIER_UNMAP;
1831 }
1832
bd2bfa4c
PX
1833 if (notifier->notifier_flags & request_flags) {
1834 notifier->notify(notifier, entry);
1835 }
1836}
1837
3df9d748 1838void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
bd2bfa4c
PX
1839 IOMMUTLBEntry entry)
1840{
1841 IOMMUNotifier *iommu_notifier;
1842
3df9d748 1843 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1844
3df9d748 1845 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
bd2bfa4c 1846 memory_region_notify_one(iommu_notifier, &entry);
cdb30812 1847 }
06866575
DG
1848}
1849
093bc2cd
AK
1850void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1851{
5a583347 1852 uint8_t mask = 1 << client;
deb809ed 1853 uint8_t old_logging;
5a583347 1854
dbddac6d 1855 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB
1856 old_logging = mr->vga_logging_count;
1857 mr->vga_logging_count += log ? 1 : -1;
1858 if (!!old_logging == !!mr->vga_logging_count) {
1859 return;
1860 }
1861
59023ef4 1862 memory_region_transaction_begin();
5a583347 1863 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1864 memory_region_update_pending |= mr->enabled;
59023ef4 1865 memory_region_transaction_commit();
093bc2cd
AK
1866}
1867
a8170e5e
AK
1868bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1869 hwaddr size, unsigned client)
093bc2cd 1870{
8e41fb63
FZ
1871 assert(mr->ram_block);
1872 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1873 size, client);
093bc2cd
AK
1874}
1875
a8170e5e
AK
1876void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1877 hwaddr size)
093bc2cd 1878{
8e41fb63
FZ
1879 assert(mr->ram_block);
1880 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1881 size,
58d2707e 1882 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK
1883}
1884
6c279db8
JQ
1885bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1886 hwaddr size, unsigned client)
1887{
8e41fb63
FZ
1888 assert(mr->ram_block);
1889 return cpu_physical_memory_test_and_clear_dirty(
1890 memory_region_get_ram_addr(mr) + addr, size, client);
6c279db8
JQ
1891}
1892
8deaf12c
GH
1893DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
1894 hwaddr addr,
1895 hwaddr size,
1896 unsigned client)
1897{
1898 assert(mr->ram_block);
1899 return cpu_physical_memory_snapshot_and_clear_dirty(
1900 memory_region_get_ram_addr(mr) + addr, size, client);
1901}
1902
1903bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
1904 hwaddr addr, hwaddr size)
1905{
1906 assert(mr->ram_block);
1907 return cpu_physical_memory_snapshot_get_dirty(snap,
1908 memory_region_get_ram_addr(mr) + addr, size);
1909}
6c279db8 1910
093bc2cd
AK
1911void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1912{
0a752eee 1913 MemoryListener *listener;
0d673e36 1914 AddressSpace *as;
0a752eee 1915 FlatView *view;
5a583347
AK
1916 FlatRange *fr;
1917
0a752eee
PB
1918 /* If the same address space has multiple log_sync listeners, we
1919 * visit that address space's FlatView multiple times. But because
1920 * log_sync listeners are rare, it's still cheaper than walking each
1921 * address space once.
1922 */
1923 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1924 if (!listener->log_sync) {
1925 continue;
1926 }
1927 as = listener->address_space;
1928 view = address_space_get_flatview(as);
99e86347 1929 FOR_EACH_FLAT_RANGE(fr, view) {
0d673e36 1930 if (fr->mr == mr) {
16620684 1931 MemoryRegionSection mrs = section_from_flat_range(fr, view);
0a752eee 1932 listener->log_sync(listener, &mrs);
0d673e36 1933 }
5a583347 1934 }
856d7245 1935 flatview_unref(view);
5a583347 1936 }
093bc2cd
AK
1937}
1938
1939void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1940{
fb1cd6f9 1941 if (mr->readonly != readonly) {
59023ef4 1942 memory_region_transaction_begin();
fb1cd6f9 1943 mr->readonly = readonly;
22bde714 1944 memory_region_update_pending |= mr->enabled;
59023ef4 1945 memory_region_transaction_commit();
fb1cd6f9 1946 }
093bc2cd
AK
1947}
1948
5f9a5ea1 1949void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 1950{
5f9a5ea1 1951 if (mr->romd_mode != romd_mode) {
59023ef4 1952 memory_region_transaction_begin();
5f9a5ea1 1953 mr->romd_mode = romd_mode;
22bde714 1954 memory_region_update_pending |= mr->enabled;
59023ef4 1955 memory_region_transaction_commit();
d0a9b5bc
AK
1956 }
1957}
1958
a8170e5e
AK
1959void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
1960 hwaddr size, unsigned client)
093bc2cd 1961{
8e41fb63
FZ
1962 assert(mr->ram_block);
1963 cpu_physical_memory_test_and_clear_dirty(
1964 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK
1965}
1966
a35ba7be
PB
1967int memory_region_get_fd(MemoryRegion *mr)
1968{
4ff87573
PB
1969 int fd;
1970
1971 rcu_read_lock();
1972 while (mr->alias) {
1973 mr = mr->alias;
a35ba7be 1974 }
4ff87573
PB
1975 fd = mr->ram_block->fd;
1976 rcu_read_unlock();
a35ba7be 1977
4ff87573
PB
1978 return fd;
1979}
a35ba7be 1980
093bc2cd
AK
1981void *memory_region_get_ram_ptr(MemoryRegion *mr)
1982{
49b24afc
PB
1983 void *ptr;
1984 uint64_t offset = 0;
093bc2cd 1985
49b24afc
PB
1986 rcu_read_lock();
1987 while (mr->alias) {
1988 offset += mr->alias_offset;
1989 mr = mr->alias;
1990 }
8e41fb63 1991 assert(mr->ram_block);
0878d0e1 1992 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
49b24afc 1993 rcu_read_unlock();
093bc2cd 1994
0878d0e1 1995 return ptr;
093bc2cd
AK
1996}
1997
07bdaa41
PB
1998MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
1999{
2000 RAMBlock *block;
2001
2002 block = qemu_ram_block_from_host(ptr, false, offset);
2003 if (!block) {
2004 return NULL;
2005 }
2006
2007 return block->mr;
2008}
2009
7ebb2745
FZ
2010ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2011{
2012 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2013}
2014
37d7c084
PB
2015void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2016{
8e41fb63 2017 assert(mr->ram_block);
37d7c084 2018
fa53a0e5 2019 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB
2020}
2021
0d673e36 2022static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 2023{
99e86347 2024 FlatView *view;
093bc2cd
AK
2025 FlatRange *fr;
2026 CoalescedMemoryRange *cmr;
2027 AddrRange tmp;
95d2994a 2028 MemoryRegionSection section;
093bc2cd 2029
856d7245 2030 view = address_space_get_flatview(as);
99e86347 2031 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 2032 if (fr->mr == mr) {
95d2994a 2033 section = (MemoryRegionSection) {
16620684 2034 .fv = view,
95d2994a 2035 .offset_within_address_space = int128_get64(fr->addr.start),
052e87b0 2036 .size = fr->addr.size,
95d2994a
AK
2037 };
2038
9a54635d 2039 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
95d2994a
AK
2040 int128_get64(fr->addr.start),
2041 int128_get64(fr->addr.size));
093bc2cd
AK
2042 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
2043 tmp = addrrange_shift(cmr->addr,
08dafab4
AK
2044 int128_sub(fr->addr.start,
2045 int128_make64(fr->offset_in_region)));
093bc2cd
AK
2046 if (!addrrange_intersects(tmp, fr->addr)) {
2047 continue;
2048 }
2049 tmp = addrrange_intersection(tmp, fr->addr);
9a54635d 2050 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
95d2994a
AK
2051 int128_get64(tmp.start),
2052 int128_get64(tmp.size));
093bc2cd
AK
2053 }
2054 }
2055 }
856d7245 2056 flatview_unref(view);
093bc2cd
AK
2057}
2058
0d673e36
AK
2059static void memory_region_update_coalesced_range(MemoryRegion *mr)
2060{
2061 AddressSpace *as;
2062
2063 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2064 memory_region_update_coalesced_range_as(mr, as);
2065 }
2066}
2067
093bc2cd
AK
2068void memory_region_set_coalescing(MemoryRegion *mr)
2069{
2070 memory_region_clear_coalescing(mr);
08dafab4 2071 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK
2072}
2073
2074void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 2075 hwaddr offset,
093bc2cd
AK
2076 uint64_t size)
2077{
7267c094 2078 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2079
08dafab4 2080 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK
2081 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2082 memory_region_update_coalesced_range(mr);
d410515e 2083 memory_region_set_flush_coalesced(mr);
093bc2cd
AK
2084}
2085
2086void memory_region_clear_coalescing(MemoryRegion *mr)
2087{
2088 CoalescedMemoryRange *cmr;
ab5b3db5 2089 bool updated = false;
093bc2cd 2090
d410515e
JK
2091 qemu_flush_coalesced_mmio_buffer();
2092 mr->flush_coalesced_mmio = false;
2093
093bc2cd
AK
2094 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2095 cmr = QTAILQ_FIRST(&mr->coalesced);
2096 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 2097 g_free(cmr);
ab5b3db5
FZ
2098 updated = true;
2099 }
2100
2101 if (updated) {
2102 memory_region_update_coalesced_range(mr);
093bc2cd 2103 }
093bc2cd
AK
2104}
2105
d410515e
JK
2106void memory_region_set_flush_coalesced(MemoryRegion *mr)
2107{
2108 mr->flush_coalesced_mmio = true;
2109}
2110
2111void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2112{
2113 qemu_flush_coalesced_mmio_buffer();
2114 if (QTAILQ_EMPTY(&mr->coalesced)) {
2115 mr->flush_coalesced_mmio = false;
2116 }
2117}
2118
196ea131
JK
2119void memory_region_set_global_locking(MemoryRegion *mr)
2120{
2121 mr->global_locking = true;
2122}
2123
2124void memory_region_clear_global_locking(MemoryRegion *mr)
2125{
2126 mr->global_locking = false;
2127}
2128
8c56c1a5
PF
2129static bool userspace_eventfd_warning;
2130
3e9d69e7 2131void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2132 hwaddr addr,
3e9d69e7
AK
2133 unsigned size,
2134 bool match_data,
2135 uint64_t data,
753d5e14 2136 EventNotifier *e)
3e9d69e7
AK
2137{
2138 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2139 .addr.start = int128_make64(addr),
2140 .addr.size = int128_make64(size),
3e9d69e7
AK
2141 .match_data = match_data,
2142 .data = data,
753d5e14 2143 .e = e,
3e9d69e7
AK
2144 };
2145 unsigned i;
2146
8c56c1a5
PF
2147 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2148 userspace_eventfd_warning))) {
2149 userspace_eventfd_warning = true;
2150 error_report("Using eventfd without MMIO binding in KVM. "
2151 "Suboptimal performance expected");
2152 }
2153
b8aecea2
JW
2154 if (size) {
2155 adjust_endianness(mr, &mrfd.data, size);
2156 }
59023ef4 2157 memory_region_transaction_begin();
3e9d69e7
AK
2158 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2159 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
2160 break;
2161 }
2162 }
2163 ++mr->ioeventfd_nb;
7267c094 2164 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK
2165 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2166 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2167 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2168 mr->ioeventfds[i] = mrfd;
4dc56152 2169 ioeventfd_update_pending |= mr->enabled;
59023ef4 2170 memory_region_transaction_commit();
3e9d69e7
AK
2171}
2172
2173void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2174 hwaddr addr,
3e9d69e7
AK
2175 unsigned size,
2176 bool match_data,
2177 uint64_t data,
753d5e14 2178 EventNotifier *e)
3e9d69e7
AK
2179{
2180 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2181 .addr.start = int128_make64(addr),
2182 .addr.size = int128_make64(size),
3e9d69e7
AK
2183 .match_data = match_data,
2184 .data = data,
753d5e14 2185 .e = e,
3e9d69e7
AK
2186 };
2187 unsigned i;
2188
b8aecea2
JW
2189 if (size) {
2190 adjust_endianness(mr, &mrfd.data, size);
2191 }
59023ef4 2192 memory_region_transaction_begin();
3e9d69e7
AK
2193 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2194 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
2195 break;
2196 }
2197 }
2198 assert(i != mr->ioeventfd_nb);
2199 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2200 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2201 --mr->ioeventfd_nb;
7267c094 2202 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2203 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2204 ioeventfd_update_pending |= mr->enabled;
59023ef4 2205 memory_region_transaction_commit();
3e9d69e7
AK
2206}
2207
feca4ac1 2208static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2209{
feca4ac1 2210 MemoryRegion *mr = subregion->container;
093bc2cd
AK
2211 MemoryRegion *other;
2212
59023ef4
JK
2213 memory_region_transaction_begin();
2214
dfde4e6e 2215 memory_region_ref(subregion);
093bc2cd
AK
2216 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2217 if (subregion->priority >= other->priority) {
2218 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2219 goto done;
2220 }
2221 }
2222 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2223done:
22bde714 2224 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2225 memory_region_transaction_commit();
093bc2cd
AK
2226}
2227
0598701a
PC
2228static void memory_region_add_subregion_common(MemoryRegion *mr,
2229 hwaddr offset,
2230 MemoryRegion *subregion)
2231{
feca4ac1
PB
2232 assert(!subregion->container);
2233 subregion->container = mr;
0598701a 2234 subregion->addr = offset;
feca4ac1 2235 memory_region_update_container_subregions(subregion);
0598701a 2236}
093bc2cd
AK
2237
2238void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2239 hwaddr offset,
093bc2cd
AK
2240 MemoryRegion *subregion)
2241{
093bc2cd
AK
2242 subregion->priority = 0;
2243 memory_region_add_subregion_common(mr, offset, subregion);
2244}
2245
2246void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2247 hwaddr offset,
093bc2cd 2248 MemoryRegion *subregion,
a1ff8ae0 2249 int priority)
093bc2cd 2250{
093bc2cd
AK
2251 subregion->priority = priority;
2252 memory_region_add_subregion_common(mr, offset, subregion);
2253}
2254
2255void memory_region_del_subregion(MemoryRegion *mr,
2256 MemoryRegion *subregion)
2257{
59023ef4 2258 memory_region_transaction_begin();
feca4ac1
PB
2259 assert(subregion->container == mr);
2260 subregion->container = NULL;
093bc2cd 2261 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2262 memory_region_unref(subregion);
22bde714 2263 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2264 memory_region_transaction_commit();
6bba19ba
AK
2265}
2266
2267void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2268{
2269 if (enabled == mr->enabled) {
2270 return;
2271 }
59023ef4 2272 memory_region_transaction_begin();
6bba19ba 2273 mr->enabled = enabled;
22bde714 2274 memory_region_update_pending = true;
59023ef4 2275 memory_region_transaction_commit();
093bc2cd 2276}
1c0ffa58 2277
e7af4c67
MT
2278void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2279{
2280 Int128 s = int128_make64(size);
2281
2282 if (size == UINT64_MAX) {
2283 s = int128_2_64();
2284 }
2285 if (int128_eq(s, mr->size)) {
2286 return;
2287 }
2288 memory_region_transaction_begin();
2289 mr->size = s;
2290 memory_region_update_pending = true;
2291 memory_region_transaction_commit();
2292}
2293
67891b8a 2294static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2295{
feca4ac1 2296 MemoryRegion *container = mr->container;
2282e1af 2297
feca4ac1 2298 if (container) {
67891b8a
PC
2299 memory_region_transaction_begin();
2300 memory_region_ref(mr);
feca4ac1
PB
2301 memory_region_del_subregion(container, mr);
2302 mr->container = container;
2303 memory_region_update_container_subregions(mr);
67891b8a
PC
2304 memory_region_unref(mr);
2305 memory_region_transaction_commit();
2282e1af 2306 }
67891b8a 2307}
2282e1af 2308
67891b8a
PC
2309void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2310{
2311 if (addr != mr->addr) {
2312 mr->addr = addr;
2313 memory_region_readd_subregion(mr);
2314 }
2282e1af
AK
2315}
2316
a8170e5e 2317void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2318{
4703359e 2319 assert(mr->alias);
4703359e 2320
59023ef4 2321 if (offset == mr->alias_offset) {
4703359e
AK
2322 return;
2323 }
2324
59023ef4
JK
2325 memory_region_transaction_begin();
2326 mr->alias_offset = offset;
22bde714 2327 memory_region_update_pending |= mr->enabled;
59023ef4 2328 memory_region_transaction_commit();
4703359e
AK
2329}
2330
a2b257d6
IM
2331uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2332{
2333 return mr->align;
2334}
2335
e2177955
AK
2336static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2337{
2338 const AddrRange *addr = addr_;
2339 const FlatRange *fr = fr_;
2340
2341 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2342 return -1;
2343 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2344 return 1;
2345 }
2346 return 0;
2347}
2348
99e86347 2349static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2350{
99e86347 2351 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK
2352 sizeof(FlatRange), cmp_flatrange_addr);
2353}
2354
eed2bacf
IM
2355bool memory_region_is_mapped(MemoryRegion *mr)
2356{
2357 return mr->container ? true : false;
2358}
2359
c6742b14
PB
2360/* Same as memory_region_find, but it does not add a reference to the
2361 * returned region. It must be called from an RCU critical section.
2362 */
2363static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2364 hwaddr addr, uint64_t size)
e2177955 2365{
052e87b0 2366 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB
2367 MemoryRegion *root;
2368 AddressSpace *as;
2369 AddrRange range;
99e86347 2370 FlatView *view;
73034e9e
PB
2371 FlatRange *fr;
2372
2373 addr += mr->addr;
feca4ac1
PB
2374 for (root = mr; root->container; ) {
2375 root = root->container;
73034e9e
PB
2376 addr += root->addr;
2377 }
e2177955 2378
73034e9e 2379 as = memory_region_to_address_space(root);
eed2bacf
IM
2380 if (!as) {
2381 return ret;
2382 }
73034e9e 2383 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2384
16620684 2385 view = address_space_to_flatview(as);
99e86347 2386 fr = flatview_lookup(view, range);
e2177955 2387 if (!fr) {
c6742b14 2388 return ret;
e2177955
AK
2389 }
2390
99e86347 2391 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK
2392 --fr;
2393 }
2394
2395 ret.mr = fr->mr;
16620684 2396 ret.fv = view;
e2177955
AK
2397 range = addrrange_intersection(range, fr->addr);
2398 ret.offset_within_region = fr->offset_in_region;
2399 ret.offset_within_region += int128_get64(int128_sub(range.start,
2400 fr->addr.start));
052e87b0 2401 ret.size = range.size;
e2177955 2402 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2403 ret.readonly = fr->readonly;
c6742b14
PB
2404 return ret;
2405}
2406
2407MemoryRegionSection memory_region_find(MemoryRegion *mr,
2408 hwaddr addr, uint64_t size)
2409{
2410 MemoryRegionSection ret;
2411 rcu_read_lock();
2412 ret = memory_region_find_rcu(mr, addr, size);
2413 if (ret.mr) {
2414 memory_region_ref(ret.mr);
2415 }
2b647668 2416 rcu_read_unlock();
e2177955
AK
2417 return ret;
2418}
2419
c6742b14
PB
2420bool memory_region_present(MemoryRegion *container, hwaddr addr)
2421{
2422 MemoryRegion *mr;
2423
2424 rcu_read_lock();
2425 mr = memory_region_find_rcu(container, addr, 1).mr;
2426 rcu_read_unlock();
2427 return mr && mr != container;
2428}
2429
9c1f8f44 2430void memory_global_dirty_log_sync(void)
86e775c6 2431{
9c1f8f44
PB
2432 MemoryListener *listener;
2433 AddressSpace *as;
99e86347 2434 FlatView *view;
7664e80c
AK
2435 FlatRange *fr;
2436
9c1f8f44
PB
2437 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2438 if (!listener->log_sync) {
2439 continue;
2440 }
d45fa784 2441 as = listener->address_space;
9c1f8f44
PB
2442 view = address_space_get_flatview(as);
2443 FOR_EACH_FLAT_RANGE(fr, view) {
adaad61c 2444 if (fr->dirty_log_mask) {
16620684
AK
2445 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2446
adaad61c
PB
2447 listener->log_sync(listener, &mrs);
2448 }
9c1f8f44
PB
2449 }
2450 flatview_unref(view);
7664e80c
AK
2451 }
2452}
2453
19310760
JZ
2454static VMChangeStateEntry *vmstate_change;
2455
7664e80c
AK
2456void memory_global_dirty_log_start(void)
2457{
19310760
JZ
2458 if (vmstate_change) {
2459 qemu_del_vm_change_state_handler(vmstate_change);
2460 vmstate_change = NULL;
2461 }
2462
7664e80c 2463 global_dirty_log = true;
6f6a5ef3 2464
7376e582 2465 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3
PB
2466
2467 /* Refresh DIRTY_LOG_MIGRATION bit. */
2468 memory_region_transaction_begin();
2469 memory_region_update_pending = true;
2470 memory_region_transaction_commit();
7664e80c
AK
2471}
2472
19310760 2473static void memory_global_dirty_log_do_stop(void)
7664e80c 2474{
7664e80c 2475 global_dirty_log = false;
6f6a5ef3
PB
2476
2477 /* Refresh DIRTY_LOG_MIGRATION bit. */
2478 memory_region_transaction_begin();
2479 memory_region_update_pending = true;
2480 memory_region_transaction_commit();
2481
7376e582 2482 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK
2483}
2484
19310760
JZ
2485static void memory_vm_change_state_handler(void *opaque, int running,
2486 RunState state)
2487{
2488 if (running) {
2489 memory_global_dirty_log_do_stop();
2490
2491 if (vmstate_change) {
2492 qemu_del_vm_change_state_handler(vmstate_change);
2493 vmstate_change = NULL;
2494 }
2495 }
2496}
2497
2498void memory_global_dirty_log_stop(void)
2499{
2500 if (!runstate_is_running()) {
2501 if (vmstate_change) {
2502 return;
2503 }
2504 vmstate_change = qemu_add_vm_change_state_handler(
2505 memory_vm_change_state_handler, NULL);
2506 return;
2507 }
2508
2509 memory_global_dirty_log_do_stop();
2510}
2511
7664e80c
AK
2512static void listener_add_address_space(MemoryListener *listener,
2513 AddressSpace *as)
2514{
99e86347 2515 FlatView *view;
7664e80c
AK
2516 FlatRange *fr;
2517
680a4783
PB
2518 if (listener->begin) {
2519 listener->begin(listener);
2520 }
7664e80c 2521 if (global_dirty_log) {
975aefe0
AK
2522 if (listener->log_global_start) {
2523 listener->log_global_start(listener);
2524 }
7664e80c 2525 }
975aefe0 2526
856d7245 2527 view = address_space_get_flatview(as);
99e86347 2528 FOR_EACH_FLAT_RANGE(fr, view) {
7664e80c
AK
2529 MemoryRegionSection section = {
2530 .mr = fr->mr,
16620684 2531 .fv = view,
7664e80c 2532 .offset_within_region = fr->offset_in_region,
052e87b0 2533 .size = fr->addr.size,
7664e80c 2534 .offset_within_address_space = int128_get64(fr->addr.start),
7a8499e8 2535 .readonly = fr->readonly,
7664e80c 2536 };
680a4783
PB
2537 if (fr->dirty_log_mask && listener->log_start) {
2538 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2539 }
975aefe0
AK
2540 if (listener->region_add) {
2541 listener->region_add(listener, &section);
2542 }
7664e80c 2543 }
680a4783
PB
2544 if (listener->commit) {
2545 listener->commit(listener);
2546 }
856d7245 2547 flatview_unref(view);
7664e80c
AK
2548}
2549
d45fa784 2550void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2551{
72e22d2f
AK
2552 MemoryListener *other = NULL;
2553
d45fa784 2554 listener->address_space = as;
72e22d2f
AK
2555 if (QTAILQ_EMPTY(&memory_listeners)
2556 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2557 memory_listeners)->priority) {
2558 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2559 } else {
2560 QTAILQ_FOREACH(other, &memory_listeners, link) {
2561 if (listener->priority < other->priority) {
2562 break;
2563 }
2564 }
2565 QTAILQ_INSERT_BEFORE(other, listener, link);
2566 }
0d673e36 2567
9a54635d
PB
2568 if (QTAILQ_EMPTY(&as->listeners)
2569 || listener->priority >= QTAILQ_LAST(&as->listeners,
2570 memory_listeners)->priority) {
2571 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2572 } else {
2573 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2574 if (listener->priority < other->priority) {
2575 break;
2576 }
2577 }
2578 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2579 }
2580
d45fa784 2581 listener_add_address_space(listener, as);
7664e80c
AK
2582}
2583
2584void memory_listener_unregister(MemoryListener *listener)
2585{
1d8280c1
PB
2586 if (!listener->address_space) {
2587 return;
2588 }
2589
72e22d2f 2590 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2591 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2592 listener->address_space = NULL;
86e775c6 2593}
e2177955 2594
c9356746
FK
2595bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2596{
2597 void *host;
2598 unsigned size = 0;
2599 unsigned offset = 0;
2600 Object *new_interface;
2601
2602 if (!mr || !mr->ops->request_ptr) {
2603 return false;
2604 }
2605
2606 /*
2607 * Avoid an update if the request_ptr call
2608 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2609 * a cache.
2610 */
2611 memory_region_transaction_begin();
2612
2613 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2614
2615 if (!host || !size) {
2616 memory_region_transaction_commit();
2617 return false;
2618 }
2619
2620 new_interface = object_new("mmio_interface");
2621 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2622 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2623 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2624 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2625 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2626 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2627
2628 memory_region_transaction_commit();
2629 return true;
2630}
2631
2632typedef struct MMIOPtrInvalidate {
2633 MemoryRegion *mr;
2634 hwaddr offset;
2635 unsigned size;
2636 int busy;
2637 int allocated;
2638} MMIOPtrInvalidate;
2639
2640#define MAX_MMIO_INVALIDATE 10
2641static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2642
2643static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2644 run_on_cpu_data data)
2645{
2646 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2647 MemoryRegion *mr = invalidate_data->mr;
2648 hwaddr offset = invalidate_data->offset;
2649 unsigned size = invalidate_data->size;
2650 MemoryRegionSection section = memory_region_find(mr, offset, size);
2651
2652 qemu_mutex_lock_iothread();
2653
2654 /* Reset dirty so this doesn't happen later. */
2655 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2656
2657 if (section.mr != mr) {
2658 /* memory_region_find add a ref on section.mr */
2659 memory_region_unref(section.mr);
2660 if (MMIO_INTERFACE(section.mr->owner)) {
2661 /* We found the interface just drop it. */
2662 object_property_set_bool(section.mr->owner, false, "realized",
2663 NULL);
2664 object_unref(section.mr->owner);
2665 object_unparent(section.mr->owner);
2666 }
2667 }
2668
2669 qemu_mutex_unlock_iothread();
2670
2671 if (invalidate_data->allocated) {
2672 g_free(invalidate_data);
2673 } else {
2674 invalidate_data->busy = 0;
2675 }
2676}
2677
2678void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2679 unsigned size)
2680{
2681 size_t i;
2682 MMIOPtrInvalidate *invalidate_data = NULL;
2683
2684 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2685 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2686 invalidate_data = &mmio_ptr_invalidate_list[i];
2687 break;
2688 }
2689 }
2690
2691 if (!invalidate_data) {
2692 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2693 invalidate_data->allocated = 1;
2694 }
2695
2696 invalidate_data->mr = mr;
2697 invalidate_data->offset = offset;
2698 invalidate_data->size = size;
2699
2700 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2701 RUN_ON_CPU_HOST_PTR(invalidate_data));
2702}
2703
7dca8043 2704void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2705{
ac95190e 2706 memory_region_ref(root);
59023ef4 2707 memory_region_transaction_begin();
f0c02d15 2708 as->ref_count = 1;
8786db7c 2709 as->root = root;
f0c02d15 2710 as->malloced = false;
89c177bb 2711 as->current_map = flatview_new(root);
4c19eb72
AK
2712 as->ioeventfd_nb = 0;
2713 as->ioeventfds = NULL;
9a54635d 2714 QTAILQ_INIT(&as->listeners);
0d673e36 2715 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2716 as->name = g_strdup(name ? name : "anonymous");
f43793c7
PB
2717 memory_region_update_pending |= root->enabled;
2718 memory_region_transaction_commit();
1c0ffa58 2719}
658b2224 2720
374f2981 2721static void do_address_space_destroy(AddressSpace *as)
83f3c251 2722{
f0c02d15 2723 bool do_free = as->malloced;
078c44f4 2724
9a54635d 2725 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2726
856d7245 2727 flatview_unref(as->current_map);
7dca8043 2728 g_free(as->name);
4c19eb72 2729 g_free(as->ioeventfds);
ac95190e 2730 memory_region_unref(as->root);
f0c02d15
PC
2731 if (do_free) {
2732 g_free(as);
2733 }
2734}
2735
2736AddressSpace *address_space_init_shareable(MemoryRegion *root, const char *name)
2737{
2738 AddressSpace *as;
2739
f0c02d15
PC
2740 as = g_malloc0(sizeof *as);
2741 address_space_init(as, root, name);
2742 as->malloced = true;
2743 return as;
83f3c251
AK
2744}
2745
374f2981
PB
2746void address_space_destroy(AddressSpace *as)
2747{
ac95190e
PB
2748 MemoryRegion *root = as->root;
2749
f0c02d15
PC
2750 as->ref_count--;
2751 if (as->ref_count) {
2752 return;
2753 }
374f2981
PB
2754 /* Flush out anything from MemoryListeners listening in on this */
2755 memory_region_transaction_begin();
2756 as->root = NULL;
2757 memory_region_transaction_commit();
2758 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2759
2760 /* At this point, as->dispatch and as->current_map are dummy
2761 * entries that the guest should never use. Wait for the old
2762 * values to expire before freeing the data.
2763 */
ac95190e 2764 as->root = root;
374f2981
PB
2765 call_rcu(as, do_address_space_destroy, rcu);
2766}
2767
4e831901
PX
2768static const char *memory_region_type(MemoryRegion *mr)
2769{
2770 if (memory_region_is_ram_device(mr)) {
2771 return "ramd";
2772 } else if (memory_region_is_romd(mr)) {
2773 return "romd";
2774 } else if (memory_region_is_rom(mr)) {
2775 return "rom";
2776 } else if (memory_region_is_ram(mr)) {
2777 return "ram";
2778 } else {
2779 return "i/o";
2780 }
2781}
2782
314e2987
BS
2783typedef struct MemoryRegionList MemoryRegionList;
2784
2785struct MemoryRegionList {
2786 const MemoryRegion *mr;
a16878d2 2787 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS
2788};
2789
a16878d2 2790typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
314e2987 2791
4e831901
PX
2792#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2793 int128_sub((size), int128_one())) : 0)
2794#define MTREE_INDENT " "
2795
314e2987
BS
2796static void mtree_print_mr(fprintf_function mon_printf, void *f,
2797 const MemoryRegion *mr, unsigned int level,
a8170e5e 2798 hwaddr base,
9479c57a 2799 MemoryRegionListHead *alias_print_queue)
314e2987 2800{
9479c57a
JK
2801 MemoryRegionList *new_ml, *ml, *next_ml;
2802 MemoryRegionListHead submr_print_queue;
314e2987
BS
2803 const MemoryRegion *submr;
2804 unsigned int i;
b31f8412 2805 hwaddr cur_start, cur_end;
314e2987 2806
f8a9f720 2807 if (!mr) {
314e2987
BS
2808 return;
2809 }
2810
2811 for (i = 0; i < level; i++) {
4e831901 2812 mon_printf(f, MTREE_INDENT);
314e2987
BS
2813 }
2814
b31f8412
PX
2815 cur_start = base + mr->addr;
2816 cur_end = cur_start + MR_SIZE(mr->size);
2817
2818 /*
2819 * Try to detect overflow of memory region. This should never
2820 * happen normally. When it happens, we dump something to warn the
2821 * user who is observing this.
2822 */
2823 if (cur_start < base || cur_end < cur_start) {
2824 mon_printf(f, "[DETECTED OVERFLOW!] ");
2825 }
2826
314e2987
BS
2827 if (mr->alias) {
2828 MemoryRegionList *ml;
2829 bool found = false;
2830
2831 /* check if the alias is already in the queue */
a16878d2 2832 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2833 if (ml->mr == mr->alias) {
314e2987
BS
2834 found = true;
2835 }
2836 }
2837
2838 if (!found) {
2839 ml = g_new(MemoryRegionList, 1);
2840 ml->mr = mr->alias;
a16878d2 2841 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2842 }
4896d74b 2843 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
4e831901 2844 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
f8a9f720 2845 "-" TARGET_FMT_plx "%s\n",
b31f8412 2846 cur_start, cur_end,
4b474ba7 2847 mr->priority,
4e831901 2848 memory_region_type((MemoryRegion *)mr),
3fb18b4d
PC
2849 memory_region_name(mr),
2850 memory_region_name(mr->alias),
314e2987 2851 mr->alias_offset,
4e831901 2852 mr->alias_offset + MR_SIZE(mr->size),
f8a9f720 2853 mr->enabled ? "" : " [disabled]");
314e2987 2854 } else {
4896d74b 2855 mon_printf(f,
4e831901 2856 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
b31f8412 2857 cur_start, cur_end,
4b474ba7 2858 mr->priority,
4e831901 2859 memory_region_type((MemoryRegion *)mr),
f8a9f720
GH
2860 memory_region_name(mr),
2861 mr->enabled ? "" : " [disabled]");
314e2987 2862 }
9479c57a
JK
2863
2864 QTAILQ_INIT(&submr_print_queue);
2865
314e2987 2866 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
2867 new_ml = g_new(MemoryRegionList, 1);
2868 new_ml->mr = submr;
a16878d2 2869 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK
2870 if (new_ml->mr->addr < ml->mr->addr ||
2871 (new_ml->mr->addr == ml->mr->addr &&
2872 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 2873 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK
2874 new_ml = NULL;
2875 break;
2876 }
2877 }
2878 if (new_ml) {
a16878d2 2879 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK
2880 }
2881 }
2882
a16878d2 2883 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b31f8412 2884 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
9479c57a
JK
2885 alias_print_queue);
2886 }
2887
a16878d2 2888 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 2889 g_free(ml);
314e2987
BS
2890 }
2891}
2892
57bb40c9
PX
2893static void mtree_print_flatview(fprintf_function p, void *f,
2894 AddressSpace *as)
2895{
2896 FlatView *view = address_space_get_flatview(as);
2897 FlatRange *range = &view->ranges[0];
2898 MemoryRegion *mr;
2899 int n = view->nr;
2900
2901 if (n <= 0) {
2902 p(f, MTREE_INDENT "No rendered FlatView for "
2903 "address space '%s'\n", as->name);
2904 flatview_unref(view);
2905 return;
2906 }
2907
2908 while (n--) {
2909 mr = range->mr;
377a07aa
PB
2910 if (range->offset_in_region) {
2911 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2912 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
2913 int128_get64(range->addr.start),
2914 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2915 mr->priority,
2916 range->readonly ? "rom" : memory_region_type(mr),
2917 memory_region_name(mr),
2918 range->offset_in_region);
2919 } else {
2920 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2921 TARGET_FMT_plx " (prio %d, %s): %s\n",
2922 int128_get64(range->addr.start),
2923 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2924 mr->priority,
2925 range->readonly ? "rom" : memory_region_type(mr),
2926 memory_region_name(mr));
2927 }
57bb40c9
PX
2928 range++;
2929 }
2930
2931 flatview_unref(view);
2932}
2933
2934void mtree_info(fprintf_function mon_printf, void *f, bool flatview)
314e2987
BS
2935{
2936 MemoryRegionListHead ml_head;
2937 MemoryRegionList *ml, *ml2;
0d673e36 2938 AddressSpace *as;
314e2987 2939
57bb40c9
PX
2940 if (flatview) {
2941 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2942 mon_printf(f, "address-space (flat view): %s\n", as->name);
2943 mtree_print_flatview(mon_printf, f, as);
2944 mon_printf(f, "\n");
2945 }
2946 return;
2947 }
2948
314e2987
BS
2949 QTAILQ_INIT(&ml_head);
2950
0d673e36 2951 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
e48816aa
GH
2952 mon_printf(f, "address-space: %s\n", as->name);
2953 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
2954 mon_printf(f, "\n");
b9f9be88
BS
2955 }
2956
314e2987 2957 /* print aliased regions */
a16878d2 2958 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
e48816aa
GH
2959 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
2960 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
2961 mon_printf(f, "\n");
314e2987
BS
2962 }
2963
a16878d2 2964 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 2965 g_free(ml);
314e2987 2966 }
314e2987 2967}
b4fefef9 2968
b08199c6
PM
2969void memory_region_init_ram(MemoryRegion *mr,
2970 struct Object *owner,
2971 const char *name,
2972 uint64_t size,
2973 Error **errp)
2974{
2975 DeviceState *owner_dev;
2976 Error *err = NULL;
2977
2978 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
2979 if (err) {
2980 error_propagate(errp, err);
2981 return;
2982 }
2983 /* This will assert if owner is neither NULL nor a DeviceState.
2984 * We only want the owner here for the purposes of defining a
2985 * unique name for migration. TODO: Ideally we should implement
2986 * a naming scheme for Objects which are not DeviceStates, in
2987 * which case we can relax this restriction.
2988 */
2989 owner_dev = DEVICE(owner);
2990 vmstate_register_ram(mr, owner_dev);
2991}
2992
2993void memory_region_init_rom(MemoryRegion *mr,
2994 struct Object *owner,
2995 const char *name,
2996 uint64_t size,
2997 Error **errp)
2998{
2999 DeviceState *owner_dev;
3000 Error *err = NULL;
3001
3002 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3003 if (err) {
3004 error_propagate(errp, err);
3005 return;
3006 }
3007 /* This will assert if owner is neither NULL nor a DeviceState.
3008 * We only want the owner here for the purposes of defining a
3009 * unique name for migration. TODO: Ideally we should implement
3010 * a naming scheme for Objects which are not DeviceStates, in
3011 * which case we can relax this restriction.
3012 */
3013 owner_dev = DEVICE(owner);
3014 vmstate_register_ram(mr, owner_dev);
3015}
3016
3017void memory_region_init_rom_device(MemoryRegion *mr,
3018 struct Object *owner,
3019 const MemoryRegionOps *ops,
3020 void *opaque,
3021 const char *name,
3022 uint64_t size,
3023 Error **errp)
3024{
3025 DeviceState *owner_dev;
3026 Error *err = NULL;
3027
3028 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3029 name, size, &err);
3030 if (err) {
3031 error_propagate(errp, err);
3032 return;
3033 }
3034 /* This will assert if owner is neither NULL nor a DeviceState.
3035 * We only want the owner here for the purposes of defining a
3036 * unique name for migration. TODO: Ideally we should implement
3037 * a naming scheme for Objects which are not DeviceStates, in
3038 * which case we can relax this restriction.
3039 */
3040 owner_dev = DEVICE(owner);
3041 vmstate_register_ram(mr, owner_dev);
3042}
3043
b4fefef9
PC
3044static const TypeInfo memory_region_info = {
3045 .parent = TYPE_OBJECT,
3046 .name = TYPE_MEMORY_REGION,
3047 .instance_size = sizeof(MemoryRegion),
3048 .instance_init = memory_region_initfn,
3049 .instance_finalize = memory_region_finalize,
3050};
3051
3df9d748
AK
3052static const TypeInfo iommu_memory_region_info = {
3053 .parent = TYPE_MEMORY_REGION,
3054 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 3055 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK
3056 .instance_size = sizeof(IOMMUMemoryRegion),
3057 .instance_init = iommu_memory_region_initfn,
1221a474 3058 .abstract = true,
3df9d748
AK
3059};
3060
b4fefef9
PC
3061static void memory_register_types(void)
3062{
3063 type_register_static(&memory_region_info);
3df9d748 3064 type_register_static(&iommu_memory_region_info);
b4fefef9
PC
3065}
3066
3067type_init(memory_register_types)