]> git.proxmox.com Git - mirror_qemu.git/blame - memory.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
chardev: fix parallel device can't be reconnect
[mirror_qemu.git] / memory.c
CommitLineData
093bc2cd
AK		 1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB		 12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
AK		 14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879
PB		 18#include "qemu-common.h"
19#include "cpu.h"
022c62cb
PB		 20#include "exec/memory.h"
21#include "exec/address-spaces.h"
22#include "exec/ioport.h"
409ddd01 23#include "qapi/visitor.h"
1de7afc9 24#include "qemu/bitops.h"
8c56c1a5 25#include "qemu/error-report.h"
2c9b15ca 26#include "qom/object.h"
0ab8ed18 27#include "trace-root.h"
093bc2cd 28
022c62cb 29#include "exec/memory-internal.h"
220c3ebd 30#include "exec/ram_addr.h"
8c56c1a5 31#include "sysemu/kvm.h"
e1c57ab8 32#include "sysemu/sysemu.h"
c9356746
FK		 33#include "hw/misc/mmio_interface.h"
34#include "hw/qdev-properties.h"
67d95c15 35
d197063f
PB		 36//#define DEBUG_UNASSIGNED
37
22bde714
JK		 38static unsigned memory_region_transaction_depth;
39static bool memory_region_update_pending;
4dc56152 40static bool ioeventfd_update_pending;
7664e80c
AK		 41static bool global_dirty_log = false;
42
72e22d2f
AK		 43static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
44 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 45
0d673e36
AK		 46static QTAILQ_HEAD(, AddressSpace) address_spaces
47 = QTAILQ_HEAD_INITIALIZER(address_spaces);
48
093bc2cd
AK		 49typedef struct AddrRange AddrRange;
50
8417cebf 51/*
c9cdaa3a 52 * Note that signed integers are needed for negative offsetting in aliases
8417cebf
AK		 53 * (large MemoryRegion::alias_offset).
54 */
093bc2cd 55struct AddrRange {
08dafab4
AK		 56 Int128 start;
57 Int128 size;
093bc2cd
AK		 58};
59
08dafab4 60static AddrRange addrrange_make(Int128 start, Int128 size)
093bc2cd
AK		 61{
62 return (AddrRange) { start, size };
63}
64
65static bool addrrange_equal(AddrRange r1, AddrRange r2)
66{
08dafab4 67 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
093bc2cd
AK		 68}
69
08dafab4 70static Int128 addrrange_end(AddrRange r)
093bc2cd 71{
08dafab4 72 return int128_add(r.start, r.size);
093bc2cd
AK		 73}
74
08dafab4 75static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 76{
08dafab4 77 int128_addto(&range.start, delta);
093bc2cd
AK		 78 return range;
79}
80
08dafab4
AK		 81static bool addrrange_contains(AddrRange range, Int128 addr)
82{
83 return int128_ge(addr, range.start)
84 && int128_lt(addr, addrrange_end(range));
85}
86
093bc2cd
AK		 87static bool addrrange_intersects(AddrRange r1, AddrRange r2)
88{
08dafab4
AK		 89 return addrrange_contains(r1, r2.start)
90 || addrrange_contains(r2, r1.start);
093bc2cd
AK		 91}
92
93static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
94{
08dafab4
AK		 95 Int128 start = int128_max(r1.start, r2.start);
96 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
97 return addrrange_make(start, int128_sub(end, start));
093bc2cd
AK		 98}
99
0e0d36b4
AK		 100enum ListenerDirection { Forward, Reverse };
101
7376e582 102#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
AK		 103 do { \
104 MemoryListener *_listener; \
105 \
106 switch (_direction) { \
107 case Forward: \
108 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
AK		 109 if (_listener->_callback) { \
110 _listener->_callback(_listener, ##_args); \
111 } \
0e0d36b4
AK		 112 } \
113 break; \
114 case Reverse: \
115 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
116 memory_listeners, link) { \
975aefe0
AK		 117 if (_listener->_callback) { \
118 _listener->_callback(_listener, ##_args); \
119 } \
0e0d36b4
AK		 120 } \
121 break; \
122 default: \
123 abort(); \
124 } \
125 } while (0)
126
9a54635d 127#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
7376e582
AK		 128 do { \
129 MemoryListener *_listener; \
9a54635d 130 struct memory_listeners_as *list = &(_as)->listeners; \
7376e582
AK		 131 \
132 switch (_direction) { \
133 case Forward: \
9a54635d
PB		 134 QTAILQ_FOREACH(_listener, list, link_as) { \
135 if (_listener->_callback) { \
7376e582
AK		 136 _listener->_callback(_listener, _section, ##_args); \
137 } \
138 } \
139 break; \
140 case Reverse: \
9a54635d
PB		 141 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
142 link_as) { \
143 if (_listener->_callback) { \
7376e582
AK		 144 _listener->_callback(_listener, _section, ##_args); \
145 } \
146 } \
147 break; \
148 default: \
149 abort(); \
150 } \
151 } while (0)
152
dfde4e6e 153/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 154#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44
PB		 155 do { \
156 MemoryRegionSection mrs = section_from_flat_range(fr, as); \
9a54635d 157 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 158 } while(0)
0e0d36b4 159
093bc2cd
AK		 160struct CoalescedMemoryRange {
161 AddrRange addr;
162 QTAILQ_ENTRY(CoalescedMemoryRange) link;
163};
164
3e9d69e7
AK		 165struct MemoryRegionIoeventfd {
166 AddrRange addr;
167 bool match_data;
168 uint64_t data;
753d5e14 169 EventNotifier *e;
3e9d69e7
AK		 170};
171
172static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
173 MemoryRegionIoeventfd b)
174{
08dafab4 175 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 176 return true;
08dafab4 177 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 178 return false;
08dafab4 179 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 180 return true;
08dafab4 181 } else if (int128_gt(a.addr.size, b.addr.size)) {
3e9d69e7
AK		 182 return false;
183 } else if (a.match_data < b.match_data) {
184 return true;
185 } else if (a.match_data > b.match_data) {
186 return false;
187 } else if (a.match_data) {
188 if (a.data < b.data) {
189 return true;
190 } else if (a.data > b.data) {
191 return false;
192 }
193 }
753d5e14 194 if (a.e < b.e) {
3e9d69e7 195 return true;
753d5e14 196 } else if (a.e > b.e) {
3e9d69e7
AK		 197 return false;
198 }
199 return false;
200}
201
202static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
203 MemoryRegionIoeventfd b)
204{
205 return !memory_region_ioeventfd_before(a, b)
206 && !memory_region_ioeventfd_before(b, a);
207}
208
093bc2cd
AK		 209typedef struct FlatRange FlatRange;
210typedef struct FlatView FlatView;
211
212/* Range of memory in the global map. Addresses are absolute. */
213struct FlatRange {
214 MemoryRegion *mr;
a8170e5e 215 hwaddr offset_in_region;
093bc2cd 216 AddrRange addr;
5a583347 217 uint8_t dirty_log_mask;
b138e654 218 bool romd_mode;
fb1cd6f9 219 bool readonly;
093bc2cd
AK		 220};
221
222/* Flattened global view of current active memory hierarchy. Kept in sorted
223 * order.
224 */
225struct FlatView {
374f2981 226 struct rcu_head rcu;
856d7245 227 unsigned ref;
093bc2cd
AK		 228 FlatRange *ranges;
229 unsigned nr;
230 unsigned nr_allocated;
231};
232
cc31e6e7
AK		 233typedef struct AddressSpaceOps AddressSpaceOps;
234
093bc2cd
AK		 235#define FOR_EACH_FLAT_RANGE(var, view) \
236 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
237
9c1f8f44
PB		 238static inline MemoryRegionSection
239section_from_flat_range(FlatRange *fr, AddressSpace *as)
240{
241 return (MemoryRegionSection) {
242 .mr = fr->mr,
243 .address_space = as,
244 .offset_within_region = fr->offset_in_region,
245 .size = fr->addr.size,
246 .offset_within_address_space = int128_get64(fr->addr.start),
247 .readonly = fr->readonly,
248 };
249}
250
093bc2cd
AK		 251static bool flatrange_equal(FlatRange *a, FlatRange *b)
252{
253 return a->mr == b->mr
254 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 255 && a->offset_in_region == b->offset_in_region
b138e654 256 && a->romd_mode == b->romd_mode
fb1cd6f9 257 && a->readonly == b->readonly;
093bc2cd
AK		 258}
259
260static void flatview_init(FlatView *view)
261{
856d7245 262 view->ref = 1;
093bc2cd
AK		 263 view->ranges = NULL;
264 view->nr = 0;
265 view->nr_allocated = 0;
266}
267
268/* Insert a range into a given position. Caller is responsible for maintaining
269 * sorting order.
270 */
271static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
272{
273 if (view->nr == view->nr_allocated) {
274 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 275 view->ranges = g_realloc(view->ranges,
093bc2cd
AK		 276 view->nr_allocated * sizeof(*view->ranges));
277 }
278 memmove(view->ranges + pos + 1, view->ranges + pos,
279 (view->nr - pos) * sizeof(FlatRange));
280 view->ranges[pos] = *range;
dfde4e6e 281 memory_region_ref(range->mr);
093bc2cd
AK		 282 ++view->nr;
283}
284
285static void flatview_destroy(FlatView *view)
286{
dfde4e6e
PB		 287 int i;
288
289 for (i = 0; i < view->nr; i++) {
290 memory_region_unref(view->ranges[i].mr);
291 }
7267c094 292 g_free(view->ranges);
a9a0c06d 293 g_free(view);
093bc2cd
AK		 294}
295
856d7245
PB		 296static void flatview_ref(FlatView *view)
297{
298 atomic_inc(&view->ref);
299}
300
301static void flatview_unref(FlatView *view)
302{
303 if (atomic_fetch_dec(&view->ref) == 1) {
304 flatview_destroy(view);
305 }
306}
307
3d8e6bf9
AK		 308static bool can_merge(FlatRange *r1, FlatRange *r2)
309{
08dafab4 310 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 311 && r1->mr == r2->mr
08dafab4
AK		 312 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
313 r1->addr.size),
314 int128_make64(r2->offset_in_region))
d0a9b5bc 315 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 316 && r1->romd_mode == r2->romd_mode
fb1cd6f9 317 && r1->readonly == r2->readonly;
3d8e6bf9
AK		 318}
319
8508e024 320/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK		 321static void flatview_simplify(FlatView *view)
322{
323 unsigned i, j;
324
325 i = 0;
326 while (i < view->nr) {
327 j = i + 1;
328 while (j < view->nr
329 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 330 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
AK		 331 ++j;
332 }
333 ++i;
334 memmove(&view->ranges[i], &view->ranges[j],
335 (view->nr - j) * sizeof(view->ranges[j]));
336 view->nr -= j - i;
337 }
338}
339
e7342aa3
PB		 340static bool memory_region_big_endian(MemoryRegion *mr)
341{
342#ifdef TARGET_WORDS_BIGENDIAN
343 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
344#else
345 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
346#endif
347}
348
e11ef3d1
PB		 349static bool memory_region_wrong_endianness(MemoryRegion *mr)
350{
351#ifdef TARGET_WORDS_BIGENDIAN
352 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
353#else
354 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
355#endif
356}
357
358static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
359{
360 if (memory_region_wrong_endianness(mr)) {
361 switch (size) {
362 case 1:
363 break;
364 case 2:
365 *data = bswap16(*data);
366 break;
367 case 4:
368 *data = bswap32(*data);
369 break;
370 case 8:
371 *data = bswap64(*data);
372 break;
373 default:
374 abort();
375 }
376 }
377}
378
4779dc1d
HB		 379static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
380{
381 MemoryRegion *root;
382 hwaddr abs_addr = offset;
383
384 abs_addr += mr->addr;
385 for (root = mr; root->container; ) {
386 root = root->container;
387 abs_addr += root->addr;
388 }
389
390 return abs_addr;
391}
392
5a68be94
HB		 393static int get_cpu_index(void)
394{
395 if (current_cpu) {
396 return current_cpu->cpu_index;
397 }
398 return -1;
399}
400
cc05c43a
PM		 401static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
402 hwaddr addr,
403 uint64_t *value,
404 unsigned size,
405 unsigned shift,
406 uint64_t mask,
407 MemTxAttrs attrs)
408{
409 uint64_t tmp;
410
411 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
23d92d68 412 if (mr->subpage) {
5a68be94 413 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 414 } else if (mr == &io_mem_notdirty) {
415 /* Accesses to code which has previously been translated into a TB show
416 * up in the MMIO path, as accesses to the io_mem_notdirty
417 * MemoryRegion. */
418 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 419 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
420 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 421 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 422 }
cc05c43a
PM		 423 *value |= (tmp & mask) << shift;
424 return MEMTX_OK;
425}
426
427static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB		 428 hwaddr addr,
429 uint64_t *value,
430 unsigned size,
431 unsigned shift,
cc05c43a
PM		 432 uint64_t mask,
433 MemTxAttrs attrs)
ce5d2f33 434{
ce5d2f33
PB		 435 uint64_t tmp;
436
cc05c43a 437 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 438 if (mr->subpage) {
5a68be94 439 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 440 } else if (mr == &io_mem_notdirty) {
441 /* Accesses to code which has previously been translated into a TB show
442 * up in the MMIO path, as accesses to the io_mem_notdirty
443 * MemoryRegion. */
444 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 445 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
446 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 447 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 448 }
ce5d2f33 449 *value |= (tmp & mask) << shift;
cc05c43a 450 return MEMTX_OK;
ce5d2f33
PB		 451}
452
cc05c43a
PM		 453static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
454 hwaddr addr,
455 uint64_t *value,
456 unsigned size,
457 unsigned shift,
458 uint64_t mask,
459 MemTxAttrs attrs)
164a4dcd 460{
cc05c43a
PM		 461 uint64_t tmp = 0;
462 MemTxResult r;
164a4dcd 463
cc05c43a 464 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 465 if (mr->subpage) {
5a68be94 466 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 467 } else if (mr == &io_mem_notdirty) {
468 /* Accesses to code which has previously been translated into a TB show
469 * up in the MMIO path, as accesses to the io_mem_notdirty
470 * MemoryRegion. */
471 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 472 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
473 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 474 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 475 }
164a4dcd 476 *value |= (tmp & mask) << shift;
cc05c43a 477 return r;
164a4dcd
AK		 478}
479
cc05c43a
PM		 480static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
481 hwaddr addr,
482 uint64_t *value,
483 unsigned size,
484 unsigned shift,
485 uint64_t mask,
486 MemTxAttrs attrs)
ce5d2f33 487{
ce5d2f33
PB		 488 uint64_t tmp;
489
490 tmp = (*value >> shift) & mask;
23d92d68 491 if (mr->subpage) {
5a68be94 492 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 493 } else if (mr == &io_mem_notdirty) {
494 /* Accesses to code which has previously been translated into a TB show
495 * up in the MMIO path, as accesses to the io_mem_notdirty
496 * MemoryRegion. */
497 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 498 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
499 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 500 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 501 }
ce5d2f33 502 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
cc05c43a 503 return MEMTX_OK;
ce5d2f33
PB		 504}
505
cc05c43a
PM		 506static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
507 hwaddr addr,
508 uint64_t *value,
509 unsigned size,
510 unsigned shift,
511 uint64_t mask,
512 MemTxAttrs attrs)
164a4dcd 513{
164a4dcd
AK		 514 uint64_t tmp;
515
516 tmp = (*value >> shift) & mask;
23d92d68 517 if (mr->subpage) {
5a68be94 518 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 519 } else if (mr == &io_mem_notdirty) {
520 /* Accesses to code which has previously been translated into a TB show
521 * up in the MMIO path, as accesses to the io_mem_notdirty
522 * MemoryRegion. */
523 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 524 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
525 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 526 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 527 }
164a4dcd 528 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 529 return MEMTX_OK;
164a4dcd
AK		 530}
531
cc05c43a
PM		 532static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
533 hwaddr addr,
534 uint64_t *value,
535 unsigned size,
536 unsigned shift,
537 uint64_t mask,
538 MemTxAttrs attrs)
539{
540 uint64_t tmp;
541
cc05c43a 542 tmp = (*value >> shift) & mask;
23d92d68 543 if (mr->subpage) {
5a68be94 544 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 545 } else if (mr == &io_mem_notdirty) {
546 /* Accesses to code which has previously been translated into a TB show
547 * up in the MMIO path, as accesses to the io_mem_notdirty
548 * MemoryRegion. */
549 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 550 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
551 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 552 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 553 }
cc05c43a
PM		 554 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
555}
556
557static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK		 558 uint64_t *value,
559 unsigned size,
560 unsigned access_size_min,
561 unsigned access_size_max,
cc05c43a
PM		 562 MemTxResult (*access)(MemoryRegion *mr,
563 hwaddr addr,
564 uint64_t *value,
565 unsigned size,
566 unsigned shift,
567 uint64_t mask,
568 MemTxAttrs attrs),
569 MemoryRegion *mr,
570 MemTxAttrs attrs)
164a4dcd
AK		 571{
572 uint64_t access_mask;
573 unsigned access_size;
574 unsigned i;
cc05c43a 575 MemTxResult r = MEMTX_OK;
164a4dcd
AK		 576
577 if (!access_size_min) {
578 access_size_min = 1;
579 }
580 if (!access_size_max) {
581 access_size_max = 4;
582 }
ce5d2f33
PB		 583
584 /* FIXME: support unaligned access? */
164a4dcd
AK		 585 access_size = MAX(MIN(size, access_size_max), access_size_min);
586 access_mask = -1ULL >> (64 - access_size * 8);
e7342aa3
PB		 587 if (memory_region_big_endian(mr)) {
588 for (i = 0; i < size; i += access_size) {
cc05c43a
PM		 589 r |= access(mr, addr + i, value, access_size,
590 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB		 591 }
592 } else {
593 for (i = 0; i < size; i += access_size) {
cc05c43a
PM		 594 r |= access(mr, addr + i, value, access_size, i * 8,
595 access_mask, attrs);
e7342aa3 596 }
164a4dcd 597 }
cc05c43a 598 return r;
164a4dcd
AK		 599}
600
e2177955
AK		 601static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
602{
0d673e36
AK		 603 AddressSpace *as;
604
feca4ac1
PB		 605 while (mr->container) {
606 mr = mr->container;
e2177955 607 }
0d673e36
AK		 608 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
609 if (mr == as->root) {
610 return as;
611 }
e2177955 612 }
eed2bacf 613 return NULL;
e2177955
AK		 614}
615
093bc2cd
AK		 616/* Render a memory region into the global view. Ranges in @view obscure
617 * ranges in @mr.
618 */
619static void render_memory_region(FlatView *view,
620 MemoryRegion *mr,
08dafab4 621 Int128 base,
fb1cd6f9
AK		 622 AddrRange clip,
623 bool readonly)
093bc2cd
AK		 624{
625 MemoryRegion *subregion;
626 unsigned i;
a8170e5e 627 hwaddr offset_in_region;
08dafab4
AK		 628 Int128 remain;
629 Int128 now;
093bc2cd
AK		 630 FlatRange fr;
631 AddrRange tmp;
632
6bba19ba
AK		 633 if (!mr->enabled) {
634 return;
635 }
636
08dafab4 637 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 638 readonly |= mr->readonly;
093bc2cd
AK		 639
640 tmp = addrrange_make(base, mr->size);
641
642 if (!addrrange_intersects(tmp, clip)) {
643 return;
644 }
645
646 clip = addrrange_intersection(tmp, clip);
647
648 if (mr->alias) {
08dafab4
AK		 649 int128_subfrom(&base, int128_make64(mr->alias->addr));
650 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 651 render_memory_region(view, mr->alias, base, clip, readonly);
093bc2cd
AK		 652 return;
653 }
654
655 /* Render subregions in priority order. */
656 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 657 render_memory_region(view, subregion, base, clip, readonly);
093bc2cd
AK		 658 }
659
14a3c10a 660 if (!mr->terminates) {
093bc2cd
AK		 661 return;
662 }
663
08dafab4 664 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK		 665 base = clip.start;
666 remain = clip.size;
667
2eb74e1a 668 fr.mr = mr;
6f6a5ef3 669 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 670 fr.romd_mode = mr->romd_mode;
2eb74e1a
PC		 671 fr.readonly = readonly;
672
093bc2cd 673 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK		 674 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
675 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK		 676 continue;
677 }
08dafab4
AK		 678 if (int128_lt(base, view->ranges[i].addr.start)) {
679 now = int128_min(remain,
680 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK		 681 fr.offset_in_region = offset_in_region;
682 fr.addr = addrrange_make(base, now);
683 flatview_insert(view, i, &fr);
684 ++i;
08dafab4
AK		 685 int128_addto(&base, now);
686 offset_in_region += int128_get64(now);
687 int128_subfrom(&remain, now);
093bc2cd 688 }
d26a8cae
AK		 689 now = int128_sub(int128_min(int128_add(base, remain),
690 addrrange_end(view->ranges[i].addr)),
691 base);
692 int128_addto(&base, now);
693 offset_in_region += int128_get64(now);
694 int128_subfrom(&remain, now);
093bc2cd 695 }
08dafab4 696 if (int128_nz(remain)) {
093bc2cd
AK		 697 fr.offset_in_region = offset_in_region;
698 fr.addr = addrrange_make(base, remain);
699 flatview_insert(view, i, &fr);
700 }
701}
702
703/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 704static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 705{
a9a0c06d 706 FlatView *view;
093bc2cd 707
a9a0c06d
PB		 708 view = g_new(FlatView, 1);
709 flatview_init(view);
093bc2cd 710
83f3c251 711 if (mr) {
a9a0c06d 712 render_memory_region(view, mr, int128_zero(),
83f3c251
AK		 713 addrrange_make(int128_zero(), int128_2_64()), false);
714 }
a9a0c06d 715 flatview_simplify(view);
093bc2cd
AK		 716
717 return view;
718}
719
3e9d69e7
AK		 720static void address_space_add_del_ioeventfds(AddressSpace *as,
721 MemoryRegionIoeventfd *fds_new,
722 unsigned fds_new_nb,
723 MemoryRegionIoeventfd *fds_old,
724 unsigned fds_old_nb)
725{
726 unsigned iold, inew;
80a1ea37
AK		 727 MemoryRegionIoeventfd *fd;
728 MemoryRegionSection section;
3e9d69e7
AK		 729
730 /* Generate a symmetric difference of the old and new fd sets, adding
731 * and deleting as necessary.
732 */
733
734 iold = inew = 0;
735 while (iold < fds_old_nb || inew < fds_new_nb) {
736 if (iold < fds_old_nb
737 && (inew == fds_new_nb
738 || memory_region_ioeventfd_before(fds_old[iold],
739 fds_new[inew]))) {
80a1ea37
AK		 740 fd = &fds_old[iold];
741 section = (MemoryRegionSection) {
f6790af6 742 .address_space = as,
80a1ea37 743 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 744 .size = fd->addr.size,
80a1ea37 745 };
9a54635d 746 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 747 fd->match_data, fd->data, fd->e);
3e9d69e7
AK		 748 ++iold;
749 } else if (inew < fds_new_nb
750 && (iold == fds_old_nb
751 || memory_region_ioeventfd_before(fds_new[inew],
752 fds_old[iold]))) {
80a1ea37
AK		 753 fd = &fds_new[inew];
754 section = (MemoryRegionSection) {
f6790af6 755 .address_space = as,
80a1ea37 756 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 757 .size = fd->addr.size,
80a1ea37 758 };
9a54635d 759 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 760 fd->match_data, fd->data, fd->e);
3e9d69e7
AK		 761 ++inew;
762 } else {
763 ++iold;
764 ++inew;
765 }
766 }
767}
768
856d7245
PB		 769static FlatView *address_space_get_flatview(AddressSpace *as)
770{
771 FlatView *view;
772
374f2981
PB		 773 rcu_read_lock();
774 view = atomic_rcu_read(&as->current_map);
856d7245 775 flatview_ref(view);
374f2981 776 rcu_read_unlock();
856d7245
PB		 777 return view;
778}
779
3e9d69e7
AK		 780static void address_space_update_ioeventfds(AddressSpace *as)
781{
99e86347 782 FlatView *view;
3e9d69e7
AK		 783 FlatRange *fr;
784 unsigned ioeventfd_nb = 0;
785 MemoryRegionIoeventfd *ioeventfds = NULL;
786 AddrRange tmp;
787 unsigned i;
788
856d7245 789 view = address_space_get_flatview(as);
99e86347 790 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK		 791 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
792 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK		 793 int128_sub(fr->addr.start,
794 int128_make64(fr->offset_in_region)));
3e9d69e7
AK		 795 if (addrrange_intersects(fr->addr, tmp)) {
796 ++ioeventfd_nb;
7267c094 797 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK		 798 ioeventfd_nb * sizeof(*ioeventfds));
799 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
800 ioeventfds[ioeventfd_nb-1].addr = tmp;
801 }
802 }
803 }
804
805 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
806 as->ioeventfds, as->ioeventfd_nb);
807
7267c094 808 g_free(as->ioeventfds);
3e9d69e7
AK		 809 as->ioeventfds = ioeventfds;
810 as->ioeventfd_nb = ioeventfd_nb;
856d7245 811 flatview_unref(view);
3e9d69e7
AK		 812}
813
b8af1afb 814static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB		 815 const FlatView *old_view,
816 const FlatView *new_view,
b8af1afb 817 bool adding)
093bc2cd 818{
093bc2cd
AK		 819 unsigned iold, inew;
820 FlatRange *frold, *frnew;
093bc2cd
AK		 821
822 /* Generate a symmetric difference of the old and new memory maps.
823 * Kill ranges in the old map, and instantiate ranges in the new map.
824 */
825 iold = inew = 0;
a9a0c06d
PB		 826 while (iold < old_view->nr || inew < new_view->nr) {
827 if (iold < old_view->nr) {
828 frold = &old_view->ranges[iold];
093bc2cd
AK		 829 } else {
830 frold = NULL;
831 }
a9a0c06d
PB		 832 if (inew < new_view->nr) {
833 frnew = &new_view->ranges[inew];
093bc2cd
AK		 834 } else {
835 frnew = NULL;
836 }
837
838 if (frold
839 && (!frnew
08dafab4
AK		 840 || int128_lt(frold->addr.start, frnew->addr.start)
841 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 842 && !flatrange_equal(frold, frnew)))) {
41a6e477 843 /* In old but not in new, or in both but attributes changed. */
093bc2cd 844
b8af1afb 845 if (!adding) {
72e22d2f 846 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK		 847 }
848
093bc2cd
AK		 849 ++iold;
850 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 851 /* In both and unchanged (except logging may have changed) */
093bc2cd 852
b8af1afb 853 if (adding) {
50c1e149 854 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB		 855 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
856 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
857 frold->dirty_log_mask,
858 frnew->dirty_log_mask);
859 }
860 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
861 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
862 frold->dirty_log_mask,
863 frnew->dirty_log_mask);
b8af1afb 864 }
5a583347
AK		 865 }
866
093bc2cd
AK		 867 ++iold;
868 ++inew;
093bc2cd
AK		 869 } else {
870 /* In new */
871
b8af1afb 872 if (adding) {
72e22d2f 873 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK		 874 }
875
093bc2cd
AK		 876 ++inew;
877 }
878 }
b8af1afb
AK		 879}
880
881
882static void address_space_update_topology(AddressSpace *as)
883{
856d7245 884 FlatView *old_view = address_space_get_flatview(as);
a9a0c06d 885 FlatView *new_view = generate_memory_topology(as->root);
b8af1afb
AK		 886
887 address_space_update_topology_pass(as, old_view, new_view, false);
888 address_space_update_topology_pass(as, old_view, new_view, true);
889
374f2981
PB		 890 /* Writes are protected by the BQL. */
891 atomic_rcu_set(&as->current_map, new_view);
892 call_rcu(old_view, flatview_unref, rcu);
856d7245
PB		 893
894 /* Note that all the old MemoryRegions are still alive up to this
895 * point. This relieves most MemoryListeners from the need to
896 * ref/unref the MemoryRegions they get---unless they use them
897 * outside the iothread mutex, in which case precise reference
898 * counting is necessary.
899 */
900 flatview_unref(old_view);
901
3e9d69e7 902 address_space_update_ioeventfds(as);
093bc2cd
AK		 903}
904
4ef4db86
AK		 905void memory_region_transaction_begin(void)
906{
bb880ded 907 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK		 908 ++memory_region_transaction_depth;
909}
910
911void memory_region_transaction_commit(void)
912{
0d673e36
AK		 913 AddressSpace *as;
914
4ef4db86 915 assert(memory_region_transaction_depth);
8d04fb55
JK		 916 assert(qemu_mutex_iothread_locked());
917
4ef4db86 918 --memory_region_transaction_depth;
4dc56152
GA		 919 if (!memory_region_transaction_depth) {
920 if (memory_region_update_pending) {
921 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 922
4dc56152
GA		 923 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
924 address_space_update_topology(as);
925 }
ade9c1aa 926 memory_region_update_pending = false;
4dc56152
GA		 927 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
928 } else if (ioeventfd_update_pending) {
929 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
930 address_space_update_ioeventfds(as);
931 }
ade9c1aa 932 ioeventfd_update_pending = false;
4dc56152 933 }
4dc56152 934 }
4ef4db86
AK		 935}
936
545e92e0
AK		 937static void memory_region_destructor_none(MemoryRegion *mr)
938{
939}
940
941static void memory_region_destructor_ram(MemoryRegion *mr)
942{
f1060c55 943 qemu_ram_free(mr->ram_block);
545e92e0
AK		 944}
945
b4fefef9
PC		 946static bool memory_region_need_escape(char c)
947{
948 return c == '/' || c == '[' || c == '\\' || c == ']';
949}
950
951static char *memory_region_escape_name(const char *name)
952{
953 const char *p;
954 char *escaped, *q;
955 uint8_t c;
956 size_t bytes = 0;
957
958 for (p = name; *p; p++) {
959 bytes += memory_region_need_escape(*p) ? 4 : 1;
960 }
961 if (bytes == p - name) {
962 return g_memdup(name, bytes + 1);
963 }
964
965 escaped = g_malloc(bytes + 1);
966 for (p = name, q = escaped; *p; p++) {
967 c = *p;
968 if (unlikely(memory_region_need_escape(c))) {
969 *q++ = '\\';
970 *q++ = 'x';
971 *q++ = "0123456789abcdef"[c >> 4];
972 c = "0123456789abcdef"[c & 15];
973 }
974 *q++ = c;
975 }
976 *q = 0;
977 return escaped;
978}
979
093bc2cd 980void memory_region_init(MemoryRegion *mr,
2c9b15ca 981 Object *owner,
093bc2cd
AK		 982 const char *name,
983 uint64_t size)
984{
22a893e4 985 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
08dafab4
AK		 986 mr->size = int128_make64(size);
987 if (size == UINT64_MAX) {
988 mr->size = int128_2_64();
989 }
302fa283 990 mr->name = g_strdup(name);
612263cf 991 mr->owner = owner;
58eaa217 992 mr->ram_block = NULL;
b4fefef9
PC		 993
994 if (name) {
843ef73a
PC		 995 char *escaped_name = memory_region_escape_name(name);
996 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB		 997
998 if (!owner) {
999 owner = container_get(qdev_get_machine(), "/unattached");
1000 }
1001
843ef73a 1002 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1003 object_unref(OBJECT(mr));
843ef73a
PC		 1004 g_free(name_array);
1005 g_free(escaped_name);
b4fefef9
PC		 1006 }
1007}
1008
d7bce999
EB		 1009static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1010 void *opaque, Error **errp)
409ddd01
PC		 1011{
1012 MemoryRegion *mr = MEMORY_REGION(obj);
1013 uint64_t value = mr->addr;
1014
51e72bc1 1015 visit_type_uint64(v, name, &value, errp);
409ddd01
PC		 1016}
1017
d7bce999
EB		 1018static void memory_region_get_container(Object *obj, Visitor *v,
1019 const char *name, void *opaque,
1020 Error **errp)
409ddd01
PC		 1021{
1022 MemoryRegion *mr = MEMORY_REGION(obj);
1023 gchar *path = (gchar *)"";
1024
1025 if (mr->container) {
1026 path = object_get_canonical_path(OBJECT(mr->container));
1027 }
51e72bc1 1028 visit_type_str(v, name, &path, errp);
409ddd01
PC		 1029 if (mr->container) {
1030 g_free(path);
1031 }
1032}
1033
1034static Object *memory_region_resolve_container(Object *obj, void *opaque,
1035 const char *part)
1036{
1037 MemoryRegion *mr = MEMORY_REGION(obj);
1038
1039 return OBJECT(mr->container);
1040}
1041
d7bce999
EB		 1042static void memory_region_get_priority(Object *obj, Visitor *v,
1043 const char *name, void *opaque,
1044 Error **errp)
d33382da
PC		 1045{
1046 MemoryRegion *mr = MEMORY_REGION(obj);
1047 int32_t value = mr->priority;
1048
51e72bc1 1049 visit_type_int32(v, name, &value, errp);
d33382da
PC		 1050}
1051
d7bce999
EB		 1052static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1053 void *opaque, Error **errp)
52aef7bb
PC		 1054{
1055 MemoryRegion *mr = MEMORY_REGION(obj);
1056 uint64_t value = memory_region_size(mr);
1057
51e72bc1 1058 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC		 1059}
1060
b4fefef9
PC		 1061static void memory_region_initfn(Object *obj)
1062{
1063 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1064 ObjectProperty *op;
b4fefef9
PC		 1065
1066 mr->ops = &unassigned_mem_ops;
6bba19ba 1067 mr->enabled = true;
5f9a5ea1 1068 mr->romd_mode = true;
196ea131 1069 mr->global_locking = true;
545e92e0 1070 mr->destructor = memory_region_destructor_none;
093bc2cd 1071 QTAILQ_INIT(&mr->subregions);
093bc2cd 1072 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC		 1073
1074 op = object_property_add(OBJECT(mr), "container",
1075 "link<" TYPE_MEMORY_REGION ">",
1076 memory_region_get_container,
1077 NULL, /* memory_region_set_container */
1078 NULL, NULL, &error_abort);
1079 op->resolve = memory_region_resolve_container;
1080
1081 object_property_add(OBJECT(mr), "addr", "uint64",
1082 memory_region_get_addr,
1083 NULL, /* memory_region_set_addr */
1084 NULL, NULL, &error_abort);
d33382da
PC		 1085 object_property_add(OBJECT(mr), "priority", "uint32",
1086 memory_region_get_priority,
1087 NULL, /* memory_region_set_priority */
1088 NULL, NULL, &error_abort);
52aef7bb
PC		 1089 object_property_add(OBJECT(mr), "size", "uint64",
1090 memory_region_get_size,
1091 NULL, /* memory_region_set_size, */
1092 NULL, NULL, &error_abort);
093bc2cd
AK		 1093}
1094
b018ddf6
PB		 1095static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1096 unsigned size)
1097{
1098#ifdef DEBUG_UNASSIGNED
1099 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1100#endif
4917cf44
AF		 1101 if (current_cpu != NULL) {
1102 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
c658b94f 1103 }
68a7439a 1104 return 0;
b018ddf6
PB		 1105}
1106
1107static void unassigned_mem_write(void *opaque, hwaddr addr,
1108 uint64_t val, unsigned size)
1109{
1110#ifdef DEBUG_UNASSIGNED
1111 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1112#endif
4917cf44
AF		 1113 if (current_cpu != NULL) {
1114 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1115 }
b018ddf6
PB		 1116}
1117
d197063f
PB		 1118static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1119 unsigned size, bool is_write)
1120{
1121 return false;
1122}
1123
1124const MemoryRegionOps unassigned_mem_ops = {
1125 .valid.accepts = unassigned_mem_accepts,
1126 .endianness = DEVICE_NATIVE_ENDIAN,
1127};
1128
4a2e242b
AW		 1129static uint64_t memory_region_ram_device_read(void *opaque,
1130 hwaddr addr, unsigned size)
1131{
1132 MemoryRegion *mr = opaque;
1133 uint64_t data = (uint64_t)~0;
1134
1135 switch (size) {
1136 case 1:
1137 data = *(uint8_t *)(mr->ram_block->host + addr);
1138 break;
1139 case 2:
1140 data = *(uint16_t *)(mr->ram_block->host + addr);
1141 break;
1142 case 4:
1143 data = *(uint32_t *)(mr->ram_block->host + addr);
1144 break;
1145 case 8:
1146 data = *(uint64_t *)(mr->ram_block->host + addr);
1147 break;
1148 }
1149
1150 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1151
1152 return data;
1153}
1154
1155static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1156 uint64_t data, unsigned size)
1157{
1158 MemoryRegion *mr = opaque;
1159
1160 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1161
1162 switch (size) {
1163 case 1:
1164 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1165 break;
1166 case 2:
1167 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1168 break;
1169 case 4:
1170 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1171 break;
1172 case 8:
1173 *(uint64_t *)(mr->ram_block->host + addr) = data;
1174 break;
1175 }
1176}
1177
1178static const MemoryRegionOps ram_device_mem_ops = {
1179 .read = memory_region_ram_device_read,
1180 .write = memory_region_ram_device_write,
c99a29e7 1181 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW		 1182 .valid = {
1183 .min_access_size = 1,
1184 .max_access_size = 8,
1185 .unaligned = true,
1186 },
1187 .impl = {
1188 .min_access_size = 1,
1189 .max_access_size = 8,
1190 .unaligned = true,
1191 },
1192};
1193
d2702032
PB		 1194bool memory_region_access_valid(MemoryRegion *mr,
1195 hwaddr addr,
1196 unsigned size,
1197 bool is_write)
093bc2cd 1198{
a014ed07
PB		 1199 int access_size_min, access_size_max;
1200 int access_size, i;
897fa7cf 1201
093bc2cd
AK		 1202 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1203 return false;
1204 }
1205
a014ed07 1206 if (!mr->ops->valid.accepts) {
093bc2cd
AK		 1207 return true;
1208 }
1209
a014ed07
PB		 1210 access_size_min = mr->ops->valid.min_access_size;
1211 if (!mr->ops->valid.min_access_size) {
1212 access_size_min = 1;
1213 }
1214
1215 access_size_max = mr->ops->valid.max_access_size;
1216 if (!mr->ops->valid.max_access_size) {
1217 access_size_max = 4;
1218 }
1219
1220 access_size = MAX(MIN(size, access_size_max), access_size_min);
1221 for (i = 0; i < size; i += access_size) {
1222 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1223 is_write)) {
1224 return false;
1225 }
093bc2cd 1226 }
a014ed07 1227
093bc2cd
AK		 1228 return true;
1229}
1230
cc05c43a
PM		 1231static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1232 hwaddr addr,
1233 uint64_t *pval,
1234 unsigned size,
1235 MemTxAttrs attrs)
093bc2cd 1236{
cc05c43a 1237 *pval = 0;
093bc2cd 1238
ce5d2f33 1239 if (mr->ops->read) {
cc05c43a
PM		 1240 return access_with_adjusted_size(addr, pval, size,
1241 mr->ops->impl.min_access_size,
1242 mr->ops->impl.max_access_size,
1243 memory_region_read_accessor,
1244 mr, attrs);
1245 } else if (mr->ops->read_with_attrs) {
1246 return access_with_adjusted_size(addr, pval, size,
1247 mr->ops->impl.min_access_size,
1248 mr->ops->impl.max_access_size,
1249 memory_region_read_with_attrs_accessor,
1250 mr, attrs);
ce5d2f33 1251 } else {
cc05c43a
PM		 1252 return access_with_adjusted_size(addr, pval, size, 1, 4,
1253 memory_region_oldmmio_read_accessor,
1254 mr, attrs);
74901c3b 1255 }
093bc2cd
AK		 1256}
1257
3b643495
PM		 1258MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1259 hwaddr addr,
1260 uint64_t *pval,
1261 unsigned size,
1262 MemTxAttrs attrs)
a621f38d 1263{
cc05c43a
PM		 1264 MemTxResult r;
1265
791af8c8
PB		 1266 if (!memory_region_access_valid(mr, addr, size, false)) {
1267 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1268 return MEMTX_DECODE_ERROR;
791af8c8 1269 }
a621f38d 1270
cc05c43a 1271 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1272 adjust_endianness(mr, pval, size);
cc05c43a 1273 return r;
a621f38d 1274}
093bc2cd 1275
8c56c1a5
PF		 1276/* Return true if an eventfd was signalled */
1277static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1278 hwaddr addr,
1279 uint64_t data,
1280 unsigned size,
1281 MemTxAttrs attrs)
1282{
1283 MemoryRegionIoeventfd ioeventfd = {
1284 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1285 .data = data,
1286 };
1287 unsigned i;
1288
1289 for (i = 0; i < mr->ioeventfd_nb; i++) {
1290 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1291 ioeventfd.e = mr->ioeventfds[i].e;
1292
1293 if (memory_region_ioeventfd_equal(ioeventfd, mr->ioeventfds[i])) {
1294 event_notifier_set(ioeventfd.e);
1295 return true;
1296 }
1297 }
1298
1299 return false;
1300}
1301
3b643495
PM		 1302MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1303 hwaddr addr,
1304 uint64_t data,
1305 unsigned size,
1306 MemTxAttrs attrs)
a621f38d 1307{
897fa7cf 1308 if (!memory_region_access_valid(mr, addr, size, true)) {
b018ddf6 1309 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1310 return MEMTX_DECODE_ERROR;
093bc2cd
AK		 1311 }
1312
a621f38d
AK		 1313 adjust_endianness(mr, &data, size);
1314
8c56c1a5
PF		 1315 if ((!kvm_eventfds_enabled()) &&
1316 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1317 return MEMTX_OK;
1318 }
1319
ce5d2f33 1320 if (mr->ops->write) {
cc05c43a
PM		 1321 return access_with_adjusted_size(addr, &data, size,
1322 mr->ops->impl.min_access_size,
1323 mr->ops->impl.max_access_size,
1324 memory_region_write_accessor, mr,
1325 attrs);
1326 } else if (mr->ops->write_with_attrs) {
1327 return
1328 access_with_adjusted_size(addr, &data, size,
1329 mr->ops->impl.min_access_size,
1330 mr->ops->impl.max_access_size,
1331 memory_region_write_with_attrs_accessor,
1332 mr, attrs);
ce5d2f33 1333 } else {
cc05c43a
PM		 1334 return access_with_adjusted_size(addr, &data, size, 1, 4,
1335 memory_region_oldmmio_write_accessor,
1336 mr, attrs);
74901c3b 1337 }
093bc2cd
AK		 1338}
1339
093bc2cd 1340void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1341 Object *owner,
093bc2cd
AK		 1342 const MemoryRegionOps *ops,
1343 void *opaque,
1344 const char *name,
1345 uint64_t size)
1346{
2c9b15ca 1347 memory_region_init(mr, owner, name, size);
6d6d2abf 1348 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1349 mr->opaque = opaque;
14a3c10a 1350 mr->terminates = true;
093bc2cd
AK		 1351}
1352
1353void memory_region_init_ram(MemoryRegion *mr,
2c9b15ca 1354 Object *owner,
093bc2cd 1355 const char *name,
49946538
HT		 1356 uint64_t size,
1357 Error **errp)
093bc2cd 1358{
2c9b15ca 1359 memory_region_init(mr, owner, name, size);
8ea9252a 1360 mr->ram = true;
14a3c10a 1361 mr->terminates = true;
545e92e0 1362 mr->destructor = memory_region_destructor_ram;
8e41fb63 1363 mr->ram_block = qemu_ram_alloc(size, mr, errp);
677e7805 1364 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
0b183fc8
PB		 1365}
1366
60786ef3
MT		 1367void memory_region_init_resizeable_ram(MemoryRegion *mr,
1368 Object *owner,
1369 const char *name,
1370 uint64_t size,
1371 uint64_t max_size,
1372 void (*resized)(const char*,
1373 uint64_t length,
1374 void *host),
1375 Error **errp)
1376{
1377 memory_region_init(mr, owner, name, size);
1378 mr->ram = true;
1379 mr->terminates = true;
1380 mr->destructor = memory_region_destructor_ram;
8e41fb63
FZ		 1381 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1382 mr, errp);
677e7805 1383 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
60786ef3
MT		 1384}
1385
0b183fc8
PB		 1386#ifdef __linux__
1387void memory_region_init_ram_from_file(MemoryRegion *mr,
1388 struct Object *owner,
1389 const char *name,
1390 uint64_t size,
dbcb8981 1391 bool share,
7f56e740
PB		 1392 const char *path,
1393 Error **errp)
0b183fc8
PB		 1394{
1395 memory_region_init(mr, owner, name, size);
1396 mr->ram = true;
1397 mr->terminates = true;
1398 mr->destructor = memory_region_destructor_ram;
8e41fb63 1399 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
677e7805 1400 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
093bc2cd 1401}
fea617c5
MAL		 1402
1403void memory_region_init_ram_from_fd(MemoryRegion *mr,
1404 struct Object *owner,
1405 const char *name,
1406 uint64_t size,
1407 bool share,
1408 int fd,
1409 Error **errp)
1410{
1411 memory_region_init(mr, owner, name, size);
1412 mr->ram = true;
1413 mr->terminates = true;
1414 mr->destructor = memory_region_destructor_ram;
1415 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1416 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1417}
0b183fc8 1418#endif
093bc2cd
AK		 1419
1420void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1421 Object *owner,
093bc2cd
AK		 1422 const char *name,
1423 uint64_t size,
1424 void *ptr)
1425{
2c9b15ca 1426 memory_region_init(mr, owner, name, size);
8ea9252a 1427 mr->ram = true;
14a3c10a 1428 mr->terminates = true;
fc3e7665 1429 mr->destructor = memory_region_destructor_ram;
677e7805 1430 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT		 1431
1432 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1433 assert(ptr != NULL);
8e41fb63 1434 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK		 1435}
1436
21e00fa5
AW		 1437void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1438 Object *owner,
1439 const char *name,
1440 uint64_t size,
1441 void *ptr)
e4dc3f59 1442{
21e00fa5
AW		 1443 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1444 mr->ram_device = true;
4a2e242b
AW		 1445 mr->ops = &ram_device_mem_ops;
1446 mr->opaque = mr;
e4dc3f59
ND		 1447}
1448
093bc2cd 1449void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1450 Object *owner,
093bc2cd
AK		 1451 const char *name,
1452 MemoryRegion *orig,
a8170e5e 1453 hwaddr offset,
093bc2cd
AK		 1454 uint64_t size)
1455{
2c9b15ca 1456 memory_region_init(mr, owner, name, size);
093bc2cd
AK		 1457 mr->alias = orig;
1458 mr->alias_offset = offset;
1459}
1460
a1777f7f
PM		 1461void memory_region_init_rom(MemoryRegion *mr,
1462 struct Object *owner,
1463 const char *name,
1464 uint64_t size,
1465 Error **errp)
1466{
1467 memory_region_init(mr, owner, name, size);
1468 mr->ram = true;
1469 mr->readonly = true;
1470 mr->terminates = true;
1471 mr->destructor = memory_region_destructor_ram;
1472 mr->ram_block = qemu_ram_alloc(size, mr, errp);
1473 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1474}
1475
d0a9b5bc 1476void memory_region_init_rom_device(MemoryRegion *mr,
2c9b15ca 1477 Object *owner,
d0a9b5bc 1478 const MemoryRegionOps *ops,
75f5941c 1479 void *opaque,
d0a9b5bc 1480 const char *name,
33e0eb52
HT		 1481 uint64_t size,
1482 Error **errp)
d0a9b5bc 1483{
39e0b03d 1484 assert(ops);
2c9b15ca 1485 memory_region_init(mr, owner, name, size);
7bc2b9cd 1486 mr->ops = ops;
75f5941c 1487 mr->opaque = opaque;
d0a9b5bc 1488 mr->terminates = true;
75c578dc 1489 mr->rom_device = true;
58268c8d 1490 mr->destructor = memory_region_destructor_ram;
8e41fb63 1491 mr->ram_block = qemu_ram_alloc(size, mr, errp);
d0a9b5bc
AK		 1492}
1493
30951157 1494void memory_region_init_iommu(MemoryRegion *mr,
2c9b15ca 1495 Object *owner,
30951157
AK		 1496 const MemoryRegionIOMMUOps *ops,
1497 const char *name,
1498 uint64_t size)
1499{
2c9b15ca 1500 memory_region_init(mr, owner, name, size);
30951157
AK		 1501 mr->iommu_ops = ops,
1502 mr->terminates = true; /* then re-forwards */
cdb30812 1503 QLIST_INIT(&mr->iommu_notify);
5bf3d319 1504 mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK		 1505}
1506
b4fefef9 1507static void memory_region_finalize(Object *obj)
093bc2cd 1508{
b4fefef9
PC		 1509 MemoryRegion *mr = MEMORY_REGION(obj);
1510
2e2b8eb7
PB		 1511 assert(!mr->container);
1512
1513 /* We know the region is not visible in any address space (it
1514 * does not have a container and cannot be a root either because
1515 * it has no references, so we can blindly clear mr->enabled.
1516 * memory_region_set_enabled instead could trigger a transaction
1517 * and cause an infinite loop.
1518 */
1519 mr->enabled = false;
1520 memory_region_transaction_begin();
1521 while (!QTAILQ_EMPTY(&mr->subregions)) {
1522 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1523 memory_region_del_subregion(mr, subregion);
1524 }
1525 memory_region_transaction_commit();
1526
545e92e0 1527 mr->destructor(mr);
093bc2cd 1528 memory_region_clear_coalescing(mr);
302fa283 1529 g_free((char *)mr->name);
7267c094 1530 g_free(mr->ioeventfds);
093bc2cd
AK		 1531}
1532
803c0816
PB		 1533Object *memory_region_owner(MemoryRegion *mr)
1534{
22a893e4
PB		 1535 Object *obj = OBJECT(mr);
1536 return obj->parent;
803c0816
PB		 1537}
1538
46637be2
PB		 1539void memory_region_ref(MemoryRegion *mr)
1540{
22a893e4
PB		 1541 /* MMIO callbacks most likely will access data that belongs
1542 * to the owner, hence the need to ref/unref the owner whenever
1543 * the memory region is in use.
1544 *
1545 * The memory region is a child of its owner. As long as the
1546 * owner doesn't call unparent itself on the memory region,
1547 * ref-ing the owner will also keep the memory region alive.
612263cf
PB		 1548 * Memory regions without an owner are supposed to never go away;
1549 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1550 */
612263cf
PB		 1551 if (mr && mr->owner) {
1552 object_ref(mr->owner);
46637be2
PB		 1553 }
1554}
1555
1556void memory_region_unref(MemoryRegion *mr)
1557{
612263cf
PB		 1558 if (mr && mr->owner) {
1559 object_unref(mr->owner);
46637be2
PB		 1560 }
1561}
1562
093bc2cd
AK		 1563uint64_t memory_region_size(MemoryRegion *mr)
1564{
08dafab4
AK		 1565 if (int128_eq(mr->size, int128_2_64())) {
1566 return UINT64_MAX;
1567 }
1568 return int128_get64(mr->size);
093bc2cd
AK		 1569}
1570
5d546d4b 1571const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1572{
d1dd32af
PC		 1573 if (!mr->name) {
1574 ((MemoryRegion *)mr)->name =
1575 object_get_canonical_path_component(OBJECT(mr));
1576 }
302fa283 1577 return mr->name;
8991c79b
AK		 1578}
1579
21e00fa5 1580bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1581{
21e00fa5 1582 return mr->ram_device;
e4dc3f59
ND		 1583}
1584
2d1a35be 1585uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1586{
6f6a5ef3 1587 uint8_t mask = mr->dirty_log_mask;
adaad61c 1588 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB		 1589 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1590 }
1591 return mask;
55043ba3
AK		 1592}
1593
2d1a35be
PB		 1594bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1595{
1596 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1597}
1598
5bf3d319
PX		 1599static void memory_region_update_iommu_notify_flags(MemoryRegion *mr)
1600{
1601 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1602 IOMMUNotifier *iommu_notifier;
1603
512fa408 1604 IOMMU_NOTIFIER_FOREACH(iommu_notifier, mr) {
5bf3d319
PX		 1605 flags |= iommu_notifier->notifier_flags;
1606 }
1607
1608 if (flags != mr->iommu_notify_flags &&
1609 mr->iommu_ops->notify_flag_changed) {
1610 mr->iommu_ops->notify_flag_changed(mr, mr->iommu_notify_flags,
1611 flags);
1612 }
1613
1614 mr->iommu_notify_flags = flags;
1615}
1616
cdb30812
PX		 1617void memory_region_register_iommu_notifier(MemoryRegion *mr,
1618 IOMMUNotifier *n)
06866575 1619{
efcd38c5
JW		 1620 if (mr->alias) {
1621 memory_region_register_iommu_notifier(mr->alias, n);
1622 return;
1623 }
1624
cdb30812
PX		 1625 /* We need to register for at least one bitfield */
1626 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1627 assert(n->start <= n->end);
cdb30812 1628 QLIST_INSERT_HEAD(&mr->iommu_notify, n, node);
5bf3d319 1629 memory_region_update_iommu_notify_flags(mr);
06866575
DG		 1630}
1631
f682e9c2 1632uint64_t memory_region_iommu_get_min_page_size(MemoryRegion *mr)
a788f227 1633{
f682e9c2
AK		 1634 assert(memory_region_is_iommu(mr));
1635 if (mr->iommu_ops && mr->iommu_ops->get_min_page_size) {
1636 return mr->iommu_ops->get_min_page_size(mr);
1637 }
1638 return TARGET_PAGE_SIZE;
1639}
1640
ad523590 1641void memory_region_iommu_replay(MemoryRegion *mr, IOMMUNotifier *n)
f682e9c2
AK		 1642{
1643 hwaddr addr, granularity;
a788f227
DG		 1644 IOMMUTLBEntry iotlb;
1645
faa362e3
PX		 1646 /* If the IOMMU has its own replay callback, override */
1647 if (mr->iommu_ops->replay) {
1648 mr->iommu_ops->replay(mr, n);
1649 return;
1650 }
1651
f682e9c2
AK		 1652 granularity = memory_region_iommu_get_min_page_size(mr);
1653
a788f227 1654 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
ad523590 1655 iotlb = mr->iommu_ops->translate(mr, addr, IOMMU_NONE);
a788f227
DG		 1656 if (iotlb.perm != IOMMU_NONE) {
1657 n->notify(n, &iotlb);
1658 }
1659
1660 /* if (2^64 - MR size) < granularity, it's possible to get an
1661 * infinite loop here. This should catch such a wraparound */
1662 if ((addr + granularity) < addr) {
1663 break;
1664 }
1665 }
1666}
1667
de472e4a
PX		 1668void memory_region_iommu_replay_all(MemoryRegion *mr)
1669{
1670 IOMMUNotifier *notifier;
1671
1672 IOMMU_NOTIFIER_FOREACH(notifier, mr) {
ad523590 1673 memory_region_iommu_replay(mr, notifier);
de472e4a
PX		 1674 }
1675}
1676
cdb30812
PX		 1677void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1678 IOMMUNotifier *n)
06866575 1679{
efcd38c5
JW		 1680 if (mr->alias) {
1681 memory_region_unregister_iommu_notifier(mr->alias, n);
1682 return;
1683 }
cdb30812 1684 QLIST_REMOVE(n, node);
5bf3d319 1685 memory_region_update_iommu_notify_flags(mr);
06866575
DG		 1686}
1687
bd2bfa4c
PX		 1688void memory_region_notify_one(IOMMUNotifier *notifier,
1689 IOMMUTLBEntry *entry)
06866575 1690{
cdb30812
PX		 1691 IOMMUNotifierFlag request_flags;
1692
bd2bfa4c
PX		 1693 /*
1694 * Skip the notification if the notification does not overlap
1695 * with registered range.
1696 */
1697 if (notifier->start > entry->iova + entry->addr_mask + 1 ||
1698 notifier->end < entry->iova) {
1699 return;
1700 }
cdb30812 1701
bd2bfa4c 1702 if (entry->perm & IOMMU_RW) {
cdb30812
PX		 1703 request_flags = IOMMU_NOTIFIER_MAP;
1704 } else {
1705 request_flags = IOMMU_NOTIFIER_UNMAP;
1706 }
1707
bd2bfa4c
PX		 1708 if (notifier->notifier_flags & request_flags) {
1709 notifier->notify(notifier, entry);
1710 }
1711}
1712
1713void memory_region_notify_iommu(MemoryRegion *mr,
1714 IOMMUTLBEntry entry)
1715{
1716 IOMMUNotifier *iommu_notifier;
1717
1718 assert(memory_region_is_iommu(mr));
1719
512fa408 1720 IOMMU_NOTIFIER_FOREACH(iommu_notifier, mr) {
bd2bfa4c 1721 memory_region_notify_one(iommu_notifier, &entry);
cdb30812 1722 }
06866575
DG		 1723}
1724
093bc2cd
AK		 1725void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1726{
5a583347 1727 uint8_t mask = 1 << client;
deb809ed 1728 uint8_t old_logging;
5a583347 1729
dbddac6d 1730 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB		 1731 old_logging = mr->vga_logging_count;
1732 mr->vga_logging_count += log ? 1 : -1;
1733 if (!!old_logging == !!mr->vga_logging_count) {
1734 return;
1735 }
1736
59023ef4 1737 memory_region_transaction_begin();
5a583347 1738 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1739 memory_region_update_pending |= mr->enabled;
59023ef4 1740 memory_region_transaction_commit();
093bc2cd
AK		 1741}
1742
a8170e5e
AK		 1743bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1744 hwaddr size, unsigned client)
093bc2cd 1745{
8e41fb63
FZ		 1746 assert(mr->ram_block);
1747 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1748 size, client);
093bc2cd
AK		 1749}
1750
a8170e5e
AK		 1751void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1752 hwaddr size)
093bc2cd 1753{
8e41fb63
FZ		 1754 assert(mr->ram_block);
1755 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1756 size,
58d2707e 1757 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK		 1758}
1759
6c279db8
JQ		 1760bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1761 hwaddr size, unsigned client)
1762{
8e41fb63
FZ		 1763 assert(mr->ram_block);
1764 return cpu_physical_memory_test_and_clear_dirty(
1765 memory_region_get_ram_addr(mr) + addr, size, client);
6c279db8
JQ		 1766}
1767
8deaf12c
GH		 1768DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
1769 hwaddr addr,
1770 hwaddr size,
1771 unsigned client)
1772{
1773 assert(mr->ram_block);
1774 return cpu_physical_memory_snapshot_and_clear_dirty(
1775 memory_region_get_ram_addr(mr) + addr, size, client);
1776}
1777
1778bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
1779 hwaddr addr, hwaddr size)
1780{
1781 assert(mr->ram_block);
1782 return cpu_physical_memory_snapshot_get_dirty(snap,
1783 memory_region_get_ram_addr(mr) + addr, size);
1784}
6c279db8 1785
093bc2cd
AK		 1786void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1787{
0a752eee 1788 MemoryListener *listener;
0d673e36 1789 AddressSpace *as;
0a752eee 1790 FlatView *view;
5a583347
AK		 1791 FlatRange *fr;
1792
0a752eee
PB		 1793 /* If the same address space has multiple log_sync listeners, we
1794 * visit that address space's FlatView multiple times. But because
1795 * log_sync listeners are rare, it's still cheaper than walking each
1796 * address space once.
1797 */
1798 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1799 if (!listener->log_sync) {
1800 continue;
1801 }
1802 as = listener->address_space;
1803 view = address_space_get_flatview(as);
99e86347 1804 FOR_EACH_FLAT_RANGE(fr, view) {
0d673e36 1805 if (fr->mr == mr) {
0a752eee
PB		 1806 MemoryRegionSection mrs = section_from_flat_range(fr, as);
1807 listener->log_sync(listener, &mrs);
0d673e36 1808 }
5a583347 1809 }
856d7245 1810 flatview_unref(view);
5a583347 1811 }
093bc2cd
AK		 1812}
1813
1814void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1815{
fb1cd6f9 1816 if (mr->readonly != readonly) {
59023ef4 1817 memory_region_transaction_begin();
fb1cd6f9 1818 mr->readonly = readonly;
22bde714 1819 memory_region_update_pending |= mr->enabled;
59023ef4 1820 memory_region_transaction_commit();
fb1cd6f9 1821 }
093bc2cd
AK		 1822}
1823
5f9a5ea1 1824void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 1825{
5f9a5ea1 1826 if (mr->romd_mode != romd_mode) {
59023ef4 1827 memory_region_transaction_begin();
5f9a5ea1 1828 mr->romd_mode = romd_mode;
22bde714 1829 memory_region_update_pending |= mr->enabled;
59023ef4 1830 memory_region_transaction_commit();
d0a9b5bc
AK		 1831 }
1832}
1833
a8170e5e
AK		 1834void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
1835 hwaddr size, unsigned client)
093bc2cd 1836{
8e41fb63
FZ		 1837 assert(mr->ram_block);
1838 cpu_physical_memory_test_and_clear_dirty(
1839 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK		 1840}
1841
a35ba7be
PB		 1842int memory_region_get_fd(MemoryRegion *mr)
1843{
4ff87573
PB		 1844 int fd;
1845
1846 rcu_read_lock();
1847 while (mr->alias) {
1848 mr = mr->alias;
a35ba7be 1849 }
4ff87573
PB		 1850 fd = mr->ram_block->fd;
1851 rcu_read_unlock();
a35ba7be 1852
4ff87573
PB		 1853 return fd;
1854}
a35ba7be 1855
093bc2cd
AK		 1856void *memory_region_get_ram_ptr(MemoryRegion *mr)
1857{
49b24afc
PB		 1858 void *ptr;
1859 uint64_t offset = 0;
093bc2cd 1860
49b24afc
PB		 1861 rcu_read_lock();
1862 while (mr->alias) {
1863 offset += mr->alias_offset;
1864 mr = mr->alias;
1865 }
8e41fb63 1866 assert(mr->ram_block);
0878d0e1 1867 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
49b24afc 1868 rcu_read_unlock();
093bc2cd 1869
0878d0e1 1870 return ptr;
093bc2cd
AK		 1871}
1872
07bdaa41
PB		 1873MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
1874{
1875 RAMBlock *block;
1876
1877 block = qemu_ram_block_from_host(ptr, false, offset);
1878 if (!block) {
1879 return NULL;
1880 }
1881
1882 return block->mr;
1883}
1884
7ebb2745
FZ		 1885ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
1886{
1887 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
1888}
1889
37d7c084
PB		 1890void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
1891{
8e41fb63 1892 assert(mr->ram_block);
37d7c084 1893
fa53a0e5 1894 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB		 1895}
1896
0d673e36 1897static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 1898{
99e86347 1899 FlatView *view;
093bc2cd
AK		 1900 FlatRange *fr;
1901 CoalescedMemoryRange *cmr;
1902 AddrRange tmp;
95d2994a 1903 MemoryRegionSection section;
093bc2cd 1904
856d7245 1905 view = address_space_get_flatview(as);
99e86347 1906 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 1907 if (fr->mr == mr) {
95d2994a 1908 section = (MemoryRegionSection) {
f6790af6 1909 .address_space = as,
95d2994a 1910 .offset_within_address_space = int128_get64(fr->addr.start),
052e87b0 1911 .size = fr->addr.size,
95d2994a
AK		 1912 };
1913
9a54635d 1914 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
95d2994a
AK		 1915 int128_get64(fr->addr.start),
1916 int128_get64(fr->addr.size));
093bc2cd
AK		 1917 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
1918 tmp = addrrange_shift(cmr->addr,
08dafab4
AK		 1919 int128_sub(fr->addr.start,
1920 int128_make64(fr->offset_in_region)));
093bc2cd
AK		 1921 if (!addrrange_intersects(tmp, fr->addr)) {
1922 continue;
1923 }
1924 tmp = addrrange_intersection(tmp, fr->addr);
9a54635d 1925 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
95d2994a
AK		 1926 int128_get64(tmp.start),
1927 int128_get64(tmp.size));
093bc2cd
AK		 1928 }
1929 }
1930 }
856d7245 1931 flatview_unref(view);
093bc2cd
AK		 1932}
1933
0d673e36
AK		 1934static void memory_region_update_coalesced_range(MemoryRegion *mr)
1935{
1936 AddressSpace *as;
1937
1938 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1939 memory_region_update_coalesced_range_as(mr, as);
1940 }
1941}
1942
093bc2cd
AK		 1943void memory_region_set_coalescing(MemoryRegion *mr)
1944{
1945 memory_region_clear_coalescing(mr);
08dafab4 1946 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK		 1947}
1948
1949void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 1950 hwaddr offset,
093bc2cd
AK		 1951 uint64_t size)
1952{
7267c094 1953 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 1954
08dafab4 1955 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK		 1956 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
1957 memory_region_update_coalesced_range(mr);
d410515e 1958 memory_region_set_flush_coalesced(mr);
093bc2cd
AK		 1959}
1960
1961void memory_region_clear_coalescing(MemoryRegion *mr)
1962{
1963 CoalescedMemoryRange *cmr;
ab5b3db5 1964 bool updated = false;
093bc2cd 1965
d410515e
JK		 1966 qemu_flush_coalesced_mmio_buffer();
1967 mr->flush_coalesced_mmio = false;
1968
093bc2cd
AK		 1969 while (!QTAILQ_EMPTY(&mr->coalesced)) {
1970 cmr = QTAILQ_FIRST(&mr->coalesced);
1971 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 1972 g_free(cmr);
ab5b3db5
FZ		 1973 updated = true;
1974 }
1975
1976 if (updated) {
1977 memory_region_update_coalesced_range(mr);
093bc2cd 1978 }
093bc2cd
AK		 1979}
1980
d410515e
JK		 1981void memory_region_set_flush_coalesced(MemoryRegion *mr)
1982{
1983 mr->flush_coalesced_mmio = true;
1984}
1985
1986void memory_region_clear_flush_coalesced(MemoryRegion *mr)
1987{
1988 qemu_flush_coalesced_mmio_buffer();
1989 if (QTAILQ_EMPTY(&mr->coalesced)) {
1990 mr->flush_coalesced_mmio = false;
1991 }
1992}
1993
196ea131
JK		 1994void memory_region_set_global_locking(MemoryRegion *mr)
1995{
1996 mr->global_locking = true;
1997}
1998
1999void memory_region_clear_global_locking(MemoryRegion *mr)
2000{
2001 mr->global_locking = false;
2002}
2003
8c56c1a5
PF		 2004static bool userspace_eventfd_warning;
2005
3e9d69e7 2006void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2007 hwaddr addr,
3e9d69e7
AK		 2008 unsigned size,
2009 bool match_data,
2010 uint64_t data,
753d5e14 2011 EventNotifier *e)
3e9d69e7
AK		 2012{
2013 MemoryRegionIoeventfd mrfd = {
08dafab4
AK		 2014 .addr.start = int128_make64(addr),
2015 .addr.size = int128_make64(size),
3e9d69e7
AK		 2016 .match_data = match_data,
2017 .data = data,
753d5e14 2018 .e = e,
3e9d69e7
AK		 2019 };
2020 unsigned i;
2021
8c56c1a5
PF		 2022 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2023 userspace_eventfd_warning))) {
2024 userspace_eventfd_warning = true;
2025 error_report("Using eventfd without MMIO binding in KVM. "
2026 "Suboptimal performance expected");
2027 }
2028
b8aecea2
JW		 2029 if (size) {
2030 adjust_endianness(mr, &mrfd.data, size);
2031 }
59023ef4 2032 memory_region_transaction_begin();
3e9d69e7
AK		 2033 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2034 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
2035 break;
2036 }
2037 }
2038 ++mr->ioeventfd_nb;
7267c094 2039 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK		 2040 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2041 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2042 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2043 mr->ioeventfds[i] = mrfd;
4dc56152 2044 ioeventfd_update_pending |= mr->enabled;
59023ef4 2045 memory_region_transaction_commit();
3e9d69e7
AK		 2046}
2047
2048void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2049 hwaddr addr,
3e9d69e7
AK		 2050 unsigned size,
2051 bool match_data,
2052 uint64_t data,
753d5e14 2053 EventNotifier *e)
3e9d69e7
AK		 2054{
2055 MemoryRegionIoeventfd mrfd = {
08dafab4
AK		 2056 .addr.start = int128_make64(addr),
2057 .addr.size = int128_make64(size),
3e9d69e7
AK		 2058 .match_data = match_data,
2059 .data = data,
753d5e14 2060 .e = e,
3e9d69e7
AK		 2061 };
2062 unsigned i;
2063
b8aecea2
JW		 2064 if (size) {
2065 adjust_endianness(mr, &mrfd.data, size);
2066 }
59023ef4 2067 memory_region_transaction_begin();
3e9d69e7
AK		 2068 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2069 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
2070 break;
2071 }
2072 }
2073 assert(i != mr->ioeventfd_nb);
2074 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2075 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2076 --mr->ioeventfd_nb;
7267c094 2077 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2078 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2079 ioeventfd_update_pending |= mr->enabled;
59023ef4 2080 memory_region_transaction_commit();
3e9d69e7
AK		 2081}
2082
feca4ac1 2083static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2084{
feca4ac1 2085 MemoryRegion *mr = subregion->container;
093bc2cd
AK		 2086 MemoryRegion *other;
2087
59023ef4
JK		 2088 memory_region_transaction_begin();
2089
dfde4e6e 2090 memory_region_ref(subregion);
093bc2cd
AK		 2091 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2092 if (subregion->priority >= other->priority) {
2093 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2094 goto done;
2095 }
2096 }
2097 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2098done:
22bde714 2099 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2100 memory_region_transaction_commit();
093bc2cd
AK		 2101}
2102
0598701a
PC		 2103static void memory_region_add_subregion_common(MemoryRegion *mr,
2104 hwaddr offset,
2105 MemoryRegion *subregion)
2106{
feca4ac1
PB		 2107 assert(!subregion->container);
2108 subregion->container = mr;
0598701a 2109 subregion->addr = offset;
feca4ac1 2110 memory_region_update_container_subregions(subregion);
0598701a 2111}
093bc2cd
AK		 2112
2113void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2114 hwaddr offset,
093bc2cd
AK		 2115 MemoryRegion *subregion)
2116{
093bc2cd
AK		 2117 subregion->priority = 0;
2118 memory_region_add_subregion_common(mr, offset, subregion);
2119}
2120
2121void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2122 hwaddr offset,
093bc2cd 2123 MemoryRegion *subregion,
a1ff8ae0 2124 int priority)
093bc2cd 2125{
093bc2cd
AK		 2126 subregion->priority = priority;
2127 memory_region_add_subregion_common(mr, offset, subregion);
2128}
2129
2130void memory_region_del_subregion(MemoryRegion *mr,
2131 MemoryRegion *subregion)
2132{
59023ef4 2133 memory_region_transaction_begin();
feca4ac1
PB		 2134 assert(subregion->container == mr);
2135 subregion->container = NULL;
093bc2cd 2136 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2137 memory_region_unref(subregion);
22bde714 2138 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2139 memory_region_transaction_commit();
6bba19ba
AK		 2140}
2141
2142void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2143{
2144 if (enabled == mr->enabled) {
2145 return;
2146 }
59023ef4 2147 memory_region_transaction_begin();
6bba19ba 2148 mr->enabled = enabled;
22bde714 2149 memory_region_update_pending = true;
59023ef4 2150 memory_region_transaction_commit();
093bc2cd 2151}
1c0ffa58 2152
e7af4c67
MT		 2153void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2154{
2155 Int128 s = int128_make64(size);
2156
2157 if (size == UINT64_MAX) {
2158 s = int128_2_64();
2159 }
2160 if (int128_eq(s, mr->size)) {
2161 return;
2162 }
2163 memory_region_transaction_begin();
2164 mr->size = s;
2165 memory_region_update_pending = true;
2166 memory_region_transaction_commit();
2167}
2168
67891b8a 2169static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2170{
feca4ac1 2171 MemoryRegion *container = mr->container;
2282e1af 2172
feca4ac1 2173 if (container) {
67891b8a
PC		 2174 memory_region_transaction_begin();
2175 memory_region_ref(mr);
feca4ac1
PB		 2176 memory_region_del_subregion(container, mr);
2177 mr->container = container;
2178 memory_region_update_container_subregions(mr);
67891b8a
PC		 2179 memory_region_unref(mr);
2180 memory_region_transaction_commit();
2282e1af 2181 }
67891b8a 2182}
2282e1af 2183
67891b8a
PC		 2184void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2185{
2186 if (addr != mr->addr) {
2187 mr->addr = addr;
2188 memory_region_readd_subregion(mr);
2189 }
2282e1af
AK		 2190}
2191
a8170e5e 2192void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2193{
4703359e 2194 assert(mr->alias);
4703359e 2195
59023ef4 2196 if (offset == mr->alias_offset) {
4703359e
AK		 2197 return;
2198 }
2199
59023ef4
JK		 2200 memory_region_transaction_begin();
2201 mr->alias_offset = offset;
22bde714 2202 memory_region_update_pending |= mr->enabled;
59023ef4 2203 memory_region_transaction_commit();
4703359e
AK		 2204}
2205
a2b257d6
IM		 2206uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2207{
2208 return mr->align;
2209}
2210
e2177955
AK		 2211static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2212{
2213 const AddrRange *addr = addr_;
2214 const FlatRange *fr = fr_;
2215
2216 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2217 return -1;
2218 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2219 return 1;
2220 }
2221 return 0;
2222}
2223
99e86347 2224static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2225{
99e86347 2226 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK		 2227 sizeof(FlatRange), cmp_flatrange_addr);
2228}
2229
eed2bacf
IM		 2230bool memory_region_is_mapped(MemoryRegion *mr)
2231{
2232 return mr->container ? true : false;
2233}
2234
c6742b14
PB		 2235/* Same as memory_region_find, but it does not add a reference to the
2236 * returned region. It must be called from an RCU critical section.
2237 */
2238static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2239 hwaddr addr, uint64_t size)
e2177955 2240{
052e87b0 2241 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB		 2242 MemoryRegion *root;
2243 AddressSpace *as;
2244 AddrRange range;
99e86347 2245 FlatView *view;
73034e9e
PB		 2246 FlatRange *fr;
2247
2248 addr += mr->addr;
feca4ac1
PB		 2249 for (root = mr; root->container; ) {
2250 root = root->container;
73034e9e
PB		 2251 addr += root->addr;
2252 }
e2177955 2253
73034e9e 2254 as = memory_region_to_address_space(root);
eed2bacf
IM		 2255 if (!as) {
2256 return ret;
2257 }
73034e9e 2258 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2259
2b647668 2260 view = atomic_rcu_read(&as->current_map);
99e86347 2261 fr = flatview_lookup(view, range);
e2177955 2262 if (!fr) {
c6742b14 2263 return ret;
e2177955
AK		 2264 }
2265
99e86347 2266 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK		 2267 --fr;
2268 }
2269
2270 ret.mr = fr->mr;
73034e9e 2271 ret.address_space = as;
e2177955
AK		 2272 range = addrrange_intersection(range, fr->addr);
2273 ret.offset_within_region = fr->offset_in_region;
2274 ret.offset_within_region += int128_get64(int128_sub(range.start,
2275 fr->addr.start));
052e87b0 2276 ret.size = range.size;
e2177955 2277 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2278 ret.readonly = fr->readonly;
c6742b14
PB		 2279 return ret;
2280}
2281
2282MemoryRegionSection memory_region_find(MemoryRegion *mr,
2283 hwaddr addr, uint64_t size)
2284{
2285 MemoryRegionSection ret;
2286 rcu_read_lock();
2287 ret = memory_region_find_rcu(mr, addr, size);
2288 if (ret.mr) {
2289 memory_region_ref(ret.mr);
2290 }
2b647668 2291 rcu_read_unlock();
e2177955
AK		 2292 return ret;
2293}
2294
c6742b14
PB		 2295bool memory_region_present(MemoryRegion *container, hwaddr addr)
2296{
2297 MemoryRegion *mr;
2298
2299 rcu_read_lock();
2300 mr = memory_region_find_rcu(container, addr, 1).mr;
2301 rcu_read_unlock();
2302 return mr && mr != container;
2303}
2304
9c1f8f44 2305void memory_global_dirty_log_sync(void)
86e775c6 2306{
9c1f8f44
PB		 2307 MemoryListener *listener;
2308 AddressSpace *as;
99e86347 2309 FlatView *view;
7664e80c
AK		 2310 FlatRange *fr;
2311
9c1f8f44
PB		 2312 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2313 if (!listener->log_sync) {
2314 continue;
2315 }
d45fa784 2316 as = listener->address_space;
9c1f8f44
PB		 2317 view = address_space_get_flatview(as);
2318 FOR_EACH_FLAT_RANGE(fr, view) {
adaad61c
PB		 2319 if (fr->dirty_log_mask) {
2320 MemoryRegionSection mrs = section_from_flat_range(fr, as);
2321 listener->log_sync(listener, &mrs);
2322 }
9c1f8f44
PB		 2323 }
2324 flatview_unref(view);
7664e80c
AK		 2325 }
2326}
2327
2328void memory_global_dirty_log_start(void)
2329{
7664e80c 2330 global_dirty_log = true;
6f6a5ef3 2331
7376e582 2332 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3
PB		 2333
2334 /* Refresh DIRTY_LOG_MIGRATION bit. */
2335 memory_region_transaction_begin();
2336 memory_region_update_pending = true;
2337 memory_region_transaction_commit();
7664e80c
AK		 2338}
2339
2340void memory_global_dirty_log_stop(void)
2341{
7664e80c 2342 global_dirty_log = false;
6f6a5ef3
PB		 2343
2344 /* Refresh DIRTY_LOG_MIGRATION bit. */
2345 memory_region_transaction_begin();
2346 memory_region_update_pending = true;
2347 memory_region_transaction_commit();
2348
7376e582 2349 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK		 2350}
2351
2352static void listener_add_address_space(MemoryListener *listener,
2353 AddressSpace *as)
2354{
99e86347 2355 FlatView *view;
7664e80c
AK		 2356 FlatRange *fr;
2357
680a4783
PB		 2358 if (listener->begin) {
2359 listener->begin(listener);
2360 }
7664e80c 2361 if (global_dirty_log) {
975aefe0
AK		 2362 if (listener->log_global_start) {
2363 listener->log_global_start(listener);
2364 }
7664e80c 2365 }
975aefe0 2366
856d7245 2367 view = address_space_get_flatview(as);
99e86347 2368 FOR_EACH_FLAT_RANGE(fr, view) {
7664e80c
AK		 2369 MemoryRegionSection section = {
2370 .mr = fr->mr,
f6790af6 2371 .address_space = as,
7664e80c 2372 .offset_within_region = fr->offset_in_region,
052e87b0 2373 .size = fr->addr.size,
7664e80c 2374 .offset_within_address_space = int128_get64(fr->addr.start),
7a8499e8 2375 .readonly = fr->readonly,
7664e80c 2376 };
680a4783
PB		 2377 if (fr->dirty_log_mask && listener->log_start) {
2378 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2379 }
975aefe0
AK		 2380 if (listener->region_add) {
2381 listener->region_add(listener, &section);
2382 }
7664e80c 2383 }
680a4783
PB		 2384 if (listener->commit) {
2385 listener->commit(listener);
2386 }
856d7245 2387 flatview_unref(view);
7664e80c
AK		 2388}
2389
d45fa784 2390void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2391{
72e22d2f
AK		 2392 MemoryListener *other = NULL;
2393
d45fa784 2394 listener->address_space = as;
72e22d2f
AK		 2395 if (QTAILQ_EMPTY(&memory_listeners)
2396 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2397 memory_listeners)->priority) {
2398 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2399 } else {
2400 QTAILQ_FOREACH(other, &memory_listeners, link) {
2401 if (listener->priority < other->priority) {
2402 break;
2403 }
2404 }
2405 QTAILQ_INSERT_BEFORE(other, listener, link);
2406 }
0d673e36 2407
9a54635d
PB		 2408 if (QTAILQ_EMPTY(&as->listeners)
2409 || listener->priority >= QTAILQ_LAST(&as->listeners,
2410 memory_listeners)->priority) {
2411 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2412 } else {
2413 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2414 if (listener->priority < other->priority) {
2415 break;
2416 }
2417 }
2418 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2419 }
2420
d45fa784 2421 listener_add_address_space(listener, as);
7664e80c
AK		 2422}
2423
2424void memory_listener_unregister(MemoryListener *listener)
2425{
1d8280c1
PB		 2426 if (!listener->address_space) {
2427 return;
2428 }
2429
72e22d2f 2430 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2431 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2432 listener->address_space = NULL;
86e775c6 2433}
e2177955 2434
c9356746
FK		 2435bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2436{
2437 void *host;
2438 unsigned size = 0;
2439 unsigned offset = 0;
2440 Object *new_interface;
2441
2442 if (!mr || !mr->ops->request_ptr) {
2443 return false;
2444 }
2445
2446 /*
2447 * Avoid an update if the request_ptr call
2448 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2449 * a cache.
2450 */
2451 memory_region_transaction_begin();
2452
2453 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2454
2455 if (!host || !size) {
2456 memory_region_transaction_commit();
2457 return false;
2458 }
2459
2460 new_interface = object_new("mmio_interface");
2461 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2462 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2463 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2464 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2465 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2466 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2467
2468 memory_region_transaction_commit();
2469 return true;
2470}
2471
2472typedef struct MMIOPtrInvalidate {
2473 MemoryRegion *mr;
2474 hwaddr offset;
2475 unsigned size;
2476 int busy;
2477 int allocated;
2478} MMIOPtrInvalidate;
2479
2480#define MAX_MMIO_INVALIDATE 10
2481static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2482
2483static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2484 run_on_cpu_data data)
2485{
2486 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2487 MemoryRegion *mr = invalidate_data->mr;
2488 hwaddr offset = invalidate_data->offset;
2489 unsigned size = invalidate_data->size;
2490 MemoryRegionSection section = memory_region_find(mr, offset, size);
2491
2492 qemu_mutex_lock_iothread();
2493
2494 /* Reset dirty so this doesn't happen later. */
2495 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2496
2497 if (section.mr != mr) {
2498 /* memory_region_find add a ref on section.mr */
2499 memory_region_unref(section.mr);
2500 if (MMIO_INTERFACE(section.mr->owner)) {
2501 /* We found the interface just drop it. */
2502 object_property_set_bool(section.mr->owner, false, "realized",
2503 NULL);
2504 object_unref(section.mr->owner);
2505 object_unparent(section.mr->owner);
2506 }
2507 }
2508
2509 qemu_mutex_unlock_iothread();
2510
2511 if (invalidate_data->allocated) {
2512 g_free(invalidate_data);
2513 } else {
2514 invalidate_data->busy = 0;
2515 }
2516}
2517
2518void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2519 unsigned size)
2520{
2521 size_t i;
2522 MMIOPtrInvalidate *invalidate_data = NULL;
2523
2524 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2525 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2526 invalidate_data = &mmio_ptr_invalidate_list[i];
2527 break;
2528 }
2529 }
2530
2531 if (!invalidate_data) {
2532 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2533 invalidate_data->allocated = 1;
2534 }
2535
2536 invalidate_data->mr = mr;
2537 invalidate_data->offset = offset;
2538 invalidate_data->size = size;
2539
2540 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2541 RUN_ON_CPU_HOST_PTR(invalidate_data));
2542}
2543
7dca8043 2544void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2545{
ac95190e 2546 memory_region_ref(root);
59023ef4 2547 memory_region_transaction_begin();
f0c02d15 2548 as->ref_count = 1;
8786db7c 2549 as->root = root;
f0c02d15 2550 as->malloced = false;
8786db7c
AK		 2551 as->current_map = g_new(FlatView, 1);
2552 flatview_init(as->current_map);
4c19eb72
AK		 2553 as->ioeventfd_nb = 0;
2554 as->ioeventfds = NULL;
9a54635d 2555 QTAILQ_INIT(&as->listeners);
0d673e36 2556 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2557 as->name = g_strdup(name ? name : "anonymous");
ac1970fb 2558 address_space_init_dispatch(as);
f43793c7
PB		 2559 memory_region_update_pending |= root->enabled;
2560 memory_region_transaction_commit();
1c0ffa58 2561}
658b2224 2562
374f2981 2563static void do_address_space_destroy(AddressSpace *as)
83f3c251 2564{
f0c02d15 2565 bool do_free = as->malloced;
078c44f4 2566
83f3c251 2567 address_space_destroy_dispatch(as);
9a54635d 2568 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2569
856d7245 2570 flatview_unref(as->current_map);
7dca8043 2571 g_free(as->name);
4c19eb72 2572 g_free(as->ioeventfds);
ac95190e 2573 memory_region_unref(as->root);
f0c02d15
PC		 2574 if (do_free) {
2575 g_free(as);
2576 }
2577}
2578
2579AddressSpace *address_space_init_shareable(MemoryRegion *root, const char *name)
2580{
2581 AddressSpace *as;
2582
2583 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2584 if (root == as->root && as->malloced) {
2585 as->ref_count++;
2586 return as;
2587 }
2588 }
2589
2590 as = g_malloc0(sizeof *as);
2591 address_space_init(as, root, name);
2592 as->malloced = true;
2593 return as;
83f3c251
AK		 2594}
2595
374f2981
PB		 2596void address_space_destroy(AddressSpace *as)
2597{
ac95190e
PB		 2598 MemoryRegion *root = as->root;
2599
f0c02d15
PC		 2600 as->ref_count--;
2601 if (as->ref_count) {
2602 return;
2603 }
374f2981
PB		 2604 /* Flush out anything from MemoryListeners listening in on this */
2605 memory_region_transaction_begin();
2606 as->root = NULL;
2607 memory_region_transaction_commit();
2608 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
6e48e8f9 2609 address_space_unregister(as);
374f2981
PB		 2610
2611 /* At this point, as->dispatch and as->current_map are dummy
2612 * entries that the guest should never use. Wait for the old
2613 * values to expire before freeing the data.
2614 */
ac95190e 2615 as->root = root;
374f2981
PB		 2616 call_rcu(as, do_address_space_destroy, rcu);
2617}
2618
4e831901
PX		 2619static const char *memory_region_type(MemoryRegion *mr)
2620{
2621 if (memory_region_is_ram_device(mr)) {
2622 return "ramd";
2623 } else if (memory_region_is_romd(mr)) {
2624 return "romd";
2625 } else if (memory_region_is_rom(mr)) {
2626 return "rom";
2627 } else if (memory_region_is_ram(mr)) {
2628 return "ram";
2629 } else {
2630 return "i/o";
2631 }
2632}
2633
314e2987
BS		 2634typedef struct MemoryRegionList MemoryRegionList;
2635
2636struct MemoryRegionList {
2637 const MemoryRegion *mr;
314e2987
BS		 2638 QTAILQ_ENTRY(MemoryRegionList) queue;
2639};
2640
2641typedef QTAILQ_HEAD(queue, MemoryRegionList) MemoryRegionListHead;
2642
4e831901
PX		 2643#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2644 int128_sub((size), int128_one())) : 0)
2645#define MTREE_INDENT " "
2646
314e2987
BS		 2647static void mtree_print_mr(fprintf_function mon_printf, void *f,
2648 const MemoryRegion *mr, unsigned int level,
a8170e5e 2649 hwaddr base,
9479c57a 2650 MemoryRegionListHead *alias_print_queue)
314e2987 2651{
9479c57a
JK		 2652 MemoryRegionList *new_ml, *ml, *next_ml;
2653 MemoryRegionListHead submr_print_queue;
314e2987
BS		 2654 const MemoryRegion *submr;
2655 unsigned int i;
b31f8412 2656 hwaddr cur_start, cur_end;
314e2987 2657
f8a9f720 2658 if (!mr) {
314e2987
BS		 2659 return;
2660 }
2661
2662 for (i = 0; i < level; i++) {
4e831901 2663 mon_printf(f, MTREE_INDENT);
314e2987
BS		 2664 }
2665
b31f8412
PX		 2666 cur_start = base + mr->addr;
2667 cur_end = cur_start + MR_SIZE(mr->size);
2668
2669 /*
2670 * Try to detect overflow of memory region. This should never
2671 * happen normally. When it happens, we dump something to warn the
2672 * user who is observing this.
2673 */
2674 if (cur_start < base || cur_end < cur_start) {
2675 mon_printf(f, "[DETECTED OVERFLOW!] ");
2676 }
2677
314e2987
BS		 2678 if (mr->alias) {
2679 MemoryRegionList *ml;
2680 bool found = false;
2681
2682 /* check if the alias is already in the queue */
9479c57a 2683 QTAILQ_FOREACH(ml, alias_print_queue, queue) {
f54bb15f 2684 if (ml->mr == mr->alias) {
314e2987
BS		 2685 found = true;
2686 }
2687 }
2688
2689 if (!found) {
2690 ml = g_new(MemoryRegionList, 1);
2691 ml->mr = mr->alias;
9479c57a 2692 QTAILQ_INSERT_TAIL(alias_print_queue, ml, queue);
314e2987 2693 }
4896d74b 2694 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
4e831901 2695 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
f8a9f720 2696 "-" TARGET_FMT_plx "%s\n",
b31f8412 2697 cur_start, cur_end,
4b474ba7 2698 mr->priority,
4e831901 2699 memory_region_type((MemoryRegion *)mr),
3fb18b4d
PC		 2700 memory_region_name(mr),
2701 memory_region_name(mr->alias),
314e2987 2702 mr->alias_offset,
4e831901 2703 mr->alias_offset + MR_SIZE(mr->size),
f8a9f720 2704 mr->enabled ? "" : " [disabled]");
314e2987 2705 } else {
4896d74b 2706 mon_printf(f,
4e831901 2707 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
b31f8412 2708 cur_start, cur_end,
4b474ba7 2709 mr->priority,
4e831901 2710 memory_region_type((MemoryRegion *)mr),
f8a9f720
GH		 2711 memory_region_name(mr),
2712 mr->enabled ? "" : " [disabled]");
314e2987 2713 }
9479c57a
JK		 2714
2715 QTAILQ_INIT(&submr_print_queue);
2716
314e2987 2717 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK		 2718 new_ml = g_new(MemoryRegionList, 1);
2719 new_ml->mr = submr;
2720 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
2721 if (new_ml->mr->addr < ml->mr->addr ||
2722 (new_ml->mr->addr == ml->mr->addr &&
2723 new_ml->mr->priority > ml->mr->priority)) {
2724 QTAILQ_INSERT_BEFORE(ml, new_ml, queue);
2725 new_ml = NULL;
2726 break;
2727 }
2728 }
2729 if (new_ml) {
2730 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, queue);
2731 }
2732 }
2733
2734 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
b31f8412 2735 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
9479c57a
JK		 2736 alias_print_queue);
2737 }
2738
88365e47 2739 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, queue, next_ml) {
9479c57a 2740 g_free(ml);
314e2987
BS		 2741 }
2742}
2743
57bb40c9
PX		 2744static void mtree_print_flatview(fprintf_function p, void *f,
2745 AddressSpace *as)
2746{
2747 FlatView *view = address_space_get_flatview(as);
2748 FlatRange *range = &view->ranges[0];
2749 MemoryRegion *mr;
2750 int n = view->nr;
2751
2752 if (n <= 0) {
2753 p(f, MTREE_INDENT "No rendered FlatView for "
2754 "address space '%s'\n", as->name);
2755 flatview_unref(view);
2756 return;
2757 }
2758
2759 while (n--) {
2760 mr = range->mr;
377a07aa
PB		 2761 if (range->offset_in_region) {
2762 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2763 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
2764 int128_get64(range->addr.start),
2765 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2766 mr->priority,
2767 range->readonly ? "rom" : memory_region_type(mr),
2768 memory_region_name(mr),
2769 range->offset_in_region);
2770 } else {
2771 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2772 TARGET_FMT_plx " (prio %d, %s): %s\n",
2773 int128_get64(range->addr.start),
2774 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2775 mr->priority,
2776 range->readonly ? "rom" : memory_region_type(mr),
2777 memory_region_name(mr));
2778 }
57bb40c9
PX		 2779 range++;
2780 }
2781
2782 flatview_unref(view);
2783}
2784
2785void mtree_info(fprintf_function mon_printf, void *f, bool flatview)
314e2987
BS		 2786{
2787 MemoryRegionListHead ml_head;
2788 MemoryRegionList *ml, *ml2;
0d673e36 2789 AddressSpace *as;
314e2987 2790
57bb40c9
PX		 2791 if (flatview) {
2792 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2793 mon_printf(f, "address-space (flat view): %s\n", as->name);
2794 mtree_print_flatview(mon_printf, f, as);
2795 mon_printf(f, "\n");
2796 }
2797 return;
2798 }
2799
314e2987
BS		 2800 QTAILQ_INIT(&ml_head);
2801
0d673e36 2802 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
e48816aa
GH		 2803 mon_printf(f, "address-space: %s\n", as->name);
2804 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
2805 mon_printf(f, "\n");
b9f9be88
BS		 2806 }
2807
314e2987
BS		 2808 /* print aliased regions */
2809 QTAILQ_FOREACH(ml, &ml_head, queue) {
e48816aa
GH		 2810 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
2811 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
2812 mon_printf(f, "\n");
314e2987
BS		 2813 }
2814
2815 QTAILQ_FOREACH_SAFE(ml, &ml_head, queue, ml2) {
88365e47 2816 g_free(ml);
314e2987 2817 }
314e2987 2818}
b4fefef9
PC		 2819
2820static const TypeInfo memory_region_info = {
2821 .parent = TYPE_OBJECT,
2822 .name = TYPE_MEMORY_REGION,
2823 .instance_size = sizeof(MemoryRegion),
2824 .instance_init = memory_region_initfn,
2825 .instance_finalize = memory_region_finalize,
2826};
2827
2828static void memory_register_types(void)
2829{
2830 type_register_static(&memory_region_info);
2831}
2832
2833type_init(memory_register_types)
QEMU mirror