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CommitLineData
093bc2cd
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1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
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14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879
PB
18#include "qemu-common.h"
19#include "cpu.h"
022c62cb
PB
20#include "exec/memory.h"
21#include "exec/address-spaces.h"
22#include "exec/ioport.h"
409ddd01 23#include "qapi/visitor.h"
1de7afc9 24#include "qemu/bitops.h"
8c56c1a5 25#include "qemu/error-report.h"
2c9b15ca 26#include "qom/object.h"
0ab8ed18 27#include "trace-root.h"
093bc2cd 28
022c62cb 29#include "exec/memory-internal.h"
220c3ebd 30#include "exec/ram_addr.h"
8c56c1a5 31#include "sysemu/kvm.h"
e1c57ab8 32#include "sysemu/sysemu.h"
c9356746
FK
33#include "hw/misc/mmio_interface.h"
34#include "hw/qdev-properties.h"
b08199c6 35#include "migration/vmstate.h"
67d95c15 36
d197063f
PB
37//#define DEBUG_UNASSIGNED
38
22bde714
JK
39static unsigned memory_region_transaction_depth;
40static bool memory_region_update_pending;
4dc56152 41static bool ioeventfd_update_pending;
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42static bool global_dirty_log = false;
43
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44static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
45 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 46
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47static QTAILQ_HEAD(, AddressSpace) address_spaces
48 = QTAILQ_HEAD_INITIALIZER(address_spaces);
49
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50typedef struct AddrRange AddrRange;
51
8417cebf 52/*
c9cdaa3a 53 * Note that signed integers are needed for negative offsetting in aliases
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54 * (large MemoryRegion::alias_offset).
55 */
093bc2cd 56struct AddrRange {
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57 Int128 start;
58 Int128 size;
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59};
60
08dafab4 61static AddrRange addrrange_make(Int128 start, Int128 size)
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62{
63 return (AddrRange) { start, size };
64}
65
66static bool addrrange_equal(AddrRange r1, AddrRange r2)
67{
08dafab4 68 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
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69}
70
08dafab4 71static Int128 addrrange_end(AddrRange r)
093bc2cd 72{
08dafab4 73 return int128_add(r.start, r.size);
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74}
75
08dafab4 76static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 77{
08dafab4 78 int128_addto(&range.start, delta);
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79 return range;
80}
81
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82static bool addrrange_contains(AddrRange range, Int128 addr)
83{
84 return int128_ge(addr, range.start)
85 && int128_lt(addr, addrrange_end(range));
86}
87
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88static bool addrrange_intersects(AddrRange r1, AddrRange r2)
89{
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90 return addrrange_contains(r1, r2.start)
91 || addrrange_contains(r2, r1.start);
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92}
93
94static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
95{
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96 Int128 start = int128_max(r1.start, r2.start);
97 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
98 return addrrange_make(start, int128_sub(end, start));
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99}
100
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101enum ListenerDirection { Forward, Reverse };
102
7376e582 103#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
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104 do { \
105 MemoryListener *_listener; \
106 \
107 switch (_direction) { \
108 case Forward: \
109 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
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110 if (_listener->_callback) { \
111 _listener->_callback(_listener, ##_args); \
112 } \
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113 } \
114 break; \
115 case Reverse: \
116 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
117 memory_listeners, link) { \
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118 if (_listener->_callback) { \
119 _listener->_callback(_listener, ##_args); \
120 } \
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121 } \
122 break; \
123 default: \
124 abort(); \
125 } \
126 } while (0)
127
9a54635d 128#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
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129 do { \
130 MemoryListener *_listener; \
9a54635d 131 struct memory_listeners_as *list = &(_as)->listeners; \
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132 \
133 switch (_direction) { \
134 case Forward: \
9a54635d
PB
135 QTAILQ_FOREACH(_listener, list, link_as) { \
136 if (_listener->_callback) { \
7376e582
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137 _listener->_callback(_listener, _section, ##_args); \
138 } \
139 } \
140 break; \
141 case Reverse: \
9a54635d
PB
142 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
143 link_as) { \
144 if (_listener->_callback) { \
7376e582
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145 _listener->_callback(_listener, _section, ##_args); \
146 } \
147 } \
148 break; \
149 default: \
150 abort(); \
151 } \
152 } while (0)
153
dfde4e6e 154/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 155#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44
PB
156 do { \
157 MemoryRegionSection mrs = section_from_flat_range(fr, as); \
9a54635d 158 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 159 } while(0)
0e0d36b4 160
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161struct CoalescedMemoryRange {
162 AddrRange addr;
163 QTAILQ_ENTRY(CoalescedMemoryRange) link;
164};
165
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166struct MemoryRegionIoeventfd {
167 AddrRange addr;
168 bool match_data;
169 uint64_t data;
753d5e14 170 EventNotifier *e;
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171};
172
173static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
174 MemoryRegionIoeventfd b)
175{
08dafab4 176 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 177 return true;
08dafab4 178 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 179 return false;
08dafab4 180 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 181 return true;
08dafab4 182 } else if (int128_gt(a.addr.size, b.addr.size)) {
3e9d69e7
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183 return false;
184 } else if (a.match_data < b.match_data) {
185 return true;
186 } else if (a.match_data > b.match_data) {
187 return false;
188 } else if (a.match_data) {
189 if (a.data < b.data) {
190 return true;
191 } else if (a.data > b.data) {
192 return false;
193 }
194 }
753d5e14 195 if (a.e < b.e) {
3e9d69e7 196 return true;
753d5e14 197 } else if (a.e > b.e) {
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198 return false;
199 }
200 return false;
201}
202
203static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
204 MemoryRegionIoeventfd b)
205{
206 return !memory_region_ioeventfd_before(a, b)
207 && !memory_region_ioeventfd_before(b, a);
208}
209
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210typedef struct FlatRange FlatRange;
211typedef struct FlatView FlatView;
212
213/* Range of memory in the global map. Addresses are absolute. */
214struct FlatRange {
215 MemoryRegion *mr;
a8170e5e 216 hwaddr offset_in_region;
093bc2cd 217 AddrRange addr;
5a583347 218 uint8_t dirty_log_mask;
b138e654 219 bool romd_mode;
fb1cd6f9 220 bool readonly;
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221};
222
223/* Flattened global view of current active memory hierarchy. Kept in sorted
224 * order.
225 */
226struct FlatView {
374f2981 227 struct rcu_head rcu;
856d7245 228 unsigned ref;
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229 FlatRange *ranges;
230 unsigned nr;
231 unsigned nr_allocated;
232};
233
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234typedef struct AddressSpaceOps AddressSpaceOps;
235
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236#define FOR_EACH_FLAT_RANGE(var, view) \
237 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
238
9c1f8f44
PB
239static inline MemoryRegionSection
240section_from_flat_range(FlatRange *fr, AddressSpace *as)
241{
242 return (MemoryRegionSection) {
243 .mr = fr->mr,
244 .address_space = as,
245 .offset_within_region = fr->offset_in_region,
246 .size = fr->addr.size,
247 .offset_within_address_space = int128_get64(fr->addr.start),
248 .readonly = fr->readonly,
249 };
250}
251
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252static bool flatrange_equal(FlatRange *a, FlatRange *b)
253{
254 return a->mr == b->mr
255 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 256 && a->offset_in_region == b->offset_in_region
b138e654 257 && a->romd_mode == b->romd_mode
fb1cd6f9 258 && a->readonly == b->readonly;
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259}
260
261static void flatview_init(FlatView *view)
262{
856d7245 263 view->ref = 1;
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264 view->ranges = NULL;
265 view->nr = 0;
266 view->nr_allocated = 0;
267}
268
269/* Insert a range into a given position. Caller is responsible for maintaining
270 * sorting order.
271 */
272static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
273{
274 if (view->nr == view->nr_allocated) {
275 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 276 view->ranges = g_realloc(view->ranges,
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277 view->nr_allocated * sizeof(*view->ranges));
278 }
279 memmove(view->ranges + pos + 1, view->ranges + pos,
280 (view->nr - pos) * sizeof(FlatRange));
281 view->ranges[pos] = *range;
dfde4e6e 282 memory_region_ref(range->mr);
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283 ++view->nr;
284}
285
286static void flatview_destroy(FlatView *view)
287{
dfde4e6e
PB
288 int i;
289
290 for (i = 0; i < view->nr; i++) {
291 memory_region_unref(view->ranges[i].mr);
292 }
7267c094 293 g_free(view->ranges);
a9a0c06d 294 g_free(view);
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295}
296
447b0d0b 297static bool flatview_ref(FlatView *view)
856d7245 298{
447b0d0b 299 return atomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB
300}
301
302static void flatview_unref(FlatView *view)
303{
304 if (atomic_fetch_dec(&view->ref) == 1) {
305 flatview_destroy(view);
306 }
307}
308
3d8e6bf9
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309static bool can_merge(FlatRange *r1, FlatRange *r2)
310{
08dafab4 311 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 312 && r1->mr == r2->mr
08dafab4
AK
313 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
314 r1->addr.size),
315 int128_make64(r2->offset_in_region))
d0a9b5bc 316 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 317 && r1->romd_mode == r2->romd_mode
fb1cd6f9 318 && r1->readonly == r2->readonly;
3d8e6bf9
AK
319}
320
8508e024 321/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
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322static void flatview_simplify(FlatView *view)
323{
324 unsigned i, j;
325
326 i = 0;
327 while (i < view->nr) {
328 j = i + 1;
329 while (j < view->nr
330 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 331 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
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332 ++j;
333 }
334 ++i;
335 memmove(&view->ranges[i], &view->ranges[j],
336 (view->nr - j) * sizeof(view->ranges[j]));
337 view->nr -= j - i;
338 }
339}
340
e7342aa3
PB
341static bool memory_region_big_endian(MemoryRegion *mr)
342{
343#ifdef TARGET_WORDS_BIGENDIAN
344 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
345#else
346 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
347#endif
348}
349
e11ef3d1
PB
350static bool memory_region_wrong_endianness(MemoryRegion *mr)
351{
352#ifdef TARGET_WORDS_BIGENDIAN
353 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
354#else
355 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
356#endif
357}
358
359static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
360{
361 if (memory_region_wrong_endianness(mr)) {
362 switch (size) {
363 case 1:
364 break;
365 case 2:
366 *data = bswap16(*data);
367 break;
368 case 4:
369 *data = bswap32(*data);
370 break;
371 case 8:
372 *data = bswap64(*data);
373 break;
374 default:
375 abort();
376 }
377 }
378}
379
4779dc1d
HB
380static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
381{
382 MemoryRegion *root;
383 hwaddr abs_addr = offset;
384
385 abs_addr += mr->addr;
386 for (root = mr; root->container; ) {
387 root = root->container;
388 abs_addr += root->addr;
389 }
390
391 return abs_addr;
392}
393
5a68be94
HB
394static int get_cpu_index(void)
395{
396 if (current_cpu) {
397 return current_cpu->cpu_index;
398 }
399 return -1;
400}
401
cc05c43a
PM
402static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
403 hwaddr addr,
404 uint64_t *value,
405 unsigned size,
406 unsigned shift,
407 uint64_t mask,
408 MemTxAttrs attrs)
409{
410 uint64_t tmp;
411
412 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
23d92d68 413 if (mr->subpage) {
5a68be94 414 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
415 } else if (mr == &io_mem_notdirty) {
416 /* Accesses to code which has previously been translated into a TB show
417 * up in the MMIO path, as accesses to the io_mem_notdirty
418 * MemoryRegion. */
419 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
420 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
421 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 422 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 423 }
cc05c43a
PM
424 *value |= (tmp & mask) << shift;
425 return MEMTX_OK;
426}
427
428static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB
429 hwaddr addr,
430 uint64_t *value,
431 unsigned size,
432 unsigned shift,
cc05c43a
PM
433 uint64_t mask,
434 MemTxAttrs attrs)
ce5d2f33 435{
ce5d2f33
PB
436 uint64_t tmp;
437
cc05c43a 438 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 439 if (mr->subpage) {
5a68be94 440 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
441 } else if (mr == &io_mem_notdirty) {
442 /* Accesses to code which has previously been translated into a TB show
443 * up in the MMIO path, as accesses to the io_mem_notdirty
444 * MemoryRegion. */
445 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
446 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
447 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 448 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 449 }
ce5d2f33 450 *value |= (tmp & mask) << shift;
cc05c43a 451 return MEMTX_OK;
ce5d2f33
PB
452}
453
cc05c43a
PM
454static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
455 hwaddr addr,
456 uint64_t *value,
457 unsigned size,
458 unsigned shift,
459 uint64_t mask,
460 MemTxAttrs attrs)
164a4dcd 461{
cc05c43a
PM
462 uint64_t tmp = 0;
463 MemTxResult r;
164a4dcd 464
cc05c43a 465 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 466 if (mr->subpage) {
5a68be94 467 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
468 } else if (mr == &io_mem_notdirty) {
469 /* Accesses to code which has previously been translated into a TB show
470 * up in the MMIO path, as accesses to the io_mem_notdirty
471 * MemoryRegion. */
472 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
473 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
474 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 475 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 476 }
164a4dcd 477 *value |= (tmp & mask) << shift;
cc05c43a 478 return r;
164a4dcd
AK
479}
480
cc05c43a
PM
481static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
482 hwaddr addr,
483 uint64_t *value,
484 unsigned size,
485 unsigned shift,
486 uint64_t mask,
487 MemTxAttrs attrs)
ce5d2f33 488{
ce5d2f33
PB
489 uint64_t tmp;
490
491 tmp = (*value >> shift) & mask;
23d92d68 492 if (mr->subpage) {
5a68be94 493 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
494 } else if (mr == &io_mem_notdirty) {
495 /* Accesses to code which has previously been translated into a TB show
496 * up in the MMIO path, as accesses to the io_mem_notdirty
497 * MemoryRegion. */
498 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
499 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
500 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 501 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 502 }
ce5d2f33 503 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
cc05c43a 504 return MEMTX_OK;
ce5d2f33
PB
505}
506
cc05c43a
PM
507static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
508 hwaddr addr,
509 uint64_t *value,
510 unsigned size,
511 unsigned shift,
512 uint64_t mask,
513 MemTxAttrs attrs)
164a4dcd 514{
164a4dcd
AK
515 uint64_t tmp;
516
517 tmp = (*value >> shift) & mask;
23d92d68 518 if (mr->subpage) {
5a68be94 519 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
520 } else if (mr == &io_mem_notdirty) {
521 /* Accesses to code which has previously been translated into a TB show
522 * up in the MMIO path, as accesses to the io_mem_notdirty
523 * MemoryRegion. */
524 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
525 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
526 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 527 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 528 }
164a4dcd 529 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 530 return MEMTX_OK;
164a4dcd
AK
531}
532
cc05c43a
PM
533static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
534 hwaddr addr,
535 uint64_t *value,
536 unsigned size,
537 unsigned shift,
538 uint64_t mask,
539 MemTxAttrs attrs)
540{
541 uint64_t tmp;
542
cc05c43a 543 tmp = (*value >> shift) & mask;
23d92d68 544 if (mr->subpage) {
5a68be94 545 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
546 } else if (mr == &io_mem_notdirty) {
547 /* Accesses to code which has previously been translated into a TB show
548 * up in the MMIO path, as accesses to the io_mem_notdirty
549 * MemoryRegion. */
550 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
551 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
552 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 553 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 554 }
cc05c43a
PM
555 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
556}
557
558static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK
559 uint64_t *value,
560 unsigned size,
561 unsigned access_size_min,
562 unsigned access_size_max,
05e015f7
KF
563 MemTxResult (*access_fn)
564 (MemoryRegion *mr,
565 hwaddr addr,
566 uint64_t *value,
567 unsigned size,
568 unsigned shift,
569 uint64_t mask,
570 MemTxAttrs attrs),
cc05c43a
PM
571 MemoryRegion *mr,
572 MemTxAttrs attrs)
164a4dcd
AK
573{
574 uint64_t access_mask;
575 unsigned access_size;
576 unsigned i;
cc05c43a 577 MemTxResult r = MEMTX_OK;
164a4dcd
AK
578
579 if (!access_size_min) {
580 access_size_min = 1;
581 }
582 if (!access_size_max) {
583 access_size_max = 4;
584 }
ce5d2f33
PB
585
586 /* FIXME: support unaligned access? */
164a4dcd
AK
587 access_size = MAX(MIN(size, access_size_max), access_size_min);
588 access_mask = -1ULL >> (64 - access_size * 8);
e7342aa3
PB
589 if (memory_region_big_endian(mr)) {
590 for (i = 0; i < size; i += access_size) {
05e015f7 591 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 592 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB
593 }
594 } else {
595 for (i = 0; i < size; i += access_size) {
05e015f7 596 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 597 access_mask, attrs);
e7342aa3 598 }
164a4dcd 599 }
cc05c43a 600 return r;
164a4dcd
AK
601}
602
e2177955
AK
603static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
604{
0d673e36
AK
605 AddressSpace *as;
606
feca4ac1
PB
607 while (mr->container) {
608 mr = mr->container;
e2177955 609 }
0d673e36
AK
610 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
611 if (mr == as->root) {
612 return as;
613 }
e2177955 614 }
eed2bacf 615 return NULL;
e2177955
AK
616}
617
093bc2cd
AK
618/* Render a memory region into the global view. Ranges in @view obscure
619 * ranges in @mr.
620 */
621static void render_memory_region(FlatView *view,
622 MemoryRegion *mr,
08dafab4 623 Int128 base,
fb1cd6f9
AK
624 AddrRange clip,
625 bool readonly)
093bc2cd
AK
626{
627 MemoryRegion *subregion;
628 unsigned i;
a8170e5e 629 hwaddr offset_in_region;
08dafab4
AK
630 Int128 remain;
631 Int128 now;
093bc2cd
AK
632 FlatRange fr;
633 AddrRange tmp;
634
6bba19ba
AK
635 if (!mr->enabled) {
636 return;
637 }
638
08dafab4 639 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 640 readonly |= mr->readonly;
093bc2cd
AK
641
642 tmp = addrrange_make(base, mr->size);
643
644 if (!addrrange_intersects(tmp, clip)) {
645 return;
646 }
647
648 clip = addrrange_intersection(tmp, clip);
649
650 if (mr->alias) {
08dafab4
AK
651 int128_subfrom(&base, int128_make64(mr->alias->addr));
652 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 653 render_memory_region(view, mr->alias, base, clip, readonly);
093bc2cd
AK
654 return;
655 }
656
657 /* Render subregions in priority order. */
658 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 659 render_memory_region(view, subregion, base, clip, readonly);
093bc2cd
AK
660 }
661
14a3c10a 662 if (!mr->terminates) {
093bc2cd
AK
663 return;
664 }
665
08dafab4 666 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK
667 base = clip.start;
668 remain = clip.size;
669
2eb74e1a 670 fr.mr = mr;
6f6a5ef3 671 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 672 fr.romd_mode = mr->romd_mode;
2eb74e1a
PC
673 fr.readonly = readonly;
674
093bc2cd 675 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK
676 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
677 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK
678 continue;
679 }
08dafab4
AK
680 if (int128_lt(base, view->ranges[i].addr.start)) {
681 now = int128_min(remain,
682 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK
683 fr.offset_in_region = offset_in_region;
684 fr.addr = addrrange_make(base, now);
685 flatview_insert(view, i, &fr);
686 ++i;
08dafab4
AK
687 int128_addto(&base, now);
688 offset_in_region += int128_get64(now);
689 int128_subfrom(&remain, now);
093bc2cd 690 }
d26a8cae
AK
691 now = int128_sub(int128_min(int128_add(base, remain),
692 addrrange_end(view->ranges[i].addr)),
693 base);
694 int128_addto(&base, now);
695 offset_in_region += int128_get64(now);
696 int128_subfrom(&remain, now);
093bc2cd 697 }
08dafab4 698 if (int128_nz(remain)) {
093bc2cd
AK
699 fr.offset_in_region = offset_in_region;
700 fr.addr = addrrange_make(base, remain);
701 flatview_insert(view, i, &fr);
702 }
703}
704
705/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 706static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 707{
a9a0c06d 708 FlatView *view;
093bc2cd 709
a9a0c06d
PB
710 view = g_new(FlatView, 1);
711 flatview_init(view);
093bc2cd 712
83f3c251 713 if (mr) {
a9a0c06d 714 render_memory_region(view, mr, int128_zero(),
83f3c251
AK
715 addrrange_make(int128_zero(), int128_2_64()), false);
716 }
a9a0c06d 717 flatview_simplify(view);
093bc2cd
AK
718
719 return view;
720}
721
3e9d69e7
AK
722static void address_space_add_del_ioeventfds(AddressSpace *as,
723 MemoryRegionIoeventfd *fds_new,
724 unsigned fds_new_nb,
725 MemoryRegionIoeventfd *fds_old,
726 unsigned fds_old_nb)
727{
728 unsigned iold, inew;
80a1ea37
AK
729 MemoryRegionIoeventfd *fd;
730 MemoryRegionSection section;
3e9d69e7
AK
731
732 /* Generate a symmetric difference of the old and new fd sets, adding
733 * and deleting as necessary.
734 */
735
736 iold = inew = 0;
737 while (iold < fds_old_nb || inew < fds_new_nb) {
738 if (iold < fds_old_nb
739 && (inew == fds_new_nb
740 || memory_region_ioeventfd_before(fds_old[iold],
741 fds_new[inew]))) {
80a1ea37
AK
742 fd = &fds_old[iold];
743 section = (MemoryRegionSection) {
f6790af6 744 .address_space = as,
80a1ea37 745 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 746 .size = fd->addr.size,
80a1ea37 747 };
9a54635d 748 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 749 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
750 ++iold;
751 } else if (inew < fds_new_nb
752 && (iold == fds_old_nb
753 || memory_region_ioeventfd_before(fds_new[inew],
754 fds_old[iold]))) {
80a1ea37
AK
755 fd = &fds_new[inew];
756 section = (MemoryRegionSection) {
f6790af6 757 .address_space = as,
80a1ea37 758 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 759 .size = fd->addr.size,
80a1ea37 760 };
9a54635d 761 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 762 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
763 ++inew;
764 } else {
765 ++iold;
766 ++inew;
767 }
768 }
769}
770
856d7245
PB
771static FlatView *address_space_get_flatview(AddressSpace *as)
772{
773 FlatView *view;
774
374f2981 775 rcu_read_lock();
447b0d0b
PB
776 do {
777 view = atomic_rcu_read(&as->current_map);
778 /* If somebody has replaced as->current_map concurrently,
779 * flatview_ref returns false.
780 */
781 } while (!flatview_ref(view));
374f2981 782 rcu_read_unlock();
856d7245
PB
783 return view;
784}
785
3e9d69e7
AK
786static void address_space_update_ioeventfds(AddressSpace *as)
787{
99e86347 788 FlatView *view;
3e9d69e7
AK
789 FlatRange *fr;
790 unsigned ioeventfd_nb = 0;
791 MemoryRegionIoeventfd *ioeventfds = NULL;
792 AddrRange tmp;
793 unsigned i;
794
856d7245 795 view = address_space_get_flatview(as);
99e86347 796 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK
797 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
798 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK
799 int128_sub(fr->addr.start,
800 int128_make64(fr->offset_in_region)));
3e9d69e7
AK
801 if (addrrange_intersects(fr->addr, tmp)) {
802 ++ioeventfd_nb;
7267c094 803 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK
804 ioeventfd_nb * sizeof(*ioeventfds));
805 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
806 ioeventfds[ioeventfd_nb-1].addr = tmp;
807 }
808 }
809 }
810
811 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
812 as->ioeventfds, as->ioeventfd_nb);
813
7267c094 814 g_free(as->ioeventfds);
3e9d69e7
AK
815 as->ioeventfds = ioeventfds;
816 as->ioeventfd_nb = ioeventfd_nb;
856d7245 817 flatview_unref(view);
3e9d69e7
AK
818}
819
b8af1afb 820static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB
821 const FlatView *old_view,
822 const FlatView *new_view,
b8af1afb 823 bool adding)
093bc2cd 824{
093bc2cd
AK
825 unsigned iold, inew;
826 FlatRange *frold, *frnew;
093bc2cd
AK
827
828 /* Generate a symmetric difference of the old and new memory maps.
829 * Kill ranges in the old map, and instantiate ranges in the new map.
830 */
831 iold = inew = 0;
a9a0c06d
PB
832 while (iold < old_view->nr || inew < new_view->nr) {
833 if (iold < old_view->nr) {
834 frold = &old_view->ranges[iold];
093bc2cd
AK
835 } else {
836 frold = NULL;
837 }
a9a0c06d
PB
838 if (inew < new_view->nr) {
839 frnew = &new_view->ranges[inew];
093bc2cd
AK
840 } else {
841 frnew = NULL;
842 }
843
844 if (frold
845 && (!frnew
08dafab4
AK
846 || int128_lt(frold->addr.start, frnew->addr.start)
847 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 848 && !flatrange_equal(frold, frnew)))) {
41a6e477 849 /* In old but not in new, or in both but attributes changed. */
093bc2cd 850
b8af1afb 851 if (!adding) {
72e22d2f 852 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK
853 }
854
093bc2cd
AK
855 ++iold;
856 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 857 /* In both and unchanged (except logging may have changed) */
093bc2cd 858
b8af1afb 859 if (adding) {
50c1e149 860 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB
861 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
862 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
863 frold->dirty_log_mask,
864 frnew->dirty_log_mask);
865 }
866 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
867 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
868 frold->dirty_log_mask,
869 frnew->dirty_log_mask);
b8af1afb 870 }
5a583347
AK
871 }
872
093bc2cd
AK
873 ++iold;
874 ++inew;
093bc2cd
AK
875 } else {
876 /* In new */
877
b8af1afb 878 if (adding) {
72e22d2f 879 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK
880 }
881
093bc2cd
AK
882 ++inew;
883 }
884 }
b8af1afb
AK
885}
886
b8af1afb
AK
887static void address_space_update_topology(AddressSpace *as)
888{
856d7245 889 FlatView *old_view = address_space_get_flatview(as);
a9a0c06d 890 FlatView *new_view = generate_memory_topology(as->root);
9a62e24f 891 int i;
b8af1afb 892
9a62e24f
AK
893 mem_begin(as);
894 for (i = 0; i < new_view->nr; i++) {
895 MemoryRegionSection mrs =
896 section_from_flat_range(&new_view->ranges[i], as);
897 mem_add(as, &mrs);
898 }
899 mem_commit(as);
900
901 if (!QTAILQ_EMPTY(&as->listeners)) {
902 address_space_update_topology_pass(as, old_view, new_view, false);
903 address_space_update_topology_pass(as, old_view, new_view, true);
904 }
b8af1afb 905
374f2981
PB
906 /* Writes are protected by the BQL. */
907 atomic_rcu_set(&as->current_map, new_view);
908 call_rcu(old_view, flatview_unref, rcu);
856d7245
PB
909
910 /* Note that all the old MemoryRegions are still alive up to this
911 * point. This relieves most MemoryListeners from the need to
912 * ref/unref the MemoryRegions they get---unless they use them
913 * outside the iothread mutex, in which case precise reference
914 * counting is necessary.
915 */
916 flatview_unref(old_view);
917
3e9d69e7 918 address_space_update_ioeventfds(as);
093bc2cd
AK
919}
920
4ef4db86
AK
921void memory_region_transaction_begin(void)
922{
bb880ded 923 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK
924 ++memory_region_transaction_depth;
925}
926
927void memory_region_transaction_commit(void)
928{
0d673e36
AK
929 AddressSpace *as;
930
4ef4db86 931 assert(memory_region_transaction_depth);
8d04fb55
JK
932 assert(qemu_mutex_iothread_locked());
933
4ef4db86 934 --memory_region_transaction_depth;
4dc56152
GA
935 if (!memory_region_transaction_depth) {
936 if (memory_region_update_pending) {
937 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 938
4dc56152
GA
939 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
940 address_space_update_topology(as);
941 }
ade9c1aa 942 memory_region_update_pending = false;
4dc56152
GA
943 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
944 } else if (ioeventfd_update_pending) {
945 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
946 address_space_update_ioeventfds(as);
947 }
ade9c1aa 948 ioeventfd_update_pending = false;
4dc56152 949 }
4dc56152 950 }
4ef4db86
AK
951}
952
545e92e0
AK
953static void memory_region_destructor_none(MemoryRegion *mr)
954{
955}
956
957static void memory_region_destructor_ram(MemoryRegion *mr)
958{
f1060c55 959 qemu_ram_free(mr->ram_block);
545e92e0
AK
960}
961
b4fefef9
PC
962static bool memory_region_need_escape(char c)
963{
964 return c == '/' || c == '[' || c == '\\' || c == ']';
965}
966
967static char *memory_region_escape_name(const char *name)
968{
969 const char *p;
970 char *escaped, *q;
971 uint8_t c;
972 size_t bytes = 0;
973
974 for (p = name; *p; p++) {
975 bytes += memory_region_need_escape(*p) ? 4 : 1;
976 }
977 if (bytes == p - name) {
978 return g_memdup(name, bytes + 1);
979 }
980
981 escaped = g_malloc(bytes + 1);
982 for (p = name, q = escaped; *p; p++) {
983 c = *p;
984 if (unlikely(memory_region_need_escape(c))) {
985 *q++ = '\\';
986 *q++ = 'x';
987 *q++ = "0123456789abcdef"[c >> 4];
988 c = "0123456789abcdef"[c & 15];
989 }
990 *q++ = c;
991 }
992 *q = 0;
993 return escaped;
994}
995
3df9d748
AK
996static void memory_region_do_init(MemoryRegion *mr,
997 Object *owner,
998 const char *name,
999 uint64_t size)
093bc2cd 1000{
08dafab4
AK
1001 mr->size = int128_make64(size);
1002 if (size == UINT64_MAX) {
1003 mr->size = int128_2_64();
1004 }
302fa283 1005 mr->name = g_strdup(name);
612263cf 1006 mr->owner = owner;
58eaa217 1007 mr->ram_block = NULL;
b4fefef9
PC
1008
1009 if (name) {
843ef73a
PC
1010 char *escaped_name = memory_region_escape_name(name);
1011 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB
1012
1013 if (!owner) {
1014 owner = container_get(qdev_get_machine(), "/unattached");
1015 }
1016
843ef73a 1017 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1018 object_unref(OBJECT(mr));
843ef73a
PC
1019 g_free(name_array);
1020 g_free(escaped_name);
b4fefef9
PC
1021 }
1022}
1023
3df9d748
AK
1024void memory_region_init(MemoryRegion *mr,
1025 Object *owner,
1026 const char *name,
1027 uint64_t size)
1028{
1029 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1030 memory_region_do_init(mr, owner, name, size);
1031}
1032
d7bce999
EB
1033static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1034 void *opaque, Error **errp)
409ddd01
PC
1035{
1036 MemoryRegion *mr = MEMORY_REGION(obj);
1037 uint64_t value = mr->addr;
1038
51e72bc1 1039 visit_type_uint64(v, name, &value, errp);
409ddd01
PC
1040}
1041
d7bce999
EB
1042static void memory_region_get_container(Object *obj, Visitor *v,
1043 const char *name, void *opaque,
1044 Error **errp)
409ddd01
PC
1045{
1046 MemoryRegion *mr = MEMORY_REGION(obj);
1047 gchar *path = (gchar *)"";
1048
1049 if (mr->container) {
1050 path = object_get_canonical_path(OBJECT(mr->container));
1051 }
51e72bc1 1052 visit_type_str(v, name, &path, errp);
409ddd01
PC
1053 if (mr->container) {
1054 g_free(path);
1055 }
1056}
1057
1058static Object *memory_region_resolve_container(Object *obj, void *opaque,
1059 const char *part)
1060{
1061 MemoryRegion *mr = MEMORY_REGION(obj);
1062
1063 return OBJECT(mr->container);
1064}
1065
d7bce999
EB
1066static void memory_region_get_priority(Object *obj, Visitor *v,
1067 const char *name, void *opaque,
1068 Error **errp)
d33382da
PC
1069{
1070 MemoryRegion *mr = MEMORY_REGION(obj);
1071 int32_t value = mr->priority;
1072
51e72bc1 1073 visit_type_int32(v, name, &value, errp);
d33382da
PC
1074}
1075
d7bce999
EB
1076static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1077 void *opaque, Error **errp)
52aef7bb
PC
1078{
1079 MemoryRegion *mr = MEMORY_REGION(obj);
1080 uint64_t value = memory_region_size(mr);
1081
51e72bc1 1082 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC
1083}
1084
b4fefef9
PC
1085static void memory_region_initfn(Object *obj)
1086{
1087 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1088 ObjectProperty *op;
b4fefef9
PC
1089
1090 mr->ops = &unassigned_mem_ops;
6bba19ba 1091 mr->enabled = true;
5f9a5ea1 1092 mr->romd_mode = true;
196ea131 1093 mr->global_locking = true;
545e92e0 1094 mr->destructor = memory_region_destructor_none;
093bc2cd 1095 QTAILQ_INIT(&mr->subregions);
093bc2cd 1096 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC
1097
1098 op = object_property_add(OBJECT(mr), "container",
1099 "link<" TYPE_MEMORY_REGION ">",
1100 memory_region_get_container,
1101 NULL, /* memory_region_set_container */
1102 NULL, NULL, &error_abort);
1103 op->resolve = memory_region_resolve_container;
1104
1105 object_property_add(OBJECT(mr), "addr", "uint64",
1106 memory_region_get_addr,
1107 NULL, /* memory_region_set_addr */
1108 NULL, NULL, &error_abort);
d33382da
PC
1109 object_property_add(OBJECT(mr), "priority", "uint32",
1110 memory_region_get_priority,
1111 NULL, /* memory_region_set_priority */
1112 NULL, NULL, &error_abort);
52aef7bb
PC
1113 object_property_add(OBJECT(mr), "size", "uint64",
1114 memory_region_get_size,
1115 NULL, /* memory_region_set_size, */
1116 NULL, NULL, &error_abort);
093bc2cd
AK
1117}
1118
3df9d748
AK
1119static void iommu_memory_region_initfn(Object *obj)
1120{
1121 MemoryRegion *mr = MEMORY_REGION(obj);
1122
1123 mr->is_iommu = true;
1124}
1125
b018ddf6
PB
1126static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1127 unsigned size)
1128{
1129#ifdef DEBUG_UNASSIGNED
1130 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1131#endif
4917cf44
AF
1132 if (current_cpu != NULL) {
1133 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
c658b94f 1134 }
68a7439a 1135 return 0;
b018ddf6
PB
1136}
1137
1138static void unassigned_mem_write(void *opaque, hwaddr addr,
1139 uint64_t val, unsigned size)
1140{
1141#ifdef DEBUG_UNASSIGNED
1142 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1143#endif
4917cf44
AF
1144 if (current_cpu != NULL) {
1145 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1146 }
b018ddf6
PB
1147}
1148
d197063f
PB
1149static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1150 unsigned size, bool is_write)
1151{
1152 return false;
1153}
1154
1155const MemoryRegionOps unassigned_mem_ops = {
1156 .valid.accepts = unassigned_mem_accepts,
1157 .endianness = DEVICE_NATIVE_ENDIAN,
1158};
1159
4a2e242b
AW
1160static uint64_t memory_region_ram_device_read(void *opaque,
1161 hwaddr addr, unsigned size)
1162{
1163 MemoryRegion *mr = opaque;
1164 uint64_t data = (uint64_t)~0;
1165
1166 switch (size) {
1167 case 1:
1168 data = *(uint8_t *)(mr->ram_block->host + addr);
1169 break;
1170 case 2:
1171 data = *(uint16_t *)(mr->ram_block->host + addr);
1172 break;
1173 case 4:
1174 data = *(uint32_t *)(mr->ram_block->host + addr);
1175 break;
1176 case 8:
1177 data = *(uint64_t *)(mr->ram_block->host + addr);
1178 break;
1179 }
1180
1181 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1182
1183 return data;
1184}
1185
1186static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1187 uint64_t data, unsigned size)
1188{
1189 MemoryRegion *mr = opaque;
1190
1191 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1192
1193 switch (size) {
1194 case 1:
1195 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1196 break;
1197 case 2:
1198 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1199 break;
1200 case 4:
1201 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1202 break;
1203 case 8:
1204 *(uint64_t *)(mr->ram_block->host + addr) = data;
1205 break;
1206 }
1207}
1208
1209static const MemoryRegionOps ram_device_mem_ops = {
1210 .read = memory_region_ram_device_read,
1211 .write = memory_region_ram_device_write,
c99a29e7 1212 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW
1213 .valid = {
1214 .min_access_size = 1,
1215 .max_access_size = 8,
1216 .unaligned = true,
1217 },
1218 .impl = {
1219 .min_access_size = 1,
1220 .max_access_size = 8,
1221 .unaligned = true,
1222 },
1223};
1224
d2702032
PB
1225bool memory_region_access_valid(MemoryRegion *mr,
1226 hwaddr addr,
1227 unsigned size,
1228 bool is_write)
093bc2cd 1229{
a014ed07
PB
1230 int access_size_min, access_size_max;
1231 int access_size, i;
897fa7cf 1232
093bc2cd
AK
1233 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1234 return false;
1235 }
1236
a014ed07 1237 if (!mr->ops->valid.accepts) {
093bc2cd
AK
1238 return true;
1239 }
1240
a014ed07
PB
1241 access_size_min = mr->ops->valid.min_access_size;
1242 if (!mr->ops->valid.min_access_size) {
1243 access_size_min = 1;
1244 }
1245
1246 access_size_max = mr->ops->valid.max_access_size;
1247 if (!mr->ops->valid.max_access_size) {
1248 access_size_max = 4;
1249 }
1250
1251 access_size = MAX(MIN(size, access_size_max), access_size_min);
1252 for (i = 0; i < size; i += access_size) {
1253 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1254 is_write)) {
1255 return false;
1256 }
093bc2cd 1257 }
a014ed07 1258
093bc2cd
AK
1259 return true;
1260}
1261
cc05c43a
PM
1262static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1263 hwaddr addr,
1264 uint64_t *pval,
1265 unsigned size,
1266 MemTxAttrs attrs)
093bc2cd 1267{
cc05c43a 1268 *pval = 0;
093bc2cd 1269
ce5d2f33 1270 if (mr->ops->read) {
cc05c43a
PM
1271 return access_with_adjusted_size(addr, pval, size,
1272 mr->ops->impl.min_access_size,
1273 mr->ops->impl.max_access_size,
1274 memory_region_read_accessor,
1275 mr, attrs);
1276 } else if (mr->ops->read_with_attrs) {
1277 return access_with_adjusted_size(addr, pval, size,
1278 mr->ops->impl.min_access_size,
1279 mr->ops->impl.max_access_size,
1280 memory_region_read_with_attrs_accessor,
1281 mr, attrs);
ce5d2f33 1282 } else {
cc05c43a
PM
1283 return access_with_adjusted_size(addr, pval, size, 1, 4,
1284 memory_region_oldmmio_read_accessor,
1285 mr, attrs);
74901c3b 1286 }
093bc2cd
AK
1287}
1288
3b643495
PM
1289MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1290 hwaddr addr,
1291 uint64_t *pval,
1292 unsigned size,
1293 MemTxAttrs attrs)
a621f38d 1294{
cc05c43a
PM
1295 MemTxResult r;
1296
791af8c8
PB
1297 if (!memory_region_access_valid(mr, addr, size, false)) {
1298 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1299 return MEMTX_DECODE_ERROR;
791af8c8 1300 }
a621f38d 1301
cc05c43a 1302 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1303 adjust_endianness(mr, pval, size);
cc05c43a 1304 return r;
a621f38d 1305}
093bc2cd 1306
8c56c1a5
PF
1307/* Return true if an eventfd was signalled */
1308static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1309 hwaddr addr,
1310 uint64_t data,
1311 unsigned size,
1312 MemTxAttrs attrs)
1313{
1314 MemoryRegionIoeventfd ioeventfd = {
1315 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1316 .data = data,
1317 };
1318 unsigned i;
1319
1320 for (i = 0; i < mr->ioeventfd_nb; i++) {
1321 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1322 ioeventfd.e = mr->ioeventfds[i].e;
1323
1324 if (memory_region_ioeventfd_equal(ioeventfd, mr->ioeventfds[i])) {
1325 event_notifier_set(ioeventfd.e);
1326 return true;
1327 }
1328 }
1329
1330 return false;
1331}
1332
3b643495
PM
1333MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1334 hwaddr addr,
1335 uint64_t data,
1336 unsigned size,
1337 MemTxAttrs attrs)
a621f38d 1338{
897fa7cf 1339 if (!memory_region_access_valid(mr, addr, size, true)) {
b018ddf6 1340 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1341 return MEMTX_DECODE_ERROR;
093bc2cd
AK
1342 }
1343
a621f38d
AK
1344 adjust_endianness(mr, &data, size);
1345
8c56c1a5
PF
1346 if ((!kvm_eventfds_enabled()) &&
1347 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1348 return MEMTX_OK;
1349 }
1350
ce5d2f33 1351 if (mr->ops->write) {
cc05c43a
PM
1352 return access_with_adjusted_size(addr, &data, size,
1353 mr->ops->impl.min_access_size,
1354 mr->ops->impl.max_access_size,
1355 memory_region_write_accessor, mr,
1356 attrs);
1357 } else if (mr->ops->write_with_attrs) {
1358 return
1359 access_with_adjusted_size(addr, &data, size,
1360 mr->ops->impl.min_access_size,
1361 mr->ops->impl.max_access_size,
1362 memory_region_write_with_attrs_accessor,
1363 mr, attrs);
ce5d2f33 1364 } else {
cc05c43a
PM
1365 return access_with_adjusted_size(addr, &data, size, 1, 4,
1366 memory_region_oldmmio_write_accessor,
1367 mr, attrs);
74901c3b 1368 }
093bc2cd
AK
1369}
1370
093bc2cd 1371void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1372 Object *owner,
093bc2cd
AK
1373 const MemoryRegionOps *ops,
1374 void *opaque,
1375 const char *name,
1376 uint64_t size)
1377{
2c9b15ca 1378 memory_region_init(mr, owner, name, size);
6d6d2abf 1379 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1380 mr->opaque = opaque;
14a3c10a 1381 mr->terminates = true;
093bc2cd
AK
1382}
1383
1cfe48c1
PM
1384void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1385 Object *owner,
1386 const char *name,
1387 uint64_t size,
1388 Error **errp)
093bc2cd 1389{
2c9b15ca 1390 memory_region_init(mr, owner, name, size);
8ea9252a 1391 mr->ram = true;
14a3c10a 1392 mr->terminates = true;
545e92e0 1393 mr->destructor = memory_region_destructor_ram;
8e41fb63 1394 mr->ram_block = qemu_ram_alloc(size, mr, errp);
677e7805 1395 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
0b183fc8
PB
1396}
1397
60786ef3
MT
1398void memory_region_init_resizeable_ram(MemoryRegion *mr,
1399 Object *owner,
1400 const char *name,
1401 uint64_t size,
1402 uint64_t max_size,
1403 void (*resized)(const char*,
1404 uint64_t length,
1405 void *host),
1406 Error **errp)
1407{
1408 memory_region_init(mr, owner, name, size);
1409 mr->ram = true;
1410 mr->terminates = true;
1411 mr->destructor = memory_region_destructor_ram;
8e41fb63
FZ
1412 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1413 mr, errp);
677e7805 1414 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
60786ef3
MT
1415}
1416
0b183fc8
PB
1417#ifdef __linux__
1418void memory_region_init_ram_from_file(MemoryRegion *mr,
1419 struct Object *owner,
1420 const char *name,
1421 uint64_t size,
dbcb8981 1422 bool share,
7f56e740
PB
1423 const char *path,
1424 Error **errp)
0b183fc8
PB
1425{
1426 memory_region_init(mr, owner, name, size);
1427 mr->ram = true;
1428 mr->terminates = true;
1429 mr->destructor = memory_region_destructor_ram;
8e41fb63 1430 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
677e7805 1431 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
093bc2cd 1432}
fea617c5
MAL
1433
1434void memory_region_init_ram_from_fd(MemoryRegion *mr,
1435 struct Object *owner,
1436 const char *name,
1437 uint64_t size,
1438 bool share,
1439 int fd,
1440 Error **errp)
1441{
1442 memory_region_init(mr, owner, name, size);
1443 mr->ram = true;
1444 mr->terminates = true;
1445 mr->destructor = memory_region_destructor_ram;
1446 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1447 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1448}
0b183fc8 1449#endif
093bc2cd
AK
1450
1451void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1452 Object *owner,
093bc2cd
AK
1453 const char *name,
1454 uint64_t size,
1455 void *ptr)
1456{
2c9b15ca 1457 memory_region_init(mr, owner, name, size);
8ea9252a 1458 mr->ram = true;
14a3c10a 1459 mr->terminates = true;
fc3e7665 1460 mr->destructor = memory_region_destructor_ram;
677e7805 1461 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT
1462
1463 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1464 assert(ptr != NULL);
8e41fb63 1465 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK
1466}
1467
21e00fa5
AW
1468void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1469 Object *owner,
1470 const char *name,
1471 uint64_t size,
1472 void *ptr)
e4dc3f59 1473{
21e00fa5
AW
1474 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1475 mr->ram_device = true;
4a2e242b
AW
1476 mr->ops = &ram_device_mem_ops;
1477 mr->opaque = mr;
e4dc3f59
ND
1478}
1479
093bc2cd 1480void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1481 Object *owner,
093bc2cd
AK
1482 const char *name,
1483 MemoryRegion *orig,
a8170e5e 1484 hwaddr offset,
093bc2cd
AK
1485 uint64_t size)
1486{
2c9b15ca 1487 memory_region_init(mr, owner, name, size);
093bc2cd
AK
1488 mr->alias = orig;
1489 mr->alias_offset = offset;
1490}
1491
b59821a9
PM
1492void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1493 struct Object *owner,
1494 const char *name,
1495 uint64_t size,
1496 Error **errp)
a1777f7f
PM
1497{
1498 memory_region_init(mr, owner, name, size);
1499 mr->ram = true;
1500 mr->readonly = true;
1501 mr->terminates = true;
1502 mr->destructor = memory_region_destructor_ram;
1503 mr->ram_block = qemu_ram_alloc(size, mr, errp);
1504 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1505}
1506
b59821a9
PM
1507void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1508 Object *owner,
1509 const MemoryRegionOps *ops,
1510 void *opaque,
1511 const char *name,
1512 uint64_t size,
1513 Error **errp)
d0a9b5bc 1514{
39e0b03d 1515 assert(ops);
2c9b15ca 1516 memory_region_init(mr, owner, name, size);
7bc2b9cd 1517 mr->ops = ops;
75f5941c 1518 mr->opaque = opaque;
d0a9b5bc 1519 mr->terminates = true;
75c578dc 1520 mr->rom_device = true;
58268c8d 1521 mr->destructor = memory_region_destructor_ram;
8e41fb63 1522 mr->ram_block = qemu_ram_alloc(size, mr, errp);
d0a9b5bc
AK
1523}
1524
1221a474
AK
1525void memory_region_init_iommu(void *_iommu_mr,
1526 size_t instance_size,
1527 const char *mrtypename,
2c9b15ca 1528 Object *owner,
30951157
AK
1529 const char *name,
1530 uint64_t size)
1531{
1221a474 1532 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK
1533 struct MemoryRegion *mr;
1534
1221a474
AK
1535 object_initialize(_iommu_mr, instance_size, mrtypename);
1536 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK
1537 memory_region_do_init(mr, owner, name, size);
1538 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1539 mr->terminates = true; /* then re-forwards */
3df9d748
AK
1540 QLIST_INIT(&iommu_mr->iommu_notify);
1541 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK
1542}
1543
b4fefef9 1544static void memory_region_finalize(Object *obj)
093bc2cd 1545{
b4fefef9
PC
1546 MemoryRegion *mr = MEMORY_REGION(obj);
1547
2e2b8eb7
PB
1548 assert(!mr->container);
1549
1550 /* We know the region is not visible in any address space (it
1551 * does not have a container and cannot be a root either because
1552 * it has no references, so we can blindly clear mr->enabled.
1553 * memory_region_set_enabled instead could trigger a transaction
1554 * and cause an infinite loop.
1555 */
1556 mr->enabled = false;
1557 memory_region_transaction_begin();
1558 while (!QTAILQ_EMPTY(&mr->subregions)) {
1559 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1560 memory_region_del_subregion(mr, subregion);
1561 }
1562 memory_region_transaction_commit();
1563
545e92e0 1564 mr->destructor(mr);
093bc2cd 1565 memory_region_clear_coalescing(mr);
302fa283 1566 g_free((char *)mr->name);
7267c094 1567 g_free(mr->ioeventfds);
093bc2cd
AK
1568}
1569
803c0816
PB
1570Object *memory_region_owner(MemoryRegion *mr)
1571{
22a893e4
PB
1572 Object *obj = OBJECT(mr);
1573 return obj->parent;
803c0816
PB
1574}
1575
46637be2
PB
1576void memory_region_ref(MemoryRegion *mr)
1577{
22a893e4
PB
1578 /* MMIO callbacks most likely will access data that belongs
1579 * to the owner, hence the need to ref/unref the owner whenever
1580 * the memory region is in use.
1581 *
1582 * The memory region is a child of its owner. As long as the
1583 * owner doesn't call unparent itself on the memory region,
1584 * ref-ing the owner will also keep the memory region alive.
612263cf
PB
1585 * Memory regions without an owner are supposed to never go away;
1586 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1587 */
612263cf
PB
1588 if (mr && mr->owner) {
1589 object_ref(mr->owner);
46637be2
PB
1590 }
1591}
1592
1593void memory_region_unref(MemoryRegion *mr)
1594{
612263cf
PB
1595 if (mr && mr->owner) {
1596 object_unref(mr->owner);
46637be2
PB
1597 }
1598}
1599
093bc2cd
AK
1600uint64_t memory_region_size(MemoryRegion *mr)
1601{
08dafab4
AK
1602 if (int128_eq(mr->size, int128_2_64())) {
1603 return UINT64_MAX;
1604 }
1605 return int128_get64(mr->size);
093bc2cd
AK
1606}
1607
5d546d4b 1608const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1609{
d1dd32af
PC
1610 if (!mr->name) {
1611 ((MemoryRegion *)mr)->name =
1612 object_get_canonical_path_component(OBJECT(mr));
1613 }
302fa283 1614 return mr->name;
8991c79b
AK
1615}
1616
21e00fa5 1617bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1618{
21e00fa5 1619 return mr->ram_device;
e4dc3f59
ND
1620}
1621
2d1a35be 1622uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1623{
6f6a5ef3 1624 uint8_t mask = mr->dirty_log_mask;
adaad61c 1625 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB
1626 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1627 }
1628 return mask;
55043ba3
AK
1629}
1630
2d1a35be
PB
1631bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1632{
1633 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1634}
1635
3df9d748 1636static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
5bf3d319
PX
1637{
1638 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1639 IOMMUNotifier *iommu_notifier;
1221a474 1640 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
5bf3d319 1641
3df9d748 1642 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX
1643 flags |= iommu_notifier->notifier_flags;
1644 }
1645
1221a474
AK
1646 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1647 imrc->notify_flag_changed(iommu_mr,
1648 iommu_mr->iommu_notify_flags,
1649 flags);
5bf3d319
PX
1650 }
1651
3df9d748 1652 iommu_mr->iommu_notify_flags = flags;
5bf3d319
PX
1653}
1654
cdb30812
PX
1655void memory_region_register_iommu_notifier(MemoryRegion *mr,
1656 IOMMUNotifier *n)
06866575 1657{
3df9d748
AK
1658 IOMMUMemoryRegion *iommu_mr;
1659
efcd38c5
JW
1660 if (mr->alias) {
1661 memory_region_register_iommu_notifier(mr->alias, n);
1662 return;
1663 }
1664
cdb30812 1665 /* We need to register for at least one bitfield */
3df9d748 1666 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1667 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1668 assert(n->start <= n->end);
3df9d748
AK
1669 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1670 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1671}
1672
3df9d748 1673uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1674{
1221a474
AK
1675 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1676
1677 if (imrc->get_min_page_size) {
1678 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK
1679 }
1680 return TARGET_PAGE_SIZE;
1681}
1682
3df9d748 1683void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1684{
3df9d748 1685 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1686 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1687 hwaddr addr, granularity;
a788f227
DG
1688 IOMMUTLBEntry iotlb;
1689
faa362e3 1690 /* If the IOMMU has its own replay callback, override */
1221a474
AK
1691 if (imrc->replay) {
1692 imrc->replay(iommu_mr, n);
faa362e3
PX
1693 return;
1694 }
1695
3df9d748 1696 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1697
a788f227 1698 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1221a474 1699 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE);
a788f227
DG
1700 if (iotlb.perm != IOMMU_NONE) {
1701 n->notify(n, &iotlb);
1702 }
1703
1704 /* if (2^64 - MR size) < granularity, it's possible to get an
1705 * infinite loop here. This should catch such a wraparound */
1706 if ((addr + granularity) < addr) {
1707 break;
1708 }
1709 }
1710}
1711
3df9d748 1712void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
de472e4a
PX
1713{
1714 IOMMUNotifier *notifier;
1715
3df9d748
AK
1716 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1717 memory_region_iommu_replay(iommu_mr, notifier);
de472e4a
PX
1718 }
1719}
1720
cdb30812
PX
1721void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1722 IOMMUNotifier *n)
06866575 1723{
3df9d748
AK
1724 IOMMUMemoryRegion *iommu_mr;
1725
efcd38c5
JW
1726 if (mr->alias) {
1727 memory_region_unregister_iommu_notifier(mr->alias, n);
1728 return;
1729 }
cdb30812 1730 QLIST_REMOVE(n, node);
3df9d748
AK
1731 iommu_mr = IOMMU_MEMORY_REGION(mr);
1732 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1733}
1734
bd2bfa4c
PX
1735void memory_region_notify_one(IOMMUNotifier *notifier,
1736 IOMMUTLBEntry *entry)
06866575 1737{
cdb30812
PX
1738 IOMMUNotifierFlag request_flags;
1739
bd2bfa4c
PX
1740 /*
1741 * Skip the notification if the notification does not overlap
1742 * with registered range.
1743 */
1744 if (notifier->start > entry->iova + entry->addr_mask + 1 ||
1745 notifier->end < entry->iova) {
1746 return;
1747 }
cdb30812 1748
bd2bfa4c 1749 if (entry->perm & IOMMU_RW) {
cdb30812
PX
1750 request_flags = IOMMU_NOTIFIER_MAP;
1751 } else {
1752 request_flags = IOMMU_NOTIFIER_UNMAP;
1753 }
1754
bd2bfa4c
PX
1755 if (notifier->notifier_flags & request_flags) {
1756 notifier->notify(notifier, entry);
1757 }
1758}
1759
3df9d748 1760void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
bd2bfa4c
PX
1761 IOMMUTLBEntry entry)
1762{
1763 IOMMUNotifier *iommu_notifier;
1764
3df9d748 1765 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1766
3df9d748 1767 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
bd2bfa4c 1768 memory_region_notify_one(iommu_notifier, &entry);
cdb30812 1769 }
06866575
DG
1770}
1771
093bc2cd
AK
1772void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1773{
5a583347 1774 uint8_t mask = 1 << client;
deb809ed 1775 uint8_t old_logging;
5a583347 1776
dbddac6d 1777 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB
1778 old_logging = mr->vga_logging_count;
1779 mr->vga_logging_count += log ? 1 : -1;
1780 if (!!old_logging == !!mr->vga_logging_count) {
1781 return;
1782 }
1783
59023ef4 1784 memory_region_transaction_begin();
5a583347 1785 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1786 memory_region_update_pending |= mr->enabled;
59023ef4 1787 memory_region_transaction_commit();
093bc2cd
AK
1788}
1789
a8170e5e
AK
1790bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1791 hwaddr size, unsigned client)
093bc2cd 1792{
8e41fb63
FZ
1793 assert(mr->ram_block);
1794 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1795 size, client);
093bc2cd
AK
1796}
1797
a8170e5e
AK
1798void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1799 hwaddr size)
093bc2cd 1800{
8e41fb63
FZ
1801 assert(mr->ram_block);
1802 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1803 size,
58d2707e 1804 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK
1805}
1806
6c279db8
JQ
1807bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1808 hwaddr size, unsigned client)
1809{
8e41fb63
FZ
1810 assert(mr->ram_block);
1811 return cpu_physical_memory_test_and_clear_dirty(
1812 memory_region_get_ram_addr(mr) + addr, size, client);
6c279db8
JQ
1813}
1814
8deaf12c
GH
1815DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
1816 hwaddr addr,
1817 hwaddr size,
1818 unsigned client)
1819{
1820 assert(mr->ram_block);
1821 return cpu_physical_memory_snapshot_and_clear_dirty(
1822 memory_region_get_ram_addr(mr) + addr, size, client);
1823}
1824
1825bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
1826 hwaddr addr, hwaddr size)
1827{
1828 assert(mr->ram_block);
1829 return cpu_physical_memory_snapshot_get_dirty(snap,
1830 memory_region_get_ram_addr(mr) + addr, size);
1831}
6c279db8 1832
093bc2cd
AK
1833void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1834{
0a752eee 1835 MemoryListener *listener;
0d673e36 1836 AddressSpace *as;
0a752eee 1837 FlatView *view;
5a583347
AK
1838 FlatRange *fr;
1839
0a752eee
PB
1840 /* If the same address space has multiple log_sync listeners, we
1841 * visit that address space's FlatView multiple times. But because
1842 * log_sync listeners are rare, it's still cheaper than walking each
1843 * address space once.
1844 */
1845 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1846 if (!listener->log_sync) {
1847 continue;
1848 }
1849 as = listener->address_space;
1850 view = address_space_get_flatview(as);
99e86347 1851 FOR_EACH_FLAT_RANGE(fr, view) {
0d673e36 1852 if (fr->mr == mr) {
0a752eee
PB
1853 MemoryRegionSection mrs = section_from_flat_range(fr, as);
1854 listener->log_sync(listener, &mrs);
0d673e36 1855 }
5a583347 1856 }
856d7245 1857 flatview_unref(view);
5a583347 1858 }
093bc2cd
AK
1859}
1860
1861void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1862{
fb1cd6f9 1863 if (mr->readonly != readonly) {
59023ef4 1864 memory_region_transaction_begin();
fb1cd6f9 1865 mr->readonly = readonly;
22bde714 1866 memory_region_update_pending |= mr->enabled;
59023ef4 1867 memory_region_transaction_commit();
fb1cd6f9 1868 }
093bc2cd
AK
1869}
1870
5f9a5ea1 1871void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 1872{
5f9a5ea1 1873 if (mr->romd_mode != romd_mode) {
59023ef4 1874 memory_region_transaction_begin();
5f9a5ea1 1875 mr->romd_mode = romd_mode;
22bde714 1876 memory_region_update_pending |= mr->enabled;
59023ef4 1877 memory_region_transaction_commit();
d0a9b5bc
AK
1878 }
1879}
1880
a8170e5e
AK
1881void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
1882 hwaddr size, unsigned client)
093bc2cd 1883{
8e41fb63
FZ
1884 assert(mr->ram_block);
1885 cpu_physical_memory_test_and_clear_dirty(
1886 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK
1887}
1888
a35ba7be
PB
1889int memory_region_get_fd(MemoryRegion *mr)
1890{
4ff87573
PB
1891 int fd;
1892
1893 rcu_read_lock();
1894 while (mr->alias) {
1895 mr = mr->alias;
a35ba7be 1896 }
4ff87573
PB
1897 fd = mr->ram_block->fd;
1898 rcu_read_unlock();
a35ba7be 1899
4ff87573
PB
1900 return fd;
1901}
a35ba7be 1902
093bc2cd
AK
1903void *memory_region_get_ram_ptr(MemoryRegion *mr)
1904{
49b24afc
PB
1905 void *ptr;
1906 uint64_t offset = 0;
093bc2cd 1907
49b24afc
PB
1908 rcu_read_lock();
1909 while (mr->alias) {
1910 offset += mr->alias_offset;
1911 mr = mr->alias;
1912 }
8e41fb63 1913 assert(mr->ram_block);
0878d0e1 1914 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
49b24afc 1915 rcu_read_unlock();
093bc2cd 1916
0878d0e1 1917 return ptr;
093bc2cd
AK
1918}
1919
07bdaa41
PB
1920MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
1921{
1922 RAMBlock *block;
1923
1924 block = qemu_ram_block_from_host(ptr, false, offset);
1925 if (!block) {
1926 return NULL;
1927 }
1928
1929 return block->mr;
1930}
1931
7ebb2745
FZ
1932ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
1933{
1934 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
1935}
1936
37d7c084
PB
1937void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
1938{
8e41fb63 1939 assert(mr->ram_block);
37d7c084 1940
fa53a0e5 1941 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB
1942}
1943
0d673e36 1944static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 1945{
99e86347 1946 FlatView *view;
093bc2cd
AK
1947 FlatRange *fr;
1948 CoalescedMemoryRange *cmr;
1949 AddrRange tmp;
95d2994a 1950 MemoryRegionSection section;
093bc2cd 1951
856d7245 1952 view = address_space_get_flatview(as);
99e86347 1953 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 1954 if (fr->mr == mr) {
95d2994a 1955 section = (MemoryRegionSection) {
f6790af6 1956 .address_space = as,
95d2994a 1957 .offset_within_address_space = int128_get64(fr->addr.start),
052e87b0 1958 .size = fr->addr.size,
95d2994a
AK
1959 };
1960
9a54635d 1961 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
95d2994a
AK
1962 int128_get64(fr->addr.start),
1963 int128_get64(fr->addr.size));
093bc2cd
AK
1964 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
1965 tmp = addrrange_shift(cmr->addr,
08dafab4
AK
1966 int128_sub(fr->addr.start,
1967 int128_make64(fr->offset_in_region)));
093bc2cd
AK
1968 if (!addrrange_intersects(tmp, fr->addr)) {
1969 continue;
1970 }
1971 tmp = addrrange_intersection(tmp, fr->addr);
9a54635d 1972 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
95d2994a
AK
1973 int128_get64(tmp.start),
1974 int128_get64(tmp.size));
093bc2cd
AK
1975 }
1976 }
1977 }
856d7245 1978 flatview_unref(view);
093bc2cd
AK
1979}
1980
0d673e36
AK
1981static void memory_region_update_coalesced_range(MemoryRegion *mr)
1982{
1983 AddressSpace *as;
1984
1985 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1986 memory_region_update_coalesced_range_as(mr, as);
1987 }
1988}
1989
093bc2cd
AK
1990void memory_region_set_coalescing(MemoryRegion *mr)
1991{
1992 memory_region_clear_coalescing(mr);
08dafab4 1993 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK
1994}
1995
1996void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 1997 hwaddr offset,
093bc2cd
AK
1998 uint64_t size)
1999{
7267c094 2000 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2001
08dafab4 2002 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK
2003 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2004 memory_region_update_coalesced_range(mr);
d410515e 2005 memory_region_set_flush_coalesced(mr);
093bc2cd
AK
2006}
2007
2008void memory_region_clear_coalescing(MemoryRegion *mr)
2009{
2010 CoalescedMemoryRange *cmr;
ab5b3db5 2011 bool updated = false;
093bc2cd 2012
d410515e
JK
2013 qemu_flush_coalesced_mmio_buffer();
2014 mr->flush_coalesced_mmio = false;
2015
093bc2cd
AK
2016 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2017 cmr = QTAILQ_FIRST(&mr->coalesced);
2018 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 2019 g_free(cmr);
ab5b3db5
FZ
2020 updated = true;
2021 }
2022
2023 if (updated) {
2024 memory_region_update_coalesced_range(mr);
093bc2cd 2025 }
093bc2cd
AK
2026}
2027
d410515e
JK
2028void memory_region_set_flush_coalesced(MemoryRegion *mr)
2029{
2030 mr->flush_coalesced_mmio = true;
2031}
2032
2033void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2034{
2035 qemu_flush_coalesced_mmio_buffer();
2036 if (QTAILQ_EMPTY(&mr->coalesced)) {
2037 mr->flush_coalesced_mmio = false;
2038 }
2039}
2040
196ea131
JK
2041void memory_region_set_global_locking(MemoryRegion *mr)
2042{
2043 mr->global_locking = true;
2044}
2045
2046void memory_region_clear_global_locking(MemoryRegion *mr)
2047{
2048 mr->global_locking = false;
2049}
2050
8c56c1a5
PF
2051static bool userspace_eventfd_warning;
2052
3e9d69e7 2053void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2054 hwaddr addr,
3e9d69e7
AK
2055 unsigned size,
2056 bool match_data,
2057 uint64_t data,
753d5e14 2058 EventNotifier *e)
3e9d69e7
AK
2059{
2060 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2061 .addr.start = int128_make64(addr),
2062 .addr.size = int128_make64(size),
3e9d69e7
AK
2063 .match_data = match_data,
2064 .data = data,
753d5e14 2065 .e = e,
3e9d69e7
AK
2066 };
2067 unsigned i;
2068
8c56c1a5
PF
2069 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2070 userspace_eventfd_warning))) {
2071 userspace_eventfd_warning = true;
2072 error_report("Using eventfd without MMIO binding in KVM. "
2073 "Suboptimal performance expected");
2074 }
2075
b8aecea2
JW
2076 if (size) {
2077 adjust_endianness(mr, &mrfd.data, size);
2078 }
59023ef4 2079 memory_region_transaction_begin();
3e9d69e7
AK
2080 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2081 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
2082 break;
2083 }
2084 }
2085 ++mr->ioeventfd_nb;
7267c094 2086 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK
2087 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2088 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2089 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2090 mr->ioeventfds[i] = mrfd;
4dc56152 2091 ioeventfd_update_pending |= mr->enabled;
59023ef4 2092 memory_region_transaction_commit();
3e9d69e7
AK
2093}
2094
2095void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2096 hwaddr addr,
3e9d69e7
AK
2097 unsigned size,
2098 bool match_data,
2099 uint64_t data,
753d5e14 2100 EventNotifier *e)
3e9d69e7
AK
2101{
2102 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2103 .addr.start = int128_make64(addr),
2104 .addr.size = int128_make64(size),
3e9d69e7
AK
2105 .match_data = match_data,
2106 .data = data,
753d5e14 2107 .e = e,
3e9d69e7
AK
2108 };
2109 unsigned i;
2110
b8aecea2
JW
2111 if (size) {
2112 adjust_endianness(mr, &mrfd.data, size);
2113 }
59023ef4 2114 memory_region_transaction_begin();
3e9d69e7
AK
2115 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2116 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
2117 break;
2118 }
2119 }
2120 assert(i != mr->ioeventfd_nb);
2121 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2122 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2123 --mr->ioeventfd_nb;
7267c094 2124 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2125 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2126 ioeventfd_update_pending |= mr->enabled;
59023ef4 2127 memory_region_transaction_commit();
3e9d69e7
AK
2128}
2129
feca4ac1 2130static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2131{
feca4ac1 2132 MemoryRegion *mr = subregion->container;
093bc2cd
AK
2133 MemoryRegion *other;
2134
59023ef4
JK
2135 memory_region_transaction_begin();
2136
dfde4e6e 2137 memory_region_ref(subregion);
093bc2cd
AK
2138 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2139 if (subregion->priority >= other->priority) {
2140 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2141 goto done;
2142 }
2143 }
2144 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2145done:
22bde714 2146 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2147 memory_region_transaction_commit();
093bc2cd
AK
2148}
2149
0598701a
PC
2150static void memory_region_add_subregion_common(MemoryRegion *mr,
2151 hwaddr offset,
2152 MemoryRegion *subregion)
2153{
feca4ac1
PB
2154 assert(!subregion->container);
2155 subregion->container = mr;
0598701a 2156 subregion->addr = offset;
feca4ac1 2157 memory_region_update_container_subregions(subregion);
0598701a 2158}
093bc2cd
AK
2159
2160void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2161 hwaddr offset,
093bc2cd
AK
2162 MemoryRegion *subregion)
2163{
093bc2cd
AK
2164 subregion->priority = 0;
2165 memory_region_add_subregion_common(mr, offset, subregion);
2166}
2167
2168void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2169 hwaddr offset,
093bc2cd 2170 MemoryRegion *subregion,
a1ff8ae0 2171 int priority)
093bc2cd 2172{
093bc2cd
AK
2173 subregion->priority = priority;
2174 memory_region_add_subregion_common(mr, offset, subregion);
2175}
2176
2177void memory_region_del_subregion(MemoryRegion *mr,
2178 MemoryRegion *subregion)
2179{
59023ef4 2180 memory_region_transaction_begin();
feca4ac1
PB
2181 assert(subregion->container == mr);
2182 subregion->container = NULL;
093bc2cd 2183 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2184 memory_region_unref(subregion);
22bde714 2185 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2186 memory_region_transaction_commit();
6bba19ba
AK
2187}
2188
2189void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2190{
2191 if (enabled == mr->enabled) {
2192 return;
2193 }
59023ef4 2194 memory_region_transaction_begin();
6bba19ba 2195 mr->enabled = enabled;
22bde714 2196 memory_region_update_pending = true;
59023ef4 2197 memory_region_transaction_commit();
093bc2cd 2198}
1c0ffa58 2199
e7af4c67
MT
2200void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2201{
2202 Int128 s = int128_make64(size);
2203
2204 if (size == UINT64_MAX) {
2205 s = int128_2_64();
2206 }
2207 if (int128_eq(s, mr->size)) {
2208 return;
2209 }
2210 memory_region_transaction_begin();
2211 mr->size = s;
2212 memory_region_update_pending = true;
2213 memory_region_transaction_commit();
2214}
2215
67891b8a 2216static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2217{
feca4ac1 2218 MemoryRegion *container = mr->container;
2282e1af 2219
feca4ac1 2220 if (container) {
67891b8a
PC
2221 memory_region_transaction_begin();
2222 memory_region_ref(mr);
feca4ac1
PB
2223 memory_region_del_subregion(container, mr);
2224 mr->container = container;
2225 memory_region_update_container_subregions(mr);
67891b8a
PC
2226 memory_region_unref(mr);
2227 memory_region_transaction_commit();
2282e1af 2228 }
67891b8a 2229}
2282e1af 2230
67891b8a
PC
2231void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2232{
2233 if (addr != mr->addr) {
2234 mr->addr = addr;
2235 memory_region_readd_subregion(mr);
2236 }
2282e1af
AK
2237}
2238
a8170e5e 2239void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2240{
4703359e 2241 assert(mr->alias);
4703359e 2242
59023ef4 2243 if (offset == mr->alias_offset) {
4703359e
AK
2244 return;
2245 }
2246
59023ef4
JK
2247 memory_region_transaction_begin();
2248 mr->alias_offset = offset;
22bde714 2249 memory_region_update_pending |= mr->enabled;
59023ef4 2250 memory_region_transaction_commit();
4703359e
AK
2251}
2252
a2b257d6
IM
2253uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2254{
2255 return mr->align;
2256}
2257
e2177955
AK
2258static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2259{
2260 const AddrRange *addr = addr_;
2261 const FlatRange *fr = fr_;
2262
2263 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2264 return -1;
2265 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2266 return 1;
2267 }
2268 return 0;
2269}
2270
99e86347 2271static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2272{
99e86347 2273 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK
2274 sizeof(FlatRange), cmp_flatrange_addr);
2275}
2276
eed2bacf
IM
2277bool memory_region_is_mapped(MemoryRegion *mr)
2278{
2279 return mr->container ? true : false;
2280}
2281
c6742b14
PB
2282/* Same as memory_region_find, but it does not add a reference to the
2283 * returned region. It must be called from an RCU critical section.
2284 */
2285static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2286 hwaddr addr, uint64_t size)
e2177955 2287{
052e87b0 2288 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB
2289 MemoryRegion *root;
2290 AddressSpace *as;
2291 AddrRange range;
99e86347 2292 FlatView *view;
73034e9e
PB
2293 FlatRange *fr;
2294
2295 addr += mr->addr;
feca4ac1
PB
2296 for (root = mr; root->container; ) {
2297 root = root->container;
73034e9e
PB
2298 addr += root->addr;
2299 }
e2177955 2300
73034e9e 2301 as = memory_region_to_address_space(root);
eed2bacf
IM
2302 if (!as) {
2303 return ret;
2304 }
73034e9e 2305 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2306
2b647668 2307 view = atomic_rcu_read(&as->current_map);
99e86347 2308 fr = flatview_lookup(view, range);
e2177955 2309 if (!fr) {
c6742b14 2310 return ret;
e2177955
AK
2311 }
2312
99e86347 2313 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK
2314 --fr;
2315 }
2316
2317 ret.mr = fr->mr;
73034e9e 2318 ret.address_space = as;
e2177955
AK
2319 range = addrrange_intersection(range, fr->addr);
2320 ret.offset_within_region = fr->offset_in_region;
2321 ret.offset_within_region += int128_get64(int128_sub(range.start,
2322 fr->addr.start));
052e87b0 2323 ret.size = range.size;
e2177955 2324 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2325 ret.readonly = fr->readonly;
c6742b14
PB
2326 return ret;
2327}
2328
2329MemoryRegionSection memory_region_find(MemoryRegion *mr,
2330 hwaddr addr, uint64_t size)
2331{
2332 MemoryRegionSection ret;
2333 rcu_read_lock();
2334 ret = memory_region_find_rcu(mr, addr, size);
2335 if (ret.mr) {
2336 memory_region_ref(ret.mr);
2337 }
2b647668 2338 rcu_read_unlock();
e2177955
AK
2339 return ret;
2340}
2341
c6742b14
PB
2342bool memory_region_present(MemoryRegion *container, hwaddr addr)
2343{
2344 MemoryRegion *mr;
2345
2346 rcu_read_lock();
2347 mr = memory_region_find_rcu(container, addr, 1).mr;
2348 rcu_read_unlock();
2349 return mr && mr != container;
2350}
2351
9c1f8f44 2352void memory_global_dirty_log_sync(void)
86e775c6 2353{
9c1f8f44
PB
2354 MemoryListener *listener;
2355 AddressSpace *as;
99e86347 2356 FlatView *view;
7664e80c
AK
2357 FlatRange *fr;
2358
9c1f8f44
PB
2359 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2360 if (!listener->log_sync) {
2361 continue;
2362 }
d45fa784 2363 as = listener->address_space;
9c1f8f44
PB
2364 view = address_space_get_flatview(as);
2365 FOR_EACH_FLAT_RANGE(fr, view) {
adaad61c
PB
2366 if (fr->dirty_log_mask) {
2367 MemoryRegionSection mrs = section_from_flat_range(fr, as);
2368 listener->log_sync(listener, &mrs);
2369 }
9c1f8f44
PB
2370 }
2371 flatview_unref(view);
7664e80c
AK
2372 }
2373}
2374
19310760
JZ
2375static VMChangeStateEntry *vmstate_change;
2376
7664e80c
AK
2377void memory_global_dirty_log_start(void)
2378{
19310760
JZ
2379 if (vmstate_change) {
2380 qemu_del_vm_change_state_handler(vmstate_change);
2381 vmstate_change = NULL;
2382 }
2383
7664e80c 2384 global_dirty_log = true;
6f6a5ef3 2385
7376e582 2386 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3
PB
2387
2388 /* Refresh DIRTY_LOG_MIGRATION bit. */
2389 memory_region_transaction_begin();
2390 memory_region_update_pending = true;
2391 memory_region_transaction_commit();
7664e80c
AK
2392}
2393
19310760 2394static void memory_global_dirty_log_do_stop(void)
7664e80c 2395{
7664e80c 2396 global_dirty_log = false;
6f6a5ef3
PB
2397
2398 /* Refresh DIRTY_LOG_MIGRATION bit. */
2399 memory_region_transaction_begin();
2400 memory_region_update_pending = true;
2401 memory_region_transaction_commit();
2402
7376e582 2403 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK
2404}
2405
19310760
JZ
2406static void memory_vm_change_state_handler(void *opaque, int running,
2407 RunState state)
2408{
2409 if (running) {
2410 memory_global_dirty_log_do_stop();
2411
2412 if (vmstate_change) {
2413 qemu_del_vm_change_state_handler(vmstate_change);
2414 vmstate_change = NULL;
2415 }
2416 }
2417}
2418
2419void memory_global_dirty_log_stop(void)
2420{
2421 if (!runstate_is_running()) {
2422 if (vmstate_change) {
2423 return;
2424 }
2425 vmstate_change = qemu_add_vm_change_state_handler(
2426 memory_vm_change_state_handler, NULL);
2427 return;
2428 }
2429
2430 memory_global_dirty_log_do_stop();
2431}
2432
7664e80c
AK
2433static void listener_add_address_space(MemoryListener *listener,
2434 AddressSpace *as)
2435{
99e86347 2436 FlatView *view;
7664e80c
AK
2437 FlatRange *fr;
2438
680a4783
PB
2439 if (listener->begin) {
2440 listener->begin(listener);
2441 }
7664e80c 2442 if (global_dirty_log) {
975aefe0
AK
2443 if (listener->log_global_start) {
2444 listener->log_global_start(listener);
2445 }
7664e80c 2446 }
975aefe0 2447
856d7245 2448 view = address_space_get_flatview(as);
99e86347 2449 FOR_EACH_FLAT_RANGE(fr, view) {
7664e80c
AK
2450 MemoryRegionSection section = {
2451 .mr = fr->mr,
f6790af6 2452 .address_space = as,
7664e80c 2453 .offset_within_region = fr->offset_in_region,
052e87b0 2454 .size = fr->addr.size,
7664e80c 2455 .offset_within_address_space = int128_get64(fr->addr.start),
7a8499e8 2456 .readonly = fr->readonly,
7664e80c 2457 };
680a4783
PB
2458 if (fr->dirty_log_mask && listener->log_start) {
2459 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2460 }
975aefe0
AK
2461 if (listener->region_add) {
2462 listener->region_add(listener, &section);
2463 }
7664e80c 2464 }
680a4783
PB
2465 if (listener->commit) {
2466 listener->commit(listener);
2467 }
856d7245 2468 flatview_unref(view);
7664e80c
AK
2469}
2470
d45fa784 2471void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2472{
72e22d2f
AK
2473 MemoryListener *other = NULL;
2474
d45fa784 2475 listener->address_space = as;
72e22d2f
AK
2476 if (QTAILQ_EMPTY(&memory_listeners)
2477 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2478 memory_listeners)->priority) {
2479 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2480 } else {
2481 QTAILQ_FOREACH(other, &memory_listeners, link) {
2482 if (listener->priority < other->priority) {
2483 break;
2484 }
2485 }
2486 QTAILQ_INSERT_BEFORE(other, listener, link);
2487 }
0d673e36 2488
9a54635d
PB
2489 if (QTAILQ_EMPTY(&as->listeners)
2490 || listener->priority >= QTAILQ_LAST(&as->listeners,
2491 memory_listeners)->priority) {
2492 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2493 } else {
2494 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2495 if (listener->priority < other->priority) {
2496 break;
2497 }
2498 }
2499 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2500 }
2501
d45fa784 2502 listener_add_address_space(listener, as);
7664e80c
AK
2503}
2504
2505void memory_listener_unregister(MemoryListener *listener)
2506{
1d8280c1
PB
2507 if (!listener->address_space) {
2508 return;
2509 }
2510
72e22d2f 2511 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2512 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2513 listener->address_space = NULL;
86e775c6 2514}
e2177955 2515
c9356746
FK
2516bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2517{
2518 void *host;
2519 unsigned size = 0;
2520 unsigned offset = 0;
2521 Object *new_interface;
2522
2523 if (!mr || !mr->ops->request_ptr) {
2524 return false;
2525 }
2526
2527 /*
2528 * Avoid an update if the request_ptr call
2529 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2530 * a cache.
2531 */
2532 memory_region_transaction_begin();
2533
2534 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2535
2536 if (!host || !size) {
2537 memory_region_transaction_commit();
2538 return false;
2539 }
2540
2541 new_interface = object_new("mmio_interface");
2542 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2543 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2544 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2545 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2546 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2547 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2548
2549 memory_region_transaction_commit();
2550 return true;
2551}
2552
2553typedef struct MMIOPtrInvalidate {
2554 MemoryRegion *mr;
2555 hwaddr offset;
2556 unsigned size;
2557 int busy;
2558 int allocated;
2559} MMIOPtrInvalidate;
2560
2561#define MAX_MMIO_INVALIDATE 10
2562static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2563
2564static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2565 run_on_cpu_data data)
2566{
2567 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2568 MemoryRegion *mr = invalidate_data->mr;
2569 hwaddr offset = invalidate_data->offset;
2570 unsigned size = invalidate_data->size;
2571 MemoryRegionSection section = memory_region_find(mr, offset, size);
2572
2573 qemu_mutex_lock_iothread();
2574
2575 /* Reset dirty so this doesn't happen later. */
2576 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2577
2578 if (section.mr != mr) {
2579 /* memory_region_find add a ref on section.mr */
2580 memory_region_unref(section.mr);
2581 if (MMIO_INTERFACE(section.mr->owner)) {
2582 /* We found the interface just drop it. */
2583 object_property_set_bool(section.mr->owner, false, "realized",
2584 NULL);
2585 object_unref(section.mr->owner);
2586 object_unparent(section.mr->owner);
2587 }
2588 }
2589
2590 qemu_mutex_unlock_iothread();
2591
2592 if (invalidate_data->allocated) {
2593 g_free(invalidate_data);
2594 } else {
2595 invalidate_data->busy = 0;
2596 }
2597}
2598
2599void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2600 unsigned size)
2601{
2602 size_t i;
2603 MMIOPtrInvalidate *invalidate_data = NULL;
2604
2605 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2606 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2607 invalidate_data = &mmio_ptr_invalidate_list[i];
2608 break;
2609 }
2610 }
2611
2612 if (!invalidate_data) {
2613 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2614 invalidate_data->allocated = 1;
2615 }
2616
2617 invalidate_data->mr = mr;
2618 invalidate_data->offset = offset;
2619 invalidate_data->size = size;
2620
2621 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2622 RUN_ON_CPU_HOST_PTR(invalidate_data));
2623}
2624
7dca8043 2625void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2626{
ac95190e 2627 memory_region_ref(root);
59023ef4 2628 memory_region_transaction_begin();
f0c02d15 2629 as->ref_count = 1;
8786db7c 2630 as->root = root;
f0c02d15 2631 as->malloced = false;
8786db7c
AK
2632 as->current_map = g_new(FlatView, 1);
2633 flatview_init(as->current_map);
4c19eb72
AK
2634 as->ioeventfd_nb = 0;
2635 as->ioeventfds = NULL;
9a54635d 2636 QTAILQ_INIT(&as->listeners);
0d673e36 2637 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2638 as->name = g_strdup(name ? name : "anonymous");
9a62e24f 2639 as->dispatch = NULL;
f43793c7
PB
2640 memory_region_update_pending |= root->enabled;
2641 memory_region_transaction_commit();
1c0ffa58 2642}
658b2224 2643
374f2981 2644static void do_address_space_destroy(AddressSpace *as)
83f3c251 2645{
f0c02d15 2646 bool do_free = as->malloced;
078c44f4 2647
83f3c251 2648 address_space_destroy_dispatch(as);
9a54635d 2649 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2650
856d7245 2651 flatview_unref(as->current_map);
7dca8043 2652 g_free(as->name);
4c19eb72 2653 g_free(as->ioeventfds);
ac95190e 2654 memory_region_unref(as->root);
f0c02d15
PC
2655 if (do_free) {
2656 g_free(as);
2657 }
2658}
2659
2660AddressSpace *address_space_init_shareable(MemoryRegion *root, const char *name)
2661{
2662 AddressSpace *as;
2663
2664 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2665 if (root == as->root && as->malloced) {
2666 as->ref_count++;
2667 return as;
2668 }
2669 }
2670
2671 as = g_malloc0(sizeof *as);
2672 address_space_init(as, root, name);
2673 as->malloced = true;
2674 return as;
83f3c251
AK
2675}
2676
374f2981
PB
2677void address_space_destroy(AddressSpace *as)
2678{
ac95190e
PB
2679 MemoryRegion *root = as->root;
2680
f0c02d15
PC
2681 as->ref_count--;
2682 if (as->ref_count) {
2683 return;
2684 }
374f2981
PB
2685 /* Flush out anything from MemoryListeners listening in on this */
2686 memory_region_transaction_begin();
2687 as->root = NULL;
2688 memory_region_transaction_commit();
2689 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2690
2691 /* At this point, as->dispatch and as->current_map are dummy
2692 * entries that the guest should never use. Wait for the old
2693 * values to expire before freeing the data.
2694 */
ac95190e 2695 as->root = root;
374f2981
PB
2696 call_rcu(as, do_address_space_destroy, rcu);
2697}
2698
4e831901
PX
2699static const char *memory_region_type(MemoryRegion *mr)
2700{
2701 if (memory_region_is_ram_device(mr)) {
2702 return "ramd";
2703 } else if (memory_region_is_romd(mr)) {
2704 return "romd";
2705 } else if (memory_region_is_rom(mr)) {
2706 return "rom";
2707 } else if (memory_region_is_ram(mr)) {
2708 return "ram";
2709 } else {
2710 return "i/o";
2711 }
2712}
2713
314e2987
BS
2714typedef struct MemoryRegionList MemoryRegionList;
2715
2716struct MemoryRegionList {
2717 const MemoryRegion *mr;
a16878d2 2718 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS
2719};
2720
a16878d2 2721typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
314e2987 2722
4e831901
PX
2723#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2724 int128_sub((size), int128_one())) : 0)
2725#define MTREE_INDENT " "
2726
314e2987
BS
2727static void mtree_print_mr(fprintf_function mon_printf, void *f,
2728 const MemoryRegion *mr, unsigned int level,
a8170e5e 2729 hwaddr base,
9479c57a 2730 MemoryRegionListHead *alias_print_queue)
314e2987 2731{
9479c57a
JK
2732 MemoryRegionList *new_ml, *ml, *next_ml;
2733 MemoryRegionListHead submr_print_queue;
314e2987
BS
2734 const MemoryRegion *submr;
2735 unsigned int i;
b31f8412 2736 hwaddr cur_start, cur_end;
314e2987 2737
f8a9f720 2738 if (!mr) {
314e2987
BS
2739 return;
2740 }
2741
2742 for (i = 0; i < level; i++) {
4e831901 2743 mon_printf(f, MTREE_INDENT);
314e2987
BS
2744 }
2745
b31f8412
PX
2746 cur_start = base + mr->addr;
2747 cur_end = cur_start + MR_SIZE(mr->size);
2748
2749 /*
2750 * Try to detect overflow of memory region. This should never
2751 * happen normally. When it happens, we dump something to warn the
2752 * user who is observing this.
2753 */
2754 if (cur_start < base || cur_end < cur_start) {
2755 mon_printf(f, "[DETECTED OVERFLOW!] ");
2756 }
2757
314e2987
BS
2758 if (mr->alias) {
2759 MemoryRegionList *ml;
2760 bool found = false;
2761
2762 /* check if the alias is already in the queue */
a16878d2 2763 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2764 if (ml->mr == mr->alias) {
314e2987
BS
2765 found = true;
2766 }
2767 }
2768
2769 if (!found) {
2770 ml = g_new(MemoryRegionList, 1);
2771 ml->mr = mr->alias;
a16878d2 2772 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2773 }
4896d74b 2774 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
4e831901 2775 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
f8a9f720 2776 "-" TARGET_FMT_plx "%s\n",
b31f8412 2777 cur_start, cur_end,
4b474ba7 2778 mr->priority,
4e831901 2779 memory_region_type((MemoryRegion *)mr),
3fb18b4d
PC
2780 memory_region_name(mr),
2781 memory_region_name(mr->alias),
314e2987 2782 mr->alias_offset,
4e831901 2783 mr->alias_offset + MR_SIZE(mr->size),
f8a9f720 2784 mr->enabled ? "" : " [disabled]");
314e2987 2785 } else {
4896d74b 2786 mon_printf(f,
4e831901 2787 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
b31f8412 2788 cur_start, cur_end,
4b474ba7 2789 mr->priority,
4e831901 2790 memory_region_type((MemoryRegion *)mr),
f8a9f720
GH
2791 memory_region_name(mr),
2792 mr->enabled ? "" : " [disabled]");
314e2987 2793 }
9479c57a
JK
2794
2795 QTAILQ_INIT(&submr_print_queue);
2796
314e2987 2797 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
2798 new_ml = g_new(MemoryRegionList, 1);
2799 new_ml->mr = submr;
a16878d2 2800 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK
2801 if (new_ml->mr->addr < ml->mr->addr ||
2802 (new_ml->mr->addr == ml->mr->addr &&
2803 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 2804 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK
2805 new_ml = NULL;
2806 break;
2807 }
2808 }
2809 if (new_ml) {
a16878d2 2810 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK
2811 }
2812 }
2813
a16878d2 2814 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b31f8412 2815 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
9479c57a
JK
2816 alias_print_queue);
2817 }
2818
a16878d2 2819 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 2820 g_free(ml);
314e2987
BS
2821 }
2822}
2823
57bb40c9
PX
2824static void mtree_print_flatview(fprintf_function p, void *f,
2825 AddressSpace *as)
2826{
2827 FlatView *view = address_space_get_flatview(as);
2828 FlatRange *range = &view->ranges[0];
2829 MemoryRegion *mr;
2830 int n = view->nr;
2831
2832 if (n <= 0) {
2833 p(f, MTREE_INDENT "No rendered FlatView for "
2834 "address space '%s'\n", as->name);
2835 flatview_unref(view);
2836 return;
2837 }
2838
2839 while (n--) {
2840 mr = range->mr;
377a07aa
PB
2841 if (range->offset_in_region) {
2842 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2843 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
2844 int128_get64(range->addr.start),
2845 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2846 mr->priority,
2847 range->readonly ? "rom" : memory_region_type(mr),
2848 memory_region_name(mr),
2849 range->offset_in_region);
2850 } else {
2851 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2852 TARGET_FMT_plx " (prio %d, %s): %s\n",
2853 int128_get64(range->addr.start),
2854 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2855 mr->priority,
2856 range->readonly ? "rom" : memory_region_type(mr),
2857 memory_region_name(mr));
2858 }
57bb40c9
PX
2859 range++;
2860 }
2861
2862 flatview_unref(view);
2863}
2864
2865void mtree_info(fprintf_function mon_printf, void *f, bool flatview)
314e2987
BS
2866{
2867 MemoryRegionListHead ml_head;
2868 MemoryRegionList *ml, *ml2;
0d673e36 2869 AddressSpace *as;
314e2987 2870
57bb40c9
PX
2871 if (flatview) {
2872 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2873 mon_printf(f, "address-space (flat view): %s\n", as->name);
2874 mtree_print_flatview(mon_printf, f, as);
2875 mon_printf(f, "\n");
2876 }
2877 return;
2878 }
2879
314e2987
BS
2880 QTAILQ_INIT(&ml_head);
2881
0d673e36 2882 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
e48816aa
GH
2883 mon_printf(f, "address-space: %s\n", as->name);
2884 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
2885 mon_printf(f, "\n");
b9f9be88
BS
2886 }
2887
314e2987 2888 /* print aliased regions */
a16878d2 2889 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
e48816aa
GH
2890 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
2891 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
2892 mon_printf(f, "\n");
314e2987
BS
2893 }
2894
a16878d2 2895 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 2896 g_free(ml);
314e2987 2897 }
314e2987 2898}
b4fefef9 2899
b08199c6
PM
2900void memory_region_init_ram(MemoryRegion *mr,
2901 struct Object *owner,
2902 const char *name,
2903 uint64_t size,
2904 Error **errp)
2905{
2906 DeviceState *owner_dev;
2907 Error *err = NULL;
2908
2909 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
2910 if (err) {
2911 error_propagate(errp, err);
2912 return;
2913 }
2914 /* This will assert if owner is neither NULL nor a DeviceState.
2915 * We only want the owner here for the purposes of defining a
2916 * unique name for migration. TODO: Ideally we should implement
2917 * a naming scheme for Objects which are not DeviceStates, in
2918 * which case we can relax this restriction.
2919 */
2920 owner_dev = DEVICE(owner);
2921 vmstate_register_ram(mr, owner_dev);
2922}
2923
2924void memory_region_init_rom(MemoryRegion *mr,
2925 struct Object *owner,
2926 const char *name,
2927 uint64_t size,
2928 Error **errp)
2929{
2930 DeviceState *owner_dev;
2931 Error *err = NULL;
2932
2933 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
2934 if (err) {
2935 error_propagate(errp, err);
2936 return;
2937 }
2938 /* This will assert if owner is neither NULL nor a DeviceState.
2939 * We only want the owner here for the purposes of defining a
2940 * unique name for migration. TODO: Ideally we should implement
2941 * a naming scheme for Objects which are not DeviceStates, in
2942 * which case we can relax this restriction.
2943 */
2944 owner_dev = DEVICE(owner);
2945 vmstate_register_ram(mr, owner_dev);
2946}
2947
2948void memory_region_init_rom_device(MemoryRegion *mr,
2949 struct Object *owner,
2950 const MemoryRegionOps *ops,
2951 void *opaque,
2952 const char *name,
2953 uint64_t size,
2954 Error **errp)
2955{
2956 DeviceState *owner_dev;
2957 Error *err = NULL;
2958
2959 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
2960 name, size, &err);
2961 if (err) {
2962 error_propagate(errp, err);
2963 return;
2964 }
2965 /* This will assert if owner is neither NULL nor a DeviceState.
2966 * We only want the owner here for the purposes of defining a
2967 * unique name for migration. TODO: Ideally we should implement
2968 * a naming scheme for Objects which are not DeviceStates, in
2969 * which case we can relax this restriction.
2970 */
2971 owner_dev = DEVICE(owner);
2972 vmstate_register_ram(mr, owner_dev);
2973}
2974
b4fefef9
PC
2975static const TypeInfo memory_region_info = {
2976 .parent = TYPE_OBJECT,
2977 .name = TYPE_MEMORY_REGION,
2978 .instance_size = sizeof(MemoryRegion),
2979 .instance_init = memory_region_initfn,
2980 .instance_finalize = memory_region_finalize,
2981};
2982
3df9d748
AK
2983static const TypeInfo iommu_memory_region_info = {
2984 .parent = TYPE_MEMORY_REGION,
2985 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 2986 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK
2987 .instance_size = sizeof(IOMMUMemoryRegion),
2988 .instance_init = iommu_memory_region_initfn,
1221a474 2989 .abstract = true,
3df9d748
AK
2990};
2991
b4fefef9
PC
2992static void memory_register_types(void)
2993{
2994 type_register_static(&memory_region_info);
3df9d748 2995 type_register_static(&iommu_memory_region_info);
b4fefef9
PC
2996}
2997
2998type_init(memory_register_types)