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memory: Rename memory_region_init_rom() and _rom_device() to _nomigrate()
[mirror_qemu.git] / memory.c
CommitLineData
093bc2cd
AK		 1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB		 12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
AK		 14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879
PB		 18#include "qemu-common.h"
19#include "cpu.h"
022c62cb
PB		 20#include "exec/memory.h"
21#include "exec/address-spaces.h"
22#include "exec/ioport.h"
409ddd01 23#include "qapi/visitor.h"
1de7afc9 24#include "qemu/bitops.h"
8c56c1a5 25#include "qemu/error-report.h"
2c9b15ca 26#include "qom/object.h"
0ab8ed18 27#include "trace-root.h"
093bc2cd 28
022c62cb 29#include "exec/memory-internal.h"
220c3ebd 30#include "exec/ram_addr.h"
8c56c1a5 31#include "sysemu/kvm.h"
e1c57ab8 32#include "sysemu/sysemu.h"
c9356746
FK		 33#include "hw/misc/mmio_interface.h"
34#include "hw/qdev-properties.h"
67d95c15 35
d197063f
PB		 36//#define DEBUG_UNASSIGNED
37
22bde714
JK		 38static unsigned memory_region_transaction_depth;
39static bool memory_region_update_pending;
4dc56152 40static bool ioeventfd_update_pending;
7664e80c
AK		 41static bool global_dirty_log = false;
42
72e22d2f
AK		 43static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
44 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 45
0d673e36
AK		 46static QTAILQ_HEAD(, AddressSpace) address_spaces
47 = QTAILQ_HEAD_INITIALIZER(address_spaces);
48
093bc2cd
AK		 49typedef struct AddrRange AddrRange;
50
8417cebf 51/*
c9cdaa3a 52 * Note that signed integers are needed for negative offsetting in aliases
8417cebf
AK		 53 * (large MemoryRegion::alias_offset).
54 */
093bc2cd 55struct AddrRange {
08dafab4
AK		 56 Int128 start;
57 Int128 size;
093bc2cd
AK		 58};
59
08dafab4 60static AddrRange addrrange_make(Int128 start, Int128 size)
093bc2cd
AK		 61{
62 return (AddrRange) { start, size };
63}
64
65static bool addrrange_equal(AddrRange r1, AddrRange r2)
66{
08dafab4 67 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
093bc2cd
AK		 68}
69
08dafab4 70static Int128 addrrange_end(AddrRange r)
093bc2cd 71{
08dafab4 72 return int128_add(r.start, r.size);
093bc2cd
AK		 73}
74
08dafab4 75static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 76{
08dafab4 77 int128_addto(&range.start, delta);
093bc2cd
AK		 78 return range;
79}
80
08dafab4
AK		 81static bool addrrange_contains(AddrRange range, Int128 addr)
82{
83 return int128_ge(addr, range.start)
84 && int128_lt(addr, addrrange_end(range));
85}
86
093bc2cd
AK		 87static bool addrrange_intersects(AddrRange r1, AddrRange r2)
88{
08dafab4
AK		 89 return addrrange_contains(r1, r2.start)
90 || addrrange_contains(r2, r1.start);
093bc2cd
AK		 91}
92
93static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
94{
08dafab4
AK		 95 Int128 start = int128_max(r1.start, r2.start);
96 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
97 return addrrange_make(start, int128_sub(end, start));
093bc2cd
AK		 98}
99
0e0d36b4
AK		 100enum ListenerDirection { Forward, Reverse };
101
7376e582 102#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
AK		 103 do { \
104 MemoryListener *_listener; \
105 \
106 switch (_direction) { \
107 case Forward: \
108 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
AK		 109 if (_listener->_callback) { \
110 _listener->_callback(_listener, ##_args); \
111 } \
0e0d36b4
AK		 112 } \
113 break; \
114 case Reverse: \
115 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
116 memory_listeners, link) { \
975aefe0
AK		 117 if (_listener->_callback) { \
118 _listener->_callback(_listener, ##_args); \
119 } \
0e0d36b4
AK		 120 } \
121 break; \
122 default: \
123 abort(); \
124 } \
125 } while (0)
126
9a54635d 127#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
7376e582
AK		 128 do { \
129 MemoryListener *_listener; \
9a54635d 130 struct memory_listeners_as *list = &(_as)->listeners; \
7376e582
AK		 131 \
132 switch (_direction) { \
133 case Forward: \
9a54635d
PB		 134 QTAILQ_FOREACH(_listener, list, link_as) { \
135 if (_listener->_callback) { \
7376e582
AK		 136 _listener->_callback(_listener, _section, ##_args); \
137 } \
138 } \
139 break; \
140 case Reverse: \
9a54635d
PB		 141 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
142 link_as) { \
143 if (_listener->_callback) { \
7376e582
AK		 144 _listener->_callback(_listener, _section, ##_args); \
145 } \
146 } \
147 break; \
148 default: \
149 abort(); \
150 } \
151 } while (0)
152
dfde4e6e 153/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 154#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44
PB		 155 do { \
156 MemoryRegionSection mrs = section_from_flat_range(fr, as); \
9a54635d 157 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 158 } while(0)
0e0d36b4 159
093bc2cd
AK		 160struct CoalescedMemoryRange {
161 AddrRange addr;
162 QTAILQ_ENTRY(CoalescedMemoryRange) link;
163};
164
3e9d69e7
AK		 165struct MemoryRegionIoeventfd {
166 AddrRange addr;
167 bool match_data;
168 uint64_t data;
753d5e14 169 EventNotifier *e;
3e9d69e7
AK		 170};
171
172static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
173 MemoryRegionIoeventfd b)
174{
08dafab4 175 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 176 return true;
08dafab4 177 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 178 return false;
08dafab4 179 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 180 return true;
08dafab4 181 } else if (int128_gt(a.addr.size, b.addr.size)) {
3e9d69e7
AK		 182 return false;
183 } else if (a.match_data < b.match_data) {
184 return true;
185 } else if (a.match_data > b.match_data) {
186 return false;
187 } else if (a.match_data) {
188 if (a.data < b.data) {
189 return true;
190 } else if (a.data > b.data) {
191 return false;
192 }
193 }
753d5e14 194 if (a.e < b.e) {
3e9d69e7 195 return true;
753d5e14 196 } else if (a.e > b.e) {
3e9d69e7
AK		 197 return false;
198 }
199 return false;
200}
201
202static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
203 MemoryRegionIoeventfd b)
204{
205 return !memory_region_ioeventfd_before(a, b)
206 && !memory_region_ioeventfd_before(b, a);
207}
208
093bc2cd
AK		 209typedef struct FlatRange FlatRange;
210typedef struct FlatView FlatView;
211
212/* Range of memory in the global map. Addresses are absolute. */
213struct FlatRange {
214 MemoryRegion *mr;
a8170e5e 215 hwaddr offset_in_region;
093bc2cd 216 AddrRange addr;
5a583347 217 uint8_t dirty_log_mask;
b138e654 218 bool romd_mode;
fb1cd6f9 219 bool readonly;
093bc2cd
AK		 220};
221
222/* Flattened global view of current active memory hierarchy. Kept in sorted
223 * order.
224 */
225struct FlatView {
374f2981 226 struct rcu_head rcu;
856d7245 227 unsigned ref;
093bc2cd
AK		 228 FlatRange *ranges;
229 unsigned nr;
230 unsigned nr_allocated;
231};
232
cc31e6e7
AK		 233typedef struct AddressSpaceOps AddressSpaceOps;
234
093bc2cd
AK		 235#define FOR_EACH_FLAT_RANGE(var, view) \
236 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
237
9c1f8f44
PB		 238static inline MemoryRegionSection
239section_from_flat_range(FlatRange *fr, AddressSpace *as)
240{
241 return (MemoryRegionSection) {
242 .mr = fr->mr,
243 .address_space = as,
244 .offset_within_region = fr->offset_in_region,
245 .size = fr->addr.size,
246 .offset_within_address_space = int128_get64(fr->addr.start),
247 .readonly = fr->readonly,
248 };
249}
250
093bc2cd
AK		 251static bool flatrange_equal(FlatRange *a, FlatRange *b)
252{
253 return a->mr == b->mr
254 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 255 && a->offset_in_region == b->offset_in_region
b138e654 256 && a->romd_mode == b->romd_mode
fb1cd6f9 257 && a->readonly == b->readonly;
093bc2cd
AK		 258}
259
260static void flatview_init(FlatView *view)
261{
856d7245 262 view->ref = 1;
093bc2cd
AK		 263 view->ranges = NULL;
264 view->nr = 0;
265 view->nr_allocated = 0;
266}
267
268/* Insert a range into a given position. Caller is responsible for maintaining
269 * sorting order.
270 */
271static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
272{
273 if (view->nr == view->nr_allocated) {
274 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 275 view->ranges = g_realloc(view->ranges,
093bc2cd
AK		 276 view->nr_allocated * sizeof(*view->ranges));
277 }
278 memmove(view->ranges + pos + 1, view->ranges + pos,
279 (view->nr - pos) * sizeof(FlatRange));
280 view->ranges[pos] = *range;
dfde4e6e 281 memory_region_ref(range->mr);
093bc2cd
AK		 282 ++view->nr;
283}
284
285static void flatview_destroy(FlatView *view)
286{
dfde4e6e
PB		 287 int i;
288
289 for (i = 0; i < view->nr; i++) {
290 memory_region_unref(view->ranges[i].mr);
291 }
7267c094 292 g_free(view->ranges);
a9a0c06d 293 g_free(view);
093bc2cd
AK		 294}
295
856d7245
PB		 296static void flatview_ref(FlatView *view)
297{
298 atomic_inc(&view->ref);
299}
300
301static void flatview_unref(FlatView *view)
302{
303 if (atomic_fetch_dec(&view->ref) == 1) {
304 flatview_destroy(view);
305 }
306}
307
3d8e6bf9
AK		 308static bool can_merge(FlatRange *r1, FlatRange *r2)
309{
08dafab4 310 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 311 && r1->mr == r2->mr
08dafab4
AK		 312 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
313 r1->addr.size),
314 int128_make64(r2->offset_in_region))
d0a9b5bc 315 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 316 && r1->romd_mode == r2->romd_mode
fb1cd6f9 317 && r1->readonly == r2->readonly;
3d8e6bf9
AK		 318}
319
8508e024 320/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK		 321static void flatview_simplify(FlatView *view)
322{
323 unsigned i, j;
324
325 i = 0;
326 while (i < view->nr) {
327 j = i + 1;
328 while (j < view->nr
329 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 330 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
AK		 331 ++j;
332 }
333 ++i;
334 memmove(&view->ranges[i], &view->ranges[j],
335 (view->nr - j) * sizeof(view->ranges[j]));
336 view->nr -= j - i;
337 }
338}
339
e7342aa3
PB		 340static bool memory_region_big_endian(MemoryRegion *mr)
341{
342#ifdef TARGET_WORDS_BIGENDIAN
343 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
344#else
345 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
346#endif
347}
348
e11ef3d1
PB		 349static bool memory_region_wrong_endianness(MemoryRegion *mr)
350{
351#ifdef TARGET_WORDS_BIGENDIAN
352 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
353#else
354 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
355#endif
356}
357
358static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
359{
360 if (memory_region_wrong_endianness(mr)) {
361 switch (size) {
362 case 1:
363 break;
364 case 2:
365 *data = bswap16(*data);
366 break;
367 case 4:
368 *data = bswap32(*data);
369 break;
370 case 8:
371 *data = bswap64(*data);
372 break;
373 default:
374 abort();
375 }
376 }
377}
378
4779dc1d
HB		 379static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
380{
381 MemoryRegion *root;
382 hwaddr abs_addr = offset;
383
384 abs_addr += mr->addr;
385 for (root = mr; root->container; ) {
386 root = root->container;
387 abs_addr += root->addr;
388 }
389
390 return abs_addr;
391}
392
5a68be94
HB		 393static int get_cpu_index(void)
394{
395 if (current_cpu) {
396 return current_cpu->cpu_index;
397 }
398 return -1;
399}
400
cc05c43a
PM		 401static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
402 hwaddr addr,
403 uint64_t *value,
404 unsigned size,
405 unsigned shift,
406 uint64_t mask,
407 MemTxAttrs attrs)
408{
409 uint64_t tmp;
410
411 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
23d92d68 412 if (mr->subpage) {
5a68be94 413 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 414 } else if (mr == &io_mem_notdirty) {
415 /* Accesses to code which has previously been translated into a TB show
416 * up in the MMIO path, as accesses to the io_mem_notdirty
417 * MemoryRegion. */
418 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 419 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
420 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 421 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 422 }
cc05c43a
PM		 423 *value |= (tmp & mask) << shift;
424 return MEMTX_OK;
425}
426
427static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB		 428 hwaddr addr,
429 uint64_t *value,
430 unsigned size,
431 unsigned shift,
cc05c43a
PM		 432 uint64_t mask,
433 MemTxAttrs attrs)
ce5d2f33 434{
ce5d2f33
PB		 435 uint64_t tmp;
436
cc05c43a 437 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 438 if (mr->subpage) {
5a68be94 439 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 440 } else if (mr == &io_mem_notdirty) {
441 /* Accesses to code which has previously been translated into a TB show
442 * up in the MMIO path, as accesses to the io_mem_notdirty
443 * MemoryRegion. */
444 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 445 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
446 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 447 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 448 }
ce5d2f33 449 *value |= (tmp & mask) << shift;
cc05c43a 450 return MEMTX_OK;
ce5d2f33
PB		 451}
452
cc05c43a
PM		 453static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
454 hwaddr addr,
455 uint64_t *value,
456 unsigned size,
457 unsigned shift,
458 uint64_t mask,
459 MemTxAttrs attrs)
164a4dcd 460{
cc05c43a
PM		 461 uint64_t tmp = 0;
462 MemTxResult r;
164a4dcd 463
cc05c43a 464 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 465 if (mr->subpage) {
5a68be94 466 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 467 } else if (mr == &io_mem_notdirty) {
468 /* Accesses to code which has previously been translated into a TB show
469 * up in the MMIO path, as accesses to the io_mem_notdirty
470 * MemoryRegion. */
471 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 472 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
473 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 474 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 475 }
164a4dcd 476 *value |= (tmp & mask) << shift;
cc05c43a 477 return r;
164a4dcd
AK		 478}
479
cc05c43a
PM		 480static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
481 hwaddr addr,
482 uint64_t *value,
483 unsigned size,
484 unsigned shift,
485 uint64_t mask,
486 MemTxAttrs attrs)
ce5d2f33 487{
ce5d2f33
PB		 488 uint64_t tmp;
489
490 tmp = (*value >> shift) & mask;
23d92d68 491 if (mr->subpage) {
5a68be94 492 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 493 } else if (mr == &io_mem_notdirty) {
494 /* Accesses to code which has previously been translated into a TB show
495 * up in the MMIO path, as accesses to the io_mem_notdirty
496 * MemoryRegion. */
497 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 498 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
499 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 500 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 501 }
ce5d2f33 502 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
cc05c43a 503 return MEMTX_OK;
ce5d2f33
PB		 504}
505
cc05c43a
PM		 506static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
507 hwaddr addr,
508 uint64_t *value,
509 unsigned size,
510 unsigned shift,
511 uint64_t mask,
512 MemTxAttrs attrs)
164a4dcd 513{
164a4dcd
AK		 514 uint64_t tmp;
515
516 tmp = (*value >> shift) & mask;
23d92d68 517 if (mr->subpage) {
5a68be94 518 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 519 } else if (mr == &io_mem_notdirty) {
520 /* Accesses to code which has previously been translated into a TB show
521 * up in the MMIO path, as accesses to the io_mem_notdirty
522 * MemoryRegion. */
523 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 524 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
525 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 526 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 527 }
164a4dcd 528 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 529 return MEMTX_OK;
164a4dcd
AK		 530}
531
cc05c43a
PM		 532static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
533 hwaddr addr,
534 uint64_t *value,
535 unsigned size,
536 unsigned shift,
537 uint64_t mask,
538 MemTxAttrs attrs)
539{
540 uint64_t tmp;
541
cc05c43a 542 tmp = (*value >> shift) & mask;
23d92d68 543 if (mr->subpage) {
5a68be94 544 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB		 545 } else if (mr == &io_mem_notdirty) {
546 /* Accesses to code which has previously been translated into a TB show
547 * up in the MMIO path, as accesses to the io_mem_notdirty
548 * MemoryRegion. */
549 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB		 550 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
551 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 552 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 553 }
cc05c43a
PM		 554 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
555}
556
557static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK		 558 uint64_t *value,
559 unsigned size,
560 unsigned access_size_min,
561 unsigned access_size_max,
cc05c43a
PM		 562 MemTxResult (*access)(MemoryRegion *mr,
563 hwaddr addr,
564 uint64_t *value,
565 unsigned size,
566 unsigned shift,
567 uint64_t mask,
568 MemTxAttrs attrs),
569 MemoryRegion *mr,
570 MemTxAttrs attrs)
164a4dcd
AK		 571{
572 uint64_t access_mask;
573 unsigned access_size;
574 unsigned i;
cc05c43a 575 MemTxResult r = MEMTX_OK;
164a4dcd
AK		 576
577 if (!access_size_min) {
578 access_size_min = 1;
579 }
580 if (!access_size_max) {
581 access_size_max = 4;
582 }
ce5d2f33
PB		 583
584 /* FIXME: support unaligned access? */
164a4dcd
AK		 585 access_size = MAX(MIN(size, access_size_max), access_size_min);
586 access_mask = -1ULL >> (64 - access_size * 8);
e7342aa3
PB		 587 if (memory_region_big_endian(mr)) {
588 for (i = 0; i < size; i += access_size) {
cc05c43a
PM		 589 r |= access(mr, addr + i, value, access_size,
590 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB		 591 }
592 } else {
593 for (i = 0; i < size; i += access_size) {
cc05c43a
PM		 594 r |= access(mr, addr + i, value, access_size, i * 8,
595 access_mask, attrs);
e7342aa3 596 }
164a4dcd 597 }
cc05c43a 598 return r;
164a4dcd
AK		 599}
600
e2177955
AK		 601static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
602{
0d673e36
AK		 603 AddressSpace *as;
604
feca4ac1
PB		 605 while (mr->container) {
606 mr = mr->container;
e2177955 607 }
0d673e36
AK		 608 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
609 if (mr == as->root) {
610 return as;
611 }
e2177955 612 }
eed2bacf 613 return NULL;
e2177955
AK		 614}
615
093bc2cd
AK		 616/* Render a memory region into the global view. Ranges in @view obscure
617 * ranges in @mr.
618 */
619static void render_memory_region(FlatView *view,
620 MemoryRegion *mr,
08dafab4 621 Int128 base,
fb1cd6f9
AK		 622 AddrRange clip,
623 bool readonly)
093bc2cd
AK		 624{
625 MemoryRegion *subregion;
626 unsigned i;
a8170e5e 627 hwaddr offset_in_region;
08dafab4
AK		 628 Int128 remain;
629 Int128 now;
093bc2cd
AK		 630 FlatRange fr;
631 AddrRange tmp;
632
6bba19ba
AK		 633 if (!mr->enabled) {
634 return;
635 }
636
08dafab4 637 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 638 readonly |= mr->readonly;
093bc2cd
AK		 639
640 tmp = addrrange_make(base, mr->size);
641
642 if (!addrrange_intersects(tmp, clip)) {
643 return;
644 }
645
646 clip = addrrange_intersection(tmp, clip);
647
648 if (mr->alias) {
08dafab4
AK		 649 int128_subfrom(&base, int128_make64(mr->alias->addr));
650 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 651 render_memory_region(view, mr->alias, base, clip, readonly);
093bc2cd
AK		 652 return;
653 }
654
655 /* Render subregions in priority order. */
656 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 657 render_memory_region(view, subregion, base, clip, readonly);
093bc2cd
AK		 658 }
659
14a3c10a 660 if (!mr->terminates) {
093bc2cd
AK		 661 return;
662 }
663
08dafab4 664 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK		 665 base = clip.start;
666 remain = clip.size;
667
2eb74e1a 668 fr.mr = mr;
6f6a5ef3 669 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 670 fr.romd_mode = mr->romd_mode;
2eb74e1a
PC		 671 fr.readonly = readonly;
672
093bc2cd 673 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK		 674 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
675 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK		 676 continue;
677 }
08dafab4
AK		 678 if (int128_lt(base, view->ranges[i].addr.start)) {
679 now = int128_min(remain,
680 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK		 681 fr.offset_in_region = offset_in_region;
682 fr.addr = addrrange_make(base, now);
683 flatview_insert(view, i, &fr);
684 ++i;
08dafab4
AK		 685 int128_addto(&base, now);
686 offset_in_region += int128_get64(now);
687 int128_subfrom(&remain, now);
093bc2cd 688 }
d26a8cae
AK		 689 now = int128_sub(int128_min(int128_add(base, remain),
690 addrrange_end(view->ranges[i].addr)),
691 base);
692 int128_addto(&base, now);
693 offset_in_region += int128_get64(now);
694 int128_subfrom(&remain, now);
093bc2cd 695 }
08dafab4 696 if (int128_nz(remain)) {
093bc2cd
AK		 697 fr.offset_in_region = offset_in_region;
698 fr.addr = addrrange_make(base, remain);
699 flatview_insert(view, i, &fr);
700 }
701}
702
703/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 704static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 705{
a9a0c06d 706 FlatView *view;
093bc2cd 707
a9a0c06d
PB		 708 view = g_new(FlatView, 1);
709 flatview_init(view);
093bc2cd 710
83f3c251 711 if (mr) {
a9a0c06d 712 render_memory_region(view, mr, int128_zero(),
83f3c251
AK		 713 addrrange_make(int128_zero(), int128_2_64()), false);
714 }
a9a0c06d 715 flatview_simplify(view);
093bc2cd
AK		 716
717 return view;
718}
719
3e9d69e7
AK		 720static void address_space_add_del_ioeventfds(AddressSpace *as,
721 MemoryRegionIoeventfd *fds_new,
722 unsigned fds_new_nb,
723 MemoryRegionIoeventfd *fds_old,
724 unsigned fds_old_nb)
725{
726 unsigned iold, inew;
80a1ea37
AK		 727 MemoryRegionIoeventfd *fd;
728 MemoryRegionSection section;
3e9d69e7
AK		 729
730 /* Generate a symmetric difference of the old and new fd sets, adding
731 * and deleting as necessary.
732 */
733
734 iold = inew = 0;
735 while (iold < fds_old_nb || inew < fds_new_nb) {
736 if (iold < fds_old_nb
737 && (inew == fds_new_nb
738 || memory_region_ioeventfd_before(fds_old[iold],
739 fds_new[inew]))) {
80a1ea37
AK		 740 fd = &fds_old[iold];
741 section = (MemoryRegionSection) {
f6790af6 742 .address_space = as,
80a1ea37 743 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 744 .size = fd->addr.size,
80a1ea37 745 };
9a54635d 746 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 747 fd->match_data, fd->data, fd->e);
3e9d69e7
AK		 748 ++iold;
749 } else if (inew < fds_new_nb
750 && (iold == fds_old_nb
751 || memory_region_ioeventfd_before(fds_new[inew],
752 fds_old[iold]))) {
80a1ea37
AK		 753 fd = &fds_new[inew];
754 section = (MemoryRegionSection) {
f6790af6 755 .address_space = as,
80a1ea37 756 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 757 .size = fd->addr.size,
80a1ea37 758 };
9a54635d 759 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 760 fd->match_data, fd->data, fd->e);
3e9d69e7
AK		 761 ++inew;
762 } else {
763 ++iold;
764 ++inew;
765 }
766 }
767}
768
856d7245
PB		 769static FlatView *address_space_get_flatview(AddressSpace *as)
770{
771 FlatView *view;
772
374f2981
PB		 773 rcu_read_lock();
774 view = atomic_rcu_read(&as->current_map);
856d7245 775 flatview_ref(view);
374f2981 776 rcu_read_unlock();
856d7245
PB		 777 return view;
778}
779
3e9d69e7
AK		 780static void address_space_update_ioeventfds(AddressSpace *as)
781{
99e86347 782 FlatView *view;
3e9d69e7
AK		 783 FlatRange *fr;
784 unsigned ioeventfd_nb = 0;
785 MemoryRegionIoeventfd *ioeventfds = NULL;
786 AddrRange tmp;
787 unsigned i;
788
856d7245 789 view = address_space_get_flatview(as);
99e86347 790 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK		 791 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
792 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK		 793 int128_sub(fr->addr.start,
794 int128_make64(fr->offset_in_region)));
3e9d69e7
AK		 795 if (addrrange_intersects(fr->addr, tmp)) {
796 ++ioeventfd_nb;
7267c094 797 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK		 798 ioeventfd_nb * sizeof(*ioeventfds));
799 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
800 ioeventfds[ioeventfd_nb-1].addr = tmp;
801 }
802 }
803 }
804
805 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
806 as->ioeventfds, as->ioeventfd_nb);
807
7267c094 808 g_free(as->ioeventfds);
3e9d69e7
AK		 809 as->ioeventfds = ioeventfds;
810 as->ioeventfd_nb = ioeventfd_nb;
856d7245 811 flatview_unref(view);
3e9d69e7
AK		 812}
813
b8af1afb 814static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB		 815 const FlatView *old_view,
816 const FlatView *new_view,
b8af1afb 817 bool adding)
093bc2cd 818{
093bc2cd
AK		 819 unsigned iold, inew;
820 FlatRange *frold, *frnew;
093bc2cd
AK		 821
822 /* Generate a symmetric difference of the old and new memory maps.
823 * Kill ranges in the old map, and instantiate ranges in the new map.
824 */
825 iold = inew = 0;
a9a0c06d
PB		 826 while (iold < old_view->nr || inew < new_view->nr) {
827 if (iold < old_view->nr) {
828 frold = &old_view->ranges[iold];
093bc2cd
AK		 829 } else {
830 frold = NULL;
831 }
a9a0c06d
PB		 832 if (inew < new_view->nr) {
833 frnew = &new_view->ranges[inew];
093bc2cd
AK		 834 } else {
835 frnew = NULL;
836 }
837
838 if (frold
839 && (!frnew
08dafab4
AK		 840 || int128_lt(frold->addr.start, frnew->addr.start)
841 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 842 && !flatrange_equal(frold, frnew)))) {
41a6e477 843 /* In old but not in new, or in both but attributes changed. */
093bc2cd 844
b8af1afb 845 if (!adding) {
72e22d2f 846 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK		 847 }
848
093bc2cd
AK		 849 ++iold;
850 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 851 /* In both and unchanged (except logging may have changed) */
093bc2cd 852
b8af1afb 853 if (adding) {
50c1e149 854 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB		 855 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
856 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
857 frold->dirty_log_mask,
858 frnew->dirty_log_mask);
859 }
860 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
861 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
862 frold->dirty_log_mask,
863 frnew->dirty_log_mask);
b8af1afb 864 }
5a583347
AK		 865 }
866
093bc2cd
AK		 867 ++iold;
868 ++inew;
093bc2cd
AK		 869 } else {
870 /* In new */
871
b8af1afb 872 if (adding) {
72e22d2f 873 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK		 874 }
875
093bc2cd
AK		 876 ++inew;
877 }
878 }
b8af1afb
AK		 879}
880
881
882static void address_space_update_topology(AddressSpace *as)
883{
856d7245 884 FlatView *old_view = address_space_get_flatview(as);
a9a0c06d 885 FlatView *new_view = generate_memory_topology(as->root);
b8af1afb
AK		 886
887 address_space_update_topology_pass(as, old_view, new_view, false);
888 address_space_update_topology_pass(as, old_view, new_view, true);
889
374f2981
PB		 890 /* Writes are protected by the BQL. */
891 atomic_rcu_set(&as->current_map, new_view);
892 call_rcu(old_view, flatview_unref, rcu);
856d7245
PB		 893
894 /* Note that all the old MemoryRegions are still alive up to this
895 * point. This relieves most MemoryListeners from the need to
896 * ref/unref the MemoryRegions they get---unless they use them
897 * outside the iothread mutex, in which case precise reference
898 * counting is necessary.
899 */
900 flatview_unref(old_view);
901
3e9d69e7 902 address_space_update_ioeventfds(as);
093bc2cd
AK		 903}
904
4ef4db86
AK		 905void memory_region_transaction_begin(void)
906{
bb880ded 907 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK		 908 ++memory_region_transaction_depth;
909}
910
911void memory_region_transaction_commit(void)
912{
0d673e36
AK		 913 AddressSpace *as;
914
4ef4db86 915 assert(memory_region_transaction_depth);
8d04fb55
JK		 916 assert(qemu_mutex_iothread_locked());
917
4ef4db86 918 --memory_region_transaction_depth;
4dc56152
GA		 919 if (!memory_region_transaction_depth) {
920 if (memory_region_update_pending) {
921 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 922
4dc56152
GA		 923 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
924 address_space_update_topology(as);
925 }
ade9c1aa 926 memory_region_update_pending = false;
4dc56152
GA		 927 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
928 } else if (ioeventfd_update_pending) {
929 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
930 address_space_update_ioeventfds(as);
931 }
ade9c1aa 932 ioeventfd_update_pending = false;
4dc56152 933 }
4dc56152 934 }
4ef4db86
AK		 935}
936
545e92e0
AK		 937static void memory_region_destructor_none(MemoryRegion *mr)
938{
939}
940
941static void memory_region_destructor_ram(MemoryRegion *mr)
942{
f1060c55 943 qemu_ram_free(mr->ram_block);
545e92e0
AK		 944}
945
b4fefef9
PC		 946static bool memory_region_need_escape(char c)
947{
948 return c == '/' || c == '[' || c == '\\' || c == ']';
949}
950
951static char *memory_region_escape_name(const char *name)
952{
953 const char *p;
954 char *escaped, *q;
955 uint8_t c;
956 size_t bytes = 0;
957
958 for (p = name; *p; p++) {
959 bytes += memory_region_need_escape(*p) ? 4 : 1;
960 }
961 if (bytes == p - name) {
962 return g_memdup(name, bytes + 1);
963 }
964
965 escaped = g_malloc(bytes + 1);
966 for (p = name, q = escaped; *p; p++) {
967 c = *p;
968 if (unlikely(memory_region_need_escape(c))) {
969 *q++ = '\\';
970 *q++ = 'x';
971 *q++ = "0123456789abcdef"[c >> 4];
972 c = "0123456789abcdef"[c & 15];
973 }
974 *q++ = c;
975 }
976 *q = 0;
977 return escaped;
978}
979
3df9d748
AK		 980static void memory_region_do_init(MemoryRegion *mr,
981 Object *owner,
982 const char *name,
983 uint64_t size)
093bc2cd 984{
08dafab4
AK		 985 mr->size = int128_make64(size);
986 if (size == UINT64_MAX) {
987 mr->size = int128_2_64();
988 }
302fa283 989 mr->name = g_strdup(name);
612263cf 990 mr->owner = owner;
58eaa217 991 mr->ram_block = NULL;
b4fefef9
PC		 992
993 if (name) {
843ef73a
PC		 994 char *escaped_name = memory_region_escape_name(name);
995 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB		 996
997 if (!owner) {
998 owner = container_get(qdev_get_machine(), "/unattached");
999 }
1000
843ef73a 1001 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1002 object_unref(OBJECT(mr));
843ef73a
PC		 1003 g_free(name_array);
1004 g_free(escaped_name);
b4fefef9
PC		 1005 }
1006}
1007
3df9d748
AK		 1008void memory_region_init(MemoryRegion *mr,
1009 Object *owner,
1010 const char *name,
1011 uint64_t size)
1012{
1013 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1014 memory_region_do_init(mr, owner, name, size);
1015}
1016
d7bce999
EB		 1017static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1018 void *opaque, Error **errp)
409ddd01
PC		 1019{
1020 MemoryRegion *mr = MEMORY_REGION(obj);
1021 uint64_t value = mr->addr;
1022
51e72bc1 1023 visit_type_uint64(v, name, &value, errp);
409ddd01
PC		 1024}
1025
d7bce999
EB		 1026static void memory_region_get_container(Object *obj, Visitor *v,
1027 const char *name, void *opaque,
1028 Error **errp)
409ddd01
PC		 1029{
1030 MemoryRegion *mr = MEMORY_REGION(obj);
1031 gchar *path = (gchar *)"";
1032
1033 if (mr->container) {
1034 path = object_get_canonical_path(OBJECT(mr->container));
1035 }
51e72bc1 1036 visit_type_str(v, name, &path, errp);
409ddd01
PC		 1037 if (mr->container) {
1038 g_free(path);
1039 }
1040}
1041
1042static Object *memory_region_resolve_container(Object *obj, void *opaque,
1043 const char *part)
1044{
1045 MemoryRegion *mr = MEMORY_REGION(obj);
1046
1047 return OBJECT(mr->container);
1048}
1049
d7bce999
EB		 1050static void memory_region_get_priority(Object *obj, Visitor *v,
1051 const char *name, void *opaque,
1052 Error **errp)
d33382da
PC		 1053{
1054 MemoryRegion *mr = MEMORY_REGION(obj);
1055 int32_t value = mr->priority;
1056
51e72bc1 1057 visit_type_int32(v, name, &value, errp);
d33382da
PC		 1058}
1059
d7bce999
EB		 1060static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1061 void *opaque, Error **errp)
52aef7bb
PC		 1062{
1063 MemoryRegion *mr = MEMORY_REGION(obj);
1064 uint64_t value = memory_region_size(mr);
1065
51e72bc1 1066 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC		 1067}
1068
b4fefef9
PC		 1069static void memory_region_initfn(Object *obj)
1070{
1071 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1072 ObjectProperty *op;
b4fefef9
PC		 1073
1074 mr->ops = &unassigned_mem_ops;
6bba19ba 1075 mr->enabled = true;
5f9a5ea1 1076 mr->romd_mode = true;
196ea131 1077 mr->global_locking = true;
545e92e0 1078 mr->destructor = memory_region_destructor_none;
093bc2cd 1079 QTAILQ_INIT(&mr->subregions);
093bc2cd 1080 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC		 1081
1082 op = object_property_add(OBJECT(mr), "container",
1083 "link<" TYPE_MEMORY_REGION ">",
1084 memory_region_get_container,
1085 NULL, /* memory_region_set_container */
1086 NULL, NULL, &error_abort);
1087 op->resolve = memory_region_resolve_container;
1088
1089 object_property_add(OBJECT(mr), "addr", "uint64",
1090 memory_region_get_addr,
1091 NULL, /* memory_region_set_addr */
1092 NULL, NULL, &error_abort);
d33382da
PC		 1093 object_property_add(OBJECT(mr), "priority", "uint32",
1094 memory_region_get_priority,
1095 NULL, /* memory_region_set_priority */
1096 NULL, NULL, &error_abort);
52aef7bb
PC		 1097 object_property_add(OBJECT(mr), "size", "uint64",
1098 memory_region_get_size,
1099 NULL, /* memory_region_set_size, */
1100 NULL, NULL, &error_abort);
093bc2cd
AK		 1101}
1102
3df9d748
AK		 1103static void iommu_memory_region_initfn(Object *obj)
1104{
1105 MemoryRegion *mr = MEMORY_REGION(obj);
1106
1107 mr->is_iommu = true;
1108}
1109
b018ddf6
PB		 1110static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1111 unsigned size)
1112{
1113#ifdef DEBUG_UNASSIGNED
1114 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1115#endif
4917cf44
AF		 1116 if (current_cpu != NULL) {
1117 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
c658b94f 1118 }
68a7439a 1119 return 0;
b018ddf6
PB		 1120}
1121
1122static void unassigned_mem_write(void *opaque, hwaddr addr,
1123 uint64_t val, unsigned size)
1124{
1125#ifdef DEBUG_UNASSIGNED
1126 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1127#endif
4917cf44
AF		 1128 if (current_cpu != NULL) {
1129 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1130 }
b018ddf6
PB		 1131}
1132
d197063f
PB		 1133static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1134 unsigned size, bool is_write)
1135{
1136 return false;
1137}
1138
1139const MemoryRegionOps unassigned_mem_ops = {
1140 .valid.accepts = unassigned_mem_accepts,
1141 .endianness = DEVICE_NATIVE_ENDIAN,
1142};
1143
4a2e242b
AW		 1144static uint64_t memory_region_ram_device_read(void *opaque,
1145 hwaddr addr, unsigned size)
1146{
1147 MemoryRegion *mr = opaque;
1148 uint64_t data = (uint64_t)~0;
1149
1150 switch (size) {
1151 case 1:
1152 data = *(uint8_t *)(mr->ram_block->host + addr);
1153 break;
1154 case 2:
1155 data = *(uint16_t *)(mr->ram_block->host + addr);
1156 break;
1157 case 4:
1158 data = *(uint32_t *)(mr->ram_block->host + addr);
1159 break;
1160 case 8:
1161 data = *(uint64_t *)(mr->ram_block->host + addr);
1162 break;
1163 }
1164
1165 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1166
1167 return data;
1168}
1169
1170static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1171 uint64_t data, unsigned size)
1172{
1173 MemoryRegion *mr = opaque;
1174
1175 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1176
1177 switch (size) {
1178 case 1:
1179 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1180 break;
1181 case 2:
1182 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1183 break;
1184 case 4:
1185 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1186 break;
1187 case 8:
1188 *(uint64_t *)(mr->ram_block->host + addr) = data;
1189 break;
1190 }
1191}
1192
1193static const MemoryRegionOps ram_device_mem_ops = {
1194 .read = memory_region_ram_device_read,
1195 .write = memory_region_ram_device_write,
c99a29e7 1196 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW		 1197 .valid = {
1198 .min_access_size = 1,
1199 .max_access_size = 8,
1200 .unaligned = true,
1201 },
1202 .impl = {
1203 .min_access_size = 1,
1204 .max_access_size = 8,
1205 .unaligned = true,
1206 },
1207};
1208
d2702032
PB		 1209bool memory_region_access_valid(MemoryRegion *mr,
1210 hwaddr addr,
1211 unsigned size,
1212 bool is_write)
093bc2cd 1213{
a014ed07
PB		 1214 int access_size_min, access_size_max;
1215 int access_size, i;
897fa7cf 1216
093bc2cd
AK		 1217 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1218 return false;
1219 }
1220
a014ed07 1221 if (!mr->ops->valid.accepts) {
093bc2cd
AK		 1222 return true;
1223 }
1224
a014ed07
PB		 1225 access_size_min = mr->ops->valid.min_access_size;
1226 if (!mr->ops->valid.min_access_size) {
1227 access_size_min = 1;
1228 }
1229
1230 access_size_max = mr->ops->valid.max_access_size;
1231 if (!mr->ops->valid.max_access_size) {
1232 access_size_max = 4;
1233 }
1234
1235 access_size = MAX(MIN(size, access_size_max), access_size_min);
1236 for (i = 0; i < size; i += access_size) {
1237 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1238 is_write)) {
1239 return false;
1240 }
093bc2cd 1241 }
a014ed07 1242
093bc2cd
AK		 1243 return true;
1244}
1245
cc05c43a
PM		 1246static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1247 hwaddr addr,
1248 uint64_t *pval,
1249 unsigned size,
1250 MemTxAttrs attrs)
093bc2cd 1251{
cc05c43a 1252 *pval = 0;
093bc2cd 1253
ce5d2f33 1254 if (mr->ops->read) {
cc05c43a
PM		 1255 return access_with_adjusted_size(addr, pval, size,
1256 mr->ops->impl.min_access_size,
1257 mr->ops->impl.max_access_size,
1258 memory_region_read_accessor,
1259 mr, attrs);
1260 } else if (mr->ops->read_with_attrs) {
1261 return access_with_adjusted_size(addr, pval, size,
1262 mr->ops->impl.min_access_size,
1263 mr->ops->impl.max_access_size,
1264 memory_region_read_with_attrs_accessor,
1265 mr, attrs);
ce5d2f33 1266 } else {
cc05c43a
PM		 1267 return access_with_adjusted_size(addr, pval, size, 1, 4,
1268 memory_region_oldmmio_read_accessor,
1269 mr, attrs);
74901c3b 1270 }
093bc2cd
AK		 1271}
1272
3b643495
PM		 1273MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1274 hwaddr addr,
1275 uint64_t *pval,
1276 unsigned size,
1277 MemTxAttrs attrs)
a621f38d 1278{
cc05c43a
PM		 1279 MemTxResult r;
1280
791af8c8
PB		 1281 if (!memory_region_access_valid(mr, addr, size, false)) {
1282 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1283 return MEMTX_DECODE_ERROR;
791af8c8 1284 }
a621f38d 1285
cc05c43a 1286 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1287 adjust_endianness(mr, pval, size);
cc05c43a 1288 return r;
a621f38d 1289}
093bc2cd 1290
8c56c1a5
PF		 1291/* Return true if an eventfd was signalled */
1292static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1293 hwaddr addr,
1294 uint64_t data,
1295 unsigned size,
1296 MemTxAttrs attrs)
1297{
1298 MemoryRegionIoeventfd ioeventfd = {
1299 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1300 .data = data,
1301 };
1302 unsigned i;
1303
1304 for (i = 0; i < mr->ioeventfd_nb; i++) {
1305 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1306 ioeventfd.e = mr->ioeventfds[i].e;
1307
1308 if (memory_region_ioeventfd_equal(ioeventfd, mr->ioeventfds[i])) {
1309 event_notifier_set(ioeventfd.e);
1310 return true;
1311 }
1312 }
1313
1314 return false;
1315}
1316
3b643495
PM		 1317MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1318 hwaddr addr,
1319 uint64_t data,
1320 unsigned size,
1321 MemTxAttrs attrs)
a621f38d 1322{
897fa7cf 1323 if (!memory_region_access_valid(mr, addr, size, true)) {
b018ddf6 1324 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1325 return MEMTX_DECODE_ERROR;
093bc2cd
AK		 1326 }
1327
a621f38d
AK		 1328 adjust_endianness(mr, &data, size);
1329
8c56c1a5
PF		 1330 if ((!kvm_eventfds_enabled()) &&
1331 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1332 return MEMTX_OK;
1333 }
1334
ce5d2f33 1335 if (mr->ops->write) {
cc05c43a
PM		 1336 return access_with_adjusted_size(addr, &data, size,
1337 mr->ops->impl.min_access_size,
1338 mr->ops->impl.max_access_size,
1339 memory_region_write_accessor, mr,
1340 attrs);
1341 } else if (mr->ops->write_with_attrs) {
1342 return
1343 access_with_adjusted_size(addr, &data, size,
1344 mr->ops->impl.min_access_size,
1345 mr->ops->impl.max_access_size,
1346 memory_region_write_with_attrs_accessor,
1347 mr, attrs);
ce5d2f33 1348 } else {
cc05c43a
PM		 1349 return access_with_adjusted_size(addr, &data, size, 1, 4,
1350 memory_region_oldmmio_write_accessor,
1351 mr, attrs);
74901c3b 1352 }
093bc2cd
AK		 1353}
1354
093bc2cd 1355void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1356 Object *owner,
093bc2cd
AK		 1357 const MemoryRegionOps *ops,
1358 void *opaque,
1359 const char *name,
1360 uint64_t size)
1361{
2c9b15ca 1362 memory_region_init(mr, owner, name, size);
6d6d2abf 1363 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1364 mr->opaque = opaque;
14a3c10a 1365 mr->terminates = true;
093bc2cd
AK		 1366}
1367
1cfe48c1
PM		 1368void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1369 Object *owner,
1370 const char *name,
1371 uint64_t size,
1372 Error **errp)
093bc2cd 1373{
2c9b15ca 1374 memory_region_init(mr, owner, name, size);
8ea9252a 1375 mr->ram = true;
14a3c10a 1376 mr->terminates = true;
545e92e0 1377 mr->destructor = memory_region_destructor_ram;
8e41fb63 1378 mr->ram_block = qemu_ram_alloc(size, mr, errp);
677e7805 1379 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
0b183fc8
PB		 1380}
1381
60786ef3
MT		 1382void memory_region_init_resizeable_ram(MemoryRegion *mr,
1383 Object *owner,
1384 const char *name,
1385 uint64_t size,
1386 uint64_t max_size,
1387 void (*resized)(const char*,
1388 uint64_t length,
1389 void *host),
1390 Error **errp)
1391{
1392 memory_region_init(mr, owner, name, size);
1393 mr->ram = true;
1394 mr->terminates = true;
1395 mr->destructor = memory_region_destructor_ram;
8e41fb63
FZ		 1396 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1397 mr, errp);
677e7805 1398 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
60786ef3
MT		 1399}
1400
0b183fc8
PB		 1401#ifdef __linux__
1402void memory_region_init_ram_from_file(MemoryRegion *mr,
1403 struct Object *owner,
1404 const char *name,
1405 uint64_t size,
dbcb8981 1406 bool share,
7f56e740
PB		 1407 const char *path,
1408 Error **errp)
0b183fc8
PB		 1409{
1410 memory_region_init(mr, owner, name, size);
1411 mr->ram = true;
1412 mr->terminates = true;
1413 mr->destructor = memory_region_destructor_ram;
8e41fb63 1414 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
677e7805 1415 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
093bc2cd 1416}
fea617c5
MAL		 1417
1418void memory_region_init_ram_from_fd(MemoryRegion *mr,
1419 struct Object *owner,
1420 const char *name,
1421 uint64_t size,
1422 bool share,
1423 int fd,
1424 Error **errp)
1425{
1426 memory_region_init(mr, owner, name, size);
1427 mr->ram = true;
1428 mr->terminates = true;
1429 mr->destructor = memory_region_destructor_ram;
1430 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1431 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1432}
0b183fc8 1433#endif
093bc2cd
AK		 1434
1435void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1436 Object *owner,
093bc2cd
AK		 1437 const char *name,
1438 uint64_t size,
1439 void *ptr)
1440{
2c9b15ca 1441 memory_region_init(mr, owner, name, size);
8ea9252a 1442 mr->ram = true;
14a3c10a 1443 mr->terminates = true;
fc3e7665 1444 mr->destructor = memory_region_destructor_ram;
677e7805 1445 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT		 1446
1447 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1448 assert(ptr != NULL);
8e41fb63 1449 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK		 1450}
1451
21e00fa5
AW		 1452void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1453 Object *owner,
1454 const char *name,
1455 uint64_t size,
1456 void *ptr)
e4dc3f59 1457{
21e00fa5
AW		 1458 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1459 mr->ram_device = true;
4a2e242b
AW		 1460 mr->ops = &ram_device_mem_ops;
1461 mr->opaque = mr;
e4dc3f59
ND		 1462}
1463
093bc2cd 1464void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1465 Object *owner,
093bc2cd
AK		 1466 const char *name,
1467 MemoryRegion *orig,
a8170e5e 1468 hwaddr offset,
093bc2cd
AK		 1469 uint64_t size)
1470{
2c9b15ca 1471 memory_region_init(mr, owner, name, size);
093bc2cd
AK		 1472 mr->alias = orig;
1473 mr->alias_offset = offset;
1474}
1475
b59821a9
PM		 1476void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1477 struct Object *owner,
1478 const char *name,
1479 uint64_t size,
1480 Error **errp)
a1777f7f
PM		 1481{
1482 memory_region_init(mr, owner, name, size);
1483 mr->ram = true;
1484 mr->readonly = true;
1485 mr->terminates = true;
1486 mr->destructor = memory_region_destructor_ram;
1487 mr->ram_block = qemu_ram_alloc(size, mr, errp);
1488 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1489}
1490
b59821a9
PM		 1491void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1492 Object *owner,
1493 const MemoryRegionOps *ops,
1494 void *opaque,
1495 const char *name,
1496 uint64_t size,
1497 Error **errp)
d0a9b5bc 1498{
39e0b03d 1499 assert(ops);
2c9b15ca 1500 memory_region_init(mr, owner, name, size);
7bc2b9cd 1501 mr->ops = ops;
75f5941c 1502 mr->opaque = opaque;
d0a9b5bc 1503 mr->terminates = true;
75c578dc 1504 mr->rom_device = true;
58268c8d 1505 mr->destructor = memory_region_destructor_ram;
8e41fb63 1506 mr->ram_block = qemu_ram_alloc(size, mr, errp);
d0a9b5bc
AK		 1507}
1508
1221a474
AK		 1509void memory_region_init_iommu(void *_iommu_mr,
1510 size_t instance_size,
1511 const char *mrtypename,
2c9b15ca 1512 Object *owner,
30951157
AK		 1513 const char *name,
1514 uint64_t size)
1515{
1221a474 1516 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK		 1517 struct MemoryRegion *mr;
1518
1221a474
AK		 1519 object_initialize(_iommu_mr, instance_size, mrtypename);
1520 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK		 1521 memory_region_do_init(mr, owner, name, size);
1522 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1523 mr->terminates = true; /* then re-forwards */
3df9d748
AK		 1524 QLIST_INIT(&iommu_mr->iommu_notify);
1525 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK		 1526}
1527
b4fefef9 1528static void memory_region_finalize(Object *obj)
093bc2cd 1529{
b4fefef9
PC		 1530 MemoryRegion *mr = MEMORY_REGION(obj);
1531
2e2b8eb7
PB		 1532 assert(!mr->container);
1533
1534 /* We know the region is not visible in any address space (it
1535 * does not have a container and cannot be a root either because
1536 * it has no references, so we can blindly clear mr->enabled.
1537 * memory_region_set_enabled instead could trigger a transaction
1538 * and cause an infinite loop.
1539 */
1540 mr->enabled = false;
1541 memory_region_transaction_begin();
1542 while (!QTAILQ_EMPTY(&mr->subregions)) {
1543 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1544 memory_region_del_subregion(mr, subregion);
1545 }
1546 memory_region_transaction_commit();
1547
545e92e0 1548 mr->destructor(mr);
093bc2cd 1549 memory_region_clear_coalescing(mr);
302fa283 1550 g_free((char *)mr->name);
7267c094 1551 g_free(mr->ioeventfds);
093bc2cd
AK		 1552}
1553
803c0816
PB		 1554Object *memory_region_owner(MemoryRegion *mr)
1555{
22a893e4
PB		 1556 Object *obj = OBJECT(mr);
1557 return obj->parent;
803c0816
PB		 1558}
1559
46637be2
PB		 1560void memory_region_ref(MemoryRegion *mr)
1561{
22a893e4
PB		 1562 /* MMIO callbacks most likely will access data that belongs
1563 * to the owner, hence the need to ref/unref the owner whenever
1564 * the memory region is in use.
1565 *
1566 * The memory region is a child of its owner. As long as the
1567 * owner doesn't call unparent itself on the memory region,
1568 * ref-ing the owner will also keep the memory region alive.
612263cf
PB		 1569 * Memory regions without an owner are supposed to never go away;
1570 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1571 */
612263cf
PB		 1572 if (mr && mr->owner) {
1573 object_ref(mr->owner);
46637be2
PB		 1574 }
1575}
1576
1577void memory_region_unref(MemoryRegion *mr)
1578{
612263cf
PB		 1579 if (mr && mr->owner) {
1580 object_unref(mr->owner);
46637be2
PB		 1581 }
1582}
1583
093bc2cd
AK		 1584uint64_t memory_region_size(MemoryRegion *mr)
1585{
08dafab4
AK		 1586 if (int128_eq(mr->size, int128_2_64())) {
1587 return UINT64_MAX;
1588 }
1589 return int128_get64(mr->size);
093bc2cd
AK		 1590}
1591
5d546d4b 1592const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1593{
d1dd32af
PC		 1594 if (!mr->name) {
1595 ((MemoryRegion *)mr)->name =
1596 object_get_canonical_path_component(OBJECT(mr));
1597 }
302fa283 1598 return mr->name;
8991c79b
AK		 1599}
1600
21e00fa5 1601bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1602{
21e00fa5 1603 return mr->ram_device;
e4dc3f59
ND		 1604}
1605
2d1a35be 1606uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1607{
6f6a5ef3 1608 uint8_t mask = mr->dirty_log_mask;
adaad61c 1609 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB		 1610 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1611 }
1612 return mask;
55043ba3
AK		 1613}
1614
2d1a35be
PB		 1615bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1616{
1617 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1618}
1619
3df9d748 1620static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
5bf3d319
PX		 1621{
1622 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1623 IOMMUNotifier *iommu_notifier;
1221a474 1624 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
5bf3d319 1625
3df9d748 1626 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX		 1627 flags |= iommu_notifier->notifier_flags;
1628 }
1629
1221a474
AK		 1630 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1631 imrc->notify_flag_changed(iommu_mr,
1632 iommu_mr->iommu_notify_flags,
1633 flags);
5bf3d319
PX		 1634 }
1635
3df9d748 1636 iommu_mr->iommu_notify_flags = flags;
5bf3d319
PX		 1637}
1638
cdb30812
PX		 1639void memory_region_register_iommu_notifier(MemoryRegion *mr,
1640 IOMMUNotifier *n)
06866575 1641{
3df9d748
AK		 1642 IOMMUMemoryRegion *iommu_mr;
1643
efcd38c5
JW		 1644 if (mr->alias) {
1645 memory_region_register_iommu_notifier(mr->alias, n);
1646 return;
1647 }
1648
cdb30812 1649 /* We need to register for at least one bitfield */
3df9d748 1650 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1651 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1652 assert(n->start <= n->end);
3df9d748
AK		 1653 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1654 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG		 1655}
1656
3df9d748 1657uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1658{
1221a474
AK		 1659 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1660
1661 if (imrc->get_min_page_size) {
1662 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK		 1663 }
1664 return TARGET_PAGE_SIZE;
1665}
1666
3df9d748 1667void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1668{
3df9d748 1669 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1670 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1671 hwaddr addr, granularity;
a788f227
DG		 1672 IOMMUTLBEntry iotlb;
1673
faa362e3 1674 /* If the IOMMU has its own replay callback, override */
1221a474
AK		 1675 if (imrc->replay) {
1676 imrc->replay(iommu_mr, n);
faa362e3
PX		 1677 return;
1678 }
1679
3df9d748 1680 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1681
a788f227 1682 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1221a474 1683 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE);
a788f227
DG		 1684 if (iotlb.perm != IOMMU_NONE) {
1685 n->notify(n, &iotlb);
1686 }
1687
1688 /* if (2^64 - MR size) < granularity, it's possible to get an
1689 * infinite loop here. This should catch such a wraparound */
1690 if ((addr + granularity) < addr) {
1691 break;
1692 }
1693 }
1694}
1695
3df9d748 1696void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
de472e4a
PX		 1697{
1698 IOMMUNotifier *notifier;
1699
3df9d748
AK		 1700 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1701 memory_region_iommu_replay(iommu_mr, notifier);
de472e4a
PX		 1702 }
1703}
1704
cdb30812
PX		 1705void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1706 IOMMUNotifier *n)
06866575 1707{
3df9d748
AK		 1708 IOMMUMemoryRegion *iommu_mr;
1709
efcd38c5
JW		 1710 if (mr->alias) {
1711 memory_region_unregister_iommu_notifier(mr->alias, n);
1712 return;
1713 }
cdb30812 1714 QLIST_REMOVE(n, node);
3df9d748
AK		 1715 iommu_mr = IOMMU_MEMORY_REGION(mr);
1716 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG		 1717}
1718
bd2bfa4c
PX		 1719void memory_region_notify_one(IOMMUNotifier *notifier,
1720 IOMMUTLBEntry *entry)
06866575 1721{
cdb30812
PX		 1722 IOMMUNotifierFlag request_flags;
1723
bd2bfa4c
PX		 1724 /*
1725 * Skip the notification if the notification does not overlap
1726 * with registered range.
1727 */
1728 if (notifier->start > entry->iova + entry->addr_mask + 1 ||
1729 notifier->end < entry->iova) {
1730 return;
1731 }
cdb30812 1732
bd2bfa4c 1733 if (entry->perm & IOMMU_RW) {
cdb30812
PX		 1734 request_flags = IOMMU_NOTIFIER_MAP;
1735 } else {
1736 request_flags = IOMMU_NOTIFIER_UNMAP;
1737 }
1738
bd2bfa4c
PX		 1739 if (notifier->notifier_flags & request_flags) {
1740 notifier->notify(notifier, entry);
1741 }
1742}
1743
3df9d748 1744void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
bd2bfa4c
PX		 1745 IOMMUTLBEntry entry)
1746{
1747 IOMMUNotifier *iommu_notifier;
1748
3df9d748 1749 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1750
3df9d748 1751 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
bd2bfa4c 1752 memory_region_notify_one(iommu_notifier, &entry);
cdb30812 1753 }
06866575
DG		 1754}
1755
093bc2cd
AK		 1756void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1757{
5a583347 1758 uint8_t mask = 1 << client;
deb809ed 1759 uint8_t old_logging;
5a583347 1760
dbddac6d 1761 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB		 1762 old_logging = mr->vga_logging_count;
1763 mr->vga_logging_count += log ? 1 : -1;
1764 if (!!old_logging == !!mr->vga_logging_count) {
1765 return;
1766 }
1767
59023ef4 1768 memory_region_transaction_begin();
5a583347 1769 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1770 memory_region_update_pending |= mr->enabled;
59023ef4 1771 memory_region_transaction_commit();
093bc2cd
AK		 1772}
1773
a8170e5e
AK		 1774bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1775 hwaddr size, unsigned client)
093bc2cd 1776{
8e41fb63
FZ		 1777 assert(mr->ram_block);
1778 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1779 size, client);
093bc2cd
AK		 1780}
1781
a8170e5e
AK		 1782void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1783 hwaddr size)
093bc2cd 1784{
8e41fb63
FZ		 1785 assert(mr->ram_block);
1786 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1787 size,
58d2707e 1788 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK		 1789}
1790
6c279db8
JQ		 1791bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1792 hwaddr size, unsigned client)
1793{
8e41fb63
FZ		 1794 assert(mr->ram_block);
1795 return cpu_physical_memory_test_and_clear_dirty(
1796 memory_region_get_ram_addr(mr) + addr, size, client);
6c279db8
JQ		 1797}
1798
8deaf12c
GH		 1799DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
1800 hwaddr addr,
1801 hwaddr size,
1802 unsigned client)
1803{
1804 assert(mr->ram_block);
1805 return cpu_physical_memory_snapshot_and_clear_dirty(
1806 memory_region_get_ram_addr(mr) + addr, size, client);
1807}
1808
1809bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
1810 hwaddr addr, hwaddr size)
1811{
1812 assert(mr->ram_block);
1813 return cpu_physical_memory_snapshot_get_dirty(snap,
1814 memory_region_get_ram_addr(mr) + addr, size);
1815}
6c279db8 1816
093bc2cd
AK		 1817void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1818{
0a752eee 1819 MemoryListener *listener;
0d673e36 1820 AddressSpace *as;
0a752eee 1821 FlatView *view;
5a583347
AK		 1822 FlatRange *fr;
1823
0a752eee
PB		 1824 /* If the same address space has multiple log_sync listeners, we
1825 * visit that address space's FlatView multiple times. But because
1826 * log_sync listeners are rare, it's still cheaper than walking each
1827 * address space once.
1828 */
1829 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1830 if (!listener->log_sync) {
1831 continue;
1832 }
1833 as = listener->address_space;
1834 view = address_space_get_flatview(as);
99e86347 1835 FOR_EACH_FLAT_RANGE(fr, view) {
0d673e36 1836 if (fr->mr == mr) {
0a752eee
PB		 1837 MemoryRegionSection mrs = section_from_flat_range(fr, as);
1838 listener->log_sync(listener, &mrs);
0d673e36 1839 }
5a583347 1840 }
856d7245 1841 flatview_unref(view);
5a583347 1842 }
093bc2cd
AK		 1843}
1844
1845void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1846{
fb1cd6f9 1847 if (mr->readonly != readonly) {
59023ef4 1848 memory_region_transaction_begin();
fb1cd6f9 1849 mr->readonly = readonly;
22bde714 1850 memory_region_update_pending |= mr->enabled;
59023ef4 1851 memory_region_transaction_commit();
fb1cd6f9 1852 }
093bc2cd
AK		 1853}
1854
5f9a5ea1 1855void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 1856{
5f9a5ea1 1857 if (mr->romd_mode != romd_mode) {
59023ef4 1858 memory_region_transaction_begin();
5f9a5ea1 1859 mr->romd_mode = romd_mode;
22bde714 1860 memory_region_update_pending |= mr->enabled;
59023ef4 1861 memory_region_transaction_commit();
d0a9b5bc
AK		 1862 }
1863}
1864
a8170e5e
AK		 1865void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
1866 hwaddr size, unsigned client)
093bc2cd 1867{
8e41fb63
FZ		 1868 assert(mr->ram_block);
1869 cpu_physical_memory_test_and_clear_dirty(
1870 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK		 1871}
1872
a35ba7be
PB		 1873int memory_region_get_fd(MemoryRegion *mr)
1874{
4ff87573
PB		 1875 int fd;
1876
1877 rcu_read_lock();
1878 while (mr->alias) {
1879 mr = mr->alias;
a35ba7be 1880 }
4ff87573
PB		 1881 fd = mr->ram_block->fd;
1882 rcu_read_unlock();
a35ba7be 1883
4ff87573
PB		 1884 return fd;
1885}
a35ba7be 1886
093bc2cd
AK		 1887void *memory_region_get_ram_ptr(MemoryRegion *mr)
1888{
49b24afc
PB		 1889 void *ptr;
1890 uint64_t offset = 0;
093bc2cd 1891
49b24afc
PB		 1892 rcu_read_lock();
1893 while (mr->alias) {
1894 offset += mr->alias_offset;
1895 mr = mr->alias;
1896 }
8e41fb63 1897 assert(mr->ram_block);
0878d0e1 1898 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
49b24afc 1899 rcu_read_unlock();
093bc2cd 1900
0878d0e1 1901 return ptr;
093bc2cd
AK		 1902}
1903
07bdaa41
PB		 1904MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
1905{
1906 RAMBlock *block;
1907
1908 block = qemu_ram_block_from_host(ptr, false, offset);
1909 if (!block) {
1910 return NULL;
1911 }
1912
1913 return block->mr;
1914}
1915
7ebb2745
FZ		 1916ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
1917{
1918 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
1919}
1920
37d7c084
PB		 1921void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
1922{
8e41fb63 1923 assert(mr->ram_block);
37d7c084 1924
fa53a0e5 1925 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB		 1926}
1927
0d673e36 1928static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 1929{
99e86347 1930 FlatView *view;
093bc2cd
AK		 1931 FlatRange *fr;
1932 CoalescedMemoryRange *cmr;
1933 AddrRange tmp;
95d2994a 1934 MemoryRegionSection section;
093bc2cd 1935
856d7245 1936 view = address_space_get_flatview(as);
99e86347 1937 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 1938 if (fr->mr == mr) {
95d2994a 1939 section = (MemoryRegionSection) {
f6790af6 1940 .address_space = as,
95d2994a 1941 .offset_within_address_space = int128_get64(fr->addr.start),
052e87b0 1942 .size = fr->addr.size,
95d2994a
AK		 1943 };
1944
9a54635d 1945 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
95d2994a
AK		 1946 int128_get64(fr->addr.start),
1947 int128_get64(fr->addr.size));
093bc2cd
AK		 1948 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
1949 tmp = addrrange_shift(cmr->addr,
08dafab4
AK		 1950 int128_sub(fr->addr.start,
1951 int128_make64(fr->offset_in_region)));
093bc2cd
AK		 1952 if (!addrrange_intersects(tmp, fr->addr)) {
1953 continue;
1954 }
1955 tmp = addrrange_intersection(tmp, fr->addr);
9a54635d 1956 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
95d2994a
AK		 1957 int128_get64(tmp.start),
1958 int128_get64(tmp.size));
093bc2cd
AK		 1959 }
1960 }
1961 }
856d7245 1962 flatview_unref(view);
093bc2cd
AK		 1963}
1964
0d673e36
AK		 1965static void memory_region_update_coalesced_range(MemoryRegion *mr)
1966{
1967 AddressSpace *as;
1968
1969 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1970 memory_region_update_coalesced_range_as(mr, as);
1971 }
1972}
1973
093bc2cd
AK		 1974void memory_region_set_coalescing(MemoryRegion *mr)
1975{
1976 memory_region_clear_coalescing(mr);
08dafab4 1977 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK		 1978}
1979
1980void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 1981 hwaddr offset,
093bc2cd
AK		 1982 uint64_t size)
1983{
7267c094 1984 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 1985
08dafab4 1986 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK		 1987 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
1988 memory_region_update_coalesced_range(mr);
d410515e 1989 memory_region_set_flush_coalesced(mr);
093bc2cd
AK		 1990}
1991
1992void memory_region_clear_coalescing(MemoryRegion *mr)
1993{
1994 CoalescedMemoryRange *cmr;
ab5b3db5 1995 bool updated = false;
093bc2cd 1996
d410515e
JK		 1997 qemu_flush_coalesced_mmio_buffer();
1998 mr->flush_coalesced_mmio = false;
1999
093bc2cd
AK		 2000 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2001 cmr = QTAILQ_FIRST(&mr->coalesced);
2002 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 2003 g_free(cmr);
ab5b3db5
FZ		 2004 updated = true;
2005 }
2006
2007 if (updated) {
2008 memory_region_update_coalesced_range(mr);
093bc2cd 2009 }
093bc2cd
AK		 2010}
2011
d410515e
JK		 2012void memory_region_set_flush_coalesced(MemoryRegion *mr)
2013{
2014 mr->flush_coalesced_mmio = true;
2015}
2016
2017void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2018{
2019 qemu_flush_coalesced_mmio_buffer();
2020 if (QTAILQ_EMPTY(&mr->coalesced)) {
2021 mr->flush_coalesced_mmio = false;
2022 }
2023}
2024
196ea131
JK		 2025void memory_region_set_global_locking(MemoryRegion *mr)
2026{
2027 mr->global_locking = true;
2028}
2029
2030void memory_region_clear_global_locking(MemoryRegion *mr)
2031{
2032 mr->global_locking = false;
2033}
2034
8c56c1a5
PF		 2035static bool userspace_eventfd_warning;
2036
3e9d69e7 2037void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2038 hwaddr addr,
3e9d69e7
AK		 2039 unsigned size,
2040 bool match_data,
2041 uint64_t data,
753d5e14 2042 EventNotifier *e)
3e9d69e7
AK		 2043{
2044 MemoryRegionIoeventfd mrfd = {
08dafab4
AK		 2045 .addr.start = int128_make64(addr),
2046 .addr.size = int128_make64(size),
3e9d69e7
AK		 2047 .match_data = match_data,
2048 .data = data,
753d5e14 2049 .e = e,
3e9d69e7
AK		 2050 };
2051 unsigned i;
2052
8c56c1a5
PF		 2053 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2054 userspace_eventfd_warning))) {
2055 userspace_eventfd_warning = true;
2056 error_report("Using eventfd without MMIO binding in KVM. "
2057 "Suboptimal performance expected");
2058 }
2059
b8aecea2
JW		 2060 if (size) {
2061 adjust_endianness(mr, &mrfd.data, size);
2062 }
59023ef4 2063 memory_region_transaction_begin();
3e9d69e7
AK		 2064 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2065 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
2066 break;
2067 }
2068 }
2069 ++mr->ioeventfd_nb;
7267c094 2070 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK		 2071 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2072 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2073 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2074 mr->ioeventfds[i] = mrfd;
4dc56152 2075 ioeventfd_update_pending |= mr->enabled;
59023ef4 2076 memory_region_transaction_commit();
3e9d69e7
AK		 2077}
2078
2079void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2080 hwaddr addr,
3e9d69e7
AK		 2081 unsigned size,
2082 bool match_data,
2083 uint64_t data,
753d5e14 2084 EventNotifier *e)
3e9d69e7
AK		 2085{
2086 MemoryRegionIoeventfd mrfd = {
08dafab4
AK		 2087 .addr.start = int128_make64(addr),
2088 .addr.size = int128_make64(size),
3e9d69e7
AK		 2089 .match_data = match_data,
2090 .data = data,
753d5e14 2091 .e = e,
3e9d69e7
AK		 2092 };
2093 unsigned i;
2094
b8aecea2
JW		 2095 if (size) {
2096 adjust_endianness(mr, &mrfd.data, size);
2097 }
59023ef4 2098 memory_region_transaction_begin();
3e9d69e7
AK		 2099 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2100 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
2101 break;
2102 }
2103 }
2104 assert(i != mr->ioeventfd_nb);
2105 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2106 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2107 --mr->ioeventfd_nb;
7267c094 2108 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2109 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2110 ioeventfd_update_pending |= mr->enabled;
59023ef4 2111 memory_region_transaction_commit();
3e9d69e7
AK		 2112}
2113
feca4ac1 2114static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2115{
feca4ac1 2116 MemoryRegion *mr = subregion->container;
093bc2cd
AK		 2117 MemoryRegion *other;
2118
59023ef4
JK		 2119 memory_region_transaction_begin();
2120
dfde4e6e 2121 memory_region_ref(subregion);
093bc2cd
AK		 2122 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2123 if (subregion->priority >= other->priority) {
2124 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2125 goto done;
2126 }
2127 }
2128 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2129done:
22bde714 2130 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2131 memory_region_transaction_commit();
093bc2cd
AK		 2132}
2133
0598701a
PC		 2134static void memory_region_add_subregion_common(MemoryRegion *mr,
2135 hwaddr offset,
2136 MemoryRegion *subregion)
2137{
feca4ac1
PB		 2138 assert(!subregion->container);
2139 subregion->container = mr;
0598701a 2140 subregion->addr = offset;
feca4ac1 2141 memory_region_update_container_subregions(subregion);
0598701a 2142}
093bc2cd
AK		 2143
2144void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2145 hwaddr offset,
093bc2cd
AK		 2146 MemoryRegion *subregion)
2147{
093bc2cd
AK		 2148 subregion->priority = 0;
2149 memory_region_add_subregion_common(mr, offset, subregion);
2150}
2151
2152void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2153 hwaddr offset,
093bc2cd 2154 MemoryRegion *subregion,
a1ff8ae0 2155 int priority)
093bc2cd 2156{
093bc2cd
AK		 2157 subregion->priority = priority;
2158 memory_region_add_subregion_common(mr, offset, subregion);
2159}
2160
2161void memory_region_del_subregion(MemoryRegion *mr,
2162 MemoryRegion *subregion)
2163{
59023ef4 2164 memory_region_transaction_begin();
feca4ac1
PB		 2165 assert(subregion->container == mr);
2166 subregion->container = NULL;
093bc2cd 2167 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2168 memory_region_unref(subregion);
22bde714 2169 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2170 memory_region_transaction_commit();
6bba19ba
AK		 2171}
2172
2173void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2174{
2175 if (enabled == mr->enabled) {
2176 return;
2177 }
59023ef4 2178 memory_region_transaction_begin();
6bba19ba 2179 mr->enabled = enabled;
22bde714 2180 memory_region_update_pending = true;
59023ef4 2181 memory_region_transaction_commit();
093bc2cd 2182}
1c0ffa58 2183
e7af4c67
MT		 2184void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2185{
2186 Int128 s = int128_make64(size);
2187
2188 if (size == UINT64_MAX) {
2189 s = int128_2_64();
2190 }
2191 if (int128_eq(s, mr->size)) {
2192 return;
2193 }
2194 memory_region_transaction_begin();
2195 mr->size = s;
2196 memory_region_update_pending = true;
2197 memory_region_transaction_commit();
2198}
2199
67891b8a 2200static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2201{
feca4ac1 2202 MemoryRegion *container = mr->container;
2282e1af 2203
feca4ac1 2204 if (container) {
67891b8a
PC		 2205 memory_region_transaction_begin();
2206 memory_region_ref(mr);
feca4ac1
PB		 2207 memory_region_del_subregion(container, mr);
2208 mr->container = container;
2209 memory_region_update_container_subregions(mr);
67891b8a
PC		 2210 memory_region_unref(mr);
2211 memory_region_transaction_commit();
2282e1af 2212 }
67891b8a 2213}
2282e1af 2214
67891b8a
PC		 2215void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2216{
2217 if (addr != mr->addr) {
2218 mr->addr = addr;
2219 memory_region_readd_subregion(mr);
2220 }
2282e1af
AK		 2221}
2222
a8170e5e 2223void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2224{
4703359e 2225 assert(mr->alias);
4703359e 2226
59023ef4 2227 if (offset == mr->alias_offset) {
4703359e
AK		 2228 return;
2229 }
2230
59023ef4
JK		 2231 memory_region_transaction_begin();
2232 mr->alias_offset = offset;
22bde714 2233 memory_region_update_pending |= mr->enabled;
59023ef4 2234 memory_region_transaction_commit();
4703359e
AK		 2235}
2236
a2b257d6
IM		 2237uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2238{
2239 return mr->align;
2240}
2241
e2177955
AK		 2242static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2243{
2244 const AddrRange *addr = addr_;
2245 const FlatRange *fr = fr_;
2246
2247 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2248 return -1;
2249 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2250 return 1;
2251 }
2252 return 0;
2253}
2254
99e86347 2255static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2256{
99e86347 2257 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK		 2258 sizeof(FlatRange), cmp_flatrange_addr);
2259}
2260
eed2bacf
IM		 2261bool memory_region_is_mapped(MemoryRegion *mr)
2262{
2263 return mr->container ? true : false;
2264}
2265
c6742b14
PB		 2266/* Same as memory_region_find, but it does not add a reference to the
2267 * returned region. It must be called from an RCU critical section.
2268 */
2269static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2270 hwaddr addr, uint64_t size)
e2177955 2271{
052e87b0 2272 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB		 2273 MemoryRegion *root;
2274 AddressSpace *as;
2275 AddrRange range;
99e86347 2276 FlatView *view;
73034e9e
PB		 2277 FlatRange *fr;
2278
2279 addr += mr->addr;
feca4ac1
PB		 2280 for (root = mr; root->container; ) {
2281 root = root->container;
73034e9e
PB		 2282 addr += root->addr;
2283 }
e2177955 2284
73034e9e 2285 as = memory_region_to_address_space(root);
eed2bacf
IM		 2286 if (!as) {
2287 return ret;
2288 }
73034e9e 2289 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2290
2b647668 2291 view = atomic_rcu_read(&as->current_map);
99e86347 2292 fr = flatview_lookup(view, range);
e2177955 2293 if (!fr) {
c6742b14 2294 return ret;
e2177955
AK		 2295 }
2296
99e86347 2297 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK		 2298 --fr;
2299 }
2300
2301 ret.mr = fr->mr;
73034e9e 2302 ret.address_space = as;
e2177955
AK		 2303 range = addrrange_intersection(range, fr->addr);
2304 ret.offset_within_region = fr->offset_in_region;
2305 ret.offset_within_region += int128_get64(int128_sub(range.start,
2306 fr->addr.start));
052e87b0 2307 ret.size = range.size;
e2177955 2308 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2309 ret.readonly = fr->readonly;
c6742b14
PB		 2310 return ret;
2311}
2312
2313MemoryRegionSection memory_region_find(MemoryRegion *mr,
2314 hwaddr addr, uint64_t size)
2315{
2316 MemoryRegionSection ret;
2317 rcu_read_lock();
2318 ret = memory_region_find_rcu(mr, addr, size);
2319 if (ret.mr) {
2320 memory_region_ref(ret.mr);
2321 }
2b647668 2322 rcu_read_unlock();
e2177955
AK		 2323 return ret;
2324}
2325
c6742b14
PB		 2326bool memory_region_present(MemoryRegion *container, hwaddr addr)
2327{
2328 MemoryRegion *mr;
2329
2330 rcu_read_lock();
2331 mr = memory_region_find_rcu(container, addr, 1).mr;
2332 rcu_read_unlock();
2333 return mr && mr != container;
2334}
2335
9c1f8f44 2336void memory_global_dirty_log_sync(void)
86e775c6 2337{
9c1f8f44
PB		 2338 MemoryListener *listener;
2339 AddressSpace *as;
99e86347 2340 FlatView *view;
7664e80c
AK		 2341 FlatRange *fr;
2342
9c1f8f44
PB		 2343 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2344 if (!listener->log_sync) {
2345 continue;
2346 }
d45fa784 2347 as = listener->address_space;
9c1f8f44
PB		 2348 view = address_space_get_flatview(as);
2349 FOR_EACH_FLAT_RANGE(fr, view) {
adaad61c
PB		 2350 if (fr->dirty_log_mask) {
2351 MemoryRegionSection mrs = section_from_flat_range(fr, as);
2352 listener->log_sync(listener, &mrs);
2353 }
9c1f8f44
PB		 2354 }
2355 flatview_unref(view);
7664e80c
AK		 2356 }
2357}
2358
2359void memory_global_dirty_log_start(void)
2360{
7664e80c 2361 global_dirty_log = true;
6f6a5ef3 2362
7376e582 2363 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3
PB		 2364
2365 /* Refresh DIRTY_LOG_MIGRATION bit. */
2366 memory_region_transaction_begin();
2367 memory_region_update_pending = true;
2368 memory_region_transaction_commit();
7664e80c
AK		 2369}
2370
2371void memory_global_dirty_log_stop(void)
2372{
7664e80c 2373 global_dirty_log = false;
6f6a5ef3
PB		 2374
2375 /* Refresh DIRTY_LOG_MIGRATION bit. */
2376 memory_region_transaction_begin();
2377 memory_region_update_pending = true;
2378 memory_region_transaction_commit();
2379
7376e582 2380 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK		 2381}
2382
2383static void listener_add_address_space(MemoryListener *listener,
2384 AddressSpace *as)
2385{
99e86347 2386 FlatView *view;
7664e80c
AK		 2387 FlatRange *fr;
2388
680a4783
PB		 2389 if (listener->begin) {
2390 listener->begin(listener);
2391 }
7664e80c 2392 if (global_dirty_log) {
975aefe0
AK		 2393 if (listener->log_global_start) {
2394 listener->log_global_start(listener);
2395 }
7664e80c 2396 }
975aefe0 2397
856d7245 2398 view = address_space_get_flatview(as);
99e86347 2399 FOR_EACH_FLAT_RANGE(fr, view) {
7664e80c
AK		 2400 MemoryRegionSection section = {
2401 .mr = fr->mr,
f6790af6 2402 .address_space = as,
7664e80c 2403 .offset_within_region = fr->offset_in_region,
052e87b0 2404 .size = fr->addr.size,
7664e80c 2405 .offset_within_address_space = int128_get64(fr->addr.start),
7a8499e8 2406 .readonly = fr->readonly,
7664e80c 2407 };
680a4783
PB		 2408 if (fr->dirty_log_mask && listener->log_start) {
2409 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2410 }
975aefe0
AK		 2411 if (listener->region_add) {
2412 listener->region_add(listener, &section);
2413 }
7664e80c 2414 }
680a4783
PB		 2415 if (listener->commit) {
2416 listener->commit(listener);
2417 }
856d7245 2418 flatview_unref(view);
7664e80c
AK		 2419}
2420
d45fa784 2421void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2422{
72e22d2f
AK		 2423 MemoryListener *other = NULL;
2424
d45fa784 2425 listener->address_space = as;
72e22d2f
AK		 2426 if (QTAILQ_EMPTY(&memory_listeners)
2427 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2428 memory_listeners)->priority) {
2429 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2430 } else {
2431 QTAILQ_FOREACH(other, &memory_listeners, link) {
2432 if (listener->priority < other->priority) {
2433 break;
2434 }
2435 }
2436 QTAILQ_INSERT_BEFORE(other, listener, link);
2437 }
0d673e36 2438
9a54635d
PB		 2439 if (QTAILQ_EMPTY(&as->listeners)
2440 || listener->priority >= QTAILQ_LAST(&as->listeners,
2441 memory_listeners)->priority) {
2442 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2443 } else {
2444 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2445 if (listener->priority < other->priority) {
2446 break;
2447 }
2448 }
2449 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2450 }
2451
d45fa784 2452 listener_add_address_space(listener, as);
7664e80c
AK		 2453}
2454
2455void memory_listener_unregister(MemoryListener *listener)
2456{
1d8280c1
PB		 2457 if (!listener->address_space) {
2458 return;
2459 }
2460
72e22d2f 2461 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2462 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2463 listener->address_space = NULL;
86e775c6 2464}
e2177955 2465
c9356746
FK		 2466bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2467{
2468 void *host;
2469 unsigned size = 0;
2470 unsigned offset = 0;
2471 Object *new_interface;
2472
2473 if (!mr || !mr->ops->request_ptr) {
2474 return false;
2475 }
2476
2477 /*
2478 * Avoid an update if the request_ptr call
2479 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2480 * a cache.
2481 */
2482 memory_region_transaction_begin();
2483
2484 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2485
2486 if (!host || !size) {
2487 memory_region_transaction_commit();
2488 return false;
2489 }
2490
2491 new_interface = object_new("mmio_interface");
2492 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2493 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2494 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2495 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2496 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2497 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2498
2499 memory_region_transaction_commit();
2500 return true;
2501}
2502
2503typedef struct MMIOPtrInvalidate {
2504 MemoryRegion *mr;
2505 hwaddr offset;
2506 unsigned size;
2507 int busy;
2508 int allocated;
2509} MMIOPtrInvalidate;
2510
2511#define MAX_MMIO_INVALIDATE 10
2512static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2513
2514static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2515 run_on_cpu_data data)
2516{
2517 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2518 MemoryRegion *mr = invalidate_data->mr;
2519 hwaddr offset = invalidate_data->offset;
2520 unsigned size = invalidate_data->size;
2521 MemoryRegionSection section = memory_region_find(mr, offset, size);
2522
2523 qemu_mutex_lock_iothread();
2524
2525 /* Reset dirty so this doesn't happen later. */
2526 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2527
2528 if (section.mr != mr) {
2529 /* memory_region_find add a ref on section.mr */
2530 memory_region_unref(section.mr);
2531 if (MMIO_INTERFACE(section.mr->owner)) {
2532 /* We found the interface just drop it. */
2533 object_property_set_bool(section.mr->owner, false, "realized",
2534 NULL);
2535 object_unref(section.mr->owner);
2536 object_unparent(section.mr->owner);
2537 }
2538 }
2539
2540 qemu_mutex_unlock_iothread();
2541
2542 if (invalidate_data->allocated) {
2543 g_free(invalidate_data);
2544 } else {
2545 invalidate_data->busy = 0;
2546 }
2547}
2548
2549void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2550 unsigned size)
2551{
2552 size_t i;
2553 MMIOPtrInvalidate *invalidate_data = NULL;
2554
2555 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2556 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2557 invalidate_data = &mmio_ptr_invalidate_list[i];
2558 break;
2559 }
2560 }
2561
2562 if (!invalidate_data) {
2563 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2564 invalidate_data->allocated = 1;
2565 }
2566
2567 invalidate_data->mr = mr;
2568 invalidate_data->offset = offset;
2569 invalidate_data->size = size;
2570
2571 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2572 RUN_ON_CPU_HOST_PTR(invalidate_data));
2573}
2574
7dca8043 2575void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2576{
ac95190e 2577 memory_region_ref(root);
59023ef4 2578 memory_region_transaction_begin();
f0c02d15 2579 as->ref_count = 1;
8786db7c 2580 as->root = root;
f0c02d15 2581 as->malloced = false;
8786db7c
AK		 2582 as->current_map = g_new(FlatView, 1);
2583 flatview_init(as->current_map);
4c19eb72
AK		 2584 as->ioeventfd_nb = 0;
2585 as->ioeventfds = NULL;
9a54635d 2586 QTAILQ_INIT(&as->listeners);
0d673e36 2587 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2588 as->name = g_strdup(name ? name : "anonymous");
ac1970fb 2589 address_space_init_dispatch(as);
f43793c7
PB		 2590 memory_region_update_pending |= root->enabled;
2591 memory_region_transaction_commit();
1c0ffa58 2592}
658b2224 2593
374f2981 2594static void do_address_space_destroy(AddressSpace *as)
83f3c251 2595{
f0c02d15 2596 bool do_free = as->malloced;
078c44f4 2597
83f3c251 2598 address_space_destroy_dispatch(as);
9a54635d 2599 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2600
856d7245 2601 flatview_unref(as->current_map);
7dca8043 2602 g_free(as->name);
4c19eb72 2603 g_free(as->ioeventfds);
ac95190e 2604 memory_region_unref(as->root);
f0c02d15
PC		 2605 if (do_free) {
2606 g_free(as);
2607 }
2608}
2609
2610AddressSpace *address_space_init_shareable(MemoryRegion *root, const char *name)
2611{
2612 AddressSpace *as;
2613
2614 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2615 if (root == as->root && as->malloced) {
2616 as->ref_count++;
2617 return as;
2618 }
2619 }
2620
2621 as = g_malloc0(sizeof *as);
2622 address_space_init(as, root, name);
2623 as->malloced = true;
2624 return as;
83f3c251
AK		 2625}
2626
374f2981
PB		 2627void address_space_destroy(AddressSpace *as)
2628{
ac95190e
PB		 2629 MemoryRegion *root = as->root;
2630
f0c02d15
PC		 2631 as->ref_count--;
2632 if (as->ref_count) {
2633 return;
2634 }
374f2981
PB		 2635 /* Flush out anything from MemoryListeners listening in on this */
2636 memory_region_transaction_begin();
2637 as->root = NULL;
2638 memory_region_transaction_commit();
2639 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
6e48e8f9 2640 address_space_unregister(as);
374f2981
PB		 2641
2642 /* At this point, as->dispatch and as->current_map are dummy
2643 * entries that the guest should never use. Wait for the old
2644 * values to expire before freeing the data.
2645 */
ac95190e 2646 as->root = root;
374f2981
PB		 2647 call_rcu(as, do_address_space_destroy, rcu);
2648}
2649
4e831901
PX		 2650static const char *memory_region_type(MemoryRegion *mr)
2651{
2652 if (memory_region_is_ram_device(mr)) {
2653 return "ramd";
2654 } else if (memory_region_is_romd(mr)) {
2655 return "romd";
2656 } else if (memory_region_is_rom(mr)) {
2657 return "rom";
2658 } else if (memory_region_is_ram(mr)) {
2659 return "ram";
2660 } else {
2661 return "i/o";
2662 }
2663}
2664
314e2987
BS		 2665typedef struct MemoryRegionList MemoryRegionList;
2666
2667struct MemoryRegionList {
2668 const MemoryRegion *mr;
314e2987
BS		 2669 QTAILQ_ENTRY(MemoryRegionList) queue;
2670};
2671
2672typedef QTAILQ_HEAD(queue, MemoryRegionList) MemoryRegionListHead;
2673
4e831901
PX		 2674#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2675 int128_sub((size), int128_one())) : 0)
2676#define MTREE_INDENT " "
2677
314e2987
BS		 2678static void mtree_print_mr(fprintf_function mon_printf, void *f,
2679 const MemoryRegion *mr, unsigned int level,
a8170e5e 2680 hwaddr base,
9479c57a 2681 MemoryRegionListHead *alias_print_queue)
314e2987 2682{
9479c57a
JK		 2683 MemoryRegionList *new_ml, *ml, *next_ml;
2684 MemoryRegionListHead submr_print_queue;
314e2987
BS		 2685 const MemoryRegion *submr;
2686 unsigned int i;
b31f8412 2687 hwaddr cur_start, cur_end;
314e2987 2688
f8a9f720 2689 if (!mr) {
314e2987
BS		 2690 return;
2691 }
2692
2693 for (i = 0; i < level; i++) {
4e831901 2694 mon_printf(f, MTREE_INDENT);
314e2987
BS		 2695 }
2696
b31f8412
PX		 2697 cur_start = base + mr->addr;
2698 cur_end = cur_start + MR_SIZE(mr->size);
2699
2700 /*
2701 * Try to detect overflow of memory region. This should never
2702 * happen normally. When it happens, we dump something to warn the
2703 * user who is observing this.
2704 */
2705 if (cur_start < base || cur_end < cur_start) {
2706 mon_printf(f, "[DETECTED OVERFLOW!] ");
2707 }
2708
314e2987
BS		 2709 if (mr->alias) {
2710 MemoryRegionList *ml;
2711 bool found = false;
2712
2713 /* check if the alias is already in the queue */
9479c57a 2714 QTAILQ_FOREACH(ml, alias_print_queue, queue) {
f54bb15f 2715 if (ml->mr == mr->alias) {
314e2987
BS		 2716 found = true;
2717 }
2718 }
2719
2720 if (!found) {
2721 ml = g_new(MemoryRegionList, 1);
2722 ml->mr = mr->alias;
9479c57a 2723 QTAILQ_INSERT_TAIL(alias_print_queue, ml, queue);
314e2987 2724 }
4896d74b 2725 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
4e831901 2726 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
f8a9f720 2727 "-" TARGET_FMT_plx "%s\n",
b31f8412 2728 cur_start, cur_end,
4b474ba7 2729 mr->priority,
4e831901 2730 memory_region_type((MemoryRegion *)mr),
3fb18b4d
PC		 2731 memory_region_name(mr),
2732 memory_region_name(mr->alias),
314e2987 2733 mr->alias_offset,
4e831901 2734 mr->alias_offset + MR_SIZE(mr->size),
f8a9f720 2735 mr->enabled ? "" : " [disabled]");
314e2987 2736 } else {
4896d74b 2737 mon_printf(f,
4e831901 2738 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
b31f8412 2739 cur_start, cur_end,
4b474ba7 2740 mr->priority,
4e831901 2741 memory_region_type((MemoryRegion *)mr),
f8a9f720
GH		 2742 memory_region_name(mr),
2743 mr->enabled ? "" : " [disabled]");
314e2987 2744 }
9479c57a
JK		 2745
2746 QTAILQ_INIT(&submr_print_queue);
2747
314e2987 2748 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK		 2749 new_ml = g_new(MemoryRegionList, 1);
2750 new_ml->mr = submr;
2751 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
2752 if (new_ml->mr->addr < ml->mr->addr ||
2753 (new_ml->mr->addr == ml->mr->addr &&
2754 new_ml->mr->priority > ml->mr->priority)) {
2755 QTAILQ_INSERT_BEFORE(ml, new_ml, queue);
2756 new_ml = NULL;
2757 break;
2758 }
2759 }
2760 if (new_ml) {
2761 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, queue);
2762 }
2763 }
2764
2765 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
b31f8412 2766 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
9479c57a
JK		 2767 alias_print_queue);
2768 }
2769
88365e47 2770 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, queue, next_ml) {
9479c57a 2771 g_free(ml);
314e2987
BS		 2772 }
2773}
2774
57bb40c9
PX		 2775static void mtree_print_flatview(fprintf_function p, void *f,
2776 AddressSpace *as)
2777{
2778 FlatView *view = address_space_get_flatview(as);
2779 FlatRange *range = &view->ranges[0];
2780 MemoryRegion *mr;
2781 int n = view->nr;
2782
2783 if (n <= 0) {
2784 p(f, MTREE_INDENT "No rendered FlatView for "
2785 "address space '%s'\n", as->name);
2786 flatview_unref(view);
2787 return;
2788 }
2789
2790 while (n--) {
2791 mr = range->mr;
377a07aa
PB		 2792 if (range->offset_in_region) {
2793 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2794 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
2795 int128_get64(range->addr.start),
2796 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2797 mr->priority,
2798 range->readonly ? "rom" : memory_region_type(mr),
2799 memory_region_name(mr),
2800 range->offset_in_region);
2801 } else {
2802 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2803 TARGET_FMT_plx " (prio %d, %s): %s\n",
2804 int128_get64(range->addr.start),
2805 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2806 mr->priority,
2807 range->readonly ? "rom" : memory_region_type(mr),
2808 memory_region_name(mr));
2809 }
57bb40c9
PX		 2810 range++;
2811 }
2812
2813 flatview_unref(view);
2814}
2815
2816void mtree_info(fprintf_function mon_printf, void *f, bool flatview)
314e2987
BS		 2817{
2818 MemoryRegionListHead ml_head;
2819 MemoryRegionList *ml, *ml2;
0d673e36 2820 AddressSpace *as;
314e2987 2821
57bb40c9
PX		 2822 if (flatview) {
2823 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2824 mon_printf(f, "address-space (flat view): %s\n", as->name);
2825 mtree_print_flatview(mon_printf, f, as);
2826 mon_printf(f, "\n");
2827 }
2828 return;
2829 }
2830
314e2987
BS		 2831 QTAILQ_INIT(&ml_head);
2832
0d673e36 2833 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
e48816aa
GH		 2834 mon_printf(f, "address-space: %s\n", as->name);
2835 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
2836 mon_printf(f, "\n");
b9f9be88
BS		 2837 }
2838
314e2987
BS		 2839 /* print aliased regions */
2840 QTAILQ_FOREACH(ml, &ml_head, queue) {
e48816aa
GH		 2841 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
2842 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
2843 mon_printf(f, "\n");
314e2987
BS		 2844 }
2845
2846 QTAILQ_FOREACH_SAFE(ml, &ml_head, queue, ml2) {
88365e47 2847 g_free(ml);
314e2987 2848 }
314e2987 2849}
b4fefef9
PC		 2850
2851static const TypeInfo memory_region_info = {
2852 .parent = TYPE_OBJECT,
2853 .name = TYPE_MEMORY_REGION,
2854 .instance_size = sizeof(MemoryRegion),
2855 .instance_init = memory_region_initfn,
2856 .instance_finalize = memory_region_finalize,
2857};
2858
3df9d748
AK		 2859static const TypeInfo iommu_memory_region_info = {
2860 .parent = TYPE_MEMORY_REGION,
2861 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 2862 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK		 2863 .instance_size = sizeof(IOMMUMemoryRegion),
2864 .instance_init = iommu_memory_region_initfn,
1221a474 2865 .abstract = true,
3df9d748
AK		 2866};
2867
b4fefef9
PC		 2868static void memory_register_types(void)
2869{
2870 type_register_static(&memory_region_info);
3df9d748 2871 type_register_static(&iommu_memory_region_info);
b4fefef9
PC		 2872}
2873
2874type_init(memory_register_types)
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