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memory: Move FlatView allocation to a helper
[mirror_qemu.git] / memory.c
CommitLineData
093bc2cd
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1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
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14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879
PB
18#include "qemu-common.h"
19#include "cpu.h"
022c62cb
PB
20#include "exec/memory.h"
21#include "exec/address-spaces.h"
22#include "exec/ioport.h"
409ddd01 23#include "qapi/visitor.h"
1de7afc9 24#include "qemu/bitops.h"
8c56c1a5 25#include "qemu/error-report.h"
2c9b15ca 26#include "qom/object.h"
0ab8ed18 27#include "trace-root.h"
093bc2cd 28
022c62cb 29#include "exec/memory-internal.h"
220c3ebd 30#include "exec/ram_addr.h"
8c56c1a5 31#include "sysemu/kvm.h"
e1c57ab8 32#include "sysemu/sysemu.h"
c9356746
FK
33#include "hw/misc/mmio_interface.h"
34#include "hw/qdev-properties.h"
b08199c6 35#include "migration/vmstate.h"
67d95c15 36
d197063f
PB
37//#define DEBUG_UNASSIGNED
38
22bde714
JK
39static unsigned memory_region_transaction_depth;
40static bool memory_region_update_pending;
4dc56152 41static bool ioeventfd_update_pending;
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42static bool global_dirty_log = false;
43
72e22d2f
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44static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
45 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 46
0d673e36
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47static QTAILQ_HEAD(, AddressSpace) address_spaces
48 = QTAILQ_HEAD_INITIALIZER(address_spaces);
49
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50typedef struct AddrRange AddrRange;
51
8417cebf 52/*
c9cdaa3a 53 * Note that signed integers are needed for negative offsetting in aliases
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54 * (large MemoryRegion::alias_offset).
55 */
093bc2cd 56struct AddrRange {
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57 Int128 start;
58 Int128 size;
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59};
60
08dafab4 61static AddrRange addrrange_make(Int128 start, Int128 size)
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62{
63 return (AddrRange) { start, size };
64}
65
66static bool addrrange_equal(AddrRange r1, AddrRange r2)
67{
08dafab4 68 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
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69}
70
08dafab4 71static Int128 addrrange_end(AddrRange r)
093bc2cd 72{
08dafab4 73 return int128_add(r.start, r.size);
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74}
75
08dafab4 76static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 77{
08dafab4 78 int128_addto(&range.start, delta);
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79 return range;
80}
81
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82static bool addrrange_contains(AddrRange range, Int128 addr)
83{
84 return int128_ge(addr, range.start)
85 && int128_lt(addr, addrrange_end(range));
86}
87
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88static bool addrrange_intersects(AddrRange r1, AddrRange r2)
89{
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AK
90 return addrrange_contains(r1, r2.start)
91 || addrrange_contains(r2, r1.start);
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92}
93
94static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
95{
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96 Int128 start = int128_max(r1.start, r2.start);
97 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
98 return addrrange_make(start, int128_sub(end, start));
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99}
100
0e0d36b4
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101enum ListenerDirection { Forward, Reverse };
102
7376e582 103#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
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104 do { \
105 MemoryListener *_listener; \
106 \
107 switch (_direction) { \
108 case Forward: \
109 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
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110 if (_listener->_callback) { \
111 _listener->_callback(_listener, ##_args); \
112 } \
0e0d36b4
AK
113 } \
114 break; \
115 case Reverse: \
116 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
117 memory_listeners, link) { \
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118 if (_listener->_callback) { \
119 _listener->_callback(_listener, ##_args); \
120 } \
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121 } \
122 break; \
123 default: \
124 abort(); \
125 } \
126 } while (0)
127
9a54635d 128#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
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129 do { \
130 MemoryListener *_listener; \
9a54635d 131 struct memory_listeners_as *list = &(_as)->listeners; \
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132 \
133 switch (_direction) { \
134 case Forward: \
9a54635d
PB
135 QTAILQ_FOREACH(_listener, list, link_as) { \
136 if (_listener->_callback) { \
7376e582
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137 _listener->_callback(_listener, _section, ##_args); \
138 } \
139 } \
140 break; \
141 case Reverse: \
9a54635d
PB
142 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
143 link_as) { \
144 if (_listener->_callback) { \
7376e582
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145 _listener->_callback(_listener, _section, ##_args); \
146 } \
147 } \
148 break; \
149 default: \
150 abort(); \
151 } \
152 } while (0)
153
dfde4e6e 154/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 155#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44
PB
156 do { \
157 MemoryRegionSection mrs = section_from_flat_range(fr, as); \
9a54635d 158 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 159 } while(0)
0e0d36b4 160
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161struct CoalescedMemoryRange {
162 AddrRange addr;
163 QTAILQ_ENTRY(CoalescedMemoryRange) link;
164};
165
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166struct MemoryRegionIoeventfd {
167 AddrRange addr;
168 bool match_data;
169 uint64_t data;
753d5e14 170 EventNotifier *e;
3e9d69e7
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171};
172
173static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
174 MemoryRegionIoeventfd b)
175{
08dafab4 176 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 177 return true;
08dafab4 178 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 179 return false;
08dafab4 180 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 181 return true;
08dafab4 182 } else if (int128_gt(a.addr.size, b.addr.size)) {
3e9d69e7
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183 return false;
184 } else if (a.match_data < b.match_data) {
185 return true;
186 } else if (a.match_data > b.match_data) {
187 return false;
188 } else if (a.match_data) {
189 if (a.data < b.data) {
190 return true;
191 } else if (a.data > b.data) {
192 return false;
193 }
194 }
753d5e14 195 if (a.e < b.e) {
3e9d69e7 196 return true;
753d5e14 197 } else if (a.e > b.e) {
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198 return false;
199 }
200 return false;
201}
202
203static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
204 MemoryRegionIoeventfd b)
205{
206 return !memory_region_ioeventfd_before(a, b)
207 && !memory_region_ioeventfd_before(b, a);
208}
209
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210typedef struct FlatRange FlatRange;
211typedef struct FlatView FlatView;
212
213/* Range of memory in the global map. Addresses are absolute. */
214struct FlatRange {
215 MemoryRegion *mr;
a8170e5e 216 hwaddr offset_in_region;
093bc2cd 217 AddrRange addr;
5a583347 218 uint8_t dirty_log_mask;
b138e654 219 bool romd_mode;
fb1cd6f9 220 bool readonly;
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221};
222
223/* Flattened global view of current active memory hierarchy. Kept in sorted
224 * order.
225 */
226struct FlatView {
374f2981 227 struct rcu_head rcu;
856d7245 228 unsigned ref;
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229 FlatRange *ranges;
230 unsigned nr;
231 unsigned nr_allocated;
232};
233
cc31e6e7
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234typedef struct AddressSpaceOps AddressSpaceOps;
235
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236#define FOR_EACH_FLAT_RANGE(var, view) \
237 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
238
9c1f8f44
PB
239static inline MemoryRegionSection
240section_from_flat_range(FlatRange *fr, AddressSpace *as)
241{
242 return (MemoryRegionSection) {
243 .mr = fr->mr,
244 .address_space = as,
245 .offset_within_region = fr->offset_in_region,
246 .size = fr->addr.size,
247 .offset_within_address_space = int128_get64(fr->addr.start),
248 .readonly = fr->readonly,
249 };
250}
251
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252static bool flatrange_equal(FlatRange *a, FlatRange *b)
253{
254 return a->mr == b->mr
255 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 256 && a->offset_in_region == b->offset_in_region
b138e654 257 && a->romd_mode == b->romd_mode
fb1cd6f9 258 && a->readonly == b->readonly;
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259}
260
cc94cd6d 261static FlatView *flatview_new(void)
093bc2cd 262{
cc94cd6d
AK
263 FlatView *view;
264
265 view = g_new0(FlatView, 1);
856d7245 266 view->ref = 1;
cc94cd6d
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267
268 return view;
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269}
270
271/* Insert a range into a given position. Caller is responsible for maintaining
272 * sorting order.
273 */
274static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
275{
276 if (view->nr == view->nr_allocated) {
277 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 278 view->ranges = g_realloc(view->ranges,
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AK
279 view->nr_allocated * sizeof(*view->ranges));
280 }
281 memmove(view->ranges + pos + 1, view->ranges + pos,
282 (view->nr - pos) * sizeof(FlatRange));
283 view->ranges[pos] = *range;
dfde4e6e 284 memory_region_ref(range->mr);
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285 ++view->nr;
286}
287
288static void flatview_destroy(FlatView *view)
289{
dfde4e6e
PB
290 int i;
291
292 for (i = 0; i < view->nr; i++) {
293 memory_region_unref(view->ranges[i].mr);
294 }
7267c094 295 g_free(view->ranges);
a9a0c06d 296 g_free(view);
093bc2cd
AK
297}
298
447b0d0b 299static bool flatview_ref(FlatView *view)
856d7245 300{
447b0d0b 301 return atomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB
302}
303
304static void flatview_unref(FlatView *view)
305{
306 if (atomic_fetch_dec(&view->ref) == 1) {
307 flatview_destroy(view);
308 }
309}
310
3d8e6bf9
AK
311static bool can_merge(FlatRange *r1, FlatRange *r2)
312{
08dafab4 313 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 314 && r1->mr == r2->mr
08dafab4
AK
315 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
316 r1->addr.size),
317 int128_make64(r2->offset_in_region))
d0a9b5bc 318 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 319 && r1->romd_mode == r2->romd_mode
fb1cd6f9 320 && r1->readonly == r2->readonly;
3d8e6bf9
AK
321}
322
8508e024 323/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
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324static void flatview_simplify(FlatView *view)
325{
326 unsigned i, j;
327
328 i = 0;
329 while (i < view->nr) {
330 j = i + 1;
331 while (j < view->nr
332 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 333 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
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334 ++j;
335 }
336 ++i;
337 memmove(&view->ranges[i], &view->ranges[j],
338 (view->nr - j) * sizeof(view->ranges[j]));
339 view->nr -= j - i;
340 }
341}
342
e7342aa3
PB
343static bool memory_region_big_endian(MemoryRegion *mr)
344{
345#ifdef TARGET_WORDS_BIGENDIAN
346 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
347#else
348 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
349#endif
350}
351
e11ef3d1
PB
352static bool memory_region_wrong_endianness(MemoryRegion *mr)
353{
354#ifdef TARGET_WORDS_BIGENDIAN
355 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
356#else
357 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
358#endif
359}
360
361static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
362{
363 if (memory_region_wrong_endianness(mr)) {
364 switch (size) {
365 case 1:
366 break;
367 case 2:
368 *data = bswap16(*data);
369 break;
370 case 4:
371 *data = bswap32(*data);
372 break;
373 case 8:
374 *data = bswap64(*data);
375 break;
376 default:
377 abort();
378 }
379 }
380}
381
4779dc1d
HB
382static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
383{
384 MemoryRegion *root;
385 hwaddr abs_addr = offset;
386
387 abs_addr += mr->addr;
388 for (root = mr; root->container; ) {
389 root = root->container;
390 abs_addr += root->addr;
391 }
392
393 return abs_addr;
394}
395
5a68be94
HB
396static int get_cpu_index(void)
397{
398 if (current_cpu) {
399 return current_cpu->cpu_index;
400 }
401 return -1;
402}
403
cc05c43a
PM
404static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
405 hwaddr addr,
406 uint64_t *value,
407 unsigned size,
408 unsigned shift,
409 uint64_t mask,
410 MemTxAttrs attrs)
411{
412 uint64_t tmp;
413
414 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
23d92d68 415 if (mr->subpage) {
5a68be94 416 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
417 } else if (mr == &io_mem_notdirty) {
418 /* Accesses to code which has previously been translated into a TB show
419 * up in the MMIO path, as accesses to the io_mem_notdirty
420 * MemoryRegion. */
421 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
422 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
423 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 424 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 425 }
cc05c43a
PM
426 *value |= (tmp & mask) << shift;
427 return MEMTX_OK;
428}
429
430static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB
431 hwaddr addr,
432 uint64_t *value,
433 unsigned size,
434 unsigned shift,
cc05c43a
PM
435 uint64_t mask,
436 MemTxAttrs attrs)
ce5d2f33 437{
ce5d2f33
PB
438 uint64_t tmp;
439
cc05c43a 440 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 441 if (mr->subpage) {
5a68be94 442 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
443 } else if (mr == &io_mem_notdirty) {
444 /* Accesses to code which has previously been translated into a TB show
445 * up in the MMIO path, as accesses to the io_mem_notdirty
446 * MemoryRegion. */
447 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
448 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
449 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 450 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 451 }
ce5d2f33 452 *value |= (tmp & mask) << shift;
cc05c43a 453 return MEMTX_OK;
ce5d2f33
PB
454}
455
cc05c43a
PM
456static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
457 hwaddr addr,
458 uint64_t *value,
459 unsigned size,
460 unsigned shift,
461 uint64_t mask,
462 MemTxAttrs attrs)
164a4dcd 463{
cc05c43a
PM
464 uint64_t tmp = 0;
465 MemTxResult r;
164a4dcd 466
cc05c43a 467 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 468 if (mr->subpage) {
5a68be94 469 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
470 } else if (mr == &io_mem_notdirty) {
471 /* Accesses to code which has previously been translated into a TB show
472 * up in the MMIO path, as accesses to the io_mem_notdirty
473 * MemoryRegion. */
474 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
475 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
476 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 477 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 478 }
164a4dcd 479 *value |= (tmp & mask) << shift;
cc05c43a 480 return r;
164a4dcd
AK
481}
482
cc05c43a
PM
483static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
484 hwaddr addr,
485 uint64_t *value,
486 unsigned size,
487 unsigned shift,
488 uint64_t mask,
489 MemTxAttrs attrs)
ce5d2f33 490{
ce5d2f33
PB
491 uint64_t tmp;
492
493 tmp = (*value >> shift) & mask;
23d92d68 494 if (mr->subpage) {
5a68be94 495 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
496 } else if (mr == &io_mem_notdirty) {
497 /* Accesses to code which has previously been translated into a TB show
498 * up in the MMIO path, as accesses to the io_mem_notdirty
499 * MemoryRegion. */
500 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
501 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
502 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 503 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 504 }
ce5d2f33 505 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
cc05c43a 506 return MEMTX_OK;
ce5d2f33
PB
507}
508
cc05c43a
PM
509static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
510 hwaddr addr,
511 uint64_t *value,
512 unsigned size,
513 unsigned shift,
514 uint64_t mask,
515 MemTxAttrs attrs)
164a4dcd 516{
164a4dcd
AK
517 uint64_t tmp;
518
519 tmp = (*value >> shift) & mask;
23d92d68 520 if (mr->subpage) {
5a68be94 521 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
522 } else if (mr == &io_mem_notdirty) {
523 /* Accesses to code which has previously been translated into a TB show
524 * up in the MMIO path, as accesses to the io_mem_notdirty
525 * MemoryRegion. */
526 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
527 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
528 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 529 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 530 }
164a4dcd 531 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 532 return MEMTX_OK;
164a4dcd
AK
533}
534
cc05c43a
PM
535static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
536 hwaddr addr,
537 uint64_t *value,
538 unsigned size,
539 unsigned shift,
540 uint64_t mask,
541 MemTxAttrs attrs)
542{
543 uint64_t tmp;
544
cc05c43a 545 tmp = (*value >> shift) & mask;
23d92d68 546 if (mr->subpage) {
5a68be94 547 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
548 } else if (mr == &io_mem_notdirty) {
549 /* Accesses to code which has previously been translated into a TB show
550 * up in the MMIO path, as accesses to the io_mem_notdirty
551 * MemoryRegion. */
552 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
553 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
554 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 555 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 556 }
cc05c43a
PM
557 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
558}
559
560static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK
561 uint64_t *value,
562 unsigned size,
563 unsigned access_size_min,
564 unsigned access_size_max,
05e015f7
KF
565 MemTxResult (*access_fn)
566 (MemoryRegion *mr,
567 hwaddr addr,
568 uint64_t *value,
569 unsigned size,
570 unsigned shift,
571 uint64_t mask,
572 MemTxAttrs attrs),
cc05c43a
PM
573 MemoryRegion *mr,
574 MemTxAttrs attrs)
164a4dcd
AK
575{
576 uint64_t access_mask;
577 unsigned access_size;
578 unsigned i;
cc05c43a 579 MemTxResult r = MEMTX_OK;
164a4dcd
AK
580
581 if (!access_size_min) {
582 access_size_min = 1;
583 }
584 if (!access_size_max) {
585 access_size_max = 4;
586 }
ce5d2f33
PB
587
588 /* FIXME: support unaligned access? */
164a4dcd
AK
589 access_size = MAX(MIN(size, access_size_max), access_size_min);
590 access_mask = -1ULL >> (64 - access_size * 8);
e7342aa3
PB
591 if (memory_region_big_endian(mr)) {
592 for (i = 0; i < size; i += access_size) {
05e015f7 593 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 594 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB
595 }
596 } else {
597 for (i = 0; i < size; i += access_size) {
05e015f7 598 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 599 access_mask, attrs);
e7342aa3 600 }
164a4dcd 601 }
cc05c43a 602 return r;
164a4dcd
AK
603}
604
e2177955
AK
605static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
606{
0d673e36
AK
607 AddressSpace *as;
608
feca4ac1
PB
609 while (mr->container) {
610 mr = mr->container;
e2177955 611 }
0d673e36
AK
612 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
613 if (mr == as->root) {
614 return as;
615 }
e2177955 616 }
eed2bacf 617 return NULL;
e2177955
AK
618}
619
093bc2cd
AK
620/* Render a memory region into the global view. Ranges in @view obscure
621 * ranges in @mr.
622 */
623static void render_memory_region(FlatView *view,
624 MemoryRegion *mr,
08dafab4 625 Int128 base,
fb1cd6f9
AK
626 AddrRange clip,
627 bool readonly)
093bc2cd
AK
628{
629 MemoryRegion *subregion;
630 unsigned i;
a8170e5e 631 hwaddr offset_in_region;
08dafab4
AK
632 Int128 remain;
633 Int128 now;
093bc2cd
AK
634 FlatRange fr;
635 AddrRange tmp;
636
6bba19ba
AK
637 if (!mr->enabled) {
638 return;
639 }
640
08dafab4 641 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 642 readonly |= mr->readonly;
093bc2cd
AK
643
644 tmp = addrrange_make(base, mr->size);
645
646 if (!addrrange_intersects(tmp, clip)) {
647 return;
648 }
649
650 clip = addrrange_intersection(tmp, clip);
651
652 if (mr->alias) {
08dafab4
AK
653 int128_subfrom(&base, int128_make64(mr->alias->addr));
654 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 655 render_memory_region(view, mr->alias, base, clip, readonly);
093bc2cd
AK
656 return;
657 }
658
659 /* Render subregions in priority order. */
660 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 661 render_memory_region(view, subregion, base, clip, readonly);
093bc2cd
AK
662 }
663
14a3c10a 664 if (!mr->terminates) {
093bc2cd
AK
665 return;
666 }
667
08dafab4 668 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK
669 base = clip.start;
670 remain = clip.size;
671
2eb74e1a 672 fr.mr = mr;
6f6a5ef3 673 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 674 fr.romd_mode = mr->romd_mode;
2eb74e1a
PC
675 fr.readonly = readonly;
676
093bc2cd 677 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK
678 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
679 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK
680 continue;
681 }
08dafab4
AK
682 if (int128_lt(base, view->ranges[i].addr.start)) {
683 now = int128_min(remain,
684 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK
685 fr.offset_in_region = offset_in_region;
686 fr.addr = addrrange_make(base, now);
687 flatview_insert(view, i, &fr);
688 ++i;
08dafab4
AK
689 int128_addto(&base, now);
690 offset_in_region += int128_get64(now);
691 int128_subfrom(&remain, now);
093bc2cd 692 }
d26a8cae
AK
693 now = int128_sub(int128_min(int128_add(base, remain),
694 addrrange_end(view->ranges[i].addr)),
695 base);
696 int128_addto(&base, now);
697 offset_in_region += int128_get64(now);
698 int128_subfrom(&remain, now);
093bc2cd 699 }
08dafab4 700 if (int128_nz(remain)) {
093bc2cd
AK
701 fr.offset_in_region = offset_in_region;
702 fr.addr = addrrange_make(base, remain);
703 flatview_insert(view, i, &fr);
704 }
705}
706
707/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 708static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 709{
a9a0c06d 710 FlatView *view;
093bc2cd 711
cc94cd6d 712 view = flatview_new();
093bc2cd 713
83f3c251 714 if (mr) {
a9a0c06d 715 render_memory_region(view, mr, int128_zero(),
83f3c251
AK
716 addrrange_make(int128_zero(), int128_2_64()), false);
717 }
a9a0c06d 718 flatview_simplify(view);
093bc2cd
AK
719
720 return view;
721}
722
3e9d69e7
AK
723static void address_space_add_del_ioeventfds(AddressSpace *as,
724 MemoryRegionIoeventfd *fds_new,
725 unsigned fds_new_nb,
726 MemoryRegionIoeventfd *fds_old,
727 unsigned fds_old_nb)
728{
729 unsigned iold, inew;
80a1ea37
AK
730 MemoryRegionIoeventfd *fd;
731 MemoryRegionSection section;
3e9d69e7
AK
732
733 /* Generate a symmetric difference of the old and new fd sets, adding
734 * and deleting as necessary.
735 */
736
737 iold = inew = 0;
738 while (iold < fds_old_nb || inew < fds_new_nb) {
739 if (iold < fds_old_nb
740 && (inew == fds_new_nb
741 || memory_region_ioeventfd_before(fds_old[iold],
742 fds_new[inew]))) {
80a1ea37
AK
743 fd = &fds_old[iold];
744 section = (MemoryRegionSection) {
f6790af6 745 .address_space = as,
80a1ea37 746 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 747 .size = fd->addr.size,
80a1ea37 748 };
9a54635d 749 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 750 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
751 ++iold;
752 } else if (inew < fds_new_nb
753 && (iold == fds_old_nb
754 || memory_region_ioeventfd_before(fds_new[inew],
755 fds_old[iold]))) {
80a1ea37
AK
756 fd = &fds_new[inew];
757 section = (MemoryRegionSection) {
f6790af6 758 .address_space = as,
80a1ea37 759 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 760 .size = fd->addr.size,
80a1ea37 761 };
9a54635d 762 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 763 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
764 ++inew;
765 } else {
766 ++iold;
767 ++inew;
768 }
769 }
770}
771
856d7245
PB
772static FlatView *address_space_get_flatview(AddressSpace *as)
773{
774 FlatView *view;
775
374f2981 776 rcu_read_lock();
447b0d0b
PB
777 do {
778 view = atomic_rcu_read(&as->current_map);
779 /* If somebody has replaced as->current_map concurrently,
780 * flatview_ref returns false.
781 */
782 } while (!flatview_ref(view));
374f2981 783 rcu_read_unlock();
856d7245
PB
784 return view;
785}
786
3e9d69e7
AK
787static void address_space_update_ioeventfds(AddressSpace *as)
788{
99e86347 789 FlatView *view;
3e9d69e7
AK
790 FlatRange *fr;
791 unsigned ioeventfd_nb = 0;
792 MemoryRegionIoeventfd *ioeventfds = NULL;
793 AddrRange tmp;
794 unsigned i;
795
856d7245 796 view = address_space_get_flatview(as);
99e86347 797 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK
798 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
799 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK
800 int128_sub(fr->addr.start,
801 int128_make64(fr->offset_in_region)));
3e9d69e7
AK
802 if (addrrange_intersects(fr->addr, tmp)) {
803 ++ioeventfd_nb;
7267c094 804 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK
805 ioeventfd_nb * sizeof(*ioeventfds));
806 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
807 ioeventfds[ioeventfd_nb-1].addr = tmp;
808 }
809 }
810 }
811
812 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
813 as->ioeventfds, as->ioeventfd_nb);
814
7267c094 815 g_free(as->ioeventfds);
3e9d69e7
AK
816 as->ioeventfds = ioeventfds;
817 as->ioeventfd_nb = ioeventfd_nb;
856d7245 818 flatview_unref(view);
3e9d69e7
AK
819}
820
b8af1afb 821static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB
822 const FlatView *old_view,
823 const FlatView *new_view,
b8af1afb 824 bool adding)
093bc2cd 825{
093bc2cd
AK
826 unsigned iold, inew;
827 FlatRange *frold, *frnew;
093bc2cd
AK
828
829 /* Generate a symmetric difference of the old and new memory maps.
830 * Kill ranges in the old map, and instantiate ranges in the new map.
831 */
832 iold = inew = 0;
a9a0c06d
PB
833 while (iold < old_view->nr || inew < new_view->nr) {
834 if (iold < old_view->nr) {
835 frold = &old_view->ranges[iold];
093bc2cd
AK
836 } else {
837 frold = NULL;
838 }
a9a0c06d
PB
839 if (inew < new_view->nr) {
840 frnew = &new_view->ranges[inew];
093bc2cd
AK
841 } else {
842 frnew = NULL;
843 }
844
845 if (frold
846 && (!frnew
08dafab4
AK
847 || int128_lt(frold->addr.start, frnew->addr.start)
848 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 849 && !flatrange_equal(frold, frnew)))) {
41a6e477 850 /* In old but not in new, or in both but attributes changed. */
093bc2cd 851
b8af1afb 852 if (!adding) {
72e22d2f 853 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK
854 }
855
093bc2cd
AK
856 ++iold;
857 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 858 /* In both and unchanged (except logging may have changed) */
093bc2cd 859
b8af1afb 860 if (adding) {
50c1e149 861 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB
862 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
863 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
864 frold->dirty_log_mask,
865 frnew->dirty_log_mask);
866 }
867 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
868 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
869 frold->dirty_log_mask,
870 frnew->dirty_log_mask);
b8af1afb 871 }
5a583347
AK
872 }
873
093bc2cd
AK
874 ++iold;
875 ++inew;
093bc2cd
AK
876 } else {
877 /* In new */
878
b8af1afb 879 if (adding) {
72e22d2f 880 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK
881 }
882
093bc2cd
AK
883 ++inew;
884 }
885 }
b8af1afb
AK
886}
887
b8af1afb
AK
888static void address_space_update_topology(AddressSpace *as)
889{
856d7245 890 FlatView *old_view = address_space_get_flatview(as);
a9a0c06d 891 FlatView *new_view = generate_memory_topology(as->root);
9a62e24f 892 int i;
b8af1afb 893
9a62e24f
AK
894 mem_begin(as);
895 for (i = 0; i < new_view->nr; i++) {
896 MemoryRegionSection mrs =
897 section_from_flat_range(&new_view->ranges[i], as);
898 mem_add(as, &mrs);
899 }
900 mem_commit(as);
901
902 if (!QTAILQ_EMPTY(&as->listeners)) {
903 address_space_update_topology_pass(as, old_view, new_view, false);
904 address_space_update_topology_pass(as, old_view, new_view, true);
905 }
b8af1afb 906
374f2981
PB
907 /* Writes are protected by the BQL. */
908 atomic_rcu_set(&as->current_map, new_view);
909 call_rcu(old_view, flatview_unref, rcu);
856d7245
PB
910
911 /* Note that all the old MemoryRegions are still alive up to this
912 * point. This relieves most MemoryListeners from the need to
913 * ref/unref the MemoryRegions they get---unless they use them
914 * outside the iothread mutex, in which case precise reference
915 * counting is necessary.
916 */
917 flatview_unref(old_view);
918
3e9d69e7 919 address_space_update_ioeventfds(as);
093bc2cd
AK
920}
921
4ef4db86
AK
922void memory_region_transaction_begin(void)
923{
bb880ded 924 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK
925 ++memory_region_transaction_depth;
926}
927
928void memory_region_transaction_commit(void)
929{
0d673e36
AK
930 AddressSpace *as;
931
4ef4db86 932 assert(memory_region_transaction_depth);
8d04fb55
JK
933 assert(qemu_mutex_iothread_locked());
934
4ef4db86 935 --memory_region_transaction_depth;
4dc56152
GA
936 if (!memory_region_transaction_depth) {
937 if (memory_region_update_pending) {
938 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 939
4dc56152
GA
940 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
941 address_space_update_topology(as);
942 }
ade9c1aa 943 memory_region_update_pending = false;
4dc56152
GA
944 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
945 } else if (ioeventfd_update_pending) {
946 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
947 address_space_update_ioeventfds(as);
948 }
ade9c1aa 949 ioeventfd_update_pending = false;
4dc56152 950 }
4dc56152 951 }
4ef4db86
AK
952}
953
545e92e0
AK
954static void memory_region_destructor_none(MemoryRegion *mr)
955{
956}
957
958static void memory_region_destructor_ram(MemoryRegion *mr)
959{
f1060c55 960 qemu_ram_free(mr->ram_block);
545e92e0
AK
961}
962
b4fefef9
PC
963static bool memory_region_need_escape(char c)
964{
965 return c == '/' || c == '[' || c == '\\' || c == ']';
966}
967
968static char *memory_region_escape_name(const char *name)
969{
970 const char *p;
971 char *escaped, *q;
972 uint8_t c;
973 size_t bytes = 0;
974
975 for (p = name; *p; p++) {
976 bytes += memory_region_need_escape(*p) ? 4 : 1;
977 }
978 if (bytes == p - name) {
979 return g_memdup(name, bytes + 1);
980 }
981
982 escaped = g_malloc(bytes + 1);
983 for (p = name, q = escaped; *p; p++) {
984 c = *p;
985 if (unlikely(memory_region_need_escape(c))) {
986 *q++ = '\\';
987 *q++ = 'x';
988 *q++ = "0123456789abcdef"[c >> 4];
989 c = "0123456789abcdef"[c & 15];
990 }
991 *q++ = c;
992 }
993 *q = 0;
994 return escaped;
995}
996
3df9d748
AK
997static void memory_region_do_init(MemoryRegion *mr,
998 Object *owner,
999 const char *name,
1000 uint64_t size)
093bc2cd 1001{
08dafab4
AK
1002 mr->size = int128_make64(size);
1003 if (size == UINT64_MAX) {
1004 mr->size = int128_2_64();
1005 }
302fa283 1006 mr->name = g_strdup(name);
612263cf 1007 mr->owner = owner;
58eaa217 1008 mr->ram_block = NULL;
b4fefef9
PC
1009
1010 if (name) {
843ef73a
PC
1011 char *escaped_name = memory_region_escape_name(name);
1012 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB
1013
1014 if (!owner) {
1015 owner = container_get(qdev_get_machine(), "/unattached");
1016 }
1017
843ef73a 1018 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1019 object_unref(OBJECT(mr));
843ef73a
PC
1020 g_free(name_array);
1021 g_free(escaped_name);
b4fefef9
PC
1022 }
1023}
1024
3df9d748
AK
1025void memory_region_init(MemoryRegion *mr,
1026 Object *owner,
1027 const char *name,
1028 uint64_t size)
1029{
1030 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1031 memory_region_do_init(mr, owner, name, size);
1032}
1033
d7bce999
EB
1034static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1035 void *opaque, Error **errp)
409ddd01
PC
1036{
1037 MemoryRegion *mr = MEMORY_REGION(obj);
1038 uint64_t value = mr->addr;
1039
51e72bc1 1040 visit_type_uint64(v, name, &value, errp);
409ddd01
PC
1041}
1042
d7bce999
EB
1043static void memory_region_get_container(Object *obj, Visitor *v,
1044 const char *name, void *opaque,
1045 Error **errp)
409ddd01
PC
1046{
1047 MemoryRegion *mr = MEMORY_REGION(obj);
1048 gchar *path = (gchar *)"";
1049
1050 if (mr->container) {
1051 path = object_get_canonical_path(OBJECT(mr->container));
1052 }
51e72bc1 1053 visit_type_str(v, name, &path, errp);
409ddd01
PC
1054 if (mr->container) {
1055 g_free(path);
1056 }
1057}
1058
1059static Object *memory_region_resolve_container(Object *obj, void *opaque,
1060 const char *part)
1061{
1062 MemoryRegion *mr = MEMORY_REGION(obj);
1063
1064 return OBJECT(mr->container);
1065}
1066
d7bce999
EB
1067static void memory_region_get_priority(Object *obj, Visitor *v,
1068 const char *name, void *opaque,
1069 Error **errp)
d33382da
PC
1070{
1071 MemoryRegion *mr = MEMORY_REGION(obj);
1072 int32_t value = mr->priority;
1073
51e72bc1 1074 visit_type_int32(v, name, &value, errp);
d33382da
PC
1075}
1076
d7bce999
EB
1077static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1078 void *opaque, Error **errp)
52aef7bb
PC
1079{
1080 MemoryRegion *mr = MEMORY_REGION(obj);
1081 uint64_t value = memory_region_size(mr);
1082
51e72bc1 1083 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC
1084}
1085
b4fefef9
PC
1086static void memory_region_initfn(Object *obj)
1087{
1088 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1089 ObjectProperty *op;
b4fefef9
PC
1090
1091 mr->ops = &unassigned_mem_ops;
6bba19ba 1092 mr->enabled = true;
5f9a5ea1 1093 mr->romd_mode = true;
196ea131 1094 mr->global_locking = true;
545e92e0 1095 mr->destructor = memory_region_destructor_none;
093bc2cd 1096 QTAILQ_INIT(&mr->subregions);
093bc2cd 1097 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC
1098
1099 op = object_property_add(OBJECT(mr), "container",
1100 "link<" TYPE_MEMORY_REGION ">",
1101 memory_region_get_container,
1102 NULL, /* memory_region_set_container */
1103 NULL, NULL, &error_abort);
1104 op->resolve = memory_region_resolve_container;
1105
1106 object_property_add(OBJECT(mr), "addr", "uint64",
1107 memory_region_get_addr,
1108 NULL, /* memory_region_set_addr */
1109 NULL, NULL, &error_abort);
d33382da
PC
1110 object_property_add(OBJECT(mr), "priority", "uint32",
1111 memory_region_get_priority,
1112 NULL, /* memory_region_set_priority */
1113 NULL, NULL, &error_abort);
52aef7bb
PC
1114 object_property_add(OBJECT(mr), "size", "uint64",
1115 memory_region_get_size,
1116 NULL, /* memory_region_set_size, */
1117 NULL, NULL, &error_abort);
093bc2cd
AK
1118}
1119
3df9d748
AK
1120static void iommu_memory_region_initfn(Object *obj)
1121{
1122 MemoryRegion *mr = MEMORY_REGION(obj);
1123
1124 mr->is_iommu = true;
1125}
1126
b018ddf6
PB
1127static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1128 unsigned size)
1129{
1130#ifdef DEBUG_UNASSIGNED
1131 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1132#endif
4917cf44
AF
1133 if (current_cpu != NULL) {
1134 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
c658b94f 1135 }
68a7439a 1136 return 0;
b018ddf6
PB
1137}
1138
1139static void unassigned_mem_write(void *opaque, hwaddr addr,
1140 uint64_t val, unsigned size)
1141{
1142#ifdef DEBUG_UNASSIGNED
1143 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1144#endif
4917cf44
AF
1145 if (current_cpu != NULL) {
1146 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1147 }
b018ddf6
PB
1148}
1149
d197063f
PB
1150static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1151 unsigned size, bool is_write)
1152{
1153 return false;
1154}
1155
1156const MemoryRegionOps unassigned_mem_ops = {
1157 .valid.accepts = unassigned_mem_accepts,
1158 .endianness = DEVICE_NATIVE_ENDIAN,
1159};
1160
4a2e242b
AW
1161static uint64_t memory_region_ram_device_read(void *opaque,
1162 hwaddr addr, unsigned size)
1163{
1164 MemoryRegion *mr = opaque;
1165 uint64_t data = (uint64_t)~0;
1166
1167 switch (size) {
1168 case 1:
1169 data = *(uint8_t *)(mr->ram_block->host + addr);
1170 break;
1171 case 2:
1172 data = *(uint16_t *)(mr->ram_block->host + addr);
1173 break;
1174 case 4:
1175 data = *(uint32_t *)(mr->ram_block->host + addr);
1176 break;
1177 case 8:
1178 data = *(uint64_t *)(mr->ram_block->host + addr);
1179 break;
1180 }
1181
1182 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1183
1184 return data;
1185}
1186
1187static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1188 uint64_t data, unsigned size)
1189{
1190 MemoryRegion *mr = opaque;
1191
1192 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1193
1194 switch (size) {
1195 case 1:
1196 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1197 break;
1198 case 2:
1199 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1200 break;
1201 case 4:
1202 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1203 break;
1204 case 8:
1205 *(uint64_t *)(mr->ram_block->host + addr) = data;
1206 break;
1207 }
1208}
1209
1210static const MemoryRegionOps ram_device_mem_ops = {
1211 .read = memory_region_ram_device_read,
1212 .write = memory_region_ram_device_write,
c99a29e7 1213 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW
1214 .valid = {
1215 .min_access_size = 1,
1216 .max_access_size = 8,
1217 .unaligned = true,
1218 },
1219 .impl = {
1220 .min_access_size = 1,
1221 .max_access_size = 8,
1222 .unaligned = true,
1223 },
1224};
1225
d2702032
PB
1226bool memory_region_access_valid(MemoryRegion *mr,
1227 hwaddr addr,
1228 unsigned size,
1229 bool is_write)
093bc2cd 1230{
a014ed07
PB
1231 int access_size_min, access_size_max;
1232 int access_size, i;
897fa7cf 1233
093bc2cd
AK
1234 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1235 return false;
1236 }
1237
a014ed07 1238 if (!mr->ops->valid.accepts) {
093bc2cd
AK
1239 return true;
1240 }
1241
a014ed07
PB
1242 access_size_min = mr->ops->valid.min_access_size;
1243 if (!mr->ops->valid.min_access_size) {
1244 access_size_min = 1;
1245 }
1246
1247 access_size_max = mr->ops->valid.max_access_size;
1248 if (!mr->ops->valid.max_access_size) {
1249 access_size_max = 4;
1250 }
1251
1252 access_size = MAX(MIN(size, access_size_max), access_size_min);
1253 for (i = 0; i < size; i += access_size) {
1254 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1255 is_write)) {
1256 return false;
1257 }
093bc2cd 1258 }
a014ed07 1259
093bc2cd
AK
1260 return true;
1261}
1262
cc05c43a
PM
1263static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1264 hwaddr addr,
1265 uint64_t *pval,
1266 unsigned size,
1267 MemTxAttrs attrs)
093bc2cd 1268{
cc05c43a 1269 *pval = 0;
093bc2cd 1270
ce5d2f33 1271 if (mr->ops->read) {
cc05c43a
PM
1272 return access_with_adjusted_size(addr, pval, size,
1273 mr->ops->impl.min_access_size,
1274 mr->ops->impl.max_access_size,
1275 memory_region_read_accessor,
1276 mr, attrs);
1277 } else if (mr->ops->read_with_attrs) {
1278 return access_with_adjusted_size(addr, pval, size,
1279 mr->ops->impl.min_access_size,
1280 mr->ops->impl.max_access_size,
1281 memory_region_read_with_attrs_accessor,
1282 mr, attrs);
ce5d2f33 1283 } else {
cc05c43a
PM
1284 return access_with_adjusted_size(addr, pval, size, 1, 4,
1285 memory_region_oldmmio_read_accessor,
1286 mr, attrs);
74901c3b 1287 }
093bc2cd
AK
1288}
1289
3b643495
PM
1290MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1291 hwaddr addr,
1292 uint64_t *pval,
1293 unsigned size,
1294 MemTxAttrs attrs)
a621f38d 1295{
cc05c43a
PM
1296 MemTxResult r;
1297
791af8c8
PB
1298 if (!memory_region_access_valid(mr, addr, size, false)) {
1299 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1300 return MEMTX_DECODE_ERROR;
791af8c8 1301 }
a621f38d 1302
cc05c43a 1303 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1304 adjust_endianness(mr, pval, size);
cc05c43a 1305 return r;
a621f38d 1306}
093bc2cd 1307
8c56c1a5
PF
1308/* Return true if an eventfd was signalled */
1309static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1310 hwaddr addr,
1311 uint64_t data,
1312 unsigned size,
1313 MemTxAttrs attrs)
1314{
1315 MemoryRegionIoeventfd ioeventfd = {
1316 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1317 .data = data,
1318 };
1319 unsigned i;
1320
1321 for (i = 0; i < mr->ioeventfd_nb; i++) {
1322 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1323 ioeventfd.e = mr->ioeventfds[i].e;
1324
1325 if (memory_region_ioeventfd_equal(ioeventfd, mr->ioeventfds[i])) {
1326 event_notifier_set(ioeventfd.e);
1327 return true;
1328 }
1329 }
1330
1331 return false;
1332}
1333
3b643495
PM
1334MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1335 hwaddr addr,
1336 uint64_t data,
1337 unsigned size,
1338 MemTxAttrs attrs)
a621f38d 1339{
897fa7cf 1340 if (!memory_region_access_valid(mr, addr, size, true)) {
b018ddf6 1341 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1342 return MEMTX_DECODE_ERROR;
093bc2cd
AK
1343 }
1344
a621f38d
AK
1345 adjust_endianness(mr, &data, size);
1346
8c56c1a5
PF
1347 if ((!kvm_eventfds_enabled()) &&
1348 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1349 return MEMTX_OK;
1350 }
1351
ce5d2f33 1352 if (mr->ops->write) {
cc05c43a
PM
1353 return access_with_adjusted_size(addr, &data, size,
1354 mr->ops->impl.min_access_size,
1355 mr->ops->impl.max_access_size,
1356 memory_region_write_accessor, mr,
1357 attrs);
1358 } else if (mr->ops->write_with_attrs) {
1359 return
1360 access_with_adjusted_size(addr, &data, size,
1361 mr->ops->impl.min_access_size,
1362 mr->ops->impl.max_access_size,
1363 memory_region_write_with_attrs_accessor,
1364 mr, attrs);
ce5d2f33 1365 } else {
cc05c43a
PM
1366 return access_with_adjusted_size(addr, &data, size, 1, 4,
1367 memory_region_oldmmio_write_accessor,
1368 mr, attrs);
74901c3b 1369 }
093bc2cd
AK
1370}
1371
093bc2cd 1372void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1373 Object *owner,
093bc2cd
AK
1374 const MemoryRegionOps *ops,
1375 void *opaque,
1376 const char *name,
1377 uint64_t size)
1378{
2c9b15ca 1379 memory_region_init(mr, owner, name, size);
6d6d2abf 1380 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1381 mr->opaque = opaque;
14a3c10a 1382 mr->terminates = true;
093bc2cd
AK
1383}
1384
1cfe48c1
PM
1385void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1386 Object *owner,
1387 const char *name,
1388 uint64_t size,
1389 Error **errp)
093bc2cd 1390{
2c9b15ca 1391 memory_region_init(mr, owner, name, size);
8ea9252a 1392 mr->ram = true;
14a3c10a 1393 mr->terminates = true;
545e92e0 1394 mr->destructor = memory_region_destructor_ram;
8e41fb63 1395 mr->ram_block = qemu_ram_alloc(size, mr, errp);
677e7805 1396 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
0b183fc8
PB
1397}
1398
60786ef3
MT
1399void memory_region_init_resizeable_ram(MemoryRegion *mr,
1400 Object *owner,
1401 const char *name,
1402 uint64_t size,
1403 uint64_t max_size,
1404 void (*resized)(const char*,
1405 uint64_t length,
1406 void *host),
1407 Error **errp)
1408{
1409 memory_region_init(mr, owner, name, size);
1410 mr->ram = true;
1411 mr->terminates = true;
1412 mr->destructor = memory_region_destructor_ram;
8e41fb63
FZ
1413 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1414 mr, errp);
677e7805 1415 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
60786ef3
MT
1416}
1417
0b183fc8
PB
1418#ifdef __linux__
1419void memory_region_init_ram_from_file(MemoryRegion *mr,
1420 struct Object *owner,
1421 const char *name,
1422 uint64_t size,
dbcb8981 1423 bool share,
7f56e740
PB
1424 const char *path,
1425 Error **errp)
0b183fc8
PB
1426{
1427 memory_region_init(mr, owner, name, size);
1428 mr->ram = true;
1429 mr->terminates = true;
1430 mr->destructor = memory_region_destructor_ram;
8e41fb63 1431 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
677e7805 1432 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
093bc2cd 1433}
fea617c5
MAL
1434
1435void memory_region_init_ram_from_fd(MemoryRegion *mr,
1436 struct Object *owner,
1437 const char *name,
1438 uint64_t size,
1439 bool share,
1440 int fd,
1441 Error **errp)
1442{
1443 memory_region_init(mr, owner, name, size);
1444 mr->ram = true;
1445 mr->terminates = true;
1446 mr->destructor = memory_region_destructor_ram;
1447 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1448 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1449}
0b183fc8 1450#endif
093bc2cd
AK
1451
1452void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1453 Object *owner,
093bc2cd
AK
1454 const char *name,
1455 uint64_t size,
1456 void *ptr)
1457{
2c9b15ca 1458 memory_region_init(mr, owner, name, size);
8ea9252a 1459 mr->ram = true;
14a3c10a 1460 mr->terminates = true;
fc3e7665 1461 mr->destructor = memory_region_destructor_ram;
677e7805 1462 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT
1463
1464 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1465 assert(ptr != NULL);
8e41fb63 1466 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK
1467}
1468
21e00fa5
AW
1469void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1470 Object *owner,
1471 const char *name,
1472 uint64_t size,
1473 void *ptr)
e4dc3f59 1474{
21e00fa5
AW
1475 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1476 mr->ram_device = true;
4a2e242b
AW
1477 mr->ops = &ram_device_mem_ops;
1478 mr->opaque = mr;
e4dc3f59
ND
1479}
1480
093bc2cd 1481void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1482 Object *owner,
093bc2cd
AK
1483 const char *name,
1484 MemoryRegion *orig,
a8170e5e 1485 hwaddr offset,
093bc2cd
AK
1486 uint64_t size)
1487{
2c9b15ca 1488 memory_region_init(mr, owner, name, size);
093bc2cd
AK
1489 mr->alias = orig;
1490 mr->alias_offset = offset;
1491}
1492
b59821a9
PM
1493void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1494 struct Object *owner,
1495 const char *name,
1496 uint64_t size,
1497 Error **errp)
a1777f7f
PM
1498{
1499 memory_region_init(mr, owner, name, size);
1500 mr->ram = true;
1501 mr->readonly = true;
1502 mr->terminates = true;
1503 mr->destructor = memory_region_destructor_ram;
1504 mr->ram_block = qemu_ram_alloc(size, mr, errp);
1505 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1506}
1507
b59821a9
PM
1508void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1509 Object *owner,
1510 const MemoryRegionOps *ops,
1511 void *opaque,
1512 const char *name,
1513 uint64_t size,
1514 Error **errp)
d0a9b5bc 1515{
39e0b03d 1516 assert(ops);
2c9b15ca 1517 memory_region_init(mr, owner, name, size);
7bc2b9cd 1518 mr->ops = ops;
75f5941c 1519 mr->opaque = opaque;
d0a9b5bc 1520 mr->terminates = true;
75c578dc 1521 mr->rom_device = true;
58268c8d 1522 mr->destructor = memory_region_destructor_ram;
8e41fb63 1523 mr->ram_block = qemu_ram_alloc(size, mr, errp);
d0a9b5bc
AK
1524}
1525
1221a474
AK
1526void memory_region_init_iommu(void *_iommu_mr,
1527 size_t instance_size,
1528 const char *mrtypename,
2c9b15ca 1529 Object *owner,
30951157
AK
1530 const char *name,
1531 uint64_t size)
1532{
1221a474 1533 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK
1534 struct MemoryRegion *mr;
1535
1221a474
AK
1536 object_initialize(_iommu_mr, instance_size, mrtypename);
1537 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK
1538 memory_region_do_init(mr, owner, name, size);
1539 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1540 mr->terminates = true; /* then re-forwards */
3df9d748
AK
1541 QLIST_INIT(&iommu_mr->iommu_notify);
1542 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK
1543}
1544
b4fefef9 1545static void memory_region_finalize(Object *obj)
093bc2cd 1546{
b4fefef9
PC
1547 MemoryRegion *mr = MEMORY_REGION(obj);
1548
2e2b8eb7
PB
1549 assert(!mr->container);
1550
1551 /* We know the region is not visible in any address space (it
1552 * does not have a container and cannot be a root either because
1553 * it has no references, so we can blindly clear mr->enabled.
1554 * memory_region_set_enabled instead could trigger a transaction
1555 * and cause an infinite loop.
1556 */
1557 mr->enabled = false;
1558 memory_region_transaction_begin();
1559 while (!QTAILQ_EMPTY(&mr->subregions)) {
1560 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1561 memory_region_del_subregion(mr, subregion);
1562 }
1563 memory_region_transaction_commit();
1564
545e92e0 1565 mr->destructor(mr);
093bc2cd 1566 memory_region_clear_coalescing(mr);
302fa283 1567 g_free((char *)mr->name);
7267c094 1568 g_free(mr->ioeventfds);
093bc2cd
AK
1569}
1570
803c0816
PB
1571Object *memory_region_owner(MemoryRegion *mr)
1572{
22a893e4
PB
1573 Object *obj = OBJECT(mr);
1574 return obj->parent;
803c0816
PB
1575}
1576
46637be2
PB
1577void memory_region_ref(MemoryRegion *mr)
1578{
22a893e4
PB
1579 /* MMIO callbacks most likely will access data that belongs
1580 * to the owner, hence the need to ref/unref the owner whenever
1581 * the memory region is in use.
1582 *
1583 * The memory region is a child of its owner. As long as the
1584 * owner doesn't call unparent itself on the memory region,
1585 * ref-ing the owner will also keep the memory region alive.
612263cf
PB
1586 * Memory regions without an owner are supposed to never go away;
1587 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1588 */
612263cf
PB
1589 if (mr && mr->owner) {
1590 object_ref(mr->owner);
46637be2
PB
1591 }
1592}
1593
1594void memory_region_unref(MemoryRegion *mr)
1595{
612263cf
PB
1596 if (mr && mr->owner) {
1597 object_unref(mr->owner);
46637be2
PB
1598 }
1599}
1600
093bc2cd
AK
1601uint64_t memory_region_size(MemoryRegion *mr)
1602{
08dafab4
AK
1603 if (int128_eq(mr->size, int128_2_64())) {
1604 return UINT64_MAX;
1605 }
1606 return int128_get64(mr->size);
093bc2cd
AK
1607}
1608
5d546d4b 1609const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1610{
d1dd32af
PC
1611 if (!mr->name) {
1612 ((MemoryRegion *)mr)->name =
1613 object_get_canonical_path_component(OBJECT(mr));
1614 }
302fa283 1615 return mr->name;
8991c79b
AK
1616}
1617
21e00fa5 1618bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1619{
21e00fa5 1620 return mr->ram_device;
e4dc3f59
ND
1621}
1622
2d1a35be 1623uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1624{
6f6a5ef3 1625 uint8_t mask = mr->dirty_log_mask;
adaad61c 1626 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB
1627 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1628 }
1629 return mask;
55043ba3
AK
1630}
1631
2d1a35be
PB
1632bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1633{
1634 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1635}
1636
3df9d748 1637static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
5bf3d319
PX
1638{
1639 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1640 IOMMUNotifier *iommu_notifier;
1221a474 1641 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
5bf3d319 1642
3df9d748 1643 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX
1644 flags |= iommu_notifier->notifier_flags;
1645 }
1646
1221a474
AK
1647 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1648 imrc->notify_flag_changed(iommu_mr,
1649 iommu_mr->iommu_notify_flags,
1650 flags);
5bf3d319
PX
1651 }
1652
3df9d748 1653 iommu_mr->iommu_notify_flags = flags;
5bf3d319
PX
1654}
1655
cdb30812
PX
1656void memory_region_register_iommu_notifier(MemoryRegion *mr,
1657 IOMMUNotifier *n)
06866575 1658{
3df9d748
AK
1659 IOMMUMemoryRegion *iommu_mr;
1660
efcd38c5
JW
1661 if (mr->alias) {
1662 memory_region_register_iommu_notifier(mr->alias, n);
1663 return;
1664 }
1665
cdb30812 1666 /* We need to register for at least one bitfield */
3df9d748 1667 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1668 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1669 assert(n->start <= n->end);
3df9d748
AK
1670 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1671 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1672}
1673
3df9d748 1674uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1675{
1221a474
AK
1676 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1677
1678 if (imrc->get_min_page_size) {
1679 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK
1680 }
1681 return TARGET_PAGE_SIZE;
1682}
1683
3df9d748 1684void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1685{
3df9d748 1686 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1687 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1688 hwaddr addr, granularity;
a788f227
DG
1689 IOMMUTLBEntry iotlb;
1690
faa362e3 1691 /* If the IOMMU has its own replay callback, override */
1221a474
AK
1692 if (imrc->replay) {
1693 imrc->replay(iommu_mr, n);
faa362e3
PX
1694 return;
1695 }
1696
3df9d748 1697 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1698
a788f227 1699 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1221a474 1700 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE);
a788f227
DG
1701 if (iotlb.perm != IOMMU_NONE) {
1702 n->notify(n, &iotlb);
1703 }
1704
1705 /* if (2^64 - MR size) < granularity, it's possible to get an
1706 * infinite loop here. This should catch such a wraparound */
1707 if ((addr + granularity) < addr) {
1708 break;
1709 }
1710 }
1711}
1712
3df9d748 1713void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
de472e4a
PX
1714{
1715 IOMMUNotifier *notifier;
1716
3df9d748
AK
1717 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1718 memory_region_iommu_replay(iommu_mr, notifier);
de472e4a
PX
1719 }
1720}
1721
cdb30812
PX
1722void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1723 IOMMUNotifier *n)
06866575 1724{
3df9d748
AK
1725 IOMMUMemoryRegion *iommu_mr;
1726
efcd38c5
JW
1727 if (mr->alias) {
1728 memory_region_unregister_iommu_notifier(mr->alias, n);
1729 return;
1730 }
cdb30812 1731 QLIST_REMOVE(n, node);
3df9d748
AK
1732 iommu_mr = IOMMU_MEMORY_REGION(mr);
1733 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1734}
1735
bd2bfa4c
PX
1736void memory_region_notify_one(IOMMUNotifier *notifier,
1737 IOMMUTLBEntry *entry)
06866575 1738{
cdb30812
PX
1739 IOMMUNotifierFlag request_flags;
1740
bd2bfa4c
PX
1741 /*
1742 * Skip the notification if the notification does not overlap
1743 * with registered range.
1744 */
1745 if (notifier->start > entry->iova + entry->addr_mask + 1 ||
1746 notifier->end < entry->iova) {
1747 return;
1748 }
cdb30812 1749
bd2bfa4c 1750 if (entry->perm & IOMMU_RW) {
cdb30812
PX
1751 request_flags = IOMMU_NOTIFIER_MAP;
1752 } else {
1753 request_flags = IOMMU_NOTIFIER_UNMAP;
1754 }
1755
bd2bfa4c
PX
1756 if (notifier->notifier_flags & request_flags) {
1757 notifier->notify(notifier, entry);
1758 }
1759}
1760
3df9d748 1761void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
bd2bfa4c
PX
1762 IOMMUTLBEntry entry)
1763{
1764 IOMMUNotifier *iommu_notifier;
1765
3df9d748 1766 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1767
3df9d748 1768 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
bd2bfa4c 1769 memory_region_notify_one(iommu_notifier, &entry);
cdb30812 1770 }
06866575
DG
1771}
1772
093bc2cd
AK
1773void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1774{
5a583347 1775 uint8_t mask = 1 << client;
deb809ed 1776 uint8_t old_logging;
5a583347 1777
dbddac6d 1778 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB
1779 old_logging = mr->vga_logging_count;
1780 mr->vga_logging_count += log ? 1 : -1;
1781 if (!!old_logging == !!mr->vga_logging_count) {
1782 return;
1783 }
1784
59023ef4 1785 memory_region_transaction_begin();
5a583347 1786 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1787 memory_region_update_pending |= mr->enabled;
59023ef4 1788 memory_region_transaction_commit();
093bc2cd
AK
1789}
1790
a8170e5e
AK
1791bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1792 hwaddr size, unsigned client)
093bc2cd 1793{
8e41fb63
FZ
1794 assert(mr->ram_block);
1795 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1796 size, client);
093bc2cd
AK
1797}
1798
a8170e5e
AK
1799void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1800 hwaddr size)
093bc2cd 1801{
8e41fb63
FZ
1802 assert(mr->ram_block);
1803 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1804 size,
58d2707e 1805 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK
1806}
1807
6c279db8
JQ
1808bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1809 hwaddr size, unsigned client)
1810{
8e41fb63
FZ
1811 assert(mr->ram_block);
1812 return cpu_physical_memory_test_and_clear_dirty(
1813 memory_region_get_ram_addr(mr) + addr, size, client);
6c279db8
JQ
1814}
1815
8deaf12c
GH
1816DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
1817 hwaddr addr,
1818 hwaddr size,
1819 unsigned client)
1820{
1821 assert(mr->ram_block);
1822 return cpu_physical_memory_snapshot_and_clear_dirty(
1823 memory_region_get_ram_addr(mr) + addr, size, client);
1824}
1825
1826bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
1827 hwaddr addr, hwaddr size)
1828{
1829 assert(mr->ram_block);
1830 return cpu_physical_memory_snapshot_get_dirty(snap,
1831 memory_region_get_ram_addr(mr) + addr, size);
1832}
6c279db8 1833
093bc2cd
AK
1834void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1835{
0a752eee 1836 MemoryListener *listener;
0d673e36 1837 AddressSpace *as;
0a752eee 1838 FlatView *view;
5a583347
AK
1839 FlatRange *fr;
1840
0a752eee
PB
1841 /* If the same address space has multiple log_sync listeners, we
1842 * visit that address space's FlatView multiple times. But because
1843 * log_sync listeners are rare, it's still cheaper than walking each
1844 * address space once.
1845 */
1846 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1847 if (!listener->log_sync) {
1848 continue;
1849 }
1850 as = listener->address_space;
1851 view = address_space_get_flatview(as);
99e86347 1852 FOR_EACH_FLAT_RANGE(fr, view) {
0d673e36 1853 if (fr->mr == mr) {
0a752eee
PB
1854 MemoryRegionSection mrs = section_from_flat_range(fr, as);
1855 listener->log_sync(listener, &mrs);
0d673e36 1856 }
5a583347 1857 }
856d7245 1858 flatview_unref(view);
5a583347 1859 }
093bc2cd
AK
1860}
1861
1862void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1863{
fb1cd6f9 1864 if (mr->readonly != readonly) {
59023ef4 1865 memory_region_transaction_begin();
fb1cd6f9 1866 mr->readonly = readonly;
22bde714 1867 memory_region_update_pending |= mr->enabled;
59023ef4 1868 memory_region_transaction_commit();
fb1cd6f9 1869 }
093bc2cd
AK
1870}
1871
5f9a5ea1 1872void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 1873{
5f9a5ea1 1874 if (mr->romd_mode != romd_mode) {
59023ef4 1875 memory_region_transaction_begin();
5f9a5ea1 1876 mr->romd_mode = romd_mode;
22bde714 1877 memory_region_update_pending |= mr->enabled;
59023ef4 1878 memory_region_transaction_commit();
d0a9b5bc
AK
1879 }
1880}
1881
a8170e5e
AK
1882void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
1883 hwaddr size, unsigned client)
093bc2cd 1884{
8e41fb63
FZ
1885 assert(mr->ram_block);
1886 cpu_physical_memory_test_and_clear_dirty(
1887 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK
1888}
1889
a35ba7be
PB
1890int memory_region_get_fd(MemoryRegion *mr)
1891{
4ff87573
PB
1892 int fd;
1893
1894 rcu_read_lock();
1895 while (mr->alias) {
1896 mr = mr->alias;
a35ba7be 1897 }
4ff87573
PB
1898 fd = mr->ram_block->fd;
1899 rcu_read_unlock();
a35ba7be 1900
4ff87573
PB
1901 return fd;
1902}
a35ba7be 1903
093bc2cd
AK
1904void *memory_region_get_ram_ptr(MemoryRegion *mr)
1905{
49b24afc
PB
1906 void *ptr;
1907 uint64_t offset = 0;
093bc2cd 1908
49b24afc
PB
1909 rcu_read_lock();
1910 while (mr->alias) {
1911 offset += mr->alias_offset;
1912 mr = mr->alias;
1913 }
8e41fb63 1914 assert(mr->ram_block);
0878d0e1 1915 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
49b24afc 1916 rcu_read_unlock();
093bc2cd 1917
0878d0e1 1918 return ptr;
093bc2cd
AK
1919}
1920
07bdaa41
PB
1921MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
1922{
1923 RAMBlock *block;
1924
1925 block = qemu_ram_block_from_host(ptr, false, offset);
1926 if (!block) {
1927 return NULL;
1928 }
1929
1930 return block->mr;
1931}
1932
7ebb2745
FZ
1933ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
1934{
1935 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
1936}
1937
37d7c084
PB
1938void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
1939{
8e41fb63 1940 assert(mr->ram_block);
37d7c084 1941
fa53a0e5 1942 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB
1943}
1944
0d673e36 1945static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 1946{
99e86347 1947 FlatView *view;
093bc2cd
AK
1948 FlatRange *fr;
1949 CoalescedMemoryRange *cmr;
1950 AddrRange tmp;
95d2994a 1951 MemoryRegionSection section;
093bc2cd 1952
856d7245 1953 view = address_space_get_flatview(as);
99e86347 1954 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 1955 if (fr->mr == mr) {
95d2994a 1956 section = (MemoryRegionSection) {
f6790af6 1957 .address_space = as,
95d2994a 1958 .offset_within_address_space = int128_get64(fr->addr.start),
052e87b0 1959 .size = fr->addr.size,
95d2994a
AK
1960 };
1961
9a54635d 1962 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
95d2994a
AK
1963 int128_get64(fr->addr.start),
1964 int128_get64(fr->addr.size));
093bc2cd
AK
1965 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
1966 tmp = addrrange_shift(cmr->addr,
08dafab4
AK
1967 int128_sub(fr->addr.start,
1968 int128_make64(fr->offset_in_region)));
093bc2cd
AK
1969 if (!addrrange_intersects(tmp, fr->addr)) {
1970 continue;
1971 }
1972 tmp = addrrange_intersection(tmp, fr->addr);
9a54635d 1973 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
95d2994a
AK
1974 int128_get64(tmp.start),
1975 int128_get64(tmp.size));
093bc2cd
AK
1976 }
1977 }
1978 }
856d7245 1979 flatview_unref(view);
093bc2cd
AK
1980}
1981
0d673e36
AK
1982static void memory_region_update_coalesced_range(MemoryRegion *mr)
1983{
1984 AddressSpace *as;
1985
1986 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1987 memory_region_update_coalesced_range_as(mr, as);
1988 }
1989}
1990
093bc2cd
AK
1991void memory_region_set_coalescing(MemoryRegion *mr)
1992{
1993 memory_region_clear_coalescing(mr);
08dafab4 1994 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK
1995}
1996
1997void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 1998 hwaddr offset,
093bc2cd
AK
1999 uint64_t size)
2000{
7267c094 2001 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2002
08dafab4 2003 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK
2004 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2005 memory_region_update_coalesced_range(mr);
d410515e 2006 memory_region_set_flush_coalesced(mr);
093bc2cd
AK
2007}
2008
2009void memory_region_clear_coalescing(MemoryRegion *mr)
2010{
2011 CoalescedMemoryRange *cmr;
ab5b3db5 2012 bool updated = false;
093bc2cd 2013
d410515e
JK
2014 qemu_flush_coalesced_mmio_buffer();
2015 mr->flush_coalesced_mmio = false;
2016
093bc2cd
AK
2017 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2018 cmr = QTAILQ_FIRST(&mr->coalesced);
2019 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 2020 g_free(cmr);
ab5b3db5
FZ
2021 updated = true;
2022 }
2023
2024 if (updated) {
2025 memory_region_update_coalesced_range(mr);
093bc2cd 2026 }
093bc2cd
AK
2027}
2028
d410515e
JK
2029void memory_region_set_flush_coalesced(MemoryRegion *mr)
2030{
2031 mr->flush_coalesced_mmio = true;
2032}
2033
2034void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2035{
2036 qemu_flush_coalesced_mmio_buffer();
2037 if (QTAILQ_EMPTY(&mr->coalesced)) {
2038 mr->flush_coalesced_mmio = false;
2039 }
2040}
2041
196ea131
JK
2042void memory_region_set_global_locking(MemoryRegion *mr)
2043{
2044 mr->global_locking = true;
2045}
2046
2047void memory_region_clear_global_locking(MemoryRegion *mr)
2048{
2049 mr->global_locking = false;
2050}
2051
8c56c1a5
PF
2052static bool userspace_eventfd_warning;
2053
3e9d69e7 2054void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2055 hwaddr addr,
3e9d69e7
AK
2056 unsigned size,
2057 bool match_data,
2058 uint64_t data,
753d5e14 2059 EventNotifier *e)
3e9d69e7
AK
2060{
2061 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2062 .addr.start = int128_make64(addr),
2063 .addr.size = int128_make64(size),
3e9d69e7
AK
2064 .match_data = match_data,
2065 .data = data,
753d5e14 2066 .e = e,
3e9d69e7
AK
2067 };
2068 unsigned i;
2069
8c56c1a5
PF
2070 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2071 userspace_eventfd_warning))) {
2072 userspace_eventfd_warning = true;
2073 error_report("Using eventfd without MMIO binding in KVM. "
2074 "Suboptimal performance expected");
2075 }
2076
b8aecea2
JW
2077 if (size) {
2078 adjust_endianness(mr, &mrfd.data, size);
2079 }
59023ef4 2080 memory_region_transaction_begin();
3e9d69e7
AK
2081 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2082 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
2083 break;
2084 }
2085 }
2086 ++mr->ioeventfd_nb;
7267c094 2087 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK
2088 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2089 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2090 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2091 mr->ioeventfds[i] = mrfd;
4dc56152 2092 ioeventfd_update_pending |= mr->enabled;
59023ef4 2093 memory_region_transaction_commit();
3e9d69e7
AK
2094}
2095
2096void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2097 hwaddr addr,
3e9d69e7
AK
2098 unsigned size,
2099 bool match_data,
2100 uint64_t data,
753d5e14 2101 EventNotifier *e)
3e9d69e7
AK
2102{
2103 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2104 .addr.start = int128_make64(addr),
2105 .addr.size = int128_make64(size),
3e9d69e7
AK
2106 .match_data = match_data,
2107 .data = data,
753d5e14 2108 .e = e,
3e9d69e7
AK
2109 };
2110 unsigned i;
2111
b8aecea2
JW
2112 if (size) {
2113 adjust_endianness(mr, &mrfd.data, size);
2114 }
59023ef4 2115 memory_region_transaction_begin();
3e9d69e7
AK
2116 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2117 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
2118 break;
2119 }
2120 }
2121 assert(i != mr->ioeventfd_nb);
2122 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2123 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2124 --mr->ioeventfd_nb;
7267c094 2125 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2126 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2127 ioeventfd_update_pending |= mr->enabled;
59023ef4 2128 memory_region_transaction_commit();
3e9d69e7
AK
2129}
2130
feca4ac1 2131static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2132{
feca4ac1 2133 MemoryRegion *mr = subregion->container;
093bc2cd
AK
2134 MemoryRegion *other;
2135
59023ef4
JK
2136 memory_region_transaction_begin();
2137
dfde4e6e 2138 memory_region_ref(subregion);
093bc2cd
AK
2139 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2140 if (subregion->priority >= other->priority) {
2141 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2142 goto done;
2143 }
2144 }
2145 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2146done:
22bde714 2147 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2148 memory_region_transaction_commit();
093bc2cd
AK
2149}
2150
0598701a
PC
2151static void memory_region_add_subregion_common(MemoryRegion *mr,
2152 hwaddr offset,
2153 MemoryRegion *subregion)
2154{
feca4ac1
PB
2155 assert(!subregion->container);
2156 subregion->container = mr;
0598701a 2157 subregion->addr = offset;
feca4ac1 2158 memory_region_update_container_subregions(subregion);
0598701a 2159}
093bc2cd
AK
2160
2161void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2162 hwaddr offset,
093bc2cd
AK
2163 MemoryRegion *subregion)
2164{
093bc2cd
AK
2165 subregion->priority = 0;
2166 memory_region_add_subregion_common(mr, offset, subregion);
2167}
2168
2169void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2170 hwaddr offset,
093bc2cd 2171 MemoryRegion *subregion,
a1ff8ae0 2172 int priority)
093bc2cd 2173{
093bc2cd
AK
2174 subregion->priority = priority;
2175 memory_region_add_subregion_common(mr, offset, subregion);
2176}
2177
2178void memory_region_del_subregion(MemoryRegion *mr,
2179 MemoryRegion *subregion)
2180{
59023ef4 2181 memory_region_transaction_begin();
feca4ac1
PB
2182 assert(subregion->container == mr);
2183 subregion->container = NULL;
093bc2cd 2184 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2185 memory_region_unref(subregion);
22bde714 2186 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2187 memory_region_transaction_commit();
6bba19ba
AK
2188}
2189
2190void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2191{
2192 if (enabled == mr->enabled) {
2193 return;
2194 }
59023ef4 2195 memory_region_transaction_begin();
6bba19ba 2196 mr->enabled = enabled;
22bde714 2197 memory_region_update_pending = true;
59023ef4 2198 memory_region_transaction_commit();
093bc2cd 2199}
1c0ffa58 2200
e7af4c67
MT
2201void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2202{
2203 Int128 s = int128_make64(size);
2204
2205 if (size == UINT64_MAX) {
2206 s = int128_2_64();
2207 }
2208 if (int128_eq(s, mr->size)) {
2209 return;
2210 }
2211 memory_region_transaction_begin();
2212 mr->size = s;
2213 memory_region_update_pending = true;
2214 memory_region_transaction_commit();
2215}
2216
67891b8a 2217static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2218{
feca4ac1 2219 MemoryRegion *container = mr->container;
2282e1af 2220
feca4ac1 2221 if (container) {
67891b8a
PC
2222 memory_region_transaction_begin();
2223 memory_region_ref(mr);
feca4ac1
PB
2224 memory_region_del_subregion(container, mr);
2225 mr->container = container;
2226 memory_region_update_container_subregions(mr);
67891b8a
PC
2227 memory_region_unref(mr);
2228 memory_region_transaction_commit();
2282e1af 2229 }
67891b8a 2230}
2282e1af 2231
67891b8a
PC
2232void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2233{
2234 if (addr != mr->addr) {
2235 mr->addr = addr;
2236 memory_region_readd_subregion(mr);
2237 }
2282e1af
AK
2238}
2239
a8170e5e 2240void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2241{
4703359e 2242 assert(mr->alias);
4703359e 2243
59023ef4 2244 if (offset == mr->alias_offset) {
4703359e
AK
2245 return;
2246 }
2247
59023ef4
JK
2248 memory_region_transaction_begin();
2249 mr->alias_offset = offset;
22bde714 2250 memory_region_update_pending |= mr->enabled;
59023ef4 2251 memory_region_transaction_commit();
4703359e
AK
2252}
2253
a2b257d6
IM
2254uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2255{
2256 return mr->align;
2257}
2258
e2177955
AK
2259static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2260{
2261 const AddrRange *addr = addr_;
2262 const FlatRange *fr = fr_;
2263
2264 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2265 return -1;
2266 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2267 return 1;
2268 }
2269 return 0;
2270}
2271
99e86347 2272static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2273{
99e86347 2274 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK
2275 sizeof(FlatRange), cmp_flatrange_addr);
2276}
2277
eed2bacf
IM
2278bool memory_region_is_mapped(MemoryRegion *mr)
2279{
2280 return mr->container ? true : false;
2281}
2282
c6742b14
PB
2283/* Same as memory_region_find, but it does not add a reference to the
2284 * returned region. It must be called from an RCU critical section.
2285 */
2286static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2287 hwaddr addr, uint64_t size)
e2177955 2288{
052e87b0 2289 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB
2290 MemoryRegion *root;
2291 AddressSpace *as;
2292 AddrRange range;
99e86347 2293 FlatView *view;
73034e9e
PB
2294 FlatRange *fr;
2295
2296 addr += mr->addr;
feca4ac1
PB
2297 for (root = mr; root->container; ) {
2298 root = root->container;
73034e9e
PB
2299 addr += root->addr;
2300 }
e2177955 2301
73034e9e 2302 as = memory_region_to_address_space(root);
eed2bacf
IM
2303 if (!as) {
2304 return ret;
2305 }
73034e9e 2306 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2307
2b647668 2308 view = atomic_rcu_read(&as->current_map);
99e86347 2309 fr = flatview_lookup(view, range);
e2177955 2310 if (!fr) {
c6742b14 2311 return ret;
e2177955
AK
2312 }
2313
99e86347 2314 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK
2315 --fr;
2316 }
2317
2318 ret.mr = fr->mr;
73034e9e 2319 ret.address_space = as;
e2177955
AK
2320 range = addrrange_intersection(range, fr->addr);
2321 ret.offset_within_region = fr->offset_in_region;
2322 ret.offset_within_region += int128_get64(int128_sub(range.start,
2323 fr->addr.start));
052e87b0 2324 ret.size = range.size;
e2177955 2325 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2326 ret.readonly = fr->readonly;
c6742b14
PB
2327 return ret;
2328}
2329
2330MemoryRegionSection memory_region_find(MemoryRegion *mr,
2331 hwaddr addr, uint64_t size)
2332{
2333 MemoryRegionSection ret;
2334 rcu_read_lock();
2335 ret = memory_region_find_rcu(mr, addr, size);
2336 if (ret.mr) {
2337 memory_region_ref(ret.mr);
2338 }
2b647668 2339 rcu_read_unlock();
e2177955
AK
2340 return ret;
2341}
2342
c6742b14
PB
2343bool memory_region_present(MemoryRegion *container, hwaddr addr)
2344{
2345 MemoryRegion *mr;
2346
2347 rcu_read_lock();
2348 mr = memory_region_find_rcu(container, addr, 1).mr;
2349 rcu_read_unlock();
2350 return mr && mr != container;
2351}
2352
9c1f8f44 2353void memory_global_dirty_log_sync(void)
86e775c6 2354{
9c1f8f44
PB
2355 MemoryListener *listener;
2356 AddressSpace *as;
99e86347 2357 FlatView *view;
7664e80c
AK
2358 FlatRange *fr;
2359
9c1f8f44
PB
2360 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2361 if (!listener->log_sync) {
2362 continue;
2363 }
d45fa784 2364 as = listener->address_space;
9c1f8f44
PB
2365 view = address_space_get_flatview(as);
2366 FOR_EACH_FLAT_RANGE(fr, view) {
adaad61c
PB
2367 if (fr->dirty_log_mask) {
2368 MemoryRegionSection mrs = section_from_flat_range(fr, as);
2369 listener->log_sync(listener, &mrs);
2370 }
9c1f8f44
PB
2371 }
2372 flatview_unref(view);
7664e80c
AK
2373 }
2374}
2375
19310760
JZ
2376static VMChangeStateEntry *vmstate_change;
2377
7664e80c
AK
2378void memory_global_dirty_log_start(void)
2379{
19310760
JZ
2380 if (vmstate_change) {
2381 qemu_del_vm_change_state_handler(vmstate_change);
2382 vmstate_change = NULL;
2383 }
2384
7664e80c 2385 global_dirty_log = true;
6f6a5ef3 2386
7376e582 2387 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3
PB
2388
2389 /* Refresh DIRTY_LOG_MIGRATION bit. */
2390 memory_region_transaction_begin();
2391 memory_region_update_pending = true;
2392 memory_region_transaction_commit();
7664e80c
AK
2393}
2394
19310760 2395static void memory_global_dirty_log_do_stop(void)
7664e80c 2396{
7664e80c 2397 global_dirty_log = false;
6f6a5ef3
PB
2398
2399 /* Refresh DIRTY_LOG_MIGRATION bit. */
2400 memory_region_transaction_begin();
2401 memory_region_update_pending = true;
2402 memory_region_transaction_commit();
2403
7376e582 2404 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK
2405}
2406
19310760
JZ
2407static void memory_vm_change_state_handler(void *opaque, int running,
2408 RunState state)
2409{
2410 if (running) {
2411 memory_global_dirty_log_do_stop();
2412
2413 if (vmstate_change) {
2414 qemu_del_vm_change_state_handler(vmstate_change);
2415 vmstate_change = NULL;
2416 }
2417 }
2418}
2419
2420void memory_global_dirty_log_stop(void)
2421{
2422 if (!runstate_is_running()) {
2423 if (vmstate_change) {
2424 return;
2425 }
2426 vmstate_change = qemu_add_vm_change_state_handler(
2427 memory_vm_change_state_handler, NULL);
2428 return;
2429 }
2430
2431 memory_global_dirty_log_do_stop();
2432}
2433
7664e80c
AK
2434static void listener_add_address_space(MemoryListener *listener,
2435 AddressSpace *as)
2436{
99e86347 2437 FlatView *view;
7664e80c
AK
2438 FlatRange *fr;
2439
680a4783
PB
2440 if (listener->begin) {
2441 listener->begin(listener);
2442 }
7664e80c 2443 if (global_dirty_log) {
975aefe0
AK
2444 if (listener->log_global_start) {
2445 listener->log_global_start(listener);
2446 }
7664e80c 2447 }
975aefe0 2448
856d7245 2449 view = address_space_get_flatview(as);
99e86347 2450 FOR_EACH_FLAT_RANGE(fr, view) {
7664e80c
AK
2451 MemoryRegionSection section = {
2452 .mr = fr->mr,
f6790af6 2453 .address_space = as,
7664e80c 2454 .offset_within_region = fr->offset_in_region,
052e87b0 2455 .size = fr->addr.size,
7664e80c 2456 .offset_within_address_space = int128_get64(fr->addr.start),
7a8499e8 2457 .readonly = fr->readonly,
7664e80c 2458 };
680a4783
PB
2459 if (fr->dirty_log_mask && listener->log_start) {
2460 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2461 }
975aefe0
AK
2462 if (listener->region_add) {
2463 listener->region_add(listener, &section);
2464 }
7664e80c 2465 }
680a4783
PB
2466 if (listener->commit) {
2467 listener->commit(listener);
2468 }
856d7245 2469 flatview_unref(view);
7664e80c
AK
2470}
2471
d45fa784 2472void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2473{
72e22d2f
AK
2474 MemoryListener *other = NULL;
2475
d45fa784 2476 listener->address_space = as;
72e22d2f
AK
2477 if (QTAILQ_EMPTY(&memory_listeners)
2478 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2479 memory_listeners)->priority) {
2480 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2481 } else {
2482 QTAILQ_FOREACH(other, &memory_listeners, link) {
2483 if (listener->priority < other->priority) {
2484 break;
2485 }
2486 }
2487 QTAILQ_INSERT_BEFORE(other, listener, link);
2488 }
0d673e36 2489
9a54635d
PB
2490 if (QTAILQ_EMPTY(&as->listeners)
2491 || listener->priority >= QTAILQ_LAST(&as->listeners,
2492 memory_listeners)->priority) {
2493 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2494 } else {
2495 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2496 if (listener->priority < other->priority) {
2497 break;
2498 }
2499 }
2500 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2501 }
2502
d45fa784 2503 listener_add_address_space(listener, as);
7664e80c
AK
2504}
2505
2506void memory_listener_unregister(MemoryListener *listener)
2507{
1d8280c1
PB
2508 if (!listener->address_space) {
2509 return;
2510 }
2511
72e22d2f 2512 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2513 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2514 listener->address_space = NULL;
86e775c6 2515}
e2177955 2516
c9356746
FK
2517bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2518{
2519 void *host;
2520 unsigned size = 0;
2521 unsigned offset = 0;
2522 Object *new_interface;
2523
2524 if (!mr || !mr->ops->request_ptr) {
2525 return false;
2526 }
2527
2528 /*
2529 * Avoid an update if the request_ptr call
2530 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2531 * a cache.
2532 */
2533 memory_region_transaction_begin();
2534
2535 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2536
2537 if (!host || !size) {
2538 memory_region_transaction_commit();
2539 return false;
2540 }
2541
2542 new_interface = object_new("mmio_interface");
2543 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2544 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2545 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2546 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2547 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2548 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2549
2550 memory_region_transaction_commit();
2551 return true;
2552}
2553
2554typedef struct MMIOPtrInvalidate {
2555 MemoryRegion *mr;
2556 hwaddr offset;
2557 unsigned size;
2558 int busy;
2559 int allocated;
2560} MMIOPtrInvalidate;
2561
2562#define MAX_MMIO_INVALIDATE 10
2563static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2564
2565static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2566 run_on_cpu_data data)
2567{
2568 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2569 MemoryRegion *mr = invalidate_data->mr;
2570 hwaddr offset = invalidate_data->offset;
2571 unsigned size = invalidate_data->size;
2572 MemoryRegionSection section = memory_region_find(mr, offset, size);
2573
2574 qemu_mutex_lock_iothread();
2575
2576 /* Reset dirty so this doesn't happen later. */
2577 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2578
2579 if (section.mr != mr) {
2580 /* memory_region_find add a ref on section.mr */
2581 memory_region_unref(section.mr);
2582 if (MMIO_INTERFACE(section.mr->owner)) {
2583 /* We found the interface just drop it. */
2584 object_property_set_bool(section.mr->owner, false, "realized",
2585 NULL);
2586 object_unref(section.mr->owner);
2587 object_unparent(section.mr->owner);
2588 }
2589 }
2590
2591 qemu_mutex_unlock_iothread();
2592
2593 if (invalidate_data->allocated) {
2594 g_free(invalidate_data);
2595 } else {
2596 invalidate_data->busy = 0;
2597 }
2598}
2599
2600void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2601 unsigned size)
2602{
2603 size_t i;
2604 MMIOPtrInvalidate *invalidate_data = NULL;
2605
2606 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2607 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2608 invalidate_data = &mmio_ptr_invalidate_list[i];
2609 break;
2610 }
2611 }
2612
2613 if (!invalidate_data) {
2614 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2615 invalidate_data->allocated = 1;
2616 }
2617
2618 invalidate_data->mr = mr;
2619 invalidate_data->offset = offset;
2620 invalidate_data->size = size;
2621
2622 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2623 RUN_ON_CPU_HOST_PTR(invalidate_data));
2624}
2625
7dca8043 2626void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2627{
ac95190e 2628 memory_region_ref(root);
59023ef4 2629 memory_region_transaction_begin();
f0c02d15 2630 as->ref_count = 1;
8786db7c 2631 as->root = root;
f0c02d15 2632 as->malloced = false;
cc94cd6d 2633 as->current_map = flatview_new();
4c19eb72
AK
2634 as->ioeventfd_nb = 0;
2635 as->ioeventfds = NULL;
9a54635d 2636 QTAILQ_INIT(&as->listeners);
0d673e36 2637 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2638 as->name = g_strdup(name ? name : "anonymous");
9a62e24f 2639 as->dispatch = NULL;
f43793c7
PB
2640 memory_region_update_pending |= root->enabled;
2641 memory_region_transaction_commit();
1c0ffa58 2642}
658b2224 2643
374f2981 2644static void do_address_space_destroy(AddressSpace *as)
83f3c251 2645{
f0c02d15 2646 bool do_free = as->malloced;
078c44f4 2647
83f3c251 2648 address_space_destroy_dispatch(as);
9a54635d 2649 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2650
856d7245 2651 flatview_unref(as->current_map);
7dca8043 2652 g_free(as->name);
4c19eb72 2653 g_free(as->ioeventfds);
ac95190e 2654 memory_region_unref(as->root);
f0c02d15
PC
2655 if (do_free) {
2656 g_free(as);
2657 }
2658}
2659
2660AddressSpace *address_space_init_shareable(MemoryRegion *root, const char *name)
2661{
2662 AddressSpace *as;
2663
2664 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2665 if (root == as->root && as->malloced) {
2666 as->ref_count++;
2667 return as;
2668 }
2669 }
2670
2671 as = g_malloc0(sizeof *as);
2672 address_space_init(as, root, name);
2673 as->malloced = true;
2674 return as;
83f3c251
AK
2675}
2676
374f2981
PB
2677void address_space_destroy(AddressSpace *as)
2678{
ac95190e
PB
2679 MemoryRegion *root = as->root;
2680
f0c02d15
PC
2681 as->ref_count--;
2682 if (as->ref_count) {
2683 return;
2684 }
374f2981
PB
2685 /* Flush out anything from MemoryListeners listening in on this */
2686 memory_region_transaction_begin();
2687 as->root = NULL;
2688 memory_region_transaction_commit();
2689 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2690
2691 /* At this point, as->dispatch and as->current_map are dummy
2692 * entries that the guest should never use. Wait for the old
2693 * values to expire before freeing the data.
2694 */
ac95190e 2695 as->root = root;
374f2981
PB
2696 call_rcu(as, do_address_space_destroy, rcu);
2697}
2698
4e831901
PX
2699static const char *memory_region_type(MemoryRegion *mr)
2700{
2701 if (memory_region_is_ram_device(mr)) {
2702 return "ramd";
2703 } else if (memory_region_is_romd(mr)) {
2704 return "romd";
2705 } else if (memory_region_is_rom(mr)) {
2706 return "rom";
2707 } else if (memory_region_is_ram(mr)) {
2708 return "ram";
2709 } else {
2710 return "i/o";
2711 }
2712}
2713
314e2987
BS
2714typedef struct MemoryRegionList MemoryRegionList;
2715
2716struct MemoryRegionList {
2717 const MemoryRegion *mr;
a16878d2 2718 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS
2719};
2720
a16878d2 2721typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
314e2987 2722
4e831901
PX
2723#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2724 int128_sub((size), int128_one())) : 0)
2725#define MTREE_INDENT " "
2726
314e2987
BS
2727static void mtree_print_mr(fprintf_function mon_printf, void *f,
2728 const MemoryRegion *mr, unsigned int level,
a8170e5e 2729 hwaddr base,
9479c57a 2730 MemoryRegionListHead *alias_print_queue)
314e2987 2731{
9479c57a
JK
2732 MemoryRegionList *new_ml, *ml, *next_ml;
2733 MemoryRegionListHead submr_print_queue;
314e2987
BS
2734 const MemoryRegion *submr;
2735 unsigned int i;
b31f8412 2736 hwaddr cur_start, cur_end;
314e2987 2737
f8a9f720 2738 if (!mr) {
314e2987
BS
2739 return;
2740 }
2741
2742 for (i = 0; i < level; i++) {
4e831901 2743 mon_printf(f, MTREE_INDENT);
314e2987
BS
2744 }
2745
b31f8412
PX
2746 cur_start = base + mr->addr;
2747 cur_end = cur_start + MR_SIZE(mr->size);
2748
2749 /*
2750 * Try to detect overflow of memory region. This should never
2751 * happen normally. When it happens, we dump something to warn the
2752 * user who is observing this.
2753 */
2754 if (cur_start < base || cur_end < cur_start) {
2755 mon_printf(f, "[DETECTED OVERFLOW!] ");
2756 }
2757
314e2987
BS
2758 if (mr->alias) {
2759 MemoryRegionList *ml;
2760 bool found = false;
2761
2762 /* check if the alias is already in the queue */
a16878d2 2763 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2764 if (ml->mr == mr->alias) {
314e2987
BS
2765 found = true;
2766 }
2767 }
2768
2769 if (!found) {
2770 ml = g_new(MemoryRegionList, 1);
2771 ml->mr = mr->alias;
a16878d2 2772 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2773 }
4896d74b 2774 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
4e831901 2775 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
f8a9f720 2776 "-" TARGET_FMT_plx "%s\n",
b31f8412 2777 cur_start, cur_end,
4b474ba7 2778 mr->priority,
4e831901 2779 memory_region_type((MemoryRegion *)mr),
3fb18b4d
PC
2780 memory_region_name(mr),
2781 memory_region_name(mr->alias),
314e2987 2782 mr->alias_offset,
4e831901 2783 mr->alias_offset + MR_SIZE(mr->size),
f8a9f720 2784 mr->enabled ? "" : " [disabled]");
314e2987 2785 } else {
4896d74b 2786 mon_printf(f,
4e831901 2787 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
b31f8412 2788 cur_start, cur_end,
4b474ba7 2789 mr->priority,
4e831901 2790 memory_region_type((MemoryRegion *)mr),
f8a9f720
GH
2791 memory_region_name(mr),
2792 mr->enabled ? "" : " [disabled]");
314e2987 2793 }
9479c57a
JK
2794
2795 QTAILQ_INIT(&submr_print_queue);
2796
314e2987 2797 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
2798 new_ml = g_new(MemoryRegionList, 1);
2799 new_ml->mr = submr;
a16878d2 2800 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK
2801 if (new_ml->mr->addr < ml->mr->addr ||
2802 (new_ml->mr->addr == ml->mr->addr &&
2803 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 2804 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK
2805 new_ml = NULL;
2806 break;
2807 }
2808 }
2809 if (new_ml) {
a16878d2 2810 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK
2811 }
2812 }
2813
a16878d2 2814 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b31f8412 2815 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
9479c57a
JK
2816 alias_print_queue);
2817 }
2818
a16878d2 2819 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 2820 g_free(ml);
314e2987
BS
2821 }
2822}
2823
57bb40c9
PX
2824static void mtree_print_flatview(fprintf_function p, void *f,
2825 AddressSpace *as)
2826{
2827 FlatView *view = address_space_get_flatview(as);
2828 FlatRange *range = &view->ranges[0];
2829 MemoryRegion *mr;
2830 int n = view->nr;
2831
2832 if (n <= 0) {
2833 p(f, MTREE_INDENT "No rendered FlatView for "
2834 "address space '%s'\n", as->name);
2835 flatview_unref(view);
2836 return;
2837 }
2838
2839 while (n--) {
2840 mr = range->mr;
377a07aa
PB
2841 if (range->offset_in_region) {
2842 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2843 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
2844 int128_get64(range->addr.start),
2845 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2846 mr->priority,
2847 range->readonly ? "rom" : memory_region_type(mr),
2848 memory_region_name(mr),
2849 range->offset_in_region);
2850 } else {
2851 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2852 TARGET_FMT_plx " (prio %d, %s): %s\n",
2853 int128_get64(range->addr.start),
2854 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2855 mr->priority,
2856 range->readonly ? "rom" : memory_region_type(mr),
2857 memory_region_name(mr));
2858 }
57bb40c9
PX
2859 range++;
2860 }
2861
2862 flatview_unref(view);
2863}
2864
2865void mtree_info(fprintf_function mon_printf, void *f, bool flatview)
314e2987
BS
2866{
2867 MemoryRegionListHead ml_head;
2868 MemoryRegionList *ml, *ml2;
0d673e36 2869 AddressSpace *as;
314e2987 2870
57bb40c9
PX
2871 if (flatview) {
2872 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2873 mon_printf(f, "address-space (flat view): %s\n", as->name);
2874 mtree_print_flatview(mon_printf, f, as);
2875 mon_printf(f, "\n");
2876 }
2877 return;
2878 }
2879
314e2987
BS
2880 QTAILQ_INIT(&ml_head);
2881
0d673e36 2882 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
e48816aa
GH
2883 mon_printf(f, "address-space: %s\n", as->name);
2884 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
2885 mon_printf(f, "\n");
b9f9be88
BS
2886 }
2887
314e2987 2888 /* print aliased regions */
a16878d2 2889 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
e48816aa
GH
2890 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
2891 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
2892 mon_printf(f, "\n");
314e2987
BS
2893 }
2894
a16878d2 2895 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 2896 g_free(ml);
314e2987 2897 }
314e2987 2898}
b4fefef9 2899
b08199c6
PM
2900void memory_region_init_ram(MemoryRegion *mr,
2901 struct Object *owner,
2902 const char *name,
2903 uint64_t size,
2904 Error **errp)
2905{
2906 DeviceState *owner_dev;
2907 Error *err = NULL;
2908
2909 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
2910 if (err) {
2911 error_propagate(errp, err);
2912 return;
2913 }
2914 /* This will assert if owner is neither NULL nor a DeviceState.
2915 * We only want the owner here for the purposes of defining a
2916 * unique name for migration. TODO: Ideally we should implement
2917 * a naming scheme for Objects which are not DeviceStates, in
2918 * which case we can relax this restriction.
2919 */
2920 owner_dev = DEVICE(owner);
2921 vmstate_register_ram(mr, owner_dev);
2922}
2923
2924void memory_region_init_rom(MemoryRegion *mr,
2925 struct Object *owner,
2926 const char *name,
2927 uint64_t size,
2928 Error **errp)
2929{
2930 DeviceState *owner_dev;
2931 Error *err = NULL;
2932
2933 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
2934 if (err) {
2935 error_propagate(errp, err);
2936 return;
2937 }
2938 /* This will assert if owner is neither NULL nor a DeviceState.
2939 * We only want the owner here for the purposes of defining a
2940 * unique name for migration. TODO: Ideally we should implement
2941 * a naming scheme for Objects which are not DeviceStates, in
2942 * which case we can relax this restriction.
2943 */
2944 owner_dev = DEVICE(owner);
2945 vmstate_register_ram(mr, owner_dev);
2946}
2947
2948void memory_region_init_rom_device(MemoryRegion *mr,
2949 struct Object *owner,
2950 const MemoryRegionOps *ops,
2951 void *opaque,
2952 const char *name,
2953 uint64_t size,
2954 Error **errp)
2955{
2956 DeviceState *owner_dev;
2957 Error *err = NULL;
2958
2959 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
2960 name, size, &err);
2961 if (err) {
2962 error_propagate(errp, err);
2963 return;
2964 }
2965 /* This will assert if owner is neither NULL nor a DeviceState.
2966 * We only want the owner here for the purposes of defining a
2967 * unique name for migration. TODO: Ideally we should implement
2968 * a naming scheme for Objects which are not DeviceStates, in
2969 * which case we can relax this restriction.
2970 */
2971 owner_dev = DEVICE(owner);
2972 vmstate_register_ram(mr, owner_dev);
2973}
2974
b4fefef9
PC
2975static const TypeInfo memory_region_info = {
2976 .parent = TYPE_OBJECT,
2977 .name = TYPE_MEMORY_REGION,
2978 .instance_size = sizeof(MemoryRegion),
2979 .instance_init = memory_region_initfn,
2980 .instance_finalize = memory_region_finalize,
2981};
2982
3df9d748
AK
2983static const TypeInfo iommu_memory_region_info = {
2984 .parent = TYPE_MEMORY_REGION,
2985 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 2986 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK
2987 .instance_size = sizeof(IOMMUMemoryRegion),
2988 .instance_init = iommu_memory_region_initfn,
1221a474 2989 .abstract = true,
3df9d748
AK
2990};
2991
b4fefef9
PC
2992static void memory_register_types(void)
2993{
2994 type_register_static(&memory_region_info);
3df9d748 2995 type_register_static(&iommu_memory_region_info);
b4fefef9
PC
2996}
2997
2998type_init(memory_register_types)