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memory: seek FlatView sharing candidates among children subregions
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CommitLineData
093bc2cd
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1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
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14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879
PB
18#include "qemu-common.h"
19#include "cpu.h"
022c62cb
PB
20#include "exec/memory.h"
21#include "exec/address-spaces.h"
22#include "exec/ioport.h"
409ddd01 23#include "qapi/visitor.h"
1de7afc9 24#include "qemu/bitops.h"
8c56c1a5 25#include "qemu/error-report.h"
2c9b15ca 26#include "qom/object.h"
0ab8ed18 27#include "trace-root.h"
093bc2cd 28
022c62cb 29#include "exec/memory-internal.h"
220c3ebd 30#include "exec/ram_addr.h"
8c56c1a5 31#include "sysemu/kvm.h"
e1c57ab8 32#include "sysemu/sysemu.h"
c9356746
FK
33#include "hw/misc/mmio_interface.h"
34#include "hw/qdev-properties.h"
b08199c6 35#include "migration/vmstate.h"
67d95c15 36
d197063f
PB
37//#define DEBUG_UNASSIGNED
38
22bde714
JK
39static unsigned memory_region_transaction_depth;
40static bool memory_region_update_pending;
4dc56152 41static bool ioeventfd_update_pending;
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42static bool global_dirty_log = false;
43
72e22d2f
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44static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
45 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 46
0d673e36
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47static QTAILQ_HEAD(, AddressSpace) address_spaces
48 = QTAILQ_HEAD_INITIALIZER(address_spaces);
49
967dc9b1
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50static GHashTable *flat_views;
51
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52typedef struct AddrRange AddrRange;
53
8417cebf 54/*
c9cdaa3a 55 * Note that signed integers are needed for negative offsetting in aliases
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56 * (large MemoryRegion::alias_offset).
57 */
093bc2cd 58struct AddrRange {
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59 Int128 start;
60 Int128 size;
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61};
62
08dafab4 63static AddrRange addrrange_make(Int128 start, Int128 size)
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64{
65 return (AddrRange) { start, size };
66}
67
68static bool addrrange_equal(AddrRange r1, AddrRange r2)
69{
08dafab4 70 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
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71}
72
08dafab4 73static Int128 addrrange_end(AddrRange r)
093bc2cd 74{
08dafab4 75 return int128_add(r.start, r.size);
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AK
76}
77
08dafab4 78static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 79{
08dafab4 80 int128_addto(&range.start, delta);
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81 return range;
82}
83
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84static bool addrrange_contains(AddrRange range, Int128 addr)
85{
86 return int128_ge(addr, range.start)
87 && int128_lt(addr, addrrange_end(range));
88}
89
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90static bool addrrange_intersects(AddrRange r1, AddrRange r2)
91{
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92 return addrrange_contains(r1, r2.start)
93 || addrrange_contains(r2, r1.start);
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94}
95
96static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
97{
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98 Int128 start = int128_max(r1.start, r2.start);
99 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
100 return addrrange_make(start, int128_sub(end, start));
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101}
102
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103enum ListenerDirection { Forward, Reverse };
104
7376e582 105#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
AK
106 do { \
107 MemoryListener *_listener; \
108 \
109 switch (_direction) { \
110 case Forward: \
111 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
AK
112 if (_listener->_callback) { \
113 _listener->_callback(_listener, ##_args); \
114 } \
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AK
115 } \
116 break; \
117 case Reverse: \
118 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
119 memory_listeners, link) { \
975aefe0
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120 if (_listener->_callback) { \
121 _listener->_callback(_listener, ##_args); \
122 } \
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123 } \
124 break; \
125 default: \
126 abort(); \
127 } \
128 } while (0)
129
9a54635d 130#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
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131 do { \
132 MemoryListener *_listener; \
9a54635d 133 struct memory_listeners_as *list = &(_as)->listeners; \
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134 \
135 switch (_direction) { \
136 case Forward: \
9a54635d
PB
137 QTAILQ_FOREACH(_listener, list, link_as) { \
138 if (_listener->_callback) { \
7376e582
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139 _listener->_callback(_listener, _section, ##_args); \
140 } \
141 } \
142 break; \
143 case Reverse: \
9a54635d
PB
144 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
145 link_as) { \
146 if (_listener->_callback) { \
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147 _listener->_callback(_listener, _section, ##_args); \
148 } \
149 } \
150 break; \
151 default: \
152 abort(); \
153 } \
154 } while (0)
155
dfde4e6e 156/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 157#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44 158 do { \
16620684
AK
159 MemoryRegionSection mrs = section_from_flat_range(fr, \
160 address_space_to_flatview(as)); \
9a54635d 161 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 162 } while(0)
0e0d36b4 163
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164struct CoalescedMemoryRange {
165 AddrRange addr;
166 QTAILQ_ENTRY(CoalescedMemoryRange) link;
167};
168
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169struct MemoryRegionIoeventfd {
170 AddrRange addr;
171 bool match_data;
172 uint64_t data;
753d5e14 173 EventNotifier *e;
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174};
175
176static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
177 MemoryRegionIoeventfd b)
178{
08dafab4 179 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 180 return true;
08dafab4 181 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 182 return false;
08dafab4 183 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 184 return true;
08dafab4 185 } else if (int128_gt(a.addr.size, b.addr.size)) {
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186 return false;
187 } else if (a.match_data < b.match_data) {
188 return true;
189 } else if (a.match_data > b.match_data) {
190 return false;
191 } else if (a.match_data) {
192 if (a.data < b.data) {
193 return true;
194 } else if (a.data > b.data) {
195 return false;
196 }
197 }
753d5e14 198 if (a.e < b.e) {
3e9d69e7 199 return true;
753d5e14 200 } else if (a.e > b.e) {
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201 return false;
202 }
203 return false;
204}
205
206static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
207 MemoryRegionIoeventfd b)
208{
209 return !memory_region_ioeventfd_before(a, b)
210 && !memory_region_ioeventfd_before(b, a);
211}
212
093bc2cd 213typedef struct FlatRange FlatRange;
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214
215/* Range of memory in the global map. Addresses are absolute. */
216struct FlatRange {
217 MemoryRegion *mr;
a8170e5e 218 hwaddr offset_in_region;
093bc2cd 219 AddrRange addr;
5a583347 220 uint8_t dirty_log_mask;
b138e654 221 bool romd_mode;
fb1cd6f9 222 bool readonly;
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223};
224
225/* Flattened global view of current active memory hierarchy. Kept in sorted
226 * order.
227 */
228struct FlatView {
374f2981 229 struct rcu_head rcu;
856d7245 230 unsigned ref;
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231 FlatRange *ranges;
232 unsigned nr;
233 unsigned nr_allocated;
66a6df1d 234 struct AddressSpaceDispatch *dispatch;
89c177bb 235 MemoryRegion *root;
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236};
237
cc31e6e7
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238typedef struct AddressSpaceOps AddressSpaceOps;
239
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240#define FOR_EACH_FLAT_RANGE(var, view) \
241 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
242
9c1f8f44 243static inline MemoryRegionSection
16620684 244section_from_flat_range(FlatRange *fr, FlatView *fv)
9c1f8f44
PB
245{
246 return (MemoryRegionSection) {
247 .mr = fr->mr,
16620684 248 .fv = fv,
9c1f8f44
PB
249 .offset_within_region = fr->offset_in_region,
250 .size = fr->addr.size,
251 .offset_within_address_space = int128_get64(fr->addr.start),
252 .readonly = fr->readonly,
253 };
254}
255
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256static bool flatrange_equal(FlatRange *a, FlatRange *b)
257{
258 return a->mr == b->mr
259 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 260 && a->offset_in_region == b->offset_in_region
b138e654 261 && a->romd_mode == b->romd_mode
fb1cd6f9 262 && a->readonly == b->readonly;
093bc2cd
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263}
264
89c177bb 265static FlatView *flatview_new(MemoryRegion *mr_root)
093bc2cd 266{
cc94cd6d
AK
267 FlatView *view;
268
269 view = g_new0(FlatView, 1);
856d7245 270 view->ref = 1;
89c177bb
AK
271 view->root = mr_root;
272 memory_region_ref(mr_root);
02d9651d 273 trace_flatview_new(view, mr_root);
cc94cd6d
AK
274
275 return view;
093bc2cd
AK
276}
277
278/* Insert a range into a given position. Caller is responsible for maintaining
279 * sorting order.
280 */
281static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
282{
283 if (view->nr == view->nr_allocated) {
284 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 285 view->ranges = g_realloc(view->ranges,
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286 view->nr_allocated * sizeof(*view->ranges));
287 }
288 memmove(view->ranges + pos + 1, view->ranges + pos,
289 (view->nr - pos) * sizeof(FlatRange));
290 view->ranges[pos] = *range;
dfde4e6e 291 memory_region_ref(range->mr);
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AK
292 ++view->nr;
293}
294
295static void flatview_destroy(FlatView *view)
296{
dfde4e6e
PB
297 int i;
298
02d9651d 299 trace_flatview_destroy(view, view->root);
66a6df1d
AK
300 if (view->dispatch) {
301 address_space_dispatch_free(view->dispatch);
302 }
dfde4e6e
PB
303 for (i = 0; i < view->nr; i++) {
304 memory_region_unref(view->ranges[i].mr);
305 }
7267c094 306 g_free(view->ranges);
89c177bb 307 memory_region_unref(view->root);
a9a0c06d 308 g_free(view);
093bc2cd
AK
309}
310
447b0d0b 311static bool flatview_ref(FlatView *view)
856d7245 312{
447b0d0b 313 return atomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB
314}
315
316static void flatview_unref(FlatView *view)
317{
318 if (atomic_fetch_dec(&view->ref) == 1) {
02d9651d 319 trace_flatview_destroy_rcu(view, view->root);
66a6df1d 320 call_rcu(view, flatview_destroy, rcu);
856d7245
PB
321 }
322}
323
16620684 324FlatView *address_space_to_flatview(AddressSpace *as)
66a6df1d
AK
325{
326 return atomic_rcu_read(&as->current_map);
327}
328
329AddressSpaceDispatch *flatview_to_dispatch(FlatView *fv)
330{
331 return fv->dispatch;
332}
333
334AddressSpaceDispatch *address_space_to_dispatch(AddressSpace *as)
335{
336 return flatview_to_dispatch(address_space_to_flatview(as));
337}
338
3d8e6bf9
AK
339static bool can_merge(FlatRange *r1, FlatRange *r2)
340{
08dafab4 341 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 342 && r1->mr == r2->mr
08dafab4
AK
343 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
344 r1->addr.size),
345 int128_make64(r2->offset_in_region))
d0a9b5bc 346 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 347 && r1->romd_mode == r2->romd_mode
fb1cd6f9 348 && r1->readonly == r2->readonly;
3d8e6bf9
AK
349}
350
8508e024 351/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK
352static void flatview_simplify(FlatView *view)
353{
354 unsigned i, j;
355
356 i = 0;
357 while (i < view->nr) {
358 j = i + 1;
359 while (j < view->nr
360 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 361 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
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362 ++j;
363 }
364 ++i;
365 memmove(&view->ranges[i], &view->ranges[j],
366 (view->nr - j) * sizeof(view->ranges[j]));
367 view->nr -= j - i;
368 }
369}
370
e7342aa3
PB
371static bool memory_region_big_endian(MemoryRegion *mr)
372{
373#ifdef TARGET_WORDS_BIGENDIAN
374 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
375#else
376 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
377#endif
378}
379
e11ef3d1
PB
380static bool memory_region_wrong_endianness(MemoryRegion *mr)
381{
382#ifdef TARGET_WORDS_BIGENDIAN
383 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
384#else
385 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
386#endif
387}
388
389static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
390{
391 if (memory_region_wrong_endianness(mr)) {
392 switch (size) {
393 case 1:
394 break;
395 case 2:
396 *data = bswap16(*data);
397 break;
398 case 4:
399 *data = bswap32(*data);
400 break;
401 case 8:
402 *data = bswap64(*data);
403 break;
404 default:
405 abort();
406 }
407 }
408}
409
4779dc1d
HB
410static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
411{
412 MemoryRegion *root;
413 hwaddr abs_addr = offset;
414
415 abs_addr += mr->addr;
416 for (root = mr; root->container; ) {
417 root = root->container;
418 abs_addr += root->addr;
419 }
420
421 return abs_addr;
422}
423
5a68be94
HB
424static int get_cpu_index(void)
425{
426 if (current_cpu) {
427 return current_cpu->cpu_index;
428 }
429 return -1;
430}
431
cc05c43a
PM
432static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
433 hwaddr addr,
434 uint64_t *value,
435 unsigned size,
436 unsigned shift,
437 uint64_t mask,
438 MemTxAttrs attrs)
439{
440 uint64_t tmp;
441
442 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
23d92d68 443 if (mr->subpage) {
5a68be94 444 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
445 } else if (mr == &io_mem_notdirty) {
446 /* Accesses to code which has previously been translated into a TB show
447 * up in the MMIO path, as accesses to the io_mem_notdirty
448 * MemoryRegion. */
449 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
450 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
451 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 452 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 453 }
cc05c43a
PM
454 *value |= (tmp & mask) << shift;
455 return MEMTX_OK;
456}
457
458static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB
459 hwaddr addr,
460 uint64_t *value,
461 unsigned size,
462 unsigned shift,
cc05c43a
PM
463 uint64_t mask,
464 MemTxAttrs attrs)
ce5d2f33 465{
ce5d2f33
PB
466 uint64_t tmp;
467
cc05c43a 468 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 469 if (mr->subpage) {
5a68be94 470 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
471 } else if (mr == &io_mem_notdirty) {
472 /* Accesses to code which has previously been translated into a TB show
473 * up in the MMIO path, as accesses to the io_mem_notdirty
474 * MemoryRegion. */
475 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
476 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
477 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 478 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 479 }
ce5d2f33 480 *value |= (tmp & mask) << shift;
cc05c43a 481 return MEMTX_OK;
ce5d2f33
PB
482}
483
cc05c43a
PM
484static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
485 hwaddr addr,
486 uint64_t *value,
487 unsigned size,
488 unsigned shift,
489 uint64_t mask,
490 MemTxAttrs attrs)
164a4dcd 491{
cc05c43a
PM
492 uint64_t tmp = 0;
493 MemTxResult r;
164a4dcd 494
cc05c43a 495 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 496 if (mr->subpage) {
5a68be94 497 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
498 } else if (mr == &io_mem_notdirty) {
499 /* Accesses to code which has previously been translated into a TB show
500 * up in the MMIO path, as accesses to the io_mem_notdirty
501 * MemoryRegion. */
502 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
503 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
504 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 505 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 506 }
164a4dcd 507 *value |= (tmp & mask) << shift;
cc05c43a 508 return r;
164a4dcd
AK
509}
510
cc05c43a
PM
511static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
512 hwaddr addr,
513 uint64_t *value,
514 unsigned size,
515 unsigned shift,
516 uint64_t mask,
517 MemTxAttrs attrs)
ce5d2f33 518{
ce5d2f33
PB
519 uint64_t tmp;
520
521 tmp = (*value >> shift) & mask;
23d92d68 522 if (mr->subpage) {
5a68be94 523 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
524 } else if (mr == &io_mem_notdirty) {
525 /* Accesses to code which has previously been translated into a TB show
526 * up in the MMIO path, as accesses to the io_mem_notdirty
527 * MemoryRegion. */
528 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
529 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
530 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 531 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 532 }
ce5d2f33 533 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
cc05c43a 534 return MEMTX_OK;
ce5d2f33
PB
535}
536
cc05c43a
PM
537static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
538 hwaddr addr,
539 uint64_t *value,
540 unsigned size,
541 unsigned shift,
542 uint64_t mask,
543 MemTxAttrs attrs)
164a4dcd 544{
164a4dcd
AK
545 uint64_t tmp;
546
547 tmp = (*value >> shift) & mask;
23d92d68 548 if (mr->subpage) {
5a68be94 549 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
550 } else if (mr == &io_mem_notdirty) {
551 /* Accesses to code which has previously been translated into a TB show
552 * up in the MMIO path, as accesses to the io_mem_notdirty
553 * MemoryRegion. */
554 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
555 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
556 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 557 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 558 }
164a4dcd 559 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 560 return MEMTX_OK;
164a4dcd
AK
561}
562
cc05c43a
PM
563static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
564 hwaddr addr,
565 uint64_t *value,
566 unsigned size,
567 unsigned shift,
568 uint64_t mask,
569 MemTxAttrs attrs)
570{
571 uint64_t tmp;
572
cc05c43a 573 tmp = (*value >> shift) & mask;
23d92d68 574 if (mr->subpage) {
5a68be94 575 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
576 } else if (mr == &io_mem_notdirty) {
577 /* Accesses to code which has previously been translated into a TB show
578 * up in the MMIO path, as accesses to the io_mem_notdirty
579 * MemoryRegion. */
580 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
581 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
582 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 583 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 584 }
cc05c43a
PM
585 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
586}
587
588static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK
589 uint64_t *value,
590 unsigned size,
591 unsigned access_size_min,
592 unsigned access_size_max,
05e015f7
KF
593 MemTxResult (*access_fn)
594 (MemoryRegion *mr,
595 hwaddr addr,
596 uint64_t *value,
597 unsigned size,
598 unsigned shift,
599 uint64_t mask,
600 MemTxAttrs attrs),
cc05c43a
PM
601 MemoryRegion *mr,
602 MemTxAttrs attrs)
164a4dcd
AK
603{
604 uint64_t access_mask;
605 unsigned access_size;
606 unsigned i;
cc05c43a 607 MemTxResult r = MEMTX_OK;
164a4dcd
AK
608
609 if (!access_size_min) {
610 access_size_min = 1;
611 }
612 if (!access_size_max) {
613 access_size_max = 4;
614 }
ce5d2f33
PB
615
616 /* FIXME: support unaligned access? */
164a4dcd
AK
617 access_size = MAX(MIN(size, access_size_max), access_size_min);
618 access_mask = -1ULL >> (64 - access_size * 8);
e7342aa3
PB
619 if (memory_region_big_endian(mr)) {
620 for (i = 0; i < size; i += access_size) {
05e015f7 621 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 622 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB
623 }
624 } else {
625 for (i = 0; i < size; i += access_size) {
05e015f7 626 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 627 access_mask, attrs);
e7342aa3 628 }
164a4dcd 629 }
cc05c43a 630 return r;
164a4dcd
AK
631}
632
e2177955
AK
633static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
634{
0d673e36
AK
635 AddressSpace *as;
636
feca4ac1
PB
637 while (mr->container) {
638 mr = mr->container;
e2177955 639 }
0d673e36
AK
640 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
641 if (mr == as->root) {
642 return as;
643 }
e2177955 644 }
eed2bacf 645 return NULL;
e2177955
AK
646}
647
093bc2cd
AK
648/* Render a memory region into the global view. Ranges in @view obscure
649 * ranges in @mr.
650 */
651static void render_memory_region(FlatView *view,
652 MemoryRegion *mr,
08dafab4 653 Int128 base,
fb1cd6f9
AK
654 AddrRange clip,
655 bool readonly)
093bc2cd
AK
656{
657 MemoryRegion *subregion;
658 unsigned i;
a8170e5e 659 hwaddr offset_in_region;
08dafab4
AK
660 Int128 remain;
661 Int128 now;
093bc2cd
AK
662 FlatRange fr;
663 AddrRange tmp;
664
6bba19ba
AK
665 if (!mr->enabled) {
666 return;
667 }
668
08dafab4 669 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 670 readonly |= mr->readonly;
093bc2cd
AK
671
672 tmp = addrrange_make(base, mr->size);
673
674 if (!addrrange_intersects(tmp, clip)) {
675 return;
676 }
677
678 clip = addrrange_intersection(tmp, clip);
679
680 if (mr->alias) {
08dafab4
AK
681 int128_subfrom(&base, int128_make64(mr->alias->addr));
682 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 683 render_memory_region(view, mr->alias, base, clip, readonly);
093bc2cd
AK
684 return;
685 }
686
687 /* Render subregions in priority order. */
688 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 689 render_memory_region(view, subregion, base, clip, readonly);
093bc2cd
AK
690 }
691
14a3c10a 692 if (!mr->terminates) {
093bc2cd
AK
693 return;
694 }
695
08dafab4 696 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK
697 base = clip.start;
698 remain = clip.size;
699
2eb74e1a 700 fr.mr = mr;
6f6a5ef3 701 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 702 fr.romd_mode = mr->romd_mode;
2eb74e1a
PC
703 fr.readonly = readonly;
704
093bc2cd 705 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK
706 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
707 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK
708 continue;
709 }
08dafab4
AK
710 if (int128_lt(base, view->ranges[i].addr.start)) {
711 now = int128_min(remain,
712 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK
713 fr.offset_in_region = offset_in_region;
714 fr.addr = addrrange_make(base, now);
715 flatview_insert(view, i, &fr);
716 ++i;
08dafab4
AK
717 int128_addto(&base, now);
718 offset_in_region += int128_get64(now);
719 int128_subfrom(&remain, now);
093bc2cd 720 }
d26a8cae
AK
721 now = int128_sub(int128_min(int128_add(base, remain),
722 addrrange_end(view->ranges[i].addr)),
723 base);
724 int128_addto(&base, now);
725 offset_in_region += int128_get64(now);
726 int128_subfrom(&remain, now);
093bc2cd 727 }
08dafab4 728 if (int128_nz(remain)) {
093bc2cd
AK
729 fr.offset_in_region = offset_in_region;
730 fr.addr = addrrange_make(base, remain);
731 flatview_insert(view, i, &fr);
732 }
733}
734
89c177bb
AK
735static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
736{
e673ba9a
PB
737 while (mr->enabled) {
738 if (mr->alias) {
739 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
740 /* The alias is included in its entirety. Use it as
741 * the "real" root, so that we can share more FlatViews.
742 */
743 mr = mr->alias;
744 continue;
745 }
746 } else if (!mr->terminates) {
747 unsigned int found = 0;
748 MemoryRegion *child, *next = NULL;
749 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
750 if (child->enabled) {
751 if (++found > 1) {
752 next = NULL;
753 break;
754 }
755 if (!child->addr && int128_ge(mr->size, child->size)) {
756 /* A child is included in its entirety. If it's the only
757 * enabled one, use it in the hope of finding an alias down the
758 * way. This will also let us share FlatViews.
759 */
760 next = child;
761 }
762 }
763 }
764 if (next) {
765 mr = next;
766 continue;
767 }
768 }
769
770 break;
89c177bb
AK
771 }
772
773 return mr;
774}
775
093bc2cd 776/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 777static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 778{
9bf561e3 779 int i;
a9a0c06d 780 FlatView *view;
093bc2cd 781
89c177bb 782 view = flatview_new(mr);
093bc2cd 783
83f3c251 784 if (mr) {
a9a0c06d 785 render_memory_region(view, mr, int128_zero(),
83f3c251
AK
786 addrrange_make(int128_zero(), int128_2_64()), false);
787 }
a9a0c06d 788 flatview_simplify(view);
093bc2cd 789
9bf561e3
AK
790 view->dispatch = address_space_dispatch_new(view);
791 for (i = 0; i < view->nr; i++) {
792 MemoryRegionSection mrs =
793 section_from_flat_range(&view->ranges[i], view);
794 flatview_add_to_dispatch(view, &mrs);
795 }
796 address_space_dispatch_compact(view->dispatch);
967dc9b1 797 g_hash_table_replace(flat_views, mr, view);
9bf561e3 798
093bc2cd
AK
799 return view;
800}
801
3e9d69e7
AK
802static void address_space_add_del_ioeventfds(AddressSpace *as,
803 MemoryRegionIoeventfd *fds_new,
804 unsigned fds_new_nb,
805 MemoryRegionIoeventfd *fds_old,
806 unsigned fds_old_nb)
807{
808 unsigned iold, inew;
80a1ea37
AK
809 MemoryRegionIoeventfd *fd;
810 MemoryRegionSection section;
3e9d69e7
AK
811
812 /* Generate a symmetric difference of the old and new fd sets, adding
813 * and deleting as necessary.
814 */
815
816 iold = inew = 0;
817 while (iold < fds_old_nb || inew < fds_new_nb) {
818 if (iold < fds_old_nb
819 && (inew == fds_new_nb
820 || memory_region_ioeventfd_before(fds_old[iold],
821 fds_new[inew]))) {
80a1ea37
AK
822 fd = &fds_old[iold];
823 section = (MemoryRegionSection) {
16620684 824 .fv = address_space_to_flatview(as),
80a1ea37 825 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 826 .size = fd->addr.size,
80a1ea37 827 };
9a54635d 828 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 829 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
830 ++iold;
831 } else if (inew < fds_new_nb
832 && (iold == fds_old_nb
833 || memory_region_ioeventfd_before(fds_new[inew],
834 fds_old[iold]))) {
80a1ea37
AK
835 fd = &fds_new[inew];
836 section = (MemoryRegionSection) {
16620684 837 .fv = address_space_to_flatview(as),
80a1ea37 838 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 839 .size = fd->addr.size,
80a1ea37 840 };
9a54635d 841 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 842 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
843 ++inew;
844 } else {
845 ++iold;
846 ++inew;
847 }
848 }
849}
850
856d7245
PB
851static FlatView *address_space_get_flatview(AddressSpace *as)
852{
853 FlatView *view;
854
374f2981 855 rcu_read_lock();
447b0d0b 856 do {
16620684 857 view = address_space_to_flatview(as);
447b0d0b
PB
858 /* If somebody has replaced as->current_map concurrently,
859 * flatview_ref returns false.
860 */
861 } while (!flatview_ref(view));
374f2981 862 rcu_read_unlock();
856d7245
PB
863 return view;
864}
865
3e9d69e7
AK
866static void address_space_update_ioeventfds(AddressSpace *as)
867{
99e86347 868 FlatView *view;
3e9d69e7
AK
869 FlatRange *fr;
870 unsigned ioeventfd_nb = 0;
871 MemoryRegionIoeventfd *ioeventfds = NULL;
872 AddrRange tmp;
873 unsigned i;
874
856d7245 875 view = address_space_get_flatview(as);
99e86347 876 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK
877 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
878 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK
879 int128_sub(fr->addr.start,
880 int128_make64(fr->offset_in_region)));
3e9d69e7
AK
881 if (addrrange_intersects(fr->addr, tmp)) {
882 ++ioeventfd_nb;
7267c094 883 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK
884 ioeventfd_nb * sizeof(*ioeventfds));
885 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
886 ioeventfds[ioeventfd_nb-1].addr = tmp;
887 }
888 }
889 }
890
891 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
892 as->ioeventfds, as->ioeventfd_nb);
893
7267c094 894 g_free(as->ioeventfds);
3e9d69e7
AK
895 as->ioeventfds = ioeventfds;
896 as->ioeventfd_nb = ioeventfd_nb;
856d7245 897 flatview_unref(view);
3e9d69e7
AK
898}
899
b8af1afb 900static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB
901 const FlatView *old_view,
902 const FlatView *new_view,
b8af1afb 903 bool adding)
093bc2cd 904{
093bc2cd
AK
905 unsigned iold, inew;
906 FlatRange *frold, *frnew;
093bc2cd
AK
907
908 /* Generate a symmetric difference of the old and new memory maps.
909 * Kill ranges in the old map, and instantiate ranges in the new map.
910 */
911 iold = inew = 0;
a9a0c06d
PB
912 while (iold < old_view->nr || inew < new_view->nr) {
913 if (iold < old_view->nr) {
914 frold = &old_view->ranges[iold];
093bc2cd
AK
915 } else {
916 frold = NULL;
917 }
a9a0c06d
PB
918 if (inew < new_view->nr) {
919 frnew = &new_view->ranges[inew];
093bc2cd
AK
920 } else {
921 frnew = NULL;
922 }
923
924 if (frold
925 && (!frnew
08dafab4
AK
926 || int128_lt(frold->addr.start, frnew->addr.start)
927 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 928 && !flatrange_equal(frold, frnew)))) {
41a6e477 929 /* In old but not in new, or in both but attributes changed. */
093bc2cd 930
b8af1afb 931 if (!adding) {
72e22d2f 932 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK
933 }
934
093bc2cd
AK
935 ++iold;
936 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 937 /* In both and unchanged (except logging may have changed) */
093bc2cd 938
b8af1afb 939 if (adding) {
50c1e149 940 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB
941 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
942 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
943 frold->dirty_log_mask,
944 frnew->dirty_log_mask);
945 }
946 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
947 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
948 frold->dirty_log_mask,
949 frnew->dirty_log_mask);
b8af1afb 950 }
5a583347
AK
951 }
952
093bc2cd
AK
953 ++iold;
954 ++inew;
093bc2cd
AK
955 } else {
956 /* In new */
957
b8af1afb 958 if (adding) {
72e22d2f 959 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK
960 }
961
093bc2cd
AK
962 ++inew;
963 }
964 }
b8af1afb
AK
965}
966
967dc9b1
AK
967static void flatviews_init(void)
968{
969 if (flat_views) {
970 return;
971 }
972
973 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
974 (GDestroyNotify) flatview_unref);
975}
976
977static void flatviews_reset(void)
978{
979 AddressSpace *as;
980
981 if (flat_views) {
982 g_hash_table_unref(flat_views);
983 flat_views = NULL;
984 }
985 flatviews_init();
986
987 /* Render unique FVs */
988 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
989 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
990
991 if (g_hash_table_lookup(flat_views, physmr)) {
992 continue;
993 }
994
995 generate_memory_topology(physmr);
996 }
997}
998
999static void address_space_set_flatview(AddressSpace *as)
b8af1afb 1000{
67ace39b 1001 FlatView *old_view = address_space_to_flatview(as);
967dc9b1
AK
1002 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1003 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1004
1005 assert(new_view);
1006
67ace39b
AK
1007 if (old_view == new_view) {
1008 return;
1009 }
1010
1011 if (old_view) {
1012 flatview_ref(old_view);
1013 }
1014
967dc9b1 1015 flatview_ref(new_view);
9a62e24f
AK
1016
1017 if (!QTAILQ_EMPTY(&as->listeners)) {
67ace39b
AK
1018 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1019
1020 if (!old_view2) {
1021 old_view2 = &tmpview;
1022 }
1023 address_space_update_topology_pass(as, old_view2, new_view, false);
1024 address_space_update_topology_pass(as, old_view2, new_view, true);
9a62e24f 1025 }
b8af1afb 1026
374f2981
PB
1027 /* Writes are protected by the BQL. */
1028 atomic_rcu_set(&as->current_map, new_view);
67ace39b
AK
1029 if (old_view) {
1030 flatview_unref(old_view);
1031 }
856d7245
PB
1032
1033 /* Note that all the old MemoryRegions are still alive up to this
1034 * point. This relieves most MemoryListeners from the need to
1035 * ref/unref the MemoryRegions they get---unless they use them
1036 * outside the iothread mutex, in which case precise reference
1037 * counting is necessary.
1038 */
67ace39b
AK
1039 if (old_view) {
1040 flatview_unref(old_view);
1041 }
093bc2cd
AK
1042}
1043
202fc01b
AK
1044static void address_space_update_topology(AddressSpace *as)
1045{
1046 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1047
1048 flatviews_init();
1049 if (!g_hash_table_lookup(flat_views, physmr)) {
1050 generate_memory_topology(physmr);
1051 }
1052 address_space_set_flatview(as);
1053}
1054
4ef4db86
AK
1055void memory_region_transaction_begin(void)
1056{
bb880ded 1057 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK
1058 ++memory_region_transaction_depth;
1059}
1060
1061void memory_region_transaction_commit(void)
1062{
0d673e36
AK
1063 AddressSpace *as;
1064
4ef4db86 1065 assert(memory_region_transaction_depth);
8d04fb55
JK
1066 assert(qemu_mutex_iothread_locked());
1067
4ef4db86 1068 --memory_region_transaction_depth;
4dc56152
GA
1069 if (!memory_region_transaction_depth) {
1070 if (memory_region_update_pending) {
967dc9b1
AK
1071 flatviews_reset();
1072
4dc56152 1073 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 1074
4dc56152 1075 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
967dc9b1 1076 address_space_set_flatview(as);
02218487 1077 address_space_update_ioeventfds(as);
4dc56152 1078 }
ade9c1aa 1079 memory_region_update_pending = false;
4dc56152
GA
1080 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1081 } else if (ioeventfd_update_pending) {
1082 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1083 address_space_update_ioeventfds(as);
1084 }
ade9c1aa 1085 ioeventfd_update_pending = false;
4dc56152 1086 }
4dc56152 1087 }
4ef4db86
AK
1088}
1089
545e92e0
AK
1090static void memory_region_destructor_none(MemoryRegion *mr)
1091{
1092}
1093
1094static void memory_region_destructor_ram(MemoryRegion *mr)
1095{
f1060c55 1096 qemu_ram_free(mr->ram_block);
545e92e0
AK
1097}
1098
b4fefef9
PC
1099static bool memory_region_need_escape(char c)
1100{
1101 return c == '/' || c == '[' || c == '\\' || c == ']';
1102}
1103
1104static char *memory_region_escape_name(const char *name)
1105{
1106 const char *p;
1107 char *escaped, *q;
1108 uint8_t c;
1109 size_t bytes = 0;
1110
1111 for (p = name; *p; p++) {
1112 bytes += memory_region_need_escape(*p) ? 4 : 1;
1113 }
1114 if (bytes == p - name) {
1115 return g_memdup(name, bytes + 1);
1116 }
1117
1118 escaped = g_malloc(bytes + 1);
1119 for (p = name, q = escaped; *p; p++) {
1120 c = *p;
1121 if (unlikely(memory_region_need_escape(c))) {
1122 *q++ = '\\';
1123 *q++ = 'x';
1124 *q++ = "0123456789abcdef"[c >> 4];
1125 c = "0123456789abcdef"[c & 15];
1126 }
1127 *q++ = c;
1128 }
1129 *q = 0;
1130 return escaped;
1131}
1132
3df9d748
AK
1133static void memory_region_do_init(MemoryRegion *mr,
1134 Object *owner,
1135 const char *name,
1136 uint64_t size)
093bc2cd 1137{
08dafab4
AK
1138 mr->size = int128_make64(size);
1139 if (size == UINT64_MAX) {
1140 mr->size = int128_2_64();
1141 }
302fa283 1142 mr->name = g_strdup(name);
612263cf 1143 mr->owner = owner;
58eaa217 1144 mr->ram_block = NULL;
b4fefef9
PC
1145
1146 if (name) {
843ef73a
PC
1147 char *escaped_name = memory_region_escape_name(name);
1148 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB
1149
1150 if (!owner) {
1151 owner = container_get(qdev_get_machine(), "/unattached");
1152 }
1153
843ef73a 1154 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1155 object_unref(OBJECT(mr));
843ef73a
PC
1156 g_free(name_array);
1157 g_free(escaped_name);
b4fefef9
PC
1158 }
1159}
1160
3df9d748
AK
1161void memory_region_init(MemoryRegion *mr,
1162 Object *owner,
1163 const char *name,
1164 uint64_t size)
1165{
1166 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1167 memory_region_do_init(mr, owner, name, size);
1168}
1169
d7bce999
EB
1170static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1171 void *opaque, Error **errp)
409ddd01
PC
1172{
1173 MemoryRegion *mr = MEMORY_REGION(obj);
1174 uint64_t value = mr->addr;
1175
51e72bc1 1176 visit_type_uint64(v, name, &value, errp);
409ddd01
PC
1177}
1178
d7bce999
EB
1179static void memory_region_get_container(Object *obj, Visitor *v,
1180 const char *name, void *opaque,
1181 Error **errp)
409ddd01
PC
1182{
1183 MemoryRegion *mr = MEMORY_REGION(obj);
1184 gchar *path = (gchar *)"";
1185
1186 if (mr->container) {
1187 path = object_get_canonical_path(OBJECT(mr->container));
1188 }
51e72bc1 1189 visit_type_str(v, name, &path, errp);
409ddd01
PC
1190 if (mr->container) {
1191 g_free(path);
1192 }
1193}
1194
1195static Object *memory_region_resolve_container(Object *obj, void *opaque,
1196 const char *part)
1197{
1198 MemoryRegion *mr = MEMORY_REGION(obj);
1199
1200 return OBJECT(mr->container);
1201}
1202
d7bce999
EB
1203static void memory_region_get_priority(Object *obj, Visitor *v,
1204 const char *name, void *opaque,
1205 Error **errp)
d33382da
PC
1206{
1207 MemoryRegion *mr = MEMORY_REGION(obj);
1208 int32_t value = mr->priority;
1209
51e72bc1 1210 visit_type_int32(v, name, &value, errp);
d33382da
PC
1211}
1212
d7bce999
EB
1213static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1214 void *opaque, Error **errp)
52aef7bb
PC
1215{
1216 MemoryRegion *mr = MEMORY_REGION(obj);
1217 uint64_t value = memory_region_size(mr);
1218
51e72bc1 1219 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC
1220}
1221
b4fefef9
PC
1222static void memory_region_initfn(Object *obj)
1223{
1224 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1225 ObjectProperty *op;
b4fefef9
PC
1226
1227 mr->ops = &unassigned_mem_ops;
6bba19ba 1228 mr->enabled = true;
5f9a5ea1 1229 mr->romd_mode = true;
196ea131 1230 mr->global_locking = true;
545e92e0 1231 mr->destructor = memory_region_destructor_none;
093bc2cd 1232 QTAILQ_INIT(&mr->subregions);
093bc2cd 1233 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC
1234
1235 op = object_property_add(OBJECT(mr), "container",
1236 "link<" TYPE_MEMORY_REGION ">",
1237 memory_region_get_container,
1238 NULL, /* memory_region_set_container */
1239 NULL, NULL, &error_abort);
1240 op->resolve = memory_region_resolve_container;
1241
1242 object_property_add(OBJECT(mr), "addr", "uint64",
1243 memory_region_get_addr,
1244 NULL, /* memory_region_set_addr */
1245 NULL, NULL, &error_abort);
d33382da
PC
1246 object_property_add(OBJECT(mr), "priority", "uint32",
1247 memory_region_get_priority,
1248 NULL, /* memory_region_set_priority */
1249 NULL, NULL, &error_abort);
52aef7bb
PC
1250 object_property_add(OBJECT(mr), "size", "uint64",
1251 memory_region_get_size,
1252 NULL, /* memory_region_set_size, */
1253 NULL, NULL, &error_abort);
093bc2cd
AK
1254}
1255
3df9d748
AK
1256static void iommu_memory_region_initfn(Object *obj)
1257{
1258 MemoryRegion *mr = MEMORY_REGION(obj);
1259
1260 mr->is_iommu = true;
1261}
1262
b018ddf6
PB
1263static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1264 unsigned size)
1265{
1266#ifdef DEBUG_UNASSIGNED
1267 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1268#endif
4917cf44
AF
1269 if (current_cpu != NULL) {
1270 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
c658b94f 1271 }
68a7439a 1272 return 0;
b018ddf6
PB
1273}
1274
1275static void unassigned_mem_write(void *opaque, hwaddr addr,
1276 uint64_t val, unsigned size)
1277{
1278#ifdef DEBUG_UNASSIGNED
1279 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1280#endif
4917cf44
AF
1281 if (current_cpu != NULL) {
1282 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1283 }
b018ddf6
PB
1284}
1285
d197063f
PB
1286static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1287 unsigned size, bool is_write)
1288{
1289 return false;
1290}
1291
1292const MemoryRegionOps unassigned_mem_ops = {
1293 .valid.accepts = unassigned_mem_accepts,
1294 .endianness = DEVICE_NATIVE_ENDIAN,
1295};
1296
4a2e242b
AW
1297static uint64_t memory_region_ram_device_read(void *opaque,
1298 hwaddr addr, unsigned size)
1299{
1300 MemoryRegion *mr = opaque;
1301 uint64_t data = (uint64_t)~0;
1302
1303 switch (size) {
1304 case 1:
1305 data = *(uint8_t *)(mr->ram_block->host + addr);
1306 break;
1307 case 2:
1308 data = *(uint16_t *)(mr->ram_block->host + addr);
1309 break;
1310 case 4:
1311 data = *(uint32_t *)(mr->ram_block->host + addr);
1312 break;
1313 case 8:
1314 data = *(uint64_t *)(mr->ram_block->host + addr);
1315 break;
1316 }
1317
1318 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1319
1320 return data;
1321}
1322
1323static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1324 uint64_t data, unsigned size)
1325{
1326 MemoryRegion *mr = opaque;
1327
1328 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1329
1330 switch (size) {
1331 case 1:
1332 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1333 break;
1334 case 2:
1335 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1336 break;
1337 case 4:
1338 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1339 break;
1340 case 8:
1341 *(uint64_t *)(mr->ram_block->host + addr) = data;
1342 break;
1343 }
1344}
1345
1346static const MemoryRegionOps ram_device_mem_ops = {
1347 .read = memory_region_ram_device_read,
1348 .write = memory_region_ram_device_write,
c99a29e7 1349 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW
1350 .valid = {
1351 .min_access_size = 1,
1352 .max_access_size = 8,
1353 .unaligned = true,
1354 },
1355 .impl = {
1356 .min_access_size = 1,
1357 .max_access_size = 8,
1358 .unaligned = true,
1359 },
1360};
1361
d2702032
PB
1362bool memory_region_access_valid(MemoryRegion *mr,
1363 hwaddr addr,
1364 unsigned size,
1365 bool is_write)
093bc2cd 1366{
a014ed07
PB
1367 int access_size_min, access_size_max;
1368 int access_size, i;
897fa7cf 1369
093bc2cd
AK
1370 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1371 return false;
1372 }
1373
a014ed07 1374 if (!mr->ops->valid.accepts) {
093bc2cd
AK
1375 return true;
1376 }
1377
a014ed07
PB
1378 access_size_min = mr->ops->valid.min_access_size;
1379 if (!mr->ops->valid.min_access_size) {
1380 access_size_min = 1;
1381 }
1382
1383 access_size_max = mr->ops->valid.max_access_size;
1384 if (!mr->ops->valid.max_access_size) {
1385 access_size_max = 4;
1386 }
1387
1388 access_size = MAX(MIN(size, access_size_max), access_size_min);
1389 for (i = 0; i < size; i += access_size) {
1390 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1391 is_write)) {
1392 return false;
1393 }
093bc2cd 1394 }
a014ed07 1395
093bc2cd
AK
1396 return true;
1397}
1398
cc05c43a
PM
1399static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1400 hwaddr addr,
1401 uint64_t *pval,
1402 unsigned size,
1403 MemTxAttrs attrs)
093bc2cd 1404{
cc05c43a 1405 *pval = 0;
093bc2cd 1406
ce5d2f33 1407 if (mr->ops->read) {
cc05c43a
PM
1408 return access_with_adjusted_size(addr, pval, size,
1409 mr->ops->impl.min_access_size,
1410 mr->ops->impl.max_access_size,
1411 memory_region_read_accessor,
1412 mr, attrs);
1413 } else if (mr->ops->read_with_attrs) {
1414 return access_with_adjusted_size(addr, pval, size,
1415 mr->ops->impl.min_access_size,
1416 mr->ops->impl.max_access_size,
1417 memory_region_read_with_attrs_accessor,
1418 mr, attrs);
ce5d2f33 1419 } else {
cc05c43a
PM
1420 return access_with_adjusted_size(addr, pval, size, 1, 4,
1421 memory_region_oldmmio_read_accessor,
1422 mr, attrs);
74901c3b 1423 }
093bc2cd
AK
1424}
1425
3b643495
PM
1426MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1427 hwaddr addr,
1428 uint64_t *pval,
1429 unsigned size,
1430 MemTxAttrs attrs)
a621f38d 1431{
cc05c43a
PM
1432 MemTxResult r;
1433
791af8c8
PB
1434 if (!memory_region_access_valid(mr, addr, size, false)) {
1435 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1436 return MEMTX_DECODE_ERROR;
791af8c8 1437 }
a621f38d 1438
cc05c43a 1439 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1440 adjust_endianness(mr, pval, size);
cc05c43a 1441 return r;
a621f38d 1442}
093bc2cd 1443
8c56c1a5
PF
1444/* Return true if an eventfd was signalled */
1445static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1446 hwaddr addr,
1447 uint64_t data,
1448 unsigned size,
1449 MemTxAttrs attrs)
1450{
1451 MemoryRegionIoeventfd ioeventfd = {
1452 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1453 .data = data,
1454 };
1455 unsigned i;
1456
1457 for (i = 0; i < mr->ioeventfd_nb; i++) {
1458 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1459 ioeventfd.e = mr->ioeventfds[i].e;
1460
1461 if (memory_region_ioeventfd_equal(ioeventfd, mr->ioeventfds[i])) {
1462 event_notifier_set(ioeventfd.e);
1463 return true;
1464 }
1465 }
1466
1467 return false;
1468}
1469
3b643495
PM
1470MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1471 hwaddr addr,
1472 uint64_t data,
1473 unsigned size,
1474 MemTxAttrs attrs)
a621f38d 1475{
897fa7cf 1476 if (!memory_region_access_valid(mr, addr, size, true)) {
b018ddf6 1477 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1478 return MEMTX_DECODE_ERROR;
093bc2cd
AK
1479 }
1480
a621f38d
AK
1481 adjust_endianness(mr, &data, size);
1482
8c56c1a5
PF
1483 if ((!kvm_eventfds_enabled()) &&
1484 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1485 return MEMTX_OK;
1486 }
1487
ce5d2f33 1488 if (mr->ops->write) {
cc05c43a
PM
1489 return access_with_adjusted_size(addr, &data, size,
1490 mr->ops->impl.min_access_size,
1491 mr->ops->impl.max_access_size,
1492 memory_region_write_accessor, mr,
1493 attrs);
1494 } else if (mr->ops->write_with_attrs) {
1495 return
1496 access_with_adjusted_size(addr, &data, size,
1497 mr->ops->impl.min_access_size,
1498 mr->ops->impl.max_access_size,
1499 memory_region_write_with_attrs_accessor,
1500 mr, attrs);
ce5d2f33 1501 } else {
cc05c43a
PM
1502 return access_with_adjusted_size(addr, &data, size, 1, 4,
1503 memory_region_oldmmio_write_accessor,
1504 mr, attrs);
74901c3b 1505 }
093bc2cd
AK
1506}
1507
093bc2cd 1508void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1509 Object *owner,
093bc2cd
AK
1510 const MemoryRegionOps *ops,
1511 void *opaque,
1512 const char *name,
1513 uint64_t size)
1514{
2c9b15ca 1515 memory_region_init(mr, owner, name, size);
6d6d2abf 1516 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1517 mr->opaque = opaque;
14a3c10a 1518 mr->terminates = true;
093bc2cd
AK
1519}
1520
1cfe48c1
PM
1521void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1522 Object *owner,
1523 const char *name,
1524 uint64_t size,
1525 Error **errp)
093bc2cd 1526{
2c9b15ca 1527 memory_region_init(mr, owner, name, size);
8ea9252a 1528 mr->ram = true;
14a3c10a 1529 mr->terminates = true;
545e92e0 1530 mr->destructor = memory_region_destructor_ram;
8e41fb63 1531 mr->ram_block = qemu_ram_alloc(size, mr, errp);
677e7805 1532 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
0b183fc8
PB
1533}
1534
60786ef3
MT
1535void memory_region_init_resizeable_ram(MemoryRegion *mr,
1536 Object *owner,
1537 const char *name,
1538 uint64_t size,
1539 uint64_t max_size,
1540 void (*resized)(const char*,
1541 uint64_t length,
1542 void *host),
1543 Error **errp)
1544{
1545 memory_region_init(mr, owner, name, size);
1546 mr->ram = true;
1547 mr->terminates = true;
1548 mr->destructor = memory_region_destructor_ram;
8e41fb63
FZ
1549 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1550 mr, errp);
677e7805 1551 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
60786ef3
MT
1552}
1553
0b183fc8
PB
1554#ifdef __linux__
1555void memory_region_init_ram_from_file(MemoryRegion *mr,
1556 struct Object *owner,
1557 const char *name,
1558 uint64_t size,
dbcb8981 1559 bool share,
7f56e740
PB
1560 const char *path,
1561 Error **errp)
0b183fc8
PB
1562{
1563 memory_region_init(mr, owner, name, size);
1564 mr->ram = true;
1565 mr->terminates = true;
1566 mr->destructor = memory_region_destructor_ram;
8e41fb63 1567 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
677e7805 1568 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
093bc2cd 1569}
fea617c5
MAL
1570
1571void memory_region_init_ram_from_fd(MemoryRegion *mr,
1572 struct Object *owner,
1573 const char *name,
1574 uint64_t size,
1575 bool share,
1576 int fd,
1577 Error **errp)
1578{
1579 memory_region_init(mr, owner, name, size);
1580 mr->ram = true;
1581 mr->terminates = true;
1582 mr->destructor = memory_region_destructor_ram;
1583 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1584 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1585}
0b183fc8 1586#endif
093bc2cd
AK
1587
1588void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1589 Object *owner,
093bc2cd
AK
1590 const char *name,
1591 uint64_t size,
1592 void *ptr)
1593{
2c9b15ca 1594 memory_region_init(mr, owner, name, size);
8ea9252a 1595 mr->ram = true;
14a3c10a 1596 mr->terminates = true;
fc3e7665 1597 mr->destructor = memory_region_destructor_ram;
677e7805 1598 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT
1599
1600 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1601 assert(ptr != NULL);
8e41fb63 1602 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK
1603}
1604
21e00fa5
AW
1605void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1606 Object *owner,
1607 const char *name,
1608 uint64_t size,
1609 void *ptr)
e4dc3f59 1610{
21e00fa5
AW
1611 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1612 mr->ram_device = true;
4a2e242b
AW
1613 mr->ops = &ram_device_mem_ops;
1614 mr->opaque = mr;
e4dc3f59
ND
1615}
1616
093bc2cd 1617void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1618 Object *owner,
093bc2cd
AK
1619 const char *name,
1620 MemoryRegion *orig,
a8170e5e 1621 hwaddr offset,
093bc2cd
AK
1622 uint64_t size)
1623{
2c9b15ca 1624 memory_region_init(mr, owner, name, size);
093bc2cd
AK
1625 mr->alias = orig;
1626 mr->alias_offset = offset;
1627}
1628
b59821a9
PM
1629void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1630 struct Object *owner,
1631 const char *name,
1632 uint64_t size,
1633 Error **errp)
a1777f7f
PM
1634{
1635 memory_region_init(mr, owner, name, size);
1636 mr->ram = true;
1637 mr->readonly = true;
1638 mr->terminates = true;
1639 mr->destructor = memory_region_destructor_ram;
1640 mr->ram_block = qemu_ram_alloc(size, mr, errp);
1641 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1642}
1643
b59821a9
PM
1644void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1645 Object *owner,
1646 const MemoryRegionOps *ops,
1647 void *opaque,
1648 const char *name,
1649 uint64_t size,
1650 Error **errp)
d0a9b5bc 1651{
39e0b03d 1652 assert(ops);
2c9b15ca 1653 memory_region_init(mr, owner, name, size);
7bc2b9cd 1654 mr->ops = ops;
75f5941c 1655 mr->opaque = opaque;
d0a9b5bc 1656 mr->terminates = true;
75c578dc 1657 mr->rom_device = true;
58268c8d 1658 mr->destructor = memory_region_destructor_ram;
8e41fb63 1659 mr->ram_block = qemu_ram_alloc(size, mr, errp);
d0a9b5bc
AK
1660}
1661
1221a474
AK
1662void memory_region_init_iommu(void *_iommu_mr,
1663 size_t instance_size,
1664 const char *mrtypename,
2c9b15ca 1665 Object *owner,
30951157
AK
1666 const char *name,
1667 uint64_t size)
1668{
1221a474 1669 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK
1670 struct MemoryRegion *mr;
1671
1221a474
AK
1672 object_initialize(_iommu_mr, instance_size, mrtypename);
1673 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK
1674 memory_region_do_init(mr, owner, name, size);
1675 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1676 mr->terminates = true; /* then re-forwards */
3df9d748
AK
1677 QLIST_INIT(&iommu_mr->iommu_notify);
1678 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK
1679}
1680
b4fefef9 1681static void memory_region_finalize(Object *obj)
093bc2cd 1682{
b4fefef9
PC
1683 MemoryRegion *mr = MEMORY_REGION(obj);
1684
2e2b8eb7
PB
1685 assert(!mr->container);
1686
1687 /* We know the region is not visible in any address space (it
1688 * does not have a container and cannot be a root either because
1689 * it has no references, so we can blindly clear mr->enabled.
1690 * memory_region_set_enabled instead could trigger a transaction
1691 * and cause an infinite loop.
1692 */
1693 mr->enabled = false;
1694 memory_region_transaction_begin();
1695 while (!QTAILQ_EMPTY(&mr->subregions)) {
1696 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1697 memory_region_del_subregion(mr, subregion);
1698 }
1699 memory_region_transaction_commit();
1700
545e92e0 1701 mr->destructor(mr);
093bc2cd 1702 memory_region_clear_coalescing(mr);
302fa283 1703 g_free((char *)mr->name);
7267c094 1704 g_free(mr->ioeventfds);
093bc2cd
AK
1705}
1706
803c0816
PB
1707Object *memory_region_owner(MemoryRegion *mr)
1708{
22a893e4
PB
1709 Object *obj = OBJECT(mr);
1710 return obj->parent;
803c0816
PB
1711}
1712
46637be2
PB
1713void memory_region_ref(MemoryRegion *mr)
1714{
22a893e4
PB
1715 /* MMIO callbacks most likely will access data that belongs
1716 * to the owner, hence the need to ref/unref the owner whenever
1717 * the memory region is in use.
1718 *
1719 * The memory region is a child of its owner. As long as the
1720 * owner doesn't call unparent itself on the memory region,
1721 * ref-ing the owner will also keep the memory region alive.
612263cf
PB
1722 * Memory regions without an owner are supposed to never go away;
1723 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1724 */
612263cf
PB
1725 if (mr && mr->owner) {
1726 object_ref(mr->owner);
46637be2
PB
1727 }
1728}
1729
1730void memory_region_unref(MemoryRegion *mr)
1731{
612263cf
PB
1732 if (mr && mr->owner) {
1733 object_unref(mr->owner);
46637be2
PB
1734 }
1735}
1736
093bc2cd
AK
1737uint64_t memory_region_size(MemoryRegion *mr)
1738{
08dafab4
AK
1739 if (int128_eq(mr->size, int128_2_64())) {
1740 return UINT64_MAX;
1741 }
1742 return int128_get64(mr->size);
093bc2cd
AK
1743}
1744
5d546d4b 1745const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1746{
d1dd32af
PC
1747 if (!mr->name) {
1748 ((MemoryRegion *)mr)->name =
1749 object_get_canonical_path_component(OBJECT(mr));
1750 }
302fa283 1751 return mr->name;
8991c79b
AK
1752}
1753
21e00fa5 1754bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1755{
21e00fa5 1756 return mr->ram_device;
e4dc3f59
ND
1757}
1758
2d1a35be 1759uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1760{
6f6a5ef3 1761 uint8_t mask = mr->dirty_log_mask;
adaad61c 1762 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB
1763 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1764 }
1765 return mask;
55043ba3
AK
1766}
1767
2d1a35be
PB
1768bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1769{
1770 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1771}
1772
3df9d748 1773static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
5bf3d319
PX
1774{
1775 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1776 IOMMUNotifier *iommu_notifier;
1221a474 1777 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
5bf3d319 1778
3df9d748 1779 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX
1780 flags |= iommu_notifier->notifier_flags;
1781 }
1782
1221a474
AK
1783 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1784 imrc->notify_flag_changed(iommu_mr,
1785 iommu_mr->iommu_notify_flags,
1786 flags);
5bf3d319
PX
1787 }
1788
3df9d748 1789 iommu_mr->iommu_notify_flags = flags;
5bf3d319
PX
1790}
1791
cdb30812
PX
1792void memory_region_register_iommu_notifier(MemoryRegion *mr,
1793 IOMMUNotifier *n)
06866575 1794{
3df9d748
AK
1795 IOMMUMemoryRegion *iommu_mr;
1796
efcd38c5
JW
1797 if (mr->alias) {
1798 memory_region_register_iommu_notifier(mr->alias, n);
1799 return;
1800 }
1801
cdb30812 1802 /* We need to register for at least one bitfield */
3df9d748 1803 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1804 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1805 assert(n->start <= n->end);
3df9d748
AK
1806 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1807 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1808}
1809
3df9d748 1810uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1811{
1221a474
AK
1812 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1813
1814 if (imrc->get_min_page_size) {
1815 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK
1816 }
1817 return TARGET_PAGE_SIZE;
1818}
1819
3df9d748 1820void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1821{
3df9d748 1822 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1823 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1824 hwaddr addr, granularity;
a788f227
DG
1825 IOMMUTLBEntry iotlb;
1826
faa362e3 1827 /* If the IOMMU has its own replay callback, override */
1221a474
AK
1828 if (imrc->replay) {
1829 imrc->replay(iommu_mr, n);
faa362e3
PX
1830 return;
1831 }
1832
3df9d748 1833 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1834
a788f227 1835 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1221a474 1836 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE);
a788f227
DG
1837 if (iotlb.perm != IOMMU_NONE) {
1838 n->notify(n, &iotlb);
1839 }
1840
1841 /* if (2^64 - MR size) < granularity, it's possible to get an
1842 * infinite loop here. This should catch such a wraparound */
1843 if ((addr + granularity) < addr) {
1844 break;
1845 }
1846 }
1847}
1848
3df9d748 1849void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
de472e4a
PX
1850{
1851 IOMMUNotifier *notifier;
1852
3df9d748
AK
1853 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1854 memory_region_iommu_replay(iommu_mr, notifier);
de472e4a
PX
1855 }
1856}
1857
cdb30812
PX
1858void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1859 IOMMUNotifier *n)
06866575 1860{
3df9d748
AK
1861 IOMMUMemoryRegion *iommu_mr;
1862
efcd38c5
JW
1863 if (mr->alias) {
1864 memory_region_unregister_iommu_notifier(mr->alias, n);
1865 return;
1866 }
cdb30812 1867 QLIST_REMOVE(n, node);
3df9d748
AK
1868 iommu_mr = IOMMU_MEMORY_REGION(mr);
1869 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1870}
1871
bd2bfa4c
PX
1872void memory_region_notify_one(IOMMUNotifier *notifier,
1873 IOMMUTLBEntry *entry)
06866575 1874{
cdb30812
PX
1875 IOMMUNotifierFlag request_flags;
1876
bd2bfa4c
PX
1877 /*
1878 * Skip the notification if the notification does not overlap
1879 * with registered range.
1880 */
1881 if (notifier->start > entry->iova + entry->addr_mask + 1 ||
1882 notifier->end < entry->iova) {
1883 return;
1884 }
cdb30812 1885
bd2bfa4c 1886 if (entry->perm & IOMMU_RW) {
cdb30812
PX
1887 request_flags = IOMMU_NOTIFIER_MAP;
1888 } else {
1889 request_flags = IOMMU_NOTIFIER_UNMAP;
1890 }
1891
bd2bfa4c
PX
1892 if (notifier->notifier_flags & request_flags) {
1893 notifier->notify(notifier, entry);
1894 }
1895}
1896
3df9d748 1897void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
bd2bfa4c
PX
1898 IOMMUTLBEntry entry)
1899{
1900 IOMMUNotifier *iommu_notifier;
1901
3df9d748 1902 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1903
3df9d748 1904 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
bd2bfa4c 1905 memory_region_notify_one(iommu_notifier, &entry);
cdb30812 1906 }
06866575
DG
1907}
1908
093bc2cd
AK
1909void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1910{
5a583347 1911 uint8_t mask = 1 << client;
deb809ed 1912 uint8_t old_logging;
5a583347 1913
dbddac6d 1914 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB
1915 old_logging = mr->vga_logging_count;
1916 mr->vga_logging_count += log ? 1 : -1;
1917 if (!!old_logging == !!mr->vga_logging_count) {
1918 return;
1919 }
1920
59023ef4 1921 memory_region_transaction_begin();
5a583347 1922 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1923 memory_region_update_pending |= mr->enabled;
59023ef4 1924 memory_region_transaction_commit();
093bc2cd
AK
1925}
1926
a8170e5e
AK
1927bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1928 hwaddr size, unsigned client)
093bc2cd 1929{
8e41fb63
FZ
1930 assert(mr->ram_block);
1931 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1932 size, client);
093bc2cd
AK
1933}
1934
a8170e5e
AK
1935void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1936 hwaddr size)
093bc2cd 1937{
8e41fb63
FZ
1938 assert(mr->ram_block);
1939 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1940 size,
58d2707e 1941 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK
1942}
1943
6c279db8
JQ
1944bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1945 hwaddr size, unsigned client)
1946{
8e41fb63
FZ
1947 assert(mr->ram_block);
1948 return cpu_physical_memory_test_and_clear_dirty(
1949 memory_region_get_ram_addr(mr) + addr, size, client);
6c279db8
JQ
1950}
1951
8deaf12c
GH
1952DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
1953 hwaddr addr,
1954 hwaddr size,
1955 unsigned client)
1956{
1957 assert(mr->ram_block);
1958 return cpu_physical_memory_snapshot_and_clear_dirty(
1959 memory_region_get_ram_addr(mr) + addr, size, client);
1960}
1961
1962bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
1963 hwaddr addr, hwaddr size)
1964{
1965 assert(mr->ram_block);
1966 return cpu_physical_memory_snapshot_get_dirty(snap,
1967 memory_region_get_ram_addr(mr) + addr, size);
1968}
6c279db8 1969
093bc2cd
AK
1970void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1971{
0a752eee 1972 MemoryListener *listener;
0d673e36 1973 AddressSpace *as;
0a752eee 1974 FlatView *view;
5a583347
AK
1975 FlatRange *fr;
1976
0a752eee
PB
1977 /* If the same address space has multiple log_sync listeners, we
1978 * visit that address space's FlatView multiple times. But because
1979 * log_sync listeners are rare, it's still cheaper than walking each
1980 * address space once.
1981 */
1982 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1983 if (!listener->log_sync) {
1984 continue;
1985 }
1986 as = listener->address_space;
1987 view = address_space_get_flatview(as);
99e86347 1988 FOR_EACH_FLAT_RANGE(fr, view) {
0d673e36 1989 if (fr->mr == mr) {
16620684 1990 MemoryRegionSection mrs = section_from_flat_range(fr, view);
0a752eee 1991 listener->log_sync(listener, &mrs);
0d673e36 1992 }
5a583347 1993 }
856d7245 1994 flatview_unref(view);
5a583347 1995 }
093bc2cd
AK
1996}
1997
1998void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1999{
fb1cd6f9 2000 if (mr->readonly != readonly) {
59023ef4 2001 memory_region_transaction_begin();
fb1cd6f9 2002 mr->readonly = readonly;
22bde714 2003 memory_region_update_pending |= mr->enabled;
59023ef4 2004 memory_region_transaction_commit();
fb1cd6f9 2005 }
093bc2cd
AK
2006}
2007
5f9a5ea1 2008void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 2009{
5f9a5ea1 2010 if (mr->romd_mode != romd_mode) {
59023ef4 2011 memory_region_transaction_begin();
5f9a5ea1 2012 mr->romd_mode = romd_mode;
22bde714 2013 memory_region_update_pending |= mr->enabled;
59023ef4 2014 memory_region_transaction_commit();
d0a9b5bc
AK
2015 }
2016}
2017
a8170e5e
AK
2018void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2019 hwaddr size, unsigned client)
093bc2cd 2020{
8e41fb63
FZ
2021 assert(mr->ram_block);
2022 cpu_physical_memory_test_and_clear_dirty(
2023 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK
2024}
2025
a35ba7be
PB
2026int memory_region_get_fd(MemoryRegion *mr)
2027{
4ff87573
PB
2028 int fd;
2029
2030 rcu_read_lock();
2031 while (mr->alias) {
2032 mr = mr->alias;
a35ba7be 2033 }
4ff87573
PB
2034 fd = mr->ram_block->fd;
2035 rcu_read_unlock();
a35ba7be 2036
4ff87573
PB
2037 return fd;
2038}
a35ba7be 2039
093bc2cd
AK
2040void *memory_region_get_ram_ptr(MemoryRegion *mr)
2041{
49b24afc
PB
2042 void *ptr;
2043 uint64_t offset = 0;
093bc2cd 2044
49b24afc
PB
2045 rcu_read_lock();
2046 while (mr->alias) {
2047 offset += mr->alias_offset;
2048 mr = mr->alias;
2049 }
8e41fb63 2050 assert(mr->ram_block);
0878d0e1 2051 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
49b24afc 2052 rcu_read_unlock();
093bc2cd 2053
0878d0e1 2054 return ptr;
093bc2cd
AK
2055}
2056
07bdaa41
PB
2057MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2058{
2059 RAMBlock *block;
2060
2061 block = qemu_ram_block_from_host(ptr, false, offset);
2062 if (!block) {
2063 return NULL;
2064 }
2065
2066 return block->mr;
2067}
2068
7ebb2745
FZ
2069ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2070{
2071 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2072}
2073
37d7c084
PB
2074void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2075{
8e41fb63 2076 assert(mr->ram_block);
37d7c084 2077
fa53a0e5 2078 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB
2079}
2080
0d673e36 2081static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 2082{
99e86347 2083 FlatView *view;
093bc2cd
AK
2084 FlatRange *fr;
2085 CoalescedMemoryRange *cmr;
2086 AddrRange tmp;
95d2994a 2087 MemoryRegionSection section;
093bc2cd 2088
856d7245 2089 view = address_space_get_flatview(as);
99e86347 2090 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 2091 if (fr->mr == mr) {
95d2994a 2092 section = (MemoryRegionSection) {
16620684 2093 .fv = view,
95d2994a 2094 .offset_within_address_space = int128_get64(fr->addr.start),
052e87b0 2095 .size = fr->addr.size,
95d2994a
AK
2096 };
2097
9a54635d 2098 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
95d2994a
AK
2099 int128_get64(fr->addr.start),
2100 int128_get64(fr->addr.size));
093bc2cd
AK
2101 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
2102 tmp = addrrange_shift(cmr->addr,
08dafab4
AK
2103 int128_sub(fr->addr.start,
2104 int128_make64(fr->offset_in_region)));
093bc2cd
AK
2105 if (!addrrange_intersects(tmp, fr->addr)) {
2106 continue;
2107 }
2108 tmp = addrrange_intersection(tmp, fr->addr);
9a54635d 2109 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
95d2994a
AK
2110 int128_get64(tmp.start),
2111 int128_get64(tmp.size));
093bc2cd
AK
2112 }
2113 }
2114 }
856d7245 2115 flatview_unref(view);
093bc2cd
AK
2116}
2117
0d673e36
AK
2118static void memory_region_update_coalesced_range(MemoryRegion *mr)
2119{
2120 AddressSpace *as;
2121
2122 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2123 memory_region_update_coalesced_range_as(mr, as);
2124 }
2125}
2126
093bc2cd
AK
2127void memory_region_set_coalescing(MemoryRegion *mr)
2128{
2129 memory_region_clear_coalescing(mr);
08dafab4 2130 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK
2131}
2132
2133void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 2134 hwaddr offset,
093bc2cd
AK
2135 uint64_t size)
2136{
7267c094 2137 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2138
08dafab4 2139 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK
2140 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2141 memory_region_update_coalesced_range(mr);
d410515e 2142 memory_region_set_flush_coalesced(mr);
093bc2cd
AK
2143}
2144
2145void memory_region_clear_coalescing(MemoryRegion *mr)
2146{
2147 CoalescedMemoryRange *cmr;
ab5b3db5 2148 bool updated = false;
093bc2cd 2149
d410515e
JK
2150 qemu_flush_coalesced_mmio_buffer();
2151 mr->flush_coalesced_mmio = false;
2152
093bc2cd
AK
2153 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2154 cmr = QTAILQ_FIRST(&mr->coalesced);
2155 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 2156 g_free(cmr);
ab5b3db5
FZ
2157 updated = true;
2158 }
2159
2160 if (updated) {
2161 memory_region_update_coalesced_range(mr);
093bc2cd 2162 }
093bc2cd
AK
2163}
2164
d410515e
JK
2165void memory_region_set_flush_coalesced(MemoryRegion *mr)
2166{
2167 mr->flush_coalesced_mmio = true;
2168}
2169
2170void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2171{
2172 qemu_flush_coalesced_mmio_buffer();
2173 if (QTAILQ_EMPTY(&mr->coalesced)) {
2174 mr->flush_coalesced_mmio = false;
2175 }
2176}
2177
196ea131
JK
2178void memory_region_set_global_locking(MemoryRegion *mr)
2179{
2180 mr->global_locking = true;
2181}
2182
2183void memory_region_clear_global_locking(MemoryRegion *mr)
2184{
2185 mr->global_locking = false;
2186}
2187
8c56c1a5
PF
2188static bool userspace_eventfd_warning;
2189
3e9d69e7 2190void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2191 hwaddr addr,
3e9d69e7
AK
2192 unsigned size,
2193 bool match_data,
2194 uint64_t data,
753d5e14 2195 EventNotifier *e)
3e9d69e7
AK
2196{
2197 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2198 .addr.start = int128_make64(addr),
2199 .addr.size = int128_make64(size),
3e9d69e7
AK
2200 .match_data = match_data,
2201 .data = data,
753d5e14 2202 .e = e,
3e9d69e7
AK
2203 };
2204 unsigned i;
2205
8c56c1a5
PF
2206 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2207 userspace_eventfd_warning))) {
2208 userspace_eventfd_warning = true;
2209 error_report("Using eventfd without MMIO binding in KVM. "
2210 "Suboptimal performance expected");
2211 }
2212
b8aecea2
JW
2213 if (size) {
2214 adjust_endianness(mr, &mrfd.data, size);
2215 }
59023ef4 2216 memory_region_transaction_begin();
3e9d69e7
AK
2217 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2218 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
2219 break;
2220 }
2221 }
2222 ++mr->ioeventfd_nb;
7267c094 2223 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK
2224 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2225 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2226 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2227 mr->ioeventfds[i] = mrfd;
4dc56152 2228 ioeventfd_update_pending |= mr->enabled;
59023ef4 2229 memory_region_transaction_commit();
3e9d69e7
AK
2230}
2231
2232void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2233 hwaddr addr,
3e9d69e7
AK
2234 unsigned size,
2235 bool match_data,
2236 uint64_t data,
753d5e14 2237 EventNotifier *e)
3e9d69e7
AK
2238{
2239 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2240 .addr.start = int128_make64(addr),
2241 .addr.size = int128_make64(size),
3e9d69e7
AK
2242 .match_data = match_data,
2243 .data = data,
753d5e14 2244 .e = e,
3e9d69e7
AK
2245 };
2246 unsigned i;
2247
b8aecea2
JW
2248 if (size) {
2249 adjust_endianness(mr, &mrfd.data, size);
2250 }
59023ef4 2251 memory_region_transaction_begin();
3e9d69e7
AK
2252 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2253 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
2254 break;
2255 }
2256 }
2257 assert(i != mr->ioeventfd_nb);
2258 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2259 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2260 --mr->ioeventfd_nb;
7267c094 2261 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2262 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2263 ioeventfd_update_pending |= mr->enabled;
59023ef4 2264 memory_region_transaction_commit();
3e9d69e7
AK
2265}
2266
feca4ac1 2267static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2268{
feca4ac1 2269 MemoryRegion *mr = subregion->container;
093bc2cd
AK
2270 MemoryRegion *other;
2271
59023ef4
JK
2272 memory_region_transaction_begin();
2273
dfde4e6e 2274 memory_region_ref(subregion);
093bc2cd
AK
2275 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2276 if (subregion->priority >= other->priority) {
2277 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2278 goto done;
2279 }
2280 }
2281 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2282done:
22bde714 2283 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2284 memory_region_transaction_commit();
093bc2cd
AK
2285}
2286
0598701a
PC
2287static void memory_region_add_subregion_common(MemoryRegion *mr,
2288 hwaddr offset,
2289 MemoryRegion *subregion)
2290{
feca4ac1
PB
2291 assert(!subregion->container);
2292 subregion->container = mr;
0598701a 2293 subregion->addr = offset;
feca4ac1 2294 memory_region_update_container_subregions(subregion);
0598701a 2295}
093bc2cd
AK
2296
2297void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2298 hwaddr offset,
093bc2cd
AK
2299 MemoryRegion *subregion)
2300{
093bc2cd
AK
2301 subregion->priority = 0;
2302 memory_region_add_subregion_common(mr, offset, subregion);
2303}
2304
2305void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2306 hwaddr offset,
093bc2cd 2307 MemoryRegion *subregion,
a1ff8ae0 2308 int priority)
093bc2cd 2309{
093bc2cd
AK
2310 subregion->priority = priority;
2311 memory_region_add_subregion_common(mr, offset, subregion);
2312}
2313
2314void memory_region_del_subregion(MemoryRegion *mr,
2315 MemoryRegion *subregion)
2316{
59023ef4 2317 memory_region_transaction_begin();
feca4ac1
PB
2318 assert(subregion->container == mr);
2319 subregion->container = NULL;
093bc2cd 2320 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2321 memory_region_unref(subregion);
22bde714 2322 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2323 memory_region_transaction_commit();
6bba19ba
AK
2324}
2325
2326void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2327{
2328 if (enabled == mr->enabled) {
2329 return;
2330 }
59023ef4 2331 memory_region_transaction_begin();
6bba19ba 2332 mr->enabled = enabled;
22bde714 2333 memory_region_update_pending = true;
59023ef4 2334 memory_region_transaction_commit();
093bc2cd 2335}
1c0ffa58 2336
e7af4c67
MT
2337void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2338{
2339 Int128 s = int128_make64(size);
2340
2341 if (size == UINT64_MAX) {
2342 s = int128_2_64();
2343 }
2344 if (int128_eq(s, mr->size)) {
2345 return;
2346 }
2347 memory_region_transaction_begin();
2348 mr->size = s;
2349 memory_region_update_pending = true;
2350 memory_region_transaction_commit();
2351}
2352
67891b8a 2353static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2354{
feca4ac1 2355 MemoryRegion *container = mr->container;
2282e1af 2356
feca4ac1 2357 if (container) {
67891b8a
PC
2358 memory_region_transaction_begin();
2359 memory_region_ref(mr);
feca4ac1
PB
2360 memory_region_del_subregion(container, mr);
2361 mr->container = container;
2362 memory_region_update_container_subregions(mr);
67891b8a
PC
2363 memory_region_unref(mr);
2364 memory_region_transaction_commit();
2282e1af 2365 }
67891b8a 2366}
2282e1af 2367
67891b8a
PC
2368void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2369{
2370 if (addr != mr->addr) {
2371 mr->addr = addr;
2372 memory_region_readd_subregion(mr);
2373 }
2282e1af
AK
2374}
2375
a8170e5e 2376void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2377{
4703359e 2378 assert(mr->alias);
4703359e 2379
59023ef4 2380 if (offset == mr->alias_offset) {
4703359e
AK
2381 return;
2382 }
2383
59023ef4
JK
2384 memory_region_transaction_begin();
2385 mr->alias_offset = offset;
22bde714 2386 memory_region_update_pending |= mr->enabled;
59023ef4 2387 memory_region_transaction_commit();
4703359e
AK
2388}
2389
a2b257d6
IM
2390uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2391{
2392 return mr->align;
2393}
2394
e2177955
AK
2395static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2396{
2397 const AddrRange *addr = addr_;
2398 const FlatRange *fr = fr_;
2399
2400 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2401 return -1;
2402 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2403 return 1;
2404 }
2405 return 0;
2406}
2407
99e86347 2408static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2409{
99e86347 2410 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK
2411 sizeof(FlatRange), cmp_flatrange_addr);
2412}
2413
eed2bacf
IM
2414bool memory_region_is_mapped(MemoryRegion *mr)
2415{
2416 return mr->container ? true : false;
2417}
2418
c6742b14
PB
2419/* Same as memory_region_find, but it does not add a reference to the
2420 * returned region. It must be called from an RCU critical section.
2421 */
2422static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2423 hwaddr addr, uint64_t size)
e2177955 2424{
052e87b0 2425 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB
2426 MemoryRegion *root;
2427 AddressSpace *as;
2428 AddrRange range;
99e86347 2429 FlatView *view;
73034e9e
PB
2430 FlatRange *fr;
2431
2432 addr += mr->addr;
feca4ac1
PB
2433 for (root = mr; root->container; ) {
2434 root = root->container;
73034e9e
PB
2435 addr += root->addr;
2436 }
e2177955 2437
73034e9e 2438 as = memory_region_to_address_space(root);
eed2bacf
IM
2439 if (!as) {
2440 return ret;
2441 }
73034e9e 2442 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2443
16620684 2444 view = address_space_to_flatview(as);
99e86347 2445 fr = flatview_lookup(view, range);
e2177955 2446 if (!fr) {
c6742b14 2447 return ret;
e2177955
AK
2448 }
2449
99e86347 2450 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK
2451 --fr;
2452 }
2453
2454 ret.mr = fr->mr;
16620684 2455 ret.fv = view;
e2177955
AK
2456 range = addrrange_intersection(range, fr->addr);
2457 ret.offset_within_region = fr->offset_in_region;
2458 ret.offset_within_region += int128_get64(int128_sub(range.start,
2459 fr->addr.start));
052e87b0 2460 ret.size = range.size;
e2177955 2461 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2462 ret.readonly = fr->readonly;
c6742b14
PB
2463 return ret;
2464}
2465
2466MemoryRegionSection memory_region_find(MemoryRegion *mr,
2467 hwaddr addr, uint64_t size)
2468{
2469 MemoryRegionSection ret;
2470 rcu_read_lock();
2471 ret = memory_region_find_rcu(mr, addr, size);
2472 if (ret.mr) {
2473 memory_region_ref(ret.mr);
2474 }
2b647668 2475 rcu_read_unlock();
e2177955
AK
2476 return ret;
2477}
2478
c6742b14
PB
2479bool memory_region_present(MemoryRegion *container, hwaddr addr)
2480{
2481 MemoryRegion *mr;
2482
2483 rcu_read_lock();
2484 mr = memory_region_find_rcu(container, addr, 1).mr;
2485 rcu_read_unlock();
2486 return mr && mr != container;
2487}
2488
9c1f8f44 2489void memory_global_dirty_log_sync(void)
86e775c6 2490{
9c1f8f44
PB
2491 MemoryListener *listener;
2492 AddressSpace *as;
99e86347 2493 FlatView *view;
7664e80c
AK
2494 FlatRange *fr;
2495
9c1f8f44
PB
2496 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2497 if (!listener->log_sync) {
2498 continue;
2499 }
d45fa784 2500 as = listener->address_space;
9c1f8f44
PB
2501 view = address_space_get_flatview(as);
2502 FOR_EACH_FLAT_RANGE(fr, view) {
adaad61c 2503 if (fr->dirty_log_mask) {
16620684
AK
2504 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2505
adaad61c
PB
2506 listener->log_sync(listener, &mrs);
2507 }
9c1f8f44
PB
2508 }
2509 flatview_unref(view);
7664e80c
AK
2510 }
2511}
2512
19310760
JZ
2513static VMChangeStateEntry *vmstate_change;
2514
7664e80c
AK
2515void memory_global_dirty_log_start(void)
2516{
19310760
JZ
2517 if (vmstate_change) {
2518 qemu_del_vm_change_state_handler(vmstate_change);
2519 vmstate_change = NULL;
2520 }
2521
7664e80c 2522 global_dirty_log = true;
6f6a5ef3 2523
7376e582 2524 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3
PB
2525
2526 /* Refresh DIRTY_LOG_MIGRATION bit. */
2527 memory_region_transaction_begin();
2528 memory_region_update_pending = true;
2529 memory_region_transaction_commit();
7664e80c
AK
2530}
2531
19310760 2532static void memory_global_dirty_log_do_stop(void)
7664e80c 2533{
7664e80c 2534 global_dirty_log = false;
6f6a5ef3
PB
2535
2536 /* Refresh DIRTY_LOG_MIGRATION bit. */
2537 memory_region_transaction_begin();
2538 memory_region_update_pending = true;
2539 memory_region_transaction_commit();
2540
7376e582 2541 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK
2542}
2543
19310760
JZ
2544static void memory_vm_change_state_handler(void *opaque, int running,
2545 RunState state)
2546{
2547 if (running) {
2548 memory_global_dirty_log_do_stop();
2549
2550 if (vmstate_change) {
2551 qemu_del_vm_change_state_handler(vmstate_change);
2552 vmstate_change = NULL;
2553 }
2554 }
2555}
2556
2557void memory_global_dirty_log_stop(void)
2558{
2559 if (!runstate_is_running()) {
2560 if (vmstate_change) {
2561 return;
2562 }
2563 vmstate_change = qemu_add_vm_change_state_handler(
2564 memory_vm_change_state_handler, NULL);
2565 return;
2566 }
2567
2568 memory_global_dirty_log_do_stop();
2569}
2570
7664e80c
AK
2571static void listener_add_address_space(MemoryListener *listener,
2572 AddressSpace *as)
2573{
99e86347 2574 FlatView *view;
7664e80c
AK
2575 FlatRange *fr;
2576
680a4783
PB
2577 if (listener->begin) {
2578 listener->begin(listener);
2579 }
7664e80c 2580 if (global_dirty_log) {
975aefe0
AK
2581 if (listener->log_global_start) {
2582 listener->log_global_start(listener);
2583 }
7664e80c 2584 }
975aefe0 2585
856d7245 2586 view = address_space_get_flatview(as);
99e86347 2587 FOR_EACH_FLAT_RANGE(fr, view) {
7664e80c
AK
2588 MemoryRegionSection section = {
2589 .mr = fr->mr,
16620684 2590 .fv = view,
7664e80c 2591 .offset_within_region = fr->offset_in_region,
052e87b0 2592 .size = fr->addr.size,
7664e80c 2593 .offset_within_address_space = int128_get64(fr->addr.start),
7a8499e8 2594 .readonly = fr->readonly,
7664e80c 2595 };
680a4783
PB
2596 if (fr->dirty_log_mask && listener->log_start) {
2597 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2598 }
975aefe0
AK
2599 if (listener->region_add) {
2600 listener->region_add(listener, &section);
2601 }
7664e80c 2602 }
680a4783
PB
2603 if (listener->commit) {
2604 listener->commit(listener);
2605 }
856d7245 2606 flatview_unref(view);
7664e80c
AK
2607}
2608
d45fa784 2609void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2610{
72e22d2f
AK
2611 MemoryListener *other = NULL;
2612
d45fa784 2613 listener->address_space = as;
72e22d2f
AK
2614 if (QTAILQ_EMPTY(&memory_listeners)
2615 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2616 memory_listeners)->priority) {
2617 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2618 } else {
2619 QTAILQ_FOREACH(other, &memory_listeners, link) {
2620 if (listener->priority < other->priority) {
2621 break;
2622 }
2623 }
2624 QTAILQ_INSERT_BEFORE(other, listener, link);
2625 }
0d673e36 2626
9a54635d
PB
2627 if (QTAILQ_EMPTY(&as->listeners)
2628 || listener->priority >= QTAILQ_LAST(&as->listeners,
2629 memory_listeners)->priority) {
2630 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2631 } else {
2632 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2633 if (listener->priority < other->priority) {
2634 break;
2635 }
2636 }
2637 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2638 }
2639
d45fa784 2640 listener_add_address_space(listener, as);
7664e80c
AK
2641}
2642
2643void memory_listener_unregister(MemoryListener *listener)
2644{
1d8280c1
PB
2645 if (!listener->address_space) {
2646 return;
2647 }
2648
72e22d2f 2649 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2650 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2651 listener->address_space = NULL;
86e775c6 2652}
e2177955 2653
c9356746
FK
2654bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2655{
2656 void *host;
2657 unsigned size = 0;
2658 unsigned offset = 0;
2659 Object *new_interface;
2660
2661 if (!mr || !mr->ops->request_ptr) {
2662 return false;
2663 }
2664
2665 /*
2666 * Avoid an update if the request_ptr call
2667 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2668 * a cache.
2669 */
2670 memory_region_transaction_begin();
2671
2672 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2673
2674 if (!host || !size) {
2675 memory_region_transaction_commit();
2676 return false;
2677 }
2678
2679 new_interface = object_new("mmio_interface");
2680 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2681 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2682 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2683 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2684 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2685 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2686
2687 memory_region_transaction_commit();
2688 return true;
2689}
2690
2691typedef struct MMIOPtrInvalidate {
2692 MemoryRegion *mr;
2693 hwaddr offset;
2694 unsigned size;
2695 int busy;
2696 int allocated;
2697} MMIOPtrInvalidate;
2698
2699#define MAX_MMIO_INVALIDATE 10
2700static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2701
2702static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2703 run_on_cpu_data data)
2704{
2705 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2706 MemoryRegion *mr = invalidate_data->mr;
2707 hwaddr offset = invalidate_data->offset;
2708 unsigned size = invalidate_data->size;
2709 MemoryRegionSection section = memory_region_find(mr, offset, size);
2710
2711 qemu_mutex_lock_iothread();
2712
2713 /* Reset dirty so this doesn't happen later. */
2714 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2715
2716 if (section.mr != mr) {
2717 /* memory_region_find add a ref on section.mr */
2718 memory_region_unref(section.mr);
2719 if (MMIO_INTERFACE(section.mr->owner)) {
2720 /* We found the interface just drop it. */
2721 object_property_set_bool(section.mr->owner, false, "realized",
2722 NULL);
2723 object_unref(section.mr->owner);
2724 object_unparent(section.mr->owner);
2725 }
2726 }
2727
2728 qemu_mutex_unlock_iothread();
2729
2730 if (invalidate_data->allocated) {
2731 g_free(invalidate_data);
2732 } else {
2733 invalidate_data->busy = 0;
2734 }
2735}
2736
2737void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2738 unsigned size)
2739{
2740 size_t i;
2741 MMIOPtrInvalidate *invalidate_data = NULL;
2742
2743 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2744 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2745 invalidate_data = &mmio_ptr_invalidate_list[i];
2746 break;
2747 }
2748 }
2749
2750 if (!invalidate_data) {
2751 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2752 invalidate_data->allocated = 1;
2753 }
2754
2755 invalidate_data->mr = mr;
2756 invalidate_data->offset = offset;
2757 invalidate_data->size = size;
2758
2759 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2760 RUN_ON_CPU_HOST_PTR(invalidate_data));
2761}
2762
7dca8043 2763void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2764{
ac95190e 2765 memory_region_ref(root);
8786db7c 2766 as->root = root;
67ace39b 2767 as->current_map = NULL;
4c19eb72
AK
2768 as->ioeventfd_nb = 0;
2769 as->ioeventfds = NULL;
9a54635d 2770 QTAILQ_INIT(&as->listeners);
0d673e36 2771 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2772 as->name = g_strdup(name ? name : "anonymous");
202fc01b
AK
2773 address_space_update_topology(as);
2774 address_space_update_ioeventfds(as);
1c0ffa58 2775}
658b2224 2776
374f2981 2777static void do_address_space_destroy(AddressSpace *as)
83f3c251 2778{
9a54635d 2779 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2780
856d7245 2781 flatview_unref(as->current_map);
7dca8043 2782 g_free(as->name);
4c19eb72 2783 g_free(as->ioeventfds);
ac95190e 2784 memory_region_unref(as->root);
83f3c251
AK
2785}
2786
374f2981
PB
2787void address_space_destroy(AddressSpace *as)
2788{
ac95190e
PB
2789 MemoryRegion *root = as->root;
2790
374f2981
PB
2791 /* Flush out anything from MemoryListeners listening in on this */
2792 memory_region_transaction_begin();
2793 as->root = NULL;
2794 memory_region_transaction_commit();
2795 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2796
2797 /* At this point, as->dispatch and as->current_map are dummy
2798 * entries that the guest should never use. Wait for the old
2799 * values to expire before freeing the data.
2800 */
ac95190e 2801 as->root = root;
374f2981
PB
2802 call_rcu(as, do_address_space_destroy, rcu);
2803}
2804
4e831901
PX
2805static const char *memory_region_type(MemoryRegion *mr)
2806{
2807 if (memory_region_is_ram_device(mr)) {
2808 return "ramd";
2809 } else if (memory_region_is_romd(mr)) {
2810 return "romd";
2811 } else if (memory_region_is_rom(mr)) {
2812 return "rom";
2813 } else if (memory_region_is_ram(mr)) {
2814 return "ram";
2815 } else {
2816 return "i/o";
2817 }
2818}
2819
314e2987
BS
2820typedef struct MemoryRegionList MemoryRegionList;
2821
2822struct MemoryRegionList {
2823 const MemoryRegion *mr;
a16878d2 2824 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS
2825};
2826
a16878d2 2827typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
314e2987 2828
4e831901
PX
2829#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2830 int128_sub((size), int128_one())) : 0)
2831#define MTREE_INDENT " "
2832
314e2987
BS
2833static void mtree_print_mr(fprintf_function mon_printf, void *f,
2834 const MemoryRegion *mr, unsigned int level,
a8170e5e 2835 hwaddr base,
9479c57a 2836 MemoryRegionListHead *alias_print_queue)
314e2987 2837{
9479c57a
JK
2838 MemoryRegionList *new_ml, *ml, *next_ml;
2839 MemoryRegionListHead submr_print_queue;
314e2987
BS
2840 const MemoryRegion *submr;
2841 unsigned int i;
b31f8412 2842 hwaddr cur_start, cur_end;
314e2987 2843
f8a9f720 2844 if (!mr) {
314e2987
BS
2845 return;
2846 }
2847
2848 for (i = 0; i < level; i++) {
4e831901 2849 mon_printf(f, MTREE_INDENT);
314e2987
BS
2850 }
2851
b31f8412
PX
2852 cur_start = base + mr->addr;
2853 cur_end = cur_start + MR_SIZE(mr->size);
2854
2855 /*
2856 * Try to detect overflow of memory region. This should never
2857 * happen normally. When it happens, we dump something to warn the
2858 * user who is observing this.
2859 */
2860 if (cur_start < base || cur_end < cur_start) {
2861 mon_printf(f, "[DETECTED OVERFLOW!] ");
2862 }
2863
314e2987
BS
2864 if (mr->alias) {
2865 MemoryRegionList *ml;
2866 bool found = false;
2867
2868 /* check if the alias is already in the queue */
a16878d2 2869 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2870 if (ml->mr == mr->alias) {
314e2987
BS
2871 found = true;
2872 }
2873 }
2874
2875 if (!found) {
2876 ml = g_new(MemoryRegionList, 1);
2877 ml->mr = mr->alias;
a16878d2 2878 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2879 }
4896d74b 2880 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
4e831901 2881 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
f8a9f720 2882 "-" TARGET_FMT_plx "%s\n",
b31f8412 2883 cur_start, cur_end,
4b474ba7 2884 mr->priority,
4e831901 2885 memory_region_type((MemoryRegion *)mr),
3fb18b4d
PC
2886 memory_region_name(mr),
2887 memory_region_name(mr->alias),
314e2987 2888 mr->alias_offset,
4e831901 2889 mr->alias_offset + MR_SIZE(mr->size),
f8a9f720 2890 mr->enabled ? "" : " [disabled]");
314e2987 2891 } else {
4896d74b 2892 mon_printf(f,
4e831901 2893 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
b31f8412 2894 cur_start, cur_end,
4b474ba7 2895 mr->priority,
4e831901 2896 memory_region_type((MemoryRegion *)mr),
f8a9f720
GH
2897 memory_region_name(mr),
2898 mr->enabled ? "" : " [disabled]");
314e2987 2899 }
9479c57a
JK
2900
2901 QTAILQ_INIT(&submr_print_queue);
2902
314e2987 2903 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
2904 new_ml = g_new(MemoryRegionList, 1);
2905 new_ml->mr = submr;
a16878d2 2906 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK
2907 if (new_ml->mr->addr < ml->mr->addr ||
2908 (new_ml->mr->addr == ml->mr->addr &&
2909 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 2910 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK
2911 new_ml = NULL;
2912 break;
2913 }
2914 }
2915 if (new_ml) {
a16878d2 2916 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK
2917 }
2918 }
2919
a16878d2 2920 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b31f8412 2921 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
9479c57a
JK
2922 alias_print_queue);
2923 }
2924
a16878d2 2925 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 2926 g_free(ml);
314e2987
BS
2927 }
2928}
2929
5e8fd947
AK
2930struct FlatViewInfo {
2931 fprintf_function mon_printf;
2932 void *f;
2933 int counter;
2934 bool dispatch_tree;
2935};
2936
2937static void mtree_print_flatview(gpointer key, gpointer value,
2938 gpointer user_data)
57bb40c9 2939{
5e8fd947
AK
2940 FlatView *view = key;
2941 GArray *fv_address_spaces = value;
2942 struct FlatViewInfo *fvi = user_data;
2943 fprintf_function p = fvi->mon_printf;
2944 void *f = fvi->f;
57bb40c9
PX
2945 FlatRange *range = &view->ranges[0];
2946 MemoryRegion *mr;
2947 int n = view->nr;
5e8fd947
AK
2948 int i;
2949 AddressSpace *as;
2950
2951 p(f, "FlatView #%d\n", fvi->counter);
2952 ++fvi->counter;
2953
2954 for (i = 0; i < fv_address_spaces->len; ++i) {
2955 as = g_array_index(fv_address_spaces, AddressSpace*, i);
2956 p(f, " AS \"%s\", root: %s", as->name, memory_region_name(as->root));
2957 if (as->root->alias) {
2958 p(f, ", alias %s", memory_region_name(as->root->alias));
2959 }
2960 p(f, "\n");
2961 }
2962
2963 p(f, " Root memory region: %s\n",
2964 view->root ? memory_region_name(view->root) : "(none)");
57bb40c9
PX
2965
2966 if (n <= 0) {
5e8fd947 2967 p(f, MTREE_INDENT "No rendered FlatView\n\n");
57bb40c9
PX
2968 return;
2969 }
2970
2971 while (n--) {
2972 mr = range->mr;
377a07aa
PB
2973 if (range->offset_in_region) {
2974 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2975 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
2976 int128_get64(range->addr.start),
2977 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2978 mr->priority,
2979 range->readonly ? "rom" : memory_region_type(mr),
2980 memory_region_name(mr),
2981 range->offset_in_region);
2982 } else {
2983 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2984 TARGET_FMT_plx " (prio %d, %s): %s\n",
2985 int128_get64(range->addr.start),
2986 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2987 mr->priority,
2988 range->readonly ? "rom" : memory_region_type(mr),
2989 memory_region_name(mr));
2990 }
57bb40c9
PX
2991 range++;
2992 }
2993
5e8fd947
AK
2994#if !defined(CONFIG_USER_ONLY)
2995 if (fvi->dispatch_tree && view->root) {
2996 mtree_print_dispatch(p, f, view->dispatch, view->root);
2997 }
2998#endif
2999
3000 p(f, "\n");
3001}
3002
3003static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3004 gpointer user_data)
3005{
3006 FlatView *view = key;
3007 GArray *fv_address_spaces = value;
3008
3009 g_array_unref(fv_address_spaces);
57bb40c9 3010 flatview_unref(view);
5e8fd947
AK
3011
3012 return true;
57bb40c9
PX
3013}
3014
5e8fd947
AK
3015void mtree_info(fprintf_function mon_printf, void *f, bool flatview,
3016 bool dispatch_tree)
314e2987
BS
3017{
3018 MemoryRegionListHead ml_head;
3019 MemoryRegionList *ml, *ml2;
0d673e36 3020 AddressSpace *as;
314e2987 3021
57bb40c9 3022 if (flatview) {
5e8fd947
AK
3023 FlatView *view;
3024 struct FlatViewInfo fvi = {
3025 .mon_printf = mon_printf,
3026 .f = f,
3027 .counter = 0,
3028 .dispatch_tree = dispatch_tree
3029 };
3030 GArray *fv_address_spaces;
3031 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3032
3033 /* Gather all FVs in one table */
57bb40c9 3034 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
5e8fd947
AK
3035 view = address_space_get_flatview(as);
3036
3037 fv_address_spaces = g_hash_table_lookup(views, view);
3038 if (!fv_address_spaces) {
3039 fv_address_spaces = g_array_new(false, false, sizeof(as));
3040 g_hash_table_insert(views, view, fv_address_spaces);
3041 }
3042
3043 g_array_append_val(fv_address_spaces, as);
57bb40c9 3044 }
5e8fd947
AK
3045
3046 /* Print */
3047 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3048
3049 /* Free */
3050 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3051 g_hash_table_unref(views);
3052
57bb40c9
PX
3053 return;
3054 }
3055
314e2987
BS
3056 QTAILQ_INIT(&ml_head);
3057
0d673e36 3058 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
e48816aa
GH
3059 mon_printf(f, "address-space: %s\n", as->name);
3060 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
3061 mon_printf(f, "\n");
b9f9be88
BS
3062 }
3063
314e2987 3064 /* print aliased regions */
a16878d2 3065 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
e48816aa
GH
3066 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
3067 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
3068 mon_printf(f, "\n");
314e2987
BS
3069 }
3070
a16878d2 3071 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 3072 g_free(ml);
314e2987 3073 }
314e2987 3074}
b4fefef9 3075
b08199c6
PM
3076void memory_region_init_ram(MemoryRegion *mr,
3077 struct Object *owner,
3078 const char *name,
3079 uint64_t size,
3080 Error **errp)
3081{
3082 DeviceState *owner_dev;
3083 Error *err = NULL;
3084
3085 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3086 if (err) {
3087 error_propagate(errp, err);
3088 return;
3089 }
3090 /* This will assert if owner is neither NULL nor a DeviceState.
3091 * We only want the owner here for the purposes of defining a
3092 * unique name for migration. TODO: Ideally we should implement
3093 * a naming scheme for Objects which are not DeviceStates, in
3094 * which case we can relax this restriction.
3095 */
3096 owner_dev = DEVICE(owner);
3097 vmstate_register_ram(mr, owner_dev);
3098}
3099
3100void memory_region_init_rom(MemoryRegion *mr,
3101 struct Object *owner,
3102 const char *name,
3103 uint64_t size,
3104 Error **errp)
3105{
3106 DeviceState *owner_dev;
3107 Error *err = NULL;
3108
3109 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3110 if (err) {
3111 error_propagate(errp, err);
3112 return;
3113 }
3114 /* This will assert if owner is neither NULL nor a DeviceState.
3115 * We only want the owner here for the purposes of defining a
3116 * unique name for migration. TODO: Ideally we should implement
3117 * a naming scheme for Objects which are not DeviceStates, in
3118 * which case we can relax this restriction.
3119 */
3120 owner_dev = DEVICE(owner);
3121 vmstate_register_ram(mr, owner_dev);
3122}
3123
3124void memory_region_init_rom_device(MemoryRegion *mr,
3125 struct Object *owner,
3126 const MemoryRegionOps *ops,
3127 void *opaque,
3128 const char *name,
3129 uint64_t size,
3130 Error **errp)
3131{
3132 DeviceState *owner_dev;
3133 Error *err = NULL;
3134
3135 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3136 name, size, &err);
3137 if (err) {
3138 error_propagate(errp, err);
3139 return;
3140 }
3141 /* This will assert if owner is neither NULL nor a DeviceState.
3142 * We only want the owner here for the purposes of defining a
3143 * unique name for migration. TODO: Ideally we should implement
3144 * a naming scheme for Objects which are not DeviceStates, in
3145 * which case we can relax this restriction.
3146 */
3147 owner_dev = DEVICE(owner);
3148 vmstate_register_ram(mr, owner_dev);
3149}
3150
b4fefef9
PC
3151static const TypeInfo memory_region_info = {
3152 .parent = TYPE_OBJECT,
3153 .name = TYPE_MEMORY_REGION,
3154 .instance_size = sizeof(MemoryRegion),
3155 .instance_init = memory_region_initfn,
3156 .instance_finalize = memory_region_finalize,
3157};
3158
3df9d748
AK
3159static const TypeInfo iommu_memory_region_info = {
3160 .parent = TYPE_MEMORY_REGION,
3161 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 3162 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK
3163 .instance_size = sizeof(IOMMUMemoryRegion),
3164 .instance_init = iommu_memory_region_initfn,
1221a474 3165 .abstract = true,
3df9d748
AK
3166};
3167
b4fefef9
PC
3168static void memory_register_types(void)
3169{
3170 type_register_static(&memory_region_info);
3df9d748 3171 type_register_static(&iommu_memory_region_info);
b4fefef9
PC
3172}
3173
3174type_init(memory_register_types)