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exec: Explicitly export target AS from address_space_translate_internal
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CommitLineData
093bc2cd
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1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
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14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879
PB
18#include "qemu-common.h"
19#include "cpu.h"
022c62cb
PB
20#include "exec/memory.h"
21#include "exec/address-spaces.h"
22#include "exec/ioport.h"
409ddd01 23#include "qapi/visitor.h"
1de7afc9 24#include "qemu/bitops.h"
8c56c1a5 25#include "qemu/error-report.h"
2c9b15ca 26#include "qom/object.h"
0ab8ed18 27#include "trace-root.h"
093bc2cd 28
022c62cb 29#include "exec/memory-internal.h"
220c3ebd 30#include "exec/ram_addr.h"
8c56c1a5 31#include "sysemu/kvm.h"
e1c57ab8 32#include "sysemu/sysemu.h"
c9356746
FK
33#include "hw/misc/mmio_interface.h"
34#include "hw/qdev-properties.h"
b08199c6 35#include "migration/vmstate.h"
67d95c15 36
d197063f
PB
37//#define DEBUG_UNASSIGNED
38
22bde714
JK
39static unsigned memory_region_transaction_depth;
40static bool memory_region_update_pending;
4dc56152 41static bool ioeventfd_update_pending;
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42static bool global_dirty_log = false;
43
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44static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
45 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 46
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47static QTAILQ_HEAD(, AddressSpace) address_spaces
48 = QTAILQ_HEAD_INITIALIZER(address_spaces);
49
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50typedef struct AddrRange AddrRange;
51
8417cebf 52/*
c9cdaa3a 53 * Note that signed integers are needed for negative offsetting in aliases
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54 * (large MemoryRegion::alias_offset).
55 */
093bc2cd 56struct AddrRange {
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57 Int128 start;
58 Int128 size;
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59};
60
08dafab4 61static AddrRange addrrange_make(Int128 start, Int128 size)
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62{
63 return (AddrRange) { start, size };
64}
65
66static bool addrrange_equal(AddrRange r1, AddrRange r2)
67{
08dafab4 68 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
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69}
70
08dafab4 71static Int128 addrrange_end(AddrRange r)
093bc2cd 72{
08dafab4 73 return int128_add(r.start, r.size);
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74}
75
08dafab4 76static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 77{
08dafab4 78 int128_addto(&range.start, delta);
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79 return range;
80}
81
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82static bool addrrange_contains(AddrRange range, Int128 addr)
83{
84 return int128_ge(addr, range.start)
85 && int128_lt(addr, addrrange_end(range));
86}
87
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88static bool addrrange_intersects(AddrRange r1, AddrRange r2)
89{
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90 return addrrange_contains(r1, r2.start)
91 || addrrange_contains(r2, r1.start);
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92}
93
94static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
95{
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96 Int128 start = int128_max(r1.start, r2.start);
97 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
98 return addrrange_make(start, int128_sub(end, start));
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99}
100
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101enum ListenerDirection { Forward, Reverse };
102
7376e582 103#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
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104 do { \
105 MemoryListener *_listener; \
106 \
107 switch (_direction) { \
108 case Forward: \
109 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
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110 if (_listener->_callback) { \
111 _listener->_callback(_listener, ##_args); \
112 } \
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113 } \
114 break; \
115 case Reverse: \
116 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
117 memory_listeners, link) { \
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118 if (_listener->_callback) { \
119 _listener->_callback(_listener, ##_args); \
120 } \
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121 } \
122 break; \
123 default: \
124 abort(); \
125 } \
126 } while (0)
127
9a54635d 128#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
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129 do { \
130 MemoryListener *_listener; \
9a54635d 131 struct memory_listeners_as *list = &(_as)->listeners; \
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132 \
133 switch (_direction) { \
134 case Forward: \
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PB
135 QTAILQ_FOREACH(_listener, list, link_as) { \
136 if (_listener->_callback) { \
7376e582
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137 _listener->_callback(_listener, _section, ##_args); \
138 } \
139 } \
140 break; \
141 case Reverse: \
9a54635d
PB
142 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
143 link_as) { \
144 if (_listener->_callback) { \
7376e582
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145 _listener->_callback(_listener, _section, ##_args); \
146 } \
147 } \
148 break; \
149 default: \
150 abort(); \
151 } \
152 } while (0)
153
dfde4e6e 154/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 155#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44
PB
156 do { \
157 MemoryRegionSection mrs = section_from_flat_range(fr, as); \
9a54635d 158 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 159 } while(0)
0e0d36b4 160
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161struct CoalescedMemoryRange {
162 AddrRange addr;
163 QTAILQ_ENTRY(CoalescedMemoryRange) link;
164};
165
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166struct MemoryRegionIoeventfd {
167 AddrRange addr;
168 bool match_data;
169 uint64_t data;
753d5e14 170 EventNotifier *e;
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171};
172
173static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
174 MemoryRegionIoeventfd b)
175{
08dafab4 176 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 177 return true;
08dafab4 178 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 179 return false;
08dafab4 180 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 181 return true;
08dafab4 182 } else if (int128_gt(a.addr.size, b.addr.size)) {
3e9d69e7
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183 return false;
184 } else if (a.match_data < b.match_data) {
185 return true;
186 } else if (a.match_data > b.match_data) {
187 return false;
188 } else if (a.match_data) {
189 if (a.data < b.data) {
190 return true;
191 } else if (a.data > b.data) {
192 return false;
193 }
194 }
753d5e14 195 if (a.e < b.e) {
3e9d69e7 196 return true;
753d5e14 197 } else if (a.e > b.e) {
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198 return false;
199 }
200 return false;
201}
202
203static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
204 MemoryRegionIoeventfd b)
205{
206 return !memory_region_ioeventfd_before(a, b)
207 && !memory_region_ioeventfd_before(b, a);
208}
209
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210typedef struct FlatRange FlatRange;
211typedef struct FlatView FlatView;
212
213/* Range of memory in the global map. Addresses are absolute. */
214struct FlatRange {
215 MemoryRegion *mr;
a8170e5e 216 hwaddr offset_in_region;
093bc2cd 217 AddrRange addr;
5a583347 218 uint8_t dirty_log_mask;
b138e654 219 bool romd_mode;
fb1cd6f9 220 bool readonly;
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221};
222
223/* Flattened global view of current active memory hierarchy. Kept in sorted
224 * order.
225 */
226struct FlatView {
374f2981 227 struct rcu_head rcu;
856d7245 228 unsigned ref;
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229 FlatRange *ranges;
230 unsigned nr;
231 unsigned nr_allocated;
232};
233
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234typedef struct AddressSpaceOps AddressSpaceOps;
235
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236#define FOR_EACH_FLAT_RANGE(var, view) \
237 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
238
9c1f8f44
PB
239static inline MemoryRegionSection
240section_from_flat_range(FlatRange *fr, AddressSpace *as)
241{
242 return (MemoryRegionSection) {
243 .mr = fr->mr,
244 .address_space = as,
245 .offset_within_region = fr->offset_in_region,
246 .size = fr->addr.size,
247 .offset_within_address_space = int128_get64(fr->addr.start),
248 .readonly = fr->readonly,
249 };
250}
251
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252static bool flatrange_equal(FlatRange *a, FlatRange *b)
253{
254 return a->mr == b->mr
255 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 256 && a->offset_in_region == b->offset_in_region
b138e654 257 && a->romd_mode == b->romd_mode
fb1cd6f9 258 && a->readonly == b->readonly;
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259}
260
261static void flatview_init(FlatView *view)
262{
856d7245 263 view->ref = 1;
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264 view->ranges = NULL;
265 view->nr = 0;
266 view->nr_allocated = 0;
267}
268
269/* Insert a range into a given position. Caller is responsible for maintaining
270 * sorting order.
271 */
272static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
273{
274 if (view->nr == view->nr_allocated) {
275 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 276 view->ranges = g_realloc(view->ranges,
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277 view->nr_allocated * sizeof(*view->ranges));
278 }
279 memmove(view->ranges + pos + 1, view->ranges + pos,
280 (view->nr - pos) * sizeof(FlatRange));
281 view->ranges[pos] = *range;
dfde4e6e 282 memory_region_ref(range->mr);
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283 ++view->nr;
284}
285
286static void flatview_destroy(FlatView *view)
287{
dfde4e6e
PB
288 int i;
289
290 for (i = 0; i < view->nr; i++) {
291 memory_region_unref(view->ranges[i].mr);
292 }
7267c094 293 g_free(view->ranges);
a9a0c06d 294 g_free(view);
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295}
296
447b0d0b 297static bool flatview_ref(FlatView *view)
856d7245 298{
447b0d0b 299 return atomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB
300}
301
302static void flatview_unref(FlatView *view)
303{
304 if (atomic_fetch_dec(&view->ref) == 1) {
305 flatview_destroy(view);
306 }
307}
308
3d8e6bf9
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309static bool can_merge(FlatRange *r1, FlatRange *r2)
310{
08dafab4 311 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 312 && r1->mr == r2->mr
08dafab4
AK
313 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
314 r1->addr.size),
315 int128_make64(r2->offset_in_region))
d0a9b5bc 316 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 317 && r1->romd_mode == r2->romd_mode
fb1cd6f9 318 && r1->readonly == r2->readonly;
3d8e6bf9
AK
319}
320
8508e024 321/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK
322static void flatview_simplify(FlatView *view)
323{
324 unsigned i, j;
325
326 i = 0;
327 while (i < view->nr) {
328 j = i + 1;
329 while (j < view->nr
330 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 331 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
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332 ++j;
333 }
334 ++i;
335 memmove(&view->ranges[i], &view->ranges[j],
336 (view->nr - j) * sizeof(view->ranges[j]));
337 view->nr -= j - i;
338 }
339}
340
e7342aa3
PB
341static bool memory_region_big_endian(MemoryRegion *mr)
342{
343#ifdef TARGET_WORDS_BIGENDIAN
344 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
345#else
346 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
347#endif
348}
349
e11ef3d1
PB
350static bool memory_region_wrong_endianness(MemoryRegion *mr)
351{
352#ifdef TARGET_WORDS_BIGENDIAN
353 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
354#else
355 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
356#endif
357}
358
359static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
360{
361 if (memory_region_wrong_endianness(mr)) {
362 switch (size) {
363 case 1:
364 break;
365 case 2:
366 *data = bswap16(*data);
367 break;
368 case 4:
369 *data = bswap32(*data);
370 break;
371 case 8:
372 *data = bswap64(*data);
373 break;
374 default:
375 abort();
376 }
377 }
378}
379
4779dc1d
HB
380static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
381{
382 MemoryRegion *root;
383 hwaddr abs_addr = offset;
384
385 abs_addr += mr->addr;
386 for (root = mr; root->container; ) {
387 root = root->container;
388 abs_addr += root->addr;
389 }
390
391 return abs_addr;
392}
393
5a68be94
HB
394static int get_cpu_index(void)
395{
396 if (current_cpu) {
397 return current_cpu->cpu_index;
398 }
399 return -1;
400}
401
cc05c43a
PM
402static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
403 hwaddr addr,
404 uint64_t *value,
405 unsigned size,
406 unsigned shift,
407 uint64_t mask,
408 MemTxAttrs attrs)
409{
410 uint64_t tmp;
411
412 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
23d92d68 413 if (mr->subpage) {
5a68be94 414 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
415 } else if (mr == &io_mem_notdirty) {
416 /* Accesses to code which has previously been translated into a TB show
417 * up in the MMIO path, as accesses to the io_mem_notdirty
418 * MemoryRegion. */
419 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
420 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
421 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 422 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 423 }
cc05c43a
PM
424 *value |= (tmp & mask) << shift;
425 return MEMTX_OK;
426}
427
428static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB
429 hwaddr addr,
430 uint64_t *value,
431 unsigned size,
432 unsigned shift,
cc05c43a
PM
433 uint64_t mask,
434 MemTxAttrs attrs)
ce5d2f33 435{
ce5d2f33
PB
436 uint64_t tmp;
437
cc05c43a 438 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 439 if (mr->subpage) {
5a68be94 440 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
441 } else if (mr == &io_mem_notdirty) {
442 /* Accesses to code which has previously been translated into a TB show
443 * up in the MMIO path, as accesses to the io_mem_notdirty
444 * MemoryRegion. */
445 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
446 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
447 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 448 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 449 }
ce5d2f33 450 *value |= (tmp & mask) << shift;
cc05c43a 451 return MEMTX_OK;
ce5d2f33
PB
452}
453
cc05c43a
PM
454static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
455 hwaddr addr,
456 uint64_t *value,
457 unsigned size,
458 unsigned shift,
459 uint64_t mask,
460 MemTxAttrs attrs)
164a4dcd 461{
cc05c43a
PM
462 uint64_t tmp = 0;
463 MemTxResult r;
164a4dcd 464
cc05c43a 465 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 466 if (mr->subpage) {
5a68be94 467 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
468 } else if (mr == &io_mem_notdirty) {
469 /* Accesses to code which has previously been translated into a TB show
470 * up in the MMIO path, as accesses to the io_mem_notdirty
471 * MemoryRegion. */
472 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
473 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
474 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 475 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 476 }
164a4dcd 477 *value |= (tmp & mask) << shift;
cc05c43a 478 return r;
164a4dcd
AK
479}
480
cc05c43a
PM
481static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
482 hwaddr addr,
483 uint64_t *value,
484 unsigned size,
485 unsigned shift,
486 uint64_t mask,
487 MemTxAttrs attrs)
ce5d2f33 488{
ce5d2f33
PB
489 uint64_t tmp;
490
491 tmp = (*value >> shift) & mask;
23d92d68 492 if (mr->subpage) {
5a68be94 493 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
494 } else if (mr == &io_mem_notdirty) {
495 /* Accesses to code which has previously been translated into a TB show
496 * up in the MMIO path, as accesses to the io_mem_notdirty
497 * MemoryRegion. */
498 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
499 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
500 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 501 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 502 }
ce5d2f33 503 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
cc05c43a 504 return MEMTX_OK;
ce5d2f33
PB
505}
506
cc05c43a
PM
507static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
508 hwaddr addr,
509 uint64_t *value,
510 unsigned size,
511 unsigned shift,
512 uint64_t mask,
513 MemTxAttrs attrs)
164a4dcd 514{
164a4dcd
AK
515 uint64_t tmp;
516
517 tmp = (*value >> shift) & mask;
23d92d68 518 if (mr->subpage) {
5a68be94 519 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
520 } else if (mr == &io_mem_notdirty) {
521 /* Accesses to code which has previously been translated into a TB show
522 * up in the MMIO path, as accesses to the io_mem_notdirty
523 * MemoryRegion. */
524 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
525 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
526 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 527 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 528 }
164a4dcd 529 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 530 return MEMTX_OK;
164a4dcd
AK
531}
532
cc05c43a
PM
533static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
534 hwaddr addr,
535 uint64_t *value,
536 unsigned size,
537 unsigned shift,
538 uint64_t mask,
539 MemTxAttrs attrs)
540{
541 uint64_t tmp;
542
cc05c43a 543 tmp = (*value >> shift) & mask;
23d92d68 544 if (mr->subpage) {
5a68be94 545 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
546 } else if (mr == &io_mem_notdirty) {
547 /* Accesses to code which has previously been translated into a TB show
548 * up in the MMIO path, as accesses to the io_mem_notdirty
549 * MemoryRegion. */
550 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
551 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
552 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 553 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 554 }
cc05c43a
PM
555 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
556}
557
558static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK
559 uint64_t *value,
560 unsigned size,
561 unsigned access_size_min,
562 unsigned access_size_max,
05e015f7
KF
563 MemTxResult (*access_fn)
564 (MemoryRegion *mr,
565 hwaddr addr,
566 uint64_t *value,
567 unsigned size,
568 unsigned shift,
569 uint64_t mask,
570 MemTxAttrs attrs),
cc05c43a
PM
571 MemoryRegion *mr,
572 MemTxAttrs attrs)
164a4dcd
AK
573{
574 uint64_t access_mask;
575 unsigned access_size;
576 unsigned i;
cc05c43a 577 MemTxResult r = MEMTX_OK;
164a4dcd
AK
578
579 if (!access_size_min) {
580 access_size_min = 1;
581 }
582 if (!access_size_max) {
583 access_size_max = 4;
584 }
ce5d2f33
PB
585
586 /* FIXME: support unaligned access? */
164a4dcd
AK
587 access_size = MAX(MIN(size, access_size_max), access_size_min);
588 access_mask = -1ULL >> (64 - access_size * 8);
e7342aa3
PB
589 if (memory_region_big_endian(mr)) {
590 for (i = 0; i < size; i += access_size) {
05e015f7 591 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 592 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB
593 }
594 } else {
595 for (i = 0; i < size; i += access_size) {
05e015f7 596 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 597 access_mask, attrs);
e7342aa3 598 }
164a4dcd 599 }
cc05c43a 600 return r;
164a4dcd
AK
601}
602
e2177955
AK
603static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
604{
0d673e36
AK
605 AddressSpace *as;
606
feca4ac1
PB
607 while (mr->container) {
608 mr = mr->container;
e2177955 609 }
0d673e36
AK
610 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
611 if (mr == as->root) {
612 return as;
613 }
e2177955 614 }
eed2bacf 615 return NULL;
e2177955
AK
616}
617
093bc2cd
AK
618/* Render a memory region into the global view. Ranges in @view obscure
619 * ranges in @mr.
620 */
621static void render_memory_region(FlatView *view,
622 MemoryRegion *mr,
08dafab4 623 Int128 base,
fb1cd6f9
AK
624 AddrRange clip,
625 bool readonly)
093bc2cd
AK
626{
627 MemoryRegion *subregion;
628 unsigned i;
a8170e5e 629 hwaddr offset_in_region;
08dafab4
AK
630 Int128 remain;
631 Int128 now;
093bc2cd
AK
632 FlatRange fr;
633 AddrRange tmp;
634
6bba19ba
AK
635 if (!mr->enabled) {
636 return;
637 }
638
08dafab4 639 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 640 readonly |= mr->readonly;
093bc2cd
AK
641
642 tmp = addrrange_make(base, mr->size);
643
644 if (!addrrange_intersects(tmp, clip)) {
645 return;
646 }
647
648 clip = addrrange_intersection(tmp, clip);
649
650 if (mr->alias) {
08dafab4
AK
651 int128_subfrom(&base, int128_make64(mr->alias->addr));
652 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 653 render_memory_region(view, mr->alias, base, clip, readonly);
093bc2cd
AK
654 return;
655 }
656
657 /* Render subregions in priority order. */
658 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 659 render_memory_region(view, subregion, base, clip, readonly);
093bc2cd
AK
660 }
661
14a3c10a 662 if (!mr->terminates) {
093bc2cd
AK
663 return;
664 }
665
08dafab4 666 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK
667 base = clip.start;
668 remain = clip.size;
669
2eb74e1a 670 fr.mr = mr;
6f6a5ef3 671 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 672 fr.romd_mode = mr->romd_mode;
2eb74e1a
PC
673 fr.readonly = readonly;
674
093bc2cd 675 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK
676 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
677 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK
678 continue;
679 }
08dafab4
AK
680 if (int128_lt(base, view->ranges[i].addr.start)) {
681 now = int128_min(remain,
682 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK
683 fr.offset_in_region = offset_in_region;
684 fr.addr = addrrange_make(base, now);
685 flatview_insert(view, i, &fr);
686 ++i;
08dafab4
AK
687 int128_addto(&base, now);
688 offset_in_region += int128_get64(now);
689 int128_subfrom(&remain, now);
093bc2cd 690 }
d26a8cae
AK
691 now = int128_sub(int128_min(int128_add(base, remain),
692 addrrange_end(view->ranges[i].addr)),
693 base);
694 int128_addto(&base, now);
695 offset_in_region += int128_get64(now);
696 int128_subfrom(&remain, now);
093bc2cd 697 }
08dafab4 698 if (int128_nz(remain)) {
093bc2cd
AK
699 fr.offset_in_region = offset_in_region;
700 fr.addr = addrrange_make(base, remain);
701 flatview_insert(view, i, &fr);
702 }
703}
704
705/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 706static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 707{
a9a0c06d 708 FlatView *view;
093bc2cd 709
a9a0c06d
PB
710 view = g_new(FlatView, 1);
711 flatview_init(view);
093bc2cd 712
83f3c251 713 if (mr) {
a9a0c06d 714 render_memory_region(view, mr, int128_zero(),
83f3c251
AK
715 addrrange_make(int128_zero(), int128_2_64()), false);
716 }
a9a0c06d 717 flatview_simplify(view);
093bc2cd
AK
718
719 return view;
720}
721
3e9d69e7
AK
722static void address_space_add_del_ioeventfds(AddressSpace *as,
723 MemoryRegionIoeventfd *fds_new,
724 unsigned fds_new_nb,
725 MemoryRegionIoeventfd *fds_old,
726 unsigned fds_old_nb)
727{
728 unsigned iold, inew;
80a1ea37
AK
729 MemoryRegionIoeventfd *fd;
730 MemoryRegionSection section;
3e9d69e7
AK
731
732 /* Generate a symmetric difference of the old and new fd sets, adding
733 * and deleting as necessary.
734 */
735
736 iold = inew = 0;
737 while (iold < fds_old_nb || inew < fds_new_nb) {
738 if (iold < fds_old_nb
739 && (inew == fds_new_nb
740 || memory_region_ioeventfd_before(fds_old[iold],
741 fds_new[inew]))) {
80a1ea37
AK
742 fd = &fds_old[iold];
743 section = (MemoryRegionSection) {
f6790af6 744 .address_space = as,
80a1ea37 745 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 746 .size = fd->addr.size,
80a1ea37 747 };
9a54635d 748 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 749 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
750 ++iold;
751 } else if (inew < fds_new_nb
752 && (iold == fds_old_nb
753 || memory_region_ioeventfd_before(fds_new[inew],
754 fds_old[iold]))) {
80a1ea37
AK
755 fd = &fds_new[inew];
756 section = (MemoryRegionSection) {
f6790af6 757 .address_space = as,
80a1ea37 758 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 759 .size = fd->addr.size,
80a1ea37 760 };
9a54635d 761 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 762 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
763 ++inew;
764 } else {
765 ++iold;
766 ++inew;
767 }
768 }
769}
770
856d7245
PB
771static FlatView *address_space_get_flatview(AddressSpace *as)
772{
773 FlatView *view;
774
374f2981 775 rcu_read_lock();
447b0d0b
PB
776 do {
777 view = atomic_rcu_read(&as->current_map);
778 /* If somebody has replaced as->current_map concurrently,
779 * flatview_ref returns false.
780 */
781 } while (!flatview_ref(view));
374f2981 782 rcu_read_unlock();
856d7245
PB
783 return view;
784}
785
3e9d69e7
AK
786static void address_space_update_ioeventfds(AddressSpace *as)
787{
99e86347 788 FlatView *view;
3e9d69e7
AK
789 FlatRange *fr;
790 unsigned ioeventfd_nb = 0;
791 MemoryRegionIoeventfd *ioeventfds = NULL;
792 AddrRange tmp;
793 unsigned i;
794
856d7245 795 view = address_space_get_flatview(as);
99e86347 796 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK
797 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
798 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK
799 int128_sub(fr->addr.start,
800 int128_make64(fr->offset_in_region)));
3e9d69e7
AK
801 if (addrrange_intersects(fr->addr, tmp)) {
802 ++ioeventfd_nb;
7267c094 803 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK
804 ioeventfd_nb * sizeof(*ioeventfds));
805 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
806 ioeventfds[ioeventfd_nb-1].addr = tmp;
807 }
808 }
809 }
810
811 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
812 as->ioeventfds, as->ioeventfd_nb);
813
7267c094 814 g_free(as->ioeventfds);
3e9d69e7
AK
815 as->ioeventfds = ioeventfds;
816 as->ioeventfd_nb = ioeventfd_nb;
856d7245 817 flatview_unref(view);
3e9d69e7
AK
818}
819
b8af1afb 820static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB
821 const FlatView *old_view,
822 const FlatView *new_view,
b8af1afb 823 bool adding)
093bc2cd 824{
093bc2cd
AK
825 unsigned iold, inew;
826 FlatRange *frold, *frnew;
093bc2cd
AK
827
828 /* Generate a symmetric difference of the old and new memory maps.
829 * Kill ranges in the old map, and instantiate ranges in the new map.
830 */
831 iold = inew = 0;
a9a0c06d
PB
832 while (iold < old_view->nr || inew < new_view->nr) {
833 if (iold < old_view->nr) {
834 frold = &old_view->ranges[iold];
093bc2cd
AK
835 } else {
836 frold = NULL;
837 }
a9a0c06d
PB
838 if (inew < new_view->nr) {
839 frnew = &new_view->ranges[inew];
093bc2cd
AK
840 } else {
841 frnew = NULL;
842 }
843
844 if (frold
845 && (!frnew
08dafab4
AK
846 || int128_lt(frold->addr.start, frnew->addr.start)
847 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 848 && !flatrange_equal(frold, frnew)))) {
41a6e477 849 /* In old but not in new, or in both but attributes changed. */
093bc2cd 850
b8af1afb 851 if (!adding) {
72e22d2f 852 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK
853 }
854
093bc2cd
AK
855 ++iold;
856 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 857 /* In both and unchanged (except logging may have changed) */
093bc2cd 858
b8af1afb 859 if (adding) {
50c1e149 860 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB
861 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
862 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
863 frold->dirty_log_mask,
864 frnew->dirty_log_mask);
865 }
866 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
867 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
868 frold->dirty_log_mask,
869 frnew->dirty_log_mask);
b8af1afb 870 }
5a583347
AK
871 }
872
093bc2cd
AK
873 ++iold;
874 ++inew;
093bc2cd
AK
875 } else {
876 /* In new */
877
b8af1afb 878 if (adding) {
72e22d2f 879 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK
880 }
881
093bc2cd
AK
882 ++inew;
883 }
884 }
b8af1afb
AK
885}
886
887
888static void address_space_update_topology(AddressSpace *as)
889{
856d7245 890 FlatView *old_view = address_space_get_flatview(as);
a9a0c06d 891 FlatView *new_view = generate_memory_topology(as->root);
b8af1afb
AK
892
893 address_space_update_topology_pass(as, old_view, new_view, false);
894 address_space_update_topology_pass(as, old_view, new_view, true);
895
374f2981
PB
896 /* Writes are protected by the BQL. */
897 atomic_rcu_set(&as->current_map, new_view);
898 call_rcu(old_view, flatview_unref, rcu);
856d7245
PB
899
900 /* Note that all the old MemoryRegions are still alive up to this
901 * point. This relieves most MemoryListeners from the need to
902 * ref/unref the MemoryRegions they get---unless they use them
903 * outside the iothread mutex, in which case precise reference
904 * counting is necessary.
905 */
906 flatview_unref(old_view);
907
3e9d69e7 908 address_space_update_ioeventfds(as);
093bc2cd
AK
909}
910
4ef4db86
AK
911void memory_region_transaction_begin(void)
912{
bb880ded 913 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK
914 ++memory_region_transaction_depth;
915}
916
917void memory_region_transaction_commit(void)
918{
0d673e36
AK
919 AddressSpace *as;
920
4ef4db86 921 assert(memory_region_transaction_depth);
8d04fb55
JK
922 assert(qemu_mutex_iothread_locked());
923
4ef4db86 924 --memory_region_transaction_depth;
4dc56152
GA
925 if (!memory_region_transaction_depth) {
926 if (memory_region_update_pending) {
927 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 928
4dc56152
GA
929 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
930 address_space_update_topology(as);
931 }
ade9c1aa 932 memory_region_update_pending = false;
4dc56152
GA
933 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
934 } else if (ioeventfd_update_pending) {
935 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
936 address_space_update_ioeventfds(as);
937 }
ade9c1aa 938 ioeventfd_update_pending = false;
4dc56152 939 }
4dc56152 940 }
4ef4db86
AK
941}
942
545e92e0
AK
943static void memory_region_destructor_none(MemoryRegion *mr)
944{
945}
946
947static void memory_region_destructor_ram(MemoryRegion *mr)
948{
f1060c55 949 qemu_ram_free(mr->ram_block);
545e92e0
AK
950}
951
b4fefef9
PC
952static bool memory_region_need_escape(char c)
953{
954 return c == '/' || c == '[' || c == '\\' || c == ']';
955}
956
957static char *memory_region_escape_name(const char *name)
958{
959 const char *p;
960 char *escaped, *q;
961 uint8_t c;
962 size_t bytes = 0;
963
964 for (p = name; *p; p++) {
965 bytes += memory_region_need_escape(*p) ? 4 : 1;
966 }
967 if (bytes == p - name) {
968 return g_memdup(name, bytes + 1);
969 }
970
971 escaped = g_malloc(bytes + 1);
972 for (p = name, q = escaped; *p; p++) {
973 c = *p;
974 if (unlikely(memory_region_need_escape(c))) {
975 *q++ = '\\';
976 *q++ = 'x';
977 *q++ = "0123456789abcdef"[c >> 4];
978 c = "0123456789abcdef"[c & 15];
979 }
980 *q++ = c;
981 }
982 *q = 0;
983 return escaped;
984}
985
3df9d748
AK
986static void memory_region_do_init(MemoryRegion *mr,
987 Object *owner,
988 const char *name,
989 uint64_t size)
093bc2cd 990{
08dafab4
AK
991 mr->size = int128_make64(size);
992 if (size == UINT64_MAX) {
993 mr->size = int128_2_64();
994 }
302fa283 995 mr->name = g_strdup(name);
612263cf 996 mr->owner = owner;
58eaa217 997 mr->ram_block = NULL;
b4fefef9
PC
998
999 if (name) {
843ef73a
PC
1000 char *escaped_name = memory_region_escape_name(name);
1001 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB
1002
1003 if (!owner) {
1004 owner = container_get(qdev_get_machine(), "/unattached");
1005 }
1006
843ef73a 1007 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1008 object_unref(OBJECT(mr));
843ef73a
PC
1009 g_free(name_array);
1010 g_free(escaped_name);
b4fefef9
PC
1011 }
1012}
1013
3df9d748
AK
1014void memory_region_init(MemoryRegion *mr,
1015 Object *owner,
1016 const char *name,
1017 uint64_t size)
1018{
1019 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1020 memory_region_do_init(mr, owner, name, size);
1021}
1022
d7bce999
EB
1023static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1024 void *opaque, Error **errp)
409ddd01
PC
1025{
1026 MemoryRegion *mr = MEMORY_REGION(obj);
1027 uint64_t value = mr->addr;
1028
51e72bc1 1029 visit_type_uint64(v, name, &value, errp);
409ddd01
PC
1030}
1031
d7bce999
EB
1032static void memory_region_get_container(Object *obj, Visitor *v,
1033 const char *name, void *opaque,
1034 Error **errp)
409ddd01
PC
1035{
1036 MemoryRegion *mr = MEMORY_REGION(obj);
1037 gchar *path = (gchar *)"";
1038
1039 if (mr->container) {
1040 path = object_get_canonical_path(OBJECT(mr->container));
1041 }
51e72bc1 1042 visit_type_str(v, name, &path, errp);
409ddd01
PC
1043 if (mr->container) {
1044 g_free(path);
1045 }
1046}
1047
1048static Object *memory_region_resolve_container(Object *obj, void *opaque,
1049 const char *part)
1050{
1051 MemoryRegion *mr = MEMORY_REGION(obj);
1052
1053 return OBJECT(mr->container);
1054}
1055
d7bce999
EB
1056static void memory_region_get_priority(Object *obj, Visitor *v,
1057 const char *name, void *opaque,
1058 Error **errp)
d33382da
PC
1059{
1060 MemoryRegion *mr = MEMORY_REGION(obj);
1061 int32_t value = mr->priority;
1062
51e72bc1 1063 visit_type_int32(v, name, &value, errp);
d33382da
PC
1064}
1065
d7bce999
EB
1066static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1067 void *opaque, Error **errp)
52aef7bb
PC
1068{
1069 MemoryRegion *mr = MEMORY_REGION(obj);
1070 uint64_t value = memory_region_size(mr);
1071
51e72bc1 1072 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC
1073}
1074
b4fefef9
PC
1075static void memory_region_initfn(Object *obj)
1076{
1077 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1078 ObjectProperty *op;
b4fefef9
PC
1079
1080 mr->ops = &unassigned_mem_ops;
6bba19ba 1081 mr->enabled = true;
5f9a5ea1 1082 mr->romd_mode = true;
196ea131 1083 mr->global_locking = true;
545e92e0 1084 mr->destructor = memory_region_destructor_none;
093bc2cd 1085 QTAILQ_INIT(&mr->subregions);
093bc2cd 1086 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC
1087
1088 op = object_property_add(OBJECT(mr), "container",
1089 "link<" TYPE_MEMORY_REGION ">",
1090 memory_region_get_container,
1091 NULL, /* memory_region_set_container */
1092 NULL, NULL, &error_abort);
1093 op->resolve = memory_region_resolve_container;
1094
1095 object_property_add(OBJECT(mr), "addr", "uint64",
1096 memory_region_get_addr,
1097 NULL, /* memory_region_set_addr */
1098 NULL, NULL, &error_abort);
d33382da
PC
1099 object_property_add(OBJECT(mr), "priority", "uint32",
1100 memory_region_get_priority,
1101 NULL, /* memory_region_set_priority */
1102 NULL, NULL, &error_abort);
52aef7bb
PC
1103 object_property_add(OBJECT(mr), "size", "uint64",
1104 memory_region_get_size,
1105 NULL, /* memory_region_set_size, */
1106 NULL, NULL, &error_abort);
093bc2cd
AK
1107}
1108
3df9d748
AK
1109static void iommu_memory_region_initfn(Object *obj)
1110{
1111 MemoryRegion *mr = MEMORY_REGION(obj);
1112
1113 mr->is_iommu = true;
1114}
1115
b018ddf6
PB
1116static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1117 unsigned size)
1118{
1119#ifdef DEBUG_UNASSIGNED
1120 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1121#endif
4917cf44
AF
1122 if (current_cpu != NULL) {
1123 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
c658b94f 1124 }
68a7439a 1125 return 0;
b018ddf6
PB
1126}
1127
1128static void unassigned_mem_write(void *opaque, hwaddr addr,
1129 uint64_t val, unsigned size)
1130{
1131#ifdef DEBUG_UNASSIGNED
1132 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1133#endif
4917cf44
AF
1134 if (current_cpu != NULL) {
1135 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1136 }
b018ddf6
PB
1137}
1138
d197063f
PB
1139static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1140 unsigned size, bool is_write)
1141{
1142 return false;
1143}
1144
1145const MemoryRegionOps unassigned_mem_ops = {
1146 .valid.accepts = unassigned_mem_accepts,
1147 .endianness = DEVICE_NATIVE_ENDIAN,
1148};
1149
4a2e242b
AW
1150static uint64_t memory_region_ram_device_read(void *opaque,
1151 hwaddr addr, unsigned size)
1152{
1153 MemoryRegion *mr = opaque;
1154 uint64_t data = (uint64_t)~0;
1155
1156 switch (size) {
1157 case 1:
1158 data = *(uint8_t *)(mr->ram_block->host + addr);
1159 break;
1160 case 2:
1161 data = *(uint16_t *)(mr->ram_block->host + addr);
1162 break;
1163 case 4:
1164 data = *(uint32_t *)(mr->ram_block->host + addr);
1165 break;
1166 case 8:
1167 data = *(uint64_t *)(mr->ram_block->host + addr);
1168 break;
1169 }
1170
1171 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1172
1173 return data;
1174}
1175
1176static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1177 uint64_t data, unsigned size)
1178{
1179 MemoryRegion *mr = opaque;
1180
1181 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1182
1183 switch (size) {
1184 case 1:
1185 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1186 break;
1187 case 2:
1188 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1189 break;
1190 case 4:
1191 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1192 break;
1193 case 8:
1194 *(uint64_t *)(mr->ram_block->host + addr) = data;
1195 break;
1196 }
1197}
1198
1199static const MemoryRegionOps ram_device_mem_ops = {
1200 .read = memory_region_ram_device_read,
1201 .write = memory_region_ram_device_write,
c99a29e7 1202 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW
1203 .valid = {
1204 .min_access_size = 1,
1205 .max_access_size = 8,
1206 .unaligned = true,
1207 },
1208 .impl = {
1209 .min_access_size = 1,
1210 .max_access_size = 8,
1211 .unaligned = true,
1212 },
1213};
1214
d2702032
PB
1215bool memory_region_access_valid(MemoryRegion *mr,
1216 hwaddr addr,
1217 unsigned size,
1218 bool is_write)
093bc2cd 1219{
a014ed07
PB
1220 int access_size_min, access_size_max;
1221 int access_size, i;
897fa7cf 1222
093bc2cd
AK
1223 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1224 return false;
1225 }
1226
a014ed07 1227 if (!mr->ops->valid.accepts) {
093bc2cd
AK
1228 return true;
1229 }
1230
a014ed07
PB
1231 access_size_min = mr->ops->valid.min_access_size;
1232 if (!mr->ops->valid.min_access_size) {
1233 access_size_min = 1;
1234 }
1235
1236 access_size_max = mr->ops->valid.max_access_size;
1237 if (!mr->ops->valid.max_access_size) {
1238 access_size_max = 4;
1239 }
1240
1241 access_size = MAX(MIN(size, access_size_max), access_size_min);
1242 for (i = 0; i < size; i += access_size) {
1243 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1244 is_write)) {
1245 return false;
1246 }
093bc2cd 1247 }
a014ed07 1248
093bc2cd
AK
1249 return true;
1250}
1251
cc05c43a
PM
1252static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1253 hwaddr addr,
1254 uint64_t *pval,
1255 unsigned size,
1256 MemTxAttrs attrs)
093bc2cd 1257{
cc05c43a 1258 *pval = 0;
093bc2cd 1259
ce5d2f33 1260 if (mr->ops->read) {
cc05c43a
PM
1261 return access_with_adjusted_size(addr, pval, size,
1262 mr->ops->impl.min_access_size,
1263 mr->ops->impl.max_access_size,
1264 memory_region_read_accessor,
1265 mr, attrs);
1266 } else if (mr->ops->read_with_attrs) {
1267 return access_with_adjusted_size(addr, pval, size,
1268 mr->ops->impl.min_access_size,
1269 mr->ops->impl.max_access_size,
1270 memory_region_read_with_attrs_accessor,
1271 mr, attrs);
ce5d2f33 1272 } else {
cc05c43a
PM
1273 return access_with_adjusted_size(addr, pval, size, 1, 4,
1274 memory_region_oldmmio_read_accessor,
1275 mr, attrs);
74901c3b 1276 }
093bc2cd
AK
1277}
1278
3b643495
PM
1279MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1280 hwaddr addr,
1281 uint64_t *pval,
1282 unsigned size,
1283 MemTxAttrs attrs)
a621f38d 1284{
cc05c43a
PM
1285 MemTxResult r;
1286
791af8c8
PB
1287 if (!memory_region_access_valid(mr, addr, size, false)) {
1288 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1289 return MEMTX_DECODE_ERROR;
791af8c8 1290 }
a621f38d 1291
cc05c43a 1292 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1293 adjust_endianness(mr, pval, size);
cc05c43a 1294 return r;
a621f38d 1295}
093bc2cd 1296
8c56c1a5
PF
1297/* Return true if an eventfd was signalled */
1298static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1299 hwaddr addr,
1300 uint64_t data,
1301 unsigned size,
1302 MemTxAttrs attrs)
1303{
1304 MemoryRegionIoeventfd ioeventfd = {
1305 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1306 .data = data,
1307 };
1308 unsigned i;
1309
1310 for (i = 0; i < mr->ioeventfd_nb; i++) {
1311 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1312 ioeventfd.e = mr->ioeventfds[i].e;
1313
1314 if (memory_region_ioeventfd_equal(ioeventfd, mr->ioeventfds[i])) {
1315 event_notifier_set(ioeventfd.e);
1316 return true;
1317 }
1318 }
1319
1320 return false;
1321}
1322
3b643495
PM
1323MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1324 hwaddr addr,
1325 uint64_t data,
1326 unsigned size,
1327 MemTxAttrs attrs)
a621f38d 1328{
897fa7cf 1329 if (!memory_region_access_valid(mr, addr, size, true)) {
b018ddf6 1330 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1331 return MEMTX_DECODE_ERROR;
093bc2cd
AK
1332 }
1333
a621f38d
AK
1334 adjust_endianness(mr, &data, size);
1335
8c56c1a5
PF
1336 if ((!kvm_eventfds_enabled()) &&
1337 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1338 return MEMTX_OK;
1339 }
1340
ce5d2f33 1341 if (mr->ops->write) {
cc05c43a
PM
1342 return access_with_adjusted_size(addr, &data, size,
1343 mr->ops->impl.min_access_size,
1344 mr->ops->impl.max_access_size,
1345 memory_region_write_accessor, mr,
1346 attrs);
1347 } else if (mr->ops->write_with_attrs) {
1348 return
1349 access_with_adjusted_size(addr, &data, size,
1350 mr->ops->impl.min_access_size,
1351 mr->ops->impl.max_access_size,
1352 memory_region_write_with_attrs_accessor,
1353 mr, attrs);
ce5d2f33 1354 } else {
cc05c43a
PM
1355 return access_with_adjusted_size(addr, &data, size, 1, 4,
1356 memory_region_oldmmio_write_accessor,
1357 mr, attrs);
74901c3b 1358 }
093bc2cd
AK
1359}
1360
093bc2cd 1361void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1362 Object *owner,
093bc2cd
AK
1363 const MemoryRegionOps *ops,
1364 void *opaque,
1365 const char *name,
1366 uint64_t size)
1367{
2c9b15ca 1368 memory_region_init(mr, owner, name, size);
6d6d2abf 1369 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1370 mr->opaque = opaque;
14a3c10a 1371 mr->terminates = true;
093bc2cd
AK
1372}
1373
1cfe48c1
PM
1374void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1375 Object *owner,
1376 const char *name,
1377 uint64_t size,
1378 Error **errp)
093bc2cd 1379{
2c9b15ca 1380 memory_region_init(mr, owner, name, size);
8ea9252a 1381 mr->ram = true;
14a3c10a 1382 mr->terminates = true;
545e92e0 1383 mr->destructor = memory_region_destructor_ram;
8e41fb63 1384 mr->ram_block = qemu_ram_alloc(size, mr, errp);
677e7805 1385 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
0b183fc8
PB
1386}
1387
60786ef3
MT
1388void memory_region_init_resizeable_ram(MemoryRegion *mr,
1389 Object *owner,
1390 const char *name,
1391 uint64_t size,
1392 uint64_t max_size,
1393 void (*resized)(const char*,
1394 uint64_t length,
1395 void *host),
1396 Error **errp)
1397{
1398 memory_region_init(mr, owner, name, size);
1399 mr->ram = true;
1400 mr->terminates = true;
1401 mr->destructor = memory_region_destructor_ram;
8e41fb63
FZ
1402 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1403 mr, errp);
677e7805 1404 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
60786ef3
MT
1405}
1406
0b183fc8
PB
1407#ifdef __linux__
1408void memory_region_init_ram_from_file(MemoryRegion *mr,
1409 struct Object *owner,
1410 const char *name,
1411 uint64_t size,
dbcb8981 1412 bool share,
7f56e740
PB
1413 const char *path,
1414 Error **errp)
0b183fc8
PB
1415{
1416 memory_region_init(mr, owner, name, size);
1417 mr->ram = true;
1418 mr->terminates = true;
1419 mr->destructor = memory_region_destructor_ram;
8e41fb63 1420 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
677e7805 1421 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
093bc2cd 1422}
fea617c5
MAL
1423
1424void memory_region_init_ram_from_fd(MemoryRegion *mr,
1425 struct Object *owner,
1426 const char *name,
1427 uint64_t size,
1428 bool share,
1429 int fd,
1430 Error **errp)
1431{
1432 memory_region_init(mr, owner, name, size);
1433 mr->ram = true;
1434 mr->terminates = true;
1435 mr->destructor = memory_region_destructor_ram;
1436 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1437 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1438}
0b183fc8 1439#endif
093bc2cd
AK
1440
1441void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1442 Object *owner,
093bc2cd
AK
1443 const char *name,
1444 uint64_t size,
1445 void *ptr)
1446{
2c9b15ca 1447 memory_region_init(mr, owner, name, size);
8ea9252a 1448 mr->ram = true;
14a3c10a 1449 mr->terminates = true;
fc3e7665 1450 mr->destructor = memory_region_destructor_ram;
677e7805 1451 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT
1452
1453 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1454 assert(ptr != NULL);
8e41fb63 1455 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK
1456}
1457
21e00fa5
AW
1458void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1459 Object *owner,
1460 const char *name,
1461 uint64_t size,
1462 void *ptr)
e4dc3f59 1463{
21e00fa5
AW
1464 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1465 mr->ram_device = true;
4a2e242b
AW
1466 mr->ops = &ram_device_mem_ops;
1467 mr->opaque = mr;
e4dc3f59
ND
1468}
1469
093bc2cd 1470void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1471 Object *owner,
093bc2cd
AK
1472 const char *name,
1473 MemoryRegion *orig,
a8170e5e 1474 hwaddr offset,
093bc2cd
AK
1475 uint64_t size)
1476{
2c9b15ca 1477 memory_region_init(mr, owner, name, size);
093bc2cd
AK
1478 mr->alias = orig;
1479 mr->alias_offset = offset;
1480}
1481
b59821a9
PM
1482void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1483 struct Object *owner,
1484 const char *name,
1485 uint64_t size,
1486 Error **errp)
a1777f7f
PM
1487{
1488 memory_region_init(mr, owner, name, size);
1489 mr->ram = true;
1490 mr->readonly = true;
1491 mr->terminates = true;
1492 mr->destructor = memory_region_destructor_ram;
1493 mr->ram_block = qemu_ram_alloc(size, mr, errp);
1494 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1495}
1496
b59821a9
PM
1497void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1498 Object *owner,
1499 const MemoryRegionOps *ops,
1500 void *opaque,
1501 const char *name,
1502 uint64_t size,
1503 Error **errp)
d0a9b5bc 1504{
39e0b03d 1505 assert(ops);
2c9b15ca 1506 memory_region_init(mr, owner, name, size);
7bc2b9cd 1507 mr->ops = ops;
75f5941c 1508 mr->opaque = opaque;
d0a9b5bc 1509 mr->terminates = true;
75c578dc 1510 mr->rom_device = true;
58268c8d 1511 mr->destructor = memory_region_destructor_ram;
8e41fb63 1512 mr->ram_block = qemu_ram_alloc(size, mr, errp);
d0a9b5bc
AK
1513}
1514
1221a474
AK
1515void memory_region_init_iommu(void *_iommu_mr,
1516 size_t instance_size,
1517 const char *mrtypename,
2c9b15ca 1518 Object *owner,
30951157
AK
1519 const char *name,
1520 uint64_t size)
1521{
1221a474 1522 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK
1523 struct MemoryRegion *mr;
1524
1221a474
AK
1525 object_initialize(_iommu_mr, instance_size, mrtypename);
1526 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK
1527 memory_region_do_init(mr, owner, name, size);
1528 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1529 mr->terminates = true; /* then re-forwards */
3df9d748
AK
1530 QLIST_INIT(&iommu_mr->iommu_notify);
1531 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK
1532}
1533
b4fefef9 1534static void memory_region_finalize(Object *obj)
093bc2cd 1535{
b4fefef9
PC
1536 MemoryRegion *mr = MEMORY_REGION(obj);
1537
2e2b8eb7
PB
1538 assert(!mr->container);
1539
1540 /* We know the region is not visible in any address space (it
1541 * does not have a container and cannot be a root either because
1542 * it has no references, so we can blindly clear mr->enabled.
1543 * memory_region_set_enabled instead could trigger a transaction
1544 * and cause an infinite loop.
1545 */
1546 mr->enabled = false;
1547 memory_region_transaction_begin();
1548 while (!QTAILQ_EMPTY(&mr->subregions)) {
1549 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1550 memory_region_del_subregion(mr, subregion);
1551 }
1552 memory_region_transaction_commit();
1553
545e92e0 1554 mr->destructor(mr);
093bc2cd 1555 memory_region_clear_coalescing(mr);
302fa283 1556 g_free((char *)mr->name);
7267c094 1557 g_free(mr->ioeventfds);
093bc2cd
AK
1558}
1559
803c0816
PB
1560Object *memory_region_owner(MemoryRegion *mr)
1561{
22a893e4
PB
1562 Object *obj = OBJECT(mr);
1563 return obj->parent;
803c0816
PB
1564}
1565
46637be2
PB
1566void memory_region_ref(MemoryRegion *mr)
1567{
22a893e4
PB
1568 /* MMIO callbacks most likely will access data that belongs
1569 * to the owner, hence the need to ref/unref the owner whenever
1570 * the memory region is in use.
1571 *
1572 * The memory region is a child of its owner. As long as the
1573 * owner doesn't call unparent itself on the memory region,
1574 * ref-ing the owner will also keep the memory region alive.
612263cf
PB
1575 * Memory regions without an owner are supposed to never go away;
1576 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1577 */
612263cf
PB
1578 if (mr && mr->owner) {
1579 object_ref(mr->owner);
46637be2
PB
1580 }
1581}
1582
1583void memory_region_unref(MemoryRegion *mr)
1584{
612263cf
PB
1585 if (mr && mr->owner) {
1586 object_unref(mr->owner);
46637be2
PB
1587 }
1588}
1589
093bc2cd
AK
1590uint64_t memory_region_size(MemoryRegion *mr)
1591{
08dafab4
AK
1592 if (int128_eq(mr->size, int128_2_64())) {
1593 return UINT64_MAX;
1594 }
1595 return int128_get64(mr->size);
093bc2cd
AK
1596}
1597
5d546d4b 1598const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1599{
d1dd32af
PC
1600 if (!mr->name) {
1601 ((MemoryRegion *)mr)->name =
1602 object_get_canonical_path_component(OBJECT(mr));
1603 }
302fa283 1604 return mr->name;
8991c79b
AK
1605}
1606
21e00fa5 1607bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1608{
21e00fa5 1609 return mr->ram_device;
e4dc3f59
ND
1610}
1611
2d1a35be 1612uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1613{
6f6a5ef3 1614 uint8_t mask = mr->dirty_log_mask;
adaad61c 1615 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB
1616 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1617 }
1618 return mask;
55043ba3
AK
1619}
1620
2d1a35be
PB
1621bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1622{
1623 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1624}
1625
3df9d748 1626static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
5bf3d319
PX
1627{
1628 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1629 IOMMUNotifier *iommu_notifier;
1221a474 1630 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
5bf3d319 1631
3df9d748 1632 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX
1633 flags |= iommu_notifier->notifier_flags;
1634 }
1635
1221a474
AK
1636 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1637 imrc->notify_flag_changed(iommu_mr,
1638 iommu_mr->iommu_notify_flags,
1639 flags);
5bf3d319
PX
1640 }
1641
3df9d748 1642 iommu_mr->iommu_notify_flags = flags;
5bf3d319
PX
1643}
1644
cdb30812
PX
1645void memory_region_register_iommu_notifier(MemoryRegion *mr,
1646 IOMMUNotifier *n)
06866575 1647{
3df9d748
AK
1648 IOMMUMemoryRegion *iommu_mr;
1649
efcd38c5
JW
1650 if (mr->alias) {
1651 memory_region_register_iommu_notifier(mr->alias, n);
1652 return;
1653 }
1654
cdb30812 1655 /* We need to register for at least one bitfield */
3df9d748 1656 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1657 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1658 assert(n->start <= n->end);
3df9d748
AK
1659 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1660 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1661}
1662
3df9d748 1663uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1664{
1221a474
AK
1665 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1666
1667 if (imrc->get_min_page_size) {
1668 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK
1669 }
1670 return TARGET_PAGE_SIZE;
1671}
1672
3df9d748 1673void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1674{
3df9d748 1675 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1676 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1677 hwaddr addr, granularity;
a788f227
DG
1678 IOMMUTLBEntry iotlb;
1679
faa362e3 1680 /* If the IOMMU has its own replay callback, override */
1221a474
AK
1681 if (imrc->replay) {
1682 imrc->replay(iommu_mr, n);
faa362e3
PX
1683 return;
1684 }
1685
3df9d748 1686 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1687
a788f227 1688 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1221a474 1689 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE);
a788f227
DG
1690 if (iotlb.perm != IOMMU_NONE) {
1691 n->notify(n, &iotlb);
1692 }
1693
1694 /* if (2^64 - MR size) < granularity, it's possible to get an
1695 * infinite loop here. This should catch such a wraparound */
1696 if ((addr + granularity) < addr) {
1697 break;
1698 }
1699 }
1700}
1701
3df9d748 1702void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
de472e4a
PX
1703{
1704 IOMMUNotifier *notifier;
1705
3df9d748
AK
1706 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1707 memory_region_iommu_replay(iommu_mr, notifier);
de472e4a
PX
1708 }
1709}
1710
cdb30812
PX
1711void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1712 IOMMUNotifier *n)
06866575 1713{
3df9d748
AK
1714 IOMMUMemoryRegion *iommu_mr;
1715
efcd38c5
JW
1716 if (mr->alias) {
1717 memory_region_unregister_iommu_notifier(mr->alias, n);
1718 return;
1719 }
cdb30812 1720 QLIST_REMOVE(n, node);
3df9d748
AK
1721 iommu_mr = IOMMU_MEMORY_REGION(mr);
1722 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1723}
1724
bd2bfa4c
PX
1725void memory_region_notify_one(IOMMUNotifier *notifier,
1726 IOMMUTLBEntry *entry)
06866575 1727{
cdb30812
PX
1728 IOMMUNotifierFlag request_flags;
1729
bd2bfa4c
PX
1730 /*
1731 * Skip the notification if the notification does not overlap
1732 * with registered range.
1733 */
1734 if (notifier->start > entry->iova + entry->addr_mask + 1 ||
1735 notifier->end < entry->iova) {
1736 return;
1737 }
cdb30812 1738
bd2bfa4c 1739 if (entry->perm & IOMMU_RW) {
cdb30812
PX
1740 request_flags = IOMMU_NOTIFIER_MAP;
1741 } else {
1742 request_flags = IOMMU_NOTIFIER_UNMAP;
1743 }
1744
bd2bfa4c
PX
1745 if (notifier->notifier_flags & request_flags) {
1746 notifier->notify(notifier, entry);
1747 }
1748}
1749
3df9d748 1750void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
bd2bfa4c
PX
1751 IOMMUTLBEntry entry)
1752{
1753 IOMMUNotifier *iommu_notifier;
1754
3df9d748 1755 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1756
3df9d748 1757 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
bd2bfa4c 1758 memory_region_notify_one(iommu_notifier, &entry);
cdb30812 1759 }
06866575
DG
1760}
1761
093bc2cd
AK
1762void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1763{
5a583347 1764 uint8_t mask = 1 << client;
deb809ed 1765 uint8_t old_logging;
5a583347 1766
dbddac6d 1767 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB
1768 old_logging = mr->vga_logging_count;
1769 mr->vga_logging_count += log ? 1 : -1;
1770 if (!!old_logging == !!mr->vga_logging_count) {
1771 return;
1772 }
1773
59023ef4 1774 memory_region_transaction_begin();
5a583347 1775 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1776 memory_region_update_pending |= mr->enabled;
59023ef4 1777 memory_region_transaction_commit();
093bc2cd
AK
1778}
1779
a8170e5e
AK
1780bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1781 hwaddr size, unsigned client)
093bc2cd 1782{
8e41fb63
FZ
1783 assert(mr->ram_block);
1784 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1785 size, client);
093bc2cd
AK
1786}
1787
a8170e5e
AK
1788void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1789 hwaddr size)
093bc2cd 1790{
8e41fb63
FZ
1791 assert(mr->ram_block);
1792 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1793 size,
58d2707e 1794 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK
1795}
1796
6c279db8
JQ
1797bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1798 hwaddr size, unsigned client)
1799{
8e41fb63
FZ
1800 assert(mr->ram_block);
1801 return cpu_physical_memory_test_and_clear_dirty(
1802 memory_region_get_ram_addr(mr) + addr, size, client);
6c279db8
JQ
1803}
1804
8deaf12c
GH
1805DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
1806 hwaddr addr,
1807 hwaddr size,
1808 unsigned client)
1809{
1810 assert(mr->ram_block);
1811 return cpu_physical_memory_snapshot_and_clear_dirty(
1812 memory_region_get_ram_addr(mr) + addr, size, client);
1813}
1814
1815bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
1816 hwaddr addr, hwaddr size)
1817{
1818 assert(mr->ram_block);
1819 return cpu_physical_memory_snapshot_get_dirty(snap,
1820 memory_region_get_ram_addr(mr) + addr, size);
1821}
6c279db8 1822
093bc2cd
AK
1823void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1824{
0a752eee 1825 MemoryListener *listener;
0d673e36 1826 AddressSpace *as;
0a752eee 1827 FlatView *view;
5a583347
AK
1828 FlatRange *fr;
1829
0a752eee
PB
1830 /* If the same address space has multiple log_sync listeners, we
1831 * visit that address space's FlatView multiple times. But because
1832 * log_sync listeners are rare, it's still cheaper than walking each
1833 * address space once.
1834 */
1835 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1836 if (!listener->log_sync) {
1837 continue;
1838 }
1839 as = listener->address_space;
1840 view = address_space_get_flatview(as);
99e86347 1841 FOR_EACH_FLAT_RANGE(fr, view) {
0d673e36 1842 if (fr->mr == mr) {
0a752eee
PB
1843 MemoryRegionSection mrs = section_from_flat_range(fr, as);
1844 listener->log_sync(listener, &mrs);
0d673e36 1845 }
5a583347 1846 }
856d7245 1847 flatview_unref(view);
5a583347 1848 }
093bc2cd
AK
1849}
1850
1851void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1852{
fb1cd6f9 1853 if (mr->readonly != readonly) {
59023ef4 1854 memory_region_transaction_begin();
fb1cd6f9 1855 mr->readonly = readonly;
22bde714 1856 memory_region_update_pending |= mr->enabled;
59023ef4 1857 memory_region_transaction_commit();
fb1cd6f9 1858 }
093bc2cd
AK
1859}
1860
5f9a5ea1 1861void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 1862{
5f9a5ea1 1863 if (mr->romd_mode != romd_mode) {
59023ef4 1864 memory_region_transaction_begin();
5f9a5ea1 1865 mr->romd_mode = romd_mode;
22bde714 1866 memory_region_update_pending |= mr->enabled;
59023ef4 1867 memory_region_transaction_commit();
d0a9b5bc
AK
1868 }
1869}
1870
a8170e5e
AK
1871void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
1872 hwaddr size, unsigned client)
093bc2cd 1873{
8e41fb63
FZ
1874 assert(mr->ram_block);
1875 cpu_physical_memory_test_and_clear_dirty(
1876 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK
1877}
1878
a35ba7be
PB
1879int memory_region_get_fd(MemoryRegion *mr)
1880{
4ff87573
PB
1881 int fd;
1882
1883 rcu_read_lock();
1884 while (mr->alias) {
1885 mr = mr->alias;
a35ba7be 1886 }
4ff87573
PB
1887 fd = mr->ram_block->fd;
1888 rcu_read_unlock();
a35ba7be 1889
4ff87573
PB
1890 return fd;
1891}
a35ba7be 1892
093bc2cd
AK
1893void *memory_region_get_ram_ptr(MemoryRegion *mr)
1894{
49b24afc
PB
1895 void *ptr;
1896 uint64_t offset = 0;
093bc2cd 1897
49b24afc
PB
1898 rcu_read_lock();
1899 while (mr->alias) {
1900 offset += mr->alias_offset;
1901 mr = mr->alias;
1902 }
8e41fb63 1903 assert(mr->ram_block);
0878d0e1 1904 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
49b24afc 1905 rcu_read_unlock();
093bc2cd 1906
0878d0e1 1907 return ptr;
093bc2cd
AK
1908}
1909
07bdaa41
PB
1910MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
1911{
1912 RAMBlock *block;
1913
1914 block = qemu_ram_block_from_host(ptr, false, offset);
1915 if (!block) {
1916 return NULL;
1917 }
1918
1919 return block->mr;
1920}
1921
7ebb2745
FZ
1922ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
1923{
1924 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
1925}
1926
37d7c084
PB
1927void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
1928{
8e41fb63 1929 assert(mr->ram_block);
37d7c084 1930
fa53a0e5 1931 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB
1932}
1933
0d673e36 1934static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 1935{
99e86347 1936 FlatView *view;
093bc2cd
AK
1937 FlatRange *fr;
1938 CoalescedMemoryRange *cmr;
1939 AddrRange tmp;
95d2994a 1940 MemoryRegionSection section;
093bc2cd 1941
856d7245 1942 view = address_space_get_flatview(as);
99e86347 1943 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 1944 if (fr->mr == mr) {
95d2994a 1945 section = (MemoryRegionSection) {
f6790af6 1946 .address_space = as,
95d2994a 1947 .offset_within_address_space = int128_get64(fr->addr.start),
052e87b0 1948 .size = fr->addr.size,
95d2994a
AK
1949 };
1950
9a54635d 1951 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
95d2994a
AK
1952 int128_get64(fr->addr.start),
1953 int128_get64(fr->addr.size));
093bc2cd
AK
1954 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
1955 tmp = addrrange_shift(cmr->addr,
08dafab4
AK
1956 int128_sub(fr->addr.start,
1957 int128_make64(fr->offset_in_region)));
093bc2cd
AK
1958 if (!addrrange_intersects(tmp, fr->addr)) {
1959 continue;
1960 }
1961 tmp = addrrange_intersection(tmp, fr->addr);
9a54635d 1962 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
95d2994a
AK
1963 int128_get64(tmp.start),
1964 int128_get64(tmp.size));
093bc2cd
AK
1965 }
1966 }
1967 }
856d7245 1968 flatview_unref(view);
093bc2cd
AK
1969}
1970
0d673e36
AK
1971static void memory_region_update_coalesced_range(MemoryRegion *mr)
1972{
1973 AddressSpace *as;
1974
1975 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1976 memory_region_update_coalesced_range_as(mr, as);
1977 }
1978}
1979
093bc2cd
AK
1980void memory_region_set_coalescing(MemoryRegion *mr)
1981{
1982 memory_region_clear_coalescing(mr);
08dafab4 1983 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK
1984}
1985
1986void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 1987 hwaddr offset,
093bc2cd
AK
1988 uint64_t size)
1989{
7267c094 1990 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 1991
08dafab4 1992 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK
1993 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
1994 memory_region_update_coalesced_range(mr);
d410515e 1995 memory_region_set_flush_coalesced(mr);
093bc2cd
AK
1996}
1997
1998void memory_region_clear_coalescing(MemoryRegion *mr)
1999{
2000 CoalescedMemoryRange *cmr;
ab5b3db5 2001 bool updated = false;
093bc2cd 2002
d410515e
JK
2003 qemu_flush_coalesced_mmio_buffer();
2004 mr->flush_coalesced_mmio = false;
2005
093bc2cd
AK
2006 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2007 cmr = QTAILQ_FIRST(&mr->coalesced);
2008 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 2009 g_free(cmr);
ab5b3db5
FZ
2010 updated = true;
2011 }
2012
2013 if (updated) {
2014 memory_region_update_coalesced_range(mr);
093bc2cd 2015 }
093bc2cd
AK
2016}
2017
d410515e
JK
2018void memory_region_set_flush_coalesced(MemoryRegion *mr)
2019{
2020 mr->flush_coalesced_mmio = true;
2021}
2022
2023void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2024{
2025 qemu_flush_coalesced_mmio_buffer();
2026 if (QTAILQ_EMPTY(&mr->coalesced)) {
2027 mr->flush_coalesced_mmio = false;
2028 }
2029}
2030
196ea131
JK
2031void memory_region_set_global_locking(MemoryRegion *mr)
2032{
2033 mr->global_locking = true;
2034}
2035
2036void memory_region_clear_global_locking(MemoryRegion *mr)
2037{
2038 mr->global_locking = false;
2039}
2040
8c56c1a5
PF
2041static bool userspace_eventfd_warning;
2042
3e9d69e7 2043void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2044 hwaddr addr,
3e9d69e7
AK
2045 unsigned size,
2046 bool match_data,
2047 uint64_t data,
753d5e14 2048 EventNotifier *e)
3e9d69e7
AK
2049{
2050 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2051 .addr.start = int128_make64(addr),
2052 .addr.size = int128_make64(size),
3e9d69e7
AK
2053 .match_data = match_data,
2054 .data = data,
753d5e14 2055 .e = e,
3e9d69e7
AK
2056 };
2057 unsigned i;
2058
8c56c1a5
PF
2059 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2060 userspace_eventfd_warning))) {
2061 userspace_eventfd_warning = true;
2062 error_report("Using eventfd without MMIO binding in KVM. "
2063 "Suboptimal performance expected");
2064 }
2065
b8aecea2
JW
2066 if (size) {
2067 adjust_endianness(mr, &mrfd.data, size);
2068 }
59023ef4 2069 memory_region_transaction_begin();
3e9d69e7
AK
2070 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2071 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
2072 break;
2073 }
2074 }
2075 ++mr->ioeventfd_nb;
7267c094 2076 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK
2077 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2078 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2079 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2080 mr->ioeventfds[i] = mrfd;
4dc56152 2081 ioeventfd_update_pending |= mr->enabled;
59023ef4 2082 memory_region_transaction_commit();
3e9d69e7
AK
2083}
2084
2085void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2086 hwaddr addr,
3e9d69e7
AK
2087 unsigned size,
2088 bool match_data,
2089 uint64_t data,
753d5e14 2090 EventNotifier *e)
3e9d69e7
AK
2091{
2092 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2093 .addr.start = int128_make64(addr),
2094 .addr.size = int128_make64(size),
3e9d69e7
AK
2095 .match_data = match_data,
2096 .data = data,
753d5e14 2097 .e = e,
3e9d69e7
AK
2098 };
2099 unsigned i;
2100
b8aecea2
JW
2101 if (size) {
2102 adjust_endianness(mr, &mrfd.data, size);
2103 }
59023ef4 2104 memory_region_transaction_begin();
3e9d69e7
AK
2105 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2106 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
2107 break;
2108 }
2109 }
2110 assert(i != mr->ioeventfd_nb);
2111 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2112 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2113 --mr->ioeventfd_nb;
7267c094 2114 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2115 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2116 ioeventfd_update_pending |= mr->enabled;
59023ef4 2117 memory_region_transaction_commit();
3e9d69e7
AK
2118}
2119
feca4ac1 2120static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2121{
feca4ac1 2122 MemoryRegion *mr = subregion->container;
093bc2cd
AK
2123 MemoryRegion *other;
2124
59023ef4
JK
2125 memory_region_transaction_begin();
2126
dfde4e6e 2127 memory_region_ref(subregion);
093bc2cd
AK
2128 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2129 if (subregion->priority >= other->priority) {
2130 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2131 goto done;
2132 }
2133 }
2134 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2135done:
22bde714 2136 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2137 memory_region_transaction_commit();
093bc2cd
AK
2138}
2139
0598701a
PC
2140static void memory_region_add_subregion_common(MemoryRegion *mr,
2141 hwaddr offset,
2142 MemoryRegion *subregion)
2143{
feca4ac1
PB
2144 assert(!subregion->container);
2145 subregion->container = mr;
0598701a 2146 subregion->addr = offset;
feca4ac1 2147 memory_region_update_container_subregions(subregion);
0598701a 2148}
093bc2cd
AK
2149
2150void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2151 hwaddr offset,
093bc2cd
AK
2152 MemoryRegion *subregion)
2153{
093bc2cd
AK
2154 subregion->priority = 0;
2155 memory_region_add_subregion_common(mr, offset, subregion);
2156}
2157
2158void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2159 hwaddr offset,
093bc2cd 2160 MemoryRegion *subregion,
a1ff8ae0 2161 int priority)
093bc2cd 2162{
093bc2cd
AK
2163 subregion->priority = priority;
2164 memory_region_add_subregion_common(mr, offset, subregion);
2165}
2166
2167void memory_region_del_subregion(MemoryRegion *mr,
2168 MemoryRegion *subregion)
2169{
59023ef4 2170 memory_region_transaction_begin();
feca4ac1
PB
2171 assert(subregion->container == mr);
2172 subregion->container = NULL;
093bc2cd 2173 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2174 memory_region_unref(subregion);
22bde714 2175 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2176 memory_region_transaction_commit();
6bba19ba
AK
2177}
2178
2179void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2180{
2181 if (enabled == mr->enabled) {
2182 return;
2183 }
59023ef4 2184 memory_region_transaction_begin();
6bba19ba 2185 mr->enabled = enabled;
22bde714 2186 memory_region_update_pending = true;
59023ef4 2187 memory_region_transaction_commit();
093bc2cd 2188}
1c0ffa58 2189
e7af4c67
MT
2190void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2191{
2192 Int128 s = int128_make64(size);
2193
2194 if (size == UINT64_MAX) {
2195 s = int128_2_64();
2196 }
2197 if (int128_eq(s, mr->size)) {
2198 return;
2199 }
2200 memory_region_transaction_begin();
2201 mr->size = s;
2202 memory_region_update_pending = true;
2203 memory_region_transaction_commit();
2204}
2205
67891b8a 2206static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2207{
feca4ac1 2208 MemoryRegion *container = mr->container;
2282e1af 2209
feca4ac1 2210 if (container) {
67891b8a
PC
2211 memory_region_transaction_begin();
2212 memory_region_ref(mr);
feca4ac1
PB
2213 memory_region_del_subregion(container, mr);
2214 mr->container = container;
2215 memory_region_update_container_subregions(mr);
67891b8a
PC
2216 memory_region_unref(mr);
2217 memory_region_transaction_commit();
2282e1af 2218 }
67891b8a 2219}
2282e1af 2220
67891b8a
PC
2221void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2222{
2223 if (addr != mr->addr) {
2224 mr->addr = addr;
2225 memory_region_readd_subregion(mr);
2226 }
2282e1af
AK
2227}
2228
a8170e5e 2229void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2230{
4703359e 2231 assert(mr->alias);
4703359e 2232
59023ef4 2233 if (offset == mr->alias_offset) {
4703359e
AK
2234 return;
2235 }
2236
59023ef4
JK
2237 memory_region_transaction_begin();
2238 mr->alias_offset = offset;
22bde714 2239 memory_region_update_pending |= mr->enabled;
59023ef4 2240 memory_region_transaction_commit();
4703359e
AK
2241}
2242
a2b257d6
IM
2243uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2244{
2245 return mr->align;
2246}
2247
e2177955
AK
2248static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2249{
2250 const AddrRange *addr = addr_;
2251 const FlatRange *fr = fr_;
2252
2253 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2254 return -1;
2255 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2256 return 1;
2257 }
2258 return 0;
2259}
2260
99e86347 2261static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2262{
99e86347 2263 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK
2264 sizeof(FlatRange), cmp_flatrange_addr);
2265}
2266
eed2bacf
IM
2267bool memory_region_is_mapped(MemoryRegion *mr)
2268{
2269 return mr->container ? true : false;
2270}
2271
c6742b14
PB
2272/* Same as memory_region_find, but it does not add a reference to the
2273 * returned region. It must be called from an RCU critical section.
2274 */
2275static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2276 hwaddr addr, uint64_t size)
e2177955 2277{
052e87b0 2278 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB
2279 MemoryRegion *root;
2280 AddressSpace *as;
2281 AddrRange range;
99e86347 2282 FlatView *view;
73034e9e
PB
2283 FlatRange *fr;
2284
2285 addr += mr->addr;
feca4ac1
PB
2286 for (root = mr; root->container; ) {
2287 root = root->container;
73034e9e
PB
2288 addr += root->addr;
2289 }
e2177955 2290
73034e9e 2291 as = memory_region_to_address_space(root);
eed2bacf
IM
2292 if (!as) {
2293 return ret;
2294 }
73034e9e 2295 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2296
2b647668 2297 view = atomic_rcu_read(&as->current_map);
99e86347 2298 fr = flatview_lookup(view, range);
e2177955 2299 if (!fr) {
c6742b14 2300 return ret;
e2177955
AK
2301 }
2302
99e86347 2303 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK
2304 --fr;
2305 }
2306
2307 ret.mr = fr->mr;
73034e9e 2308 ret.address_space = as;
e2177955
AK
2309 range = addrrange_intersection(range, fr->addr);
2310 ret.offset_within_region = fr->offset_in_region;
2311 ret.offset_within_region += int128_get64(int128_sub(range.start,
2312 fr->addr.start));
052e87b0 2313 ret.size = range.size;
e2177955 2314 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2315 ret.readonly = fr->readonly;
c6742b14
PB
2316 return ret;
2317}
2318
2319MemoryRegionSection memory_region_find(MemoryRegion *mr,
2320 hwaddr addr, uint64_t size)
2321{
2322 MemoryRegionSection ret;
2323 rcu_read_lock();
2324 ret = memory_region_find_rcu(mr, addr, size);
2325 if (ret.mr) {
2326 memory_region_ref(ret.mr);
2327 }
2b647668 2328 rcu_read_unlock();
e2177955
AK
2329 return ret;
2330}
2331
c6742b14
PB
2332bool memory_region_present(MemoryRegion *container, hwaddr addr)
2333{
2334 MemoryRegion *mr;
2335
2336 rcu_read_lock();
2337 mr = memory_region_find_rcu(container, addr, 1).mr;
2338 rcu_read_unlock();
2339 return mr && mr != container;
2340}
2341
9c1f8f44 2342void memory_global_dirty_log_sync(void)
86e775c6 2343{
9c1f8f44
PB
2344 MemoryListener *listener;
2345 AddressSpace *as;
99e86347 2346 FlatView *view;
7664e80c
AK
2347 FlatRange *fr;
2348
9c1f8f44
PB
2349 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2350 if (!listener->log_sync) {
2351 continue;
2352 }
d45fa784 2353 as = listener->address_space;
9c1f8f44
PB
2354 view = address_space_get_flatview(as);
2355 FOR_EACH_FLAT_RANGE(fr, view) {
adaad61c
PB
2356 if (fr->dirty_log_mask) {
2357 MemoryRegionSection mrs = section_from_flat_range(fr, as);
2358 listener->log_sync(listener, &mrs);
2359 }
9c1f8f44
PB
2360 }
2361 flatview_unref(view);
7664e80c
AK
2362 }
2363}
2364
19310760
JZ
2365static VMChangeStateEntry *vmstate_change;
2366
7664e80c
AK
2367void memory_global_dirty_log_start(void)
2368{
19310760
JZ
2369 if (vmstate_change) {
2370 qemu_del_vm_change_state_handler(vmstate_change);
2371 vmstate_change = NULL;
2372 }
2373
7664e80c 2374 global_dirty_log = true;
6f6a5ef3 2375
7376e582 2376 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3
PB
2377
2378 /* Refresh DIRTY_LOG_MIGRATION bit. */
2379 memory_region_transaction_begin();
2380 memory_region_update_pending = true;
2381 memory_region_transaction_commit();
7664e80c
AK
2382}
2383
19310760 2384static void memory_global_dirty_log_do_stop(void)
7664e80c 2385{
7664e80c 2386 global_dirty_log = false;
6f6a5ef3
PB
2387
2388 /* Refresh DIRTY_LOG_MIGRATION bit. */
2389 memory_region_transaction_begin();
2390 memory_region_update_pending = true;
2391 memory_region_transaction_commit();
2392
7376e582 2393 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK
2394}
2395
19310760
JZ
2396static void memory_vm_change_state_handler(void *opaque, int running,
2397 RunState state)
2398{
2399 if (running) {
2400 memory_global_dirty_log_do_stop();
2401
2402 if (vmstate_change) {
2403 qemu_del_vm_change_state_handler(vmstate_change);
2404 vmstate_change = NULL;
2405 }
2406 }
2407}
2408
2409void memory_global_dirty_log_stop(void)
2410{
2411 if (!runstate_is_running()) {
2412 if (vmstate_change) {
2413 return;
2414 }
2415 vmstate_change = qemu_add_vm_change_state_handler(
2416 memory_vm_change_state_handler, NULL);
2417 return;
2418 }
2419
2420 memory_global_dirty_log_do_stop();
2421}
2422
7664e80c
AK
2423static void listener_add_address_space(MemoryListener *listener,
2424 AddressSpace *as)
2425{
99e86347 2426 FlatView *view;
7664e80c
AK
2427 FlatRange *fr;
2428
680a4783
PB
2429 if (listener->begin) {
2430 listener->begin(listener);
2431 }
7664e80c 2432 if (global_dirty_log) {
975aefe0
AK
2433 if (listener->log_global_start) {
2434 listener->log_global_start(listener);
2435 }
7664e80c 2436 }
975aefe0 2437
856d7245 2438 view = address_space_get_flatview(as);
99e86347 2439 FOR_EACH_FLAT_RANGE(fr, view) {
7664e80c
AK
2440 MemoryRegionSection section = {
2441 .mr = fr->mr,
f6790af6 2442 .address_space = as,
7664e80c 2443 .offset_within_region = fr->offset_in_region,
052e87b0 2444 .size = fr->addr.size,
7664e80c 2445 .offset_within_address_space = int128_get64(fr->addr.start),
7a8499e8 2446 .readonly = fr->readonly,
7664e80c 2447 };
680a4783
PB
2448 if (fr->dirty_log_mask && listener->log_start) {
2449 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2450 }
975aefe0
AK
2451 if (listener->region_add) {
2452 listener->region_add(listener, &section);
2453 }
7664e80c 2454 }
680a4783
PB
2455 if (listener->commit) {
2456 listener->commit(listener);
2457 }
856d7245 2458 flatview_unref(view);
7664e80c
AK
2459}
2460
d45fa784 2461void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2462{
72e22d2f
AK
2463 MemoryListener *other = NULL;
2464
d45fa784 2465 listener->address_space = as;
72e22d2f
AK
2466 if (QTAILQ_EMPTY(&memory_listeners)
2467 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2468 memory_listeners)->priority) {
2469 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2470 } else {
2471 QTAILQ_FOREACH(other, &memory_listeners, link) {
2472 if (listener->priority < other->priority) {
2473 break;
2474 }
2475 }
2476 QTAILQ_INSERT_BEFORE(other, listener, link);
2477 }
0d673e36 2478
9a54635d
PB
2479 if (QTAILQ_EMPTY(&as->listeners)
2480 || listener->priority >= QTAILQ_LAST(&as->listeners,
2481 memory_listeners)->priority) {
2482 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2483 } else {
2484 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2485 if (listener->priority < other->priority) {
2486 break;
2487 }
2488 }
2489 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2490 }
2491
d45fa784 2492 listener_add_address_space(listener, as);
7664e80c
AK
2493}
2494
2495void memory_listener_unregister(MemoryListener *listener)
2496{
1d8280c1
PB
2497 if (!listener->address_space) {
2498 return;
2499 }
2500
72e22d2f 2501 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2502 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2503 listener->address_space = NULL;
86e775c6 2504}
e2177955 2505
c9356746
FK
2506bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2507{
2508 void *host;
2509 unsigned size = 0;
2510 unsigned offset = 0;
2511 Object *new_interface;
2512
2513 if (!mr || !mr->ops->request_ptr) {
2514 return false;
2515 }
2516
2517 /*
2518 * Avoid an update if the request_ptr call
2519 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2520 * a cache.
2521 */
2522 memory_region_transaction_begin();
2523
2524 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2525
2526 if (!host || !size) {
2527 memory_region_transaction_commit();
2528 return false;
2529 }
2530
2531 new_interface = object_new("mmio_interface");
2532 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2533 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2534 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2535 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2536 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2537 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2538
2539 memory_region_transaction_commit();
2540 return true;
2541}
2542
2543typedef struct MMIOPtrInvalidate {
2544 MemoryRegion *mr;
2545 hwaddr offset;
2546 unsigned size;
2547 int busy;
2548 int allocated;
2549} MMIOPtrInvalidate;
2550
2551#define MAX_MMIO_INVALIDATE 10
2552static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2553
2554static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2555 run_on_cpu_data data)
2556{
2557 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2558 MemoryRegion *mr = invalidate_data->mr;
2559 hwaddr offset = invalidate_data->offset;
2560 unsigned size = invalidate_data->size;
2561 MemoryRegionSection section = memory_region_find(mr, offset, size);
2562
2563 qemu_mutex_lock_iothread();
2564
2565 /* Reset dirty so this doesn't happen later. */
2566 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2567
2568 if (section.mr != mr) {
2569 /* memory_region_find add a ref on section.mr */
2570 memory_region_unref(section.mr);
2571 if (MMIO_INTERFACE(section.mr->owner)) {
2572 /* We found the interface just drop it. */
2573 object_property_set_bool(section.mr->owner, false, "realized",
2574 NULL);
2575 object_unref(section.mr->owner);
2576 object_unparent(section.mr->owner);
2577 }
2578 }
2579
2580 qemu_mutex_unlock_iothread();
2581
2582 if (invalidate_data->allocated) {
2583 g_free(invalidate_data);
2584 } else {
2585 invalidate_data->busy = 0;
2586 }
2587}
2588
2589void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2590 unsigned size)
2591{
2592 size_t i;
2593 MMIOPtrInvalidate *invalidate_data = NULL;
2594
2595 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2596 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2597 invalidate_data = &mmio_ptr_invalidate_list[i];
2598 break;
2599 }
2600 }
2601
2602 if (!invalidate_data) {
2603 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2604 invalidate_data->allocated = 1;
2605 }
2606
2607 invalidate_data->mr = mr;
2608 invalidate_data->offset = offset;
2609 invalidate_data->size = size;
2610
2611 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2612 RUN_ON_CPU_HOST_PTR(invalidate_data));
2613}
2614
7dca8043 2615void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2616{
ac95190e 2617 memory_region_ref(root);
59023ef4 2618 memory_region_transaction_begin();
f0c02d15 2619 as->ref_count = 1;
8786db7c 2620 as->root = root;
f0c02d15 2621 as->malloced = false;
8786db7c
AK
2622 as->current_map = g_new(FlatView, 1);
2623 flatview_init(as->current_map);
4c19eb72
AK
2624 as->ioeventfd_nb = 0;
2625 as->ioeventfds = NULL;
9a54635d 2626 QTAILQ_INIT(&as->listeners);
0d673e36 2627 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2628 as->name = g_strdup(name ? name : "anonymous");
ac1970fb 2629 address_space_init_dispatch(as);
f43793c7
PB
2630 memory_region_update_pending |= root->enabled;
2631 memory_region_transaction_commit();
1c0ffa58 2632}
658b2224 2633
374f2981 2634static void do_address_space_destroy(AddressSpace *as)
83f3c251 2635{
f0c02d15 2636 bool do_free = as->malloced;
078c44f4 2637
83f3c251 2638 address_space_destroy_dispatch(as);
9a54635d 2639 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2640
856d7245 2641 flatview_unref(as->current_map);
7dca8043 2642 g_free(as->name);
4c19eb72 2643 g_free(as->ioeventfds);
ac95190e 2644 memory_region_unref(as->root);
f0c02d15
PC
2645 if (do_free) {
2646 g_free(as);
2647 }
2648}
2649
2650AddressSpace *address_space_init_shareable(MemoryRegion *root, const char *name)
2651{
2652 AddressSpace *as;
2653
2654 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2655 if (root == as->root && as->malloced) {
2656 as->ref_count++;
2657 return as;
2658 }
2659 }
2660
2661 as = g_malloc0(sizeof *as);
2662 address_space_init(as, root, name);
2663 as->malloced = true;
2664 return as;
83f3c251
AK
2665}
2666
374f2981
PB
2667void address_space_destroy(AddressSpace *as)
2668{
ac95190e
PB
2669 MemoryRegion *root = as->root;
2670
f0c02d15
PC
2671 as->ref_count--;
2672 if (as->ref_count) {
2673 return;
2674 }
374f2981
PB
2675 /* Flush out anything from MemoryListeners listening in on this */
2676 memory_region_transaction_begin();
2677 as->root = NULL;
2678 memory_region_transaction_commit();
2679 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
6e48e8f9 2680 address_space_unregister(as);
374f2981
PB
2681
2682 /* At this point, as->dispatch and as->current_map are dummy
2683 * entries that the guest should never use. Wait for the old
2684 * values to expire before freeing the data.
2685 */
ac95190e 2686 as->root = root;
374f2981
PB
2687 call_rcu(as, do_address_space_destroy, rcu);
2688}
2689
4e831901
PX
2690static const char *memory_region_type(MemoryRegion *mr)
2691{
2692 if (memory_region_is_ram_device(mr)) {
2693 return "ramd";
2694 } else if (memory_region_is_romd(mr)) {
2695 return "romd";
2696 } else if (memory_region_is_rom(mr)) {
2697 return "rom";
2698 } else if (memory_region_is_ram(mr)) {
2699 return "ram";
2700 } else {
2701 return "i/o";
2702 }
2703}
2704
314e2987
BS
2705typedef struct MemoryRegionList MemoryRegionList;
2706
2707struct MemoryRegionList {
2708 const MemoryRegion *mr;
a16878d2 2709 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS
2710};
2711
a16878d2 2712typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
314e2987 2713
4e831901
PX
2714#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2715 int128_sub((size), int128_one())) : 0)
2716#define MTREE_INDENT " "
2717
314e2987
BS
2718static void mtree_print_mr(fprintf_function mon_printf, void *f,
2719 const MemoryRegion *mr, unsigned int level,
a8170e5e 2720 hwaddr base,
9479c57a 2721 MemoryRegionListHead *alias_print_queue)
314e2987 2722{
9479c57a
JK
2723 MemoryRegionList *new_ml, *ml, *next_ml;
2724 MemoryRegionListHead submr_print_queue;
314e2987
BS
2725 const MemoryRegion *submr;
2726 unsigned int i;
b31f8412 2727 hwaddr cur_start, cur_end;
314e2987 2728
f8a9f720 2729 if (!mr) {
314e2987
BS
2730 return;
2731 }
2732
2733 for (i = 0; i < level; i++) {
4e831901 2734 mon_printf(f, MTREE_INDENT);
314e2987
BS
2735 }
2736
b31f8412
PX
2737 cur_start = base + mr->addr;
2738 cur_end = cur_start + MR_SIZE(mr->size);
2739
2740 /*
2741 * Try to detect overflow of memory region. This should never
2742 * happen normally. When it happens, we dump something to warn the
2743 * user who is observing this.
2744 */
2745 if (cur_start < base || cur_end < cur_start) {
2746 mon_printf(f, "[DETECTED OVERFLOW!] ");
2747 }
2748
314e2987
BS
2749 if (mr->alias) {
2750 MemoryRegionList *ml;
2751 bool found = false;
2752
2753 /* check if the alias is already in the queue */
a16878d2 2754 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2755 if (ml->mr == mr->alias) {
314e2987
BS
2756 found = true;
2757 }
2758 }
2759
2760 if (!found) {
2761 ml = g_new(MemoryRegionList, 1);
2762 ml->mr = mr->alias;
a16878d2 2763 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2764 }
4896d74b 2765 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
4e831901 2766 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
f8a9f720 2767 "-" TARGET_FMT_plx "%s\n",
b31f8412 2768 cur_start, cur_end,
4b474ba7 2769 mr->priority,
4e831901 2770 memory_region_type((MemoryRegion *)mr),
3fb18b4d
PC
2771 memory_region_name(mr),
2772 memory_region_name(mr->alias),
314e2987 2773 mr->alias_offset,
4e831901 2774 mr->alias_offset + MR_SIZE(mr->size),
f8a9f720 2775 mr->enabled ? "" : " [disabled]");
314e2987 2776 } else {
4896d74b 2777 mon_printf(f,
4e831901 2778 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
b31f8412 2779 cur_start, cur_end,
4b474ba7 2780 mr->priority,
4e831901 2781 memory_region_type((MemoryRegion *)mr),
f8a9f720
GH
2782 memory_region_name(mr),
2783 mr->enabled ? "" : " [disabled]");
314e2987 2784 }
9479c57a
JK
2785
2786 QTAILQ_INIT(&submr_print_queue);
2787
314e2987 2788 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
2789 new_ml = g_new(MemoryRegionList, 1);
2790 new_ml->mr = submr;
a16878d2 2791 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK
2792 if (new_ml->mr->addr < ml->mr->addr ||
2793 (new_ml->mr->addr == ml->mr->addr &&
2794 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 2795 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK
2796 new_ml = NULL;
2797 break;
2798 }
2799 }
2800 if (new_ml) {
a16878d2 2801 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK
2802 }
2803 }
2804
a16878d2 2805 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b31f8412 2806 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
9479c57a
JK
2807 alias_print_queue);
2808 }
2809
a16878d2 2810 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 2811 g_free(ml);
314e2987
BS
2812 }
2813}
2814
57bb40c9
PX
2815static void mtree_print_flatview(fprintf_function p, void *f,
2816 AddressSpace *as)
2817{
2818 FlatView *view = address_space_get_flatview(as);
2819 FlatRange *range = &view->ranges[0];
2820 MemoryRegion *mr;
2821 int n = view->nr;
2822
2823 if (n <= 0) {
2824 p(f, MTREE_INDENT "No rendered FlatView for "
2825 "address space '%s'\n", as->name);
2826 flatview_unref(view);
2827 return;
2828 }
2829
2830 while (n--) {
2831 mr = range->mr;
377a07aa
PB
2832 if (range->offset_in_region) {
2833 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2834 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
2835 int128_get64(range->addr.start),
2836 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2837 mr->priority,
2838 range->readonly ? "rom" : memory_region_type(mr),
2839 memory_region_name(mr),
2840 range->offset_in_region);
2841 } else {
2842 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2843 TARGET_FMT_plx " (prio %d, %s): %s\n",
2844 int128_get64(range->addr.start),
2845 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2846 mr->priority,
2847 range->readonly ? "rom" : memory_region_type(mr),
2848 memory_region_name(mr));
2849 }
57bb40c9
PX
2850 range++;
2851 }
2852
2853 flatview_unref(view);
2854}
2855
2856void mtree_info(fprintf_function mon_printf, void *f, bool flatview)
314e2987
BS
2857{
2858 MemoryRegionListHead ml_head;
2859 MemoryRegionList *ml, *ml2;
0d673e36 2860 AddressSpace *as;
314e2987 2861
57bb40c9
PX
2862 if (flatview) {
2863 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2864 mon_printf(f, "address-space (flat view): %s\n", as->name);
2865 mtree_print_flatview(mon_printf, f, as);
2866 mon_printf(f, "\n");
2867 }
2868 return;
2869 }
2870
314e2987
BS
2871 QTAILQ_INIT(&ml_head);
2872
0d673e36 2873 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
e48816aa
GH
2874 mon_printf(f, "address-space: %s\n", as->name);
2875 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
2876 mon_printf(f, "\n");
b9f9be88
BS
2877 }
2878
314e2987 2879 /* print aliased regions */
a16878d2 2880 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
e48816aa
GH
2881 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
2882 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
2883 mon_printf(f, "\n");
314e2987
BS
2884 }
2885
a16878d2 2886 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 2887 g_free(ml);
314e2987 2888 }
314e2987 2889}
b4fefef9 2890
b08199c6
PM
2891void memory_region_init_ram(MemoryRegion *mr,
2892 struct Object *owner,
2893 const char *name,
2894 uint64_t size,
2895 Error **errp)
2896{
2897 DeviceState *owner_dev;
2898 Error *err = NULL;
2899
2900 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
2901 if (err) {
2902 error_propagate(errp, err);
2903 return;
2904 }
2905 /* This will assert if owner is neither NULL nor a DeviceState.
2906 * We only want the owner here for the purposes of defining a
2907 * unique name for migration. TODO: Ideally we should implement
2908 * a naming scheme for Objects which are not DeviceStates, in
2909 * which case we can relax this restriction.
2910 */
2911 owner_dev = DEVICE(owner);
2912 vmstate_register_ram(mr, owner_dev);
2913}
2914
2915void memory_region_init_rom(MemoryRegion *mr,
2916 struct Object *owner,
2917 const char *name,
2918 uint64_t size,
2919 Error **errp)
2920{
2921 DeviceState *owner_dev;
2922 Error *err = NULL;
2923
2924 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
2925 if (err) {
2926 error_propagate(errp, err);
2927 return;
2928 }
2929 /* This will assert if owner is neither NULL nor a DeviceState.
2930 * We only want the owner here for the purposes of defining a
2931 * unique name for migration. TODO: Ideally we should implement
2932 * a naming scheme for Objects which are not DeviceStates, in
2933 * which case we can relax this restriction.
2934 */
2935 owner_dev = DEVICE(owner);
2936 vmstate_register_ram(mr, owner_dev);
2937}
2938
2939void memory_region_init_rom_device(MemoryRegion *mr,
2940 struct Object *owner,
2941 const MemoryRegionOps *ops,
2942 void *opaque,
2943 const char *name,
2944 uint64_t size,
2945 Error **errp)
2946{
2947 DeviceState *owner_dev;
2948 Error *err = NULL;
2949
2950 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
2951 name, size, &err);
2952 if (err) {
2953 error_propagate(errp, err);
2954 return;
2955 }
2956 /* This will assert if owner is neither NULL nor a DeviceState.
2957 * We only want the owner here for the purposes of defining a
2958 * unique name for migration. TODO: Ideally we should implement
2959 * a naming scheme for Objects which are not DeviceStates, in
2960 * which case we can relax this restriction.
2961 */
2962 owner_dev = DEVICE(owner);
2963 vmstate_register_ram(mr, owner_dev);
2964}
2965
b4fefef9
PC
2966static const TypeInfo memory_region_info = {
2967 .parent = TYPE_OBJECT,
2968 .name = TYPE_MEMORY_REGION,
2969 .instance_size = sizeof(MemoryRegion),
2970 .instance_init = memory_region_initfn,
2971 .instance_finalize = memory_region_finalize,
2972};
2973
3df9d748
AK
2974static const TypeInfo iommu_memory_region_info = {
2975 .parent = TYPE_MEMORY_REGION,
2976 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 2977 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK
2978 .instance_size = sizeof(IOMMUMemoryRegion),
2979 .instance_init = iommu_memory_region_initfn,
1221a474 2980 .abstract = true,
3df9d748
AK
2981};
2982
b4fefef9
PC
2983static void memory_register_types(void)
2984{
2985 type_register_static(&memory_region_info);
3df9d748 2986 type_register_static(&iommu_memory_region_info);
b4fefef9
PC
2987}
2988
2989type_init(memory_register_types)