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migration: disallow migrate_add_blocker during migration
[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
b3946626 26#include "sysemu/hw_accel.h"
6410848b 27#include "sysemu/kvm_int.h"
1d31f66b 28#include "kvm_i386.h"
50efe82c
AS		 29#include "hyperv.h"
30
022c62cb 31#include "exec/gdbstub.h"
1de7afc9
PB		 32#include "qemu/host-utils.h"
33#include "qemu/config-file.h"
1c4a55db 34#include "qemu/error-report.h"
0d09e41a
PB		 35#include "hw/i386/pc.h"
36#include "hw/i386/apic.h"
e0723c45
PB		 37#include "hw/i386/apic_internal.h"
38#include "hw/i386/apic-msidef.h"
8b5ed7df 39#include "hw/i386/intel_iommu.h"
e1d4fb2d 40#include "hw/i386/x86-iommu.h"
50efe82c 41
022c62cb 42#include "exec/ioport.h"
73aa529a 43#include "standard-headers/asm-x86/hyperv.h"
a2cb15b0 44#include "hw/pci/pci.h"
15eafc2e 45#include "hw/pci/msi.h"
68bfd0ad 46#include "migration/migration.h"
4c663752 47#include "exec/memattrs.h"
8b5ed7df 48#include "trace.h"
05330448
AL		 49
50//#define DEBUG_KVM
51
52#ifdef DEBUG_KVM
8c0d577e 53#define DPRINTF(fmt, ...) \
05330448
AL		 54 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55#else
8c0d577e 56#define DPRINTF(fmt, ...) \
05330448
AL		 57 do { } while (0)
58#endif
59
1a03675d
GC		 60#define MSR_KVM_WALL_CLOCK 0x11
61#define MSR_KVM_SYSTEM_TIME 0x12
62
d1138251
EH		 63/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
64 * 255 kvm_msr_entry structs */
65#define MSR_BUF_SIZE 4096
d71b62a1 66
c0532a76
MT		 67#ifndef BUS_MCEERR_AR
68#define BUS_MCEERR_AR 4
69#endif
70#ifndef BUS_MCEERR_AO
71#define BUS_MCEERR_AO 5
72#endif
73
94a8d39a
JK		 74const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
75 KVM_CAP_INFO(SET_TSS_ADDR),
76 KVM_CAP_INFO(EXT_CPUID),
77 KVM_CAP_INFO(MP_STATE),
78 KVM_CAP_LAST_INFO
79};
25d2e361 80
c3a3a7d3
JK		 81static bool has_msr_star;
82static bool has_msr_hsave_pa;
c9b8f6b6 83static bool has_msr_tsc_aux;
f28558d3 84static bool has_msr_tsc_adjust;
aa82ba54 85static bool has_msr_tsc_deadline;
df67696e 86static bool has_msr_feature_control;
21e87c46 87static bool has_msr_misc_enable;
fc12d72e 88static bool has_msr_smbase;
79e9ebeb 89static bool has_msr_bndcfgs;
25d2e361 90static int lm_capable_kernel;
7bc3d711 91static bool has_msr_hv_hypercall;
f2a53c9e 92static bool has_msr_hv_crash;
744b8a94 93static bool has_msr_hv_reset;
8c145d7c 94static bool has_msr_hv_vpindex;
46eb8f98 95static bool has_msr_hv_runtime;
866eea9a 96static bool has_msr_hv_synic;
ff99aa64 97static bool has_msr_hv_stimer;
18cd2c17 98static bool has_msr_xss;
b827df58 99
0d894367
PB		 100static bool has_msr_architectural_pmu;
101static uint32_t num_architectural_pmu_counters;
102
28143b40
TH		 103static int has_xsave;
104static int has_xcrs;
105static int has_pit_state2;
106
87f8b626
AR		 107static bool has_msr_mcg_ext_ctl;
108
494e95e9
CP		 109static struct kvm_cpuid2 *cpuid_cache;
110
28143b40
TH		 111int kvm_has_pit_state2(void)
112{
113 return has_pit_state2;
114}
115
355023f2
PB		 116bool kvm_has_smm(void)
117{
118 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
119}
120
6053a86f
MT		 121bool kvm_has_adjust_clock_stable(void)
122{
123 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
124
125 return (ret == KVM_CLOCK_TSC_STABLE);
126}
127
1d31f66b
PM		 128bool kvm_allows_irq0_override(void)
129{
130 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
131}
132
fb506e70
RK		 133static bool kvm_x2apic_api_set_flags(uint64_t flags)
134{
135 KVMState *s = KVM_STATE(current_machine->accelerator);
136
137 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
138}
139
e391c009 140#define MEMORIZE(fn, _result) \
2a138ec3 141 ({ \
2a138ec3
RK		 142 static bool _memorized; \
143 \
144 if (_memorized) { \
145 return _result; \
146 } \
147 _memorized = true; \
148 _result = fn; \
149 })
150
e391c009
IM		 151static bool has_x2apic_api;
152
153bool kvm_has_x2apic_api(void)
154{
155 return has_x2apic_api;
156}
157
fb506e70
RK		 158bool kvm_enable_x2apic(void)
159{
2a138ec3
RK		 160 return MEMORIZE(
161 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 162 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
163 has_x2apic_api);
fb506e70
RK		 164}
165
0fd7e098
LL		 166static int kvm_get_tsc(CPUState *cs)
167{
168 X86CPU *cpu = X86_CPU(cs);
169 CPUX86State *env = &cpu->env;
170 struct {
171 struct kvm_msrs info;
172 struct kvm_msr_entry entries[1];
173 } msr_data;
174 int ret;
175
176 if (env->tsc_valid) {
177 return 0;
178 }
179
180 msr_data.info.nmsrs = 1;
181 msr_data.entries[0].index = MSR_IA32_TSC;
182 env->tsc_valid = !runstate_is_running();
183
184 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
185 if (ret < 0) {
186 return ret;
187 }
188
48e1a45c 189 assert(ret == 1);
0fd7e098
LL		 190 env->tsc = msr_data.entries[0].data;
191 return 0;
192}
193
14e6fe12 194static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 195{
0fd7e098
LL		 196 kvm_get_tsc(cpu);
197}
198
199void kvm_synchronize_all_tsc(void)
200{
201 CPUState *cpu;
202
203 if (kvm_enabled()) {
204 CPU_FOREACH(cpu) {
14e6fe12 205 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 206 }
207 }
208}
209
b827df58
AK		 210static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
211{
212 struct kvm_cpuid2 *cpuid;
213 int r, size;
214
215 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 216 cpuid = g_malloc0(size);
b827df58
AK		 217 cpuid->nent = max;
218 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 219 if (r == 0 && cpuid->nent >= max) {
220 r = -E2BIG;
221 }
b827df58
AK		 222 if (r < 0) {
223 if (r == -E2BIG) {
7267c094 224 g_free(cpuid);
b827df58
AK		 225 return NULL;
226 } else {
227 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
228 strerror(-r));
229 exit(1);
230 }
231 }
232 return cpuid;
233}
234
dd87f8a6
EH		 235/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
236 * for all entries.
237 */
238static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
239{
240 struct kvm_cpuid2 *cpuid;
241 int max = 1;
494e95e9
CP		 242
243 if (cpuid_cache != NULL) {
244 return cpuid_cache;
245 }
dd87f8a6
EH		 246 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
247 max *= 2;
248 }
494e95e9 249 cpuid_cache = cpuid;
dd87f8a6
EH		 250 return cpuid;
251}
252
a443bc34 253static const struct kvm_para_features {
0c31b744
GC		 254 int cap;
255 int feature;
256} para_features[] = {
257 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
258 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
259 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 260 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 261};
262
ba9bc59e 263static int get_para_features(KVMState *s)
0c31b744
GC		 264{
265 int i, features = 0;
266
8e03c100 267 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 268 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 269 features |= (1 << para_features[i].feature);
270 }
271 }
272
273 return features;
274}
0c31b744
GC		 275
276
829ae2f9
EH		 277/* Returns the value for a specific register on the cpuid entry
278 */
279static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
280{
281 uint32_t ret = 0;
282 switch (reg) {
283 case R_EAX:
284 ret = entry->eax;
285 break;
286 case R_EBX:
287 ret = entry->ebx;
288 break;
289 case R_ECX:
290 ret = entry->ecx;
291 break;
292 case R_EDX:
293 ret = entry->edx;
294 break;
295 }
296 return ret;
297}
298
4fb73f1d
EH		 299/* Find matching entry for function/index on kvm_cpuid2 struct
300 */
301static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
302 uint32_t function,
303 uint32_t index)
304{
305 int i;
306 for (i = 0; i < cpuid->nent; ++i) {
307 if (cpuid->entries[i].function == function &&
308 cpuid->entries[i].index == index) {
309 return &cpuid->entries[i];
310 }
311 }
312 /* not found: */
313 return NULL;
314}
315
ba9bc59e 316uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 317 uint32_t index, int reg)
b827df58
AK		 318{
319 struct kvm_cpuid2 *cpuid;
b827df58
AK		 320 uint32_t ret = 0;
321 uint32_t cpuid_1_edx;
8c723b79 322 bool found = false;
b827df58 323
dd87f8a6 324 cpuid = get_supported_cpuid(s);
b827df58 325
4fb73f1d
EH		 326 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
327 if (entry) {
328 found = true;
329 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 330 }
331
7b46e5ce
EH		 332 /* Fixups for the data returned by KVM, below */
333
c2acb022
EH		 334 if (function == 1 && reg == R_EDX) {
335 /* KVM before 2.6.30 misreports the following features */
336 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 337 } else if (function == 1 && reg == R_ECX) {
338 /* We can set the hypervisor flag, even if KVM does not return it on
339 * GET_SUPPORTED_CPUID
340 */
341 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 342 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
343 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
344 * and the irqchip is in the kernel.
345 */
346 if (kvm_irqchip_in_kernel() &&
347 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
348 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
349 }
41e5e76d
EH		 350
351 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
352 * without the in-kernel irqchip
353 */
354 if (!kvm_irqchip_in_kernel()) {
355 ret &= ~CPUID_EXT_X2APIC;
b827df58 356 }
28b8e4d0
JK		 357 } else if (function == 6 && reg == R_EAX) {
358 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
c2acb022
EH		 359 } else if (function == 0x80000001 && reg == R_EDX) {
360 /* On Intel, kvm returns cpuid according to the Intel spec,
361 * so add missing bits according to the AMD spec:
362 */
363 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
364 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 365 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
366 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
367 * be enabled without the in-kernel irqchip
368 */
369 if (!kvm_irqchip_in_kernel()) {
370 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
371 }
b827df58
AK		 372 }
373
0c31b744 374 /* fallback for older kernels */
8c723b79 375 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 376 ret = get_para_features(s);
b9bec74b 377 }
0c31b744
GC		 378
379 return ret;
bb0300dc 380}
bb0300dc 381
3c85e74f
HY		 382typedef struct HWPoisonPage {
383 ram_addr_t ram_addr;
384 QLIST_ENTRY(HWPoisonPage) list;
385} HWPoisonPage;
386
387static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
388 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
389
390static void kvm_unpoison_all(void *param)
391{
392 HWPoisonPage *page, *next_page;
393
394 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
395 QLIST_REMOVE(page, list);
396 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 397 g_free(page);
3c85e74f
HY		 398 }
399}
400
3c85e74f
HY		 401static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
402{
403 HWPoisonPage *page;
404
405 QLIST_FOREACH(page, &hwpoison_page_list, list) {
406 if (page->ram_addr == ram_addr) {
407 return;
408 }
409 }
ab3ad07f 410 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 411 page->ram_addr = ram_addr;
412 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
413}
414
e7701825
MT		 415static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
416 int *max_banks)
417{
418 int r;
419
14a09518 420 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 421 if (r > 0) {
422 *max_banks = r;
423 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
424 }
425 return -ENOSYS;
426}
427
bee615d4 428static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 429{
87f8b626 430 CPUState *cs = CPU(cpu);
bee615d4 431 CPUX86State *env = &cpu->env;
c34d440a
JK		 432 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
433 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
434 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 435 int flags = 0;
e7701825 436
c34d440a
JK		 437 if (code == BUS_MCEERR_AR) {
438 status |= MCI_STATUS_AR | 0x134;
439 mcg_status |= MCG_STATUS_EIPV;
440 } else {
441 status |= 0xc0;
442 mcg_status |= MCG_STATUS_RIPV;
419fb20a 443 }
87f8b626
AR		 444
445 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
446 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
447 * guest kernel back into env->mcg_ext_ctl.
448 */
449 cpu_synchronize_state(cs);
450 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
451 mcg_status |= MCG_STATUS_LMCE;
452 flags = 0;
453 }
454
8c5cf3b6 455 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 456 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 457}
419fb20a
JK		 458
459static void hardware_memory_error(void)
460{
461 fprintf(stderr, "Hardware memory error!\n");
462 exit(1);
463}
464
20d695a9 465int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 466{
20d695a9
AF		 467 X86CPU *cpu = X86_CPU(c);
468 CPUX86State *env = &cpu->env;
419fb20a 469 ram_addr_t ram_addr;
a8170e5e 470 hwaddr paddr;
419fb20a
JK		 471
472 if ((env->mcg_cap & MCG_SER_P) && addr
c34d440a 473 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
07bdaa41
PB		 474 ram_addr = qemu_ram_addr_from_host(addr);
475 if (ram_addr == RAM_ADDR_INVALID ||
a60f24b5 476 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
419fb20a
JK		 477 fprintf(stderr, "Hardware memory error for memory used by "
478 "QEMU itself instead of guest system!\n");
479 /* Hope we are lucky for AO MCE */
480 if (code == BUS_MCEERR_AO) {
481 return 0;
482 } else {
483 hardware_memory_error();
484 }
485 }
3c85e74f 486 kvm_hwpoison_page_add(ram_addr);
bee615d4 487 kvm_mce_inject(cpu, paddr, code);
e56ff191 488 } else {
419fb20a
JK		 489 if (code == BUS_MCEERR_AO) {
490 return 0;
491 } else if (code == BUS_MCEERR_AR) {
492 hardware_memory_error();
493 } else {
494 return 1;
495 }
496 }
497 return 0;
498}
499
500int kvm_arch_on_sigbus(int code, void *addr)
501{
182735ef
AF		 502 X86CPU *cpu = X86_CPU(first_cpu);
503
504 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
419fb20a 505 ram_addr_t ram_addr;
a8170e5e 506 hwaddr paddr;
419fb20a
JK		 507
508 /* Hope we are lucky for AO MCE */
07bdaa41
PB		 509 ram_addr = qemu_ram_addr_from_host(addr);
510 if (ram_addr == RAM_ADDR_INVALID ||
182735ef 511 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
a60f24b5 512 addr, &paddr)) {
419fb20a
JK		 513 fprintf(stderr, "Hardware memory error for memory used by "
514 "QEMU itself instead of guest system!: %p\n", addr);
515 return 0;
516 }
3c85e74f 517 kvm_hwpoison_page_add(ram_addr);
182735ef 518 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
e56ff191 519 } else {
419fb20a
JK		 520 if (code == BUS_MCEERR_AO) {
521 return 0;
522 } else if (code == BUS_MCEERR_AR) {
523 hardware_memory_error();
524 } else {
525 return 1;
526 }
527 }
528 return 0;
529}
e7701825 530
1bc22652 531static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 532{
1bc22652
AF		 533 CPUX86State *env = &cpu->env;
534
ab443475
JK		 535 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
536 unsigned int bank, bank_num = env->mcg_cap & 0xff;
537 struct kvm_x86_mce mce;
538
539 env->exception_injected = -1;
540
541 /*
542 * There must be at least one bank in use if an MCE is pending.
543 * Find it and use its values for the event injection.
544 */
545 for (bank = 0; bank < bank_num; bank++) {
546 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
547 break;
548 }
549 }
550 assert(bank < bank_num);
551
552 mce.bank = bank;
553 mce.status = env->mce_banks[bank * 4 + 1];
554 mce.mcg_status = env->mcg_status;
555 mce.addr = env->mce_banks[bank * 4 + 2];
556 mce.misc = env->mce_banks[bank * 4 + 3];
557
1bc22652 558 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 559 }
ab443475
JK		 560 return 0;
561}
562
1dfb4dd9 563static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 564{
317ac620 565 CPUX86State *env = opaque;
b8cc45d6
GC		 566
567 if (running) {
568 env->tsc_valid = false;
569 }
570}
571
83b17af5 572unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 573{
83b17af5 574 X86CPU *cpu = X86_CPU(cs);
7e72a45c 575 return cpu->apic_id;
b164e48e
EH		 576}
577
92067bf4
IM		 578#ifndef KVM_CPUID_SIGNATURE_NEXT
579#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
580#endif
581
582static bool hyperv_hypercall_available(X86CPU *cpu)
583{
584 return cpu->hyperv_vapic ||
585 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
586}
587
588static bool hyperv_enabled(X86CPU *cpu)
589{
7bc3d711
PB		 590 CPUState *cs = CPU(cpu);
591 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
592 (hyperv_hypercall_available(cpu) ||
48a5f3bc 593 cpu->hyperv_time ||
f2a53c9e 594 cpu->hyperv_relaxed_timing ||
744b8a94 595 cpu->hyperv_crash ||
8c145d7c 596 cpu->hyperv_reset ||
46eb8f98 597 cpu->hyperv_vpindex ||
866eea9a 598 cpu->hyperv_runtime ||
ff99aa64
AS		 599 cpu->hyperv_synic ||
600 cpu->hyperv_stimer);
92067bf4
IM		 601}
602
5031283d
HZ		 603static int kvm_arch_set_tsc_khz(CPUState *cs)
604{
605 X86CPU *cpu = X86_CPU(cs);
606 CPUX86State *env = &cpu->env;
607 int r;
608
609 if (!env->tsc_khz) {
610 return 0;
611 }
612
613 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
614 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
615 -ENOTSUP;
616 if (r < 0) {
617 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
618 * TSC frequency doesn't match the one we want.
619 */
620 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
621 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
622 -ENOTSUP;
623 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
624 error_report("warning: TSC frequency mismatch between "
d6276d26
EH		 625 "VM (%" PRId64 " kHz) and host (%d kHz), "
626 "and TSC scaling unavailable",
627 env->tsc_khz, cur_freq);
5031283d
HZ		 628 return r;
629 }
630 }
631
632 return 0;
633}
634
c35bd19a
EY		 635static int hyperv_handle_properties(CPUState *cs)
636{
637 X86CPU *cpu = X86_CPU(cs);
638 CPUX86State *env = &cpu->env;
639
3ddcd2ed
EH		 640 if (cpu->hyperv_time &&
641 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
642 cpu->hyperv_time = false;
643 }
644
c35bd19a
EY		 645 if (cpu->hyperv_relaxed_timing) {
646 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
647 }
648 if (cpu->hyperv_vapic) {
649 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
650 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
c35bd19a 651 }
3ddcd2ed 652 if (cpu->hyperv_time) {
c35bd19a
EY		 653 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
654 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
655 env->features[FEAT_HYPERV_EAX] |= 0x200;
c35bd19a
EY		 656 }
657 if (cpu->hyperv_crash && has_msr_hv_crash) {
658 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
659 }
660 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
661 if (cpu->hyperv_reset && has_msr_hv_reset) {
662 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
663 }
664 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
665 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
666 }
667 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
668 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
669 }
670 if (cpu->hyperv_synic) {
671 int sint;
672
673 if (!has_msr_hv_synic ||
674 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
675 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
676 return -ENOSYS;
677 }
678
679 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
680 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
681 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
682 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
683 }
684 }
685 if (cpu->hyperv_stimer) {
686 if (!has_msr_hv_stimer) {
687 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
688 return -ENOSYS;
689 }
690 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
691 }
692 return 0;
693}
694
68bfd0ad
MT		 695static Error *invtsc_mig_blocker;
696
f8bb0565 697#define KVM_MAX_CPUID_ENTRIES 100
0893d460 698
20d695a9 699int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 700{
701 struct {
486bd5a2 702 struct kvm_cpuid2 cpuid;
f8bb0565 703 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 704 } QEMU_PACKED cpuid_data;
20d695a9
AF		 705 X86CPU *cpu = X86_CPU(cs);
706 CPUX86State *env = &cpu->env;
486bd5a2 707 uint32_t limit, i, j, cpuid_i;
a33609ca 708 uint32_t unused;
bb0300dc 709 struct kvm_cpuid_entry2 *c;
bb0300dc 710 uint32_t signature[3];
234cc647 711 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 712 int r;
fe44dc91 713 Error *local_err = NULL;
05330448 714
ef4cbe14
SW		 715 memset(&cpuid_data, 0, sizeof(cpuid_data));
716
05330448
AL		 717 cpuid_i = 0;
718
bb0300dc 719 /* Paravirtualization CPUIDs */
234cc647
PB		 720 if (hyperv_enabled(cpu)) {
721 c = &cpuid_data.entries[cpuid_i++];
722 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 723 if (!cpu->hyperv_vendor_id) {
724 memcpy(signature, "Microsoft Hv", 12);
725 } else {
726 size_t len = strlen(cpu->hyperv_vendor_id);
727
728 if (len > 12) {
729 error_report("hv-vendor-id truncated to 12 characters");
730 len = 12;
731 }
732 memset(signature, 0, 12);
733 memcpy(signature, cpu->hyperv_vendor_id, len);
734 }
eab70139 735 c->eax = HYPERV_CPUID_MIN;
234cc647
PB		 736 c->ebx = signature[0];
737 c->ecx = signature[1];
738 c->edx = signature[2];
0c31b744 739
234cc647
PB		 740 c = &cpuid_data.entries[cpuid_i++];
741 c->function = HYPERV_CPUID_INTERFACE;
eab70139
VR		 742 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
743 c->eax = signature[0];
234cc647
PB		 744 c->ebx = 0;
745 c->ecx = 0;
746 c->edx = 0;
eab70139
VR		 747
748 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 749 c->function = HYPERV_CPUID_VERSION;
750 c->eax = 0x00001bbc;
751 c->ebx = 0x00060001;
752
753 c = &cpuid_data.entries[cpuid_i++];
eab70139 754 c->function = HYPERV_CPUID_FEATURES;
c35bd19a
EY		 755 r = hyperv_handle_properties(cs);
756 if (r) {
757 return r;
46eb8f98 758 }
c35bd19a
EY		 759 c->eax = env->features[FEAT_HYPERV_EAX];
760 c->ebx = env->features[FEAT_HYPERV_EBX];
761 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 762
eab70139 763 c = &cpuid_data.entries[cpuid_i++];
eab70139 764 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
92067bf4 765 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 766 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
767 }
2d5aa872 768 if (cpu->hyperv_vapic) {
eab70139
VR		 769 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
770 }
92067bf4 771 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 772
773 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 774 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
775 c->eax = 0x40;
776 c->ebx = 0x40;
777
234cc647 778 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 779 has_msr_hv_hypercall = true;
eab70139
VR		 780 }
781
f522d2ac
AW		 782 if (cpu->expose_kvm) {
783 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
784 c = &cpuid_data.entries[cpuid_i++];
785 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 786 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 787 c->ebx = signature[0];
788 c->ecx = signature[1];
789 c->edx = signature[2];
234cc647 790
f522d2ac
AW		 791 c = &cpuid_data.entries[cpuid_i++];
792 c->function = KVM_CPUID_FEATURES | kvm_base;
793 c->eax = env->features[FEAT_KVM];
f522d2ac 794 }
917367aa 795
a33609ca 796 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 797
798 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 799 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
800 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
801 abort();
802 }
bb0300dc 803 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 804
805 switch (i) {
a36b1029
AL		 806 case 2: {
807 /* Keep reading function 2 till all the input is received */
808 int times;
809
a36b1029 810 c->function = i;
a33609ca
AL		 811 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
812 KVM_CPUID_FLAG_STATE_READ_NEXT;
813 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
814 times = c->eax & 0xff;
a36b1029
AL		 815
816 for (j = 1; j < times; ++j) {
f8bb0565
IM		 817 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
818 fprintf(stderr, "cpuid_data is full, no space for "
819 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
820 abort();
821 }
a33609ca 822 c = &cpuid_data.entries[cpuid_i++];
a36b1029 823 c->function = i;
a33609ca
AL		 824 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
825 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 826 }
827 break;
828 }
486bd5a2
AL		 829 case 4:
830 case 0xb:
831 case 0xd:
832 for (j = 0; ; j++) {
31e8c696
AP		 833 if (i == 0xd && j == 64) {
834 break;
835 }
486bd5a2
AL		 836 c->function = i;
837 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
838 c->index = j;
a33609ca 839 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 840
b9bec74b 841 if (i == 4 && c->eax == 0) {
486bd5a2 842 break;
b9bec74b
JK		 843 }
844 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 845 break;
b9bec74b
JK		 846 }
847 if (i == 0xd && c->eax == 0) {
31e8c696 848 continue;
b9bec74b 849 }
f8bb0565
IM		 850 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
851 fprintf(stderr, "cpuid_data is full, no space for "
852 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
853 abort();
854 }
a33609ca 855 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 856 }
857 break;
858 default:
486bd5a2 859 c->function = i;
a33609ca
AL		 860 c->flags = 0;
861 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 862 break;
863 }
05330448 864 }
0d894367
PB		 865
866 if (limit >= 0x0a) {
867 uint32_t ver;
868
869 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
870 if ((ver & 0xff) > 0) {
871 has_msr_architectural_pmu = true;
872 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
873
874 /* Shouldn't be more than 32, since that's the number of bits
875 * available in EBX to tell us _which_ counters are available.
876 * Play it safe.
877 */
878 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
879 num_architectural_pmu_counters = MAX_GP_COUNTERS;
880 }
881 }
882 }
883
a33609ca 884 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 885
886 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 887 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
888 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
889 abort();
890 }
bb0300dc 891 c = &cpuid_data.entries[cpuid_i++];
05330448 892
05330448 893 c->function = i;
a33609ca
AL		 894 c->flags = 0;
895 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 896 }
897
b3baa152
BW		 898 /* Call Centaur's CPUID instructions they are supported. */
899 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 900 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
901
902 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 903 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
904 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
905 abort();
906 }
b3baa152
BW		 907 c = &cpuid_data.entries[cpuid_i++];
908
909 c->function = i;
910 c->flags = 0;
911 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
912 }
913 }
914
05330448
AL		 915 cpuid_data.cpuid.nent = cpuid_i;
916
e7701825 917 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 918 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 919 (CPUID_MCE | CPUID_MCA)
a60f24b5 920 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 921 uint64_t mcg_cap, unsupported_caps;
e7701825 922 int banks;
32a42024 923 int ret;
e7701825 924
a60f24b5 925 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 926 if (ret < 0) {
927 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
928 return ret;
e7701825 929 }
75d49497 930
2590f15b 931 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 932 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 933 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 934 return -ENOTSUP;
75d49497 935 }
49b69cbf 936
5120901a
EH		 937 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
938 if (unsupported_caps) {
87f8b626
AR		 939 if (unsupported_caps & MCG_LMCE_P) {
940 error_report("kvm: LMCE not supported");
941 return -ENOTSUP;
942 }
5120901a
EH		 943 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
944 unsupported_caps);
945 }
946
2590f15b
EH		 947 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
948 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 949 if (ret < 0) {
950 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
951 return ret;
952 }
e7701825 953 }
e7701825 954
b8cc45d6
GC		 955 qemu_add_vm_change_state_handler(cpu_update_state, env);
956
df67696e
LJ		 957 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
958 if (c) {
959 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
960 !!(c->ecx & CPUID_EXT_SMX);
961 }
962
87f8b626
AR		 963 if (env->mcg_cap & MCG_LMCE_P) {
964 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
965 }
966
d99569d9
EH		 967 if (!env->user_tsc_khz) {
968 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
969 invtsc_mig_blocker == NULL) {
970 /* for migration */
971 error_setg(&invtsc_mig_blocker,
972 "State blocked by non-migratable CPU device"
973 " (invtsc flag)");
fe44dc91
AA		 974 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
975 if (local_err) {
976 error_report_err(local_err);
977 error_free(invtsc_mig_blocker);
978 goto fail;
979 }
d99569d9
EH		 980 /* for savevm */
981 vmstate_x86_cpu.unmigratable = 1;
982 }
68bfd0ad
MT		 983 }
984
7e680753 985 cpuid_data.cpuid.padding = 0;
1bc22652 986 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
fdc9c41a 987 if (r) {
fe44dc91 988 goto fail;
fdc9c41a 989 }
e7429073 990
5031283d
HZ		 991 r = kvm_arch_set_tsc_khz(cs);
992 if (r < 0) {
fe44dc91 993 goto fail;
e7429073 994 }
e7429073 995
bcffbeeb
HZ		 996 /* vcpu's TSC frequency is either specified by user, or following
997 * the value used by KVM if the former is not present. In the
998 * latter case, we query it from KVM and record in env->tsc_khz,
999 * so that vcpu's TSC frequency can be migrated later via this field.
1000 */
1001 if (!env->tsc_khz) {
1002 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1003 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1004 -ENOTSUP;
1005 if (r > 0) {
1006 env->tsc_khz = r;
1007 }
1008 }
1009
28143b40 1010 if (has_xsave) {
fabacc0f
JK		 1011 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1012 }
d71b62a1 1013 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1014
273c515c
PB		 1015 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1016 has_msr_tsc_aux = false;
1017 }
d1ae67f6 1018
e7429073 1019 return 0;
fe44dc91
AA		 1020
1021 fail:
1022 migrate_del_blocker(invtsc_mig_blocker);
1023 return r;
05330448
AL		 1024}
1025
50a2c6e5 1026void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1027{
20d695a9 1028 CPUX86State *env = &cpu->env;
dd673288 1029
e73223a5 1030 env->exception_injected = -1;
0e607a80 1031 env->interrupt_injected = -1;
1a5e9d2f 1032 env->xcr0 = 1;
ddced198 1033 if (kvm_irqchip_in_kernel()) {
dd673288 1034 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1035 KVM_MP_STATE_UNINITIALIZED;
1036 } else {
1037 env->mp_state = KVM_MP_STATE_RUNNABLE;
1038 }
caa5af0f
JK		 1039}
1040
e0723c45
PB		 1041void kvm_arch_do_init_vcpu(X86CPU *cpu)
1042{
1043 CPUX86State *env = &cpu->env;
1044
1045 /* APs get directly into wait-for-SIPI state. */
1046 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1047 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1048 }
1049}
1050
c3a3a7d3 1051static int kvm_get_supported_msrs(KVMState *s)
05330448 1052{
75b10c43 1053 static int kvm_supported_msrs;
c3a3a7d3 1054 int ret = 0;
05330448
AL		 1055
1056 /* first time */
75b10c43 1057 if (kvm_supported_msrs == 0) {
05330448
AL		 1058 struct kvm_msr_list msr_list, *kvm_msr_list;
1059
75b10c43 1060 kvm_supported_msrs = -1;
05330448
AL		 1061
1062 /* Obtain MSR list from KVM. These are the MSRs that we must
1063 * save/restore */
4c9f7372 1064 msr_list.nmsrs = 0;
c3a3a7d3 1065 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1066 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1067 return ret;
6fb6d245 1068 }
d9db889f
JK		 1069 /* Old kernel modules had a bug and could write beyond the provided
1070 memory. Allocate at least a safe amount of 1K. */
7267c094 1071 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1072 msr_list.nmsrs *
1073 sizeof(msr_list.indices[0])));
05330448 1074
55308450 1075 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1076 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1077 if (ret >= 0) {
1078 int i;
1079
1080 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1081 if (kvm_msr_list->indices[i] == MSR_STAR) {
c3a3a7d3 1082 has_msr_star = true;
75b10c43
MT		 1083 continue;
1084 }
1085 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
c3a3a7d3 1086 has_msr_hsave_pa = true;
75b10c43 1087 continue;
05330448 1088 }
c9b8f6b6
AS		 1089 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1090 has_msr_tsc_aux = true;
1091 continue;
1092 }
f28558d3
WA		 1093 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1094 has_msr_tsc_adjust = true;
1095 continue;
1096 }
aa82ba54
LJ		 1097 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1098 has_msr_tsc_deadline = true;
1099 continue;
1100 }
fc12d72e
PB		 1101 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1102 has_msr_smbase = true;
1103 continue;
1104 }
21e87c46
AK		 1105 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1106 has_msr_misc_enable = true;
1107 continue;
1108 }
79e9ebeb
LJ		 1109 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1110 has_msr_bndcfgs = true;
1111 continue;
1112 }
18cd2c17
WL		 1113 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1114 has_msr_xss = true;
1115 continue;
1116 }
f2a53c9e
AS		 1117 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1118 has_msr_hv_crash = true;
1119 continue;
1120 }
744b8a94
AS		 1121 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1122 has_msr_hv_reset = true;
1123 continue;
1124 }
8c145d7c
AS		 1125 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1126 has_msr_hv_vpindex = true;
1127 continue;
1128 }
46eb8f98
AS		 1129 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1130 has_msr_hv_runtime = true;
1131 continue;
1132 }
866eea9a
AS		 1133 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1134 has_msr_hv_synic = true;
1135 continue;
1136 }
ff99aa64
AS		 1137 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1138 has_msr_hv_stimer = true;
1139 continue;
1140 }
05330448
AL		 1141 }
1142 }
1143
7267c094 1144 g_free(kvm_msr_list);
05330448
AL		 1145 }
1146
c3a3a7d3 1147 return ret;
05330448
AL		 1148}
1149
6410848b
PB		 1150static Notifier smram_machine_done;
1151static KVMMemoryListener smram_listener;
1152static AddressSpace smram_address_space;
1153static MemoryRegion smram_as_root;
1154static MemoryRegion smram_as_mem;
1155
1156static void register_smram_listener(Notifier *n, void *unused)
1157{
1158 MemoryRegion *smram =
1159 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1160
1161 /* Outer container... */
1162 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1163 memory_region_set_enabled(&smram_as_root, true);
1164
1165 /* ... with two regions inside: normal system memory with low
1166 * priority, and...
1167 */
1168 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1169 get_system_memory(), 0, ~0ull);
1170 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1171 memory_region_set_enabled(&smram_as_mem, true);
1172
1173 if (smram) {
1174 /* ... SMRAM with higher priority */
1175 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1176 memory_region_set_enabled(smram, true);
1177 }
1178
1179 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1180 kvm_memory_listener_register(kvm_state, &smram_listener,
1181 &smram_address_space, 1);
1182}
1183
b16565b3 1184int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1185{
11076198 1186 uint64_t identity_base = 0xfffbc000;
39d6960a 1187 uint64_t shadow_mem;
20420430 1188 int ret;
25d2e361 1189 struct utsname utsname;
20420430 1190
28143b40
TH		 1191#ifdef KVM_CAP_XSAVE
1192 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1193#endif
1194
1195#ifdef KVM_CAP_XCRS
1196 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1197#endif
1198
1199#ifdef KVM_CAP_PIT_STATE2
1200 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1201#endif
1202
c3a3a7d3 1203 ret = kvm_get_supported_msrs(s);
20420430 1204 if (ret < 0) {
20420430
SY		 1205 return ret;
1206 }
25d2e361
MT		 1207
1208 uname(&utsname);
1209 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1210
4c5b10b7 1211 /*
11076198
JK		 1212 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1213 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1214 * Since these must be part of guest physical memory, we need to allocate
1215 * them, both by setting their start addresses in the kernel and by
1216 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1217 *
1218 * Older KVM versions may not support setting the identity map base. In
1219 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1220 * size.
4c5b10b7 1221 */
11076198
JK		 1222 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1223 /* Allows up to 16M BIOSes. */
1224 identity_base = 0xfeffc000;
1225
1226 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1227 if (ret < 0) {
1228 return ret;
1229 }
4c5b10b7 1230 }
e56ff191 1231
11076198
JK		 1232 /* Set TSS base one page after EPT identity map. */
1233 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1234 if (ret < 0) {
1235 return ret;
1236 }
1237
11076198
JK		 1238 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1239 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1240 if (ret < 0) {
11076198 1241 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1242 return ret;
1243 }
3c85e74f 1244 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1245
4689b77b 1246 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1247 if (shadow_mem != -1) {
1248 shadow_mem /= 4096;
1249 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1250 if (ret < 0) {
1251 return ret;
39d6960a
JK		 1252 }
1253 }
6410848b
PB		 1254
1255 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1256 smram_machine_done.notify = register_smram_listener;
1257 qemu_add_machine_init_done_notifier(&smram_machine_done);
1258 }
11076198 1259 return 0;
05330448 1260}
b9bec74b 1261
05330448
AL		 1262static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1263{
1264 lhs->selector = rhs->selector;
1265 lhs->base = rhs->base;
1266 lhs->limit = rhs->limit;
1267 lhs->type = 3;
1268 lhs->present = 1;
1269 lhs->dpl = 3;
1270 lhs->db = 0;
1271 lhs->s = 1;
1272 lhs->l = 0;
1273 lhs->g = 0;
1274 lhs->avl = 0;
1275 lhs->unusable = 0;
1276}
1277
1278static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1279{
1280 unsigned flags = rhs->flags;
1281 lhs->selector = rhs->selector;
1282 lhs->base = rhs->base;
1283 lhs->limit = rhs->limit;
1284 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1285 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1286 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1287 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1288 lhs->s = (flags & DESC_S_MASK) != 0;
1289 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1290 lhs->g = (flags & DESC_G_MASK) != 0;
1291 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1292 lhs->unusable = !lhs->present;
7e680753 1293 lhs->padding = 0;
05330448
AL		 1294}
1295
1296static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1297{
1298 lhs->selector = rhs->selector;
1299 lhs->base = rhs->base;
1300 lhs->limit = rhs->limit;
4cae9c97
MC		 1301 if (rhs->unusable) {
1302 lhs->flags = 0;
1303 } else {
1304 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1305 (rhs->present * DESC_P_MASK) |
1306 (rhs->dpl << DESC_DPL_SHIFT) |
1307 (rhs->db << DESC_B_SHIFT) |
1308 (rhs->s * DESC_S_MASK) |
1309 (rhs->l << DESC_L_SHIFT) |
1310 (rhs->g * DESC_G_MASK) |
1311 (rhs->avl * DESC_AVL_MASK);
1312 }
05330448
AL		 1313}
1314
1315static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1316{
b9bec74b 1317 if (set) {
05330448 1318 *kvm_reg = *qemu_reg;
b9bec74b 1319 } else {
05330448 1320 *qemu_reg = *kvm_reg;
b9bec74b 1321 }
05330448
AL		 1322}
1323
1bc22652 1324static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1325{
1bc22652 1326 CPUX86State *env = &cpu->env;
05330448
AL		 1327 struct kvm_regs regs;
1328 int ret = 0;
1329
1330 if (!set) {
1bc22652 1331 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1332 if (ret < 0) {
05330448 1333 return ret;
b9bec74b 1334 }
05330448
AL		 1335 }
1336
1337 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1338 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1339 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1340 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1341 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1342 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1343 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1344 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1345#ifdef TARGET_X86_64
1346 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1347 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1348 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1349 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1350 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1351 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1352 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1353 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1354#endif
1355
1356 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1357 kvm_getput_reg(&regs.rip, &env->eip, set);
1358
b9bec74b 1359 if (set) {
1bc22652 1360 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1361 }
05330448
AL		 1362
1363 return ret;
1364}
1365
1bc22652 1366static int kvm_put_fpu(X86CPU *cpu)
05330448 1367{
1bc22652 1368 CPUX86State *env = &cpu->env;
05330448
AL		 1369 struct kvm_fpu fpu;
1370 int i;
1371
1372 memset(&fpu, 0, sizeof fpu);
1373 fpu.fsw = env->fpus & ~(7 << 11);
1374 fpu.fsw |= (env->fpstt & 7) << 11;
1375 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1376 fpu.last_opcode = env->fpop;
1377 fpu.last_ip = env->fpip;
1378 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1379 for (i = 0; i < 8; ++i) {
1380 fpu.ftwx |= (!env->fptags[i]) << i;
1381 }
05330448 1382 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1383 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1384 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1385 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1386 }
05330448
AL		 1387 fpu.mxcsr = env->mxcsr;
1388
1bc22652 1389 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1390}
1391
6b42494b
JK		 1392#define XSAVE_FCW_FSW 0
1393#define XSAVE_FTW_FOP 1
f1665b21
SY		 1394#define XSAVE_CWD_RIP 2
1395#define XSAVE_CWD_RDP 4
1396#define XSAVE_MXCSR 6
1397#define XSAVE_ST_SPACE 8
1398#define XSAVE_XMM_SPACE 40
1399#define XSAVE_XSTATE_BV 128
1400#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1401#define XSAVE_BNDREGS 240
1402#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1403#define XSAVE_OPMASK 272
1404#define XSAVE_ZMM_Hi256 288
1405#define XSAVE_Hi16_ZMM 416
f74eefe0 1406#define XSAVE_PKRU 672
f1665b21 1407
b503717d
EH		 1408#define XSAVE_BYTE_OFFSET(word_offset) \
1409 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1410
1411#define ASSERT_OFFSET(word_offset, field) \
1412 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1413 offsetof(X86XSaveArea, field))
1414
1415ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1416ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1417ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1418ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1419ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1420ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1421ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1422ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1423ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1424ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1425ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1426ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1427ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1428ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1429ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1430
1bc22652 1431static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1432{
1bc22652 1433 CPUX86State *env = &cpu->env;
86cd2ea0 1434 X86XSaveArea *xsave = env->kvm_xsave_buf;
42cc8fa6 1435 uint16_t cwd, swd, twd;
9be38598 1436 int i;
f1665b21 1437
28143b40 1438 if (!has_xsave) {
1bc22652 1439 return kvm_put_fpu(cpu);
b9bec74b 1440 }
f1665b21 1441
f1665b21 1442 memset(xsave, 0, sizeof(struct kvm_xsave));
6115c0a8 1443 twd = 0;
f1665b21
SY		 1444 swd = env->fpus & ~(7 << 11);
1445 swd |= (env->fpstt & 7) << 11;
1446 cwd = env->fpuc;
b9bec74b 1447 for (i = 0; i < 8; ++i) {
f1665b21 1448 twd |= (!env->fptags[i]) << i;
b9bec74b 1449 }
86cd2ea0
EH		 1450 xsave->legacy.fcw = cwd;
1451 xsave->legacy.fsw = swd;
1452 xsave->legacy.ftw = twd;
1453 xsave->legacy.fpop = env->fpop;
1454 xsave->legacy.fpip = env->fpip;
1455 xsave->legacy.fpdp = env->fpdp;
1456 memcpy(&xsave->legacy.fpregs, env->fpregs,
f1665b21 1457 sizeof env->fpregs);
86cd2ea0
EH		 1458 xsave->legacy.mxcsr = env->mxcsr;
1459 xsave->header.xstate_bv = env->xstate_bv;
1460 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
79e9ebeb 1461 sizeof env->bnd_regs);
86cd2ea0
EH		 1462 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1463 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
9aecd6f8 1464 sizeof env->opmask_regs);
bee81887 1465
86cd2ea0
EH		 1466 for (i = 0; i < CPU_NB_REGS; i++) {
1467 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1468 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1469 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
19cbd87c
EH		 1470 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1471 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1472 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1473 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1474 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1475 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1476 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1477 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
bee81887
PB		 1478 }
1479
9aecd6f8 1480#ifdef TARGET_X86_64
86cd2ea0 1481 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
b7711471 1482 16 * sizeof env->xmm_regs[16]);
86cd2ea0 1483 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
9aecd6f8 1484#endif
9be38598 1485 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1486}
1487
1bc22652 1488static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1489{
1bc22652 1490 CPUX86State *env = &cpu->env;
bdfc8480 1491 struct kvm_xcrs xcrs = {};
f1665b21 1492
28143b40 1493 if (!has_xcrs) {
f1665b21 1494 return 0;
b9bec74b 1495 }
f1665b21
SY		 1496
1497 xcrs.nr_xcrs = 1;
1498 xcrs.flags = 0;
1499 xcrs.xcrs[0].xcr = 0;
1500 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1501 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1502}
1503
1bc22652 1504static int kvm_put_sregs(X86CPU *cpu)
05330448 1505{
1bc22652 1506 CPUX86State *env = &cpu->env;
05330448
AL		 1507 struct kvm_sregs sregs;
1508
0e607a80
JK		 1509 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1510 if (env->interrupt_injected >= 0) {
1511 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1512 (uint64_t)1 << (env->interrupt_injected % 64);
1513 }
05330448
AL		 1514
1515 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1516 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1517 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1518 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1519 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1520 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1521 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1522 } else {
b9bec74b
JK		 1523 set_seg(&sregs.cs, &env->segs[R_CS]);
1524 set_seg(&sregs.ds, &env->segs[R_DS]);
1525 set_seg(&sregs.es, &env->segs[R_ES]);
1526 set_seg(&sregs.fs, &env->segs[R_FS]);
1527 set_seg(&sregs.gs, &env->segs[R_GS]);
1528 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1529 }
1530
1531 set_seg(&sregs.tr, &env->tr);
1532 set_seg(&sregs.ldt, &env->ldt);
1533
1534 sregs.idt.limit = env->idt.limit;
1535 sregs.idt.base = env->idt.base;
7e680753 1536 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1537 sregs.gdt.limit = env->gdt.limit;
1538 sregs.gdt.base = env->gdt.base;
7e680753 1539 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1540
1541 sregs.cr0 = env->cr[0];
1542 sregs.cr2 = env->cr[2];
1543 sregs.cr3 = env->cr[3];
1544 sregs.cr4 = env->cr[4];
1545
02e51483
CF		 1546 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1547 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1548
1549 sregs.efer = env->efer;
1550
1bc22652 1551 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1552}
1553
d71b62a1
EH		 1554static void kvm_msr_buf_reset(X86CPU *cpu)
1555{
1556 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1557}
1558
9c600a84
EH		 1559static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1560{
1561 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1562 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1563 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1564
1565 assert((void *)(entry + 1) <= limit);
1566
1abc2cae
EH		 1567 entry->index = index;
1568 entry->reserved = 0;
1569 entry->data = value;
9c600a84
EH		 1570 msrs->nmsrs++;
1571}
1572
73e1b8f2
PB		 1573static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1574{
1575 kvm_msr_buf_reset(cpu);
1576 kvm_msr_entry_add(cpu, index, value);
1577
1578 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1579}
1580
f8d9ccf8
DDAG		 1581void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1582{
1583 int ret;
1584
1585 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1586 assert(ret == 1);
1587}
1588
7477cd38
MT		 1589static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1590{
1591 CPUX86State *env = &cpu->env;
48e1a45c 1592 int ret;
7477cd38
MT		 1593
1594 if (!has_msr_tsc_deadline) {
1595 return 0;
1596 }
1597
73e1b8f2 1598 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1599 if (ret < 0) {
1600 return ret;
1601 }
1602
1603 assert(ret == 1);
1604 return 0;
7477cd38
MT		 1605}
1606
6bdf863d
JK		 1607/*
1608 * Provide a separate write service for the feature control MSR in order to
1609 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1610 * before writing any other state because forcibly leaving nested mode
1611 * invalidates the VCPU state.
1612 */
1613static int kvm_put_msr_feature_control(X86CPU *cpu)
1614{
48e1a45c
PB		 1615 int ret;
1616
1617 if (!has_msr_feature_control) {
1618 return 0;
1619 }
6bdf863d 1620
73e1b8f2
PB		 1621 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1622 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1623 if (ret < 0) {
1624 return ret;
1625 }
1626
1627 assert(ret == 1);
1628 return 0;
6bdf863d
JK		 1629}
1630
1bc22652 1631static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1632{
1bc22652 1633 CPUX86State *env = &cpu->env;
9c600a84 1634 int i;
48e1a45c 1635 int ret;
05330448 1636
d71b62a1
EH		 1637 kvm_msr_buf_reset(cpu);
1638
9c600a84
EH		 1639 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1640 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1641 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1642 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1643 if (has_msr_star) {
9c600a84 1644 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1645 }
c3a3a7d3 1646 if (has_msr_hsave_pa) {
9c600a84 1647 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1648 }
c9b8f6b6 1649 if (has_msr_tsc_aux) {
9c600a84 1650 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1651 }
f28558d3 1652 if (has_msr_tsc_adjust) {
9c600a84 1653 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1654 }
21e87c46 1655 if (has_msr_misc_enable) {
9c600a84 1656 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1657 env->msr_ia32_misc_enable);
1658 }
fc12d72e 1659 if (has_msr_smbase) {
9c600a84 1660 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1661 }
439d19f2 1662 if (has_msr_bndcfgs) {
9c600a84 1663 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1664 }
18cd2c17 1665 if (has_msr_xss) {
9c600a84 1666 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1667 }
05330448 1668#ifdef TARGET_X86_64
25d2e361 1669 if (lm_capable_kernel) {
9c600a84
EH		 1670 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1671 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1672 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1673 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1674 }
05330448 1675#endif
ff5c186b 1676 /*
0d894367
PB		 1677 * The following MSRs have side effects on the guest or are too heavy
1678 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1679 */
1680 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1681 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1682 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1683 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 1684 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 1685 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1686 }
55c911a5 1687 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 1688 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1689 }
55c911a5 1690 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 1691 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1692 }
0d894367
PB		 1693 if (has_msr_architectural_pmu) {
1694 /* Stop the counter. */
9c600a84
EH		 1695 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1696 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
0d894367
PB		 1697
1698 /* Set the counter values. */
1699 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 1700 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1701 env->msr_fixed_counters[i]);
1702 }
1703 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84 1704 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1705 env->msr_gp_counters[i]);
9c600a84 1706 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1707 env->msr_gp_evtsel[i]);
1708 }
9c600a84 1709 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
0d894367 1710 env->msr_global_status);
9c600a84 1711 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
0d894367
PB		 1712 env->msr_global_ovf_ctrl);
1713
1714 /* Now start the PMU. */
9c600a84 1715 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
0d894367 1716 env->msr_fixed_ctr_ctrl);
9c600a84 1717 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
0d894367
PB		 1718 env->msr_global_ctrl);
1719 }
7bc3d711 1720 if (has_msr_hv_hypercall) {
9c600a84 1721 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1c90ef26 1722 env->msr_hv_guest_os_id);
9c600a84 1723 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1c90ef26 1724 env->msr_hv_hypercall);
eab70139 1725 }
2d5aa872 1726 if (cpu->hyperv_vapic) {
9c600a84 1727 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1728 env->msr_hv_vapic);
eab70139 1729 }
3ddcd2ed 1730 if (cpu->hyperv_time) {
9c600a84 1731 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
48a5f3bc 1732 }
f2a53c9e
AS		 1733 if (has_msr_hv_crash) {
1734 int j;
1735
1736 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
9c600a84 1737 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1738 env->msr_hv_crash_params[j]);
1739
9c600a84 1740 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
f2a53c9e
AS		 1741 HV_X64_MSR_CRASH_CTL_NOTIFY);
1742 }
46eb8f98 1743 if (has_msr_hv_runtime) {
9c600a84 1744 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1745 }
866eea9a
AS		 1746 if (cpu->hyperv_synic) {
1747 int j;
1748
9c600a84 1749 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1750 env->msr_hv_synic_control);
9c600a84 1751 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
866eea9a 1752 env->msr_hv_synic_version);
9c600a84 1753 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1754 env->msr_hv_synic_evt_page);
9c600a84 1755 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1756 env->msr_hv_synic_msg_page);
1757
1758 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1759 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1760 env->msr_hv_synic_sint[j]);
1761 }
1762 }
ff99aa64
AS		 1763 if (has_msr_hv_stimer) {
1764 int j;
1765
1766 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1767 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1768 env->msr_hv_stimer_config[j]);
1769 }
1770
1771 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1772 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1773 env->msr_hv_stimer_count[j]);
1774 }
1775 }
1eabfce6 1776 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 1777 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1778
9c600a84
EH		 1779 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1780 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1781 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1782 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1783 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1784 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1785 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1786 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1787 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1788 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1789 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1790 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1791 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 1792 /* The CPU GPs if we write to a bit above the physical limit of
1793 * the host CPU (and KVM emulates that)
1794 */
1795 uint64_t mask = env->mtrr_var[i].mask;
1796 mask &= phys_mask;
1797
9c600a84
EH		 1798 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1799 env->mtrr_var[i].base);
112dad69 1800 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 1801 }
1802 }
6bdf863d
JK		 1803
1804 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1805 * kvm_put_msr_feature_control. */
ea643051 1806 }
57780495 1807 if (env->mcg_cap) {
d8da8574 1808 int i;
b9bec74b 1809
9c600a84
EH		 1810 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1811 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 1812 if (has_msr_mcg_ext_ctl) {
1813 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1814 }
c34d440a 1815 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1816 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1817 }
1818 }
1a03675d 1819
d71b62a1 1820 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1821 if (ret < 0) {
1822 return ret;
1823 }
05330448 1824
9c600a84 1825 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 1826 return 0;
05330448
AL		 1827}
1828
1829
1bc22652 1830static int kvm_get_fpu(X86CPU *cpu)
05330448 1831{
1bc22652 1832 CPUX86State *env = &cpu->env;
05330448
AL		 1833 struct kvm_fpu fpu;
1834 int i, ret;
1835
1bc22652 1836 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1837 if (ret < 0) {
05330448 1838 return ret;
b9bec74b 1839 }
05330448
AL		 1840
1841 env->fpstt = (fpu.fsw >> 11) & 7;
1842 env->fpus = fpu.fsw;
1843 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1844 env->fpop = fpu.last_opcode;
1845 env->fpip = fpu.last_ip;
1846 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1847 for (i = 0; i < 8; ++i) {
1848 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1849 }
05330448 1850 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 1851 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1852 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1853 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 1854 }
05330448
AL		 1855 env->mxcsr = fpu.mxcsr;
1856
1857 return 0;
1858}
1859
1bc22652 1860static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1861{
1bc22652 1862 CPUX86State *env = &cpu->env;
86cd2ea0 1863 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1864 int ret, i;
42cc8fa6 1865 uint16_t cwd, swd, twd;
f1665b21 1866
28143b40 1867 if (!has_xsave) {
1bc22652 1868 return kvm_get_fpu(cpu);
b9bec74b 1869 }
f1665b21 1870
1bc22652 1871 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1872 if (ret < 0) {
f1665b21 1873 return ret;
0f53994f 1874 }
f1665b21 1875
86cd2ea0
EH		 1876 cwd = xsave->legacy.fcw;
1877 swd = xsave->legacy.fsw;
1878 twd = xsave->legacy.ftw;
1879 env->fpop = xsave->legacy.fpop;
f1665b21
SY		 1880 env->fpstt = (swd >> 11) & 7;
1881 env->fpus = swd;
1882 env->fpuc = cwd;
b9bec74b 1883 for (i = 0; i < 8; ++i) {
f1665b21 1884 env->fptags[i] = !((twd >> i) & 1);
b9bec74b 1885 }
86cd2ea0
EH		 1886 env->fpip = xsave->legacy.fpip;
1887 env->fpdp = xsave->legacy.fpdp;
1888 env->mxcsr = xsave->legacy.mxcsr;
1889 memcpy(env->fpregs, &xsave->legacy.fpregs,
f1665b21 1890 sizeof env->fpregs);
86cd2ea0
EH		 1891 env->xstate_bv = xsave->header.xstate_bv;
1892 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
79e9ebeb 1893 sizeof env->bnd_regs);
86cd2ea0
EH		 1894 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1895 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
9aecd6f8 1896 sizeof env->opmask_regs);
bee81887 1897
86cd2ea0
EH		 1898 for (i = 0; i < CPU_NB_REGS; i++) {
1899 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1900 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1901 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
19cbd87c
EH		 1902 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1903 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1904 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1905 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1906 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1907 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1908 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1909 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
bee81887
PB		 1910 }
1911
9aecd6f8 1912#ifdef TARGET_X86_64
86cd2ea0 1913 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
b7711471 1914 16 * sizeof env->xmm_regs[16]);
86cd2ea0 1915 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
9aecd6f8 1916#endif
f1665b21 1917 return 0;
f1665b21
SY		 1918}
1919
1bc22652 1920static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1921{
1bc22652 1922 CPUX86State *env = &cpu->env;
f1665b21
SY		 1923 int i, ret;
1924 struct kvm_xcrs xcrs;
1925
28143b40 1926 if (!has_xcrs) {
f1665b21 1927 return 0;
b9bec74b 1928 }
f1665b21 1929
1bc22652 1930 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1931 if (ret < 0) {
f1665b21 1932 return ret;
b9bec74b 1933 }
f1665b21 1934
b9bec74b 1935 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1936 /* Only support xcr0 now */
0fd53fec
PB		 1937 if (xcrs.xcrs[i].xcr == 0) {
1938 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1939 break;
1940 }
b9bec74b 1941 }
f1665b21 1942 return 0;
f1665b21
SY		 1943}
1944
1bc22652 1945static int kvm_get_sregs(X86CPU *cpu)
05330448 1946{
1bc22652 1947 CPUX86State *env = &cpu->env;
05330448
AL		 1948 struct kvm_sregs sregs;
1949 uint32_t hflags;
0e607a80 1950 int bit, i, ret;
05330448 1951
1bc22652 1952 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1953 if (ret < 0) {
05330448 1954 return ret;
b9bec74b 1955 }
05330448 1956
0e607a80
JK		 1957 /* There can only be one pending IRQ set in the bitmap at a time, so try
1958 to find it and save its number instead (-1 for none). */
1959 env->interrupt_injected = -1;
1960 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1961 if (sregs.interrupt_bitmap[i]) {
1962 bit = ctz64(sregs.interrupt_bitmap[i]);
1963 env->interrupt_injected = i * 64 + bit;
1964 break;
1965 }
1966 }
05330448
AL		 1967
1968 get_seg(&env->segs[R_CS], &sregs.cs);
1969 get_seg(&env->segs[R_DS], &sregs.ds);
1970 get_seg(&env->segs[R_ES], &sregs.es);
1971 get_seg(&env->segs[R_FS], &sregs.fs);
1972 get_seg(&env->segs[R_GS], &sregs.gs);
1973 get_seg(&env->segs[R_SS], &sregs.ss);
1974
1975 get_seg(&env->tr, &sregs.tr);
1976 get_seg(&env->ldt, &sregs.ldt);
1977
1978 env->idt.limit = sregs.idt.limit;
1979 env->idt.base = sregs.idt.base;
1980 env->gdt.limit = sregs.gdt.limit;
1981 env->gdt.base = sregs.gdt.base;
1982
1983 env->cr[0] = sregs.cr0;
1984 env->cr[2] = sregs.cr2;
1985 env->cr[3] = sregs.cr3;
1986 env->cr[4] = sregs.cr4;
1987
05330448 1988 env->efer = sregs.efer;
cce47516
JK		 1989
1990 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
05330448 1991
b9bec74b
JK		 1992#define HFLAG_COPY_MASK \
1993 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1994 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1995 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1996 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
05330448 1997
19dc85db
RH		 1998 hflags = env->hflags & HFLAG_COPY_MASK;
1999 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
05330448
AL		 2000 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
2001 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
b9bec74b 2002 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
05330448 2003 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
19dc85db
RH		 2004
2005 if (env->cr[4] & CR4_OSFXSR_MASK) {
2006 hflags |= HF_OSFXSR_MASK;
2007 }
05330448
AL		 2008
2009 if (env->efer & MSR_EFER_LMA) {
2010 hflags |= HF_LMA_MASK;
2011 }
2012
2013 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
2014 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
2015 } else {
2016 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
b9bec74b 2017 (DESC_B_SHIFT - HF_CS32_SHIFT);
05330448 2018 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
b9bec74b
JK		 2019 (DESC_B_SHIFT - HF_SS32_SHIFT);
2020 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
2021 !(hflags & HF_CS32_MASK)) {
2022 hflags |= HF_ADDSEG_MASK;
2023 } else {
2024 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
2025 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
2026 }
05330448 2027 }
19dc85db 2028 env->hflags = hflags;
05330448
AL		 2029
2030 return 0;
2031}
2032
1bc22652 2033static int kvm_get_msrs(X86CPU *cpu)
05330448 2034{
1bc22652 2035 CPUX86State *env = &cpu->env;
d71b62a1 2036 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2037 int ret, i;
fcc35e7c 2038 uint64_t mtrr_top_bits;
05330448 2039
d71b62a1
EH		 2040 kvm_msr_buf_reset(cpu);
2041
9c600a84
EH		 2042 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2043 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2044 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2045 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2046 if (has_msr_star) {
9c600a84 2047 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2048 }
c3a3a7d3 2049 if (has_msr_hsave_pa) {
9c600a84 2050 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2051 }
c9b8f6b6 2052 if (has_msr_tsc_aux) {
9c600a84 2053 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2054 }
f28558d3 2055 if (has_msr_tsc_adjust) {
9c600a84 2056 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2057 }
aa82ba54 2058 if (has_msr_tsc_deadline) {
9c600a84 2059 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2060 }
21e87c46 2061 if (has_msr_misc_enable) {
9c600a84 2062 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2063 }
fc12d72e 2064 if (has_msr_smbase) {
9c600a84 2065 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2066 }
df67696e 2067 if (has_msr_feature_control) {
9c600a84 2068 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2069 }
79e9ebeb 2070 if (has_msr_bndcfgs) {
9c600a84 2071 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2072 }
18cd2c17 2073 if (has_msr_xss) {
9c600a84 2074 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17
WL		 2075 }
2076
b8cc45d6
GC		 2077
2078 if (!env->tsc_valid) {
9c600a84 2079 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2080 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2081 }
2082
05330448 2083#ifdef TARGET_X86_64
25d2e361 2084 if (lm_capable_kernel) {
9c600a84
EH		 2085 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2086 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2087 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2088 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2089 }
05330448 2090#endif
9c600a84
EH		 2091 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2092 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2093 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2094 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2095 }
55c911a5 2096 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2097 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2098 }
55c911a5 2099 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2100 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2101 }
0d894367 2102 if (has_msr_architectural_pmu) {
9c600a84
EH		 2103 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2104 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2105 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2106 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
0d894367 2107 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 2108 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367
PB		 2109 }
2110 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84
EH		 2111 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2112 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2113 }
2114 }
1a03675d 2115
57780495 2116 if (env->mcg_cap) {
9c600a84
EH		 2117 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2118 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2119 if (has_msr_mcg_ext_ctl) {
2120 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2121 }
b9bec74b 2122 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2123 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2124 }
57780495 2125 }
57780495 2126
1c90ef26 2127 if (has_msr_hv_hypercall) {
9c600a84
EH		 2128 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2129 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2130 }
2d5aa872 2131 if (cpu->hyperv_vapic) {
9c600a84 2132 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2133 }
3ddcd2ed 2134 if (cpu->hyperv_time) {
9c600a84 2135 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2136 }
f2a53c9e
AS		 2137 if (has_msr_hv_crash) {
2138 int j;
2139
2140 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
9c600a84 2141 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2142 }
2143 }
46eb8f98 2144 if (has_msr_hv_runtime) {
9c600a84 2145 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2146 }
866eea9a
AS		 2147 if (cpu->hyperv_synic) {
2148 uint32_t msr;
2149
9c600a84
EH		 2150 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2151 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2152 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2153 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2154 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2155 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2156 }
2157 }
ff99aa64
AS		 2158 if (has_msr_hv_stimer) {
2159 uint32_t msr;
2160
2161 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2162 msr++) {
9c600a84 2163 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2164 }
2165 }
1eabfce6 2166 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2167 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2168 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2169 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2170 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2171 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2172 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2173 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2174 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2175 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2176 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2177 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2178 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2179 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2180 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2181 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2182 }
2183 }
5ef68987 2184
d71b62a1 2185 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2186 if (ret < 0) {
05330448 2187 return ret;
b9bec74b 2188 }
05330448 2189
9c600a84 2190 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2191 /*
2192 * MTRR masks: Each mask consists of 5 parts
2193 * a 10..0: must be zero
2194 * b 11 : valid bit
2195 * c n-1.12: actual mask bits
2196 * d 51..n: reserved must be zero
2197 * e 63.52: reserved must be zero
2198 *
2199 * 'n' is the number of physical bits supported by the CPU and is
2200 * apparently always <= 52. We know our 'n' but don't know what
2201 * the destinations 'n' is; it might be smaller, in which case
2202 * it masks (c) on loading. It might be larger, in which case
2203 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2204 * we're migrating to.
2205 */
2206
2207 if (cpu->fill_mtrr_mask) {
2208 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2209 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2210 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2211 } else {
2212 mtrr_top_bits = 0;
2213 }
2214
05330448 2215 for (i = 0; i < ret; i++) {
0d894367
PB		 2216 uint32_t index = msrs[i].index;
2217 switch (index) {
05330448
AL		 2218 case MSR_IA32_SYSENTER_CS:
2219 env->sysenter_cs = msrs[i].data;
2220 break;
2221 case MSR_IA32_SYSENTER_ESP:
2222 env->sysenter_esp = msrs[i].data;
2223 break;
2224 case MSR_IA32_SYSENTER_EIP:
2225 env->sysenter_eip = msrs[i].data;
2226 break;
0c03266a
JK		 2227 case MSR_PAT:
2228 env->pat = msrs[i].data;
2229 break;
05330448
AL		 2230 case MSR_STAR:
2231 env->star = msrs[i].data;
2232 break;
2233#ifdef TARGET_X86_64
2234 case MSR_CSTAR:
2235 env->cstar = msrs[i].data;
2236 break;
2237 case MSR_KERNELGSBASE:
2238 env->kernelgsbase = msrs[i].data;
2239 break;
2240 case MSR_FMASK:
2241 env->fmask = msrs[i].data;
2242 break;
2243 case MSR_LSTAR:
2244 env->lstar = msrs[i].data;
2245 break;
2246#endif
2247 case MSR_IA32_TSC:
2248 env->tsc = msrs[i].data;
2249 break;
c9b8f6b6
AS		 2250 case MSR_TSC_AUX:
2251 env->tsc_aux = msrs[i].data;
2252 break;
f28558d3
WA		 2253 case MSR_TSC_ADJUST:
2254 env->tsc_adjust = msrs[i].data;
2255 break;
aa82ba54
LJ		 2256 case MSR_IA32_TSCDEADLINE:
2257 env->tsc_deadline = msrs[i].data;
2258 break;
aa851e36
MT		 2259 case MSR_VM_HSAVE_PA:
2260 env->vm_hsave = msrs[i].data;
2261 break;
1a03675d
GC		 2262 case MSR_KVM_SYSTEM_TIME:
2263 env->system_time_msr = msrs[i].data;
2264 break;
2265 case MSR_KVM_WALL_CLOCK:
2266 env->wall_clock_msr = msrs[i].data;
2267 break;
57780495
MT		 2268 case MSR_MCG_STATUS:
2269 env->mcg_status = msrs[i].data;
2270 break;
2271 case MSR_MCG_CTL:
2272 env->mcg_ctl = msrs[i].data;
2273 break;
87f8b626
AR		 2274 case MSR_MCG_EXT_CTL:
2275 env->mcg_ext_ctl = msrs[i].data;
2276 break;
21e87c46
AK		 2277 case MSR_IA32_MISC_ENABLE:
2278 env->msr_ia32_misc_enable = msrs[i].data;
2279 break;
fc12d72e
PB		 2280 case MSR_IA32_SMBASE:
2281 env->smbase = msrs[i].data;
2282 break;
0779caeb
ACL		 2283 case MSR_IA32_FEATURE_CONTROL:
2284 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2285 break;
79e9ebeb
LJ		 2286 case MSR_IA32_BNDCFGS:
2287 env->msr_bndcfgs = msrs[i].data;
2288 break;
18cd2c17
WL		 2289 case MSR_IA32_XSS:
2290 env->xss = msrs[i].data;
2291 break;
57780495 2292 default:
57780495
MT		 2293 if (msrs[i].index >= MSR_MC0_CTL &&
2294 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2295 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2296 }
d8da8574 2297 break;
f6584ee2
GN		 2298 case MSR_KVM_ASYNC_PF_EN:
2299 env->async_pf_en_msr = msrs[i].data;
2300 break;
bc9a839d
MT		 2301 case MSR_KVM_PV_EOI_EN:
2302 env->pv_eoi_en_msr = msrs[i].data;
2303 break;
917367aa
MT		 2304 case MSR_KVM_STEAL_TIME:
2305 env->steal_time_msr = msrs[i].data;
2306 break;
0d894367
PB		 2307 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2308 env->msr_fixed_ctr_ctrl = msrs[i].data;
2309 break;
2310 case MSR_CORE_PERF_GLOBAL_CTRL:
2311 env->msr_global_ctrl = msrs[i].data;
2312 break;
2313 case MSR_CORE_PERF_GLOBAL_STATUS:
2314 env->msr_global_status = msrs[i].data;
2315 break;
2316 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2317 env->msr_global_ovf_ctrl = msrs[i].data;
2318 break;
2319 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2320 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2321 break;
2322 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2323 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2324 break;
2325 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2326 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2327 break;
1c90ef26
VR		 2328 case HV_X64_MSR_HYPERCALL:
2329 env->msr_hv_hypercall = msrs[i].data;
2330 break;
2331 case HV_X64_MSR_GUEST_OS_ID:
2332 env->msr_hv_guest_os_id = msrs[i].data;
2333 break;
5ef68987
VR		 2334 case HV_X64_MSR_APIC_ASSIST_PAGE:
2335 env->msr_hv_vapic = msrs[i].data;
2336 break;
48a5f3bc
VR		 2337 case HV_X64_MSR_REFERENCE_TSC:
2338 env->msr_hv_tsc = msrs[i].data;
2339 break;
f2a53c9e
AS		 2340 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2341 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2342 break;
46eb8f98
AS		 2343 case HV_X64_MSR_VP_RUNTIME:
2344 env->msr_hv_runtime = msrs[i].data;
2345 break;
866eea9a
AS		 2346 case HV_X64_MSR_SCONTROL:
2347 env->msr_hv_synic_control = msrs[i].data;
2348 break;
2349 case HV_X64_MSR_SVERSION:
2350 env->msr_hv_synic_version = msrs[i].data;
2351 break;
2352 case HV_X64_MSR_SIEFP:
2353 env->msr_hv_synic_evt_page = msrs[i].data;
2354 break;
2355 case HV_X64_MSR_SIMP:
2356 env->msr_hv_synic_msg_page = msrs[i].data;
2357 break;
2358 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2359 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2360 break;
2361 case HV_X64_MSR_STIMER0_CONFIG:
2362 case HV_X64_MSR_STIMER1_CONFIG:
2363 case HV_X64_MSR_STIMER2_CONFIG:
2364 case HV_X64_MSR_STIMER3_CONFIG:
2365 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2366 msrs[i].data;
2367 break;
2368 case HV_X64_MSR_STIMER0_COUNT:
2369 case HV_X64_MSR_STIMER1_COUNT:
2370 case HV_X64_MSR_STIMER2_COUNT:
2371 case HV_X64_MSR_STIMER3_COUNT:
2372 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2373 msrs[i].data;
866eea9a 2374 break;
d1ae67f6
AW		 2375 case MSR_MTRRdefType:
2376 env->mtrr_deftype = msrs[i].data;
2377 break;
2378 case MSR_MTRRfix64K_00000:
2379 env->mtrr_fixed[0] = msrs[i].data;
2380 break;
2381 case MSR_MTRRfix16K_80000:
2382 env->mtrr_fixed[1] = msrs[i].data;
2383 break;
2384 case MSR_MTRRfix16K_A0000:
2385 env->mtrr_fixed[2] = msrs[i].data;
2386 break;
2387 case MSR_MTRRfix4K_C0000:
2388 env->mtrr_fixed[3] = msrs[i].data;
2389 break;
2390 case MSR_MTRRfix4K_C8000:
2391 env->mtrr_fixed[4] = msrs[i].data;
2392 break;
2393 case MSR_MTRRfix4K_D0000:
2394 env->mtrr_fixed[5] = msrs[i].data;
2395 break;
2396 case MSR_MTRRfix4K_D8000:
2397 env->mtrr_fixed[6] = msrs[i].data;
2398 break;
2399 case MSR_MTRRfix4K_E0000:
2400 env->mtrr_fixed[7] = msrs[i].data;
2401 break;
2402 case MSR_MTRRfix4K_E8000:
2403 env->mtrr_fixed[8] = msrs[i].data;
2404 break;
2405 case MSR_MTRRfix4K_F0000:
2406 env->mtrr_fixed[9] = msrs[i].data;
2407 break;
2408 case MSR_MTRRfix4K_F8000:
2409 env->mtrr_fixed[10] = msrs[i].data;
2410 break;
2411 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2412 if (index & 1) {
fcc35e7c
DDAG		 2413 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2414 mtrr_top_bits;
d1ae67f6
AW		 2415 } else {
2416 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2417 }
2418 break;
05330448
AL		 2419 }
2420 }
2421
2422 return 0;
2423}
2424
1bc22652 2425static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2426{
1bc22652 2427 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2428
1bc22652 2429 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2430}
2431
23d02d9b 2432static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2433{
259186a7 2434 CPUState *cs = CPU(cpu);
23d02d9b 2435 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2436 struct kvm_mp_state mp_state;
2437 int ret;
2438
259186a7 2439 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2440 if (ret < 0) {
2441 return ret;
2442 }
2443 env->mp_state = mp_state.mp_state;
c14750e8 2444 if (kvm_irqchip_in_kernel()) {
259186a7 2445 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2446 }
9bdbe550
HB		 2447 return 0;
2448}
2449
1bc22652 2450static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2451{
02e51483 2452 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2453 struct kvm_lapic_state kapic;
2454 int ret;
2455
3d4b2649 2456 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2457 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2458 if (ret < 0) {
2459 return ret;
2460 }
2461
2462 kvm_get_apic_state(apic, &kapic);
2463 }
2464 return 0;
2465}
2466
1bc22652 2467static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2468{
fc12d72e 2469 CPUState *cs = CPU(cpu);
1bc22652 2470 CPUX86State *env = &cpu->env;
076796f8 2471 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2472
2473 if (!kvm_has_vcpu_events()) {
2474 return 0;
2475 }
2476
31827373
JK		 2477 events.exception.injected = (env->exception_injected >= 0);
2478 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2479 events.exception.has_error_code = env->has_error_code;
2480 events.exception.error_code = env->error_code;
7e680753 2481 events.exception.pad = 0;
a0fb002c
JK		 2482
2483 events.interrupt.injected = (env->interrupt_injected >= 0);
2484 events.interrupt.nr = env->interrupt_injected;
2485 events.interrupt.soft = env->soft_interrupt;
2486
2487 events.nmi.injected = env->nmi_injected;
2488 events.nmi.pending = env->nmi_pending;
2489 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2490 events.nmi.pad = 0;
a0fb002c
JK		 2491
2492 events.sipi_vector = env->sipi_vector;
68c6efe0 2493 events.flags = 0;
a0fb002c 2494
fc12d72e
PB		 2495 if (has_msr_smbase) {
2496 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2497 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2498 if (kvm_irqchip_in_kernel()) {
2499 /* As soon as these are moved to the kernel, remove them
2500 * from cs->interrupt_request.
2501 */
2502 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2503 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2504 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2505 } else {
2506 /* Keep these in cs->interrupt_request. */
2507 events.smi.pending = 0;
2508 events.smi.latched_init = 0;
2509 }
2510 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2511 }
2512
ea643051
JK		 2513 if (level >= KVM_PUT_RESET_STATE) {
2514 events.flags |=
2515 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2516 }
aee028b9 2517
1bc22652 2518 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2519}
2520
1bc22652 2521static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2522{
1bc22652 2523 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2524 struct kvm_vcpu_events events;
2525 int ret;
2526
2527 if (!kvm_has_vcpu_events()) {
2528 return 0;
2529 }
2530
fc12d72e 2531 memset(&events, 0, sizeof(events));
1bc22652 2532 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2533 if (ret < 0) {
2534 return ret;
2535 }
31827373 2536 env->exception_injected =
a0fb002c
JK		 2537 events.exception.injected ? events.exception.nr : -1;
2538 env->has_error_code = events.exception.has_error_code;
2539 env->error_code = events.exception.error_code;
2540
2541 env->interrupt_injected =
2542 events.interrupt.injected ? events.interrupt.nr : -1;
2543 env->soft_interrupt = events.interrupt.soft;
2544
2545 env->nmi_injected = events.nmi.injected;
2546 env->nmi_pending = events.nmi.pending;
2547 if (events.nmi.masked) {
2548 env->hflags2 |= HF2_NMI_MASK;
2549 } else {
2550 env->hflags2 &= ~HF2_NMI_MASK;
2551 }
2552
fc12d72e
PB		 2553 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2554 if (events.smi.smm) {
2555 env->hflags |= HF_SMM_MASK;
2556 } else {
2557 env->hflags &= ~HF_SMM_MASK;
2558 }
2559 if (events.smi.pending) {
2560 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2561 } else {
2562 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2563 }
2564 if (events.smi.smm_inside_nmi) {
2565 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2566 } else {
2567 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2568 }
2569 if (events.smi.latched_init) {
2570 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2571 } else {
2572 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2573 }
2574 }
2575
a0fb002c 2576 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2577
2578 return 0;
2579}
2580
1bc22652 2581static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2582{
ed2803da 2583 CPUState *cs = CPU(cpu);
1bc22652 2584 CPUX86State *env = &cpu->env;
b0b1d690 2585 int ret = 0;
b0b1d690
JK		 2586 unsigned long reinject_trap = 0;
2587
2588 if (!kvm_has_vcpu_events()) {
2589 if (env->exception_injected == 1) {
2590 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2591 } else if (env->exception_injected == 3) {
2592 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2593 }
2594 env->exception_injected = -1;
2595 }
2596
2597 /*
2598 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2599 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2600 * by updating the debug state once again if single-stepping is on.
2601 * Another reason to call kvm_update_guest_debug here is a pending debug
2602 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2603 * reinject them via SET_GUEST_DEBUG.
2604 */
2605 if (reinject_trap ||
ed2803da 2606 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2607 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2608 }
b0b1d690
JK		 2609 return ret;
2610}
2611
1bc22652 2612static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2613{
1bc22652 2614 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2615 struct kvm_debugregs dbgregs;
2616 int i;
2617
2618 if (!kvm_has_debugregs()) {
2619 return 0;
2620 }
2621
2622 for (i = 0; i < 4; i++) {
2623 dbgregs.db[i] = env->dr[i];
2624 }
2625 dbgregs.dr6 = env->dr[6];
2626 dbgregs.dr7 = env->dr[7];
2627 dbgregs.flags = 0;
2628
1bc22652 2629 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2630}
2631
1bc22652 2632static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2633{
1bc22652 2634 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2635 struct kvm_debugregs dbgregs;
2636 int i, ret;
2637
2638 if (!kvm_has_debugregs()) {
2639 return 0;
2640 }
2641
1bc22652 2642 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2643 if (ret < 0) {
b9bec74b 2644 return ret;
ff44f1a3
JK		 2645 }
2646 for (i = 0; i < 4; i++) {
2647 env->dr[i] = dbgregs.db[i];
2648 }
2649 env->dr[4] = env->dr[6] = dbgregs.dr6;
2650 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2651
2652 return 0;
2653}
2654
20d695a9 2655int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2656{
20d695a9 2657 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2658 int ret;
2659
2fa45344 2660 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2661
48e1a45c 2662 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2663 ret = kvm_put_msr_feature_control(x86_cpu);
2664 if (ret < 0) {
2665 return ret;
2666 }
2667 }
2668
36f96c4b
HZ		 2669 if (level == KVM_PUT_FULL_STATE) {
2670 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2671 * because TSC frequency mismatch shouldn't abort migration,
2672 * unless the user explicitly asked for a more strict TSC
2673 * setting (e.g. using an explicit "tsc-freq" option).
2674 */
2675 kvm_arch_set_tsc_khz(cpu);
2676 }
2677
1bc22652 2678 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2679 if (ret < 0) {
05330448 2680 return ret;
b9bec74b 2681 }
1bc22652 2682 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2683 if (ret < 0) {
f1665b21 2684 return ret;
b9bec74b 2685 }
1bc22652 2686 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2687 if (ret < 0) {
05330448 2688 return ret;
b9bec74b 2689 }
1bc22652 2690 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2691 if (ret < 0) {
05330448 2692 return ret;
b9bec74b 2693 }
ab443475 2694 /* must be before kvm_put_msrs */
1bc22652 2695 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2696 if (ret < 0) {
2697 return ret;
2698 }
1bc22652 2699 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2700 if (ret < 0) {
05330448 2701 return ret;
b9bec74b 2702 }
ea643051 2703 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2704 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2705 if (ret < 0) {
680c1c6f
JK		 2706 return ret;
2707 }
ea643051 2708 }
7477cd38
MT		 2709
2710 ret = kvm_put_tscdeadline_msr(x86_cpu);
2711 if (ret < 0) {
2712 return ret;
2713 }
2714
1bc22652 2715 ret = kvm_put_vcpu_events(x86_cpu, level);
b9bec74b 2716 if (ret < 0) {
a0fb002c 2717 return ret;
b9bec74b 2718 }
1bc22652 2719 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2720 if (ret < 0) {
b0b1d690 2721 return ret;
b9bec74b 2722 }
b0b1d690 2723 /* must be last */
1bc22652 2724 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2725 if (ret < 0) {
ff44f1a3 2726 return ret;
b9bec74b 2727 }
05330448
AL		 2728 return 0;
2729}
2730
20d695a9 2731int kvm_arch_get_registers(CPUState *cs)
05330448 2732{
20d695a9 2733 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2734 int ret;
2735
20d695a9 2736 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2737
1bc22652 2738 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2739 if (ret < 0) {
f4f1110e 2740 goto out;
b9bec74b 2741 }
1bc22652 2742 ret = kvm_get_xsave(cpu);
b9bec74b 2743 if (ret < 0) {
f4f1110e 2744 goto out;
b9bec74b 2745 }
1bc22652 2746 ret = kvm_get_xcrs(cpu);
b9bec74b 2747 if (ret < 0) {
f4f1110e 2748 goto out;
b9bec74b 2749 }
1bc22652 2750 ret = kvm_get_sregs(cpu);
b9bec74b 2751 if (ret < 0) {
f4f1110e 2752 goto out;
b9bec74b 2753 }
1bc22652 2754 ret = kvm_get_msrs(cpu);
b9bec74b 2755 if (ret < 0) {
f4f1110e 2756 goto out;
b9bec74b 2757 }
23d02d9b 2758 ret = kvm_get_mp_state(cpu);
b9bec74b 2759 if (ret < 0) {
f4f1110e 2760 goto out;
b9bec74b 2761 }
1bc22652 2762 ret = kvm_get_apic(cpu);
680c1c6f 2763 if (ret < 0) {
f4f1110e 2764 goto out;
680c1c6f 2765 }
1bc22652 2766 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2767 if (ret < 0) {
f4f1110e 2768 goto out;
b9bec74b 2769 }
1bc22652 2770 ret = kvm_get_debugregs(cpu);
b9bec74b 2771 if (ret < 0) {
f4f1110e 2772 goto out;
b9bec74b 2773 }
f4f1110e
RH		 2774 ret = 0;
2775 out:
2776 cpu_sync_bndcs_hflags(&cpu->env);
2777 return ret;
05330448
AL		 2778}
2779
20d695a9 2780void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2781{
20d695a9
AF		 2782 X86CPU *x86_cpu = X86_CPU(cpu);
2783 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2784 int ret;
2785
276ce815 2786 /* Inject NMI */
fc12d72e
PB		 2787 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2788 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2789 qemu_mutex_lock_iothread();
2790 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2791 qemu_mutex_unlock_iothread();
2792 DPRINTF("injected NMI\n");
2793 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2794 if (ret < 0) {
2795 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2796 strerror(-ret));
2797 }
2798 }
2799 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2800 qemu_mutex_lock_iothread();
2801 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2802 qemu_mutex_unlock_iothread();
2803 DPRINTF("injected SMI\n");
2804 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2805 if (ret < 0) {
2806 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2807 strerror(-ret));
2808 }
ce377af3 2809 }
276ce815
LJ		 2810 }
2811
15eafc2e 2812 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2813 qemu_mutex_lock_iothread();
2814 }
2815
e0723c45
PB		 2816 /* Force the VCPU out of its inner loop to process any INIT requests
2817 * or (for userspace APIC, but it is cheap to combine the checks here)
2818 * pending TPR access reports.
2819 */
2820 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2821 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2822 !(env->hflags & HF_SMM_MASK)) {
2823 cpu->exit_request = 1;
2824 }
2825 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2826 cpu->exit_request = 1;
2827 }
e0723c45 2828 }
05330448 2829
15eafc2e 2830 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 2831 /* Try to inject an interrupt if the guest can accept it */
2832 if (run->ready_for_interrupt_injection &&
259186a7 2833 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2834 (env->eflags & IF_MASK)) {
2835 int irq;
2836
259186a7 2837 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2838 irq = cpu_get_pic_interrupt(env);
2839 if (irq >= 0) {
2840 struct kvm_interrupt intr;
2841
2842 intr.irq = irq;
db1669bc 2843 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2844 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2845 if (ret < 0) {
2846 fprintf(stderr,
2847 "KVM: injection failed, interrupt lost (%s)\n",
2848 strerror(-ret));
2849 }
db1669bc
JK		 2850 }
2851 }
05330448 2852
db1669bc
JK		 2853 /* If we have an interrupt but the guest is not ready to receive an
2854 * interrupt, request an interrupt window exit. This will
2855 * cause a return to userspace as soon as the guest is ready to
2856 * receive interrupts. */
259186a7 2857 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2858 run->request_interrupt_window = 1;
2859 } else {
2860 run->request_interrupt_window = 0;
2861 }
2862
2863 DPRINTF("setting tpr\n");
02e51483 2864 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2865
2866 qemu_mutex_unlock_iothread();
db1669bc 2867 }
05330448
AL		 2868}
2869
4c663752 2870MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2871{
20d695a9
AF		 2872 X86CPU *x86_cpu = X86_CPU(cpu);
2873 CPUX86State *env = &x86_cpu->env;
2874
fc12d72e
PB		 2875 if (run->flags & KVM_RUN_X86_SMM) {
2876 env->hflags |= HF_SMM_MASK;
2877 } else {
f5c052b9 2878 env->hflags &= ~HF_SMM_MASK;
fc12d72e 2879 }
b9bec74b 2880 if (run->if_flag) {
05330448 2881 env->eflags |= IF_MASK;
b9bec74b 2882 } else {
05330448 2883 env->eflags &= ~IF_MASK;
b9bec74b 2884 }
4b8523ee
JK		 2885
2886 /* We need to protect the apic state against concurrent accesses from
2887 * different threads in case the userspace irqchip is used. */
2888 if (!kvm_irqchip_in_kernel()) {
2889 qemu_mutex_lock_iothread();
2890 }
02e51483
CF		 2891 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2892 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2893 if (!kvm_irqchip_in_kernel()) {
2894 qemu_mutex_unlock_iothread();
2895 }
f794aa4a 2896 return cpu_get_mem_attrs(env);
05330448
AL		 2897}
2898
20d695a9 2899int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2900{
20d695a9
AF		 2901 X86CPU *cpu = X86_CPU(cs);
2902 CPUX86State *env = &cpu->env;
232fc23b 2903
259186a7 2904 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2905 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2906 assert(env->mcg_cap);
2907
259186a7 2908 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2909
dd1750d7 2910 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2911
2912 if (env->exception_injected == EXCP08_DBLE) {
2913 /* this means triple fault */
2914 qemu_system_reset_request();
fcd7d003 2915 cs->exit_request = 1;
ab443475
JK		 2916 return 0;
2917 }
2918 env->exception_injected = EXCP12_MCHK;
2919 env->has_error_code = 0;
2920
259186a7 2921 cs->halted = 0;
ab443475
JK		 2922 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2923 env->mp_state = KVM_MP_STATE_RUNNABLE;
2924 }
2925 }
2926
fc12d72e
PB		 2927 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2928 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2929 kvm_cpu_synchronize_state(cs);
2930 do_cpu_init(cpu);
2931 }
2932
db1669bc
JK		 2933 if (kvm_irqchip_in_kernel()) {
2934 return 0;
2935 }
2936
259186a7
AF		 2937 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2938 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2939 apic_poll_irq(cpu->apic_state);
5d62c43a 2940 }
259186a7 2941 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2942 (env->eflags & IF_MASK)) ||
259186a7
AF		 2943 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2944 cs->halted = 0;
6792a57b 2945 }
259186a7 2946 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2947 kvm_cpu_synchronize_state(cs);
232fc23b 2948 do_cpu_sipi(cpu);
0af691d7 2949 }
259186a7
AF		 2950 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2951 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2952 kvm_cpu_synchronize_state(cs);
02e51483 2953 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2954 env->tpr_access_type);
2955 }
0af691d7 2956
259186a7 2957 return cs->halted;
0af691d7
MT		 2958}
2959
839b5630 2960static int kvm_handle_halt(X86CPU *cpu)
05330448 2961{
259186a7 2962 CPUState *cs = CPU(cpu);
839b5630
AF		 2963 CPUX86State *env = &cpu->env;
2964
259186a7 2965 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2966 (env->eflags & IF_MASK)) &&
259186a7
AF		 2967 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2968 cs->halted = 1;
bb4ea393 2969 return EXCP_HLT;
05330448
AL		 2970 }
2971
bb4ea393 2972 return 0;
05330448
AL		 2973}
2974
f7575c96 2975static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 2976{
f7575c96
AF		 2977 CPUState *cs = CPU(cpu);
2978 struct kvm_run *run = cs->kvm_run;
d362e757 2979
02e51483 2980 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 2981 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2982 : TPR_ACCESS_READ);
2983 return 1;
2984}
2985
f17ec444 2986int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 2987{
38972938 2988 static const uint8_t int3 = 0xcc;
64bf3f4e 2989
f17ec444
AF		 2990 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2991 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 2992 return -EINVAL;
b9bec74b 2993 }
e22a25c9
AL		 2994 return 0;
2995}
2996
f17ec444 2997int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 2998{
2999 uint8_t int3;
3000
f17ec444
AF		 3001 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3002 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3003 return -EINVAL;
b9bec74b 3004 }
e22a25c9
AL		 3005 return 0;
3006}
3007
3008static struct {
3009 target_ulong addr;
3010 int len;
3011 int type;
3012} hw_breakpoint[4];
3013
3014static int nb_hw_breakpoint;
3015
3016static int find_hw_breakpoint(target_ulong addr, int len, int type)
3017{
3018 int n;
3019
b9bec74b 3020 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3021 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3022 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3023 return n;
b9bec74b
JK		 3024 }
3025 }
e22a25c9
AL		 3026 return -1;
3027}
3028
3029int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3030 target_ulong len, int type)
3031{
3032 switch (type) {
3033 case GDB_BREAKPOINT_HW:
3034 len = 1;
3035 break;
3036 case GDB_WATCHPOINT_WRITE:
3037 case GDB_WATCHPOINT_ACCESS:
3038 switch (len) {
3039 case 1:
3040 break;
3041 case 2:
3042 case 4:
3043 case 8:
b9bec74b 3044 if (addr & (len - 1)) {
e22a25c9 3045 return -EINVAL;
b9bec74b 3046 }
e22a25c9
AL		 3047 break;
3048 default:
3049 return -EINVAL;
3050 }
3051 break;
3052 default:
3053 return -ENOSYS;
3054 }
3055
b9bec74b 3056 if (nb_hw_breakpoint == 4) {
e22a25c9 3057 return -ENOBUFS;
b9bec74b
JK		 3058 }
3059 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3060 return -EEXIST;
b9bec74b 3061 }
e22a25c9
AL		 3062 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3063 hw_breakpoint[nb_hw_breakpoint].len = len;
3064 hw_breakpoint[nb_hw_breakpoint].type = type;
3065 nb_hw_breakpoint++;
3066
3067 return 0;
3068}
3069
3070int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3071 target_ulong len, int type)
3072{
3073 int n;
3074
3075 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3076 if (n < 0) {
e22a25c9 3077 return -ENOENT;
b9bec74b 3078 }
e22a25c9
AL		 3079 nb_hw_breakpoint--;
3080 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3081
3082 return 0;
3083}
3084
3085void kvm_arch_remove_all_hw_breakpoints(void)
3086{
3087 nb_hw_breakpoint = 0;
3088}
3089
3090static CPUWatchpoint hw_watchpoint;
3091
a60f24b5 3092static int kvm_handle_debug(X86CPU *cpu,
48405526 3093 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3094{
ed2803da 3095 CPUState *cs = CPU(cpu);
a60f24b5 3096 CPUX86State *env = &cpu->env;
f2574737 3097 int ret = 0;
e22a25c9
AL		 3098 int n;
3099
3100 if (arch_info->exception == 1) {
3101 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3102 if (cs->singlestep_enabled) {
f2574737 3103 ret = EXCP_DEBUG;
b9bec74b 3104 }
e22a25c9 3105 } else {
b9bec74b
JK		 3106 for (n = 0; n < 4; n++) {
3107 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3108 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3109 case 0x0:
f2574737 3110 ret = EXCP_DEBUG;
e22a25c9
AL		 3111 break;
3112 case 0x1:
f2574737 3113 ret = EXCP_DEBUG;
ff4700b0 3114 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3115 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3116 hw_watchpoint.flags = BP_MEM_WRITE;
3117 break;
3118 case 0x3:
f2574737 3119 ret = EXCP_DEBUG;
ff4700b0 3120 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3121 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3122 hw_watchpoint.flags = BP_MEM_ACCESS;
3123 break;
3124 }
b9bec74b
JK		 3125 }
3126 }
e22a25c9 3127 }
ff4700b0 3128 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3129 ret = EXCP_DEBUG;
b9bec74b 3130 }
f2574737 3131 if (ret == 0) {
ff4700b0 3132 cpu_synchronize_state(cs);
48405526 3133 assert(env->exception_injected == -1);
b0b1d690 3134
f2574737 3135 /* pass to guest */
48405526
BS		 3136 env->exception_injected = arch_info->exception;
3137 env->has_error_code = 0;
b0b1d690 3138 }
e22a25c9 3139
f2574737 3140 return ret;
e22a25c9
AL		 3141}
3142
20d695a9 3143void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3144{
3145 const uint8_t type_code[] = {
3146 [GDB_BREAKPOINT_HW] = 0x0,
3147 [GDB_WATCHPOINT_WRITE] = 0x1,
3148 [GDB_WATCHPOINT_ACCESS] = 0x3
3149 };
3150 const uint8_t len_code[] = {
3151 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3152 };
3153 int n;
3154
a60f24b5 3155 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3156 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3157 }
e22a25c9
AL		 3158 if (nb_hw_breakpoint > 0) {
3159 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3160 dbg->arch.debugreg[7] = 0x0600;
3161 for (n = 0; n < nb_hw_breakpoint; n++) {
3162 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3163 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3164 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3165 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3166 }
3167 }
3168}
4513d923 3169
2a4dac83
JK		 3170static bool host_supports_vmx(void)
3171{
3172 uint32_t ecx, unused;
3173
3174 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3175 return ecx & CPUID_EXT_VMX;
3176}
3177
3178#define VMX_INVALID_GUEST_STATE 0x80000021
3179
20d695a9 3180int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3181{
20d695a9 3182 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3183 uint64_t code;
3184 int ret;
3185
3186 switch (run->exit_reason) {
3187 case KVM_EXIT_HLT:
3188 DPRINTF("handle_hlt\n");
4b8523ee 3189 qemu_mutex_lock_iothread();
839b5630 3190 ret = kvm_handle_halt(cpu);
4b8523ee 3191 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3192 break;
3193 case KVM_EXIT_SET_TPR:
3194 ret = 0;
3195 break;
d362e757 3196 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3197 qemu_mutex_lock_iothread();
f7575c96 3198 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3199 qemu_mutex_unlock_iothread();
d362e757 3200 break;
2a4dac83
JK		 3201 case KVM_EXIT_FAIL_ENTRY:
3202 code = run->fail_entry.hardware_entry_failure_reason;
3203 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3204 code);
3205 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3206 fprintf(stderr,
12619721 3207 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3208 "unrestricted mode\n"
3209 "support, the failure can be most likely due to the guest "
3210 "entering an invalid\n"
3211 "state for Intel VT. For example, the guest maybe running "
3212 "in big real mode\n"
3213 "which is not supported on less recent Intel processors."
3214 "\n\n");
3215 }
3216 ret = -1;
3217 break;
3218 case KVM_EXIT_EXCEPTION:
3219 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3220 run->ex.exception, run->ex.error_code);
3221 ret = -1;
3222 break;
f2574737
JK		 3223 case KVM_EXIT_DEBUG:
3224 DPRINTF("kvm_exit_debug\n");
4b8523ee 3225 qemu_mutex_lock_iothread();
a60f24b5 3226 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3227 qemu_mutex_unlock_iothread();
f2574737 3228 break;
50efe82c
AS		 3229 case KVM_EXIT_HYPERV:
3230 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3231 break;
15eafc2e
PB		 3232 case KVM_EXIT_IOAPIC_EOI:
3233 ioapic_eoi_broadcast(run->eoi.vector);
3234 ret = 0;
3235 break;
2a4dac83
JK		 3236 default:
3237 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3238 ret = -1;
3239 break;
3240 }
3241
3242 return ret;
3243}
3244
20d695a9 3245bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3246{
20d695a9
AF		 3247 X86CPU *cpu = X86_CPU(cs);
3248 CPUX86State *env = &cpu->env;
3249
dd1750d7 3250 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3251 return !(env->cr[0] & CR0_PE_MASK) ||
3252 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3253}
84b058d7
JK		 3254
3255void kvm_arch_init_irq_routing(KVMState *s)
3256{
3257 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3258 /* If kernel can't do irq routing, interrupt source
3259 * override 0->2 cannot be set up as required by HPET.
3260 * So we have to disable it.
3261 */
3262 no_hpet = 1;
3263 }
cc7e0ddf 3264 /* We know at this point that we're using the in-kernel
614e41bc 3265 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3266 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3267 */
614e41bc 3268 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3269 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3270
3271 if (kvm_irqchip_is_split()) {
3272 int i;
3273
3274 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3275 MSI routes for signaling interrupts to the local apics. */
3276 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3277 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3278 error_report("Could not enable split IRQ mode.");
3279 exit(1);
3280 }
3281 }
3282 }
3283}
3284
3285int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3286{
3287 int ret;
3288 if (machine_kernel_irqchip_split(ms)) {
3289 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3290 if (ret) {
df3c286c 3291 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3292 strerror(-ret));
3293 exit(1);
3294 } else {
3295 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3296 kvm_split_irqchip = true;
3297 return 1;
3298 }
3299 } else {
3300 return 0;
3301 }
84b058d7 3302}
b139bd30
JK		 3303
3304/* Classic KVM device assignment interface. Will remain x86 only. */
3305int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3306 uint32_t flags, uint32_t *dev_id)
3307{
3308 struct kvm_assigned_pci_dev dev_data = {
3309 .segnr = dev_addr->domain,
3310 .busnr = dev_addr->bus,
3311 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3312 .flags = flags,
3313 };
3314 int ret;
3315
3316 dev_data.assigned_dev_id =
3317 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3318
3319 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3320 if (ret < 0) {
3321 return ret;
3322 }
3323
3324 *dev_id = dev_data.assigned_dev_id;
3325
3326 return 0;
3327}
3328
3329int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3330{
3331 struct kvm_assigned_pci_dev dev_data = {
3332 .assigned_dev_id = dev_id,
3333 };
3334
3335 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3336}
3337
3338static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3339 uint32_t irq_type, uint32_t guest_irq)
3340{
3341 struct kvm_assigned_irq assigned_irq = {
3342 .assigned_dev_id = dev_id,
3343 .guest_irq = guest_irq,
3344 .flags = irq_type,
3345 };
3346
3347 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3348 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3349 } else {
3350 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3351 }
3352}
3353
3354int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3355 uint32_t guest_irq)
3356{
3357 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3358 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3359
3360 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3361}
3362
3363int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3364{
3365 struct kvm_assigned_pci_dev dev_data = {
3366 .assigned_dev_id = dev_id,
3367 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3368 };
3369
3370 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3371}
3372
3373static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3374 uint32_t type)
3375{
3376 struct kvm_assigned_irq assigned_irq = {
3377 .assigned_dev_id = dev_id,
3378 .flags = type,
3379 };
3380
3381 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3382}
3383
3384int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3385{
3386 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3387 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3388}
3389
3390int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3391{
3392 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3393 KVM_DEV_IRQ_GUEST_MSI, virq);
3394}
3395
3396int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3397{
3398 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3399 KVM_DEV_IRQ_HOST_MSI);
3400}
3401
3402bool kvm_device_msix_supported(KVMState *s)
3403{
3404 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3405 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3406 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3407}
3408
3409int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3410 uint32_t nr_vectors)
3411{
3412 struct kvm_assigned_msix_nr msix_nr = {
3413 .assigned_dev_id = dev_id,
3414 .entry_nr = nr_vectors,
3415 };
3416
3417 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3418}
3419
3420int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3421 int virq)
3422{
3423 struct kvm_assigned_msix_entry msix_entry = {
3424 .assigned_dev_id = dev_id,
3425 .gsi = virq,
3426 .entry = vector,
3427 };
3428
3429 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3430}
3431
3432int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3433{
3434 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3435 KVM_DEV_IRQ_GUEST_MSIX, 0);
3436}
3437
3438int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3439{
3440 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3441 KVM_DEV_IRQ_HOST_MSIX);
3442}
9e03a040
FB		 3443
3444int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3445 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3446{
8b5ed7df
PX		 3447 X86IOMMUState *iommu = x86_iommu_get_default();
3448
3449 if (iommu) {
3450 int ret;
3451 MSIMessage src, dst;
3452 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3453
3454 src.address = route->u.msi.address_hi;
3455 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3456 src.address |= route->u.msi.address_lo;
3457 src.data = route->u.msi.data;
3458
3459 ret = class->int_remap(iommu, &src, &dst, dev ? \
3460 pci_requester_id(dev) : \
3461 X86_IOMMU_SID_INVALID);
3462 if (ret) {
3463 trace_kvm_x86_fixup_msi_error(route->gsi);
3464 return 1;
3465 }
3466
3467 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3468 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3469 route->u.msi.data = dst.data;
3470 }
3471
9e03a040
FB		 3472 return 0;
3473}
1850b6b7 3474
38d87493
PX		 3475typedef struct MSIRouteEntry MSIRouteEntry;
3476
3477struct MSIRouteEntry {
3478 PCIDevice *dev; /* Device pointer */
3479 int vector; /* MSI/MSIX vector index */
3480 int virq; /* Virtual IRQ index */
3481 QLIST_ENTRY(MSIRouteEntry) list;
3482};
3483
3484/* List of used GSI routes */
3485static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3486 QLIST_HEAD_INITIALIZER(msi_route_list);
3487
e1d4fb2d
PX		 3488static void kvm_update_msi_routes_all(void *private, bool global,
3489 uint32_t index, uint32_t mask)
3490{
3491 int cnt = 0;
3492 MSIRouteEntry *entry;
3493 MSIMessage msg;
3494 /* TODO: explicit route update */
3495 QLIST_FOREACH(entry, &msi_route_list, list) {
3496 cnt++;
3497 msg = pci_get_msi_message(entry->dev, entry->vector);
3498 kvm_irqchip_update_msi_route(kvm_state, entry->virq,
3499 msg, entry->dev);
3500 }
3f1fea0f 3501 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3502 trace_kvm_x86_update_msi_routes(cnt);
3503}
3504
38d87493
PX		 3505int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3506 int vector, PCIDevice *dev)
3507{
e1d4fb2d 3508 static bool notify_list_inited = false;
38d87493
PX		 3509 MSIRouteEntry *entry;
3510
3511 if (!dev) {
3512 /* These are (possibly) IOAPIC routes only used for split
3513 * kernel irqchip mode, while what we are housekeeping are
3514 * PCI devices only. */
3515 return 0;
3516 }
3517
3518 entry = g_new0(MSIRouteEntry, 1);
3519 entry->dev = dev;
3520 entry->vector = vector;
3521 entry->virq = route->gsi;
3522 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3523
3524 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3525
3526 if (!notify_list_inited) {
3527 /* For the first time we do add route, add ourselves into
3528 * IOMMU's IEC notify list if needed. */
3529 X86IOMMUState *iommu = x86_iommu_get_default();
3530 if (iommu) {
3531 x86_iommu_iec_register_notifier(iommu,
3532 kvm_update_msi_routes_all,
3533 NULL);
3534 }
3535 notify_list_inited = true;
3536 }
38d87493
PX		 3537 return 0;
3538}
3539
3540int kvm_arch_release_virq_post(int virq)
3541{
3542 MSIRouteEntry *entry, *next;
3543 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3544 if (entry->virq == virq) {
3545 trace_kvm_x86_remove_msi_route(virq);
3546 QLIST_REMOVE(entry, list);
3547 break;
3548 }
3549 }
9e03a040
FB		 3550 return 0;
3551}
1850b6b7
EA		 3552
3553int kvm_arch_msi_data_to_gsi(uint32_t data)
3554{
3555 abort();
3556}
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