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target-arm: Infer AUXCR feature from ARMv6
[qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31
FB		 1#include <stdio.h>
2#include <stdlib.h>
3#include <string.h>
4
5#include "cpu.h"
9ee6e8bb 6#include "gdbstub.h"
7b59220e 7#include "helper.h"
ca10f867 8#include "qemu-common.h"
7bbcb0af 9#include "host-utils.h"
4f78c9ad 10#if !defined(CONFIG_USER_ONLY)
983fe826 11#include "hw/loader.h"
4f78c9ad 12#endif
9ee6e8bb 13
10055562
PB		 14static uint32_t cortexa9_cp15_c0_c1[8] =
15{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
16
17static uint32_t cortexa9_cp15_c0_c2[8] =
18{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
19
9ee6e8bb
PB		 20static uint32_t cortexa8_cp15_c0_c1[8] =
21{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
22
23static uint32_t cortexa8_cp15_c0_c2[8] =
24{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
25
26static uint32_t mpcore_cp15_c0_c1[8] =
27{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
28
29static uint32_t mpcore_cp15_c0_c2[8] =
30{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
31
32static uint32_t arm1136_cp15_c0_c1[8] =
33{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
34
35static uint32_t arm1136_cp15_c0_c2[8] =
36{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
b5ff1b31 37
7807eed9
JI		 38static uint32_t arm1176_cp15_c0_c1[8] =
39{ 0x111, 0x11, 0x33, 0, 0x01130003, 0x10030302, 0x01222100, 0 };
40
41static uint32_t arm1176_cp15_c0_c2[8] =
42{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
43
aaed909a
FB		 44static uint32_t cpu_arm_find_by_name(const char *name);
45
f3d6b95e
PB		 46static inline void set_feature(CPUARMState *env, int feature)
47{
48 env->features |= 1u << feature;
49}
50
51static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
52{
53 env->cp15.c0_cpuid = id;
54 switch (id) {
55 case ARM_CPUID_ARM926:
be5e7a76 56 set_feature(env, ARM_FEATURE_V5);
f3d6b95e
PB		 57 set_feature(env, ARM_FEATURE_VFP);
58 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
c1713132 59 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 60 env->cp15.c1_sys = 0x00090078;
f3d6b95e 61 break;
ce819861 62 case ARM_CPUID_ARM946:
be5e7a76 63 set_feature(env, ARM_FEATURE_V5);
ce819861
PB		 64 set_feature(env, ARM_FEATURE_MPU);
65 env->cp15.c0_cachetype = 0x0f004006;
610c3c8a 66 env->cp15.c1_sys = 0x00000078;
ce819861 67 break;
f3d6b95e 68 case ARM_CPUID_ARM1026:
be5e7a76 69 set_feature(env, ARM_FEATURE_V5);
f3d6b95e
PB		 70 set_feature(env, ARM_FEATURE_VFP);
71 set_feature(env, ARM_FEATURE_AUXCR);
72 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
c1713132 73 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 74 env->cp15.c1_sys = 0x00090078;
c1713132 75 break;
9ee6e8bb 76 case ARM_CPUID_ARM1136:
906879a9
PM		 77 /* This is the 1136 r1, which is a v6K core */
78 set_feature(env, ARM_FEATURE_V6K);
79 /* Fall through */
80 case ARM_CPUID_ARM1136_R2:
81 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
82 * older core than plain "arm1136". In particular this does not
83 * have the v6K features.
84 */
9ee6e8bb
PB		 85 set_feature(env, ARM_FEATURE_V6);
86 set_feature(env, ARM_FEATURE_VFP);
906879a9
PM		 87 /* These ID register values are correct for 1136 but may be wrong
88 * for 1136_r2 (in particular r0p2 does not actually implement most
89 * of the ID registers).
90 */
9ee6e8bb
PB		 91 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
92 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
93 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
94 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 95 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb 96 env->cp15.c0_cachetype = 0x1dd20d2;
16440c5f 97 env->cp15.c1_sys = 0x00050078;
9ee6e8bb 98 break;
7807eed9 99 case ARM_CPUID_ARM1176:
7807eed9
JI		 100 set_feature(env, ARM_FEATURE_V6K);
101 set_feature(env, ARM_FEATURE_VFP);
906879a9 102 set_feature(env, ARM_FEATURE_VAPA);
7807eed9
JI		 103 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
104 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
105 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
106 memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
107 memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
108 env->cp15.c0_cachetype = 0x1dd20d2;
109 env->cp15.c1_sys = 0x00050078;
110 break;
9ee6e8bb 111 case ARM_CPUID_ARM11MPCORE:
9ee6e8bb
PB		 112 set_feature(env, ARM_FEATURE_V6K);
113 set_feature(env, ARM_FEATURE_VFP);
906879a9 114 set_feature(env, ARM_FEATURE_VAPA);
9ee6e8bb
PB		 115 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
116 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
117 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
118 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 119 memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb
PB		 120 env->cp15.c0_cachetype = 0x1dd20d2;
121 break;
122 case ARM_CPUID_CORTEXA8:
9ee6e8bb 123 set_feature(env, ARM_FEATURE_V7);
9ee6e8bb
PB		 124 set_feature(env, ARM_FEATURE_THUMB2);
125 set_feature(env, ARM_FEATURE_VFP);
126 set_feature(env, ARM_FEATURE_VFP3);
127 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 128 set_feature(env, ARM_FEATURE_THUMB2EE);
9ee6e8bb
PB		 129 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
130 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
131 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
132 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 133 memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
a49ea279
PB		 134 env->cp15.c0_cachetype = 0x82048004;
135 env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
136 env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
137 env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
138 env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
9c486ad6 139 env->cp15.c1_sys = 0x00c50078;
9ee6e8bb 140 break;
10055562 141 case ARM_CPUID_CORTEXA9:
10055562 142 set_feature(env, ARM_FEATURE_V7);
10055562
PB		 143 set_feature(env, ARM_FEATURE_THUMB2);
144 set_feature(env, ARM_FEATURE_VFP);
145 set_feature(env, ARM_FEATURE_VFP3);
146 set_feature(env, ARM_FEATURE_VFP_FP16);
147 set_feature(env, ARM_FEATURE_NEON);
148 set_feature(env, ARM_FEATURE_THUMB2EE);
e1bbf446
PM		 149 /* Note that A9 supports the MP extensions even for
150 * A9UP and single-core A9MP (which are both different
151 * and valid configurations; we don't model A9UP).
152 */
153 set_feature(env, ARM_FEATURE_V7MP);
10055562
PB		 154 env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
155 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
156 env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
157 memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
158 memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
159 env->cp15.c0_cachetype = 0x80038003;
160 env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
161 env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
162 env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
16440c5f 163 env->cp15.c1_sys = 0x00c50078;
10055562 164 break;
9ee6e8bb 165 case ARM_CPUID_CORTEXM3:
9ee6e8bb
PB		 166 set_feature(env, ARM_FEATURE_THUMB2);
167 set_feature(env, ARM_FEATURE_V7);
168 set_feature(env, ARM_FEATURE_M);
47789990 169 set_feature(env, ARM_FEATURE_THUMB_DIV);
9ee6e8bb
PB		 170 break;
171 case ARM_CPUID_ANY: /* For userspace emulation. */
9ee6e8bb
PB		 172 set_feature(env, ARM_FEATURE_V7);
173 set_feature(env, ARM_FEATURE_THUMB2);
174 set_feature(env, ARM_FEATURE_VFP);
175 set_feature(env, ARM_FEATURE_VFP3);
da97f52c 176 set_feature(env, ARM_FEATURE_VFP4);
60011498 177 set_feature(env, ARM_FEATURE_VFP_FP16);
9ee6e8bb 178 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 179 set_feature(env, ARM_FEATURE_THUMB2EE);
b8b8ea05 180 set_feature(env, ARM_FEATURE_ARM_DIV);
e1bbf446 181 set_feature(env, ARM_FEATURE_V7MP);
9ee6e8bb 182 break;
c3d2689d
AZ		 183 case ARM_CPUID_TI915T:
184 case ARM_CPUID_TI925T:
be5e7a76 185 set_feature(env, ARM_FEATURE_V4T);
c3d2689d
AZ		 186 set_feature(env, ARM_FEATURE_OMAPCP);
187 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
188 env->cp15.c0_cachetype = 0x5109149;
189 env->cp15.c1_sys = 0x00000070;
190 env->cp15.c15_i_max = 0x000;
191 env->cp15.c15_i_min = 0xff0;
192 break;
c1713132
AZ		 193 case ARM_CPUID_PXA250:
194 case ARM_CPUID_PXA255:
195 case ARM_CPUID_PXA260:
196 case ARM_CPUID_PXA261:
197 case ARM_CPUID_PXA262:
be5e7a76 198 set_feature(env, ARM_FEATURE_V5);
c1713132
AZ		 199 set_feature(env, ARM_FEATURE_XSCALE);
200 /* JTAG_ID is ((id << 28) | 0x09265013) */
201 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 202 env->cp15.c1_sys = 0x00000078;
c1713132
AZ		 203 break;
204 case ARM_CPUID_PXA270_A0:
205 case ARM_CPUID_PXA270_A1:
206 case ARM_CPUID_PXA270_B0:
207 case ARM_CPUID_PXA270_B1:
208 case ARM_CPUID_PXA270_C0:
209 case ARM_CPUID_PXA270_C5:
be5e7a76 210 set_feature(env, ARM_FEATURE_V5);
c1713132
AZ		 211 set_feature(env, ARM_FEATURE_XSCALE);
212 /* JTAG_ID is ((id << 28) | 0x09265013) */
18c9b560
AZ		 213 set_feature(env, ARM_FEATURE_IWMMXT);
214 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
c1713132 215 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 216 env->cp15.c1_sys = 0x00000078;
f3d6b95e 217 break;
5bc95aa2
DES		 218 case ARM_CPUID_SA1100:
219 case ARM_CPUID_SA1110:
220 set_feature(env, ARM_FEATURE_STRONGARM);
221 env->cp15.c1_sys = 0x00000070;
222 break;
f3d6b95e
PB		 223 default:
224 cpu_abort(env, "Bad CPU ID: %x\n", id);
225 break;
226 }
906879a9
PM		 227
228 /* Some features automatically imply others: */
229 if (arm_feature(env, ARM_FEATURE_V7)) {
230 set_feature(env, ARM_FEATURE_VAPA);
bbc5c5fa
AF		 231 if (!arm_feature(env, ARM_FEATURE_M)) {
232 set_feature(env, ARM_FEATURE_V6K);
233 } else {
234 set_feature(env, ARM_FEATURE_V6);
235 }
906879a9 236 }
6bf62124
AF		 237 if (arm_feature(env, ARM_FEATURE_V6K)) {
238 set_feature(env, ARM_FEATURE_V6);
239 }
08c40f3c
AF		 240 if (arm_feature(env, ARM_FEATURE_V6)) {
241 set_feature(env, ARM_FEATURE_V5);
10e87702
AF		 242 if (!arm_feature(env, ARM_FEATURE_M)) {
243 set_feature(env, ARM_FEATURE_AUXCR);
244 }
08c40f3c 245 }
ddb572ec
AF		 246 if (arm_feature(env, ARM_FEATURE_V5)) {
247 set_feature(env, ARM_FEATURE_V4T);
248 }
b8b8ea05
PM		 249 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
250 set_feature(env, ARM_FEATURE_THUMB_DIV);
251 }
f3d6b95e
PB		 252}
253
40f137e1
PB		 254void cpu_reset(CPUARMState *env)
255{
f3d6b95e 256 uint32_t id;
eca1bdf4
AL		 257
258 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
259 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
260 log_cpu_state(env, 0);
261 }
262
f3d6b95e
PB		 263 id = env->cp15.c0_cpuid;
264 memset(env, 0, offsetof(CPUARMState, breakpoints));
265 if (id)
266 cpu_reset_model_id(env, id);
40f137e1
PB		 267#if defined (CONFIG_USER_ONLY)
268 env->uncached_cpsr = ARM_CPU_MODE_USR;
3a807dec 269 /* For user mode we must enable access to coprocessors */
40f137e1 270 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
3a807dec
PM		 271 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
272 env->cp15.c15_cpar = 3;
273 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
274 env->cp15.c15_cpar = 1;
275 }
40f137e1
PB		 276#else
277 /* SVC mode with interrupts disabled. */
278 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
9ee6e8bb 279 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
983fe826
PB		 280 clear at reset. Initial SP and PC are loaded from ROM. */
281 if (IS_M(env)) {
282 uint32_t pc;
283 uint8_t *rom;
9ee6e8bb 284 env->uncached_cpsr &= ~CPSR_I;
983fe826
PB		 285 rom = rom_ptr(0);
286 if (rom) {
287 /* We should really use ldl_phys here, in case the guest
288 modified flash and reset itself. However images
297d1b4e 289 loaded via -kernel have not been copied yet, so load the
983fe826
PB		 290 values directly from there. */
291 env->regs[13] = ldl_p(rom);
292 pc = ldl_p(rom + 4);
293 env->thumb = pc & 1;
294 env->regs[15] = pc & ~1;
295 }
296 }
40f137e1 297 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
b2fa1797 298 env->cp15.c2_base_mask = 0xffffc000u;
74594c9d
PM		 299 /* v7 performance monitor control register: same implementor
300 * field as main ID register, and we implement no event counters.
301 */
302 env->cp15.c9_pmcr = (id & 0xff000000);
40f137e1 303#endif
3a492f3a
PM		 304 set_flush_to_zero(1, &env->vfp.standard_fp_status);
305 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
306 set_default_nan_mode(1, &env->vfp.standard_fp_status);
9df38c47
PM		 307 set_float_detect_tininess(float_tininess_before_rounding,
308 &env->vfp.fp_status);
309 set_float_detect_tininess(float_tininess_before_rounding,
310 &env->vfp.standard_fp_status);
f3d6b95e 311 tlb_flush(env, 1);
40f137e1
PB		 312}
313
56aebc89
PB		 314static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
315{
316 int nregs;
317
318 /* VFP data registers are always little-endian. */
319 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
320 if (reg < nregs) {
321 stfq_le_p(buf, env->vfp.regs[reg]);
322 return 8;
323 }
324 if (arm_feature(env, ARM_FEATURE_NEON)) {
325 /* Aliases for Q regs. */
326 nregs += 16;
327 if (reg < nregs) {
328 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
329 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
330 return 16;
331 }
332 }
333 switch (reg - nregs) {
334 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
335 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
336 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
337 }
338 return 0;
339}
340
341static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
342{
343 int nregs;
344
345 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
346 if (reg < nregs) {
347 env->vfp.regs[reg] = ldfq_le_p(buf);
348 return 8;
349 }
350 if (arm_feature(env, ARM_FEATURE_NEON)) {
351 nregs += 16;
352 if (reg < nregs) {
353 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
354 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
355 return 16;
356 }
357 }
358 switch (reg - nregs) {
359 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
360 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 361 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 362 }
363 return 0;
364}
365
aaed909a 366CPUARMState *cpu_arm_init(const char *cpu_model)
40f137e1
PB		 367{
368 CPUARMState *env;
aaed909a 369 uint32_t id;
b26eefb6 370 static int inited = 0;
40f137e1 371
aaed909a
FB		 372 id = cpu_arm_find_by_name(cpu_model);
373 if (id == 0)
374 return NULL;
7267c094 375 env = g_malloc0(sizeof(CPUARMState));
40f137e1 376 cpu_exec_init(env);
f4fc247b 377 if (tcg_enabled() && !inited) {
b26eefb6
PB		 378 inited = 1;
379 arm_translate_init();
380 }
381
01ba9816 382 env->cpu_model_str = cpu_model;
aaed909a 383 env->cp15.c0_cpuid = id;
40f137e1 384 cpu_reset(env);
56aebc89
PB		 385 if (arm_feature(env, ARM_FEATURE_NEON)) {
386 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
387 51, "arm-neon.xml", 0);
388 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
389 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
390 35, "arm-vfp3.xml", 0);
391 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
392 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
393 19, "arm-vfp.xml", 0);
394 }
0bf46a40 395 qemu_init_vcpu(env);
40f137e1
PB		 396 return env;
397}
398
3371d272
PB		 399struct arm_cpu_t {
400 uint32_t id;
401 const char *name;
402};
403
404static const struct arm_cpu_t arm_cpu_names[] = {
405 { ARM_CPUID_ARM926, "arm926"},
ce819861 406 { ARM_CPUID_ARM946, "arm946"},
3371d272 407 { ARM_CPUID_ARM1026, "arm1026"},
9ee6e8bb 408 { ARM_CPUID_ARM1136, "arm1136"},
827df9f3 409 { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
7807eed9 410 { ARM_CPUID_ARM1176, "arm1176"},
9ee6e8bb
PB		 411 { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
412 { ARM_CPUID_CORTEXM3, "cortex-m3"},
413 { ARM_CPUID_CORTEXA8, "cortex-a8"},
10055562 414 { ARM_CPUID_CORTEXA9, "cortex-a9"},
c3d2689d 415 { ARM_CPUID_TI925T, "ti925t" },
c1713132 416 { ARM_CPUID_PXA250, "pxa250" },
5bc95aa2
DES		 417 { ARM_CPUID_SA1100, "sa1100" },
418 { ARM_CPUID_SA1110, "sa1110" },
c1713132
AZ		 419 { ARM_CPUID_PXA255, "pxa255" },
420 { ARM_CPUID_PXA260, "pxa260" },
421 { ARM_CPUID_PXA261, "pxa261" },
422 { ARM_CPUID_PXA262, "pxa262" },
423 { ARM_CPUID_PXA270, "pxa270" },
424 { ARM_CPUID_PXA270_A0, "pxa270-a0" },
425 { ARM_CPUID_PXA270_A1, "pxa270-a1" },
426 { ARM_CPUID_PXA270_B0, "pxa270-b0" },
427 { ARM_CPUID_PXA270_B1, "pxa270-b1" },
428 { ARM_CPUID_PXA270_C0, "pxa270-c0" },
429 { ARM_CPUID_PXA270_C5, "pxa270-c5" },
9ee6e8bb 430 { ARM_CPUID_ANY, "any"},
3371d272
PB		 431 { 0, NULL}
432};
433
9a78eead 434void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
5adb4839
PB		 435{
436 int i;
437
c732abe2 438 (*cpu_fprintf)(f, "Available CPUs:\n");
5adb4839 439 for (i = 0; arm_cpu_names[i].name; i++) {
c732abe2 440 (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
5adb4839
PB		 441 }
442}
443
aaed909a
FB		 444/* return 0 if not found */
445static uint32_t cpu_arm_find_by_name(const char *name)
40f137e1 446{
3371d272
PB		 447 int i;
448 uint32_t id;
449
450 id = 0;
3371d272
PB		 451 for (i = 0; arm_cpu_names[i].name; i++) {
452 if (strcmp(name, arm_cpu_names[i].name) == 0) {
453 id = arm_cpu_names[i].id;
454 break;
455 }
456 }
aaed909a 457 return id;
40f137e1
PB		 458}
459
460void cpu_arm_close(CPUARMState *env)
461{
12b1de3a 462 g_free(env);
40f137e1
PB		 463}
464
2f4a40e5
AZ		 465uint32_t cpsr_read(CPUARMState *env)
466{
467 int ZF;
6fbe23d5
PB		 468 ZF = (env->ZF == 0);
469 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 470 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
471 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
472 | ((env->condexec_bits & 0xfc) << 8)
473 | (env->GE << 16);
474}
475
476void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
477{
2f4a40e5 478 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 479 env->ZF = (~val) & CPSR_Z;
480 env->NF = val;
2f4a40e5
AZ		 481 env->CF = (val >> 29) & 1;
482 env->VF = (val << 3) & 0x80000000;
483 }
484 if (mask & CPSR_Q)
485 env->QF = ((val & CPSR_Q) != 0);
486 if (mask & CPSR_T)
487 env->thumb = ((val & CPSR_T) != 0);
488 if (mask & CPSR_IT_0_1) {
489 env->condexec_bits &= ~3;
490 env->condexec_bits |= (val >> 25) & 3;
491 }
492 if (mask & CPSR_IT_2_7) {
493 env->condexec_bits &= 3;
494 env->condexec_bits |= (val >> 8) & 0xfc;
495 }
496 if (mask & CPSR_GE) {
497 env->GE = (val >> 16) & 0xf;
498 }
499
500 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
501 switch_mode(env, val & CPSR_M);
502 }
503 mask &= ~CACHED_CPSR_BITS;
504 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
505}
506
b26eefb6
PB		 507/* Sign/zero extend */
508uint32_t HELPER(sxtb16)(uint32_t x)
509{
510 uint32_t res;
511 res = (uint16_t)(int8_t)x;
512 res |= (uint32_t)(int8_t)(x >> 16) << 16;
513 return res;
514}
515
516uint32_t HELPER(uxtb16)(uint32_t x)
517{
518 uint32_t res;
519 res = (uint16_t)(uint8_t)x;
520 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
521 return res;
522}
523
f51bbbfe
PB		 524uint32_t HELPER(clz)(uint32_t x)
525{
7bbcb0af 526 return clz32(x);
f51bbbfe
PB		 527}
528
3670669c
PB		 529int32_t HELPER(sdiv)(int32_t num, int32_t den)
530{
531 if (den == 0)
532 return 0;
686eeb93
AJ		 533 if (num == INT_MIN && den == -1)
534 return INT_MIN;
3670669c
PB		 535 return num / den;
536}
537
538uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
539{
540 if (den == 0)
541 return 0;
542 return num / den;
543}
544
545uint32_t HELPER(rbit)(uint32_t x)
546{
547 x = ((x & 0xff000000) >> 24)
548 | ((x & 0x00ff0000) >> 8)
549 | ((x & 0x0000ff00) << 8)
550 | ((x & 0x000000ff) << 24);
551 x = ((x & 0xf0f0f0f0) >> 4)
552 | ((x & 0x0f0f0f0f) << 4);
553 x = ((x & 0x88888888) >> 3)
554 | ((x & 0x44444444) >> 1)
555 | ((x & 0x22222222) << 1)
556 | ((x & 0x11111111) << 3);
557 return x;
558}
559
ad69471c
PB		 560uint32_t HELPER(abs)(uint32_t x)
561{
562 return ((int32_t)x < 0) ? -x : x;
563}
564
5fafdf24 565#if defined(CONFIG_USER_ONLY)
b5ff1b31
FB		 566
567void do_interrupt (CPUState *env)
568{
569 env->exception_index = -1;
570}
571
572int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
97b348e7 573 int mmu_idx)
b5ff1b31
FB		 574{
575 if (rw == 2) {
576 env->exception_index = EXCP_PREFETCH_ABORT;
577 env->cp15.c6_insn = address;
578 } else {
579 env->exception_index = EXCP_DATA_ABORT;
580 env->cp15.c6_data = address;
581 }
582 return 1;
583}
584
b5ff1b31 585/* These should probably raise undefined insn exceptions. */
8984bd2e 586void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 587{
588 int op1 = (insn >> 8) & 0xf;
589 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
590 return;
591}
592
8984bd2e 593uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 594{
595 int op1 = (insn >> 8) & 0xf;
596 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
597 return 0;
598}
599
8984bd2e 600void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31
FB		 601{
602 cpu_abort(env, "cp15 insn %08x\n", insn);
603}
604
8984bd2e 605uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31
FB		 606{
607 cpu_abort(env, "cp15 insn %08x\n", insn);
b5ff1b31
FB		 608}
609
9ee6e8bb 610/* These should probably raise undefined insn exceptions. */
8984bd2e 611void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 612{
613 cpu_abort(env, "v7m_mrs %d\n", reg);
614}
615
8984bd2e 616uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 617{
618 cpu_abort(env, "v7m_mrs %d\n", reg);
619 return 0;
620}
621
b5ff1b31
FB		 622void switch_mode(CPUState *env, int mode)
623{
624 if (mode != ARM_CPU_MODE_USR)
625 cpu_abort(env, "Tried to switch out of user mode\n");
626}
627
b0109805 628void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 629{
630 cpu_abort(env, "banked r13 write\n");
631}
632
b0109805 633uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb
PB		 634{
635 cpu_abort(env, "banked r13 read\n");
636 return 0;
637}
638
b5ff1b31
FB		 639#else
640
8e71621f
PB		 641extern int semihosting_enabled;
642
b5ff1b31
FB		 643/* Map CPU modes onto saved register banks. */
644static inline int bank_number (int mode)
645{
646 switch (mode) {
647 case ARM_CPU_MODE_USR:
648 case ARM_CPU_MODE_SYS:
649 return 0;
650 case ARM_CPU_MODE_SVC:
651 return 1;
652 case ARM_CPU_MODE_ABT:
653 return 2;
654 case ARM_CPU_MODE_UND:
655 return 3;
656 case ARM_CPU_MODE_IRQ:
657 return 4;
658 case ARM_CPU_MODE_FIQ:
659 return 5;
660 }
661 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
662 return -1;
663}
664
665void switch_mode(CPUState *env, int mode)
666{
667 int old_mode;
668 int i;
669
670 old_mode = env->uncached_cpsr & CPSR_M;
671 if (mode == old_mode)
672 return;
673
674 if (old_mode == ARM_CPU_MODE_FIQ) {
675 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 676 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 677 } else if (mode == ARM_CPU_MODE_FIQ) {
678 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 679 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 680 }
681
682 i = bank_number(old_mode);
683 env->banked_r13[i] = env->regs[13];
684 env->banked_r14[i] = env->regs[14];
685 env->banked_spsr[i] = env->spsr;
686
687 i = bank_number(mode);
688 env->regs[13] = env->banked_r13[i];
689 env->regs[14] = env->banked_r14[i];
690 env->spsr = env->banked_spsr[i];
691}
692
9ee6e8bb
PB		 693static void v7m_push(CPUARMState *env, uint32_t val)
694{
695 env->regs[13] -= 4;
696 stl_phys(env->regs[13], val);
697}
698
699static uint32_t v7m_pop(CPUARMState *env)
700{
701 uint32_t val;
702 val = ldl_phys(env->regs[13]);
703 env->regs[13] += 4;
704 return val;
705}
706
707/* Switch to V7M main or process stack pointer. */
708static void switch_v7m_sp(CPUARMState *env, int process)
709{
710 uint32_t tmp;
711 if (env->v7m.current_sp != process) {
712 tmp = env->v7m.other_sp;
713 env->v7m.other_sp = env->regs[13];
714 env->regs[13] = tmp;
715 env->v7m.current_sp = process;
716 }
717}
718
719static void do_v7m_exception_exit(CPUARMState *env)
720{
721 uint32_t type;
722 uint32_t xpsr;
723
724 type = env->regs[15];
725 if (env->v7m.exception != 0)
983fe826 726 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 727
728 /* Switch to the target stack. */
729 switch_v7m_sp(env, (type & 4) != 0);
730 /* Pop registers. */
731 env->regs[0] = v7m_pop(env);
732 env->regs[1] = v7m_pop(env);
733 env->regs[2] = v7m_pop(env);
734 env->regs[3] = v7m_pop(env);
735 env->regs[12] = v7m_pop(env);
736 env->regs[14] = v7m_pop(env);
737 env->regs[15] = v7m_pop(env);
738 xpsr = v7m_pop(env);
739 xpsr_write(env, xpsr, 0xfffffdff);
740 /* Undo stack alignment. */
741 if (xpsr & 0x200)
742 env->regs[13] |= 4;
743 /* ??? The exception return type specifies Thread/Handler mode. However
744 this is also implied by the xPSR value. Not sure what to do
745 if there is a mismatch. */
746 /* ??? Likewise for mismatches between the CONTROL register and the stack
747 pointer. */
748}
749
2b3ea315 750static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 751{
752 uint32_t xpsr = xpsr_read(env);
753 uint32_t lr;
754 uint32_t addr;
755
756 lr = 0xfffffff1;
757 if (env->v7m.current_sp)
758 lr |= 4;
759 if (env->v7m.exception == 0)
760 lr |= 8;
761
762 /* For exceptions we just mark as pending on the NVIC, and let that
763 handle it. */
764 /* TODO: Need to escalate if the current priority is higher than the
765 one we're raising. */
766 switch (env->exception_index) {
767 case EXCP_UDEF:
983fe826 768 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 769 return;
770 case EXCP_SWI:
771 env->regs[15] += 2;
983fe826 772 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 773 return;
774 case EXCP_PREFETCH_ABORT:
775 case EXCP_DATA_ABORT:
983fe826 776 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 777 return;
778 case EXCP_BKPT:
2ad207d4
PB		 779 if (semihosting_enabled) {
780 int nr;
781 nr = lduw_code(env->regs[15]) & 0xff;
782 if (nr == 0xab) {
783 env->regs[15] += 2;
784 env->regs[0] = do_arm_semihosting(env);
785 return;
786 }
787 }
983fe826 788 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 789 return;
790 case EXCP_IRQ:
983fe826 791 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 792 break;
793 case EXCP_EXCEPTION_EXIT:
794 do_v7m_exception_exit(env);
795 return;
796 default:
797 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
798 return; /* Never happens. Keep compiler happy. */
799 }
800
801 /* Align stack pointer. */
802 /* ??? Should only do this if Configuration Control Register
803 STACKALIGN bit is set. */
804 if (env->regs[13] & 4) {
ab19b0ec 805 env->regs[13] -= 4;
9ee6e8bb
PB		 806 xpsr |= 0x200;
807 }
6c95676b 808 /* Switch to the handler mode. */
9ee6e8bb
PB		 809 v7m_push(env, xpsr);
810 v7m_push(env, env->regs[15]);
811 v7m_push(env, env->regs[14]);
812 v7m_push(env, env->regs[12]);
813 v7m_push(env, env->regs[3]);
814 v7m_push(env, env->regs[2]);
815 v7m_push(env, env->regs[1]);
816 v7m_push(env, env->regs[0]);
817 switch_v7m_sp(env, 0);
818 env->uncached_cpsr &= ~CPSR_IT;
819 env->regs[14] = lr;
820 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
821 env->regs[15] = addr & 0xfffffffe;
822 env->thumb = addr & 1;
823}
824
b5ff1b31
FB		 825/* Handle a CPU exception. */
826void do_interrupt(CPUARMState *env)
827{
828 uint32_t addr;
829 uint32_t mask;
830 int new_mode;
831 uint32_t offset;
832
9ee6e8bb
PB		 833 if (IS_M(env)) {
834 do_interrupt_v7m(env);
835 return;
836 }
b5ff1b31
FB		 837 /* TODO: Vectored interrupt controller. */
838 switch (env->exception_index) {
839 case EXCP_UDEF:
840 new_mode = ARM_CPU_MODE_UND;
841 addr = 0x04;
842 mask = CPSR_I;
843 if (env->thumb)
844 offset = 2;
845 else
846 offset = 4;
847 break;
848 case EXCP_SWI:
8e71621f
PB		 849 if (semihosting_enabled) {
850 /* Check for semihosting interrupt. */
851 if (env->thumb) {
852 mask = lduw_code(env->regs[15] - 2) & 0xff;
853 } else {
854 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
855 }
856 /* Only intercept calls from privileged modes, to provide some
857 semblance of security. */
858 if (((mask == 0x123456 && !env->thumb)
859 || (mask == 0xab && env->thumb))
860 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
861 env->regs[0] = do_arm_semihosting(env);
862 return;
863 }
864 }
b5ff1b31
FB		 865 new_mode = ARM_CPU_MODE_SVC;
866 addr = 0x08;
867 mask = CPSR_I;
601d70b9 868 /* The PC already points to the next instruction. */
b5ff1b31
FB		 869 offset = 0;
870 break;
06c949e6 871 case EXCP_BKPT:
9ee6e8bb 872 /* See if this is a semihosting syscall. */
2ad207d4 873 if (env->thumb && semihosting_enabled) {
9ee6e8bb
PB		 874 mask = lduw_code(env->regs[15]) & 0xff;
875 if (mask == 0xab
876 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
877 env->regs[15] += 2;
878 env->regs[0] = do_arm_semihosting(env);
879 return;
880 }
881 }
81c05daf 882 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 883 /* Fall through to prefetch abort. */
884 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 885 new_mode = ARM_CPU_MODE_ABT;
886 addr = 0x0c;
887 mask = CPSR_A | CPSR_I;
888 offset = 4;
889 break;
890 case EXCP_DATA_ABORT:
891 new_mode = ARM_CPU_MODE_ABT;
892 addr = 0x10;
893 mask = CPSR_A | CPSR_I;
894 offset = 8;
895 break;
896 case EXCP_IRQ:
897 new_mode = ARM_CPU_MODE_IRQ;
898 addr = 0x18;
899 /* Disable IRQ and imprecise data aborts. */
900 mask = CPSR_A | CPSR_I;
901 offset = 4;
902 break;
903 case EXCP_FIQ:
904 new_mode = ARM_CPU_MODE_FIQ;
905 addr = 0x1c;
906 /* Disable FIQ, IRQ and imprecise data aborts. */
907 mask = CPSR_A | CPSR_I | CPSR_F;
908 offset = 4;
909 break;
910 default:
911 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
912 return; /* Never happens. Keep compiler happy. */
913 }
914 /* High vectors. */
915 if (env->cp15.c1_sys & (1 << 13)) {
916 addr += 0xffff0000;
917 }
918 switch_mode (env, new_mode);
919 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 920 /* Clear IT bits. */
921 env->condexec_bits = 0;
30a8cac1 922 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 923 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 924 env->uncached_cpsr |= mask;
be5e7a76
DES		 925 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
926 * and we should just guard the thumb mode on V4 */
927 if (arm_feature(env, ARM_FEATURE_V4T)) {
928 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
929 }
b5ff1b31
FB		 930 env->regs[14] = env->regs[15] + offset;
931 env->regs[15] = addr;
932 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
933}
934
935/* Check section/page access permissions.
936 Returns the page protection flags, or zero if the access is not
937 permitted. */
dd4ebc2e
JCD		 938static inline int check_ap(CPUState *env, int ap, int domain_prot,
939 int access_type, int is_user)
b5ff1b31 940{
9ee6e8bb
PB		 941 int prot_ro;
942
dd4ebc2e 943 if (domain_prot == 3) {
b5ff1b31 944 return PAGE_READ | PAGE_WRITE;
dd4ebc2e 945 }
b5ff1b31 946
9ee6e8bb
PB		 947 if (access_type == 1)
948 prot_ro = 0;
949 else
950 prot_ro = PAGE_READ;
951
b5ff1b31
FB		 952 switch (ap) {
953 case 0:
78600320 954 if (access_type == 1)
b5ff1b31
FB		 955 return 0;
956 switch ((env->cp15.c1_sys >> 8) & 3) {
957 case 1:
958 return is_user ? 0 : PAGE_READ;
959 case 2:
960 return PAGE_READ;
961 default:
962 return 0;
963 }
964 case 1:
965 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
966 case 2:
967 if (is_user)
9ee6e8bb 968 return prot_ro;
b5ff1b31
FB		 969 else
970 return PAGE_READ | PAGE_WRITE;
971 case 3:
972 return PAGE_READ | PAGE_WRITE;
d4934d18 973 case 4: /* Reserved. */
9ee6e8bb
PB		 974 return 0;
975 case 5:
976 return is_user ? 0 : prot_ro;
977 case 6:
978 return prot_ro;
d4934d18 979 case 7:
0ab06d83 980 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 981 return 0;
982 return prot_ro;
b5ff1b31
FB		 983 default:
984 abort();
985 }
986}
987
b2fa1797
PB		 988static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
989{
990 uint32_t table;
991
992 if (address & env->cp15.c2_mask)
993 table = env->cp15.c2_base1 & 0xffffc000;
994 else
995 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
996
997 table |= (address >> 18) & 0x3ffc;
998 return table;
999}
1000
9ee6e8bb 1001static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
d4c430a8
PB		 1002 int is_user, uint32_t *phys_ptr, int *prot,
1003 target_ulong *page_size)
b5ff1b31
FB		 1004{
1005 int code;
1006 uint32_t table;
1007 uint32_t desc;
1008 int type;
1009 int ap;
1010 int domain;
dd4ebc2e 1011 int domain_prot;
b5ff1b31
FB		 1012 uint32_t phys_addr;
1013
9ee6e8bb
PB		 1014 /* Pagetable walk. */
1015 /* Lookup l1 descriptor. */
b2fa1797 1016 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1017 desc = ldl_phys(table);
1018 type = (desc & 3);
dd4ebc2e
JCD		 1019 domain = (desc >> 5) & 0x0f;
1020 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
9ee6e8bb 1021 if (type == 0) {
601d70b9 1022 /* Section translation fault. */
9ee6e8bb
PB		 1023 code = 5;
1024 goto do_fault;
1025 }
dd4ebc2e 1026 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1027 if (type == 2)
1028 code = 9; /* Section domain fault. */
1029 else
1030 code = 11; /* Page domain fault. */
1031 goto do_fault;
1032 }
1033 if (type == 2) {
1034 /* 1Mb section. */
1035 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1036 ap = (desc >> 10) & 3;
1037 code = 13;
d4c430a8 1038 *page_size = 1024 * 1024;
9ee6e8bb
PB		 1039 } else {
1040 /* Lookup l2 entry. */
1041 if (type == 1) {
1042 /* Coarse pagetable. */
1043 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1044 } else {
1045 /* Fine pagetable. */
1046 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
1047 }
1048 desc = ldl_phys(table);
1049 switch (desc & 3) {
1050 case 0: /* Page translation fault. */
1051 code = 7;
1052 goto do_fault;
1053 case 1: /* 64k page. */
1054 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1055 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1056 *page_size = 0x10000;
ce819861 1057 break;
9ee6e8bb
PB		 1058 case 2: /* 4k page. */
1059 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1060 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1061 *page_size = 0x1000;
ce819861 1062 break;
9ee6e8bb
PB		 1063 case 3: /* 1k page. */
1064 if (type == 1) {
1065 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1066 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1067 } else {
1068 /* Page translation fault. */
1069 code = 7;
1070 goto do_fault;
1071 }
1072 } else {
1073 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1074 }
1075 ap = (desc >> 4) & 3;
d4c430a8 1076 *page_size = 0x400;
ce819861
PB		 1077 break;
1078 default:
9ee6e8bb
PB		 1079 /* Never happens, but compiler isn't smart enough to tell. */
1080 abort();
ce819861 1081 }
9ee6e8bb
PB		 1082 code = 15;
1083 }
dd4ebc2e 1084 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
9ee6e8bb
PB		 1085 if (!*prot) {
1086 /* Access permission fault. */
1087 goto do_fault;
1088 }
3ad493fc 1089 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1090 *phys_ptr = phys_addr;
1091 return 0;
1092do_fault:
1093 return code | (domain << 4);
1094}
1095
1096static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
d4c430a8
PB		 1097 int is_user, uint32_t *phys_ptr, int *prot,
1098 target_ulong *page_size)
9ee6e8bb
PB		 1099{
1100 int code;
1101 uint32_t table;
1102 uint32_t desc;
1103 uint32_t xn;
1104 int type;
1105 int ap;
1106 int domain;
dd4ebc2e 1107 int domain_prot;
9ee6e8bb
PB		 1108 uint32_t phys_addr;
1109
1110 /* Pagetable walk. */
1111 /* Lookup l1 descriptor. */
b2fa1797 1112 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1113 desc = ldl_phys(table);
1114 type = (desc & 3);
1115 if (type == 0) {
601d70b9 1116 /* Section translation fault. */
9ee6e8bb
PB		 1117 code = 5;
1118 domain = 0;
1119 goto do_fault;
1120 } else if (type == 2 && (desc & (1 << 18))) {
1121 /* Supersection. */
1122 domain = 0;
b5ff1b31 1123 } else {
9ee6e8bb 1124 /* Section or page. */
dd4ebc2e 1125 domain = (desc >> 5) & 0x0f;
9ee6e8bb 1126 }
dd4ebc2e
JCD		 1127 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
1128 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1129 if (type == 2)
1130 code = 9; /* Section domain fault. */
1131 else
1132 code = 11; /* Page domain fault. */
1133 goto do_fault;
1134 }
1135 if (type == 2) {
1136 if (desc & (1 << 18)) {
1137 /* Supersection. */
1138 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 1139 *page_size = 0x1000000;
b5ff1b31 1140 } else {
9ee6e8bb
PB		 1141 /* Section. */
1142 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 1143 *page_size = 0x100000;
b5ff1b31 1144 }
9ee6e8bb
PB		 1145 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1146 xn = desc & (1 << 4);
1147 code = 13;
1148 } else {
1149 /* Lookup l2 entry. */
1150 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1151 desc = ldl_phys(table);
1152 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1153 switch (desc & 3) {
1154 case 0: /* Page translation fault. */
1155 code = 7;
b5ff1b31 1156 goto do_fault;
9ee6e8bb
PB		 1157 case 1: /* 64k page. */
1158 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1159 xn = desc & (1 << 15);
d4c430a8 1160 *page_size = 0x10000;
9ee6e8bb
PB		 1161 break;
1162 case 2: case 3: /* 4k page. */
1163 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1164 xn = desc & 1;
d4c430a8 1165 *page_size = 0x1000;
9ee6e8bb
PB		 1166 break;
1167 default:
1168 /* Never happens, but compiler isn't smart enough to tell. */
1169 abort();
b5ff1b31 1170 }
9ee6e8bb
PB		 1171 code = 15;
1172 }
dd4ebc2e 1173 if (domain_prot == 3) {
c0034328
JR		 1174 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1175 } else {
1176 if (xn && access_type == 2)
1177 goto do_fault;
9ee6e8bb 1178
c0034328
JR		 1179 /* The simplified model uses AP[0] as an access control bit. */
1180 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1181 /* Access flag fault. */
1182 code = (code == 15) ? 6 : 3;
1183 goto do_fault;
1184 }
dd4ebc2e 1185 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
c0034328
JR		 1186 if (!*prot) {
1187 /* Access permission fault. */
1188 goto do_fault;
1189 }
1190 if (!xn) {
1191 *prot |= PAGE_EXEC;
1192 }
3ad493fc 1193 }
9ee6e8bb 1194 *phys_ptr = phys_addr;
b5ff1b31
FB		 1195 return 0;
1196do_fault:
1197 return code | (domain << 4);
1198}
1199
9ee6e8bb
PB		 1200static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
1201 int is_user, uint32_t *phys_ptr, int *prot)
1202{
1203 int n;
1204 uint32_t mask;
1205 uint32_t base;
1206
1207 *phys_ptr = address;
1208 for (n = 7; n >= 0; n--) {
1209 base = env->cp15.c6_region[n];
1210 if ((base & 1) == 0)
1211 continue;
1212 mask = 1 << ((base >> 1) & 0x1f);
1213 /* Keep this shift separate from the above to avoid an
1214 (undefined) << 32. */
1215 mask = (mask << 1) - 1;
1216 if (((base ^ address) & ~mask) == 0)
1217 break;
1218 }
1219 if (n < 0)
1220 return 2;
1221
1222 if (access_type == 2) {
1223 mask = env->cp15.c5_insn;
1224 } else {
1225 mask = env->cp15.c5_data;
1226 }
1227 mask = (mask >> (n * 4)) & 0xf;
1228 switch (mask) {
1229 case 0:
1230 return 1;
1231 case 1:
1232 if (is_user)
1233 return 1;
1234 *prot = PAGE_READ | PAGE_WRITE;
1235 break;
1236 case 2:
1237 *prot = PAGE_READ;
1238 if (!is_user)
1239 *prot |= PAGE_WRITE;
1240 break;
1241 case 3:
1242 *prot = PAGE_READ | PAGE_WRITE;
1243 break;
1244 case 5:
1245 if (is_user)
1246 return 1;
1247 *prot = PAGE_READ;
1248 break;
1249 case 6:
1250 *prot = PAGE_READ;
1251 break;
1252 default:
1253 /* Bad permission. */
1254 return 1;
1255 }
3ad493fc 1256 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1257 return 0;
1258}
1259
1260static inline int get_phys_addr(CPUState *env, uint32_t address,
1261 int access_type, int is_user,
d4c430a8
PB		 1262 uint32_t *phys_ptr, int *prot,
1263 target_ulong *page_size)
9ee6e8bb
PB		 1264{
1265 /* Fast Context Switch Extension. */
1266 if (address < 0x02000000)
1267 address += env->cp15.c13_fcse;
1268
1269 if ((env->cp15.c1_sys & 1) == 0) {
1270 /* MMU/MPU disabled. */
1271 *phys_ptr = address;
3ad493fc 1272 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 1273 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1274 return 0;
1275 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 1276 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1277 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1278 prot);
1279 } else if (env->cp15.c1_sys & (1 << 23)) {
1280 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 1281 prot, page_size);
9ee6e8bb
PB		 1282 } else {
1283 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 1284 prot, page_size);
9ee6e8bb
PB		 1285 }
1286}
1287
b5ff1b31 1288int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
97b348e7 1289 int access_type, int mmu_idx)
b5ff1b31
FB		 1290{
1291 uint32_t phys_addr;
d4c430a8 1292 target_ulong page_size;
b5ff1b31 1293 int prot;
6ebbf390 1294 int ret, is_user;
b5ff1b31 1295
6ebbf390 1296 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 1297 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
1298 &page_size);
b5ff1b31
FB		 1299 if (ret == 0) {
1300 /* Map a single [sub]page. */
1301 phys_addr &= ~(uint32_t)0x3ff;
1302 address &= ~(uint32_t)0x3ff;
3ad493fc 1303 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 1304 return 0;
b5ff1b31
FB		 1305 }
1306
1307 if (access_type == 2) {
1308 env->cp15.c5_insn = ret;
1309 env->cp15.c6_insn = address;
1310 env->exception_index = EXCP_PREFETCH_ABORT;
1311 } else {
1312 env->cp15.c5_data = ret;
9ee6e8bb
PB		 1313 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1314 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 1315 env->cp15.c6_data = address;
1316 env->exception_index = EXCP_DATA_ABORT;
1317 }
1318 return 1;
1319}
1320
c227f099 1321target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
b5ff1b31
FB		 1322{
1323 uint32_t phys_addr;
d4c430a8 1324 target_ulong page_size;
b5ff1b31
FB		 1325 int prot;
1326 int ret;
1327
d4c430a8 1328 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 1329
1330 if (ret != 0)
1331 return -1;
1332
1333 return phys_addr;
1334}
1335
8984bd2e 1336void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 1337{
1338 int cp_num = (insn >> 8) & 0xf;
1339 int cp_info = (insn >> 5) & 7;
1340 int src = (insn >> 16) & 0xf;
1341 int operand = insn & 0xf;
1342
1343 if (env->cp[cp_num].cp_write)
1344 env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1345 cp_info, src, operand, val);
1346}
1347
8984bd2e 1348uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 1349{
1350 int cp_num = (insn >> 8) & 0xf;
1351 int cp_info = (insn >> 5) & 7;
1352 int dest = (insn >> 16) & 0xf;
1353 int operand = insn & 0xf;
1354
1355 if (env->cp[cp_num].cp_read)
1356 return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1357 cp_info, dest, operand);
1358 return 0;
1359}
1360
ce819861
PB		 1361/* Return basic MPU access permission bits. */
1362static uint32_t simple_mpu_ap_bits(uint32_t val)
1363{
1364 uint32_t ret;
1365 uint32_t mask;
1366 int i;
1367 ret = 0;
1368 mask = 3;
1369 for (i = 0; i < 16; i += 2) {
1370 ret |= (val >> i) & mask;
1371 mask <<= 2;
1372 }
1373 return ret;
1374}
1375
1376/* Pad basic MPU access permission bits to extended format. */
1377static uint32_t extended_mpu_ap_bits(uint32_t val)
1378{
1379 uint32_t ret;
1380 uint32_t mask;
1381 int i;
1382 ret = 0;
1383 mask = 3;
1384 for (i = 0; i < 16; i += 2) {
1385 ret |= (val & mask) << i;
1386 mask <<= 2;
1387 }
1388 return ret;
1389}
1390
8984bd2e 1391void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31 1392{
9ee6e8bb
PB		 1393 int op1;
1394 int op2;
1395 int crm;
b5ff1b31 1396
9ee6e8bb 1397 op1 = (insn >> 21) & 7;
b5ff1b31 1398 op2 = (insn >> 5) & 7;
ce819861 1399 crm = insn & 0xf;
b5ff1b31 1400 switch ((insn >> 16) & 0xf) {
9ee6e8bb 1401 case 0:
9ee6e8bb 1402 /* ID codes. */
610c3c8a
AZ		 1403 if (arm_feature(env, ARM_FEATURE_XSCALE))
1404 break;
c3d2689d
AZ		 1405 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1406 break;
a49ea279
PB		 1407 if (arm_feature(env, ARM_FEATURE_V7)
1408 && op1 == 2 && crm == 0 && op2 == 0) {
1409 env->cp15.c0_cssel = val & 0xf;
1410 break;
1411 }
b5ff1b31
FB		 1412 goto bad_reg;
1413 case 1: /* System configuration. */
c3d2689d
AZ		 1414 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1415 op2 = 0;
b5ff1b31
FB		 1416 switch (op2) {
1417 case 0:
ce819861 1418 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
c1713132 1419 env->cp15.c1_sys = val;
b5ff1b31
FB		 1420 /* ??? Lots of these bits are not implemented. */
1421 /* This may enable/disable the MMU, so do a TLB flush. */
1422 tlb_flush(env, 1);
1423 break;
61cc8701 1424 case 1: /* Auxiliary control register. */
610c3c8a
AZ		 1425 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1426 env->cp15.c1_xscaleauxcr = val;
c1713132 1427 break;
610c3c8a 1428 }
9ee6e8bb
PB		 1429 /* Not implemented. */
1430 break;
b5ff1b31 1431 case 2:
610c3c8a
AZ		 1432 if (arm_feature(env, ARM_FEATURE_XSCALE))
1433 goto bad_reg;
4be27dbb
PB		 1434 if (env->cp15.c1_coproc != val) {
1435 env->cp15.c1_coproc = val;
1436 /* ??? Is this safe when called from within a TB? */
1437 tb_flush(env);
1438 }
c1713132 1439 break;
b5ff1b31
FB		 1440 default:
1441 goto bad_reg;
1442 }
1443 break;
ce819861
PB		 1444 case 2: /* MMU Page table control / MPU cache control. */
1445 if (arm_feature(env, ARM_FEATURE_MPU)) {
1446 switch (op2) {
1447 case 0:
1448 env->cp15.c2_data = val;
1449 break;
1450 case 1:
1451 env->cp15.c2_insn = val;
1452 break;
1453 default:
1454 goto bad_reg;
1455 }
1456 } else {
9ee6e8bb
PB		 1457 switch (op2) {
1458 case 0:
1459 env->cp15.c2_base0 = val;
1460 break;
1461 case 1:
1462 env->cp15.c2_base1 = val;
1463 break;
1464 case 2:
b2fa1797
PB		 1465 val &= 7;
1466 env->cp15.c2_control = val;
9ee6e8bb 1467 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
b2fa1797 1468 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
9ee6e8bb
PB		 1469 break;
1470 default:
1471 goto bad_reg;
1472 }
ce819861 1473 }
b5ff1b31 1474 break;
ce819861 1475 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31 1476 env->cp15.c3 = val;
405ee3ad 1477 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
b5ff1b31
FB		 1478 break;
1479 case 4: /* Reserved. */
1480 goto bad_reg;
ce819861 1481 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1482 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1483 op2 = 0;
b5ff1b31
FB		 1484 switch (op2) {
1485 case 0:
ce819861
PB		 1486 if (arm_feature(env, ARM_FEATURE_MPU))
1487 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1488 env->cp15.c5_data = val;
1489 break;
1490 case 1:
ce819861
PB		 1491 if (arm_feature(env, ARM_FEATURE_MPU))
1492 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1493 env->cp15.c5_insn = val;
1494 break;
ce819861
PB		 1495 case 2:
1496 if (!arm_feature(env, ARM_FEATURE_MPU))
1497 goto bad_reg;
1498 env->cp15.c5_data = val;
b5ff1b31 1499 break;
ce819861
PB		 1500 case 3:
1501 if (!arm_feature(env, ARM_FEATURE_MPU))
1502 goto bad_reg;
1503 env->cp15.c5_insn = val;
b5ff1b31
FB		 1504 break;
1505 default:
1506 goto bad_reg;
1507 }
1508 break;
ce819861
PB		 1509 case 6: /* MMU Fault address / MPU base/size. */
1510 if (arm_feature(env, ARM_FEATURE_MPU)) {
1511 if (crm >= 8)
1512 goto bad_reg;
1513 env->cp15.c6_region[crm] = val;
1514 } else {
c3d2689d
AZ		 1515 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1516 op2 = 0;
ce819861
PB		 1517 switch (op2) {
1518 case 0:
1519 env->cp15.c6_data = val;
1520 break;
9ee6e8bb
PB		 1521 case 1: /* ??? This is WFAR on armv6 */
1522 case 2:
ce819861
PB		 1523 env->cp15.c6_insn = val;
1524 break;
1525 default:
1526 goto bad_reg;
1527 }
1528 }
1529 break;
b5ff1b31 1530 case 7: /* Cache control. */
c3d2689d
AZ		 1531 env->cp15.c15_i_max = 0x000;
1532 env->cp15.c15_i_min = 0xff0;
f8bf8606
AL		 1533 if (op1 != 0) {
1534 goto bad_reg;
1535 }
1536 /* No cache, so nothing to do except VA->PA translations. */
906879a9 1537 if (arm_feature(env, ARM_FEATURE_VAPA)) {
f8bf8606
AL		 1538 switch (crm) {
1539 case 4:
1540 if (arm_feature(env, ARM_FEATURE_V7)) {
1541 env->cp15.c7_par = val & 0xfffff6ff;
1542 } else {
1543 env->cp15.c7_par = val & 0xfffff1ff;
1544 }
1545 break;
1546 case 8: {
1547 uint32_t phys_addr;
1548 target_ulong page_size;
1549 int prot;
1550 int ret, is_user = op2 & 2;
1551 int access_type = op2 & 1;
1552
1553 if (op2 & 4) {
1554 /* Other states are only available with TrustZone */
1555 goto bad_reg;
1556 }
1557 ret = get_phys_addr(env, val, access_type, is_user,
1558 &phys_addr, &prot, &page_size);
1559 if (ret == 0) {
1560 /* We do not set any attribute bits in the PAR */
1561 if (page_size == (1 << 24)
1562 && arm_feature(env, ARM_FEATURE_V7)) {
1563 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1564 } else {
1565 env->cp15.c7_par = phys_addr & 0xfffff000;
1566 }
1567 } else {
1568 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1569 ((ret & (12 << 1)) >> 6) |
1570 ((ret & 0xf) << 1) | 1;
1571 }
1572 break;
1573 }
1574 }
1575 }
b5ff1b31
FB		 1576 break;
1577 case 8: /* MMU TLB control. */
1578 switch (op2) {
1579 case 0: /* Invalidate all. */
1580 tlb_flush(env, 0);
1581 break;
1582 case 1: /* Invalidate single TLB entry. */
d4c430a8 1583 tlb_flush_page(env, val & TARGET_PAGE_MASK);
b5ff1b31 1584 break;
9ee6e8bb
PB		 1585 case 2: /* Invalidate on ASID. */
1586 tlb_flush(env, val == 0);
1587 break;
1588 case 3: /* Invalidate single entry on MVA. */
1589 /* ??? This is like case 1, but ignores ASID. */
1590 tlb_flush(env, 1);
1591 break;
b5ff1b31
FB		 1592 default:
1593 goto bad_reg;
1594 }
1595 break;
ce819861 1596 case 9:
c3d2689d
AZ		 1597 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1598 break;
5bc95aa2
DES		 1599 if (arm_feature(env, ARM_FEATURE_STRONGARM))
1600 break; /* Ignore ReadBuffer access */
ce819861
PB		 1601 switch (crm) {
1602 case 0: /* Cache lockdown. */
9ee6e8bb
PB		 1603 switch (op1) {
1604 case 0: /* L1 cache. */
1605 switch (op2) {
1606 case 0:
1607 env->cp15.c9_data = val;
1608 break;
1609 case 1:
1610 env->cp15.c9_insn = val;
1611 break;
1612 default:
1613 goto bad_reg;
1614 }
1615 break;
1616 case 1: /* L2 cache. */
1617 /* Ignore writes to L2 lockdown/auxiliary registers. */
1618 break;
1619 default:
1620 goto bad_reg;
1621 }
1622 break;
ce819861
PB		 1623 case 1: /* TCM memory region registers. */
1624 /* Not implemented. */
1625 goto bad_reg;
74594c9d
PM		 1626 case 12: /* Performance monitor control */
1627 /* Performance monitors are implementation defined in v7,
1628 * but with an ARM recommended set of registers, which we
1629 * follow (although we don't actually implement any counters)
1630 */
1631 if (!arm_feature(env, ARM_FEATURE_V7)) {
1632 goto bad_reg;
1633 }
1634 switch (op2) {
1635 case 0: /* performance monitor control register */
1636 /* only the DP, X, D and E bits are writable */
1637 env->cp15.c9_pmcr &= ~0x39;
1638 env->cp15.c9_pmcr |= (val & 0x39);
1639 break;
1640 case 1: /* Count enable set register */
1641 val &= (1 << 31);
1642 env->cp15.c9_pmcnten |= val;
1643 break;
1644 case 2: /* Count enable clear */
1645 val &= (1 << 31);
1646 env->cp15.c9_pmcnten &= ~val;
1647 break;
1648 case 3: /* Overflow flag status */
1649 env->cp15.c9_pmovsr &= ~val;
1650 break;
1651 case 4: /* Software increment */
1652 /* RAZ/WI since we don't implement the software-count event */
1653 break;
1654 case 5: /* Event counter selection register */
1655 /* Since we don't implement any events, writing to this register
1656 * is actually UNPREDICTABLE. So we choose to RAZ/WI.
1657 */
1658 break;
1659 default:
1660 goto bad_reg;
1661 }
1662 break;
1663 case 13: /* Performance counters */
1664 if (!arm_feature(env, ARM_FEATURE_V7)) {
1665 goto bad_reg;
1666 }
1667 switch (op2) {
1668 case 0: /* Cycle count register: not implemented, so RAZ/WI */
1669 break;
1670 case 1: /* Event type select */
1671 env->cp15.c9_pmxevtyper = val & 0xff;
1672 break;
1673 case 2: /* Event count register */
1674 /* Unimplemented (we have no events), RAZ/WI */
1675 break;
1676 default:
1677 goto bad_reg;
1678 }
1679 break;
1680 case 14: /* Performance monitor control */
1681 if (!arm_feature(env, ARM_FEATURE_V7)) {
1682 goto bad_reg;
1683 }
1684 switch (op2) {
1685 case 0: /* user enable */
1686 env->cp15.c9_pmuserenr = val & 1;
1687 /* changes access rights for cp registers, so flush tbs */
1688 tb_flush(env);
1689 break;
1690 case 1: /* interrupt enable set */
1691 /* We have no event counters so only the C bit can be changed */
1692 val &= (1 << 31);
1693 env->cp15.c9_pminten |= val;
1694 break;
1695 case 2: /* interrupt enable clear */
1696 val &= (1 << 31);
1697 env->cp15.c9_pminten &= ~val;
1698 break;
1699 }
1700 break;
b5ff1b31
FB		 1701 default:
1702 goto bad_reg;
1703 }
1704 break;
1705 case 10: /* MMU TLB lockdown. */
1706 /* ??? TLB lockdown not implemented. */
1707 break;
b5ff1b31
FB		 1708 case 12: /* Reserved. */
1709 goto bad_reg;
1710 case 13: /* Process ID. */
1711 switch (op2) {
1712 case 0:
d07edbfa
PB		 1713 /* Unlike real hardware the qemu TLB uses virtual addresses,
1714 not modified virtual addresses, so this causes a TLB flush.
1715 */
1716 if (env->cp15.c13_fcse != val)
1717 tlb_flush(env, 1);
1718 env->cp15.c13_fcse = val;
b5ff1b31
FB		 1719 break;
1720 case 1:
d07edbfa 1721 /* This changes the ASID, so do a TLB flush. */
ce819861
PB		 1722 if (env->cp15.c13_context != val
1723 && !arm_feature(env, ARM_FEATURE_MPU))
d07edbfa
PB		 1724 tlb_flush(env, 0);
1725 env->cp15.c13_context = val;
b5ff1b31
FB		 1726 break;
1727 default:
1728 goto bad_reg;
1729 }
1730 break;
1731 case 14: /* Reserved. */
1732 goto bad_reg;
1733 case 15: /* Implementation specific. */
c1713132 1734 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
ce819861 1735 if (op2 == 0 && crm == 1) {
2e23213f
AZ		 1736 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1737 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1738 tb_flush(env);
1739 env->cp15.c15_cpar = val & 0x3fff;
1740 }
c1713132
AZ		 1741 break;
1742 }
1743 goto bad_reg;
1744 }
c3d2689d
AZ		 1745 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1746 switch (crm) {
1747 case 0:
1748 break;
1749 case 1: /* Set TI925T configuration. */
1750 env->cp15.c15_ticonfig = val & 0xe7;
1751 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1752 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1753 break;
1754 case 2: /* Set I_max. */
1755 env->cp15.c15_i_max = val;
1756 break;
1757 case 3: /* Set I_min. */
1758 env->cp15.c15_i_min = val;
1759 break;
1760 case 4: /* Set thread-ID. */
1761 env->cp15.c15_threadid = val & 0xffff;
1762 break;
1763 case 8: /* Wait-for-interrupt (deprecated). */
1764 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1765 break;
1766 default:
1767 goto bad_reg;
1768 }
1769 }
b5ff1b31
FB		 1770 break;
1771 }
1772 return;
1773bad_reg:
1774 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1775 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1776 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1777}
1778
8984bd2e 1779uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31 1780{
9ee6e8bb
PB		 1781 int op1;
1782 int op2;
1783 int crm;
b5ff1b31 1784
9ee6e8bb 1785 op1 = (insn >> 21) & 7;
b5ff1b31 1786 op2 = (insn >> 5) & 7;
c3d2689d 1787 crm = insn & 0xf;
b5ff1b31
FB		 1788 switch ((insn >> 16) & 0xf) {
1789 case 0: /* ID codes. */
9ee6e8bb
PB		 1790 switch (op1) {
1791 case 0:
1792 switch (crm) {
1793 case 0:
1794 switch (op2) {
1795 case 0: /* Device ID. */
1796 return env->cp15.c0_cpuid;
1797 case 1: /* Cache Type. */
1798 return env->cp15.c0_cachetype;
1799 case 2: /* TCM status. */
1800 return 0;
1801 case 3: /* TLB type register. */
1802 return 0; /* No lockable TLB entries. */
607b4b08
PM		 1803 case 5: /* MPIDR */
1804 /* The MPIDR was standardised in v7; prior to
1805 * this it was implemented only in the 11MPCore.
1806 * For all other pre-v7 cores it does not exist.
1807 */
1808 if (arm_feature(env, ARM_FEATURE_V7) ||
1809 ARM_CPUID(env) == ARM_CPUID_ARM11MPCORE) {
1810 int mpidr = env->cpu_index;
1811 /* We don't support setting cluster ID ([8..11])
1812 * so these bits always RAZ.
1813 */
1814 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1815 mpidr |= (1 << 31);
1816 /* Cores which are uniprocessor (non-coherent)
1817 * but still implement the MP extensions set
1818 * bit 30. (For instance, A9UP.) However we do
1819 * not currently model any of those cores.
1820 */
1821 }
1822 return mpidr;
10055562 1823 }
607b4b08 1824 /* otherwise fall through to the unimplemented-reg case */
9ee6e8bb
PB		 1825 default:
1826 goto bad_reg;
1827 }
1828 case 1:
1829 if (!arm_feature(env, ARM_FEATURE_V6))
1830 goto bad_reg;
1831 return env->cp15.c0_c1[op2];
1832 case 2:
1833 if (!arm_feature(env, ARM_FEATURE_V6))
1834 goto bad_reg;
1835 return env->cp15.c0_c2[op2];
1836 case 3: case 4: case 5: case 6: case 7:
1837 return 0;
1838 default:
1839 goto bad_reg;
1840 }
1841 case 1:
1842 /* These registers aren't documented on arm11 cores. However
1843 Linux looks at them anyway. */
1844 if (!arm_feature(env, ARM_FEATURE_V6))
1845 goto bad_reg;
1846 if (crm != 0)
1847 goto bad_reg;
a49ea279
PB		 1848 if (!arm_feature(env, ARM_FEATURE_V7))
1849 return 0;
1850
1851 switch (op2) {
1852 case 0:
1853 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1854 case 1:
1855 return env->cp15.c0_clid;
1856 case 7:
1857 return 0;
1858 }
1859 goto bad_reg;
1860 case 2:
1861 if (op2 != 0 || crm != 0)
610c3c8a 1862 goto bad_reg;
a49ea279 1863 return env->cp15.c0_cssel;
9ee6e8bb
PB		 1864 default:
1865 goto bad_reg;
b5ff1b31
FB		 1866 }
1867 case 1: /* System configuration. */
c3d2689d
AZ		 1868 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1869 op2 = 0;
b5ff1b31
FB		 1870 switch (op2) {
1871 case 0: /* Control register. */
1872 return env->cp15.c1_sys;
1873 case 1: /* Auxiliary control register. */
c1713132 1874 if (arm_feature(env, ARM_FEATURE_XSCALE))
610c3c8a 1875 return env->cp15.c1_xscaleauxcr;
9ee6e8bb
PB		 1876 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1877 goto bad_reg;
1878 switch (ARM_CPUID(env)) {
1879 case ARM_CPUID_ARM1026:
1880 return 1;
1881 case ARM_CPUID_ARM1136:
827df9f3 1882 case ARM_CPUID_ARM1136_R2:
7807eed9 1883 case ARM_CPUID_ARM1176:
9ee6e8bb
PB		 1884 return 7;
1885 case ARM_CPUID_ARM11MPCORE:
1886 return 1;
1887 case ARM_CPUID_CORTEXA8:
533d177a 1888 return 2;
10055562
PB		 1889 case ARM_CPUID_CORTEXA9:
1890 return 0;
9ee6e8bb
PB		 1891 default:
1892 goto bad_reg;
1893 }
b5ff1b31 1894 case 2: /* Coprocessor access register. */
610c3c8a
AZ		 1895 if (arm_feature(env, ARM_FEATURE_XSCALE))
1896 goto bad_reg;
b5ff1b31
FB		 1897 return env->cp15.c1_coproc;
1898 default:
1899 goto bad_reg;
1900 }
ce819861
PB		 1901 case 2: /* MMU Page table control / MPU cache control. */
1902 if (arm_feature(env, ARM_FEATURE_MPU)) {
1903 switch (op2) {
1904 case 0:
1905 return env->cp15.c2_data;
1906 break;
1907 case 1:
1908 return env->cp15.c2_insn;
1909 break;
1910 default:
1911 goto bad_reg;
1912 }
1913 } else {
9ee6e8bb
PB		 1914 switch (op2) {
1915 case 0:
1916 return env->cp15.c2_base0;
1917 case 1:
1918 return env->cp15.c2_base1;
1919 case 2:
b2fa1797 1920 return env->cp15.c2_control;
9ee6e8bb
PB		 1921 default:
1922 goto bad_reg;
1923 }
1924 }
ce819861 1925 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31
FB		 1926 return env->cp15.c3;
1927 case 4: /* Reserved. */
1928 goto bad_reg;
ce819861 1929 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1930 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1931 op2 = 0;
b5ff1b31
FB		 1932 switch (op2) {
1933 case 0:
ce819861
PB		 1934 if (arm_feature(env, ARM_FEATURE_MPU))
1935 return simple_mpu_ap_bits(env->cp15.c5_data);
b5ff1b31
FB		 1936 return env->cp15.c5_data;
1937 case 1:
ce819861
PB		 1938 if (arm_feature(env, ARM_FEATURE_MPU))
1939 return simple_mpu_ap_bits(env->cp15.c5_data);
1940 return env->cp15.c5_insn;
1941 case 2:
1942 if (!arm_feature(env, ARM_FEATURE_MPU))
1943 goto bad_reg;
1944 return env->cp15.c5_data;
1945 case 3:
1946 if (!arm_feature(env, ARM_FEATURE_MPU))
1947 goto bad_reg;
b5ff1b31
FB		 1948 return env->cp15.c5_insn;
1949 default:
1950 goto bad_reg;
1951 }
9ee6e8bb 1952 case 6: /* MMU Fault address. */
ce819861 1953 if (arm_feature(env, ARM_FEATURE_MPU)) {
9ee6e8bb 1954 if (crm >= 8)
ce819861 1955 goto bad_reg;
9ee6e8bb 1956 return env->cp15.c6_region[crm];
ce819861 1957 } else {
c3d2689d
AZ		 1958 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1959 op2 = 0;
9ee6e8bb
PB		 1960 switch (op2) {
1961 case 0:
1962 return env->cp15.c6_data;
1963 case 1:
1964 if (arm_feature(env, ARM_FEATURE_V6)) {
1965 /* Watchpoint Fault Adrress. */
1966 return 0; /* Not implemented. */
1967 } else {
1968 /* Instruction Fault Adrress. */
1969 /* Arm9 doesn't have an IFAR, but implementing it anyway
1970 shouldn't do any harm. */
1971 return env->cp15.c6_insn;
1972 }
1973 case 2:
1974 if (arm_feature(env, ARM_FEATURE_V6)) {
1975 /* Instruction Fault Adrress. */
1976 return env->cp15.c6_insn;
1977 } else {
1978 goto bad_reg;
1979 }
1980 default:
1981 goto bad_reg;
1982 }
b5ff1b31
FB		 1983 }
1984 case 7: /* Cache control. */
f8bf8606
AL		 1985 if (crm == 4 && op1 == 0 && op2 == 0) {
1986 return env->cp15.c7_par;
1987 }
6fbe23d5
PB		 1988 /* FIXME: Should only clear Z flag if destination is r15. */
1989 env->ZF = 0;
b5ff1b31
FB		 1990 return 0;
1991 case 8: /* MMU TLB control. */
1992 goto bad_reg;
74594c9d
PM		 1993 case 9:
1994 switch (crm) {
1995 case 0: /* Cache lockdown */
1996 switch (op1) {
1997 case 0: /* L1 cache. */
1998 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1999 return 0;
2000 }
2001 switch (op2) {
2002 case 0:
2003 return env->cp15.c9_data;
2004 case 1:
2005 return env->cp15.c9_insn;
2006 default:
2007 goto bad_reg;
2008 }
2009 case 1: /* L2 cache */
2010 if (crm != 0) {
2011 goto bad_reg;
2012 }
2013 /* L2 Lockdown and Auxiliary control. */
2014 return 0;
2015 default:
2016 goto bad_reg;
2017 }
2018 break;
2019 case 12: /* Performance monitor control */
2020 if (!arm_feature(env, ARM_FEATURE_V7)) {
2021 goto bad_reg;
2022 }
9ee6e8bb 2023 switch (op2) {
74594c9d
PM		 2024 case 0: /* performance monitor control register */
2025 return env->cp15.c9_pmcr;
2026 case 1: /* count enable set */
2027 case 2: /* count enable clear */
2028 return env->cp15.c9_pmcnten;
2029 case 3: /* overflow flag status */
2030 return env->cp15.c9_pmovsr;
2031 case 4: /* software increment */
2032 case 5: /* event counter selection register */
2033 return 0; /* Unimplemented, RAZ/WI */
9ee6e8bb
PB		 2034 default:
2035 goto bad_reg;
2036 }
74594c9d
PM		 2037 case 13: /* Performance counters */
2038 if (!arm_feature(env, ARM_FEATURE_V7)) {
2039 goto bad_reg;
2040 }
2041 switch (op2) {
2042 case 1: /* Event type select */
2043 return env->cp15.c9_pmxevtyper;
2044 case 0: /* Cycle count register */
2045 case 2: /* Event count register */
2046 /* Unimplemented, so RAZ/WI */
2047 return 0;
2048 default:
9ee6e8bb 2049 goto bad_reg;
74594c9d
PM		 2050 }
2051 case 14: /* Performance monitor control */
2052 if (!arm_feature(env, ARM_FEATURE_V7)) {
2053 goto bad_reg;
2054 }
2055 switch (op2) {
2056 case 0: /* user enable */
2057 return env->cp15.c9_pmuserenr;
2058 case 1: /* interrupt enable set */
2059 case 2: /* interrupt enable clear */
2060 return env->cp15.c9_pminten;
2061 default:
2062 goto bad_reg;
2063 }
b5ff1b31
FB		 2064 default:
2065 goto bad_reg;
2066 }
74594c9d 2067 break;
b5ff1b31
FB		 2068 case 10: /* MMU TLB lockdown. */
2069 /* ??? TLB lockdown not implemented. */
2070 return 0;
2071 case 11: /* TCM DMA control. */
2072 case 12: /* Reserved. */
2073 goto bad_reg;
2074 case 13: /* Process ID. */
2075 switch (op2) {
2076 case 0:
2077 return env->cp15.c13_fcse;
2078 case 1:
2079 return env->cp15.c13_context;
2080 default:
2081 goto bad_reg;
2082 }
2083 case 14: /* Reserved. */
2084 goto bad_reg;
2085 case 15: /* Implementation specific. */
c1713132 2086 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
c3d2689d 2087 if (op2 == 0 && crm == 1)
c1713132
AZ		 2088 return env->cp15.c15_cpar;
2089
2090 goto bad_reg;
2091 }
c3d2689d
AZ		 2092 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2093 switch (crm) {
2094 case 0:
2095 return 0;
2096 case 1: /* Read TI925T configuration. */
2097 return env->cp15.c15_ticonfig;
2098 case 2: /* Read I_max. */
2099 return env->cp15.c15_i_max;
2100 case 3: /* Read I_min. */
2101 return env->cp15.c15_i_min;
2102 case 4: /* Read thread-ID. */
2103 return env->cp15.c15_threadid;
2104 case 8: /* TI925T_status */
2105 return 0;
2106 }
827df9f3
AZ		 2107 /* TODO: Peripheral port remap register:
2108 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
2109 * controller base address at $rn & ~0xfff and map size of
2110 * 0x200 << ($rn & 0xfff), when MMU is off. */
c3d2689d
AZ		 2111 goto bad_reg;
2112 }
b5ff1b31
FB		 2113 return 0;
2114 }
2115bad_reg:
2116 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 2117 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2118 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 2119 return 0;
2120}
2121
b0109805 2122void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb 2123{
39ea3d4e
PM		 2124 if ((env->uncached_cpsr & CPSR_M) == mode) {
2125 env->regs[13] = val;
2126 } else {
2127 env->banked_r13[bank_number(mode)] = val;
2128 }
9ee6e8bb
PB		 2129}
2130
b0109805 2131uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb 2132{
39ea3d4e
PM		 2133 if ((env->uncached_cpsr & CPSR_M) == mode) {
2134 return env->regs[13];
2135 } else {
2136 return env->banked_r13[bank_number(mode)];
2137 }
9ee6e8bb
PB		 2138}
2139
8984bd2e 2140uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 2141{
2142 switch (reg) {
2143 case 0: /* APSR */
2144 return xpsr_read(env) & 0xf8000000;
2145 case 1: /* IAPSR */
2146 return xpsr_read(env) & 0xf80001ff;
2147 case 2: /* EAPSR */
2148 return xpsr_read(env) & 0xff00fc00;
2149 case 3: /* xPSR */
2150 return xpsr_read(env) & 0xff00fdff;
2151 case 5: /* IPSR */
2152 return xpsr_read(env) & 0x000001ff;
2153 case 6: /* EPSR */
2154 return xpsr_read(env) & 0x0700fc00;
2155 case 7: /* IEPSR */
2156 return xpsr_read(env) & 0x0700edff;
2157 case 8: /* MSP */
2158 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2159 case 9: /* PSP */
2160 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2161 case 16: /* PRIMASK */
2162 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 2163 case 17: /* BASEPRI */
2164 case 18: /* BASEPRI_MAX */
9ee6e8bb 2165 return env->v7m.basepri;
82845826
SH		 2166 case 19: /* FAULTMASK */
2167 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 2168 case 20: /* CONTROL */
2169 return env->v7m.control;
2170 default:
2171 /* ??? For debugging only. */
2172 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2173 return 0;
2174 }
2175}
2176
8984bd2e 2177void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2178{
2179 switch (reg) {
2180 case 0: /* APSR */
2181 xpsr_write(env, val, 0xf8000000);
2182 break;
2183 case 1: /* IAPSR */
2184 xpsr_write(env, val, 0xf8000000);
2185 break;
2186 case 2: /* EAPSR */
2187 xpsr_write(env, val, 0xfe00fc00);
2188 break;
2189 case 3: /* xPSR */
2190 xpsr_write(env, val, 0xfe00fc00);
2191 break;
2192 case 5: /* IPSR */
2193 /* IPSR bits are readonly. */
2194 break;
2195 case 6: /* EPSR */
2196 xpsr_write(env, val, 0x0600fc00);
2197 break;
2198 case 7: /* IEPSR */
2199 xpsr_write(env, val, 0x0600fc00);
2200 break;
2201 case 8: /* MSP */
2202 if (env->v7m.current_sp)
2203 env->v7m.other_sp = val;
2204 else
2205 env->regs[13] = val;
2206 break;
2207 case 9: /* PSP */
2208 if (env->v7m.current_sp)
2209 env->regs[13] = val;
2210 else
2211 env->v7m.other_sp = val;
2212 break;
2213 case 16: /* PRIMASK */
2214 if (val & 1)
2215 env->uncached_cpsr |= CPSR_I;
2216 else
2217 env->uncached_cpsr &= ~CPSR_I;
2218 break;
82845826 2219 case 17: /* BASEPRI */
9ee6e8bb
PB		 2220 env->v7m.basepri = val & 0xff;
2221 break;
82845826 2222 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 2223 val &= 0xff;
2224 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2225 env->v7m.basepri = val;
2226 break;
82845826
SH		 2227 case 19: /* FAULTMASK */
2228 if (val & 1)
2229 env->uncached_cpsr |= CPSR_F;
2230 else
2231 env->uncached_cpsr &= ~CPSR_F;
2232 break;
9ee6e8bb
PB		 2233 case 20: /* CONTROL */
2234 env->v7m.control = val & 3;
2235 switch_v7m_sp(env, (val & 2) != 0);
2236 break;
2237 default:
2238 /* ??? For debugging only. */
2239 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2240 return;
2241 }
2242}
2243
c1713132
AZ		 2244void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
2245 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
2246 void *opaque)
2247{
2248 if (cpnum < 0 || cpnum > 14) {
2249 cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
2250 return;
2251 }
2252
2253 env->cp[cpnum].cp_read = cp_read;
2254 env->cp[cpnum].cp_write = cp_write;
2255 env->cp[cpnum].opaque = opaque;
2256}
2257
b5ff1b31 2258#endif
6ddbc6e4
PB		 2259
2260/* Note that signed overflow is undefined in C. The following routines are
2261 careful to use unsigned types where modulo arithmetic is required.
2262 Failure to do so _will_ break on newer gcc. */
2263
2264/* Signed saturating arithmetic. */
2265
1654b2d6 2266/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2267static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2268{
2269 uint16_t res;
2270
2271 res = a + b;
2272 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2273 if (a & 0x8000)
2274 res = 0x8000;
2275 else
2276 res = 0x7fff;
2277 }
2278 return res;
2279}
2280
1654b2d6 2281/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2282static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2283{
2284 uint8_t res;
2285
2286 res = a + b;
2287 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2288 if (a & 0x80)
2289 res = 0x80;
2290 else
2291 res = 0x7f;
2292 }
2293 return res;
2294}
2295
1654b2d6 2296/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2297static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2298{
2299 uint16_t res;
2300
2301 res = a - b;
2302 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2303 if (a & 0x8000)
2304 res = 0x8000;
2305 else
2306 res = 0x7fff;
2307 }
2308 return res;
2309}
2310
1654b2d6 2311/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2312static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2313{
2314 uint8_t res;
2315
2316 res = a - b;
2317 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2318 if (a & 0x80)
2319 res = 0x80;
2320 else
2321 res = 0x7f;
2322 }
2323 return res;
2324}
2325
2326#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2327#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2328#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2329#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2330#define PFX q
2331
2332#include "op_addsub.h"
2333
2334/* Unsigned saturating arithmetic. */
460a09c1 2335static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2336{
2337 uint16_t res;
2338 res = a + b;
2339 if (res < a)
2340 res = 0xffff;
2341 return res;
2342}
2343
460a09c1 2344static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2345{
4c4fd3f8 2346 if (a > b)
6ddbc6e4
PB		 2347 return a - b;
2348 else
2349 return 0;
2350}
2351
2352static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2353{
2354 uint8_t res;
2355 res = a + b;
2356 if (res < a)
2357 res = 0xff;
2358 return res;
2359}
2360
2361static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2362{
4c4fd3f8 2363 if (a > b)
6ddbc6e4
PB		 2364 return a - b;
2365 else
2366 return 0;
2367}
2368
2369#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2370#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2371#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2372#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2373#define PFX uq
2374
2375#include "op_addsub.h"
2376
2377/* Signed modulo arithmetic. */
2378#define SARITH16(a, b, n, op) do { \
2379 int32_t sum; \
db6e2e65 2380 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2381 RESULT(sum, n, 16); \
2382 if (sum >= 0) \
2383 ge |= 3 << (n * 2); \
2384 } while(0)
2385
2386#define SARITH8(a, b, n, op) do { \
2387 int32_t sum; \
db6e2e65 2388 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2389 RESULT(sum, n, 8); \
2390 if (sum >= 0) \
2391 ge |= 1 << n; \
2392 } while(0)
2393
2394
2395#define ADD16(a, b, n) SARITH16(a, b, n, +)
2396#define SUB16(a, b, n) SARITH16(a, b, n, -)
2397#define ADD8(a, b, n) SARITH8(a, b, n, +)
2398#define SUB8(a, b, n) SARITH8(a, b, n, -)
2399#define PFX s
2400#define ARITH_GE
2401
2402#include "op_addsub.h"
2403
2404/* Unsigned modulo arithmetic. */
2405#define ADD16(a, b, n) do { \
2406 uint32_t sum; \
2407 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2408 RESULT(sum, n, 16); \
a87aa10b 2409 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2410 ge |= 3 << (n * 2); \
2411 } while(0)
2412
2413#define ADD8(a, b, n) do { \
2414 uint32_t sum; \
2415 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2416 RESULT(sum, n, 8); \
a87aa10b
AZ		 2417 if ((sum >> 8) == 1) \
2418 ge |= 1 << n; \
6ddbc6e4
PB		 2419 } while(0)
2420
2421#define SUB16(a, b, n) do { \
2422 uint32_t sum; \
2423 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2424 RESULT(sum, n, 16); \
2425 if ((sum >> 16) == 0) \
2426 ge |= 3 << (n * 2); \
2427 } while(0)
2428
2429#define SUB8(a, b, n) do { \
2430 uint32_t sum; \
2431 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2432 RESULT(sum, n, 8); \
2433 if ((sum >> 8) == 0) \
a87aa10b 2434 ge |= 1 << n; \
6ddbc6e4
PB		 2435 } while(0)
2436
2437#define PFX u
2438#define ARITH_GE
2439
2440#include "op_addsub.h"
2441
2442/* Halved signed arithmetic. */
2443#define ADD16(a, b, n) \
2444 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2445#define SUB16(a, b, n) \
2446 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2447#define ADD8(a, b, n) \
2448 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2449#define SUB8(a, b, n) \
2450 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2451#define PFX sh
2452
2453#include "op_addsub.h"
2454
2455/* Halved unsigned arithmetic. */
2456#define ADD16(a, b, n) \
2457 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2458#define SUB16(a, b, n) \
2459 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2460#define ADD8(a, b, n) \
2461 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2462#define SUB8(a, b, n) \
2463 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2464#define PFX uh
2465
2466#include "op_addsub.h"
2467
2468static inline uint8_t do_usad(uint8_t a, uint8_t b)
2469{
2470 if (a > b)
2471 return a - b;
2472 else
2473 return b - a;
2474}
2475
2476/* Unsigned sum of absolute byte differences. */
2477uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2478{
2479 uint32_t sum;
2480 sum = do_usad(a, b);
2481 sum += do_usad(a >> 8, b >> 8);
2482 sum += do_usad(a >> 16, b >>16);
2483 sum += do_usad(a >> 24, b >> 24);
2484 return sum;
2485}
2486
2487/* For ARMv6 SEL instruction. */
2488uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2489{
2490 uint32_t mask;
2491
2492 mask = 0;
2493 if (flags & 1)
2494 mask |= 0xff;
2495 if (flags & 2)
2496 mask |= 0xff00;
2497 if (flags & 4)
2498 mask |= 0xff0000;
2499 if (flags & 8)
2500 mask |= 0xff000000;
2501 return (a & mask) | (b & ~mask);
2502}
2503
5e3f878a
PB		 2504uint32_t HELPER(logicq_cc)(uint64_t val)
2505{
2506 return (val >> 32) | (val != 0);
2507}
4373f3ce
PB		 2508
2509/* VFP support. We follow the convention used for VFP instrunctions:
2510 Single precition routines have a "s" suffix, double precision a
2511 "d" suffix. */
2512
2513/* Convert host exception flags to vfp form. */
2514static inline int vfp_exceptbits_from_host(int host_bits)
2515{
2516 int target_bits = 0;
2517
2518 if (host_bits & float_flag_invalid)
2519 target_bits |= 1;
2520 if (host_bits & float_flag_divbyzero)
2521 target_bits |= 2;
2522 if (host_bits & float_flag_overflow)
2523 target_bits |= 4;
36802b6b 2524 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 2525 target_bits |= 8;
2526 if (host_bits & float_flag_inexact)
2527 target_bits |= 0x10;
cecd8504
PM		 2528 if (host_bits & float_flag_input_denormal)
2529 target_bits |= 0x80;
4373f3ce
PB		 2530 return target_bits;
2531}
2532
2533uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
2534{
2535 int i;
2536 uint32_t fpscr;
2537
2538 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2539 | (env->vfp.vec_len << 16)
2540 | (env->vfp.vec_stride << 20);
2541 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2542 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2543 fpscr |= vfp_exceptbits_from_host(i);
2544 return fpscr;
2545}
2546
01653295
PM		 2547uint32_t vfp_get_fpscr(CPUState *env)
2548{
2549 return HELPER(vfp_get_fpscr)(env);
2550}
2551
4373f3ce
PB		 2552/* Convert vfp exception flags to target form. */
2553static inline int vfp_exceptbits_to_host(int target_bits)
2554{
2555 int host_bits = 0;
2556
2557 if (target_bits & 1)
2558 host_bits |= float_flag_invalid;
2559 if (target_bits & 2)
2560 host_bits |= float_flag_divbyzero;
2561 if (target_bits & 4)
2562 host_bits |= float_flag_overflow;
2563 if (target_bits & 8)
2564 host_bits |= float_flag_underflow;
2565 if (target_bits & 0x10)
2566 host_bits |= float_flag_inexact;
cecd8504
PM		 2567 if (target_bits & 0x80)
2568 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2569 return host_bits;
2570}
2571
2572void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
2573{
2574 int i;
2575 uint32_t changed;
2576
2577 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2578 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2579 env->vfp.vec_len = (val >> 16) & 7;
2580 env->vfp.vec_stride = (val >> 20) & 3;
2581
2582 changed ^= val;
2583 if (changed & (3 << 22)) {
2584 i = (val >> 22) & 3;
2585 switch (i) {
2586 case 0:
2587 i = float_round_nearest_even;
2588 break;
2589 case 1:
2590 i = float_round_up;
2591 break;
2592 case 2:
2593 i = float_round_down;
2594 break;
2595 case 3:
2596 i = float_round_to_zero;
2597 break;
2598 }
2599 set_float_rounding_mode(i, &env->vfp.fp_status);
2600 }
cecd8504 2601 if (changed & (1 << 24)) {
fe76d976 2602 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 2603 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2604 }
5c7908ed
PB		 2605 if (changed & (1 << 25))
2606 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 2607
b12c390b 2608 i = vfp_exceptbits_to_host(val);
4373f3ce 2609 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 2610 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 2611}
2612
01653295
PM		 2613void vfp_set_fpscr(CPUState *env, uint32_t val)
2614{
2615 HELPER(vfp_set_fpscr)(env, val);
2616}
2617
4373f3ce
PB		 2618#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2619
2620#define VFP_BINOP(name) \
ae1857ec 2621float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 2622{ \
ae1857ec
PM		 2623 float_status *fpst = fpstp; \
2624 return float32_ ## name(a, b, fpst); \
4373f3ce 2625} \
ae1857ec 2626float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 2627{ \
ae1857ec
PM		 2628 float_status *fpst = fpstp; \
2629 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 2630}
2631VFP_BINOP(add)
2632VFP_BINOP(sub)
2633VFP_BINOP(mul)
2634VFP_BINOP(div)
2635#undef VFP_BINOP
2636
2637float32 VFP_HELPER(neg, s)(float32 a)
2638{
2639 return float32_chs(a);
2640}
2641
2642float64 VFP_HELPER(neg, d)(float64 a)
2643{
66230e0d 2644 return float64_chs(a);
4373f3ce
PB		 2645}
2646
2647float32 VFP_HELPER(abs, s)(float32 a)
2648{
2649 return float32_abs(a);
2650}
2651
2652float64 VFP_HELPER(abs, d)(float64 a)
2653{
66230e0d 2654 return float64_abs(a);
4373f3ce
PB		 2655}
2656
2657float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
2658{
2659 return float32_sqrt(a, &env->vfp.fp_status);
2660}
2661
2662float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
2663{
2664 return float64_sqrt(a, &env->vfp.fp_status);
2665}
2666
2667/* XXX: check quiet/signaling case */
2668#define DO_VFP_cmp(p, type) \
2669void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2670{ \
2671 uint32_t flags; \
2672 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2673 case 0: flags = 0x6; break; \
2674 case -1: flags = 0x8; break; \
2675 case 1: flags = 0x2; break; \
2676 default: case 2: flags = 0x3; break; \
2677 } \
2678 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2679 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2680} \
2681void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2682{ \
2683 uint32_t flags; \
2684 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2685 case 0: flags = 0x6; break; \
2686 case -1: flags = 0x8; break; \
2687 case 1: flags = 0x2; break; \
2688 default: case 2: flags = 0x3; break; \
2689 } \
2690 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2691 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2692}
2693DO_VFP_cmp(s, float32)
2694DO_VFP_cmp(d, float64)
2695#undef DO_VFP_cmp
2696
5500b06c 2697/* Integer to float and float to integer conversions */
4373f3ce 2698
5500b06c
PM		 2699#define CONV_ITOF(name, fsz, sign) \
2700 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2701{ \
2702 float_status *fpst = fpstp; \
2703 return sign##int32_to_##float##fsz(x, fpst); \
4373f3ce
PB		 2704}
2705
5500b06c
PM		 2706#define CONV_FTOI(name, fsz, sign, round) \
2707uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2708{ \
2709 float_status *fpst = fpstp; \
2710 if (float##fsz##_is_any_nan(x)) { \
2711 float_raise(float_flag_invalid, fpst); \
2712 return 0; \
2713 } \
2714 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 2715}
2716
5500b06c
PM		 2717#define FLOAT_CONVS(name, p, fsz, sign) \
2718CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2719CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2720CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 2721
5500b06c
PM		 2722FLOAT_CONVS(si, s, 32, )
2723FLOAT_CONVS(si, d, 64, )
2724FLOAT_CONVS(ui, s, 32, u)
2725FLOAT_CONVS(ui, d, 64, u)
4373f3ce 2726
5500b06c
PM		 2727#undef CONV_ITOF
2728#undef CONV_FTOI
2729#undef FLOAT_CONVS
4373f3ce
PB		 2730
2731/* floating point conversion */
2732float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
2733{
2d627737
PM		 2734 float64 r = float32_to_float64(x, &env->vfp.fp_status);
2735 /* ARM requires that S<->D conversion of any kind of NaN generates
2736 * a quiet NaN by forcing the most significant frac bit to 1.
2737 */
2738 return float64_maybe_silence_nan(r);
4373f3ce
PB		 2739}
2740
2741float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
2742{
2d627737
PM		 2743 float32 r = float64_to_float32(x, &env->vfp.fp_status);
2744 /* ARM requires that S<->D conversion of any kind of NaN generates
2745 * a quiet NaN by forcing the most significant frac bit to 1.
2746 */
2747 return float32_maybe_silence_nan(r);
4373f3ce
PB		 2748}
2749
2750/* VFP3 fixed point conversion. */
622465e1 2751#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 2752float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2753 void *fpstp) \
4373f3ce 2754{ \
5500b06c 2755 float_status *fpst = fpstp; \
622465e1 2756 float##fsz tmp; \
5500b06c
PM		 2757 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2758 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 2759} \
5500b06c
PM		 2760uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2761 void *fpstp) \
4373f3ce 2762{ \
5500b06c 2763 float_status *fpst = fpstp; \
622465e1
PM		 2764 float##fsz tmp; \
2765 if (float##fsz##_is_any_nan(x)) { \
5500b06c 2766 float_raise(float_flag_invalid, fpst); \
622465e1 2767 return 0; \
09d9487f 2768 } \
5500b06c
PM		 2769 tmp = float##fsz##_scalbn(x, shift, fpst); \
2770 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 2771}
2772
2773VFP_CONV_FIX(sh, d, 64, int16, )
2774VFP_CONV_FIX(sl, d, 64, int32, )
2775VFP_CONV_FIX(uh, d, 64, uint16, u)
2776VFP_CONV_FIX(ul, d, 64, uint32, u)
2777VFP_CONV_FIX(sh, s, 32, int16, )
2778VFP_CONV_FIX(sl, s, 32, int32, )
2779VFP_CONV_FIX(uh, s, 32, uint16, u)
2780VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 2781#undef VFP_CONV_FIX
2782
60011498 2783/* Half precision conversions. */
2d981da7 2784static float32 do_fcvt_f16_to_f32(uint32_t a, CPUState *env, float_status *s)
60011498 2785{
60011498 2786 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2787 float32 r = float16_to_float32(make_float16(a), ieee, s);
2788 if (ieee) {
2789 return float32_maybe_silence_nan(r);
2790 }
2791 return r;
60011498
PB		 2792}
2793
2d981da7 2794static uint32_t do_fcvt_f32_to_f16(float32 a, CPUState *env, float_status *s)
60011498 2795{
60011498 2796 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2797 float16 r = float32_to_float16(a, ieee, s);
2798 if (ieee) {
2799 r = float16_maybe_silence_nan(r);
2800 }
2801 return float16_val(r);
60011498
PB		 2802}
2803
2d981da7
PM		 2804float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2805{
2806 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
2807}
2808
2809uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUState *env)
2810{
2811 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
2812}
2813
2814float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2815{
2816 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
2817}
2818
2819uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
2820{
2821 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
2822}
2823
dda3ec49 2824#define float32_two make_float32(0x40000000)
6aae3df1
PM		 2825#define float32_three make_float32(0x40400000)
2826#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 2827
4373f3ce
PB		 2828float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
2829{
dda3ec49
PM		 2830 float_status *s = &env->vfp.standard_fp_status;
2831 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2832 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2833 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2834 float_raise(float_flag_input_denormal, s);
2835 }
dda3ec49
PM		 2836 return float32_two;
2837 }
2838 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 2839}
2840
2841float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
2842{
71826966 2843 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 2844 float32 product;
2845 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2846 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2847 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2848 float_raise(float_flag_input_denormal, s);
2849 }
6aae3df1 2850 return float32_one_point_five;
9ea62f57 2851 }
6aae3df1
PM		 2852 product = float32_mul(a, b, s);
2853 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 2854}
2855
8f8e3aa4
PB		 2856/* NEON helpers. */
2857
56bf4fe2
CL		 2858/* Constants 256 and 512 are used in some helpers; we avoid relying on
2859 * int->float conversions at run-time. */
2860#define float64_256 make_float64(0x4070000000000000LL)
2861#define float64_512 make_float64(0x4080000000000000LL)
2862
fe0e4872
CL		 2863/* The algorithm that must be used to calculate the estimate
2864 * is specified by the ARM ARM.
2865 */
2866static float64 recip_estimate(float64 a, CPUState *env)
2867{
1146a817
PM		 2868 /* These calculations mustn't set any fp exception flags,
2869 * so we use a local copy of the fp_status.
2870 */
2871 float_status dummy_status = env->vfp.standard_fp_status;
2872 float_status *s = &dummy_status;
fe0e4872
CL		 2873 /* q = (int)(a * 512.0) */
2874 float64 q = float64_mul(float64_512, a, s);
2875 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2876
2877 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2878 q = int64_to_float64(q_int, s);
2879 q = float64_add(q, float64_half, s);
2880 q = float64_div(q, float64_512, s);
2881 q = float64_div(float64_one, q, s);
2882
2883 /* s = (int)(256.0 * r + 0.5) */
2884 q = float64_mul(q, float64_256, s);
2885 q = float64_add(q, float64_half, s);
2886 q_int = float64_to_int64_round_to_zero(q, s);
2887
2888 /* return (double)s / 256.0 */
2889 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2890}
2891
4373f3ce
PB		 2892float32 HELPER(recpe_f32)(float32 a, CPUState *env)
2893{
fe0e4872
CL		 2894 float_status *s = &env->vfp.standard_fp_status;
2895 float64 f64;
2896 uint32_t val32 = float32_val(a);
2897
2898 int result_exp;
2899 int a_exp = (val32 & 0x7f800000) >> 23;
2900 int sign = val32 & 0x80000000;
2901
2902 if (float32_is_any_nan(a)) {
2903 if (float32_is_signaling_nan(a)) {
2904 float_raise(float_flag_invalid, s);
2905 }
2906 return float32_default_nan;
2907 } else if (float32_is_infinity(a)) {
2908 return float32_set_sign(float32_zero, float32_is_neg(a));
2909 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 2910 if (!float32_is_zero(a)) {
2911 float_raise(float_flag_input_denormal, s);
2912 }
fe0e4872
CL		 2913 float_raise(float_flag_divbyzero, s);
2914 return float32_set_sign(float32_infinity, float32_is_neg(a));
2915 } else if (a_exp >= 253) {
2916 float_raise(float_flag_underflow, s);
2917 return float32_set_sign(float32_zero, float32_is_neg(a));
2918 }
2919
2920 f64 = make_float64((0x3feULL << 52)
2921 | ((int64_t)(val32 & 0x7fffff) << 29));
2922
2923 result_exp = 253 - a_exp;
2924
2925 f64 = recip_estimate(f64, env);
2926
2927 val32 = sign
2928 | ((result_exp & 0xff) << 23)
2929 | ((float64_val(f64) >> 29) & 0x7fffff);
2930 return make_float32(val32);
4373f3ce
PB		 2931}
2932
e07be5d2
CL		 2933/* The algorithm that must be used to calculate the estimate
2934 * is specified by the ARM ARM.
2935 */
2936static float64 recip_sqrt_estimate(float64 a, CPUState *env)
2937{
1146a817
PM		 2938 /* These calculations mustn't set any fp exception flags,
2939 * so we use a local copy of the fp_status.
2940 */
2941 float_status dummy_status = env->vfp.standard_fp_status;
2942 float_status *s = &dummy_status;
e07be5d2
CL		 2943 float64 q;
2944 int64_t q_int;
2945
2946 if (float64_lt(a, float64_half, s)) {
2947 /* range 0.25 <= a < 0.5 */
2948
2949 /* a in units of 1/512 rounded down */
2950 /* q0 = (int)(a * 512.0); */
2951 q = float64_mul(float64_512, a, s);
2952 q_int = float64_to_int64_round_to_zero(q, s);
2953
2954 /* reciprocal root r */
2955 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2956 q = int64_to_float64(q_int, s);
2957 q = float64_add(q, float64_half, s);
2958 q = float64_div(q, float64_512, s);
2959 q = float64_sqrt(q, s);
2960 q = float64_div(float64_one, q, s);
2961 } else {
2962 /* range 0.5 <= a < 1.0 */
2963
2964 /* a in units of 1/256 rounded down */
2965 /* q1 = (int)(a * 256.0); */
2966 q = float64_mul(float64_256, a, s);
2967 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2968
2969 /* reciprocal root r */
2970 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
2971 q = int64_to_float64(q_int, s);
2972 q = float64_add(q, float64_half, s);
2973 q = float64_div(q, float64_256, s);
2974 q = float64_sqrt(q, s);
2975 q = float64_div(float64_one, q, s);
2976 }
2977 /* r in units of 1/256 rounded to nearest */
2978 /* s = (int)(256.0 * r + 0.5); */
2979
2980 q = float64_mul(q, float64_256,s );
2981 q = float64_add(q, float64_half, s);
2982 q_int = float64_to_int64_round_to_zero(q, s);
2983
2984 /* return (double)s / 256.0;*/
2985 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2986}
2987
4373f3ce
PB		 2988float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
2989{
e07be5d2
CL		 2990 float_status *s = &env->vfp.standard_fp_status;
2991 int result_exp;
2992 float64 f64;
2993 uint32_t val;
2994 uint64_t val64;
2995
2996 val = float32_val(a);
2997
2998 if (float32_is_any_nan(a)) {
2999 if (float32_is_signaling_nan(a)) {
3000 float_raise(float_flag_invalid, s);
3001 }
3002 return float32_default_nan;
3003 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3004 if (!float32_is_zero(a)) {
3005 float_raise(float_flag_input_denormal, s);
3006 }
e07be5d2
CL		 3007 float_raise(float_flag_divbyzero, s);
3008 return float32_set_sign(float32_infinity, float32_is_neg(a));
3009 } else if (float32_is_neg(a)) {
3010 float_raise(float_flag_invalid, s);
3011 return float32_default_nan;
3012 } else if (float32_is_infinity(a)) {
3013 return float32_zero;
3014 }
3015
3016 /* Normalize to a double-precision value between 0.25 and 1.0,
3017 * preserving the parity of the exponent. */
3018 if ((val & 0x800000) == 0) {
3019 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3020 | (0x3feULL << 52)
3021 | ((uint64_t)(val & 0x7fffff) << 29));
3022 } else {
3023 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3024 | (0x3fdULL << 52)
3025 | ((uint64_t)(val & 0x7fffff) << 29));
3026 }
3027
3028 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3029
3030 f64 = recip_sqrt_estimate(f64, env);
3031
3032 val64 = float64_val(f64);
3033
26cc6abf 3034 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 3035 | ((val64 >> 29) & 0x7fffff);
3036 return make_float32(val);
4373f3ce
PB		 3037}
3038
3039uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
3040{
fe0e4872
CL		 3041 float64 f64;
3042
3043 if ((a & 0x80000000) == 0) {
3044 return 0xffffffff;
3045 }
3046
3047 f64 = make_float64((0x3feULL << 52)
3048 | ((int64_t)(a & 0x7fffffff) << 21));
3049
3050 f64 = recip_estimate (f64, env);
3051
3052 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3053}
3054
3055uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
3056{
e07be5d2
CL		 3057 float64 f64;
3058
3059 if ((a & 0xc0000000) == 0) {
3060 return 0xffffffff;
3061 }
3062
3063 if (a & 0x80000000) {
3064 f64 = make_float64((0x3feULL << 52)
3065 | ((uint64_t)(a & 0x7fffffff) << 21));
3066 } else { /* bits 31-30 == '01' */
3067 f64 = make_float64((0x3fdULL << 52)
3068 | ((uint64_t)(a & 0x3fffffff) << 22));
3069 }
3070
3071 f64 = recip_sqrt_estimate(f64, env);
3072
3073 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 3074}
fe1479c3 3075
da97f52c
PM		 3076/* VFPv4 fused multiply-accumulate */
3077float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3078{
3079 float_status *fpst = fpstp;
3080 return float32_muladd(a, b, c, 0, fpst);
3081}
3082
3083float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3084{
3085 float_status *fpst = fpstp;
3086 return float64_muladd(a, b, c, 0, fpst);
3087}
3088
fe1479c3
PB		 3089void HELPER(set_teecr)(CPUState *env, uint32_t val)
3090{
3091 val &= 1;
3092 if (env->teecr != val) {
3093 env->teecr = val;
3094 tb_flush(env);
3095 }
3096}
Qemu copy for testing