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target-arm: Infer ARMv6 feature from v6K
[qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31
FB		 1#include <stdio.h>
2#include <stdlib.h>
3#include <string.h>
4
5#include "cpu.h"
9ee6e8bb 6#include "gdbstub.h"
7b59220e 7#include "helper.h"
ca10f867 8#include "qemu-common.h"
7bbcb0af 9#include "host-utils.h"
4f78c9ad 10#if !defined(CONFIG_USER_ONLY)
983fe826 11#include "hw/loader.h"
4f78c9ad 12#endif
9ee6e8bb 13
10055562
PB		 14static uint32_t cortexa9_cp15_c0_c1[8] =
15{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
16
17static uint32_t cortexa9_cp15_c0_c2[8] =
18{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
19
9ee6e8bb
PB		 20static uint32_t cortexa8_cp15_c0_c1[8] =
21{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
22
23static uint32_t cortexa8_cp15_c0_c2[8] =
24{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
25
26static uint32_t mpcore_cp15_c0_c1[8] =
27{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
28
29static uint32_t mpcore_cp15_c0_c2[8] =
30{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
31
32static uint32_t arm1136_cp15_c0_c1[8] =
33{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
34
35static uint32_t arm1136_cp15_c0_c2[8] =
36{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
b5ff1b31 37
7807eed9
JI		 38static uint32_t arm1176_cp15_c0_c1[8] =
39{ 0x111, 0x11, 0x33, 0, 0x01130003, 0x10030302, 0x01222100, 0 };
40
41static uint32_t arm1176_cp15_c0_c2[8] =
42{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
43
aaed909a
FB		 44static uint32_t cpu_arm_find_by_name(const char *name);
45
f3d6b95e
PB		 46static inline void set_feature(CPUARMState *env, int feature)
47{
48 env->features |= 1u << feature;
49}
50
51static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
52{
53 env->cp15.c0_cpuid = id;
54 switch (id) {
55 case ARM_CPUID_ARM926:
be5e7a76 56 set_feature(env, ARM_FEATURE_V5);
f3d6b95e
PB		 57 set_feature(env, ARM_FEATURE_VFP);
58 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
c1713132 59 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 60 env->cp15.c1_sys = 0x00090078;
f3d6b95e 61 break;
ce819861 62 case ARM_CPUID_ARM946:
be5e7a76 63 set_feature(env, ARM_FEATURE_V5);
ce819861
PB		 64 set_feature(env, ARM_FEATURE_MPU);
65 env->cp15.c0_cachetype = 0x0f004006;
610c3c8a 66 env->cp15.c1_sys = 0x00000078;
ce819861 67 break;
f3d6b95e 68 case ARM_CPUID_ARM1026:
be5e7a76 69 set_feature(env, ARM_FEATURE_V5);
f3d6b95e
PB		 70 set_feature(env, ARM_FEATURE_VFP);
71 set_feature(env, ARM_FEATURE_AUXCR);
72 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
c1713132 73 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 74 env->cp15.c1_sys = 0x00090078;
c1713132 75 break;
9ee6e8bb 76 case ARM_CPUID_ARM1136:
906879a9
PM		 77 /* This is the 1136 r1, which is a v6K core */
78 set_feature(env, ARM_FEATURE_V6K);
79 /* Fall through */
80 case ARM_CPUID_ARM1136_R2:
81 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
82 * older core than plain "arm1136". In particular this does not
83 * have the v6K features.
84 */
9ee6e8bb
PB		 85 set_feature(env, ARM_FEATURE_V6);
86 set_feature(env, ARM_FEATURE_VFP);
87 set_feature(env, ARM_FEATURE_AUXCR);
906879a9
PM		 88 /* These ID register values are correct for 1136 but may be wrong
89 * for 1136_r2 (in particular r0p2 does not actually implement most
90 * of the ID registers).
91 */
9ee6e8bb
PB		 92 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
93 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
94 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
95 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 96 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb 97 env->cp15.c0_cachetype = 0x1dd20d2;
16440c5f 98 env->cp15.c1_sys = 0x00050078;
9ee6e8bb 99 break;
7807eed9 100 case ARM_CPUID_ARM1176:
7807eed9
JI		 101 set_feature(env, ARM_FEATURE_V6K);
102 set_feature(env, ARM_FEATURE_VFP);
103 set_feature(env, ARM_FEATURE_AUXCR);
906879a9 104 set_feature(env, ARM_FEATURE_VAPA);
7807eed9
JI		 105 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
106 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
107 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
108 memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
109 memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
110 env->cp15.c0_cachetype = 0x1dd20d2;
111 env->cp15.c1_sys = 0x00050078;
112 break;
9ee6e8bb 113 case ARM_CPUID_ARM11MPCORE:
9ee6e8bb
PB		 114 set_feature(env, ARM_FEATURE_V6K);
115 set_feature(env, ARM_FEATURE_VFP);
116 set_feature(env, ARM_FEATURE_AUXCR);
906879a9 117 set_feature(env, ARM_FEATURE_VAPA);
9ee6e8bb
PB		 118 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
119 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
120 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
121 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 122 memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb
PB		 123 env->cp15.c0_cachetype = 0x1dd20d2;
124 break;
125 case ARM_CPUID_CORTEXA8:
9ee6e8bb
PB		 126 set_feature(env, ARM_FEATURE_V6K);
127 set_feature(env, ARM_FEATURE_V7);
128 set_feature(env, ARM_FEATURE_AUXCR);
129 set_feature(env, ARM_FEATURE_THUMB2);
130 set_feature(env, ARM_FEATURE_VFP);
131 set_feature(env, ARM_FEATURE_VFP3);
132 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 133 set_feature(env, ARM_FEATURE_THUMB2EE);
9ee6e8bb
PB		 134 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
135 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
136 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
137 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 138 memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
a49ea279
PB		 139 env->cp15.c0_cachetype = 0x82048004;
140 env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
141 env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
142 env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
143 env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
9c486ad6 144 env->cp15.c1_sys = 0x00c50078;
9ee6e8bb 145 break;
10055562 146 case ARM_CPUID_CORTEXA9:
10055562
PB		 147 set_feature(env, ARM_FEATURE_V6K);
148 set_feature(env, ARM_FEATURE_V7);
149 set_feature(env, ARM_FEATURE_AUXCR);
150 set_feature(env, ARM_FEATURE_THUMB2);
151 set_feature(env, ARM_FEATURE_VFP);
152 set_feature(env, ARM_FEATURE_VFP3);
153 set_feature(env, ARM_FEATURE_VFP_FP16);
154 set_feature(env, ARM_FEATURE_NEON);
155 set_feature(env, ARM_FEATURE_THUMB2EE);
e1bbf446
PM		 156 /* Note that A9 supports the MP extensions even for
157 * A9UP and single-core A9MP (which are both different
158 * and valid configurations; we don't model A9UP).
159 */
160 set_feature(env, ARM_FEATURE_V7MP);
10055562
PB		 161 env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
162 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
163 env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
164 memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
165 memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
166 env->cp15.c0_cachetype = 0x80038003;
167 env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
168 env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
169 env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
16440c5f 170 env->cp15.c1_sys = 0x00c50078;
10055562 171 break;
9ee6e8bb
PB		 172 case ARM_CPUID_CORTEXM3:
173 set_feature(env, ARM_FEATURE_V6);
174 set_feature(env, ARM_FEATURE_THUMB2);
175 set_feature(env, ARM_FEATURE_V7);
176 set_feature(env, ARM_FEATURE_M);
47789990 177 set_feature(env, ARM_FEATURE_THUMB_DIV);
9ee6e8bb
PB		 178 break;
179 case ARM_CPUID_ANY: /* For userspace emulation. */
9ee6e8bb
PB		 180 set_feature(env, ARM_FEATURE_V6K);
181 set_feature(env, ARM_FEATURE_V7);
182 set_feature(env, ARM_FEATURE_THUMB2);
183 set_feature(env, ARM_FEATURE_VFP);
184 set_feature(env, ARM_FEATURE_VFP3);
da97f52c 185 set_feature(env, ARM_FEATURE_VFP4);
60011498 186 set_feature(env, ARM_FEATURE_VFP_FP16);
9ee6e8bb 187 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 188 set_feature(env, ARM_FEATURE_THUMB2EE);
b8b8ea05 189 set_feature(env, ARM_FEATURE_ARM_DIV);
e1bbf446 190 set_feature(env, ARM_FEATURE_V7MP);
9ee6e8bb 191 break;
c3d2689d
AZ		 192 case ARM_CPUID_TI915T:
193 case ARM_CPUID_TI925T:
be5e7a76 194 set_feature(env, ARM_FEATURE_V4T);
c3d2689d
AZ		 195 set_feature(env, ARM_FEATURE_OMAPCP);
196 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
197 env->cp15.c0_cachetype = 0x5109149;
198 env->cp15.c1_sys = 0x00000070;
199 env->cp15.c15_i_max = 0x000;
200 env->cp15.c15_i_min = 0xff0;
201 break;
c1713132
AZ		 202 case ARM_CPUID_PXA250:
203 case ARM_CPUID_PXA255:
204 case ARM_CPUID_PXA260:
205 case ARM_CPUID_PXA261:
206 case ARM_CPUID_PXA262:
be5e7a76 207 set_feature(env, ARM_FEATURE_V5);
c1713132
AZ		 208 set_feature(env, ARM_FEATURE_XSCALE);
209 /* JTAG_ID is ((id << 28) | 0x09265013) */
210 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 211 env->cp15.c1_sys = 0x00000078;
c1713132
AZ		 212 break;
213 case ARM_CPUID_PXA270_A0:
214 case ARM_CPUID_PXA270_A1:
215 case ARM_CPUID_PXA270_B0:
216 case ARM_CPUID_PXA270_B1:
217 case ARM_CPUID_PXA270_C0:
218 case ARM_CPUID_PXA270_C5:
be5e7a76 219 set_feature(env, ARM_FEATURE_V5);
c1713132
AZ		 220 set_feature(env, ARM_FEATURE_XSCALE);
221 /* JTAG_ID is ((id << 28) | 0x09265013) */
18c9b560
AZ		 222 set_feature(env, ARM_FEATURE_IWMMXT);
223 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
c1713132 224 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 225 env->cp15.c1_sys = 0x00000078;
f3d6b95e 226 break;
5bc95aa2
DES		 227 case ARM_CPUID_SA1100:
228 case ARM_CPUID_SA1110:
229 set_feature(env, ARM_FEATURE_STRONGARM);
230 env->cp15.c1_sys = 0x00000070;
231 break;
f3d6b95e
PB		 232 default:
233 cpu_abort(env, "Bad CPU ID: %x\n", id);
234 break;
235 }
906879a9
PM		 236
237 /* Some features automatically imply others: */
238 if (arm_feature(env, ARM_FEATURE_V7)) {
239 set_feature(env, ARM_FEATURE_VAPA);
240 }
6bf62124
AF		 241 if (arm_feature(env, ARM_FEATURE_V6K)) {
242 set_feature(env, ARM_FEATURE_V6);
243 }
08c40f3c
AF		 244 if (arm_feature(env, ARM_FEATURE_V6)) {
245 set_feature(env, ARM_FEATURE_V5);
246 }
ddb572ec
AF		 247 if (arm_feature(env, ARM_FEATURE_V5)) {
248 set_feature(env, ARM_FEATURE_V4T);
249 }
b8b8ea05
PM		 250 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
251 set_feature(env, ARM_FEATURE_THUMB_DIV);
252 }
f3d6b95e
PB		 253}
254
40f137e1
PB		 255void cpu_reset(CPUARMState *env)
256{
f3d6b95e 257 uint32_t id;
eca1bdf4
AL		 258
259 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
260 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
261 log_cpu_state(env, 0);
262 }
263
f3d6b95e
PB		 264 id = env->cp15.c0_cpuid;
265 memset(env, 0, offsetof(CPUARMState, breakpoints));
266 if (id)
267 cpu_reset_model_id(env, id);
40f137e1
PB		 268#if defined (CONFIG_USER_ONLY)
269 env->uncached_cpsr = ARM_CPU_MODE_USR;
3a807dec 270 /* For user mode we must enable access to coprocessors */
40f137e1 271 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
3a807dec
PM		 272 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
273 env->cp15.c15_cpar = 3;
274 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
275 env->cp15.c15_cpar = 1;
276 }
40f137e1
PB		 277#else
278 /* SVC mode with interrupts disabled. */
279 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
9ee6e8bb 280 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
983fe826
PB		 281 clear at reset. Initial SP and PC are loaded from ROM. */
282 if (IS_M(env)) {
283 uint32_t pc;
284 uint8_t *rom;
9ee6e8bb 285 env->uncached_cpsr &= ~CPSR_I;
983fe826
PB		 286 rom = rom_ptr(0);
287 if (rom) {
288 /* We should really use ldl_phys here, in case the guest
289 modified flash and reset itself. However images
297d1b4e 290 loaded via -kernel have not been copied yet, so load the
983fe826
PB		 291 values directly from there. */
292 env->regs[13] = ldl_p(rom);
293 pc = ldl_p(rom + 4);
294 env->thumb = pc & 1;
295 env->regs[15] = pc & ~1;
296 }
297 }
40f137e1 298 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
b2fa1797 299 env->cp15.c2_base_mask = 0xffffc000u;
74594c9d
PM		 300 /* v7 performance monitor control register: same implementor
301 * field as main ID register, and we implement no event counters.
302 */
303 env->cp15.c9_pmcr = (id & 0xff000000);
40f137e1 304#endif
3a492f3a
PM		 305 set_flush_to_zero(1, &env->vfp.standard_fp_status);
306 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
307 set_default_nan_mode(1, &env->vfp.standard_fp_status);
9df38c47
PM		 308 set_float_detect_tininess(float_tininess_before_rounding,
309 &env->vfp.fp_status);
310 set_float_detect_tininess(float_tininess_before_rounding,
311 &env->vfp.standard_fp_status);
f3d6b95e 312 tlb_flush(env, 1);
40f137e1
PB		 313}
314
56aebc89
PB		 315static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
316{
317 int nregs;
318
319 /* VFP data registers are always little-endian. */
320 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
321 if (reg < nregs) {
322 stfq_le_p(buf, env->vfp.regs[reg]);
323 return 8;
324 }
325 if (arm_feature(env, ARM_FEATURE_NEON)) {
326 /* Aliases for Q regs. */
327 nregs += 16;
328 if (reg < nregs) {
329 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
330 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
331 return 16;
332 }
333 }
334 switch (reg - nregs) {
335 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
336 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
337 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
338 }
339 return 0;
340}
341
342static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
343{
344 int nregs;
345
346 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
347 if (reg < nregs) {
348 env->vfp.regs[reg] = ldfq_le_p(buf);
349 return 8;
350 }
351 if (arm_feature(env, ARM_FEATURE_NEON)) {
352 nregs += 16;
353 if (reg < nregs) {
354 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
355 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
356 return 16;
357 }
358 }
359 switch (reg - nregs) {
360 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
361 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 362 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 363 }
364 return 0;
365}
366
aaed909a 367CPUARMState *cpu_arm_init(const char *cpu_model)
40f137e1
PB		 368{
369 CPUARMState *env;
aaed909a 370 uint32_t id;
b26eefb6 371 static int inited = 0;
40f137e1 372
aaed909a
FB		 373 id = cpu_arm_find_by_name(cpu_model);
374 if (id == 0)
375 return NULL;
7267c094 376 env = g_malloc0(sizeof(CPUARMState));
40f137e1 377 cpu_exec_init(env);
f4fc247b 378 if (tcg_enabled() && !inited) {
b26eefb6
PB		 379 inited = 1;
380 arm_translate_init();
381 }
382
01ba9816 383 env->cpu_model_str = cpu_model;
aaed909a 384 env->cp15.c0_cpuid = id;
40f137e1 385 cpu_reset(env);
56aebc89
PB		 386 if (arm_feature(env, ARM_FEATURE_NEON)) {
387 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
388 51, "arm-neon.xml", 0);
389 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
390 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
391 35, "arm-vfp3.xml", 0);
392 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
393 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
394 19, "arm-vfp.xml", 0);
395 }
0bf46a40 396 qemu_init_vcpu(env);
40f137e1
PB		 397 return env;
398}
399
3371d272
PB		 400struct arm_cpu_t {
401 uint32_t id;
402 const char *name;
403};
404
405static const struct arm_cpu_t arm_cpu_names[] = {
406 { ARM_CPUID_ARM926, "arm926"},
ce819861 407 { ARM_CPUID_ARM946, "arm946"},
3371d272 408 { ARM_CPUID_ARM1026, "arm1026"},
9ee6e8bb 409 { ARM_CPUID_ARM1136, "arm1136"},
827df9f3 410 { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
7807eed9 411 { ARM_CPUID_ARM1176, "arm1176"},
9ee6e8bb
PB		 412 { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
413 { ARM_CPUID_CORTEXM3, "cortex-m3"},
414 { ARM_CPUID_CORTEXA8, "cortex-a8"},
10055562 415 { ARM_CPUID_CORTEXA9, "cortex-a9"},
c3d2689d 416 { ARM_CPUID_TI925T, "ti925t" },
c1713132 417 { ARM_CPUID_PXA250, "pxa250" },
5bc95aa2
DES		 418 { ARM_CPUID_SA1100, "sa1100" },
419 { ARM_CPUID_SA1110, "sa1110" },
c1713132
AZ		 420 { ARM_CPUID_PXA255, "pxa255" },
421 { ARM_CPUID_PXA260, "pxa260" },
422 { ARM_CPUID_PXA261, "pxa261" },
423 { ARM_CPUID_PXA262, "pxa262" },
424 { ARM_CPUID_PXA270, "pxa270" },
425 { ARM_CPUID_PXA270_A0, "pxa270-a0" },
426 { ARM_CPUID_PXA270_A1, "pxa270-a1" },
427 { ARM_CPUID_PXA270_B0, "pxa270-b0" },
428 { ARM_CPUID_PXA270_B1, "pxa270-b1" },
429 { ARM_CPUID_PXA270_C0, "pxa270-c0" },
430 { ARM_CPUID_PXA270_C5, "pxa270-c5" },
9ee6e8bb 431 { ARM_CPUID_ANY, "any"},
3371d272
PB		 432 { 0, NULL}
433};
434
9a78eead 435void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
5adb4839
PB		 436{
437 int i;
438
c732abe2 439 (*cpu_fprintf)(f, "Available CPUs:\n");
5adb4839 440 for (i = 0; arm_cpu_names[i].name; i++) {
c732abe2 441 (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
5adb4839
PB		 442 }
443}
444
aaed909a
FB		 445/* return 0 if not found */
446static uint32_t cpu_arm_find_by_name(const char *name)
40f137e1 447{
3371d272
PB		 448 int i;
449 uint32_t id;
450
451 id = 0;
3371d272
PB		 452 for (i = 0; arm_cpu_names[i].name; i++) {
453 if (strcmp(name, arm_cpu_names[i].name) == 0) {
454 id = arm_cpu_names[i].id;
455 break;
456 }
457 }
aaed909a 458 return id;
40f137e1
PB		 459}
460
461void cpu_arm_close(CPUARMState *env)
462{
12b1de3a 463 g_free(env);
40f137e1
PB		 464}
465
2f4a40e5
AZ		 466uint32_t cpsr_read(CPUARMState *env)
467{
468 int ZF;
6fbe23d5
PB		 469 ZF = (env->ZF == 0);
470 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 471 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
472 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
473 | ((env->condexec_bits & 0xfc) << 8)
474 | (env->GE << 16);
475}
476
477void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
478{
2f4a40e5 479 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 480 env->ZF = (~val) & CPSR_Z;
481 env->NF = val;
2f4a40e5
AZ		 482 env->CF = (val >> 29) & 1;
483 env->VF = (val << 3) & 0x80000000;
484 }
485 if (mask & CPSR_Q)
486 env->QF = ((val & CPSR_Q) != 0);
487 if (mask & CPSR_T)
488 env->thumb = ((val & CPSR_T) != 0);
489 if (mask & CPSR_IT_0_1) {
490 env->condexec_bits &= ~3;
491 env->condexec_bits |= (val >> 25) & 3;
492 }
493 if (mask & CPSR_IT_2_7) {
494 env->condexec_bits &= 3;
495 env->condexec_bits |= (val >> 8) & 0xfc;
496 }
497 if (mask & CPSR_GE) {
498 env->GE = (val >> 16) & 0xf;
499 }
500
501 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
502 switch_mode(env, val & CPSR_M);
503 }
504 mask &= ~CACHED_CPSR_BITS;
505 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
506}
507
b26eefb6
PB		 508/* Sign/zero extend */
509uint32_t HELPER(sxtb16)(uint32_t x)
510{
511 uint32_t res;
512 res = (uint16_t)(int8_t)x;
513 res |= (uint32_t)(int8_t)(x >> 16) << 16;
514 return res;
515}
516
517uint32_t HELPER(uxtb16)(uint32_t x)
518{
519 uint32_t res;
520 res = (uint16_t)(uint8_t)x;
521 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
522 return res;
523}
524
f51bbbfe
PB		 525uint32_t HELPER(clz)(uint32_t x)
526{
7bbcb0af 527 return clz32(x);
f51bbbfe
PB		 528}
529
3670669c
PB		 530int32_t HELPER(sdiv)(int32_t num, int32_t den)
531{
532 if (den == 0)
533 return 0;
686eeb93
AJ		 534 if (num == INT_MIN && den == -1)
535 return INT_MIN;
3670669c
PB		 536 return num / den;
537}
538
539uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
540{
541 if (den == 0)
542 return 0;
543 return num / den;
544}
545
546uint32_t HELPER(rbit)(uint32_t x)
547{
548 x = ((x & 0xff000000) >> 24)
549 | ((x & 0x00ff0000) >> 8)
550 | ((x & 0x0000ff00) << 8)
551 | ((x & 0x000000ff) << 24);
552 x = ((x & 0xf0f0f0f0) >> 4)
553 | ((x & 0x0f0f0f0f) << 4);
554 x = ((x & 0x88888888) >> 3)
555 | ((x & 0x44444444) >> 1)
556 | ((x & 0x22222222) << 1)
557 | ((x & 0x11111111) << 3);
558 return x;
559}
560
ad69471c
PB		 561uint32_t HELPER(abs)(uint32_t x)
562{
563 return ((int32_t)x < 0) ? -x : x;
564}
565
5fafdf24 566#if defined(CONFIG_USER_ONLY)
b5ff1b31
FB		 567
568void do_interrupt (CPUState *env)
569{
570 env->exception_index = -1;
571}
572
573int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
97b348e7 574 int mmu_idx)
b5ff1b31
FB		 575{
576 if (rw == 2) {
577 env->exception_index = EXCP_PREFETCH_ABORT;
578 env->cp15.c6_insn = address;
579 } else {
580 env->exception_index = EXCP_DATA_ABORT;
581 env->cp15.c6_data = address;
582 }
583 return 1;
584}
585
b5ff1b31 586/* These should probably raise undefined insn exceptions. */
8984bd2e 587void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 588{
589 int op1 = (insn >> 8) & 0xf;
590 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
591 return;
592}
593
8984bd2e 594uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 595{
596 int op1 = (insn >> 8) & 0xf;
597 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
598 return 0;
599}
600
8984bd2e 601void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31
FB		 602{
603 cpu_abort(env, "cp15 insn %08x\n", insn);
604}
605
8984bd2e 606uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31
FB		 607{
608 cpu_abort(env, "cp15 insn %08x\n", insn);
b5ff1b31
FB		 609}
610
9ee6e8bb 611/* These should probably raise undefined insn exceptions. */
8984bd2e 612void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 613{
614 cpu_abort(env, "v7m_mrs %d\n", reg);
615}
616
8984bd2e 617uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 618{
619 cpu_abort(env, "v7m_mrs %d\n", reg);
620 return 0;
621}
622
b5ff1b31
FB		 623void switch_mode(CPUState *env, int mode)
624{
625 if (mode != ARM_CPU_MODE_USR)
626 cpu_abort(env, "Tried to switch out of user mode\n");
627}
628
b0109805 629void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 630{
631 cpu_abort(env, "banked r13 write\n");
632}
633
b0109805 634uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb
PB		 635{
636 cpu_abort(env, "banked r13 read\n");
637 return 0;
638}
639
b5ff1b31
FB		 640#else
641
8e71621f
PB		 642extern int semihosting_enabled;
643
b5ff1b31
FB		 644/* Map CPU modes onto saved register banks. */
645static inline int bank_number (int mode)
646{
647 switch (mode) {
648 case ARM_CPU_MODE_USR:
649 case ARM_CPU_MODE_SYS:
650 return 0;
651 case ARM_CPU_MODE_SVC:
652 return 1;
653 case ARM_CPU_MODE_ABT:
654 return 2;
655 case ARM_CPU_MODE_UND:
656 return 3;
657 case ARM_CPU_MODE_IRQ:
658 return 4;
659 case ARM_CPU_MODE_FIQ:
660 return 5;
661 }
662 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
663 return -1;
664}
665
666void switch_mode(CPUState *env, int mode)
667{
668 int old_mode;
669 int i;
670
671 old_mode = env->uncached_cpsr & CPSR_M;
672 if (mode == old_mode)
673 return;
674
675 if (old_mode == ARM_CPU_MODE_FIQ) {
676 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 677 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 678 } else if (mode == ARM_CPU_MODE_FIQ) {
679 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 680 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 681 }
682
683 i = bank_number(old_mode);
684 env->banked_r13[i] = env->regs[13];
685 env->banked_r14[i] = env->regs[14];
686 env->banked_spsr[i] = env->spsr;
687
688 i = bank_number(mode);
689 env->regs[13] = env->banked_r13[i];
690 env->regs[14] = env->banked_r14[i];
691 env->spsr = env->banked_spsr[i];
692}
693
9ee6e8bb
PB		 694static void v7m_push(CPUARMState *env, uint32_t val)
695{
696 env->regs[13] -= 4;
697 stl_phys(env->regs[13], val);
698}
699
700static uint32_t v7m_pop(CPUARMState *env)
701{
702 uint32_t val;
703 val = ldl_phys(env->regs[13]);
704 env->regs[13] += 4;
705 return val;
706}
707
708/* Switch to V7M main or process stack pointer. */
709static void switch_v7m_sp(CPUARMState *env, int process)
710{
711 uint32_t tmp;
712 if (env->v7m.current_sp != process) {
713 tmp = env->v7m.other_sp;
714 env->v7m.other_sp = env->regs[13];
715 env->regs[13] = tmp;
716 env->v7m.current_sp = process;
717 }
718}
719
720static void do_v7m_exception_exit(CPUARMState *env)
721{
722 uint32_t type;
723 uint32_t xpsr;
724
725 type = env->regs[15];
726 if (env->v7m.exception != 0)
983fe826 727 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 728
729 /* Switch to the target stack. */
730 switch_v7m_sp(env, (type & 4) != 0);
731 /* Pop registers. */
732 env->regs[0] = v7m_pop(env);
733 env->regs[1] = v7m_pop(env);
734 env->regs[2] = v7m_pop(env);
735 env->regs[3] = v7m_pop(env);
736 env->regs[12] = v7m_pop(env);
737 env->regs[14] = v7m_pop(env);
738 env->regs[15] = v7m_pop(env);
739 xpsr = v7m_pop(env);
740 xpsr_write(env, xpsr, 0xfffffdff);
741 /* Undo stack alignment. */
742 if (xpsr & 0x200)
743 env->regs[13] |= 4;
744 /* ??? The exception return type specifies Thread/Handler mode. However
745 this is also implied by the xPSR value. Not sure what to do
746 if there is a mismatch. */
747 /* ??? Likewise for mismatches between the CONTROL register and the stack
748 pointer. */
749}
750
2b3ea315 751static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 752{
753 uint32_t xpsr = xpsr_read(env);
754 uint32_t lr;
755 uint32_t addr;
756
757 lr = 0xfffffff1;
758 if (env->v7m.current_sp)
759 lr |= 4;
760 if (env->v7m.exception == 0)
761 lr |= 8;
762
763 /* For exceptions we just mark as pending on the NVIC, and let that
764 handle it. */
765 /* TODO: Need to escalate if the current priority is higher than the
766 one we're raising. */
767 switch (env->exception_index) {
768 case EXCP_UDEF:
983fe826 769 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 770 return;
771 case EXCP_SWI:
772 env->regs[15] += 2;
983fe826 773 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 774 return;
775 case EXCP_PREFETCH_ABORT:
776 case EXCP_DATA_ABORT:
983fe826 777 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 778 return;
779 case EXCP_BKPT:
2ad207d4
PB		 780 if (semihosting_enabled) {
781 int nr;
782 nr = lduw_code(env->regs[15]) & 0xff;
783 if (nr == 0xab) {
784 env->regs[15] += 2;
785 env->regs[0] = do_arm_semihosting(env);
786 return;
787 }
788 }
983fe826 789 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 790 return;
791 case EXCP_IRQ:
983fe826 792 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 793 break;
794 case EXCP_EXCEPTION_EXIT:
795 do_v7m_exception_exit(env);
796 return;
797 default:
798 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
799 return; /* Never happens. Keep compiler happy. */
800 }
801
802 /* Align stack pointer. */
803 /* ??? Should only do this if Configuration Control Register
804 STACKALIGN bit is set. */
805 if (env->regs[13] & 4) {
ab19b0ec 806 env->regs[13] -= 4;
9ee6e8bb
PB		 807 xpsr |= 0x200;
808 }
6c95676b 809 /* Switch to the handler mode. */
9ee6e8bb
PB		 810 v7m_push(env, xpsr);
811 v7m_push(env, env->regs[15]);
812 v7m_push(env, env->regs[14]);
813 v7m_push(env, env->regs[12]);
814 v7m_push(env, env->regs[3]);
815 v7m_push(env, env->regs[2]);
816 v7m_push(env, env->regs[1]);
817 v7m_push(env, env->regs[0]);
818 switch_v7m_sp(env, 0);
819 env->uncached_cpsr &= ~CPSR_IT;
820 env->regs[14] = lr;
821 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
822 env->regs[15] = addr & 0xfffffffe;
823 env->thumb = addr & 1;
824}
825
b5ff1b31
FB		 826/* Handle a CPU exception. */
827void do_interrupt(CPUARMState *env)
828{
829 uint32_t addr;
830 uint32_t mask;
831 int new_mode;
832 uint32_t offset;
833
9ee6e8bb
PB		 834 if (IS_M(env)) {
835 do_interrupt_v7m(env);
836 return;
837 }
b5ff1b31
FB		 838 /* TODO: Vectored interrupt controller. */
839 switch (env->exception_index) {
840 case EXCP_UDEF:
841 new_mode = ARM_CPU_MODE_UND;
842 addr = 0x04;
843 mask = CPSR_I;
844 if (env->thumb)
845 offset = 2;
846 else
847 offset = 4;
848 break;
849 case EXCP_SWI:
8e71621f
PB		 850 if (semihosting_enabled) {
851 /* Check for semihosting interrupt. */
852 if (env->thumb) {
853 mask = lduw_code(env->regs[15] - 2) & 0xff;
854 } else {
855 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
856 }
857 /* Only intercept calls from privileged modes, to provide some
858 semblance of security. */
859 if (((mask == 0x123456 && !env->thumb)
860 || (mask == 0xab && env->thumb))
861 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
862 env->regs[0] = do_arm_semihosting(env);
863 return;
864 }
865 }
b5ff1b31
FB		 866 new_mode = ARM_CPU_MODE_SVC;
867 addr = 0x08;
868 mask = CPSR_I;
601d70b9 869 /* The PC already points to the next instruction. */
b5ff1b31
FB		 870 offset = 0;
871 break;
06c949e6 872 case EXCP_BKPT:
9ee6e8bb 873 /* See if this is a semihosting syscall. */
2ad207d4 874 if (env->thumb && semihosting_enabled) {
9ee6e8bb
PB		 875 mask = lduw_code(env->regs[15]) & 0xff;
876 if (mask == 0xab
877 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
878 env->regs[15] += 2;
879 env->regs[0] = do_arm_semihosting(env);
880 return;
881 }
882 }
81c05daf 883 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 884 /* Fall through to prefetch abort. */
885 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 886 new_mode = ARM_CPU_MODE_ABT;
887 addr = 0x0c;
888 mask = CPSR_A | CPSR_I;
889 offset = 4;
890 break;
891 case EXCP_DATA_ABORT:
892 new_mode = ARM_CPU_MODE_ABT;
893 addr = 0x10;
894 mask = CPSR_A | CPSR_I;
895 offset = 8;
896 break;
897 case EXCP_IRQ:
898 new_mode = ARM_CPU_MODE_IRQ;
899 addr = 0x18;
900 /* Disable IRQ and imprecise data aborts. */
901 mask = CPSR_A | CPSR_I;
902 offset = 4;
903 break;
904 case EXCP_FIQ:
905 new_mode = ARM_CPU_MODE_FIQ;
906 addr = 0x1c;
907 /* Disable FIQ, IRQ and imprecise data aborts. */
908 mask = CPSR_A | CPSR_I | CPSR_F;
909 offset = 4;
910 break;
911 default:
912 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
913 return; /* Never happens. Keep compiler happy. */
914 }
915 /* High vectors. */
916 if (env->cp15.c1_sys & (1 << 13)) {
917 addr += 0xffff0000;
918 }
919 switch_mode (env, new_mode);
920 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 921 /* Clear IT bits. */
922 env->condexec_bits = 0;
30a8cac1 923 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 924 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 925 env->uncached_cpsr |= mask;
be5e7a76
DES		 926 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
927 * and we should just guard the thumb mode on V4 */
928 if (arm_feature(env, ARM_FEATURE_V4T)) {
929 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
930 }
b5ff1b31
FB		 931 env->regs[14] = env->regs[15] + offset;
932 env->regs[15] = addr;
933 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
934}
935
936/* Check section/page access permissions.
937 Returns the page protection flags, or zero if the access is not
938 permitted. */
dd4ebc2e
JCD		 939static inline int check_ap(CPUState *env, int ap, int domain_prot,
940 int access_type, int is_user)
b5ff1b31 941{
9ee6e8bb
PB		 942 int prot_ro;
943
dd4ebc2e 944 if (domain_prot == 3) {
b5ff1b31 945 return PAGE_READ | PAGE_WRITE;
dd4ebc2e 946 }
b5ff1b31 947
9ee6e8bb
PB		 948 if (access_type == 1)
949 prot_ro = 0;
950 else
951 prot_ro = PAGE_READ;
952
b5ff1b31
FB		 953 switch (ap) {
954 case 0:
78600320 955 if (access_type == 1)
b5ff1b31
FB		 956 return 0;
957 switch ((env->cp15.c1_sys >> 8) & 3) {
958 case 1:
959 return is_user ? 0 : PAGE_READ;
960 case 2:
961 return PAGE_READ;
962 default:
963 return 0;
964 }
965 case 1:
966 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
967 case 2:
968 if (is_user)
9ee6e8bb 969 return prot_ro;
b5ff1b31
FB		 970 else
971 return PAGE_READ | PAGE_WRITE;
972 case 3:
973 return PAGE_READ | PAGE_WRITE;
d4934d18 974 case 4: /* Reserved. */
9ee6e8bb
PB		 975 return 0;
976 case 5:
977 return is_user ? 0 : prot_ro;
978 case 6:
979 return prot_ro;
d4934d18 980 case 7:
0ab06d83 981 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 982 return 0;
983 return prot_ro;
b5ff1b31
FB		 984 default:
985 abort();
986 }
987}
988
b2fa1797
PB		 989static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
990{
991 uint32_t table;
992
993 if (address & env->cp15.c2_mask)
994 table = env->cp15.c2_base1 & 0xffffc000;
995 else
996 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
997
998 table |= (address >> 18) & 0x3ffc;
999 return table;
1000}
1001
9ee6e8bb 1002static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
d4c430a8
PB		 1003 int is_user, uint32_t *phys_ptr, int *prot,
1004 target_ulong *page_size)
b5ff1b31
FB		 1005{
1006 int code;
1007 uint32_t table;
1008 uint32_t desc;
1009 int type;
1010 int ap;
1011 int domain;
dd4ebc2e 1012 int domain_prot;
b5ff1b31
FB		 1013 uint32_t phys_addr;
1014
9ee6e8bb
PB		 1015 /* Pagetable walk. */
1016 /* Lookup l1 descriptor. */
b2fa1797 1017 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1018 desc = ldl_phys(table);
1019 type = (desc & 3);
dd4ebc2e
JCD		 1020 domain = (desc >> 5) & 0x0f;
1021 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
9ee6e8bb 1022 if (type == 0) {
601d70b9 1023 /* Section translation fault. */
9ee6e8bb
PB		 1024 code = 5;
1025 goto do_fault;
1026 }
dd4ebc2e 1027 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1028 if (type == 2)
1029 code = 9; /* Section domain fault. */
1030 else
1031 code = 11; /* Page domain fault. */
1032 goto do_fault;
1033 }
1034 if (type == 2) {
1035 /* 1Mb section. */
1036 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1037 ap = (desc >> 10) & 3;
1038 code = 13;
d4c430a8 1039 *page_size = 1024 * 1024;
9ee6e8bb
PB		 1040 } else {
1041 /* Lookup l2 entry. */
1042 if (type == 1) {
1043 /* Coarse pagetable. */
1044 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1045 } else {
1046 /* Fine pagetable. */
1047 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
1048 }
1049 desc = ldl_phys(table);
1050 switch (desc & 3) {
1051 case 0: /* Page translation fault. */
1052 code = 7;
1053 goto do_fault;
1054 case 1: /* 64k page. */
1055 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1056 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1057 *page_size = 0x10000;
ce819861 1058 break;
9ee6e8bb
PB		 1059 case 2: /* 4k page. */
1060 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1061 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1062 *page_size = 0x1000;
ce819861 1063 break;
9ee6e8bb
PB		 1064 case 3: /* 1k page. */
1065 if (type == 1) {
1066 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1067 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1068 } else {
1069 /* Page translation fault. */
1070 code = 7;
1071 goto do_fault;
1072 }
1073 } else {
1074 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1075 }
1076 ap = (desc >> 4) & 3;
d4c430a8 1077 *page_size = 0x400;
ce819861
PB		 1078 break;
1079 default:
9ee6e8bb
PB		 1080 /* Never happens, but compiler isn't smart enough to tell. */
1081 abort();
ce819861 1082 }
9ee6e8bb
PB		 1083 code = 15;
1084 }
dd4ebc2e 1085 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
9ee6e8bb
PB		 1086 if (!*prot) {
1087 /* Access permission fault. */
1088 goto do_fault;
1089 }
3ad493fc 1090 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1091 *phys_ptr = phys_addr;
1092 return 0;
1093do_fault:
1094 return code | (domain << 4);
1095}
1096
1097static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
d4c430a8
PB		 1098 int is_user, uint32_t *phys_ptr, int *prot,
1099 target_ulong *page_size)
9ee6e8bb
PB		 1100{
1101 int code;
1102 uint32_t table;
1103 uint32_t desc;
1104 uint32_t xn;
1105 int type;
1106 int ap;
1107 int domain;
dd4ebc2e 1108 int domain_prot;
9ee6e8bb
PB		 1109 uint32_t phys_addr;
1110
1111 /* Pagetable walk. */
1112 /* Lookup l1 descriptor. */
b2fa1797 1113 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1114 desc = ldl_phys(table);
1115 type = (desc & 3);
1116 if (type == 0) {
601d70b9 1117 /* Section translation fault. */
9ee6e8bb
PB		 1118 code = 5;
1119 domain = 0;
1120 goto do_fault;
1121 } else if (type == 2 && (desc & (1 << 18))) {
1122 /* Supersection. */
1123 domain = 0;
b5ff1b31 1124 } else {
9ee6e8bb 1125 /* Section or page. */
dd4ebc2e 1126 domain = (desc >> 5) & 0x0f;
9ee6e8bb 1127 }
dd4ebc2e
JCD		 1128 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
1129 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1130 if (type == 2)
1131 code = 9; /* Section domain fault. */
1132 else
1133 code = 11; /* Page domain fault. */
1134 goto do_fault;
1135 }
1136 if (type == 2) {
1137 if (desc & (1 << 18)) {
1138 /* Supersection. */
1139 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 1140 *page_size = 0x1000000;
b5ff1b31 1141 } else {
9ee6e8bb
PB		 1142 /* Section. */
1143 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 1144 *page_size = 0x100000;
b5ff1b31 1145 }
9ee6e8bb
PB		 1146 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1147 xn = desc & (1 << 4);
1148 code = 13;
1149 } else {
1150 /* Lookup l2 entry. */
1151 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1152 desc = ldl_phys(table);
1153 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1154 switch (desc & 3) {
1155 case 0: /* Page translation fault. */
1156 code = 7;
b5ff1b31 1157 goto do_fault;
9ee6e8bb
PB		 1158 case 1: /* 64k page. */
1159 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1160 xn = desc & (1 << 15);
d4c430a8 1161 *page_size = 0x10000;
9ee6e8bb
PB		 1162 break;
1163 case 2: case 3: /* 4k page. */
1164 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1165 xn = desc & 1;
d4c430a8 1166 *page_size = 0x1000;
9ee6e8bb
PB		 1167 break;
1168 default:
1169 /* Never happens, but compiler isn't smart enough to tell. */
1170 abort();
b5ff1b31 1171 }
9ee6e8bb
PB		 1172 code = 15;
1173 }
dd4ebc2e 1174 if (domain_prot == 3) {
c0034328
JR		 1175 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1176 } else {
1177 if (xn && access_type == 2)
1178 goto do_fault;
9ee6e8bb 1179
c0034328
JR		 1180 /* The simplified model uses AP[0] as an access control bit. */
1181 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1182 /* Access flag fault. */
1183 code = (code == 15) ? 6 : 3;
1184 goto do_fault;
1185 }
dd4ebc2e 1186 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
c0034328
JR		 1187 if (!*prot) {
1188 /* Access permission fault. */
1189 goto do_fault;
1190 }
1191 if (!xn) {
1192 *prot |= PAGE_EXEC;
1193 }
3ad493fc 1194 }
9ee6e8bb 1195 *phys_ptr = phys_addr;
b5ff1b31
FB		 1196 return 0;
1197do_fault:
1198 return code | (domain << 4);
1199}
1200
9ee6e8bb
PB		 1201static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
1202 int is_user, uint32_t *phys_ptr, int *prot)
1203{
1204 int n;
1205 uint32_t mask;
1206 uint32_t base;
1207
1208 *phys_ptr = address;
1209 for (n = 7; n >= 0; n--) {
1210 base = env->cp15.c6_region[n];
1211 if ((base & 1) == 0)
1212 continue;
1213 mask = 1 << ((base >> 1) & 0x1f);
1214 /* Keep this shift separate from the above to avoid an
1215 (undefined) << 32. */
1216 mask = (mask << 1) - 1;
1217 if (((base ^ address) & ~mask) == 0)
1218 break;
1219 }
1220 if (n < 0)
1221 return 2;
1222
1223 if (access_type == 2) {
1224 mask = env->cp15.c5_insn;
1225 } else {
1226 mask = env->cp15.c5_data;
1227 }
1228 mask = (mask >> (n * 4)) & 0xf;
1229 switch (mask) {
1230 case 0:
1231 return 1;
1232 case 1:
1233 if (is_user)
1234 return 1;
1235 *prot = PAGE_READ | PAGE_WRITE;
1236 break;
1237 case 2:
1238 *prot = PAGE_READ;
1239 if (!is_user)
1240 *prot |= PAGE_WRITE;
1241 break;
1242 case 3:
1243 *prot = PAGE_READ | PAGE_WRITE;
1244 break;
1245 case 5:
1246 if (is_user)
1247 return 1;
1248 *prot = PAGE_READ;
1249 break;
1250 case 6:
1251 *prot = PAGE_READ;
1252 break;
1253 default:
1254 /* Bad permission. */
1255 return 1;
1256 }
3ad493fc 1257 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1258 return 0;
1259}
1260
1261static inline int get_phys_addr(CPUState *env, uint32_t address,
1262 int access_type, int is_user,
d4c430a8
PB		 1263 uint32_t *phys_ptr, int *prot,
1264 target_ulong *page_size)
9ee6e8bb
PB		 1265{
1266 /* Fast Context Switch Extension. */
1267 if (address < 0x02000000)
1268 address += env->cp15.c13_fcse;
1269
1270 if ((env->cp15.c1_sys & 1) == 0) {
1271 /* MMU/MPU disabled. */
1272 *phys_ptr = address;
3ad493fc 1273 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 1274 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1275 return 0;
1276 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 1277 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1278 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1279 prot);
1280 } else if (env->cp15.c1_sys & (1 << 23)) {
1281 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 1282 prot, page_size);
9ee6e8bb
PB		 1283 } else {
1284 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 1285 prot, page_size);
9ee6e8bb
PB		 1286 }
1287}
1288
b5ff1b31 1289int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
97b348e7 1290 int access_type, int mmu_idx)
b5ff1b31
FB		 1291{
1292 uint32_t phys_addr;
d4c430a8 1293 target_ulong page_size;
b5ff1b31 1294 int prot;
6ebbf390 1295 int ret, is_user;
b5ff1b31 1296
6ebbf390 1297 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 1298 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
1299 &page_size);
b5ff1b31
FB		 1300 if (ret == 0) {
1301 /* Map a single [sub]page. */
1302 phys_addr &= ~(uint32_t)0x3ff;
1303 address &= ~(uint32_t)0x3ff;
3ad493fc 1304 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 1305 return 0;
b5ff1b31
FB		 1306 }
1307
1308 if (access_type == 2) {
1309 env->cp15.c5_insn = ret;
1310 env->cp15.c6_insn = address;
1311 env->exception_index = EXCP_PREFETCH_ABORT;
1312 } else {
1313 env->cp15.c5_data = ret;
9ee6e8bb
PB		 1314 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1315 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 1316 env->cp15.c6_data = address;
1317 env->exception_index = EXCP_DATA_ABORT;
1318 }
1319 return 1;
1320}
1321
c227f099 1322target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
b5ff1b31
FB		 1323{
1324 uint32_t phys_addr;
d4c430a8 1325 target_ulong page_size;
b5ff1b31
FB		 1326 int prot;
1327 int ret;
1328
d4c430a8 1329 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 1330
1331 if (ret != 0)
1332 return -1;
1333
1334 return phys_addr;
1335}
1336
8984bd2e 1337void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 1338{
1339 int cp_num = (insn >> 8) & 0xf;
1340 int cp_info = (insn >> 5) & 7;
1341 int src = (insn >> 16) & 0xf;
1342 int operand = insn & 0xf;
1343
1344 if (env->cp[cp_num].cp_write)
1345 env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1346 cp_info, src, operand, val);
1347}
1348
8984bd2e 1349uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 1350{
1351 int cp_num = (insn >> 8) & 0xf;
1352 int cp_info = (insn >> 5) & 7;
1353 int dest = (insn >> 16) & 0xf;
1354 int operand = insn & 0xf;
1355
1356 if (env->cp[cp_num].cp_read)
1357 return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1358 cp_info, dest, operand);
1359 return 0;
1360}
1361
ce819861
PB		 1362/* Return basic MPU access permission bits. */
1363static uint32_t simple_mpu_ap_bits(uint32_t val)
1364{
1365 uint32_t ret;
1366 uint32_t mask;
1367 int i;
1368 ret = 0;
1369 mask = 3;
1370 for (i = 0; i < 16; i += 2) {
1371 ret |= (val >> i) & mask;
1372 mask <<= 2;
1373 }
1374 return ret;
1375}
1376
1377/* Pad basic MPU access permission bits to extended format. */
1378static uint32_t extended_mpu_ap_bits(uint32_t val)
1379{
1380 uint32_t ret;
1381 uint32_t mask;
1382 int i;
1383 ret = 0;
1384 mask = 3;
1385 for (i = 0; i < 16; i += 2) {
1386 ret |= (val & mask) << i;
1387 mask <<= 2;
1388 }
1389 return ret;
1390}
1391
8984bd2e 1392void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31 1393{
9ee6e8bb
PB		 1394 int op1;
1395 int op2;
1396 int crm;
b5ff1b31 1397
9ee6e8bb 1398 op1 = (insn >> 21) & 7;
b5ff1b31 1399 op2 = (insn >> 5) & 7;
ce819861 1400 crm = insn & 0xf;
b5ff1b31 1401 switch ((insn >> 16) & 0xf) {
9ee6e8bb 1402 case 0:
9ee6e8bb 1403 /* ID codes. */
610c3c8a
AZ		 1404 if (arm_feature(env, ARM_FEATURE_XSCALE))
1405 break;
c3d2689d
AZ		 1406 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1407 break;
a49ea279
PB		 1408 if (arm_feature(env, ARM_FEATURE_V7)
1409 && op1 == 2 && crm == 0 && op2 == 0) {
1410 env->cp15.c0_cssel = val & 0xf;
1411 break;
1412 }
b5ff1b31
FB		 1413 goto bad_reg;
1414 case 1: /* System configuration. */
c3d2689d
AZ		 1415 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1416 op2 = 0;
b5ff1b31
FB		 1417 switch (op2) {
1418 case 0:
ce819861 1419 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
c1713132 1420 env->cp15.c1_sys = val;
b5ff1b31
FB		 1421 /* ??? Lots of these bits are not implemented. */
1422 /* This may enable/disable the MMU, so do a TLB flush. */
1423 tlb_flush(env, 1);
1424 break;
61cc8701 1425 case 1: /* Auxiliary control register. */
610c3c8a
AZ		 1426 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1427 env->cp15.c1_xscaleauxcr = val;
c1713132 1428 break;
610c3c8a 1429 }
9ee6e8bb
PB		 1430 /* Not implemented. */
1431 break;
b5ff1b31 1432 case 2:
610c3c8a
AZ		 1433 if (arm_feature(env, ARM_FEATURE_XSCALE))
1434 goto bad_reg;
4be27dbb
PB		 1435 if (env->cp15.c1_coproc != val) {
1436 env->cp15.c1_coproc = val;
1437 /* ??? Is this safe when called from within a TB? */
1438 tb_flush(env);
1439 }
c1713132 1440 break;
b5ff1b31
FB		 1441 default:
1442 goto bad_reg;
1443 }
1444 break;
ce819861
PB		 1445 case 2: /* MMU Page table control / MPU cache control. */
1446 if (arm_feature(env, ARM_FEATURE_MPU)) {
1447 switch (op2) {
1448 case 0:
1449 env->cp15.c2_data = val;
1450 break;
1451 case 1:
1452 env->cp15.c2_insn = val;
1453 break;
1454 default:
1455 goto bad_reg;
1456 }
1457 } else {
9ee6e8bb
PB		 1458 switch (op2) {
1459 case 0:
1460 env->cp15.c2_base0 = val;
1461 break;
1462 case 1:
1463 env->cp15.c2_base1 = val;
1464 break;
1465 case 2:
b2fa1797
PB		 1466 val &= 7;
1467 env->cp15.c2_control = val;
9ee6e8bb 1468 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
b2fa1797 1469 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
9ee6e8bb
PB		 1470 break;
1471 default:
1472 goto bad_reg;
1473 }
ce819861 1474 }
b5ff1b31 1475 break;
ce819861 1476 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31 1477 env->cp15.c3 = val;
405ee3ad 1478 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
b5ff1b31
FB		 1479 break;
1480 case 4: /* Reserved. */
1481 goto bad_reg;
ce819861 1482 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1483 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1484 op2 = 0;
b5ff1b31
FB		 1485 switch (op2) {
1486 case 0:
ce819861
PB		 1487 if (arm_feature(env, ARM_FEATURE_MPU))
1488 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1489 env->cp15.c5_data = val;
1490 break;
1491 case 1:
ce819861
PB		 1492 if (arm_feature(env, ARM_FEATURE_MPU))
1493 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1494 env->cp15.c5_insn = val;
1495 break;
ce819861
PB		 1496 case 2:
1497 if (!arm_feature(env, ARM_FEATURE_MPU))
1498 goto bad_reg;
1499 env->cp15.c5_data = val;
b5ff1b31 1500 break;
ce819861
PB		 1501 case 3:
1502 if (!arm_feature(env, ARM_FEATURE_MPU))
1503 goto bad_reg;
1504 env->cp15.c5_insn = val;
b5ff1b31
FB		 1505 break;
1506 default:
1507 goto bad_reg;
1508 }
1509 break;
ce819861
PB		 1510 case 6: /* MMU Fault address / MPU base/size. */
1511 if (arm_feature(env, ARM_FEATURE_MPU)) {
1512 if (crm >= 8)
1513 goto bad_reg;
1514 env->cp15.c6_region[crm] = val;
1515 } else {
c3d2689d
AZ		 1516 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1517 op2 = 0;
ce819861
PB		 1518 switch (op2) {
1519 case 0:
1520 env->cp15.c6_data = val;
1521 break;
9ee6e8bb
PB		 1522 case 1: /* ??? This is WFAR on armv6 */
1523 case 2:
ce819861
PB		 1524 env->cp15.c6_insn = val;
1525 break;
1526 default:
1527 goto bad_reg;
1528 }
1529 }
1530 break;
b5ff1b31 1531 case 7: /* Cache control. */
c3d2689d
AZ		 1532 env->cp15.c15_i_max = 0x000;
1533 env->cp15.c15_i_min = 0xff0;
f8bf8606
AL		 1534 if (op1 != 0) {
1535 goto bad_reg;
1536 }
1537 /* No cache, so nothing to do except VA->PA translations. */
906879a9 1538 if (arm_feature(env, ARM_FEATURE_VAPA)) {
f8bf8606
AL		 1539 switch (crm) {
1540 case 4:
1541 if (arm_feature(env, ARM_FEATURE_V7)) {
1542 env->cp15.c7_par = val & 0xfffff6ff;
1543 } else {
1544 env->cp15.c7_par = val & 0xfffff1ff;
1545 }
1546 break;
1547 case 8: {
1548 uint32_t phys_addr;
1549 target_ulong page_size;
1550 int prot;
1551 int ret, is_user = op2 & 2;
1552 int access_type = op2 & 1;
1553
1554 if (op2 & 4) {
1555 /* Other states are only available with TrustZone */
1556 goto bad_reg;
1557 }
1558 ret = get_phys_addr(env, val, access_type, is_user,
1559 &phys_addr, &prot, &page_size);
1560 if (ret == 0) {
1561 /* We do not set any attribute bits in the PAR */
1562 if (page_size == (1 << 24)
1563 && arm_feature(env, ARM_FEATURE_V7)) {
1564 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1565 } else {
1566 env->cp15.c7_par = phys_addr & 0xfffff000;
1567 }
1568 } else {
1569 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1570 ((ret & (12 << 1)) >> 6) |
1571 ((ret & 0xf) << 1) | 1;
1572 }
1573 break;
1574 }
1575 }
1576 }
b5ff1b31
FB		 1577 break;
1578 case 8: /* MMU TLB control. */
1579 switch (op2) {
1580 case 0: /* Invalidate all. */
1581 tlb_flush(env, 0);
1582 break;
1583 case 1: /* Invalidate single TLB entry. */
d4c430a8 1584 tlb_flush_page(env, val & TARGET_PAGE_MASK);
b5ff1b31 1585 break;
9ee6e8bb
PB		 1586 case 2: /* Invalidate on ASID. */
1587 tlb_flush(env, val == 0);
1588 break;
1589 case 3: /* Invalidate single entry on MVA. */
1590 /* ??? This is like case 1, but ignores ASID. */
1591 tlb_flush(env, 1);
1592 break;
b5ff1b31
FB		 1593 default:
1594 goto bad_reg;
1595 }
1596 break;
ce819861 1597 case 9:
c3d2689d
AZ		 1598 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1599 break;
5bc95aa2
DES		 1600 if (arm_feature(env, ARM_FEATURE_STRONGARM))
1601 break; /* Ignore ReadBuffer access */
ce819861
PB		 1602 switch (crm) {
1603 case 0: /* Cache lockdown. */
9ee6e8bb
PB		 1604 switch (op1) {
1605 case 0: /* L1 cache. */
1606 switch (op2) {
1607 case 0:
1608 env->cp15.c9_data = val;
1609 break;
1610 case 1:
1611 env->cp15.c9_insn = val;
1612 break;
1613 default:
1614 goto bad_reg;
1615 }
1616 break;
1617 case 1: /* L2 cache. */
1618 /* Ignore writes to L2 lockdown/auxiliary registers. */
1619 break;
1620 default:
1621 goto bad_reg;
1622 }
1623 break;
ce819861
PB		 1624 case 1: /* TCM memory region registers. */
1625 /* Not implemented. */
1626 goto bad_reg;
74594c9d
PM		 1627 case 12: /* Performance monitor control */
1628 /* Performance monitors are implementation defined in v7,
1629 * but with an ARM recommended set of registers, which we
1630 * follow (although we don't actually implement any counters)
1631 */
1632 if (!arm_feature(env, ARM_FEATURE_V7)) {
1633 goto bad_reg;
1634 }
1635 switch (op2) {
1636 case 0: /* performance monitor control register */
1637 /* only the DP, X, D and E bits are writable */
1638 env->cp15.c9_pmcr &= ~0x39;
1639 env->cp15.c9_pmcr |= (val & 0x39);
1640 break;
1641 case 1: /* Count enable set register */
1642 val &= (1 << 31);
1643 env->cp15.c9_pmcnten |= val;
1644 break;
1645 case 2: /* Count enable clear */
1646 val &= (1 << 31);
1647 env->cp15.c9_pmcnten &= ~val;
1648 break;
1649 case 3: /* Overflow flag status */
1650 env->cp15.c9_pmovsr &= ~val;
1651 break;
1652 case 4: /* Software increment */
1653 /* RAZ/WI since we don't implement the software-count event */
1654 break;
1655 case 5: /* Event counter selection register */
1656 /* Since we don't implement any events, writing to this register
1657 * is actually UNPREDICTABLE. So we choose to RAZ/WI.
1658 */
1659 break;
1660 default:
1661 goto bad_reg;
1662 }
1663 break;
1664 case 13: /* Performance counters */
1665 if (!arm_feature(env, ARM_FEATURE_V7)) {
1666 goto bad_reg;
1667 }
1668 switch (op2) {
1669 case 0: /* Cycle count register: not implemented, so RAZ/WI */
1670 break;
1671 case 1: /* Event type select */
1672 env->cp15.c9_pmxevtyper = val & 0xff;
1673 break;
1674 case 2: /* Event count register */
1675 /* Unimplemented (we have no events), RAZ/WI */
1676 break;
1677 default:
1678 goto bad_reg;
1679 }
1680 break;
1681 case 14: /* Performance monitor control */
1682 if (!arm_feature(env, ARM_FEATURE_V7)) {
1683 goto bad_reg;
1684 }
1685 switch (op2) {
1686 case 0: /* user enable */
1687 env->cp15.c9_pmuserenr = val & 1;
1688 /* changes access rights for cp registers, so flush tbs */
1689 tb_flush(env);
1690 break;
1691 case 1: /* interrupt enable set */
1692 /* We have no event counters so only the C bit can be changed */
1693 val &= (1 << 31);
1694 env->cp15.c9_pminten |= val;
1695 break;
1696 case 2: /* interrupt enable clear */
1697 val &= (1 << 31);
1698 env->cp15.c9_pminten &= ~val;
1699 break;
1700 }
1701 break;
b5ff1b31
FB		 1702 default:
1703 goto bad_reg;
1704 }
1705 break;
1706 case 10: /* MMU TLB lockdown. */
1707 /* ??? TLB lockdown not implemented. */
1708 break;
b5ff1b31
FB		 1709 case 12: /* Reserved. */
1710 goto bad_reg;
1711 case 13: /* Process ID. */
1712 switch (op2) {
1713 case 0:
d07edbfa
PB		 1714 /* Unlike real hardware the qemu TLB uses virtual addresses,
1715 not modified virtual addresses, so this causes a TLB flush.
1716 */
1717 if (env->cp15.c13_fcse != val)
1718 tlb_flush(env, 1);
1719 env->cp15.c13_fcse = val;
b5ff1b31
FB		 1720 break;
1721 case 1:
d07edbfa 1722 /* This changes the ASID, so do a TLB flush. */
ce819861
PB		 1723 if (env->cp15.c13_context != val
1724 && !arm_feature(env, ARM_FEATURE_MPU))
d07edbfa
PB		 1725 tlb_flush(env, 0);
1726 env->cp15.c13_context = val;
b5ff1b31
FB		 1727 break;
1728 default:
1729 goto bad_reg;
1730 }
1731 break;
1732 case 14: /* Reserved. */
1733 goto bad_reg;
1734 case 15: /* Implementation specific. */
c1713132 1735 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
ce819861 1736 if (op2 == 0 && crm == 1) {
2e23213f
AZ		 1737 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1738 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1739 tb_flush(env);
1740 env->cp15.c15_cpar = val & 0x3fff;
1741 }
c1713132
AZ		 1742 break;
1743 }
1744 goto bad_reg;
1745 }
c3d2689d
AZ		 1746 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1747 switch (crm) {
1748 case 0:
1749 break;
1750 case 1: /* Set TI925T configuration. */
1751 env->cp15.c15_ticonfig = val & 0xe7;
1752 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1753 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1754 break;
1755 case 2: /* Set I_max. */
1756 env->cp15.c15_i_max = val;
1757 break;
1758 case 3: /* Set I_min. */
1759 env->cp15.c15_i_min = val;
1760 break;
1761 case 4: /* Set thread-ID. */
1762 env->cp15.c15_threadid = val & 0xffff;
1763 break;
1764 case 8: /* Wait-for-interrupt (deprecated). */
1765 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1766 break;
1767 default:
1768 goto bad_reg;
1769 }
1770 }
b5ff1b31
FB		 1771 break;
1772 }
1773 return;
1774bad_reg:
1775 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1776 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1777 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1778}
1779
8984bd2e 1780uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31 1781{
9ee6e8bb
PB		 1782 int op1;
1783 int op2;
1784 int crm;
b5ff1b31 1785
9ee6e8bb 1786 op1 = (insn >> 21) & 7;
b5ff1b31 1787 op2 = (insn >> 5) & 7;
c3d2689d 1788 crm = insn & 0xf;
b5ff1b31
FB		 1789 switch ((insn >> 16) & 0xf) {
1790 case 0: /* ID codes. */
9ee6e8bb
PB		 1791 switch (op1) {
1792 case 0:
1793 switch (crm) {
1794 case 0:
1795 switch (op2) {
1796 case 0: /* Device ID. */
1797 return env->cp15.c0_cpuid;
1798 case 1: /* Cache Type. */
1799 return env->cp15.c0_cachetype;
1800 case 2: /* TCM status. */
1801 return 0;
1802 case 3: /* TLB type register. */
1803 return 0; /* No lockable TLB entries. */
607b4b08
PM		 1804 case 5: /* MPIDR */
1805 /* The MPIDR was standardised in v7; prior to
1806 * this it was implemented only in the 11MPCore.
1807 * For all other pre-v7 cores it does not exist.
1808 */
1809 if (arm_feature(env, ARM_FEATURE_V7) ||
1810 ARM_CPUID(env) == ARM_CPUID_ARM11MPCORE) {
1811 int mpidr = env->cpu_index;
1812 /* We don't support setting cluster ID ([8..11])
1813 * so these bits always RAZ.
1814 */
1815 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1816 mpidr |= (1 << 31);
1817 /* Cores which are uniprocessor (non-coherent)
1818 * but still implement the MP extensions set
1819 * bit 30. (For instance, A9UP.) However we do
1820 * not currently model any of those cores.
1821 */
1822 }
1823 return mpidr;
10055562 1824 }
607b4b08 1825 /* otherwise fall through to the unimplemented-reg case */
9ee6e8bb
PB		 1826 default:
1827 goto bad_reg;
1828 }
1829 case 1:
1830 if (!arm_feature(env, ARM_FEATURE_V6))
1831 goto bad_reg;
1832 return env->cp15.c0_c1[op2];
1833 case 2:
1834 if (!arm_feature(env, ARM_FEATURE_V6))
1835 goto bad_reg;
1836 return env->cp15.c0_c2[op2];
1837 case 3: case 4: case 5: case 6: case 7:
1838 return 0;
1839 default:
1840 goto bad_reg;
1841 }
1842 case 1:
1843 /* These registers aren't documented on arm11 cores. However
1844 Linux looks at them anyway. */
1845 if (!arm_feature(env, ARM_FEATURE_V6))
1846 goto bad_reg;
1847 if (crm != 0)
1848 goto bad_reg;
a49ea279
PB		 1849 if (!arm_feature(env, ARM_FEATURE_V7))
1850 return 0;
1851
1852 switch (op2) {
1853 case 0:
1854 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1855 case 1:
1856 return env->cp15.c0_clid;
1857 case 7:
1858 return 0;
1859 }
1860 goto bad_reg;
1861 case 2:
1862 if (op2 != 0 || crm != 0)
610c3c8a 1863 goto bad_reg;
a49ea279 1864 return env->cp15.c0_cssel;
9ee6e8bb
PB		 1865 default:
1866 goto bad_reg;
b5ff1b31
FB		 1867 }
1868 case 1: /* System configuration. */
c3d2689d
AZ		 1869 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1870 op2 = 0;
b5ff1b31
FB		 1871 switch (op2) {
1872 case 0: /* Control register. */
1873 return env->cp15.c1_sys;
1874 case 1: /* Auxiliary control register. */
c1713132 1875 if (arm_feature(env, ARM_FEATURE_XSCALE))
610c3c8a 1876 return env->cp15.c1_xscaleauxcr;
9ee6e8bb
PB		 1877 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1878 goto bad_reg;
1879 switch (ARM_CPUID(env)) {
1880 case ARM_CPUID_ARM1026:
1881 return 1;
1882 case ARM_CPUID_ARM1136:
827df9f3 1883 case ARM_CPUID_ARM1136_R2:
7807eed9 1884 case ARM_CPUID_ARM1176:
9ee6e8bb
PB		 1885 return 7;
1886 case ARM_CPUID_ARM11MPCORE:
1887 return 1;
1888 case ARM_CPUID_CORTEXA8:
533d177a 1889 return 2;
10055562
PB		 1890 case ARM_CPUID_CORTEXA9:
1891 return 0;
9ee6e8bb
PB		 1892 default:
1893 goto bad_reg;
1894 }
b5ff1b31 1895 case 2: /* Coprocessor access register. */
610c3c8a
AZ		 1896 if (arm_feature(env, ARM_FEATURE_XSCALE))
1897 goto bad_reg;
b5ff1b31
FB		 1898 return env->cp15.c1_coproc;
1899 default:
1900 goto bad_reg;
1901 }
ce819861
PB		 1902 case 2: /* MMU Page table control / MPU cache control. */
1903 if (arm_feature(env, ARM_FEATURE_MPU)) {
1904 switch (op2) {
1905 case 0:
1906 return env->cp15.c2_data;
1907 break;
1908 case 1:
1909 return env->cp15.c2_insn;
1910 break;
1911 default:
1912 goto bad_reg;
1913 }
1914 } else {
9ee6e8bb
PB		 1915 switch (op2) {
1916 case 0:
1917 return env->cp15.c2_base0;
1918 case 1:
1919 return env->cp15.c2_base1;
1920 case 2:
b2fa1797 1921 return env->cp15.c2_control;
9ee6e8bb
PB		 1922 default:
1923 goto bad_reg;
1924 }
1925 }
ce819861 1926 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31
FB		 1927 return env->cp15.c3;
1928 case 4: /* Reserved. */
1929 goto bad_reg;
ce819861 1930 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1931 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1932 op2 = 0;
b5ff1b31
FB		 1933 switch (op2) {
1934 case 0:
ce819861
PB		 1935 if (arm_feature(env, ARM_FEATURE_MPU))
1936 return simple_mpu_ap_bits(env->cp15.c5_data);
b5ff1b31
FB		 1937 return env->cp15.c5_data;
1938 case 1:
ce819861
PB		 1939 if (arm_feature(env, ARM_FEATURE_MPU))
1940 return simple_mpu_ap_bits(env->cp15.c5_data);
1941 return env->cp15.c5_insn;
1942 case 2:
1943 if (!arm_feature(env, ARM_FEATURE_MPU))
1944 goto bad_reg;
1945 return env->cp15.c5_data;
1946 case 3:
1947 if (!arm_feature(env, ARM_FEATURE_MPU))
1948 goto bad_reg;
b5ff1b31
FB		 1949 return env->cp15.c5_insn;
1950 default:
1951 goto bad_reg;
1952 }
9ee6e8bb 1953 case 6: /* MMU Fault address. */
ce819861 1954 if (arm_feature(env, ARM_FEATURE_MPU)) {
9ee6e8bb 1955 if (crm >= 8)
ce819861 1956 goto bad_reg;
9ee6e8bb 1957 return env->cp15.c6_region[crm];
ce819861 1958 } else {
c3d2689d
AZ		 1959 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1960 op2 = 0;
9ee6e8bb
PB		 1961 switch (op2) {
1962 case 0:
1963 return env->cp15.c6_data;
1964 case 1:
1965 if (arm_feature(env, ARM_FEATURE_V6)) {
1966 /* Watchpoint Fault Adrress. */
1967 return 0; /* Not implemented. */
1968 } else {
1969 /* Instruction Fault Adrress. */
1970 /* Arm9 doesn't have an IFAR, but implementing it anyway
1971 shouldn't do any harm. */
1972 return env->cp15.c6_insn;
1973 }
1974 case 2:
1975 if (arm_feature(env, ARM_FEATURE_V6)) {
1976 /* Instruction Fault Adrress. */
1977 return env->cp15.c6_insn;
1978 } else {
1979 goto bad_reg;
1980 }
1981 default:
1982 goto bad_reg;
1983 }
b5ff1b31
FB		 1984 }
1985 case 7: /* Cache control. */
f8bf8606
AL		 1986 if (crm == 4 && op1 == 0 && op2 == 0) {
1987 return env->cp15.c7_par;
1988 }
6fbe23d5
PB		 1989 /* FIXME: Should only clear Z flag if destination is r15. */
1990 env->ZF = 0;
b5ff1b31
FB		 1991 return 0;
1992 case 8: /* MMU TLB control. */
1993 goto bad_reg;
74594c9d
PM		 1994 case 9:
1995 switch (crm) {
1996 case 0: /* Cache lockdown */
1997 switch (op1) {
1998 case 0: /* L1 cache. */
1999 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2000 return 0;
2001 }
2002 switch (op2) {
2003 case 0:
2004 return env->cp15.c9_data;
2005 case 1:
2006 return env->cp15.c9_insn;
2007 default:
2008 goto bad_reg;
2009 }
2010 case 1: /* L2 cache */
2011 if (crm != 0) {
2012 goto bad_reg;
2013 }
2014 /* L2 Lockdown and Auxiliary control. */
2015 return 0;
2016 default:
2017 goto bad_reg;
2018 }
2019 break;
2020 case 12: /* Performance monitor control */
2021 if (!arm_feature(env, ARM_FEATURE_V7)) {
2022 goto bad_reg;
2023 }
9ee6e8bb 2024 switch (op2) {
74594c9d
PM		 2025 case 0: /* performance monitor control register */
2026 return env->cp15.c9_pmcr;
2027 case 1: /* count enable set */
2028 case 2: /* count enable clear */
2029 return env->cp15.c9_pmcnten;
2030 case 3: /* overflow flag status */
2031 return env->cp15.c9_pmovsr;
2032 case 4: /* software increment */
2033 case 5: /* event counter selection register */
2034 return 0; /* Unimplemented, RAZ/WI */
9ee6e8bb
PB		 2035 default:
2036 goto bad_reg;
2037 }
74594c9d
PM		 2038 case 13: /* Performance counters */
2039 if (!arm_feature(env, ARM_FEATURE_V7)) {
2040 goto bad_reg;
2041 }
2042 switch (op2) {
2043 case 1: /* Event type select */
2044 return env->cp15.c9_pmxevtyper;
2045 case 0: /* Cycle count register */
2046 case 2: /* Event count register */
2047 /* Unimplemented, so RAZ/WI */
2048 return 0;
2049 default:
9ee6e8bb 2050 goto bad_reg;
74594c9d
PM		 2051 }
2052 case 14: /* Performance monitor control */
2053 if (!arm_feature(env, ARM_FEATURE_V7)) {
2054 goto bad_reg;
2055 }
2056 switch (op2) {
2057 case 0: /* user enable */
2058 return env->cp15.c9_pmuserenr;
2059 case 1: /* interrupt enable set */
2060 case 2: /* interrupt enable clear */
2061 return env->cp15.c9_pminten;
2062 default:
2063 goto bad_reg;
2064 }
b5ff1b31
FB		 2065 default:
2066 goto bad_reg;
2067 }
74594c9d 2068 break;
b5ff1b31
FB		 2069 case 10: /* MMU TLB lockdown. */
2070 /* ??? TLB lockdown not implemented. */
2071 return 0;
2072 case 11: /* TCM DMA control. */
2073 case 12: /* Reserved. */
2074 goto bad_reg;
2075 case 13: /* Process ID. */
2076 switch (op2) {
2077 case 0:
2078 return env->cp15.c13_fcse;
2079 case 1:
2080 return env->cp15.c13_context;
2081 default:
2082 goto bad_reg;
2083 }
2084 case 14: /* Reserved. */
2085 goto bad_reg;
2086 case 15: /* Implementation specific. */
c1713132 2087 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
c3d2689d 2088 if (op2 == 0 && crm == 1)
c1713132
AZ		 2089 return env->cp15.c15_cpar;
2090
2091 goto bad_reg;
2092 }
c3d2689d
AZ		 2093 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2094 switch (crm) {
2095 case 0:
2096 return 0;
2097 case 1: /* Read TI925T configuration. */
2098 return env->cp15.c15_ticonfig;
2099 case 2: /* Read I_max. */
2100 return env->cp15.c15_i_max;
2101 case 3: /* Read I_min. */
2102 return env->cp15.c15_i_min;
2103 case 4: /* Read thread-ID. */
2104 return env->cp15.c15_threadid;
2105 case 8: /* TI925T_status */
2106 return 0;
2107 }
827df9f3
AZ		 2108 /* TODO: Peripheral port remap register:
2109 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
2110 * controller base address at $rn & ~0xfff and map size of
2111 * 0x200 << ($rn & 0xfff), when MMU is off. */
c3d2689d
AZ		 2112 goto bad_reg;
2113 }
b5ff1b31
FB		 2114 return 0;
2115 }
2116bad_reg:
2117 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 2118 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2119 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 2120 return 0;
2121}
2122
b0109805 2123void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb 2124{
39ea3d4e
PM		 2125 if ((env->uncached_cpsr & CPSR_M) == mode) {
2126 env->regs[13] = val;
2127 } else {
2128 env->banked_r13[bank_number(mode)] = val;
2129 }
9ee6e8bb
PB		 2130}
2131
b0109805 2132uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb 2133{
39ea3d4e
PM		 2134 if ((env->uncached_cpsr & CPSR_M) == mode) {
2135 return env->regs[13];
2136 } else {
2137 return env->banked_r13[bank_number(mode)];
2138 }
9ee6e8bb
PB		 2139}
2140
8984bd2e 2141uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 2142{
2143 switch (reg) {
2144 case 0: /* APSR */
2145 return xpsr_read(env) & 0xf8000000;
2146 case 1: /* IAPSR */
2147 return xpsr_read(env) & 0xf80001ff;
2148 case 2: /* EAPSR */
2149 return xpsr_read(env) & 0xff00fc00;
2150 case 3: /* xPSR */
2151 return xpsr_read(env) & 0xff00fdff;
2152 case 5: /* IPSR */
2153 return xpsr_read(env) & 0x000001ff;
2154 case 6: /* EPSR */
2155 return xpsr_read(env) & 0x0700fc00;
2156 case 7: /* IEPSR */
2157 return xpsr_read(env) & 0x0700edff;
2158 case 8: /* MSP */
2159 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2160 case 9: /* PSP */
2161 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2162 case 16: /* PRIMASK */
2163 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 2164 case 17: /* BASEPRI */
2165 case 18: /* BASEPRI_MAX */
9ee6e8bb 2166 return env->v7m.basepri;
82845826
SH		 2167 case 19: /* FAULTMASK */
2168 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 2169 case 20: /* CONTROL */
2170 return env->v7m.control;
2171 default:
2172 /* ??? For debugging only. */
2173 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2174 return 0;
2175 }
2176}
2177
8984bd2e 2178void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2179{
2180 switch (reg) {
2181 case 0: /* APSR */
2182 xpsr_write(env, val, 0xf8000000);
2183 break;
2184 case 1: /* IAPSR */
2185 xpsr_write(env, val, 0xf8000000);
2186 break;
2187 case 2: /* EAPSR */
2188 xpsr_write(env, val, 0xfe00fc00);
2189 break;
2190 case 3: /* xPSR */
2191 xpsr_write(env, val, 0xfe00fc00);
2192 break;
2193 case 5: /* IPSR */
2194 /* IPSR bits are readonly. */
2195 break;
2196 case 6: /* EPSR */
2197 xpsr_write(env, val, 0x0600fc00);
2198 break;
2199 case 7: /* IEPSR */
2200 xpsr_write(env, val, 0x0600fc00);
2201 break;
2202 case 8: /* MSP */
2203 if (env->v7m.current_sp)
2204 env->v7m.other_sp = val;
2205 else
2206 env->regs[13] = val;
2207 break;
2208 case 9: /* PSP */
2209 if (env->v7m.current_sp)
2210 env->regs[13] = val;
2211 else
2212 env->v7m.other_sp = val;
2213 break;
2214 case 16: /* PRIMASK */
2215 if (val & 1)
2216 env->uncached_cpsr |= CPSR_I;
2217 else
2218 env->uncached_cpsr &= ~CPSR_I;
2219 break;
82845826 2220 case 17: /* BASEPRI */
9ee6e8bb
PB		 2221 env->v7m.basepri = val & 0xff;
2222 break;
82845826 2223 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 2224 val &= 0xff;
2225 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2226 env->v7m.basepri = val;
2227 break;
82845826
SH		 2228 case 19: /* FAULTMASK */
2229 if (val & 1)
2230 env->uncached_cpsr |= CPSR_F;
2231 else
2232 env->uncached_cpsr &= ~CPSR_F;
2233 break;
9ee6e8bb
PB		 2234 case 20: /* CONTROL */
2235 env->v7m.control = val & 3;
2236 switch_v7m_sp(env, (val & 2) != 0);
2237 break;
2238 default:
2239 /* ??? For debugging only. */
2240 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2241 return;
2242 }
2243}
2244
c1713132
AZ		 2245void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
2246 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
2247 void *opaque)
2248{
2249 if (cpnum < 0 || cpnum > 14) {
2250 cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
2251 return;
2252 }
2253
2254 env->cp[cpnum].cp_read = cp_read;
2255 env->cp[cpnum].cp_write = cp_write;
2256 env->cp[cpnum].opaque = opaque;
2257}
2258
b5ff1b31 2259#endif
6ddbc6e4
PB		 2260
2261/* Note that signed overflow is undefined in C. The following routines are
2262 careful to use unsigned types where modulo arithmetic is required.
2263 Failure to do so _will_ break on newer gcc. */
2264
2265/* Signed saturating arithmetic. */
2266
1654b2d6 2267/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2268static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2269{
2270 uint16_t res;
2271
2272 res = a + b;
2273 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2274 if (a & 0x8000)
2275 res = 0x8000;
2276 else
2277 res = 0x7fff;
2278 }
2279 return res;
2280}
2281
1654b2d6 2282/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2283static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2284{
2285 uint8_t res;
2286
2287 res = a + b;
2288 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2289 if (a & 0x80)
2290 res = 0x80;
2291 else
2292 res = 0x7f;
2293 }
2294 return res;
2295}
2296
1654b2d6 2297/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2298static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2299{
2300 uint16_t res;
2301
2302 res = a - b;
2303 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2304 if (a & 0x8000)
2305 res = 0x8000;
2306 else
2307 res = 0x7fff;
2308 }
2309 return res;
2310}
2311
1654b2d6 2312/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2313static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2314{
2315 uint8_t res;
2316
2317 res = a - b;
2318 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2319 if (a & 0x80)
2320 res = 0x80;
2321 else
2322 res = 0x7f;
2323 }
2324 return res;
2325}
2326
2327#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2328#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2329#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2330#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2331#define PFX q
2332
2333#include "op_addsub.h"
2334
2335/* Unsigned saturating arithmetic. */
460a09c1 2336static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2337{
2338 uint16_t res;
2339 res = a + b;
2340 if (res < a)
2341 res = 0xffff;
2342 return res;
2343}
2344
460a09c1 2345static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2346{
4c4fd3f8 2347 if (a > b)
6ddbc6e4
PB		 2348 return a - b;
2349 else
2350 return 0;
2351}
2352
2353static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2354{
2355 uint8_t res;
2356 res = a + b;
2357 if (res < a)
2358 res = 0xff;
2359 return res;
2360}
2361
2362static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2363{
4c4fd3f8 2364 if (a > b)
6ddbc6e4
PB		 2365 return a - b;
2366 else
2367 return 0;
2368}
2369
2370#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2371#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2372#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2373#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2374#define PFX uq
2375
2376#include "op_addsub.h"
2377
2378/* Signed modulo arithmetic. */
2379#define SARITH16(a, b, n, op) do { \
2380 int32_t sum; \
db6e2e65 2381 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2382 RESULT(sum, n, 16); \
2383 if (sum >= 0) \
2384 ge |= 3 << (n * 2); \
2385 } while(0)
2386
2387#define SARITH8(a, b, n, op) do { \
2388 int32_t sum; \
db6e2e65 2389 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2390 RESULT(sum, n, 8); \
2391 if (sum >= 0) \
2392 ge |= 1 << n; \
2393 } while(0)
2394
2395
2396#define ADD16(a, b, n) SARITH16(a, b, n, +)
2397#define SUB16(a, b, n) SARITH16(a, b, n, -)
2398#define ADD8(a, b, n) SARITH8(a, b, n, +)
2399#define SUB8(a, b, n) SARITH8(a, b, n, -)
2400#define PFX s
2401#define ARITH_GE
2402
2403#include "op_addsub.h"
2404
2405/* Unsigned modulo arithmetic. */
2406#define ADD16(a, b, n) do { \
2407 uint32_t sum; \
2408 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2409 RESULT(sum, n, 16); \
a87aa10b 2410 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2411 ge |= 3 << (n * 2); \
2412 } while(0)
2413
2414#define ADD8(a, b, n) do { \
2415 uint32_t sum; \
2416 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2417 RESULT(sum, n, 8); \
a87aa10b
AZ		 2418 if ((sum >> 8) == 1) \
2419 ge |= 1 << n; \
6ddbc6e4
PB		 2420 } while(0)
2421
2422#define SUB16(a, b, n) do { \
2423 uint32_t sum; \
2424 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2425 RESULT(sum, n, 16); \
2426 if ((sum >> 16) == 0) \
2427 ge |= 3 << (n * 2); \
2428 } while(0)
2429
2430#define SUB8(a, b, n) do { \
2431 uint32_t sum; \
2432 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2433 RESULT(sum, n, 8); \
2434 if ((sum >> 8) == 0) \
a87aa10b 2435 ge |= 1 << n; \
6ddbc6e4
PB		 2436 } while(0)
2437
2438#define PFX u
2439#define ARITH_GE
2440
2441#include "op_addsub.h"
2442
2443/* Halved signed arithmetic. */
2444#define ADD16(a, b, n) \
2445 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2446#define SUB16(a, b, n) \
2447 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2448#define ADD8(a, b, n) \
2449 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2450#define SUB8(a, b, n) \
2451 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2452#define PFX sh
2453
2454#include "op_addsub.h"
2455
2456/* Halved unsigned arithmetic. */
2457#define ADD16(a, b, n) \
2458 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2459#define SUB16(a, b, n) \
2460 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2461#define ADD8(a, b, n) \
2462 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2463#define SUB8(a, b, n) \
2464 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2465#define PFX uh
2466
2467#include "op_addsub.h"
2468
2469static inline uint8_t do_usad(uint8_t a, uint8_t b)
2470{
2471 if (a > b)
2472 return a - b;
2473 else
2474 return b - a;
2475}
2476
2477/* Unsigned sum of absolute byte differences. */
2478uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2479{
2480 uint32_t sum;
2481 sum = do_usad(a, b);
2482 sum += do_usad(a >> 8, b >> 8);
2483 sum += do_usad(a >> 16, b >>16);
2484 sum += do_usad(a >> 24, b >> 24);
2485 return sum;
2486}
2487
2488/* For ARMv6 SEL instruction. */
2489uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2490{
2491 uint32_t mask;
2492
2493 mask = 0;
2494 if (flags & 1)
2495 mask |= 0xff;
2496 if (flags & 2)
2497 mask |= 0xff00;
2498 if (flags & 4)
2499 mask |= 0xff0000;
2500 if (flags & 8)
2501 mask |= 0xff000000;
2502 return (a & mask) | (b & ~mask);
2503}
2504
5e3f878a
PB		 2505uint32_t HELPER(logicq_cc)(uint64_t val)
2506{
2507 return (val >> 32) | (val != 0);
2508}
4373f3ce
PB		 2509
2510/* VFP support. We follow the convention used for VFP instrunctions:
2511 Single precition routines have a "s" suffix, double precision a
2512 "d" suffix. */
2513
2514/* Convert host exception flags to vfp form. */
2515static inline int vfp_exceptbits_from_host(int host_bits)
2516{
2517 int target_bits = 0;
2518
2519 if (host_bits & float_flag_invalid)
2520 target_bits |= 1;
2521 if (host_bits & float_flag_divbyzero)
2522 target_bits |= 2;
2523 if (host_bits & float_flag_overflow)
2524 target_bits |= 4;
36802b6b 2525 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 2526 target_bits |= 8;
2527 if (host_bits & float_flag_inexact)
2528 target_bits |= 0x10;
cecd8504
PM		 2529 if (host_bits & float_flag_input_denormal)
2530 target_bits |= 0x80;
4373f3ce
PB		 2531 return target_bits;
2532}
2533
2534uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
2535{
2536 int i;
2537 uint32_t fpscr;
2538
2539 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2540 | (env->vfp.vec_len << 16)
2541 | (env->vfp.vec_stride << 20);
2542 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2543 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2544 fpscr |= vfp_exceptbits_from_host(i);
2545 return fpscr;
2546}
2547
01653295
PM		 2548uint32_t vfp_get_fpscr(CPUState *env)
2549{
2550 return HELPER(vfp_get_fpscr)(env);
2551}
2552
4373f3ce
PB		 2553/* Convert vfp exception flags to target form. */
2554static inline int vfp_exceptbits_to_host(int target_bits)
2555{
2556 int host_bits = 0;
2557
2558 if (target_bits & 1)
2559 host_bits |= float_flag_invalid;
2560 if (target_bits & 2)
2561 host_bits |= float_flag_divbyzero;
2562 if (target_bits & 4)
2563 host_bits |= float_flag_overflow;
2564 if (target_bits & 8)
2565 host_bits |= float_flag_underflow;
2566 if (target_bits & 0x10)
2567 host_bits |= float_flag_inexact;
cecd8504
PM		 2568 if (target_bits & 0x80)
2569 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2570 return host_bits;
2571}
2572
2573void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
2574{
2575 int i;
2576 uint32_t changed;
2577
2578 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2579 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2580 env->vfp.vec_len = (val >> 16) & 7;
2581 env->vfp.vec_stride = (val >> 20) & 3;
2582
2583 changed ^= val;
2584 if (changed & (3 << 22)) {
2585 i = (val >> 22) & 3;
2586 switch (i) {
2587 case 0:
2588 i = float_round_nearest_even;
2589 break;
2590 case 1:
2591 i = float_round_up;
2592 break;
2593 case 2:
2594 i = float_round_down;
2595 break;
2596 case 3:
2597 i = float_round_to_zero;
2598 break;
2599 }
2600 set_float_rounding_mode(i, &env->vfp.fp_status);
2601 }
cecd8504 2602 if (changed & (1 << 24)) {
fe76d976 2603 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 2604 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2605 }
5c7908ed
PB		 2606 if (changed & (1 << 25))
2607 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 2608
b12c390b 2609 i = vfp_exceptbits_to_host(val);
4373f3ce 2610 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 2611 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 2612}
2613
01653295
PM		 2614void vfp_set_fpscr(CPUState *env, uint32_t val)
2615{
2616 HELPER(vfp_set_fpscr)(env, val);
2617}
2618
4373f3ce
PB		 2619#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2620
2621#define VFP_BINOP(name) \
ae1857ec 2622float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 2623{ \
ae1857ec
PM		 2624 float_status *fpst = fpstp; \
2625 return float32_ ## name(a, b, fpst); \
4373f3ce 2626} \
ae1857ec 2627float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 2628{ \
ae1857ec
PM		 2629 float_status *fpst = fpstp; \
2630 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 2631}
2632VFP_BINOP(add)
2633VFP_BINOP(sub)
2634VFP_BINOP(mul)
2635VFP_BINOP(div)
2636#undef VFP_BINOP
2637
2638float32 VFP_HELPER(neg, s)(float32 a)
2639{
2640 return float32_chs(a);
2641}
2642
2643float64 VFP_HELPER(neg, d)(float64 a)
2644{
66230e0d 2645 return float64_chs(a);
4373f3ce
PB		 2646}
2647
2648float32 VFP_HELPER(abs, s)(float32 a)
2649{
2650 return float32_abs(a);
2651}
2652
2653float64 VFP_HELPER(abs, d)(float64 a)
2654{
66230e0d 2655 return float64_abs(a);
4373f3ce
PB		 2656}
2657
2658float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
2659{
2660 return float32_sqrt(a, &env->vfp.fp_status);
2661}
2662
2663float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
2664{
2665 return float64_sqrt(a, &env->vfp.fp_status);
2666}
2667
2668/* XXX: check quiet/signaling case */
2669#define DO_VFP_cmp(p, type) \
2670void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2671{ \
2672 uint32_t flags; \
2673 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2674 case 0: flags = 0x6; break; \
2675 case -1: flags = 0x8; break; \
2676 case 1: flags = 0x2; break; \
2677 default: case 2: flags = 0x3; break; \
2678 } \
2679 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2680 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2681} \
2682void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2683{ \
2684 uint32_t flags; \
2685 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2686 case 0: flags = 0x6; break; \
2687 case -1: flags = 0x8; break; \
2688 case 1: flags = 0x2; break; \
2689 default: case 2: flags = 0x3; break; \
2690 } \
2691 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2692 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2693}
2694DO_VFP_cmp(s, float32)
2695DO_VFP_cmp(d, float64)
2696#undef DO_VFP_cmp
2697
5500b06c 2698/* Integer to float and float to integer conversions */
4373f3ce 2699
5500b06c
PM		 2700#define CONV_ITOF(name, fsz, sign) \
2701 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2702{ \
2703 float_status *fpst = fpstp; \
2704 return sign##int32_to_##float##fsz(x, fpst); \
4373f3ce
PB		 2705}
2706
5500b06c
PM		 2707#define CONV_FTOI(name, fsz, sign, round) \
2708uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2709{ \
2710 float_status *fpst = fpstp; \
2711 if (float##fsz##_is_any_nan(x)) { \
2712 float_raise(float_flag_invalid, fpst); \
2713 return 0; \
2714 } \
2715 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 2716}
2717
5500b06c
PM		 2718#define FLOAT_CONVS(name, p, fsz, sign) \
2719CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2720CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2721CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 2722
5500b06c
PM		 2723FLOAT_CONVS(si, s, 32, )
2724FLOAT_CONVS(si, d, 64, )
2725FLOAT_CONVS(ui, s, 32, u)
2726FLOAT_CONVS(ui, d, 64, u)
4373f3ce 2727
5500b06c
PM		 2728#undef CONV_ITOF
2729#undef CONV_FTOI
2730#undef FLOAT_CONVS
4373f3ce
PB		 2731
2732/* floating point conversion */
2733float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
2734{
2d627737
PM		 2735 float64 r = float32_to_float64(x, &env->vfp.fp_status);
2736 /* ARM requires that S<->D conversion of any kind of NaN generates
2737 * a quiet NaN by forcing the most significant frac bit to 1.
2738 */
2739 return float64_maybe_silence_nan(r);
4373f3ce
PB		 2740}
2741
2742float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
2743{
2d627737
PM		 2744 float32 r = float64_to_float32(x, &env->vfp.fp_status);
2745 /* ARM requires that S<->D conversion of any kind of NaN generates
2746 * a quiet NaN by forcing the most significant frac bit to 1.
2747 */
2748 return float32_maybe_silence_nan(r);
4373f3ce
PB		 2749}
2750
2751/* VFP3 fixed point conversion. */
622465e1 2752#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 2753float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2754 void *fpstp) \
4373f3ce 2755{ \
5500b06c 2756 float_status *fpst = fpstp; \
622465e1 2757 float##fsz tmp; \
5500b06c
PM		 2758 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2759 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 2760} \
5500b06c
PM		 2761uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2762 void *fpstp) \
4373f3ce 2763{ \
5500b06c 2764 float_status *fpst = fpstp; \
622465e1
PM		 2765 float##fsz tmp; \
2766 if (float##fsz##_is_any_nan(x)) { \
5500b06c 2767 float_raise(float_flag_invalid, fpst); \
622465e1 2768 return 0; \
09d9487f 2769 } \
5500b06c
PM		 2770 tmp = float##fsz##_scalbn(x, shift, fpst); \
2771 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 2772}
2773
2774VFP_CONV_FIX(sh, d, 64, int16, )
2775VFP_CONV_FIX(sl, d, 64, int32, )
2776VFP_CONV_FIX(uh, d, 64, uint16, u)
2777VFP_CONV_FIX(ul, d, 64, uint32, u)
2778VFP_CONV_FIX(sh, s, 32, int16, )
2779VFP_CONV_FIX(sl, s, 32, int32, )
2780VFP_CONV_FIX(uh, s, 32, uint16, u)
2781VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 2782#undef VFP_CONV_FIX
2783
60011498 2784/* Half precision conversions. */
2d981da7 2785static float32 do_fcvt_f16_to_f32(uint32_t a, CPUState *env, float_status *s)
60011498 2786{
60011498 2787 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2788 float32 r = float16_to_float32(make_float16(a), ieee, s);
2789 if (ieee) {
2790 return float32_maybe_silence_nan(r);
2791 }
2792 return r;
60011498
PB		 2793}
2794
2d981da7 2795static uint32_t do_fcvt_f32_to_f16(float32 a, CPUState *env, float_status *s)
60011498 2796{
60011498 2797 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2798 float16 r = float32_to_float16(a, ieee, s);
2799 if (ieee) {
2800 r = float16_maybe_silence_nan(r);
2801 }
2802 return float16_val(r);
60011498
PB		 2803}
2804
2d981da7
PM		 2805float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2806{
2807 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
2808}
2809
2810uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUState *env)
2811{
2812 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
2813}
2814
2815float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2816{
2817 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
2818}
2819
2820uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
2821{
2822 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
2823}
2824
dda3ec49 2825#define float32_two make_float32(0x40000000)
6aae3df1
PM		 2826#define float32_three make_float32(0x40400000)
2827#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 2828
4373f3ce
PB		 2829float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
2830{
dda3ec49
PM		 2831 float_status *s = &env->vfp.standard_fp_status;
2832 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2833 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2834 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2835 float_raise(float_flag_input_denormal, s);
2836 }
dda3ec49
PM		 2837 return float32_two;
2838 }
2839 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 2840}
2841
2842float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
2843{
71826966 2844 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 2845 float32 product;
2846 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2847 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2848 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2849 float_raise(float_flag_input_denormal, s);
2850 }
6aae3df1 2851 return float32_one_point_five;
9ea62f57 2852 }
6aae3df1
PM		 2853 product = float32_mul(a, b, s);
2854 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 2855}
2856
8f8e3aa4
PB		 2857/* NEON helpers. */
2858
56bf4fe2
CL		 2859/* Constants 256 and 512 are used in some helpers; we avoid relying on
2860 * int->float conversions at run-time. */
2861#define float64_256 make_float64(0x4070000000000000LL)
2862#define float64_512 make_float64(0x4080000000000000LL)
2863
fe0e4872
CL		 2864/* The algorithm that must be used to calculate the estimate
2865 * is specified by the ARM ARM.
2866 */
2867static float64 recip_estimate(float64 a, CPUState *env)
2868{
1146a817
PM		 2869 /* These calculations mustn't set any fp exception flags,
2870 * so we use a local copy of the fp_status.
2871 */
2872 float_status dummy_status = env->vfp.standard_fp_status;
2873 float_status *s = &dummy_status;
fe0e4872
CL		 2874 /* q = (int)(a * 512.0) */
2875 float64 q = float64_mul(float64_512, a, s);
2876 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2877
2878 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2879 q = int64_to_float64(q_int, s);
2880 q = float64_add(q, float64_half, s);
2881 q = float64_div(q, float64_512, s);
2882 q = float64_div(float64_one, q, s);
2883
2884 /* s = (int)(256.0 * r + 0.5) */
2885 q = float64_mul(q, float64_256, s);
2886 q = float64_add(q, float64_half, s);
2887 q_int = float64_to_int64_round_to_zero(q, s);
2888
2889 /* return (double)s / 256.0 */
2890 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2891}
2892
4373f3ce
PB		 2893float32 HELPER(recpe_f32)(float32 a, CPUState *env)
2894{
fe0e4872
CL		 2895 float_status *s = &env->vfp.standard_fp_status;
2896 float64 f64;
2897 uint32_t val32 = float32_val(a);
2898
2899 int result_exp;
2900 int a_exp = (val32 & 0x7f800000) >> 23;
2901 int sign = val32 & 0x80000000;
2902
2903 if (float32_is_any_nan(a)) {
2904 if (float32_is_signaling_nan(a)) {
2905 float_raise(float_flag_invalid, s);
2906 }
2907 return float32_default_nan;
2908 } else if (float32_is_infinity(a)) {
2909 return float32_set_sign(float32_zero, float32_is_neg(a));
2910 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 2911 if (!float32_is_zero(a)) {
2912 float_raise(float_flag_input_denormal, s);
2913 }
fe0e4872
CL		 2914 float_raise(float_flag_divbyzero, s);
2915 return float32_set_sign(float32_infinity, float32_is_neg(a));
2916 } else if (a_exp >= 253) {
2917 float_raise(float_flag_underflow, s);
2918 return float32_set_sign(float32_zero, float32_is_neg(a));
2919 }
2920
2921 f64 = make_float64((0x3feULL << 52)
2922 | ((int64_t)(val32 & 0x7fffff) << 29));
2923
2924 result_exp = 253 - a_exp;
2925
2926 f64 = recip_estimate(f64, env);
2927
2928 val32 = sign
2929 | ((result_exp & 0xff) << 23)
2930 | ((float64_val(f64) >> 29) & 0x7fffff);
2931 return make_float32(val32);
4373f3ce
PB		 2932}
2933
e07be5d2
CL		 2934/* The algorithm that must be used to calculate the estimate
2935 * is specified by the ARM ARM.
2936 */
2937static float64 recip_sqrt_estimate(float64 a, CPUState *env)
2938{
1146a817
PM		 2939 /* These calculations mustn't set any fp exception flags,
2940 * so we use a local copy of the fp_status.
2941 */
2942 float_status dummy_status = env->vfp.standard_fp_status;
2943 float_status *s = &dummy_status;
e07be5d2
CL		 2944 float64 q;
2945 int64_t q_int;
2946
2947 if (float64_lt(a, float64_half, s)) {
2948 /* range 0.25 <= a < 0.5 */
2949
2950 /* a in units of 1/512 rounded down */
2951 /* q0 = (int)(a * 512.0); */
2952 q = float64_mul(float64_512, a, s);
2953 q_int = float64_to_int64_round_to_zero(q, s);
2954
2955 /* reciprocal root r */
2956 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2957 q = int64_to_float64(q_int, s);
2958 q = float64_add(q, float64_half, s);
2959 q = float64_div(q, float64_512, s);
2960 q = float64_sqrt(q, s);
2961 q = float64_div(float64_one, q, s);
2962 } else {
2963 /* range 0.5 <= a < 1.0 */
2964
2965 /* a in units of 1/256 rounded down */
2966 /* q1 = (int)(a * 256.0); */
2967 q = float64_mul(float64_256, a, s);
2968 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2969
2970 /* reciprocal root r */
2971 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
2972 q = int64_to_float64(q_int, s);
2973 q = float64_add(q, float64_half, s);
2974 q = float64_div(q, float64_256, s);
2975 q = float64_sqrt(q, s);
2976 q = float64_div(float64_one, q, s);
2977 }
2978 /* r in units of 1/256 rounded to nearest */
2979 /* s = (int)(256.0 * r + 0.5); */
2980
2981 q = float64_mul(q, float64_256,s );
2982 q = float64_add(q, float64_half, s);
2983 q_int = float64_to_int64_round_to_zero(q, s);
2984
2985 /* return (double)s / 256.0;*/
2986 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2987}
2988
4373f3ce
PB		 2989float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
2990{
e07be5d2
CL		 2991 float_status *s = &env->vfp.standard_fp_status;
2992 int result_exp;
2993 float64 f64;
2994 uint32_t val;
2995 uint64_t val64;
2996
2997 val = float32_val(a);
2998
2999 if (float32_is_any_nan(a)) {
3000 if (float32_is_signaling_nan(a)) {
3001 float_raise(float_flag_invalid, s);
3002 }
3003 return float32_default_nan;
3004 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3005 if (!float32_is_zero(a)) {
3006 float_raise(float_flag_input_denormal, s);
3007 }
e07be5d2
CL		 3008 float_raise(float_flag_divbyzero, s);
3009 return float32_set_sign(float32_infinity, float32_is_neg(a));
3010 } else if (float32_is_neg(a)) {
3011 float_raise(float_flag_invalid, s);
3012 return float32_default_nan;
3013 } else if (float32_is_infinity(a)) {
3014 return float32_zero;
3015 }
3016
3017 /* Normalize to a double-precision value between 0.25 and 1.0,
3018 * preserving the parity of the exponent. */
3019 if ((val & 0x800000) == 0) {
3020 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3021 | (0x3feULL << 52)
3022 | ((uint64_t)(val & 0x7fffff) << 29));
3023 } else {
3024 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3025 | (0x3fdULL << 52)
3026 | ((uint64_t)(val & 0x7fffff) << 29));
3027 }
3028
3029 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3030
3031 f64 = recip_sqrt_estimate(f64, env);
3032
3033 val64 = float64_val(f64);
3034
26cc6abf 3035 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 3036 | ((val64 >> 29) & 0x7fffff);
3037 return make_float32(val);
4373f3ce
PB		 3038}
3039
3040uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
3041{
fe0e4872
CL		 3042 float64 f64;
3043
3044 if ((a & 0x80000000) == 0) {
3045 return 0xffffffff;
3046 }
3047
3048 f64 = make_float64((0x3feULL << 52)
3049 | ((int64_t)(a & 0x7fffffff) << 21));
3050
3051 f64 = recip_estimate (f64, env);
3052
3053 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3054}
3055
3056uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
3057{
e07be5d2
CL		 3058 float64 f64;
3059
3060 if ((a & 0xc0000000) == 0) {
3061 return 0xffffffff;
3062 }
3063
3064 if (a & 0x80000000) {
3065 f64 = make_float64((0x3feULL << 52)
3066 | ((uint64_t)(a & 0x7fffffff) << 21));
3067 } else { /* bits 31-30 == '01' */
3068 f64 = make_float64((0x3fdULL << 52)
3069 | ((uint64_t)(a & 0x3fffffff) << 22));
3070 }
3071
3072 f64 = recip_sqrt_estimate(f64, env);
3073
3074 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 3075}
fe1479c3 3076
da97f52c
PM		 3077/* VFPv4 fused multiply-accumulate */
3078float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3079{
3080 float_status *fpst = fpstp;
3081 return float32_muladd(a, b, c, 0, fpst);
3082}
3083
3084float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3085{
3086 float_status *fpst = fpstp;
3087 return float64_muladd(a, b, c, 0, fpst);
3088}
3089
fe1479c3
PB		 3090void HELPER(set_teecr)(CPUState *env, uint32_t val)
3091{
3092 val &= 1;
3093 if (env->teecr != val) {
3094 env->teecr = val;
3095 tb_flush(env);
3096 }
3097}
Qemu copy for testing