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i386: -cpu help: remove reference to specific CPUID leaves/registers
[qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
25#include "kvm.h"
26
27#include "qemu-option.h"
28#include "qemu-config.h"
29
71ad61d3 30#include "qapi/qapi-visit-core.h"
76b64a7a 31#include "arch_init.h"
71ad61d3 32
28f52cc0
VR		 33#include "hyperv.h"
34
65dee380 35#include "hw/hw.h"
b834b508 36#if defined(CONFIG_KVM)
ef8621b1 37#include <linux/kvm_para.h>
b834b508 38#endif
65dee380 39
c6dc6f63
AP		 40/* feature flags taken from "Intel Processor Identification and the CPUID
41 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
42 * between feature naming conventions, aliases may be added.
43 */
44static const char *feature_name[] = {
45 "fpu", "vme", "de", "pse",
46 "tsc", "msr", "pae", "mce",
47 "cx8", "apic", NULL, "sep",
48 "mtrr", "pge", "mca", "cmov",
49 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
50 NULL, "ds" /* Intel dts */, "acpi", "mmx",
51 "fxsr", "sse", "sse2", "ss",
52 "ht" /* Intel htt */, "tm", "ia64", "pbe",
53};
54static const char *ext_feature_name[] = {
f370be3c 55 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 56 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 57 "tm2", "ssse3", "cid", NULL,
e117f772 58 "fma", "cx16", "xtpr", "pdcm",
434acb81 59 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 60 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 61 "tsc-deadline", "aes", "xsave", "osxsave",
e117f772 62 "avx", NULL, NULL, "hypervisor",
c6dc6f63 63};
3b671a40
EH		 64/* Feature names that are already defined on feature_name[] but are set on
65 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
66 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
67 * if and only if CPU vendor is AMD.
68 */
c6dc6f63 69static const char *ext2_feature_name[] = {
3b671a40
EH		 70 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
71 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
72 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
73 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
74 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
75 "nx|xd", NULL, "mmxext", NULL /* mmx */,
76 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
c6dc6f63
AP		 77};
78static const char *ext3_feature_name[] = {
79 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
80 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 81 "3dnowprefetch", "osvw", "ibs", "xop",
c6dc6f63 82 "skinit", "wdt", NULL, NULL,
e117f772 83 "fma4", NULL, "cvt16", "nodeid_msr",
c6dc6f63
AP		 84 NULL, NULL, NULL, NULL,
85 NULL, NULL, NULL, NULL,
86 NULL, NULL, NULL, NULL,
87};
88
89static const char *kvm_feature_name[] = {
bfee7546 90 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, "kvm_pv_eoi", NULL,
c6dc6f63
AP		 91 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
92 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
93 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
94};
95
296acb64
JR		 96static const char *svm_feature_name[] = {
97 "npt", "lbrv", "svm_lock", "nrip_save",
98 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
99 NULL, NULL, "pause_filter", NULL,
100 "pfthreshold", NULL, NULL, NULL,
101 NULL, NULL, NULL, NULL,
102 NULL, NULL, NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105};
106
c6dc6f63
AP		 107/* collects per-function cpuid data
108 */
109typedef struct model_features_t {
110 uint32_t *guest_feat;
111 uint32_t *host_feat;
112 uint32_t check_feat;
113 const char **flag_names;
114 uint32_t cpuid;
115 } model_features_t;
116
117int check_cpuid = 0;
118int enforce_cpuid = 0;
119
bb44e0d1
JK		 120void host_cpuid(uint32_t function, uint32_t count,
121 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 122{
123#if defined(CONFIG_KVM)
a1fd24af
AL		 124 uint32_t vec[4];
125
126#ifdef __x86_64__
127 asm volatile("cpuid"
128 : "=a"(vec[0]), "=b"(vec[1]),
129 "=c"(vec[2]), "=d"(vec[3])
130 : "0"(function), "c"(count) : "cc");
131#else
132 asm volatile("pusha \n\t"
133 "cpuid \n\t"
134 "mov %%eax, 0(%2) \n\t"
135 "mov %%ebx, 4(%2) \n\t"
136 "mov %%ecx, 8(%2) \n\t"
137 "mov %%edx, 12(%2) \n\t"
138 "popa"
139 : : "a"(function), "c"(count), "S"(vec)
140 : "memory", "cc");
141#endif
142
bdde476a 143 if (eax)
a1fd24af 144 *eax = vec[0];
bdde476a 145 if (ebx)
a1fd24af 146 *ebx = vec[1];
bdde476a 147 if (ecx)
a1fd24af 148 *ecx = vec[2];
bdde476a 149 if (edx)
a1fd24af 150 *edx = vec[3];
bdde476a
AP		 151#endif
152}
c6dc6f63
AP		 153
154#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
155
156/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
157 * a substring. ex if !NULL points to the first char after a substring,
158 * otherwise the string is assumed to sized by a terminating nul.
159 * Return lexical ordering of *s1:*s2.
160 */
161static int sstrcmp(const char *s1, const char *e1, const char *s2,
162 const char *e2)
163{
164 for (;;) {
165 if (!*s1 || !*s2 || *s1 != *s2)
166 return (*s1 - *s2);
167 ++s1, ++s2;
168 if (s1 == e1 && s2 == e2)
169 return (0);
170 else if (s1 == e1)
171 return (*s2);
172 else if (s2 == e2)
173 return (*s1);
174 }
175}
176
177/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
178 * '|' delimited (possibly empty) strings in which case search for a match
179 * within the alternatives proceeds left to right. Return 0 for success,
180 * non-zero otherwise.
181 */
182static int altcmp(const char *s, const char *e, const char *altstr)
183{
184 const char *p, *q;
185
186 for (q = p = altstr; ; ) {
187 while (*p && *p != '|')
188 ++p;
189 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
190 return (0);
191 if (!*p)
192 return (1);
193 else
194 q = ++p;
195 }
196}
197
198/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 199 * *pval and return true, otherwise return false
c6dc6f63 200 */
e41e0fc6
JK		 201static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
202 const char **featureset)
c6dc6f63
AP		 203{
204 uint32_t mask;
205 const char **ppc;
e41e0fc6 206 bool found = false;
c6dc6f63 207
e41e0fc6 208 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 209 if (*ppc && !altcmp(s, e, *ppc)) {
210 *pval |= mask;
e41e0fc6 211 found = true;
c6dc6f63 212 }
e41e0fc6
JK		 213 }
214 return found;
c6dc6f63
AP		 215}
216
217static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
218 uint32_t *ext_features,
219 uint32_t *ext2_features,
220 uint32_t *ext3_features,
296acb64
JR		 221 uint32_t *kvm_features,
222 uint32_t *svm_features)
c6dc6f63
AP		 223{
224 if (!lookup_feature(features, flagname, NULL, feature_name) &&
225 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
226 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
227 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
296acb64
JR		 228 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
229 !lookup_feature(svm_features, flagname, NULL, svm_feature_name))
c6dc6f63
AP		 230 fprintf(stderr, "CPU feature %s not found\n", flagname);
231}
232
233typedef struct x86_def_t {
234 struct x86_def_t *next;
235 const char *name;
236 uint32_t level;
237 uint32_t vendor1, vendor2, vendor3;
238 int family;
239 int model;
240 int stepping;
b862d1fe 241 int tsc_khz;
296acb64
JR		 242 uint32_t features, ext_features, ext2_features, ext3_features;
243 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 244 uint32_t xlevel;
245 char model_id[48];
246 int vendor_override;
b3baa152 247 /* Store the results of Centaur's CPUID instructions */
248 uint32_t ext4_features;
249 uint32_t xlevel2;
13526728
EH		 250 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
251 uint32_t cpuid_7_0_ebx_features;
c6dc6f63
AP		 252} x86_def_t;
253
254#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
255#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
256 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
257#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
258 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
259 CPUID_PSE36 | CPUID_FXSR)
260#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
261#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
262 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
263 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
264 CPUID_PAE | CPUID_SEP | CPUID_APIC)
265
551a2dec
AP		 266#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
267 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
268 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
269 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
270 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 271 /* partly implemented:
272 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
273 CPUID_PSE36 (needed for Solaris) */
274 /* missing:
275 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 276#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
8713f8ff 277 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 278 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 279 /* missing:
280 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 281 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
60032ac0 282#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 283 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
284 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 285 /* missing:
286 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 287#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
288 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 289#define TCG_SVM_FEATURES 0
551a2dec 290
c6dc6f63
AP		 291/* maintains list of cpu model definitions
292 */
293static x86_def_t *x86_defs = {NULL};
294
295/* built-in cpu model definitions (deprecated)
296 */
297static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 298 {
299 .name = "qemu64",
300 .level = 4,
301 .vendor1 = CPUID_VENDOR_AMD_1,
302 .vendor2 = CPUID_VENDOR_AMD_2,
303 .vendor3 = CPUID_VENDOR_AMD_3,
304 .family = 6,
305 .model = 2,
306 .stepping = 3,
307 .features = PPRO_FEATURES |
c6dc6f63 308 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 309 CPUID_PSE36,
310 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
60032ac0 311 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 312 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
313 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
314 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
315 .xlevel = 0x8000000A,
c6dc6f63
AP		 316 },
317 {
318 .name = "phenom",
319 .level = 5,
320 .vendor1 = CPUID_VENDOR_AMD_1,
321 .vendor2 = CPUID_VENDOR_AMD_2,
322 .vendor3 = CPUID_VENDOR_AMD_3,
323 .family = 16,
324 .model = 2,
325 .stepping = 3,
c6dc6f63
AP		 326 .features = PPRO_FEATURES |
327 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 328 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 329 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
330 CPUID_EXT_POPCNT,
60032ac0 331 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 332 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
333 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 334 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 335 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
336 CPUID_EXT3_CR8LEG,
337 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
338 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
339 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
340 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 341 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 342 .xlevel = 0x8000001A,
343 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
344 },
345 {
346 .name = "core2duo",
347 .level = 10,
348 .family = 6,
349 .model = 15,
350 .stepping = 11,
c6dc6f63
AP		 351 .features = PPRO_FEATURES |
352 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 353 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
354 CPUID_HT | CPUID_TM | CPUID_PBE,
355 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
356 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
357 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 358 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
359 .ext3_features = CPUID_EXT3_LAHF_LM,
360 .xlevel = 0x80000008,
361 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
362 },
363 {
364 .name = "kvm64",
365 .level = 5,
366 .vendor1 = CPUID_VENDOR_INTEL_1,
367 .vendor2 = CPUID_VENDOR_INTEL_2,
368 .vendor3 = CPUID_VENDOR_INTEL_3,
369 .family = 15,
370 .model = 6,
371 .stepping = 1,
372 /* Missing: CPUID_VME, CPUID_HT */
373 .features = PPRO_FEATURES |
374 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
375 CPUID_PSE36,
376 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
377 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
378 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
60032ac0 379 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 380 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
381 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
382 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
383 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
384 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
385 .ext3_features = 0,
386 .xlevel = 0x80000008,
387 .model_id = "Common KVM processor"
388 },
c6dc6f63
AP		 389 {
390 .name = "qemu32",
391 .level = 4,
392 .family = 6,
393 .model = 3,
394 .stepping = 3,
395 .features = PPRO_FEATURES,
396 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 397 .xlevel = 0x80000004,
c6dc6f63 398 },
eafaf1e5
AP		 399 {
400 .name = "kvm32",
401 .level = 5,
402 .family = 15,
403 .model = 6,
404 .stepping = 1,
405 .features = PPRO_FEATURES |
406 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
407 .ext_features = CPUID_EXT_SSE3,
60032ac0 408 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
eafaf1e5
AP		 409 .ext3_features = 0,
410 .xlevel = 0x80000008,
411 .model_id = "Common 32-bit KVM processor"
412 },
c6dc6f63
AP		 413 {
414 .name = "coreduo",
415 .level = 10,
416 .family = 6,
417 .model = 14,
418 .stepping = 8,
c6dc6f63 419 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 420 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
421 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
422 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
423 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 424 .ext2_features = CPUID_EXT2_NX,
425 .xlevel = 0x80000008,
426 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
427 },
428 {
429 .name = "486",
58012d66 430 .level = 1,
c6dc6f63
AP		 431 .family = 4,
432 .model = 0,
433 .stepping = 0,
434 .features = I486_FEATURES,
435 .xlevel = 0,
436 },
437 {
438 .name = "pentium",
439 .level = 1,
440 .family = 5,
441 .model = 4,
442 .stepping = 3,
443 .features = PENTIUM_FEATURES,
444 .xlevel = 0,
445 },
446 {
447 .name = "pentium2",
448 .level = 2,
449 .family = 6,
450 .model = 5,
451 .stepping = 2,
452 .features = PENTIUM2_FEATURES,
453 .xlevel = 0,
454 },
455 {
456 .name = "pentium3",
457 .level = 2,
458 .family = 6,
459 .model = 7,
460 .stepping = 3,
461 .features = PENTIUM3_FEATURES,
462 .xlevel = 0,
463 },
464 {
465 .name = "athlon",
466 .level = 2,
467 .vendor1 = CPUID_VENDOR_AMD_1,
468 .vendor2 = CPUID_VENDOR_AMD_2,
469 .vendor3 = CPUID_VENDOR_AMD_3,
470 .family = 6,
471 .model = 2,
472 .stepping = 3,
60032ac0
EH		 473 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
474 CPUID_MCA,
475 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
476 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 477 .xlevel = 0x80000008,
c6dc6f63
AP		 478 },
479 {
480 .name = "n270",
481 /* original is on level 10 */
482 .level = 5,
483 .family = 6,
484 .model = 28,
485 .stepping = 2,
486 .features = PPRO_FEATURES |
8560efed
AJ		 487 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
488 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 489 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 490 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
491 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
60032ac0
EH		 492 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
493 CPUID_EXT2_NX,
8560efed 494 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 495 .xlevel = 0x8000000A,
496 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
497 },
3eca4642
EH		 498 {
499 .name = "Conroe",
500 .level = 2,
501 .vendor1 = CPUID_VENDOR_INTEL_1,
502 .vendor2 = CPUID_VENDOR_INTEL_2,
503 .vendor3 = CPUID_VENDOR_INTEL_3,
504 .family = 6,
505 .model = 2,
506 .stepping = 3,
507 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
508 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
509 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
510 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
511 CPUID_DE | CPUID_FP87,
512 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
513 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
514 .ext3_features = CPUID_EXT3_LAHF_LM,
515 .xlevel = 0x8000000A,
516 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
517 },
518 {
519 .name = "Penryn",
520 .level = 2,
521 .vendor1 = CPUID_VENDOR_INTEL_1,
522 .vendor2 = CPUID_VENDOR_INTEL_2,
523 .vendor3 = CPUID_VENDOR_INTEL_3,
524 .family = 6,
525 .model = 2,
526 .stepping = 3,
527 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
528 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
529 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
530 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
531 CPUID_DE | CPUID_FP87,
532 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
533 CPUID_EXT_SSE3,
534 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
535 .ext3_features = CPUID_EXT3_LAHF_LM,
536 .xlevel = 0x8000000A,
537 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
538 },
539 {
540 .name = "Nehalem",
541 .level = 2,
542 .vendor1 = CPUID_VENDOR_INTEL_1,
543 .vendor2 = CPUID_VENDOR_INTEL_2,
544 .vendor3 = CPUID_VENDOR_INTEL_3,
545 .family = 6,
546 .model = 2,
547 .stepping = 3,
548 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
549 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
550 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
551 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
552 CPUID_DE | CPUID_FP87,
553 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
554 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
555 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
556 .ext3_features = CPUID_EXT3_LAHF_LM,
557 .xlevel = 0x8000000A,
558 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
559 },
560 {
561 .name = "Westmere",
562 .level = 11,
563 .vendor1 = CPUID_VENDOR_INTEL_1,
564 .vendor2 = CPUID_VENDOR_INTEL_2,
565 .vendor3 = CPUID_VENDOR_INTEL_3,
566 .family = 6,
567 .model = 44,
568 .stepping = 1,
569 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
570 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
571 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
572 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
573 CPUID_DE | CPUID_FP87,
574 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
575 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
576 CPUID_EXT_SSE3,
577 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
578 .ext3_features = CPUID_EXT3_LAHF_LM,
579 .xlevel = 0x8000000A,
580 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
581 },
582 {
583 .name = "SandyBridge",
584 .level = 0xd,
585 .vendor1 = CPUID_VENDOR_INTEL_1,
586 .vendor2 = CPUID_VENDOR_INTEL_2,
587 .vendor3 = CPUID_VENDOR_INTEL_3,
588 .family = 6,
589 .model = 42,
590 .stepping = 1,
591 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
592 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
593 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
594 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
595 CPUID_DE | CPUID_FP87,
596 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
597 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
598 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
599 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
600 CPUID_EXT_SSE3,
601 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
602 CPUID_EXT2_SYSCALL,
603 .ext3_features = CPUID_EXT3_LAHF_LM,
604 .xlevel = 0x8000000A,
605 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
606 },
607 {
608 .name = "Opteron_G1",
609 .level = 5,
610 .vendor1 = CPUID_VENDOR_AMD_1,
611 .vendor2 = CPUID_VENDOR_AMD_2,
612 .vendor3 = CPUID_VENDOR_AMD_3,
613 .family = 15,
614 .model = 6,
615 .stepping = 1,
616 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
617 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
618 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
619 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
620 CPUID_DE | CPUID_FP87,
621 .ext_features = CPUID_EXT_SSE3,
622 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
623 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
624 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
625 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
626 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
627 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
628 .xlevel = 0x80000008,
629 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
630 },
631 {
632 .name = "Opteron_G2",
633 .level = 5,
634 .vendor1 = CPUID_VENDOR_AMD_1,
635 .vendor2 = CPUID_VENDOR_AMD_2,
636 .vendor3 = CPUID_VENDOR_AMD_3,
637 .family = 15,
638 .model = 6,
639 .stepping = 1,
640 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
641 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
642 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
643 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
644 CPUID_DE | CPUID_FP87,
645 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
646 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
647 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
648 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
649 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
650 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
651 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
652 CPUID_EXT2_DE | CPUID_EXT2_FPU,
653 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
654 .xlevel = 0x80000008,
655 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
656 },
657 {
658 .name = "Opteron_G3",
659 .level = 5,
660 .vendor1 = CPUID_VENDOR_AMD_1,
661 .vendor2 = CPUID_VENDOR_AMD_2,
662 .vendor3 = CPUID_VENDOR_AMD_3,
663 .family = 15,
664 .model = 6,
665 .stepping = 1,
666 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
667 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
668 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
669 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
670 CPUID_DE | CPUID_FP87,
671 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
672 CPUID_EXT_SSE3,
673 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
674 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
675 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
676 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
677 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
678 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
679 CPUID_EXT2_DE | CPUID_EXT2_FPU,
680 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
681 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
682 .xlevel = 0x80000008,
683 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
684 },
685 {
686 .name = "Opteron_G4",
687 .level = 0xd,
688 .vendor1 = CPUID_VENDOR_AMD_1,
689 .vendor2 = CPUID_VENDOR_AMD_2,
690 .vendor3 = CPUID_VENDOR_AMD_3,
691 .family = 21,
692 .model = 1,
693 .stepping = 2,
694 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
695 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
696 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
697 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
698 CPUID_DE | CPUID_FP87,
699 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
700 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
701 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
702 CPUID_EXT_SSE3,
703 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
704 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
705 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
706 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
707 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
708 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
709 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
710 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
711 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
712 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
713 CPUID_EXT3_LAHF_LM,
714 .xlevel = 0x8000001A,
715 .model_id = "AMD Opteron 62xx class CPU",
716 },
c6dc6f63
AP		 717};
718
719static int cpu_x86_fill_model_id(char *str)
720{
721 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
722 int i;
723
724 for (i = 0; i < 3; i++) {
725 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
726 memcpy(str + i * 16 + 0, &eax, 4);
727 memcpy(str + i * 16 + 4, &ebx, 4);
728 memcpy(str + i * 16 + 8, &ecx, 4);
729 memcpy(str + i * 16 + 12, &edx, 4);
730 }
731 return 0;
732}
733
734static int cpu_x86_fill_host(x86_def_t *x86_cpu_def)
735{
736 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
737
738 x86_cpu_def->name = "host";
739 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
740 x86_cpu_def->level = eax;
741 x86_cpu_def->vendor1 = ebx;
742 x86_cpu_def->vendor2 = edx;
743 x86_cpu_def->vendor3 = ecx;
744
745 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
746 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
747 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
748 x86_cpu_def->stepping = eax & 0x0F;
749 x86_cpu_def->ext_features = ecx;
750 x86_cpu_def->features = edx;
751
13526728
EH		 752 if (kvm_enabled() && x86_cpu_def->level >= 7) {
753 x86_cpu_def->cpuid_7_0_ebx_features = kvm_arch_get_supported_cpuid(kvm_state, 0x7, 0, R_EBX);
754 } else {
755 x86_cpu_def->cpuid_7_0_ebx_features = 0;
756 }
757
c6dc6f63
AP		 758 host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
759 x86_cpu_def->xlevel = eax;
760
761 host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
762 x86_cpu_def->ext2_features = edx;
763 x86_cpu_def->ext3_features = ecx;
764 cpu_x86_fill_model_id(x86_cpu_def->model_id);
765 x86_cpu_def->vendor_override = 0;
766
b3baa152 767 /* Call Centaur's CPUID instruction. */
768 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
769 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
770 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
771 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
772 if (eax >= 0xC0000001) {
773 /* Support VIA max extended level */
774 x86_cpu_def->xlevel2 = eax;
775 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
776 x86_cpu_def->ext4_features = edx;
777 }
778 }
296acb64
JR		 779
780 /*
781 * Every SVM feature requires emulation support in KVM - so we can't just
782 * read the host features here. KVM might even support SVM features not
783 * available on the host hardware. Just set all bits and mask out the
784 * unsupported ones later.
785 */
786 x86_cpu_def->svm_features = -1;
787
c6dc6f63
AP		 788 return 0;
789}
790
791static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
792{
793 int i;
794
795 for (i = 0; i < 32; ++i)
796 if (1 << i & mask) {
797 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
798 " flag '%s' [0x%08x]\n",
799 f->cpuid >> 16, f->cpuid & 0xffff,
800 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
801 break;
802 }
803 return 0;
804}
805
806/* best effort attempt to inform user requested cpu flags aren't making
807 * their way to the guest. Note: ft[].check_feat ideally should be
808 * specified via a guest_def field to suppress report of extraneous flags.
809 */
810static int check_features_against_host(x86_def_t *guest_def)
811{
812 x86_def_t host_def;
813 uint32_t mask;
814 int rv, i;
815 struct model_features_t ft[] = {
816 {&guest_def->features, &host_def.features,
817 ~0, feature_name, 0x00000000},
818 {&guest_def->ext_features, &host_def.ext_features,
819 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
820 {&guest_def->ext2_features, &host_def.ext2_features,
821 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
822 {&guest_def->ext3_features, &host_def.ext3_features,
823 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
824
825 cpu_x86_fill_host(&host_def);
66fe09ee 826 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
c6dc6f63
AP		 827 for (mask = 1; mask; mask <<= 1)
828 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
829 !(*ft[i].host_feat & mask)) {
830 unavailable_host_feature(&ft[i], mask);
831 rv = 1;
832 }
833 return rv;
834}
835
95b8519d
AF		 836static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
837 const char *name, Error **errp)
838{
839 X86CPU *cpu = X86_CPU(obj);
840 CPUX86State *env = &cpu->env;
841 int64_t value;
842
843 value = (env->cpuid_version >> 8) & 0xf;
844 if (value == 0xf) {
845 value += (env->cpuid_version >> 20) & 0xff;
846 }
847 visit_type_int(v, &value, name, errp);
848}
849
71ad61d3
AF		 850static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
851 const char *name, Error **errp)
ed5e1ec3 852{
71ad61d3
AF		 853 X86CPU *cpu = X86_CPU(obj);
854 CPUX86State *env = &cpu->env;
855 const int64_t min = 0;
856 const int64_t max = 0xff + 0xf;
857 int64_t value;
858
859 visit_type_int(v, &value, name, errp);
860 if (error_is_set(errp)) {
861 return;
862 }
863 if (value < min || value > max) {
864 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
865 name ? name : "null", value, min, max);
866 return;
867 }
868
ed5e1ec3 869 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 870 if (value > 0x0f) {
871 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 872 } else {
71ad61d3 873 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 874 }
875}
876
67e30c83
AF		 877static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
878 const char *name, Error **errp)
879{
880 X86CPU *cpu = X86_CPU(obj);
881 CPUX86State *env = &cpu->env;
882 int64_t value;
883
884 value = (env->cpuid_version >> 4) & 0xf;
885 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
886 visit_type_int(v, &value, name, errp);
887}
888
c5291a4f
AF		 889static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
890 const char *name, Error **errp)
b0704cbd 891{
c5291a4f
AF		 892 X86CPU *cpu = X86_CPU(obj);
893 CPUX86State *env = &cpu->env;
894 const int64_t min = 0;
895 const int64_t max = 0xff;
896 int64_t value;
897
898 visit_type_int(v, &value, name, errp);
899 if (error_is_set(errp)) {
900 return;
901 }
902 if (value < min || value > max) {
903 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
904 name ? name : "null", value, min, max);
905 return;
906 }
907
b0704cbd 908 env->cpuid_version &= ~0xf00f0;
c5291a4f 909 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 910}
911
35112e41
AF		 912static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
913 void *opaque, const char *name,
914 Error **errp)
915{
916 X86CPU *cpu = X86_CPU(obj);
917 CPUX86State *env = &cpu->env;
918 int64_t value;
919
920 value = env->cpuid_version & 0xf;
921 visit_type_int(v, &value, name, errp);
922}
923
036e2222
AF		 924static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
925 void *opaque, const char *name,
926 Error **errp)
38c3dc46 927{
036e2222
AF		 928 X86CPU *cpu = X86_CPU(obj);
929 CPUX86State *env = &cpu->env;
930 const int64_t min = 0;
931 const int64_t max = 0xf;
932 int64_t value;
933
934 visit_type_int(v, &value, name, errp);
935 if (error_is_set(errp)) {
936 return;
937 }
938 if (value < min || value > max) {
939 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
940 name ? name : "null", value, min, max);
941 return;
942 }
943
38c3dc46 944 env->cpuid_version &= ~0xf;
036e2222 945 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 946}
947
8e1898bf
AF		 948static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
949 const char *name, Error **errp)
950{
951 X86CPU *cpu = X86_CPU(obj);
8e1898bf 952
fa029887 953 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 954}
955
956static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
957 const char *name, Error **errp)
958{
959 X86CPU *cpu = X86_CPU(obj);
8e1898bf 960
fa029887 961 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 962}
963
16b93aa8
AF		 964static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
965 const char *name, Error **errp)
966{
967 X86CPU *cpu = X86_CPU(obj);
16b93aa8 968
fa029887 969 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 970}
971
972static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
973 const char *name, Error **errp)
974{
975 X86CPU *cpu = X86_CPU(obj);
16b93aa8 976
fa029887 977 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 978}
979
d480e1af
AF		 980static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
981{
982 X86CPU *cpu = X86_CPU(obj);
983 CPUX86State *env = &cpu->env;
984 char *value;
985 int i;
986
987 value = (char *)g_malloc(12 + 1);
988 for (i = 0; i < 4; i++) {
989 value[i ] = env->cpuid_vendor1 >> (8 * i);
990 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
991 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
992 }
993 value[12] = '\0';
994 return value;
995}
996
997static void x86_cpuid_set_vendor(Object *obj, const char *value,
998 Error **errp)
999{
1000 X86CPU *cpu = X86_CPU(obj);
1001 CPUX86State *env = &cpu->env;
1002 int i;
1003
1004 if (strlen(value) != 12) {
1005 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1006 "vendor", value);
1007 return;
1008 }
1009
1010 env->cpuid_vendor1 = 0;
1011 env->cpuid_vendor2 = 0;
1012 env->cpuid_vendor3 = 0;
1013 for (i = 0; i < 4; i++) {
1014 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1015 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1016 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1017 }
1018 env->cpuid_vendor_override = 1;
1019}
1020
63e886eb
AF		 1021static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1022{
1023 X86CPU *cpu = X86_CPU(obj);
1024 CPUX86State *env = &cpu->env;
1025 char *value;
1026 int i;
1027
1028 value = g_malloc(48 + 1);
1029 for (i = 0; i < 48; i++) {
1030 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1031 }
1032 value[48] = '\0';
1033 return value;
1034}
1035
938d4c25
AF		 1036static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1037 Error **errp)
dcce6675 1038{
938d4c25
AF		 1039 X86CPU *cpu = X86_CPU(obj);
1040 CPUX86State *env = &cpu->env;
dcce6675
AF		 1041 int c, len, i;
1042
1043 if (model_id == NULL) {
1044 model_id = "";
1045 }
1046 len = strlen(model_id);
d0a6acf4 1047 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1048 for (i = 0; i < 48; i++) {
1049 if (i >= len) {
1050 c = '\0';
1051 } else {
1052 c = (uint8_t)model_id[i];
1053 }
1054 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1055 }
1056}
1057
89e48965
AF		 1058static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1059 const char *name, Error **errp)
1060{
1061 X86CPU *cpu = X86_CPU(obj);
1062 int64_t value;
1063
1064 value = cpu->env.tsc_khz * 1000;
1065 visit_type_int(v, &value, name, errp);
1066}
1067
1068static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1069 const char *name, Error **errp)
1070{
1071 X86CPU *cpu = X86_CPU(obj);
1072 const int64_t min = 0;
2e84849a 1073 const int64_t max = INT64_MAX;
89e48965
AF		 1074 int64_t value;
1075
1076 visit_type_int(v, &value, name, errp);
1077 if (error_is_set(errp)) {
1078 return;
1079 }
1080 if (value < min || value > max) {
1081 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1082 name ? name : "null", value, min, max);
1083 return;
1084 }
1085
1086 cpu->env.tsc_khz = value / 1000;
1087}
1088
c6dc6f63
AP		 1089static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
1090{
1091 unsigned int i;
1092 x86_def_t *def;
1093
d3c481b3 1094 char *s = g_strdup(cpu_model);
c6dc6f63 1095 char *featurestr, *name = strtok(s, ",");
296acb64
JR		 1096 /* Features to be added*/
1097 uint32_t plus_features = 0, plus_ext_features = 0;
1098 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1099 uint32_t plus_kvm_features = 0, plus_svm_features = 0;
1100 /* Features to be removed */
1101 uint32_t minus_features = 0, minus_ext_features = 0;
1102 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1103 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
c6dc6f63
AP		 1104 uint32_t numvalue;
1105
1106 for (def = x86_defs; def; def = def->next)
04c5b17a 1107 if (name && !strcmp(name, def->name))
c6dc6f63 1108 break;
04c5b17a 1109 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
c6dc6f63
AP		 1110 cpu_x86_fill_host(x86_cpu_def);
1111 } else if (!def) {
1112 goto error;
1113 } else {
1114 memcpy(x86_cpu_def, def, sizeof(*def));
1115 }
1116
ef8621b1
AL		 1117#if defined(CONFIG_KVM)
1118 plus_kvm_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
1119 (1 << KVM_FEATURE_NOP_IO_DELAY) |
1120 (1 << KVM_FEATURE_MMU_OP) |
1121 (1 << KVM_FEATURE_CLOCKSOURCE2) |
1122 (1 << KVM_FEATURE_ASYNC_PF) |
1123 (1 << KVM_FEATURE_STEAL_TIME) |
1124 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
1125#else
1126 plus_kvm_features = 0;
1127#endif
c6dc6f63
AP		 1128
1129 add_flagname_to_bitmaps("hypervisor", &plus_features,
1130 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
296acb64 1131 &plus_kvm_features, &plus_svm_features);
c6dc6f63
AP		 1132
1133 featurestr = strtok(NULL, ",");
1134
1135 while (featurestr) {
1136 char *val;
1137 if (featurestr[0] == '+') {
296acb64
JR		 1138 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1139 &plus_ext_features, &plus_ext2_features,
1140 &plus_ext3_features, &plus_kvm_features,
1141 &plus_svm_features);
c6dc6f63 1142 } else if (featurestr[0] == '-') {
296acb64
JR		 1143 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1144 &minus_ext_features, &minus_ext2_features,
1145 &minus_ext3_features, &minus_kvm_features,
1146 &minus_svm_features);
c6dc6f63
AP		 1147 } else if ((val = strchr(featurestr, '='))) {
1148 *val = 0; val++;
1149 if (!strcmp(featurestr, "family")) {
1150 char *err;
1151 numvalue = strtoul(val, &err, 0);
a88a677f 1152 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 1153 fprintf(stderr, "bad numerical value %s\n", val);
1154 goto error;
1155 }
1156 x86_cpu_def->family = numvalue;
1157 } else if (!strcmp(featurestr, "model")) {
1158 char *err;
1159 numvalue = strtoul(val, &err, 0);
1160 if (!*val || *err || numvalue > 0xff) {
1161 fprintf(stderr, "bad numerical value %s\n", val);
1162 goto error;
1163 }
1164 x86_cpu_def->model = numvalue;
1165 } else if (!strcmp(featurestr, "stepping")) {
1166 char *err;
1167 numvalue = strtoul(val, &err, 0);
1168 if (!*val || *err || numvalue > 0xf) {
1169 fprintf(stderr, "bad numerical value %s\n", val);
1170 goto error;
1171 }
1172 x86_cpu_def->stepping = numvalue ;
1173 } else if (!strcmp(featurestr, "level")) {
1174 char *err;
1175 numvalue = strtoul(val, &err, 0);
1176 if (!*val || *err) {
1177 fprintf(stderr, "bad numerical value %s\n", val);
1178 goto error;
1179 }
1180 x86_cpu_def->level = numvalue;
1181 } else if (!strcmp(featurestr, "xlevel")) {
1182 char *err;
1183 numvalue = strtoul(val, &err, 0);
1184 if (!*val || *err) {
1185 fprintf(stderr, "bad numerical value %s\n", val);
1186 goto error;
1187 }
1188 if (numvalue < 0x80000000) {
2f7a21c4 1189 numvalue += 0x80000000;
c6dc6f63
AP		 1190 }
1191 x86_cpu_def->xlevel = numvalue;
1192 } else if (!strcmp(featurestr, "vendor")) {
1193 if (strlen(val) != 12) {
1194 fprintf(stderr, "vendor string must be 12 chars long\n");
1195 goto error;
1196 }
1197 x86_cpu_def->vendor1 = 0;
1198 x86_cpu_def->vendor2 = 0;
1199 x86_cpu_def->vendor3 = 0;
1200 for(i = 0; i < 4; i++) {
1201 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1202 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1203 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1204 }
1205 x86_cpu_def->vendor_override = 1;
1206 } else if (!strcmp(featurestr, "model_id")) {
1207 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1208 val);
b862d1fe
JR		 1209 } else if (!strcmp(featurestr, "tsc_freq")) {
1210 int64_t tsc_freq;
1211 char *err;
1212
1213 tsc_freq = strtosz_suffix_unit(val, &err,
1214 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1215 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 1216 fprintf(stderr, "bad numerical value %s\n", val);
1217 goto error;
1218 }
1219 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 1220 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1221 char *err;
1222 numvalue = strtoul(val, &err, 0);
1223 if (!*val || *err) {
1224 fprintf(stderr, "bad numerical value %s\n", val);
1225 goto error;
1226 }
1227 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 1228 } else {
1229 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1230 goto error;
1231 }
1232 } else if (!strcmp(featurestr, "check")) {
1233 check_cpuid = 1;
1234 } else if (!strcmp(featurestr, "enforce")) {
1235 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 1236 } else if (!strcmp(featurestr, "hv_relaxed")) {
1237 hyperv_enable_relaxed_timing(true);
1238 } else if (!strcmp(featurestr, "hv_vapic")) {
1239 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 1240 } else {
1241 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1242 goto error;
1243 }
1244 featurestr = strtok(NULL, ",");
1245 }
1246 x86_cpu_def->features |= plus_features;
1247 x86_cpu_def->ext_features |= plus_ext_features;
1248 x86_cpu_def->ext2_features |= plus_ext2_features;
1249 x86_cpu_def->ext3_features |= plus_ext3_features;
1250 x86_cpu_def->kvm_features |= plus_kvm_features;
296acb64 1251 x86_cpu_def->svm_features |= plus_svm_features;
c6dc6f63
AP		 1252 x86_cpu_def->features &= ~minus_features;
1253 x86_cpu_def->ext_features &= ~minus_ext_features;
1254 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1255 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1256 x86_cpu_def->kvm_features &= ~minus_kvm_features;
296acb64 1257 x86_cpu_def->svm_features &= ~minus_svm_features;
c6dc6f63
AP		 1258 if (check_cpuid) {
1259 if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
1260 goto error;
1261 }
d3c481b3 1262 g_free(s);
c6dc6f63
AP		 1263 return 0;
1264
1265error:
d3c481b3 1266 g_free(s);
c6dc6f63
AP		 1267 return -1;
1268}
1269
1270/* generate a composite string into buf of all cpuid names in featureset
1271 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1272 * if flags, suppress names undefined in featureset.
1273 */
1274static void listflags(char *buf, int bufsize, uint32_t fbits,
1275 const char **featureset, uint32_t flags)
1276{
1277 const char **p = &featureset[31];
1278 char *q, *b, bit;
1279 int nc;
1280
1281 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1282 *buf = '\0';
1283 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1284 if (fbits & 1 << bit && (*p || !flags)) {
1285 if (*p)
1286 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1287 else
1288 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1289 if (bufsize <= nc) {
1290 if (b) {
1291 memcpy(b, "...", sizeof("..."));
1292 }
1293 return;
1294 }
1295 q += nc;
1296 bufsize -= nc;
1297 }
1298}
1299
e916cbf8
PM		 1300/* generate CPU information. */
1301void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1302{
c6dc6f63
AP		 1303 x86_def_t *def;
1304 char buf[256];
1305
c6dc6f63 1306 for (def = x86_defs; def; def = def->next) {
c04321b3 1307 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1308 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1309 }
ed2c54d4
AP		 1310 if (kvm_enabled()) {
1311 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1312 }
6cdf8854
PM		 1313 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1314 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
4a19e505 1315 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1316 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
4a19e505 1317 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1318 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
4a19e505 1319 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1320 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
4a19e505 1321 (*cpu_fprintf)(f, " %s\n", buf);
c6dc6f63
AP		 1322}
1323
76b64a7a 1324CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1325{
1326 CpuDefinitionInfoList *cpu_list = NULL;
1327 x86_def_t *def;
1328
1329 for (def = x86_defs; def; def = def->next) {
1330 CpuDefinitionInfoList *entry;
1331 CpuDefinitionInfo *info;
1332
1333 info = g_malloc0(sizeof(*info));
1334 info->name = g_strdup(def->name);
1335
1336 entry = g_malloc0(sizeof(*entry));
1337 entry->value = info;
1338 entry->next = cpu_list;
1339 cpu_list = entry;
1340 }
1341
1342 return cpu_list;
1343}
1344
61dcd775 1345int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 1346{
61dcd775 1347 CPUX86State *env = &cpu->env;
c6dc6f63 1348 x86_def_t def1, *def = &def1;
71ad61d3 1349 Error *error = NULL;
c6dc6f63 1350
db0ad1ba
JR		 1351 memset(def, 0, sizeof(*def));
1352
c6dc6f63
AP		 1353 if (cpu_x86_find_by_name(def, cpu_model) < 0)
1354 return -1;
1355 if (def->vendor1) {
1356 env->cpuid_vendor1 = def->vendor1;
1357 env->cpuid_vendor2 = def->vendor2;
1358 env->cpuid_vendor3 = def->vendor3;
1359 } else {
1360 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1361 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1362 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1363 }
1364 env->cpuid_vendor_override = def->vendor_override;
8e1898bf 1365 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
71ad61d3 1366 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 1367 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
036e2222 1368 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
c6dc6f63 1369 env->cpuid_features = def->features;
c6dc6f63
AP		 1370 env->cpuid_ext_features = def->ext_features;
1371 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 1372 env->cpuid_ext3_features = def->ext3_features;
16b93aa8 1373 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
c6dc6f63 1374 env->cpuid_kvm_features = def->kvm_features;
296acb64 1375 env->cpuid_svm_features = def->svm_features;
b3baa152 1376 env->cpuid_ext4_features = def->ext4_features;
13526728 1377 env->cpuid_7_0_ebx = def->cpuid_7_0_ebx_features;
b3baa152 1378 env->cpuid_xlevel2 = def->xlevel2;
89e48965
AF		 1379 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1380 "tsc-frequency", &error);
3b671a40
EH		 1381
1382 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
1383 * CPUID[1].EDX.
1384 */
1385 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
1386 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
1387 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
1388 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
1389 env->cpuid_ext2_features |= (def->features & CPUID_EXT2_AMD_ALIASES);
1390 }
1391
551a2dec
AP		 1392 if (!kvm_enabled()) {
1393 env->cpuid_features &= TCG_FEATURES;
1394 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1395 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1396#ifdef TARGET_X86_64
1397 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1398#endif
1399 );
1400 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
296acb64 1401 env->cpuid_svm_features &= TCG_SVM_FEATURES;
551a2dec 1402 }
938d4c25 1403 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
71ad61d3
AF		 1404 if (error_is_set(&error)) {
1405 error_free(error);
1406 return -1;
1407 }
c6dc6f63
AP		 1408 return 0;
1409}
1410
1411#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1412
0e26b7b8
BS		 1413void cpu_clear_apic_feature(CPUX86State *env)
1414{
1415 env->cpuid_features &= ~CPUID_APIC;
1416}
1417
c6dc6f63
AP		 1418#endif /* !CONFIG_USER_ONLY */
1419
c04321b3 1420/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 1421 */
1422void x86_cpudef_setup(void)
1423{
93bfef4c
CV		 1424 int i, j;
1425 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1426
1427 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
bc3e1291
EH		 1428 x86_def_t *def = &builtin_x86_defs[i];
1429 def->next = x86_defs;
93bfef4c
CV		 1430
1431 /* Look for specific "cpudef" models that */
09faecf2 1432 /* have the QEMU version in .model_id */
93bfef4c 1433 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 1434 if (strcmp(model_with_versions[j], def->name) == 0) {
1435 pstrcpy(def->model_id, sizeof(def->model_id),
1436 "QEMU Virtual CPU version ");
1437 pstrcat(def->model_id, sizeof(def->model_id),
1438 qemu_get_version());
93bfef4c
CV		 1439 break;
1440 }
1441 }
1442
bc3e1291 1443 x86_defs = def;
c6dc6f63 1444 }
c6dc6f63
AP		 1445}
1446
c6dc6f63
AP		 1447static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1448 uint32_t *ecx, uint32_t *edx)
1449{
1450 *ebx = env->cpuid_vendor1;
1451 *edx = env->cpuid_vendor2;
1452 *ecx = env->cpuid_vendor3;
1453
1454 /* sysenter isn't supported on compatibility mode on AMD, syscall
1455 * isn't supported in compatibility mode on Intel.
1456 * Normally we advertise the actual cpu vendor, but you can override
1457 * this if you want to use KVM's sysenter/syscall emulation
1458 * in compatibility mode and when doing cross vendor migration
1459 */
89354998 1460 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1461 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1462 }
1463}
1464
1465void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1466 uint32_t *eax, uint32_t *ebx,
1467 uint32_t *ecx, uint32_t *edx)
1468{
1469 /* test if maximum index reached */
1470 if (index & 0x80000000) {
b3baa152 1471 if (index > env->cpuid_xlevel) {
1472 if (env->cpuid_xlevel2 > 0) {
1473 /* Handle the Centaur's CPUID instruction. */
1474 if (index > env->cpuid_xlevel2) {
1475 index = env->cpuid_xlevel2;
1476 } else if (index < 0xC0000000) {
1477 index = env->cpuid_xlevel;
1478 }
1479 } else {
1480 index = env->cpuid_xlevel;
1481 }
1482 }
c6dc6f63
AP		 1483 } else {
1484 if (index > env->cpuid_level)
1485 index = env->cpuid_level;
1486 }
1487
1488 switch(index) {
1489 case 0:
1490 *eax = env->cpuid_level;
1491 get_cpuid_vendor(env, ebx, ecx, edx);
1492 break;
1493 case 1:
1494 *eax = env->cpuid_version;
1495 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1496 *ecx = env->cpuid_ext_features;
1497 *edx = env->cpuid_features;
1498 if (env->nr_cores * env->nr_threads > 1) {
1499 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1500 *edx |= 1 << 28; /* HTT bit */
1501 }
1502 break;
1503 case 2:
1504 /* cache info: needed for Pentium Pro compatibility */
1505 *eax = 1;
1506 *ebx = 0;
1507 *ecx = 0;
1508 *edx = 0x2c307d;
1509 break;
1510 case 4:
1511 /* cache info: needed for Core compatibility */
1512 if (env->nr_cores > 1) {
2f7a21c4 1513 *eax = (env->nr_cores - 1) << 26;
c6dc6f63 1514 } else {
2f7a21c4 1515 *eax = 0;
c6dc6f63
AP		 1516 }
1517 switch (count) {
1518 case 0: /* L1 dcache info */
1519 *eax |= 0x0000121;
1520 *ebx = 0x1c0003f;
1521 *ecx = 0x000003f;
1522 *edx = 0x0000001;
1523 break;
1524 case 1: /* L1 icache info */
1525 *eax |= 0x0000122;
1526 *ebx = 0x1c0003f;
1527 *ecx = 0x000003f;
1528 *edx = 0x0000001;
1529 break;
1530 case 2: /* L2 cache info */
1531 *eax |= 0x0000143;
1532 if (env->nr_threads > 1) {
1533 *eax |= (env->nr_threads - 1) << 14;
1534 }
1535 *ebx = 0x3c0003f;
1536 *ecx = 0x0000fff;
1537 *edx = 0x0000001;
1538 break;
1539 default: /* end of info */
1540 *eax = 0;
1541 *ebx = 0;
1542 *ecx = 0;
1543 *edx = 0;
1544 break;
1545 }
1546 break;
1547 case 5:
1548 /* mwait info: needed for Core compatibility */
1549 *eax = 0; /* Smallest monitor-line size in bytes */
1550 *ebx = 0; /* Largest monitor-line size in bytes */
1551 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1552 *edx = 0;
1553 break;
1554 case 6:
1555 /* Thermal and Power Leaf */
1556 *eax = 0;
1557 *ebx = 0;
1558 *ecx = 0;
1559 *edx = 0;
1560 break;
f7911686 1561 case 7:
13526728
EH		 1562 /* Structured Extended Feature Flags Enumeration Leaf */
1563 if (count == 0) {
1564 *eax = 0; /* Maximum ECX value for sub-leaves */
1565 *ebx = env->cpuid_7_0_ebx; /* Feature flags */
1566 *ecx = 0; /* Reserved */
1567 *edx = 0; /* Reserved */
f7911686
YW		 1568 } else {
1569 *eax = 0;
1570 *ebx = 0;
1571 *ecx = 0;
1572 *edx = 0;
1573 }
1574 break;
c6dc6f63
AP		 1575 case 9:
1576 /* Direct Cache Access Information Leaf */
1577 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1578 *ebx = 0;
1579 *ecx = 0;
1580 *edx = 0;
1581 break;
1582 case 0xA:
1583 /* Architectural Performance Monitoring Leaf */
a0fa8208
GN		 1584 if (kvm_enabled()) {
1585 KVMState *s = env->kvm_state;
1586
1587 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1588 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1589 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1590 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1591 } else {
1592 *eax = 0;
1593 *ebx = 0;
1594 *ecx = 0;
1595 *edx = 0;
1596 }
c6dc6f63 1597 break;
51e49430
SY		 1598 case 0xD:
1599 /* Processor Extended State */
1600 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1601 *eax = 0;
1602 *ebx = 0;
1603 *ecx = 0;
1604 *edx = 0;
1605 break;
1606 }
1607 if (kvm_enabled()) {
ba9bc59e
JK		 1608 KVMState *s = env->kvm_state;
1609
1610 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1611 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1612 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1613 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1614 } else {
1615 *eax = 0;
1616 *ebx = 0;
1617 *ecx = 0;
1618 *edx = 0;
1619 }
1620 break;
c6dc6f63
AP		 1621 case 0x80000000:
1622 *eax = env->cpuid_xlevel;
1623 *ebx = env->cpuid_vendor1;
1624 *edx = env->cpuid_vendor2;
1625 *ecx = env->cpuid_vendor3;
1626 break;
1627 case 0x80000001:
1628 *eax = env->cpuid_version;
1629 *ebx = 0;
1630 *ecx = env->cpuid_ext3_features;
1631 *edx = env->cpuid_ext2_features;
1632
1633 /* The Linux kernel checks for the CMPLegacy bit and
1634 * discards multiple thread information if it is set.
1635 * So dont set it here for Intel to make Linux guests happy.
1636 */
1637 if (env->nr_cores * env->nr_threads > 1) {
1638 uint32_t tebx, tecx, tedx;
1639 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1640 if (tebx != CPUID_VENDOR_INTEL_1 ||
1641 tedx != CPUID_VENDOR_INTEL_2 ||
1642 tecx != CPUID_VENDOR_INTEL_3) {
1643 *ecx |= 1 << 1; /* CmpLegacy bit */
1644 }
1645 }
c6dc6f63
AP		 1646 break;
1647 case 0x80000002:
1648 case 0x80000003:
1649 case 0x80000004:
1650 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1651 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1652 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1653 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1654 break;
1655 case 0x80000005:
1656 /* cache info (L1 cache) */
1657 *eax = 0x01ff01ff;
1658 *ebx = 0x01ff01ff;
1659 *ecx = 0x40020140;
1660 *edx = 0x40020140;
1661 break;
1662 case 0x80000006:
1663 /* cache info (L2 cache) */
1664 *eax = 0;
1665 *ebx = 0x42004200;
1666 *ecx = 0x02008140;
1667 *edx = 0;
1668 break;
1669 case 0x80000008:
1670 /* virtual & phys address size in low 2 bytes. */
1671/* XXX: This value must match the one used in the MMU code. */
1672 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1673 /* 64 bit processor */
1674/* XXX: The physical address space is limited to 42 bits in exec.c. */
1675 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1676 } else {
1677 if (env->cpuid_features & CPUID_PSE36)
1678 *eax = 0x00000024; /* 36 bits physical */
1679 else
1680 *eax = 0x00000020; /* 32 bits physical */
1681 }
1682 *ebx = 0;
1683 *ecx = 0;
1684 *edx = 0;
1685 if (env->nr_cores * env->nr_threads > 1) {
1686 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1687 }
1688 break;
1689 case 0x8000000A:
296acb64
JR		 1690 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1691 *eax = 0x00000001; /* SVM Revision */
1692 *ebx = 0x00000010; /* nr of ASIDs */
1693 *ecx = 0;
1694 *edx = env->cpuid_svm_features; /* optional features */
1695 } else {
1696 *eax = 0;
1697 *ebx = 0;
1698 *ecx = 0;
1699 *edx = 0;
1700 }
c6dc6f63 1701 break;
b3baa152 1702 case 0xC0000000:
1703 *eax = env->cpuid_xlevel2;
1704 *ebx = 0;
1705 *ecx = 0;
1706 *edx = 0;
1707 break;
1708 case 0xC0000001:
1709 /* Support for VIA CPU's CPUID instruction */
1710 *eax = env->cpuid_version;
1711 *ebx = 0;
1712 *ecx = 0;
1713 *edx = env->cpuid_ext4_features;
1714 break;
1715 case 0xC0000002:
1716 case 0xC0000003:
1717 case 0xC0000004:
1718 /* Reserved for the future, and now filled with zero */
1719 *eax = 0;
1720 *ebx = 0;
1721 *ecx = 0;
1722 *edx = 0;
1723 break;
c6dc6f63
AP		 1724 default:
1725 /* reserved values: zero */
1726 *eax = 0;
1727 *ebx = 0;
1728 *ecx = 0;
1729 *edx = 0;
1730 break;
1731 }
1732}
5fd2087a
AF		 1733
1734/* CPUClass::reset() */
1735static void x86_cpu_reset(CPUState *s)
1736{
1737 X86CPU *cpu = X86_CPU(s);
1738 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1739 CPUX86State *env = &cpu->env;
c1958aea
AF		 1740 int i;
1741
1742 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1743 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1744 log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
1745 }
5fd2087a
AF		 1746
1747 xcc->parent_reset(s);
1748
c1958aea
AF		 1749
1750 memset(env, 0, offsetof(CPUX86State, breakpoints));
1751
1752 tlb_flush(env, 1);
1753
1754 env->old_exception = -1;
1755
1756 /* init to reset state */
1757
1758#ifdef CONFIG_SOFTMMU
1759 env->hflags |= HF_SOFTMMU_MASK;
1760#endif
1761 env->hflags2 |= HF2_GIF_MASK;
1762
1763 cpu_x86_update_cr0(env, 0x60000010);
1764 env->a20_mask = ~0x0;
1765 env->smbase = 0x30000;
1766
1767 env->idt.limit = 0xffff;
1768 env->gdt.limit = 0xffff;
1769 env->ldt.limit = 0xffff;
1770 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1771 env->tr.limit = 0xffff;
1772 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1773
1774 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1775 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1776 DESC_R_MASK | DESC_A_MASK);
1777 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1778 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1779 DESC_A_MASK);
1780 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1781 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1782 DESC_A_MASK);
1783 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1784 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1785 DESC_A_MASK);
1786 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1787 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1788 DESC_A_MASK);
1789 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1790 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1791 DESC_A_MASK);
1792
1793 env->eip = 0xfff0;
1794 env->regs[R_EDX] = env->cpuid_version;
1795
1796 env->eflags = 0x2;
1797
1798 /* FPU init */
1799 for (i = 0; i < 8; i++) {
1800 env->fptags[i] = 1;
1801 }
1802 env->fpuc = 0x37f;
1803
1804 env->mxcsr = 0x1f80;
1805
1806 env->pat = 0x0007040600070406ULL;
1807 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1808
1809 memset(env->dr, 0, sizeof(env->dr));
1810 env->dr[6] = DR6_FIXED_1;
1811 env->dr[7] = DR7_FIXED_1;
1812 cpu_breakpoint_remove_all(env, BP_CPU);
1813 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM		 1814
1815#if !defined(CONFIG_USER_ONLY)
1816 /* We hard-wire the BSP to the first CPU. */
1817 if (env->cpu_index == 0) {
1818 apic_designate_bsp(env->apic_state);
1819 }
1820
1821 env->halted = !cpu_is_bsp(cpu);
1822#endif
5fd2087a
AF		 1823}
1824
dd673288
IM		 1825#ifndef CONFIG_USER_ONLY
1826bool cpu_is_bsp(X86CPU *cpu)
1827{
1828 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
1829}
65dee380
IM		 1830
1831/* TODO: remove me, when reset over QOM tree is implemented */
1832static void x86_cpu_machine_reset_cb(void *opaque)
1833{
1834 X86CPU *cpu = opaque;
1835 cpu_reset(CPU(cpu));
1836}
dd673288
IM		 1837#endif
1838
de024815
AF		 1839static void mce_init(X86CPU *cpu)
1840{
1841 CPUX86State *cenv = &cpu->env;
1842 unsigned int bank;
1843
1844 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
1845 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
1846 (CPUID_MCE | CPUID_MCA)) {
1847 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
1848 cenv->mcg_ctl = ~(uint64_t)0;
1849 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
1850 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
1851 }
1852 }
1853}
1854
7a059953
AF		 1855void x86_cpu_realize(Object *obj, Error **errp)
1856{
1857 X86CPU *cpu = X86_CPU(obj);
1858
65dee380
IM		 1859#ifndef CONFIG_USER_ONLY
1860 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
1861#endif
1862
7a059953
AF		 1863 mce_init(cpu);
1864 qemu_init_vcpu(&cpu->env);
65dee380 1865 cpu_reset(CPU(cpu));
7a059953
AF		 1866}
1867
de024815
AF		 1868static void x86_cpu_initfn(Object *obj)
1869{
1870 X86CPU *cpu = X86_CPU(obj);
1871 CPUX86State *env = &cpu->env;
d65e9815 1872 static int inited;
de024815
AF		 1873
1874 cpu_exec_init(env);
71ad61d3
AF		 1875
1876 object_property_add(obj, "family", "int",
95b8519d 1877 x86_cpuid_version_get_family,
71ad61d3 1878 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 1879 object_property_add(obj, "model", "int",
67e30c83 1880 x86_cpuid_version_get_model,
c5291a4f 1881 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 1882 object_property_add(obj, "stepping", "int",
35112e41 1883 x86_cpuid_version_get_stepping,
036e2222 1884 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 1885 object_property_add(obj, "level", "int",
1886 x86_cpuid_get_level,
1887 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 1888 object_property_add(obj, "xlevel", "int",
1889 x86_cpuid_get_xlevel,
1890 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 1891 object_property_add_str(obj, "vendor",
1892 x86_cpuid_get_vendor,
1893 x86_cpuid_set_vendor, NULL);
938d4c25 1894 object_property_add_str(obj, "model-id",
63e886eb 1895 x86_cpuid_get_model_id,
938d4c25 1896 x86_cpuid_set_model_id, NULL);
89e48965
AF		 1897 object_property_add(obj, "tsc-frequency", "int",
1898 x86_cpuid_get_tsc_freq,
1899 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
71ad61d3 1900
de024815 1901 env->cpuid_apic_id = env->cpu_index;
d65e9815
IM		 1902
1903 /* init various static tables used in TCG mode */
1904 if (tcg_enabled() && !inited) {
1905 inited = 1;
1906 optimize_flags_init();
1907#ifndef CONFIG_USER_ONLY
1908 cpu_set_debug_excp_handler(breakpoint_handler);
1909#endif
1910 }
de024815
AF		 1911}
1912
5fd2087a
AF		 1913static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
1914{
1915 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1916 CPUClass *cc = CPU_CLASS(oc);
1917
1918 xcc->parent_reset = cc->reset;
1919 cc->reset = x86_cpu_reset;
1920}
1921
1922static const TypeInfo x86_cpu_type_info = {
1923 .name = TYPE_X86_CPU,
1924 .parent = TYPE_CPU,
1925 .instance_size = sizeof(X86CPU),
de024815 1926 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 1927 .abstract = false,
1928 .class_size = sizeof(X86CPUClass),
1929 .class_init = x86_cpu_common_class_init,
1930};
1931
1932static void x86_cpu_register_types(void)
1933{
1934 type_register_static(&x86_cpu_type_info);
1935}
1936
1937type_init(x86_cpu_register_types)
Qemu copy for testing