]> git.proxmox.com Git - qemu.git/blame - target-i386/cpu.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i386: cpu: replace EXT2_FEATURE_MASK with CPUID_EXT2_AMD_ALIASES
[qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
25#include "kvm.h"
26
27#include "qemu-option.h"
28#include "qemu-config.h"
29
71ad61d3 30#include "qapi/qapi-visit-core.h"
76b64a7a 31#include "arch_init.h"
71ad61d3 32
28f52cc0
VR		 33#include "hyperv.h"
34
65dee380 35#include "hw/hw.h"
b834b508 36#if defined(CONFIG_KVM)
ef8621b1 37#include <linux/kvm_para.h>
b834b508 38#endif
65dee380 39
c6dc6f63
AP		 40/* feature flags taken from "Intel Processor Identification and the CPUID
41 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
42 * between feature naming conventions, aliases may be added.
43 */
44static const char *feature_name[] = {
45 "fpu", "vme", "de", "pse",
46 "tsc", "msr", "pae", "mce",
47 "cx8", "apic", NULL, "sep",
48 "mtrr", "pge", "mca", "cmov",
49 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
50 NULL, "ds" /* Intel dts */, "acpi", "mmx",
51 "fxsr", "sse", "sse2", "ss",
52 "ht" /* Intel htt */, "tm", "ia64", "pbe",
53};
54static const char *ext_feature_name[] = {
f370be3c 55 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 56 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 57 "tm2", "ssse3", "cid", NULL,
e117f772 58 "fma", "cx16", "xtpr", "pdcm",
434acb81 59 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 60 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 61 "tsc-deadline", "aes", "xsave", "osxsave",
e117f772 62 "avx", NULL, NULL, "hypervisor",
c6dc6f63
AP		 63};
64static const char *ext2_feature_name[] = {
65 "fpu", "vme", "de", "pse",
66 "tsc", "msr", "pae", "mce",
67 "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",
68 "mtrr", "pge", "mca", "cmov",
69 "pat", "pse36", NULL, NULL /* Linux mp */,
3ac8ebfe 70 "nx|xd", NULL, "mmxext", "mmx",
f370be3c 71 "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
3ac8ebfe 72 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 73};
74static const char *ext3_feature_name[] = {
75 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
76 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 77 "3dnowprefetch", "osvw", "ibs", "xop",
c6dc6f63 78 "skinit", "wdt", NULL, NULL,
e117f772 79 "fma4", NULL, "cvt16", "nodeid_msr",
c6dc6f63
AP		 80 NULL, NULL, NULL, NULL,
81 NULL, NULL, NULL, NULL,
82 NULL, NULL, NULL, NULL,
83};
84
85static const char *kvm_feature_name[] = {
bfee7546 86 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, "kvm_pv_eoi", NULL,
c6dc6f63
AP		 87 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
88 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
89 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
90};
91
296acb64
JR		 92static const char *svm_feature_name[] = {
93 "npt", "lbrv", "svm_lock", "nrip_save",
94 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
95 NULL, NULL, "pause_filter", NULL,
96 "pfthreshold", NULL, NULL, NULL,
97 NULL, NULL, NULL, NULL,
98 NULL, NULL, NULL, NULL,
99 NULL, NULL, NULL, NULL,
100 NULL, NULL, NULL, NULL,
101};
102
c6dc6f63
AP		 103/* collects per-function cpuid data
104 */
105typedef struct model_features_t {
106 uint32_t *guest_feat;
107 uint32_t *host_feat;
108 uint32_t check_feat;
109 const char **flag_names;
110 uint32_t cpuid;
111 } model_features_t;
112
113int check_cpuid = 0;
114int enforce_cpuid = 0;
115
bb44e0d1
JK		 116void host_cpuid(uint32_t function, uint32_t count,
117 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 118{
119#if defined(CONFIG_KVM)
a1fd24af
AL		 120 uint32_t vec[4];
121
122#ifdef __x86_64__
123 asm volatile("cpuid"
124 : "=a"(vec[0]), "=b"(vec[1]),
125 "=c"(vec[2]), "=d"(vec[3])
126 : "0"(function), "c"(count) : "cc");
127#else
128 asm volatile("pusha \n\t"
129 "cpuid \n\t"
130 "mov %%eax, 0(%2) \n\t"
131 "mov %%ebx, 4(%2) \n\t"
132 "mov %%ecx, 8(%2) \n\t"
133 "mov %%edx, 12(%2) \n\t"
134 "popa"
135 : : "a"(function), "c"(count), "S"(vec)
136 : "memory", "cc");
137#endif
138
bdde476a 139 if (eax)
a1fd24af 140 *eax = vec[0];
bdde476a 141 if (ebx)
a1fd24af 142 *ebx = vec[1];
bdde476a 143 if (ecx)
a1fd24af 144 *ecx = vec[2];
bdde476a 145 if (edx)
a1fd24af 146 *edx = vec[3];
bdde476a
AP		 147#endif
148}
c6dc6f63
AP		 149
150#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
151
152/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
153 * a substring. ex if !NULL points to the first char after a substring,
154 * otherwise the string is assumed to sized by a terminating nul.
155 * Return lexical ordering of *s1:*s2.
156 */
157static int sstrcmp(const char *s1, const char *e1, const char *s2,
158 const char *e2)
159{
160 for (;;) {
161 if (!*s1 || !*s2 || *s1 != *s2)
162 return (*s1 - *s2);
163 ++s1, ++s2;
164 if (s1 == e1 && s2 == e2)
165 return (0);
166 else if (s1 == e1)
167 return (*s2);
168 else if (s2 == e2)
169 return (*s1);
170 }
171}
172
173/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
174 * '|' delimited (possibly empty) strings in which case search for a match
175 * within the alternatives proceeds left to right. Return 0 for success,
176 * non-zero otherwise.
177 */
178static int altcmp(const char *s, const char *e, const char *altstr)
179{
180 const char *p, *q;
181
182 for (q = p = altstr; ; ) {
183 while (*p && *p != '|')
184 ++p;
185 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
186 return (0);
187 if (!*p)
188 return (1);
189 else
190 q = ++p;
191 }
192}
193
194/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 195 * *pval and return true, otherwise return false
c6dc6f63 196 */
e41e0fc6
JK		 197static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
198 const char **featureset)
c6dc6f63
AP		 199{
200 uint32_t mask;
201 const char **ppc;
e41e0fc6 202 bool found = false;
c6dc6f63 203
e41e0fc6 204 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 205 if (*ppc && !altcmp(s, e, *ppc)) {
206 *pval |= mask;
e41e0fc6 207 found = true;
c6dc6f63 208 }
e41e0fc6
JK		 209 }
210 return found;
c6dc6f63
AP		 211}
212
213static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
214 uint32_t *ext_features,
215 uint32_t *ext2_features,
216 uint32_t *ext3_features,
296acb64
JR		 217 uint32_t *kvm_features,
218 uint32_t *svm_features)
c6dc6f63
AP		 219{
220 if (!lookup_feature(features, flagname, NULL, feature_name) &&
221 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
222 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
223 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
296acb64
JR		 224 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
225 !lookup_feature(svm_features, flagname, NULL, svm_feature_name))
c6dc6f63
AP		 226 fprintf(stderr, "CPU feature %s not found\n", flagname);
227}
228
229typedef struct x86_def_t {
230 struct x86_def_t *next;
231 const char *name;
232 uint32_t level;
233 uint32_t vendor1, vendor2, vendor3;
234 int family;
235 int model;
236 int stepping;
b862d1fe 237 int tsc_khz;
296acb64
JR		 238 uint32_t features, ext_features, ext2_features, ext3_features;
239 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 240 uint32_t xlevel;
241 char model_id[48];
242 int vendor_override;
b3baa152 243 /* Store the results of Centaur's CPUID instructions */
244 uint32_t ext4_features;
245 uint32_t xlevel2;
13526728
EH		 246 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
247 uint32_t cpuid_7_0_ebx_features;
c6dc6f63
AP		 248} x86_def_t;
249
250#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
251#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
252 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
253#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
254 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
255 CPUID_PSE36 | CPUID_FXSR)
256#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
257#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
258 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
259 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
260 CPUID_PAE | CPUID_SEP | CPUID_APIC)
261
551a2dec
AP		 262#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
263 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
264 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
265 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
266 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 267 /* partly implemented:
268 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
269 CPUID_PSE36 (needed for Solaris) */
270 /* missing:
271 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 272#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
8713f8ff 273 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 274 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 275 /* missing:
276 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 277 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
60032ac0 278#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 279 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
280 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 281 /* missing:
282 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 283#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
284 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 285#define TCG_SVM_FEATURES 0
551a2dec 286
c6dc6f63
AP		 287/* maintains list of cpu model definitions
288 */
289static x86_def_t *x86_defs = {NULL};
290
291/* built-in cpu model definitions (deprecated)
292 */
293static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 294 {
295 .name = "qemu64",
296 .level = 4,
297 .vendor1 = CPUID_VENDOR_AMD_1,
298 .vendor2 = CPUID_VENDOR_AMD_2,
299 .vendor3 = CPUID_VENDOR_AMD_3,
300 .family = 6,
301 .model = 2,
302 .stepping = 3,
303 .features = PPRO_FEATURES |
c6dc6f63 304 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 305 CPUID_PSE36,
306 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
60032ac0 307 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 308 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
309 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
310 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
311 .xlevel = 0x8000000A,
c6dc6f63
AP		 312 },
313 {
314 .name = "phenom",
315 .level = 5,
316 .vendor1 = CPUID_VENDOR_AMD_1,
317 .vendor2 = CPUID_VENDOR_AMD_2,
318 .vendor3 = CPUID_VENDOR_AMD_3,
319 .family = 16,
320 .model = 2,
321 .stepping = 3,
c6dc6f63
AP		 322 .features = PPRO_FEATURES |
323 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 324 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 325 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
326 CPUID_EXT_POPCNT,
60032ac0 327 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 328 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
329 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 330 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 331 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
332 CPUID_EXT3_CR8LEG,
333 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
334 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
335 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
336 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 337 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 338 .xlevel = 0x8000001A,
339 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
340 },
341 {
342 .name = "core2duo",
343 .level = 10,
344 .family = 6,
345 .model = 15,
346 .stepping = 11,
c6dc6f63
AP		 347 .features = PPRO_FEATURES |
348 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 349 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
350 CPUID_HT | CPUID_TM | CPUID_PBE,
351 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
352 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
353 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 354 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
355 .ext3_features = CPUID_EXT3_LAHF_LM,
356 .xlevel = 0x80000008,
357 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
358 },
359 {
360 .name = "kvm64",
361 .level = 5,
362 .vendor1 = CPUID_VENDOR_INTEL_1,
363 .vendor2 = CPUID_VENDOR_INTEL_2,
364 .vendor3 = CPUID_VENDOR_INTEL_3,
365 .family = 15,
366 .model = 6,
367 .stepping = 1,
368 /* Missing: CPUID_VME, CPUID_HT */
369 .features = PPRO_FEATURES |
370 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
371 CPUID_PSE36,
372 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
373 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
374 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
60032ac0 375 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 376 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
377 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
378 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
379 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
380 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
381 .ext3_features = 0,
382 .xlevel = 0x80000008,
383 .model_id = "Common KVM processor"
384 },
c6dc6f63
AP		 385 {
386 .name = "qemu32",
387 .level = 4,
388 .family = 6,
389 .model = 3,
390 .stepping = 3,
391 .features = PPRO_FEATURES,
392 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 393 .xlevel = 0x80000004,
c6dc6f63 394 },
eafaf1e5
AP		 395 {
396 .name = "kvm32",
397 .level = 5,
398 .family = 15,
399 .model = 6,
400 .stepping = 1,
401 .features = PPRO_FEATURES |
402 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
403 .ext_features = CPUID_EXT_SSE3,
60032ac0 404 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
eafaf1e5
AP		 405 .ext3_features = 0,
406 .xlevel = 0x80000008,
407 .model_id = "Common 32-bit KVM processor"
408 },
c6dc6f63
AP		 409 {
410 .name = "coreduo",
411 .level = 10,
412 .family = 6,
413 .model = 14,
414 .stepping = 8,
c6dc6f63 415 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 416 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
417 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
418 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
419 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 420 .ext2_features = CPUID_EXT2_NX,
421 .xlevel = 0x80000008,
422 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
423 },
424 {
425 .name = "486",
58012d66 426 .level = 1,
c6dc6f63
AP		 427 .family = 4,
428 .model = 0,
429 .stepping = 0,
430 .features = I486_FEATURES,
431 .xlevel = 0,
432 },
433 {
434 .name = "pentium",
435 .level = 1,
436 .family = 5,
437 .model = 4,
438 .stepping = 3,
439 .features = PENTIUM_FEATURES,
440 .xlevel = 0,
441 },
442 {
443 .name = "pentium2",
444 .level = 2,
445 .family = 6,
446 .model = 5,
447 .stepping = 2,
448 .features = PENTIUM2_FEATURES,
449 .xlevel = 0,
450 },
451 {
452 .name = "pentium3",
453 .level = 2,
454 .family = 6,
455 .model = 7,
456 .stepping = 3,
457 .features = PENTIUM3_FEATURES,
458 .xlevel = 0,
459 },
460 {
461 .name = "athlon",
462 .level = 2,
463 .vendor1 = CPUID_VENDOR_AMD_1,
464 .vendor2 = CPUID_VENDOR_AMD_2,
465 .vendor3 = CPUID_VENDOR_AMD_3,
466 .family = 6,
467 .model = 2,
468 .stepping = 3,
60032ac0
EH		 469 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
470 CPUID_MCA,
471 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
472 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 473 .xlevel = 0x80000008,
c6dc6f63
AP		 474 },
475 {
476 .name = "n270",
477 /* original is on level 10 */
478 .level = 5,
479 .family = 6,
480 .model = 28,
481 .stepping = 2,
482 .features = PPRO_FEATURES |
8560efed
AJ		 483 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
484 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 485 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 486 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
487 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
60032ac0
EH		 488 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
489 CPUID_EXT2_NX,
8560efed 490 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 491 .xlevel = 0x8000000A,
492 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
493 },
3eca4642
EH		 494 {
495 .name = "Conroe",
496 .level = 2,
497 .vendor1 = CPUID_VENDOR_INTEL_1,
498 .vendor2 = CPUID_VENDOR_INTEL_2,
499 .vendor3 = CPUID_VENDOR_INTEL_3,
500 .family = 6,
501 .model = 2,
502 .stepping = 3,
503 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
504 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
505 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
506 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
507 CPUID_DE | CPUID_FP87,
508 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
509 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
510 .ext3_features = CPUID_EXT3_LAHF_LM,
511 .xlevel = 0x8000000A,
512 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
513 },
514 {
515 .name = "Penryn",
516 .level = 2,
517 .vendor1 = CPUID_VENDOR_INTEL_1,
518 .vendor2 = CPUID_VENDOR_INTEL_2,
519 .vendor3 = CPUID_VENDOR_INTEL_3,
520 .family = 6,
521 .model = 2,
522 .stepping = 3,
523 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
524 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
525 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
526 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
527 CPUID_DE | CPUID_FP87,
528 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
529 CPUID_EXT_SSE3,
530 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
531 .ext3_features = CPUID_EXT3_LAHF_LM,
532 .xlevel = 0x8000000A,
533 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
534 },
535 {
536 .name = "Nehalem",
537 .level = 2,
538 .vendor1 = CPUID_VENDOR_INTEL_1,
539 .vendor2 = CPUID_VENDOR_INTEL_2,
540 .vendor3 = CPUID_VENDOR_INTEL_3,
541 .family = 6,
542 .model = 2,
543 .stepping = 3,
544 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
545 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
546 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
547 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
548 CPUID_DE | CPUID_FP87,
549 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
550 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
551 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
552 .ext3_features = CPUID_EXT3_LAHF_LM,
553 .xlevel = 0x8000000A,
554 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
555 },
556 {
557 .name = "Westmere",
558 .level = 11,
559 .vendor1 = CPUID_VENDOR_INTEL_1,
560 .vendor2 = CPUID_VENDOR_INTEL_2,
561 .vendor3 = CPUID_VENDOR_INTEL_3,
562 .family = 6,
563 .model = 44,
564 .stepping = 1,
565 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
566 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
567 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
568 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
569 CPUID_DE | CPUID_FP87,
570 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
571 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
572 CPUID_EXT_SSE3,
573 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
574 .ext3_features = CPUID_EXT3_LAHF_LM,
575 .xlevel = 0x8000000A,
576 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
577 },
578 {
579 .name = "SandyBridge",
580 .level = 0xd,
581 .vendor1 = CPUID_VENDOR_INTEL_1,
582 .vendor2 = CPUID_VENDOR_INTEL_2,
583 .vendor3 = CPUID_VENDOR_INTEL_3,
584 .family = 6,
585 .model = 42,
586 .stepping = 1,
587 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
588 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
589 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
590 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
591 CPUID_DE | CPUID_FP87,
592 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
593 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
594 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
595 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
596 CPUID_EXT_SSE3,
597 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
598 CPUID_EXT2_SYSCALL,
599 .ext3_features = CPUID_EXT3_LAHF_LM,
600 .xlevel = 0x8000000A,
601 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
602 },
603 {
604 .name = "Opteron_G1",
605 .level = 5,
606 .vendor1 = CPUID_VENDOR_AMD_1,
607 .vendor2 = CPUID_VENDOR_AMD_2,
608 .vendor3 = CPUID_VENDOR_AMD_3,
609 .family = 15,
610 .model = 6,
611 .stepping = 1,
612 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
613 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
614 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
615 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
616 CPUID_DE | CPUID_FP87,
617 .ext_features = CPUID_EXT_SSE3,
618 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
619 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
620 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
621 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
622 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
623 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
624 .xlevel = 0x80000008,
625 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
626 },
627 {
628 .name = "Opteron_G2",
629 .level = 5,
630 .vendor1 = CPUID_VENDOR_AMD_1,
631 .vendor2 = CPUID_VENDOR_AMD_2,
632 .vendor3 = CPUID_VENDOR_AMD_3,
633 .family = 15,
634 .model = 6,
635 .stepping = 1,
636 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
637 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
638 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
639 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
640 CPUID_DE | CPUID_FP87,
641 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
642 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
643 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
644 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
645 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
646 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
647 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
648 CPUID_EXT2_DE | CPUID_EXT2_FPU,
649 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
650 .xlevel = 0x80000008,
651 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
652 },
653 {
654 .name = "Opteron_G3",
655 .level = 5,
656 .vendor1 = CPUID_VENDOR_AMD_1,
657 .vendor2 = CPUID_VENDOR_AMD_2,
658 .vendor3 = CPUID_VENDOR_AMD_3,
659 .family = 15,
660 .model = 6,
661 .stepping = 1,
662 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
663 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
664 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
665 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
666 CPUID_DE | CPUID_FP87,
667 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
668 CPUID_EXT_SSE3,
669 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
670 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
671 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
672 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
673 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
674 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
675 CPUID_EXT2_DE | CPUID_EXT2_FPU,
676 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
677 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
678 .xlevel = 0x80000008,
679 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
680 },
681 {
682 .name = "Opteron_G4",
683 .level = 0xd,
684 .vendor1 = CPUID_VENDOR_AMD_1,
685 .vendor2 = CPUID_VENDOR_AMD_2,
686 .vendor3 = CPUID_VENDOR_AMD_3,
687 .family = 21,
688 .model = 1,
689 .stepping = 2,
690 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
691 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
692 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
693 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
694 CPUID_DE | CPUID_FP87,
695 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
696 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
697 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
698 CPUID_EXT_SSE3,
699 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
700 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
701 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
702 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
703 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
704 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
705 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
706 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
707 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
708 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
709 CPUID_EXT3_LAHF_LM,
710 .xlevel = 0x8000001A,
711 .model_id = "AMD Opteron 62xx class CPU",
712 },
c6dc6f63
AP		 713};
714
715static int cpu_x86_fill_model_id(char *str)
716{
717 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
718 int i;
719
720 for (i = 0; i < 3; i++) {
721 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
722 memcpy(str + i * 16 + 0, &eax, 4);
723 memcpy(str + i * 16 + 4, &ebx, 4);
724 memcpy(str + i * 16 + 8, &ecx, 4);
725 memcpy(str + i * 16 + 12, &edx, 4);
726 }
727 return 0;
728}
729
730static int cpu_x86_fill_host(x86_def_t *x86_cpu_def)
731{
732 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
733
734 x86_cpu_def->name = "host";
735 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
736 x86_cpu_def->level = eax;
737 x86_cpu_def->vendor1 = ebx;
738 x86_cpu_def->vendor2 = edx;
739 x86_cpu_def->vendor3 = ecx;
740
741 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
742 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
743 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
744 x86_cpu_def->stepping = eax & 0x0F;
745 x86_cpu_def->ext_features = ecx;
746 x86_cpu_def->features = edx;
747
13526728
EH		 748 if (kvm_enabled() && x86_cpu_def->level >= 7) {
749 x86_cpu_def->cpuid_7_0_ebx_features = kvm_arch_get_supported_cpuid(kvm_state, 0x7, 0, R_EBX);
750 } else {
751 x86_cpu_def->cpuid_7_0_ebx_features = 0;
752 }
753
c6dc6f63
AP		 754 host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
755 x86_cpu_def->xlevel = eax;
756
757 host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
758 x86_cpu_def->ext2_features = edx;
759 x86_cpu_def->ext3_features = ecx;
760 cpu_x86_fill_model_id(x86_cpu_def->model_id);
761 x86_cpu_def->vendor_override = 0;
762
b3baa152 763 /* Call Centaur's CPUID instruction. */
764 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
765 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
766 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
767 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
768 if (eax >= 0xC0000001) {
769 /* Support VIA max extended level */
770 x86_cpu_def->xlevel2 = eax;
771 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
772 x86_cpu_def->ext4_features = edx;
773 }
774 }
296acb64
JR		 775
776 /*
777 * Every SVM feature requires emulation support in KVM - so we can't just
778 * read the host features here. KVM might even support SVM features not
779 * available on the host hardware. Just set all bits and mask out the
780 * unsupported ones later.
781 */
782 x86_cpu_def->svm_features = -1;
783
c6dc6f63
AP		 784 return 0;
785}
786
787static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
788{
789 int i;
790
791 for (i = 0; i < 32; ++i)
792 if (1 << i & mask) {
793 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
794 " flag '%s' [0x%08x]\n",
795 f->cpuid >> 16, f->cpuid & 0xffff,
796 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
797 break;
798 }
799 return 0;
800}
801
802/* best effort attempt to inform user requested cpu flags aren't making
803 * their way to the guest. Note: ft[].check_feat ideally should be
804 * specified via a guest_def field to suppress report of extraneous flags.
805 */
806static int check_features_against_host(x86_def_t *guest_def)
807{
808 x86_def_t host_def;
809 uint32_t mask;
810 int rv, i;
811 struct model_features_t ft[] = {
812 {&guest_def->features, &host_def.features,
813 ~0, feature_name, 0x00000000},
814 {&guest_def->ext_features, &host_def.ext_features,
815 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
816 {&guest_def->ext2_features, &host_def.ext2_features,
817 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
818 {&guest_def->ext3_features, &host_def.ext3_features,
819 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
820
821 cpu_x86_fill_host(&host_def);
66fe09ee 822 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
c6dc6f63
AP		 823 for (mask = 1; mask; mask <<= 1)
824 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
825 !(*ft[i].host_feat & mask)) {
826 unavailable_host_feature(&ft[i], mask);
827 rv = 1;
828 }
829 return rv;
830}
831
95b8519d
AF		 832static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
833 const char *name, Error **errp)
834{
835 X86CPU *cpu = X86_CPU(obj);
836 CPUX86State *env = &cpu->env;
837 int64_t value;
838
839 value = (env->cpuid_version >> 8) & 0xf;
840 if (value == 0xf) {
841 value += (env->cpuid_version >> 20) & 0xff;
842 }
843 visit_type_int(v, &value, name, errp);
844}
845
71ad61d3
AF		 846static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
847 const char *name, Error **errp)
ed5e1ec3 848{
71ad61d3
AF		 849 X86CPU *cpu = X86_CPU(obj);
850 CPUX86State *env = &cpu->env;
851 const int64_t min = 0;
852 const int64_t max = 0xff + 0xf;
853 int64_t value;
854
855 visit_type_int(v, &value, name, errp);
856 if (error_is_set(errp)) {
857 return;
858 }
859 if (value < min || value > max) {
860 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
861 name ? name : "null", value, min, max);
862 return;
863 }
864
ed5e1ec3 865 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 866 if (value > 0x0f) {
867 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 868 } else {
71ad61d3 869 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 870 }
871}
872
67e30c83
AF		 873static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
874 const char *name, Error **errp)
875{
876 X86CPU *cpu = X86_CPU(obj);
877 CPUX86State *env = &cpu->env;
878 int64_t value;
879
880 value = (env->cpuid_version >> 4) & 0xf;
881 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
882 visit_type_int(v, &value, name, errp);
883}
884
c5291a4f
AF		 885static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
886 const char *name, Error **errp)
b0704cbd 887{
c5291a4f
AF		 888 X86CPU *cpu = X86_CPU(obj);
889 CPUX86State *env = &cpu->env;
890 const int64_t min = 0;
891 const int64_t max = 0xff;
892 int64_t value;
893
894 visit_type_int(v, &value, name, errp);
895 if (error_is_set(errp)) {
896 return;
897 }
898 if (value < min || value > max) {
899 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
900 name ? name : "null", value, min, max);
901 return;
902 }
903
b0704cbd 904 env->cpuid_version &= ~0xf00f0;
c5291a4f 905 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 906}
907
35112e41
AF		 908static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
909 void *opaque, const char *name,
910 Error **errp)
911{
912 X86CPU *cpu = X86_CPU(obj);
913 CPUX86State *env = &cpu->env;
914 int64_t value;
915
916 value = env->cpuid_version & 0xf;
917 visit_type_int(v, &value, name, errp);
918}
919
036e2222
AF		 920static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
921 void *opaque, const char *name,
922 Error **errp)
38c3dc46 923{
036e2222
AF		 924 X86CPU *cpu = X86_CPU(obj);
925 CPUX86State *env = &cpu->env;
926 const int64_t min = 0;
927 const int64_t max = 0xf;
928 int64_t value;
929
930 visit_type_int(v, &value, name, errp);
931 if (error_is_set(errp)) {
932 return;
933 }
934 if (value < min || value > max) {
935 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
936 name ? name : "null", value, min, max);
937 return;
938 }
939
38c3dc46 940 env->cpuid_version &= ~0xf;
036e2222 941 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 942}
943
8e1898bf
AF		 944static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
945 const char *name, Error **errp)
946{
947 X86CPU *cpu = X86_CPU(obj);
8e1898bf 948
fa029887 949 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 950}
951
952static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
953 const char *name, Error **errp)
954{
955 X86CPU *cpu = X86_CPU(obj);
8e1898bf 956
fa029887 957 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 958}
959
16b93aa8
AF		 960static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
961 const char *name, Error **errp)
962{
963 X86CPU *cpu = X86_CPU(obj);
16b93aa8 964
fa029887 965 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 966}
967
968static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
969 const char *name, Error **errp)
970{
971 X86CPU *cpu = X86_CPU(obj);
16b93aa8 972
fa029887 973 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 974}
975
d480e1af
AF		 976static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
977{
978 X86CPU *cpu = X86_CPU(obj);
979 CPUX86State *env = &cpu->env;
980 char *value;
981 int i;
982
983 value = (char *)g_malloc(12 + 1);
984 for (i = 0; i < 4; i++) {
985 value[i ] = env->cpuid_vendor1 >> (8 * i);
986 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
987 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
988 }
989 value[12] = '\0';
990 return value;
991}
992
993static void x86_cpuid_set_vendor(Object *obj, const char *value,
994 Error **errp)
995{
996 X86CPU *cpu = X86_CPU(obj);
997 CPUX86State *env = &cpu->env;
998 int i;
999
1000 if (strlen(value) != 12) {
1001 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1002 "vendor", value);
1003 return;
1004 }
1005
1006 env->cpuid_vendor1 = 0;
1007 env->cpuid_vendor2 = 0;
1008 env->cpuid_vendor3 = 0;
1009 for (i = 0; i < 4; i++) {
1010 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1011 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1012 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1013 }
1014 env->cpuid_vendor_override = 1;
1015}
1016
63e886eb
AF		 1017static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1018{
1019 X86CPU *cpu = X86_CPU(obj);
1020 CPUX86State *env = &cpu->env;
1021 char *value;
1022 int i;
1023
1024 value = g_malloc(48 + 1);
1025 for (i = 0; i < 48; i++) {
1026 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1027 }
1028 value[48] = '\0';
1029 return value;
1030}
1031
938d4c25
AF		 1032static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1033 Error **errp)
dcce6675 1034{
938d4c25
AF		 1035 X86CPU *cpu = X86_CPU(obj);
1036 CPUX86State *env = &cpu->env;
dcce6675
AF		 1037 int c, len, i;
1038
1039 if (model_id == NULL) {
1040 model_id = "";
1041 }
1042 len = strlen(model_id);
d0a6acf4 1043 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1044 for (i = 0; i < 48; i++) {
1045 if (i >= len) {
1046 c = '\0';
1047 } else {
1048 c = (uint8_t)model_id[i];
1049 }
1050 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1051 }
1052}
1053
89e48965
AF		 1054static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1055 const char *name, Error **errp)
1056{
1057 X86CPU *cpu = X86_CPU(obj);
1058 int64_t value;
1059
1060 value = cpu->env.tsc_khz * 1000;
1061 visit_type_int(v, &value, name, errp);
1062}
1063
1064static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1065 const char *name, Error **errp)
1066{
1067 X86CPU *cpu = X86_CPU(obj);
1068 const int64_t min = 0;
2e84849a 1069 const int64_t max = INT64_MAX;
89e48965
AF		 1070 int64_t value;
1071
1072 visit_type_int(v, &value, name, errp);
1073 if (error_is_set(errp)) {
1074 return;
1075 }
1076 if (value < min || value > max) {
1077 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1078 name ? name : "null", value, min, max);
1079 return;
1080 }
1081
1082 cpu->env.tsc_khz = value / 1000;
1083}
1084
c6dc6f63
AP		 1085static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
1086{
1087 unsigned int i;
1088 x86_def_t *def;
1089
d3c481b3 1090 char *s = g_strdup(cpu_model);
c6dc6f63 1091 char *featurestr, *name = strtok(s, ",");
296acb64
JR		 1092 /* Features to be added*/
1093 uint32_t plus_features = 0, plus_ext_features = 0;
1094 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1095 uint32_t plus_kvm_features = 0, plus_svm_features = 0;
1096 /* Features to be removed */
1097 uint32_t minus_features = 0, minus_ext_features = 0;
1098 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1099 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
c6dc6f63
AP		 1100 uint32_t numvalue;
1101
1102 for (def = x86_defs; def; def = def->next)
04c5b17a 1103 if (name && !strcmp(name, def->name))
c6dc6f63 1104 break;
04c5b17a 1105 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
c6dc6f63
AP		 1106 cpu_x86_fill_host(x86_cpu_def);
1107 } else if (!def) {
1108 goto error;
1109 } else {
1110 memcpy(x86_cpu_def, def, sizeof(*def));
1111 }
1112
ef8621b1
AL		 1113#if defined(CONFIG_KVM)
1114 plus_kvm_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
1115 (1 << KVM_FEATURE_NOP_IO_DELAY) |
1116 (1 << KVM_FEATURE_MMU_OP) |
1117 (1 << KVM_FEATURE_CLOCKSOURCE2) |
1118 (1 << KVM_FEATURE_ASYNC_PF) |
1119 (1 << KVM_FEATURE_STEAL_TIME) |
1120 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
1121#else
1122 plus_kvm_features = 0;
1123#endif
c6dc6f63
AP		 1124
1125 add_flagname_to_bitmaps("hypervisor", &plus_features,
1126 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
296acb64 1127 &plus_kvm_features, &plus_svm_features);
c6dc6f63
AP		 1128
1129 featurestr = strtok(NULL, ",");
1130
1131 while (featurestr) {
1132 char *val;
1133 if (featurestr[0] == '+') {
296acb64
JR		 1134 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1135 &plus_ext_features, &plus_ext2_features,
1136 &plus_ext3_features, &plus_kvm_features,
1137 &plus_svm_features);
c6dc6f63 1138 } else if (featurestr[0] == '-') {
296acb64
JR		 1139 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1140 &minus_ext_features, &minus_ext2_features,
1141 &minus_ext3_features, &minus_kvm_features,
1142 &minus_svm_features);
c6dc6f63
AP		 1143 } else if ((val = strchr(featurestr, '='))) {
1144 *val = 0; val++;
1145 if (!strcmp(featurestr, "family")) {
1146 char *err;
1147 numvalue = strtoul(val, &err, 0);
a88a677f 1148 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 1149 fprintf(stderr, "bad numerical value %s\n", val);
1150 goto error;
1151 }
1152 x86_cpu_def->family = numvalue;
1153 } else if (!strcmp(featurestr, "model")) {
1154 char *err;
1155 numvalue = strtoul(val, &err, 0);
1156 if (!*val || *err || numvalue > 0xff) {
1157 fprintf(stderr, "bad numerical value %s\n", val);
1158 goto error;
1159 }
1160 x86_cpu_def->model = numvalue;
1161 } else if (!strcmp(featurestr, "stepping")) {
1162 char *err;
1163 numvalue = strtoul(val, &err, 0);
1164 if (!*val || *err || numvalue > 0xf) {
1165 fprintf(stderr, "bad numerical value %s\n", val);
1166 goto error;
1167 }
1168 x86_cpu_def->stepping = numvalue ;
1169 } else if (!strcmp(featurestr, "level")) {
1170 char *err;
1171 numvalue = strtoul(val, &err, 0);
1172 if (!*val || *err) {
1173 fprintf(stderr, "bad numerical value %s\n", val);
1174 goto error;
1175 }
1176 x86_cpu_def->level = numvalue;
1177 } else if (!strcmp(featurestr, "xlevel")) {
1178 char *err;
1179 numvalue = strtoul(val, &err, 0);
1180 if (!*val || *err) {
1181 fprintf(stderr, "bad numerical value %s\n", val);
1182 goto error;
1183 }
1184 if (numvalue < 0x80000000) {
2f7a21c4 1185 numvalue += 0x80000000;
c6dc6f63
AP		 1186 }
1187 x86_cpu_def->xlevel = numvalue;
1188 } else if (!strcmp(featurestr, "vendor")) {
1189 if (strlen(val) != 12) {
1190 fprintf(stderr, "vendor string must be 12 chars long\n");
1191 goto error;
1192 }
1193 x86_cpu_def->vendor1 = 0;
1194 x86_cpu_def->vendor2 = 0;
1195 x86_cpu_def->vendor3 = 0;
1196 for(i = 0; i < 4; i++) {
1197 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1198 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1199 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1200 }
1201 x86_cpu_def->vendor_override = 1;
1202 } else if (!strcmp(featurestr, "model_id")) {
1203 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1204 val);
b862d1fe
JR		 1205 } else if (!strcmp(featurestr, "tsc_freq")) {
1206 int64_t tsc_freq;
1207 char *err;
1208
1209 tsc_freq = strtosz_suffix_unit(val, &err,
1210 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1211 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 1212 fprintf(stderr, "bad numerical value %s\n", val);
1213 goto error;
1214 }
1215 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 1216 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1217 char *err;
1218 numvalue = strtoul(val, &err, 0);
1219 if (!*val || *err) {
1220 fprintf(stderr, "bad numerical value %s\n", val);
1221 goto error;
1222 }
1223 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 1224 } else {
1225 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1226 goto error;
1227 }
1228 } else if (!strcmp(featurestr, "check")) {
1229 check_cpuid = 1;
1230 } else if (!strcmp(featurestr, "enforce")) {
1231 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 1232 } else if (!strcmp(featurestr, "hv_relaxed")) {
1233 hyperv_enable_relaxed_timing(true);
1234 } else if (!strcmp(featurestr, "hv_vapic")) {
1235 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 1236 } else {
1237 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1238 goto error;
1239 }
1240 featurestr = strtok(NULL, ",");
1241 }
1242 x86_cpu_def->features |= plus_features;
1243 x86_cpu_def->ext_features |= plus_ext_features;
1244 x86_cpu_def->ext2_features |= plus_ext2_features;
1245 x86_cpu_def->ext3_features |= plus_ext3_features;
1246 x86_cpu_def->kvm_features |= plus_kvm_features;
296acb64 1247 x86_cpu_def->svm_features |= plus_svm_features;
c6dc6f63
AP		 1248 x86_cpu_def->features &= ~minus_features;
1249 x86_cpu_def->ext_features &= ~minus_ext_features;
1250 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1251 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1252 x86_cpu_def->kvm_features &= ~minus_kvm_features;
296acb64 1253 x86_cpu_def->svm_features &= ~minus_svm_features;
c6dc6f63
AP		 1254 if (check_cpuid) {
1255 if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
1256 goto error;
1257 }
d3c481b3 1258 g_free(s);
c6dc6f63
AP		 1259 return 0;
1260
1261error:
d3c481b3 1262 g_free(s);
c6dc6f63
AP		 1263 return -1;
1264}
1265
1266/* generate a composite string into buf of all cpuid names in featureset
1267 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1268 * if flags, suppress names undefined in featureset.
1269 */
1270static void listflags(char *buf, int bufsize, uint32_t fbits,
1271 const char **featureset, uint32_t flags)
1272{
1273 const char **p = &featureset[31];
1274 char *q, *b, bit;
1275 int nc;
1276
1277 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1278 *buf = '\0';
1279 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1280 if (fbits & 1 << bit && (*p || !flags)) {
1281 if (*p)
1282 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1283 else
1284 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1285 if (bufsize <= nc) {
1286 if (b) {
1287 memcpy(b, "...", sizeof("..."));
1288 }
1289 return;
1290 }
1291 q += nc;
1292 bufsize -= nc;
1293 }
1294}
1295
e916cbf8
PM		 1296/* generate CPU information. */
1297void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1298{
c6dc6f63
AP		 1299 x86_def_t *def;
1300 char buf[256];
1301
c6dc6f63 1302 for (def = x86_defs; def; def = def->next) {
c04321b3 1303 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1304 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1305 }
ed2c54d4
AP		 1306 if (kvm_enabled()) {
1307 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1308 }
6cdf8854
PM		 1309 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1310 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1311 (*cpu_fprintf)(f, " f_edx: %s\n", buf);
1312 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1313 (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
1314 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1315 (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
1316 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1317 (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
c6dc6f63
AP		 1318}
1319
76b64a7a 1320CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1321{
1322 CpuDefinitionInfoList *cpu_list = NULL;
1323 x86_def_t *def;
1324
1325 for (def = x86_defs; def; def = def->next) {
1326 CpuDefinitionInfoList *entry;
1327 CpuDefinitionInfo *info;
1328
1329 info = g_malloc0(sizeof(*info));
1330 info->name = g_strdup(def->name);
1331
1332 entry = g_malloc0(sizeof(*entry));
1333 entry->value = info;
1334 entry->next = cpu_list;
1335 cpu_list = entry;
1336 }
1337
1338 return cpu_list;
1339}
1340
61dcd775 1341int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 1342{
61dcd775 1343 CPUX86State *env = &cpu->env;
c6dc6f63 1344 x86_def_t def1, *def = &def1;
71ad61d3 1345 Error *error = NULL;
c6dc6f63 1346
db0ad1ba
JR		 1347 memset(def, 0, sizeof(*def));
1348
c6dc6f63
AP		 1349 if (cpu_x86_find_by_name(def, cpu_model) < 0)
1350 return -1;
1351 if (def->vendor1) {
1352 env->cpuid_vendor1 = def->vendor1;
1353 env->cpuid_vendor2 = def->vendor2;
1354 env->cpuid_vendor3 = def->vendor3;
1355 } else {
1356 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1357 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1358 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1359 }
1360 env->cpuid_vendor_override = def->vendor_override;
8e1898bf 1361 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
71ad61d3 1362 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 1363 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
036e2222 1364 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
c6dc6f63 1365 env->cpuid_features = def->features;
c6dc6f63
AP		 1366 env->cpuid_ext_features = def->ext_features;
1367 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 1368 env->cpuid_ext3_features = def->ext3_features;
16b93aa8 1369 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
c6dc6f63 1370 env->cpuid_kvm_features = def->kvm_features;
296acb64 1371 env->cpuid_svm_features = def->svm_features;
b3baa152 1372 env->cpuid_ext4_features = def->ext4_features;
13526728 1373 env->cpuid_7_0_ebx = def->cpuid_7_0_ebx_features;
b3baa152 1374 env->cpuid_xlevel2 = def->xlevel2;
89e48965
AF		 1375 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1376 "tsc-frequency", &error);
551a2dec
AP		 1377 if (!kvm_enabled()) {
1378 env->cpuid_features &= TCG_FEATURES;
1379 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1380 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1381#ifdef TARGET_X86_64
1382 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1383#endif
1384 );
1385 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
296acb64 1386 env->cpuid_svm_features &= TCG_SVM_FEATURES;
551a2dec 1387 }
938d4c25 1388 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
71ad61d3
AF		 1389 if (error_is_set(&error)) {
1390 error_free(error);
1391 return -1;
1392 }
c6dc6f63
AP		 1393 return 0;
1394}
1395
1396#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1397
0e26b7b8
BS		 1398void cpu_clear_apic_feature(CPUX86State *env)
1399{
1400 env->cpuid_features &= ~CPUID_APIC;
1401}
1402
c6dc6f63
AP		 1403#endif /* !CONFIG_USER_ONLY */
1404
c04321b3 1405/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 1406 */
1407void x86_cpudef_setup(void)
1408{
93bfef4c
CV		 1409 int i, j;
1410 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1411
1412 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
bc3e1291
EH		 1413 x86_def_t *def = &builtin_x86_defs[i];
1414 def->next = x86_defs;
93bfef4c
CV		 1415
1416 /* Look for specific "cpudef" models that */
09faecf2 1417 /* have the QEMU version in .model_id */
93bfef4c 1418 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 1419 if (strcmp(model_with_versions[j], def->name) == 0) {
1420 pstrcpy(def->model_id, sizeof(def->model_id),
1421 "QEMU Virtual CPU version ");
1422 pstrcat(def->model_id, sizeof(def->model_id),
1423 qemu_get_version());
93bfef4c
CV		 1424 break;
1425 }
1426 }
1427
bc3e1291 1428 x86_defs = def;
c6dc6f63 1429 }
c6dc6f63
AP		 1430}
1431
c6dc6f63
AP		 1432static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1433 uint32_t *ecx, uint32_t *edx)
1434{
1435 *ebx = env->cpuid_vendor1;
1436 *edx = env->cpuid_vendor2;
1437 *ecx = env->cpuid_vendor3;
1438
1439 /* sysenter isn't supported on compatibility mode on AMD, syscall
1440 * isn't supported in compatibility mode on Intel.
1441 * Normally we advertise the actual cpu vendor, but you can override
1442 * this if you want to use KVM's sysenter/syscall emulation
1443 * in compatibility mode and when doing cross vendor migration
1444 */
89354998 1445 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1446 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1447 }
1448}
1449
1450void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1451 uint32_t *eax, uint32_t *ebx,
1452 uint32_t *ecx, uint32_t *edx)
1453{
1454 /* test if maximum index reached */
1455 if (index & 0x80000000) {
b3baa152 1456 if (index > env->cpuid_xlevel) {
1457 if (env->cpuid_xlevel2 > 0) {
1458 /* Handle the Centaur's CPUID instruction. */
1459 if (index > env->cpuid_xlevel2) {
1460 index = env->cpuid_xlevel2;
1461 } else if (index < 0xC0000000) {
1462 index = env->cpuid_xlevel;
1463 }
1464 } else {
1465 index = env->cpuid_xlevel;
1466 }
1467 }
c6dc6f63
AP		 1468 } else {
1469 if (index > env->cpuid_level)
1470 index = env->cpuid_level;
1471 }
1472
1473 switch(index) {
1474 case 0:
1475 *eax = env->cpuid_level;
1476 get_cpuid_vendor(env, ebx, ecx, edx);
1477 break;
1478 case 1:
1479 *eax = env->cpuid_version;
1480 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1481 *ecx = env->cpuid_ext_features;
1482 *edx = env->cpuid_features;
1483 if (env->nr_cores * env->nr_threads > 1) {
1484 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1485 *edx |= 1 << 28; /* HTT bit */
1486 }
1487 break;
1488 case 2:
1489 /* cache info: needed for Pentium Pro compatibility */
1490 *eax = 1;
1491 *ebx = 0;
1492 *ecx = 0;
1493 *edx = 0x2c307d;
1494 break;
1495 case 4:
1496 /* cache info: needed for Core compatibility */
1497 if (env->nr_cores > 1) {
2f7a21c4 1498 *eax = (env->nr_cores - 1) << 26;
c6dc6f63 1499 } else {
2f7a21c4 1500 *eax = 0;
c6dc6f63
AP		 1501 }
1502 switch (count) {
1503 case 0: /* L1 dcache info */
1504 *eax |= 0x0000121;
1505 *ebx = 0x1c0003f;
1506 *ecx = 0x000003f;
1507 *edx = 0x0000001;
1508 break;
1509 case 1: /* L1 icache info */
1510 *eax |= 0x0000122;
1511 *ebx = 0x1c0003f;
1512 *ecx = 0x000003f;
1513 *edx = 0x0000001;
1514 break;
1515 case 2: /* L2 cache info */
1516 *eax |= 0x0000143;
1517 if (env->nr_threads > 1) {
1518 *eax |= (env->nr_threads - 1) << 14;
1519 }
1520 *ebx = 0x3c0003f;
1521 *ecx = 0x0000fff;
1522 *edx = 0x0000001;
1523 break;
1524 default: /* end of info */
1525 *eax = 0;
1526 *ebx = 0;
1527 *ecx = 0;
1528 *edx = 0;
1529 break;
1530 }
1531 break;
1532 case 5:
1533 /* mwait info: needed for Core compatibility */
1534 *eax = 0; /* Smallest monitor-line size in bytes */
1535 *ebx = 0; /* Largest monitor-line size in bytes */
1536 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1537 *edx = 0;
1538 break;
1539 case 6:
1540 /* Thermal and Power Leaf */
1541 *eax = 0;
1542 *ebx = 0;
1543 *ecx = 0;
1544 *edx = 0;
1545 break;
f7911686 1546 case 7:
13526728
EH		 1547 /* Structured Extended Feature Flags Enumeration Leaf */
1548 if (count == 0) {
1549 *eax = 0; /* Maximum ECX value for sub-leaves */
1550 *ebx = env->cpuid_7_0_ebx; /* Feature flags */
1551 *ecx = 0; /* Reserved */
1552 *edx = 0; /* Reserved */
f7911686
YW		 1553 } else {
1554 *eax = 0;
1555 *ebx = 0;
1556 *ecx = 0;
1557 *edx = 0;
1558 }
1559 break;
c6dc6f63
AP		 1560 case 9:
1561 /* Direct Cache Access Information Leaf */
1562 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1563 *ebx = 0;
1564 *ecx = 0;
1565 *edx = 0;
1566 break;
1567 case 0xA:
1568 /* Architectural Performance Monitoring Leaf */
a0fa8208
GN		 1569 if (kvm_enabled()) {
1570 KVMState *s = env->kvm_state;
1571
1572 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1573 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1574 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1575 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1576 } else {
1577 *eax = 0;
1578 *ebx = 0;
1579 *ecx = 0;
1580 *edx = 0;
1581 }
c6dc6f63 1582 break;
51e49430
SY		 1583 case 0xD:
1584 /* Processor Extended State */
1585 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1586 *eax = 0;
1587 *ebx = 0;
1588 *ecx = 0;
1589 *edx = 0;
1590 break;
1591 }
1592 if (kvm_enabled()) {
ba9bc59e
JK		 1593 KVMState *s = env->kvm_state;
1594
1595 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1596 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1597 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1598 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1599 } else {
1600 *eax = 0;
1601 *ebx = 0;
1602 *ecx = 0;
1603 *edx = 0;
1604 }
1605 break;
c6dc6f63
AP		 1606 case 0x80000000:
1607 *eax = env->cpuid_xlevel;
1608 *ebx = env->cpuid_vendor1;
1609 *edx = env->cpuid_vendor2;
1610 *ecx = env->cpuid_vendor3;
1611 break;
1612 case 0x80000001:
1613 *eax = env->cpuid_version;
1614 *ebx = 0;
1615 *ecx = env->cpuid_ext3_features;
1616 *edx = env->cpuid_ext2_features;
1617
1618 /* The Linux kernel checks for the CMPLegacy bit and
1619 * discards multiple thread information if it is set.
1620 * So dont set it here for Intel to make Linux guests happy.
1621 */
1622 if (env->nr_cores * env->nr_threads > 1) {
1623 uint32_t tebx, tecx, tedx;
1624 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1625 if (tebx != CPUID_VENDOR_INTEL_1 ||
1626 tedx != CPUID_VENDOR_INTEL_2 ||
1627 tecx != CPUID_VENDOR_INTEL_3) {
1628 *ecx |= 1 << 1; /* CmpLegacy bit */
1629 }
1630 }
c6dc6f63
AP		 1631 break;
1632 case 0x80000002:
1633 case 0x80000003:
1634 case 0x80000004:
1635 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1636 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1637 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1638 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1639 break;
1640 case 0x80000005:
1641 /* cache info (L1 cache) */
1642 *eax = 0x01ff01ff;
1643 *ebx = 0x01ff01ff;
1644 *ecx = 0x40020140;
1645 *edx = 0x40020140;
1646 break;
1647 case 0x80000006:
1648 /* cache info (L2 cache) */
1649 *eax = 0;
1650 *ebx = 0x42004200;
1651 *ecx = 0x02008140;
1652 *edx = 0;
1653 break;
1654 case 0x80000008:
1655 /* virtual & phys address size in low 2 bytes. */
1656/* XXX: This value must match the one used in the MMU code. */
1657 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1658 /* 64 bit processor */
1659/* XXX: The physical address space is limited to 42 bits in exec.c. */
1660 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1661 } else {
1662 if (env->cpuid_features & CPUID_PSE36)
1663 *eax = 0x00000024; /* 36 bits physical */
1664 else
1665 *eax = 0x00000020; /* 32 bits physical */
1666 }
1667 *ebx = 0;
1668 *ecx = 0;
1669 *edx = 0;
1670 if (env->nr_cores * env->nr_threads > 1) {
1671 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1672 }
1673 break;
1674 case 0x8000000A:
296acb64
JR		 1675 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1676 *eax = 0x00000001; /* SVM Revision */
1677 *ebx = 0x00000010; /* nr of ASIDs */
1678 *ecx = 0;
1679 *edx = env->cpuid_svm_features; /* optional features */
1680 } else {
1681 *eax = 0;
1682 *ebx = 0;
1683 *ecx = 0;
1684 *edx = 0;
1685 }
c6dc6f63 1686 break;
b3baa152 1687 case 0xC0000000:
1688 *eax = env->cpuid_xlevel2;
1689 *ebx = 0;
1690 *ecx = 0;
1691 *edx = 0;
1692 break;
1693 case 0xC0000001:
1694 /* Support for VIA CPU's CPUID instruction */
1695 *eax = env->cpuid_version;
1696 *ebx = 0;
1697 *ecx = 0;
1698 *edx = env->cpuid_ext4_features;
1699 break;
1700 case 0xC0000002:
1701 case 0xC0000003:
1702 case 0xC0000004:
1703 /* Reserved for the future, and now filled with zero */
1704 *eax = 0;
1705 *ebx = 0;
1706 *ecx = 0;
1707 *edx = 0;
1708 break;
c6dc6f63
AP		 1709 default:
1710 /* reserved values: zero */
1711 *eax = 0;
1712 *ebx = 0;
1713 *ecx = 0;
1714 *edx = 0;
1715 break;
1716 }
1717}
5fd2087a
AF		 1718
1719/* CPUClass::reset() */
1720static void x86_cpu_reset(CPUState *s)
1721{
1722 X86CPU *cpu = X86_CPU(s);
1723 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1724 CPUX86State *env = &cpu->env;
c1958aea
AF		 1725 int i;
1726
1727 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1728 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1729 log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
1730 }
5fd2087a
AF		 1731
1732 xcc->parent_reset(s);
1733
c1958aea
AF		 1734
1735 memset(env, 0, offsetof(CPUX86State, breakpoints));
1736
1737 tlb_flush(env, 1);
1738
1739 env->old_exception = -1;
1740
1741 /* init to reset state */
1742
1743#ifdef CONFIG_SOFTMMU
1744 env->hflags |= HF_SOFTMMU_MASK;
1745#endif
1746 env->hflags2 |= HF2_GIF_MASK;
1747
1748 cpu_x86_update_cr0(env, 0x60000010);
1749 env->a20_mask = ~0x0;
1750 env->smbase = 0x30000;
1751
1752 env->idt.limit = 0xffff;
1753 env->gdt.limit = 0xffff;
1754 env->ldt.limit = 0xffff;
1755 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1756 env->tr.limit = 0xffff;
1757 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1758
1759 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1760 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1761 DESC_R_MASK | DESC_A_MASK);
1762 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1763 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1764 DESC_A_MASK);
1765 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1766 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1767 DESC_A_MASK);
1768 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1769 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1770 DESC_A_MASK);
1771 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1772 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1773 DESC_A_MASK);
1774 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1775 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1776 DESC_A_MASK);
1777
1778 env->eip = 0xfff0;
1779 env->regs[R_EDX] = env->cpuid_version;
1780
1781 env->eflags = 0x2;
1782
1783 /* FPU init */
1784 for (i = 0; i < 8; i++) {
1785 env->fptags[i] = 1;
1786 }
1787 env->fpuc = 0x37f;
1788
1789 env->mxcsr = 0x1f80;
1790
1791 env->pat = 0x0007040600070406ULL;
1792 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1793
1794 memset(env->dr, 0, sizeof(env->dr));
1795 env->dr[6] = DR6_FIXED_1;
1796 env->dr[7] = DR7_FIXED_1;
1797 cpu_breakpoint_remove_all(env, BP_CPU);
1798 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM		 1799
1800#if !defined(CONFIG_USER_ONLY)
1801 /* We hard-wire the BSP to the first CPU. */
1802 if (env->cpu_index == 0) {
1803 apic_designate_bsp(env->apic_state);
1804 }
1805
1806 env->halted = !cpu_is_bsp(cpu);
1807#endif
5fd2087a
AF		 1808}
1809
dd673288
IM		 1810#ifndef CONFIG_USER_ONLY
1811bool cpu_is_bsp(X86CPU *cpu)
1812{
1813 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
1814}
65dee380
IM		 1815
1816/* TODO: remove me, when reset over QOM tree is implemented */
1817static void x86_cpu_machine_reset_cb(void *opaque)
1818{
1819 X86CPU *cpu = opaque;
1820 cpu_reset(CPU(cpu));
1821}
dd673288
IM		 1822#endif
1823
de024815
AF		 1824static void mce_init(X86CPU *cpu)
1825{
1826 CPUX86State *cenv = &cpu->env;
1827 unsigned int bank;
1828
1829 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
1830 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
1831 (CPUID_MCE | CPUID_MCA)) {
1832 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
1833 cenv->mcg_ctl = ~(uint64_t)0;
1834 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
1835 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
1836 }
1837 }
1838}
1839
7a059953
AF		 1840void x86_cpu_realize(Object *obj, Error **errp)
1841{
1842 X86CPU *cpu = X86_CPU(obj);
1843
65dee380
IM		 1844#ifndef CONFIG_USER_ONLY
1845 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
1846#endif
1847
7a059953
AF		 1848 mce_init(cpu);
1849 qemu_init_vcpu(&cpu->env);
65dee380 1850 cpu_reset(CPU(cpu));
7a059953
AF		 1851}
1852
de024815
AF		 1853static void x86_cpu_initfn(Object *obj)
1854{
1855 X86CPU *cpu = X86_CPU(obj);
1856 CPUX86State *env = &cpu->env;
d65e9815 1857 static int inited;
de024815
AF		 1858
1859 cpu_exec_init(env);
71ad61d3
AF		 1860
1861 object_property_add(obj, "family", "int",
95b8519d 1862 x86_cpuid_version_get_family,
71ad61d3 1863 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 1864 object_property_add(obj, "model", "int",
67e30c83 1865 x86_cpuid_version_get_model,
c5291a4f 1866 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 1867 object_property_add(obj, "stepping", "int",
35112e41 1868 x86_cpuid_version_get_stepping,
036e2222 1869 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 1870 object_property_add(obj, "level", "int",
1871 x86_cpuid_get_level,
1872 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 1873 object_property_add(obj, "xlevel", "int",
1874 x86_cpuid_get_xlevel,
1875 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 1876 object_property_add_str(obj, "vendor",
1877 x86_cpuid_get_vendor,
1878 x86_cpuid_set_vendor, NULL);
938d4c25 1879 object_property_add_str(obj, "model-id",
63e886eb 1880 x86_cpuid_get_model_id,
938d4c25 1881 x86_cpuid_set_model_id, NULL);
89e48965
AF		 1882 object_property_add(obj, "tsc-frequency", "int",
1883 x86_cpuid_get_tsc_freq,
1884 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
71ad61d3 1885
de024815 1886 env->cpuid_apic_id = env->cpu_index;
d65e9815
IM		 1887
1888 /* init various static tables used in TCG mode */
1889 if (tcg_enabled() && !inited) {
1890 inited = 1;
1891 optimize_flags_init();
1892#ifndef CONFIG_USER_ONLY
1893 cpu_set_debug_excp_handler(breakpoint_handler);
1894#endif
1895 }
de024815
AF		 1896}
1897
5fd2087a
AF		 1898static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
1899{
1900 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1901 CPUClass *cc = CPU_CLASS(oc);
1902
1903 xcc->parent_reset = cc->reset;
1904 cc->reset = x86_cpu_reset;
1905}
1906
1907static const TypeInfo x86_cpu_type_info = {
1908 .name = TYPE_X86_CPU,
1909 .parent = TYPE_CPU,
1910 .instance_size = sizeof(X86CPU),
de024815 1911 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 1912 .abstract = false,
1913 .class_size = sizeof(X86CPUClass),
1914 .class_init = x86_cpu_common_class_init,
1915};
1916
1917static void x86_cpu_register_types(void)
1918{
1919 type_register_static(&x86_cpu_type_info);
1920}
1921
1922type_init(x86_cpu_register_types)
Qemu copy for testing