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Eliminate cpus-x86_64.conf file
[qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
25#include "kvm.h"
26
27#include "qemu-option.h"
28#include "qemu-config.h"
29
71ad61d3 30#include "qapi/qapi-visit-core.h"
76b64a7a 31#include "arch_init.h"
71ad61d3 32
28f52cc0
VR		 33#include "hyperv.h"
34
65dee380 35#include "hw/hw.h"
b834b508 36#if defined(CONFIG_KVM)
ef8621b1 37#include <linux/kvm_para.h>
b834b508 38#endif
65dee380 39
c6dc6f63
AP		 40/* feature flags taken from "Intel Processor Identification and the CPUID
41 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
42 * between feature naming conventions, aliases may be added.
43 */
44static const char *feature_name[] = {
45 "fpu", "vme", "de", "pse",
46 "tsc", "msr", "pae", "mce",
47 "cx8", "apic", NULL, "sep",
48 "mtrr", "pge", "mca", "cmov",
49 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
50 NULL, "ds" /* Intel dts */, "acpi", "mmx",
51 "fxsr", "sse", "sse2", "ss",
52 "ht" /* Intel htt */, "tm", "ia64", "pbe",
53};
54static const char *ext_feature_name[] = {
f370be3c 55 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 56 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 57 "tm2", "ssse3", "cid", NULL,
e117f772 58 "fma", "cx16", "xtpr", "pdcm",
434acb81 59 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 60 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 61 "tsc-deadline", "aes", "xsave", "osxsave",
e117f772 62 "avx", NULL, NULL, "hypervisor",
c6dc6f63
AP		 63};
64static const char *ext2_feature_name[] = {
65 "fpu", "vme", "de", "pse",
66 "tsc", "msr", "pae", "mce",
67 "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",
68 "mtrr", "pge", "mca", "cmov",
69 "pat", "pse36", NULL, NULL /* Linux mp */,
3ac8ebfe 70 "nx|xd", NULL, "mmxext", "mmx",
f370be3c 71 "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
3ac8ebfe 72 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 73};
74static const char *ext3_feature_name[] = {
75 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
76 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 77 "3dnowprefetch", "osvw", "ibs", "xop",
c6dc6f63 78 "skinit", "wdt", NULL, NULL,
e117f772 79 "fma4", NULL, "cvt16", "nodeid_msr",
c6dc6f63
AP		 80 NULL, NULL, NULL, NULL,
81 NULL, NULL, NULL, NULL,
82 NULL, NULL, NULL, NULL,
83};
84
85static const char *kvm_feature_name[] = {
bfee7546 86 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, "kvm_pv_eoi", NULL,
c6dc6f63
AP		 87 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
88 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
89 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
90};
91
296acb64
JR		 92static const char *svm_feature_name[] = {
93 "npt", "lbrv", "svm_lock", "nrip_save",
94 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
95 NULL, NULL, "pause_filter", NULL,
96 "pfthreshold", NULL, NULL, NULL,
97 NULL, NULL, NULL, NULL,
98 NULL, NULL, NULL, NULL,
99 NULL, NULL, NULL, NULL,
100 NULL, NULL, NULL, NULL,
101};
102
c6dc6f63
AP		 103/* collects per-function cpuid data
104 */
105typedef struct model_features_t {
106 uint32_t *guest_feat;
107 uint32_t *host_feat;
108 uint32_t check_feat;
109 const char **flag_names;
110 uint32_t cpuid;
111 } model_features_t;
112
113int check_cpuid = 0;
114int enforce_cpuid = 0;
115
bb44e0d1
JK		 116void host_cpuid(uint32_t function, uint32_t count,
117 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 118{
119#if defined(CONFIG_KVM)
a1fd24af
AL		 120 uint32_t vec[4];
121
122#ifdef __x86_64__
123 asm volatile("cpuid"
124 : "=a"(vec[0]), "=b"(vec[1]),
125 "=c"(vec[2]), "=d"(vec[3])
126 : "0"(function), "c"(count) : "cc");
127#else
128 asm volatile("pusha \n\t"
129 "cpuid \n\t"
130 "mov %%eax, 0(%2) \n\t"
131 "mov %%ebx, 4(%2) \n\t"
132 "mov %%ecx, 8(%2) \n\t"
133 "mov %%edx, 12(%2) \n\t"
134 "popa"
135 : : "a"(function), "c"(count), "S"(vec)
136 : "memory", "cc");
137#endif
138
bdde476a 139 if (eax)
a1fd24af 140 *eax = vec[0];
bdde476a 141 if (ebx)
a1fd24af 142 *ebx = vec[1];
bdde476a 143 if (ecx)
a1fd24af 144 *ecx = vec[2];
bdde476a 145 if (edx)
a1fd24af 146 *edx = vec[3];
bdde476a
AP		 147#endif
148}
c6dc6f63
AP		 149
150#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
151
152/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
153 * a substring. ex if !NULL points to the first char after a substring,
154 * otherwise the string is assumed to sized by a terminating nul.
155 * Return lexical ordering of *s1:*s2.
156 */
157static int sstrcmp(const char *s1, const char *e1, const char *s2,
158 const char *e2)
159{
160 for (;;) {
161 if (!*s1 || !*s2 || *s1 != *s2)
162 return (*s1 - *s2);
163 ++s1, ++s2;
164 if (s1 == e1 && s2 == e2)
165 return (0);
166 else if (s1 == e1)
167 return (*s2);
168 else if (s2 == e2)
169 return (*s1);
170 }
171}
172
173/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
174 * '|' delimited (possibly empty) strings in which case search for a match
175 * within the alternatives proceeds left to right. Return 0 for success,
176 * non-zero otherwise.
177 */
178static int altcmp(const char *s, const char *e, const char *altstr)
179{
180 const char *p, *q;
181
182 for (q = p = altstr; ; ) {
183 while (*p && *p != '|')
184 ++p;
185 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
186 return (0);
187 if (!*p)
188 return (1);
189 else
190 q = ++p;
191 }
192}
193
194/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 195 * *pval and return true, otherwise return false
c6dc6f63 196 */
e41e0fc6
JK		 197static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
198 const char **featureset)
c6dc6f63
AP		 199{
200 uint32_t mask;
201 const char **ppc;
e41e0fc6 202 bool found = false;
c6dc6f63 203
e41e0fc6 204 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 205 if (*ppc && !altcmp(s, e, *ppc)) {
206 *pval |= mask;
e41e0fc6 207 found = true;
c6dc6f63 208 }
e41e0fc6
JK		 209 }
210 return found;
c6dc6f63
AP		 211}
212
213static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
214 uint32_t *ext_features,
215 uint32_t *ext2_features,
216 uint32_t *ext3_features,
296acb64
JR		 217 uint32_t *kvm_features,
218 uint32_t *svm_features)
c6dc6f63
AP		 219{
220 if (!lookup_feature(features, flagname, NULL, feature_name) &&
221 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
222 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
223 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
296acb64
JR		 224 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
225 !lookup_feature(svm_features, flagname, NULL, svm_feature_name))
c6dc6f63
AP		 226 fprintf(stderr, "CPU feature %s not found\n", flagname);
227}
228
229typedef struct x86_def_t {
230 struct x86_def_t *next;
231 const char *name;
232 uint32_t level;
233 uint32_t vendor1, vendor2, vendor3;
234 int family;
235 int model;
236 int stepping;
b862d1fe 237 int tsc_khz;
296acb64
JR		 238 uint32_t features, ext_features, ext2_features, ext3_features;
239 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 240 uint32_t xlevel;
241 char model_id[48];
242 int vendor_override;
243 uint32_t flags;
b3baa152 244 /* Store the results of Centaur's CPUID instructions */
245 uint32_t ext4_features;
246 uint32_t xlevel2;
13526728
EH		 247 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
248 uint32_t cpuid_7_0_ebx_features;
c6dc6f63
AP		 249} x86_def_t;
250
251#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
252#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
253 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
254#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
255 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
256 CPUID_PSE36 | CPUID_FXSR)
257#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
258#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
259 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
260 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
261 CPUID_PAE | CPUID_SEP | CPUID_APIC)
42673936 262#define EXT2_FEATURE_MASK 0x0183F3FF
c6dc6f63 263
551a2dec
AP		 264#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
265 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
266 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
267 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
268 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 269 /* partly implemented:
270 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
271 CPUID_PSE36 (needed for Solaris) */
272 /* missing:
273 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 274#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
8713f8ff 275 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 276 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 277 /* missing:
278 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 279 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
551a2dec
AP		 280#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
281 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
282 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 283 /* missing:
284 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 285#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
286 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 287#define TCG_SVM_FEATURES 0
551a2dec 288
c6dc6f63
AP		 289/* maintains list of cpu model definitions
290 */
291static x86_def_t *x86_defs = {NULL};
292
293/* built-in cpu model definitions (deprecated)
294 */
295static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 296 {
297 .name = "qemu64",
298 .level = 4,
299 .vendor1 = CPUID_VENDOR_AMD_1,
300 .vendor2 = CPUID_VENDOR_AMD_2,
301 .vendor3 = CPUID_VENDOR_AMD_3,
302 .family = 6,
303 .model = 2,
304 .stepping = 3,
305 .features = PPRO_FEATURES |
c6dc6f63 306 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 307 CPUID_PSE36,
308 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
42673936 309 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 310 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
311 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
312 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
313 .xlevel = 0x8000000A,
c6dc6f63
AP		 314 },
315 {
316 .name = "phenom",
317 .level = 5,
318 .vendor1 = CPUID_VENDOR_AMD_1,
319 .vendor2 = CPUID_VENDOR_AMD_2,
320 .vendor3 = CPUID_VENDOR_AMD_3,
321 .family = 16,
322 .model = 2,
323 .stepping = 3,
c6dc6f63
AP		 324 .features = PPRO_FEATURES |
325 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 326 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 327 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
328 CPUID_EXT_POPCNT,
42673936 329 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 330 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
331 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 332 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 333 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
334 CPUID_EXT3_CR8LEG,
335 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
336 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
337 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
338 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 339 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 340 .xlevel = 0x8000001A,
341 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
342 },
343 {
344 .name = "core2duo",
345 .level = 10,
346 .family = 6,
347 .model = 15,
348 .stepping = 11,
c6dc6f63
AP		 349 .features = PPRO_FEATURES |
350 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 351 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
352 CPUID_HT | CPUID_TM | CPUID_PBE,
353 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
354 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
355 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 356 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
357 .ext3_features = CPUID_EXT3_LAHF_LM,
358 .xlevel = 0x80000008,
359 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
360 },
361 {
362 .name = "kvm64",
363 .level = 5,
364 .vendor1 = CPUID_VENDOR_INTEL_1,
365 .vendor2 = CPUID_VENDOR_INTEL_2,
366 .vendor3 = CPUID_VENDOR_INTEL_3,
367 .family = 15,
368 .model = 6,
369 .stepping = 1,
370 /* Missing: CPUID_VME, CPUID_HT */
371 .features = PPRO_FEATURES |
372 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
373 CPUID_PSE36,
374 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
375 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
376 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
42673936 377 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 378 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
379 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
380 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
381 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
382 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
383 .ext3_features = 0,
384 .xlevel = 0x80000008,
385 .model_id = "Common KVM processor"
386 },
c6dc6f63
AP		 387 {
388 .name = "qemu32",
389 .level = 4,
390 .family = 6,
391 .model = 3,
392 .stepping = 3,
393 .features = PPRO_FEATURES,
394 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 395 .xlevel = 0x80000004,
c6dc6f63 396 },
eafaf1e5
AP		 397 {
398 .name = "kvm32",
399 .level = 5,
400 .family = 15,
401 .model = 6,
402 .stepping = 1,
403 .features = PPRO_FEATURES |
404 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
405 .ext_features = CPUID_EXT_SSE3,
406 .ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK,
407 .ext3_features = 0,
408 .xlevel = 0x80000008,
409 .model_id = "Common 32-bit KVM processor"
410 },
c6dc6f63
AP		 411 {
412 .name = "coreduo",
413 .level = 10,
414 .family = 6,
415 .model = 14,
416 .stepping = 8,
c6dc6f63 417 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 418 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
419 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
420 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
421 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 422 .ext2_features = CPUID_EXT2_NX,
423 .xlevel = 0x80000008,
424 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
425 },
426 {
427 .name = "486",
58012d66 428 .level = 1,
c6dc6f63
AP		 429 .family = 4,
430 .model = 0,
431 .stepping = 0,
432 .features = I486_FEATURES,
433 .xlevel = 0,
434 },
435 {
436 .name = "pentium",
437 .level = 1,
438 .family = 5,
439 .model = 4,
440 .stepping = 3,
441 .features = PENTIUM_FEATURES,
442 .xlevel = 0,
443 },
444 {
445 .name = "pentium2",
446 .level = 2,
447 .family = 6,
448 .model = 5,
449 .stepping = 2,
450 .features = PENTIUM2_FEATURES,
451 .xlevel = 0,
452 },
453 {
454 .name = "pentium3",
455 .level = 2,
456 .family = 6,
457 .model = 7,
458 .stepping = 3,
459 .features = PENTIUM3_FEATURES,
460 .xlevel = 0,
461 },
462 {
463 .name = "athlon",
464 .level = 2,
465 .vendor1 = CPUID_VENDOR_AMD_1,
466 .vendor2 = CPUID_VENDOR_AMD_2,
467 .vendor3 = CPUID_VENDOR_AMD_3,
468 .family = 6,
469 .model = 2,
470 .stepping = 3,
471 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
42673936 472 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 473 .xlevel = 0x80000008,
c6dc6f63
AP		 474 },
475 {
476 .name = "n270",
477 /* original is on level 10 */
478 .level = 5,
479 .family = 6,
480 .model = 28,
481 .stepping = 2,
482 .features = PPRO_FEATURES |
8560efed
AJ		 483 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
484 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 485 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 486 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
487 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
42673936 488 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX,
8560efed 489 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 490 .xlevel = 0x8000000A,
491 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
492 },
3eca4642
EH		 493 {
494 .name = "Conroe",
495 .level = 2,
496 .vendor1 = CPUID_VENDOR_INTEL_1,
497 .vendor2 = CPUID_VENDOR_INTEL_2,
498 .vendor3 = CPUID_VENDOR_INTEL_3,
499 .family = 6,
500 .model = 2,
501 .stepping = 3,
502 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
503 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
504 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
505 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
506 CPUID_DE | CPUID_FP87,
507 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
508 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
509 .ext3_features = CPUID_EXT3_LAHF_LM,
510 .xlevel = 0x8000000A,
511 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
512 },
513 {
514 .name = "Penryn",
515 .level = 2,
516 .vendor1 = CPUID_VENDOR_INTEL_1,
517 .vendor2 = CPUID_VENDOR_INTEL_2,
518 .vendor3 = CPUID_VENDOR_INTEL_3,
519 .family = 6,
520 .model = 2,
521 .stepping = 3,
522 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
523 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
524 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
525 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
526 CPUID_DE | CPUID_FP87,
527 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
528 CPUID_EXT_SSE3,
529 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
530 .ext3_features = CPUID_EXT3_LAHF_LM,
531 .xlevel = 0x8000000A,
532 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
533 },
534 {
535 .name = "Nehalem",
536 .level = 2,
537 .vendor1 = CPUID_VENDOR_INTEL_1,
538 .vendor2 = CPUID_VENDOR_INTEL_2,
539 .vendor3 = CPUID_VENDOR_INTEL_3,
540 .family = 6,
541 .model = 2,
542 .stepping = 3,
543 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
544 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
545 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
546 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
547 CPUID_DE | CPUID_FP87,
548 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
549 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
550 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
551 .ext3_features = CPUID_EXT3_LAHF_LM,
552 .xlevel = 0x8000000A,
553 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
554 },
555 {
556 .name = "Westmere",
557 .level = 11,
558 .vendor1 = CPUID_VENDOR_INTEL_1,
559 .vendor2 = CPUID_VENDOR_INTEL_2,
560 .vendor3 = CPUID_VENDOR_INTEL_3,
561 .family = 6,
562 .model = 44,
563 .stepping = 1,
564 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
565 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
566 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
567 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
568 CPUID_DE | CPUID_FP87,
569 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
570 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
571 CPUID_EXT_SSE3,
572 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
573 .ext3_features = CPUID_EXT3_LAHF_LM,
574 .xlevel = 0x8000000A,
575 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
576 },
577 {
578 .name = "SandyBridge",
579 .level = 0xd,
580 .vendor1 = CPUID_VENDOR_INTEL_1,
581 .vendor2 = CPUID_VENDOR_INTEL_2,
582 .vendor3 = CPUID_VENDOR_INTEL_3,
583 .family = 6,
584 .model = 42,
585 .stepping = 1,
586 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
587 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
588 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
589 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
590 CPUID_DE | CPUID_FP87,
591 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
592 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
593 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
594 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
595 CPUID_EXT_SSE3,
596 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
597 CPUID_EXT2_SYSCALL,
598 .ext3_features = CPUID_EXT3_LAHF_LM,
599 .xlevel = 0x8000000A,
600 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
601 },
602 {
603 .name = "Opteron_G1",
604 .level = 5,
605 .vendor1 = CPUID_VENDOR_AMD_1,
606 .vendor2 = CPUID_VENDOR_AMD_2,
607 .vendor3 = CPUID_VENDOR_AMD_3,
608 .family = 15,
609 .model = 6,
610 .stepping = 1,
611 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
612 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
613 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
614 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
615 CPUID_DE | CPUID_FP87,
616 .ext_features = CPUID_EXT_SSE3,
617 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
618 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
619 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
620 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
621 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
622 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
623 .xlevel = 0x80000008,
624 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
625 },
626 {
627 .name = "Opteron_G2",
628 .level = 5,
629 .vendor1 = CPUID_VENDOR_AMD_1,
630 .vendor2 = CPUID_VENDOR_AMD_2,
631 .vendor3 = CPUID_VENDOR_AMD_3,
632 .family = 15,
633 .model = 6,
634 .stepping = 1,
635 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
636 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
637 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
638 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
639 CPUID_DE | CPUID_FP87,
640 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
641 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
642 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
643 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
644 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
645 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
646 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
647 CPUID_EXT2_DE | CPUID_EXT2_FPU,
648 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
649 .xlevel = 0x80000008,
650 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
651 },
652 {
653 .name = "Opteron_G3",
654 .level = 5,
655 .vendor1 = CPUID_VENDOR_AMD_1,
656 .vendor2 = CPUID_VENDOR_AMD_2,
657 .vendor3 = CPUID_VENDOR_AMD_3,
658 .family = 15,
659 .model = 6,
660 .stepping = 1,
661 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
662 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
663 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
664 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
665 CPUID_DE | CPUID_FP87,
666 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
667 CPUID_EXT_SSE3,
668 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
669 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
670 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
671 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
672 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
673 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
674 CPUID_EXT2_DE | CPUID_EXT2_FPU,
675 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
676 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
677 .xlevel = 0x80000008,
678 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
679 },
680 {
681 .name = "Opteron_G4",
682 .level = 0xd,
683 .vendor1 = CPUID_VENDOR_AMD_1,
684 .vendor2 = CPUID_VENDOR_AMD_2,
685 .vendor3 = CPUID_VENDOR_AMD_3,
686 .family = 21,
687 .model = 1,
688 .stepping = 2,
689 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
690 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
691 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
692 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
693 CPUID_DE | CPUID_FP87,
694 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
695 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
696 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
697 CPUID_EXT_SSE3,
698 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
699 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
700 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
701 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
702 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
703 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
704 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
705 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
706 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
707 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
708 CPUID_EXT3_LAHF_LM,
709 .xlevel = 0x8000001A,
710 .model_id = "AMD Opteron 62xx class CPU",
711 },
c6dc6f63
AP		 712};
713
714static int cpu_x86_fill_model_id(char *str)
715{
716 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
717 int i;
718
719 for (i = 0; i < 3; i++) {
720 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
721 memcpy(str + i * 16 + 0, &eax, 4);
722 memcpy(str + i * 16 + 4, &ebx, 4);
723 memcpy(str + i * 16 + 8, &ecx, 4);
724 memcpy(str + i * 16 + 12, &edx, 4);
725 }
726 return 0;
727}
728
729static int cpu_x86_fill_host(x86_def_t *x86_cpu_def)
730{
731 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
732
733 x86_cpu_def->name = "host";
734 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
735 x86_cpu_def->level = eax;
736 x86_cpu_def->vendor1 = ebx;
737 x86_cpu_def->vendor2 = edx;
738 x86_cpu_def->vendor3 = ecx;
739
740 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
741 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
742 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
743 x86_cpu_def->stepping = eax & 0x0F;
744 x86_cpu_def->ext_features = ecx;
745 x86_cpu_def->features = edx;
746
13526728
EH		 747 if (kvm_enabled() && x86_cpu_def->level >= 7) {
748 x86_cpu_def->cpuid_7_0_ebx_features = kvm_arch_get_supported_cpuid(kvm_state, 0x7, 0, R_EBX);
749 } else {
750 x86_cpu_def->cpuid_7_0_ebx_features = 0;
751 }
752
c6dc6f63
AP		 753 host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
754 x86_cpu_def->xlevel = eax;
755
756 host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
757 x86_cpu_def->ext2_features = edx;
758 x86_cpu_def->ext3_features = ecx;
759 cpu_x86_fill_model_id(x86_cpu_def->model_id);
760 x86_cpu_def->vendor_override = 0;
761
b3baa152 762 /* Call Centaur's CPUID instruction. */
763 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
764 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
765 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
766 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
767 if (eax >= 0xC0000001) {
768 /* Support VIA max extended level */
769 x86_cpu_def->xlevel2 = eax;
770 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
771 x86_cpu_def->ext4_features = edx;
772 }
773 }
296acb64
JR		 774
775 /*
776 * Every SVM feature requires emulation support in KVM - so we can't just
777 * read the host features here. KVM might even support SVM features not
778 * available on the host hardware. Just set all bits and mask out the
779 * unsupported ones later.
780 */
781 x86_cpu_def->svm_features = -1;
782
c6dc6f63
AP		 783 return 0;
784}
785
786static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
787{
788 int i;
789
790 for (i = 0; i < 32; ++i)
791 if (1 << i & mask) {
792 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
793 " flag '%s' [0x%08x]\n",
794 f->cpuid >> 16, f->cpuid & 0xffff,
795 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
796 break;
797 }
798 return 0;
799}
800
801/* best effort attempt to inform user requested cpu flags aren't making
802 * their way to the guest. Note: ft[].check_feat ideally should be
803 * specified via a guest_def field to suppress report of extraneous flags.
804 */
805static int check_features_against_host(x86_def_t *guest_def)
806{
807 x86_def_t host_def;
808 uint32_t mask;
809 int rv, i;
810 struct model_features_t ft[] = {
811 {&guest_def->features, &host_def.features,
812 ~0, feature_name, 0x00000000},
813 {&guest_def->ext_features, &host_def.ext_features,
814 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
815 {&guest_def->ext2_features, &host_def.ext2_features,
816 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
817 {&guest_def->ext3_features, &host_def.ext3_features,
818 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
819
820 cpu_x86_fill_host(&host_def);
66fe09ee 821 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
c6dc6f63
AP		 822 for (mask = 1; mask; mask <<= 1)
823 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
824 !(*ft[i].host_feat & mask)) {
825 unavailable_host_feature(&ft[i], mask);
826 rv = 1;
827 }
828 return rv;
829}
830
95b8519d
AF		 831static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
832 const char *name, Error **errp)
833{
834 X86CPU *cpu = X86_CPU(obj);
835 CPUX86State *env = &cpu->env;
836 int64_t value;
837
838 value = (env->cpuid_version >> 8) & 0xf;
839 if (value == 0xf) {
840 value += (env->cpuid_version >> 20) & 0xff;
841 }
842 visit_type_int(v, &value, name, errp);
843}
844
71ad61d3
AF		 845static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
846 const char *name, Error **errp)
ed5e1ec3 847{
71ad61d3
AF		 848 X86CPU *cpu = X86_CPU(obj);
849 CPUX86State *env = &cpu->env;
850 const int64_t min = 0;
851 const int64_t max = 0xff + 0xf;
852 int64_t value;
853
854 visit_type_int(v, &value, name, errp);
855 if (error_is_set(errp)) {
856 return;
857 }
858 if (value < min || value > max) {
859 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
860 name ? name : "null", value, min, max);
861 return;
862 }
863
ed5e1ec3 864 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 865 if (value > 0x0f) {
866 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 867 } else {
71ad61d3 868 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 869 }
870}
871
67e30c83
AF		 872static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
873 const char *name, Error **errp)
874{
875 X86CPU *cpu = X86_CPU(obj);
876 CPUX86State *env = &cpu->env;
877 int64_t value;
878
879 value = (env->cpuid_version >> 4) & 0xf;
880 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
881 visit_type_int(v, &value, name, errp);
882}
883
c5291a4f
AF		 884static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
885 const char *name, Error **errp)
b0704cbd 886{
c5291a4f
AF		 887 X86CPU *cpu = X86_CPU(obj);
888 CPUX86State *env = &cpu->env;
889 const int64_t min = 0;
890 const int64_t max = 0xff;
891 int64_t value;
892
893 visit_type_int(v, &value, name, errp);
894 if (error_is_set(errp)) {
895 return;
896 }
897 if (value < min || value > max) {
898 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
899 name ? name : "null", value, min, max);
900 return;
901 }
902
b0704cbd 903 env->cpuid_version &= ~0xf00f0;
c5291a4f 904 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 905}
906
35112e41
AF		 907static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
908 void *opaque, const char *name,
909 Error **errp)
910{
911 X86CPU *cpu = X86_CPU(obj);
912 CPUX86State *env = &cpu->env;
913 int64_t value;
914
915 value = env->cpuid_version & 0xf;
916 visit_type_int(v, &value, name, errp);
917}
918
036e2222
AF		 919static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
920 void *opaque, const char *name,
921 Error **errp)
38c3dc46 922{
036e2222
AF		 923 X86CPU *cpu = X86_CPU(obj);
924 CPUX86State *env = &cpu->env;
925 const int64_t min = 0;
926 const int64_t max = 0xf;
927 int64_t value;
928
929 visit_type_int(v, &value, name, errp);
930 if (error_is_set(errp)) {
931 return;
932 }
933 if (value < min || value > max) {
934 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
935 name ? name : "null", value, min, max);
936 return;
937 }
938
38c3dc46 939 env->cpuid_version &= ~0xf;
036e2222 940 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 941}
942
8e1898bf
AF		 943static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
944 const char *name, Error **errp)
945{
946 X86CPU *cpu = X86_CPU(obj);
8e1898bf 947
fa029887 948 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 949}
950
951static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
952 const char *name, Error **errp)
953{
954 X86CPU *cpu = X86_CPU(obj);
8e1898bf 955
fa029887 956 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 957}
958
16b93aa8
AF		 959static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
960 const char *name, Error **errp)
961{
962 X86CPU *cpu = X86_CPU(obj);
16b93aa8 963
fa029887 964 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 965}
966
967static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
968 const char *name, Error **errp)
969{
970 X86CPU *cpu = X86_CPU(obj);
16b93aa8 971
fa029887 972 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 973}
974
d480e1af
AF		 975static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
976{
977 X86CPU *cpu = X86_CPU(obj);
978 CPUX86State *env = &cpu->env;
979 char *value;
980 int i;
981
982 value = (char *)g_malloc(12 + 1);
983 for (i = 0; i < 4; i++) {
984 value[i ] = env->cpuid_vendor1 >> (8 * i);
985 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
986 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
987 }
988 value[12] = '\0';
989 return value;
990}
991
992static void x86_cpuid_set_vendor(Object *obj, const char *value,
993 Error **errp)
994{
995 X86CPU *cpu = X86_CPU(obj);
996 CPUX86State *env = &cpu->env;
997 int i;
998
999 if (strlen(value) != 12) {
1000 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1001 "vendor", value);
1002 return;
1003 }
1004
1005 env->cpuid_vendor1 = 0;
1006 env->cpuid_vendor2 = 0;
1007 env->cpuid_vendor3 = 0;
1008 for (i = 0; i < 4; i++) {
1009 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1010 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1011 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1012 }
1013 env->cpuid_vendor_override = 1;
1014}
1015
63e886eb
AF		 1016static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1017{
1018 X86CPU *cpu = X86_CPU(obj);
1019 CPUX86State *env = &cpu->env;
1020 char *value;
1021 int i;
1022
1023 value = g_malloc(48 + 1);
1024 for (i = 0; i < 48; i++) {
1025 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1026 }
1027 value[48] = '\0';
1028 return value;
1029}
1030
938d4c25
AF		 1031static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1032 Error **errp)
dcce6675 1033{
938d4c25
AF		 1034 X86CPU *cpu = X86_CPU(obj);
1035 CPUX86State *env = &cpu->env;
dcce6675
AF		 1036 int c, len, i;
1037
1038 if (model_id == NULL) {
1039 model_id = "";
1040 }
1041 len = strlen(model_id);
d0a6acf4 1042 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1043 for (i = 0; i < 48; i++) {
1044 if (i >= len) {
1045 c = '\0';
1046 } else {
1047 c = (uint8_t)model_id[i];
1048 }
1049 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1050 }
1051}
1052
89e48965
AF		 1053static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1054 const char *name, Error **errp)
1055{
1056 X86CPU *cpu = X86_CPU(obj);
1057 int64_t value;
1058
1059 value = cpu->env.tsc_khz * 1000;
1060 visit_type_int(v, &value, name, errp);
1061}
1062
1063static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1064 const char *name, Error **errp)
1065{
1066 X86CPU *cpu = X86_CPU(obj);
1067 const int64_t min = 0;
1068 const int64_t max = INT_MAX;
1069 int64_t value;
1070
1071 visit_type_int(v, &value, name, errp);
1072 if (error_is_set(errp)) {
1073 return;
1074 }
1075 if (value < min || value > max) {
1076 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1077 name ? name : "null", value, min, max);
1078 return;
1079 }
1080
1081 cpu->env.tsc_khz = value / 1000;
1082}
1083
c6dc6f63
AP		 1084static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
1085{
1086 unsigned int i;
1087 x86_def_t *def;
1088
d3c481b3 1089 char *s = g_strdup(cpu_model);
c6dc6f63 1090 char *featurestr, *name = strtok(s, ",");
296acb64
JR		 1091 /* Features to be added*/
1092 uint32_t plus_features = 0, plus_ext_features = 0;
1093 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1094 uint32_t plus_kvm_features = 0, plus_svm_features = 0;
1095 /* Features to be removed */
1096 uint32_t minus_features = 0, minus_ext_features = 0;
1097 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1098 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
c6dc6f63
AP		 1099 uint32_t numvalue;
1100
1101 for (def = x86_defs; def; def = def->next)
04c5b17a 1102 if (name && !strcmp(name, def->name))
c6dc6f63 1103 break;
04c5b17a 1104 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
c6dc6f63
AP		 1105 cpu_x86_fill_host(x86_cpu_def);
1106 } else if (!def) {
1107 goto error;
1108 } else {
1109 memcpy(x86_cpu_def, def, sizeof(*def));
1110 }
1111
ef8621b1
AL		 1112#if defined(CONFIG_KVM)
1113 plus_kvm_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
1114 (1 << KVM_FEATURE_NOP_IO_DELAY) |
1115 (1 << KVM_FEATURE_MMU_OP) |
1116 (1 << KVM_FEATURE_CLOCKSOURCE2) |
1117 (1 << KVM_FEATURE_ASYNC_PF) |
1118 (1 << KVM_FEATURE_STEAL_TIME) |
1119 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
1120#else
1121 plus_kvm_features = 0;
1122#endif
c6dc6f63
AP		 1123
1124 add_flagname_to_bitmaps("hypervisor", &plus_features,
1125 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
296acb64 1126 &plus_kvm_features, &plus_svm_features);
c6dc6f63
AP		 1127
1128 featurestr = strtok(NULL, ",");
1129
1130 while (featurestr) {
1131 char *val;
1132 if (featurestr[0] == '+') {
296acb64
JR		 1133 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1134 &plus_ext_features, &plus_ext2_features,
1135 &plus_ext3_features, &plus_kvm_features,
1136 &plus_svm_features);
c6dc6f63 1137 } else if (featurestr[0] == '-') {
296acb64
JR		 1138 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1139 &minus_ext_features, &minus_ext2_features,
1140 &minus_ext3_features, &minus_kvm_features,
1141 &minus_svm_features);
c6dc6f63
AP		 1142 } else if ((val = strchr(featurestr, '='))) {
1143 *val = 0; val++;
1144 if (!strcmp(featurestr, "family")) {
1145 char *err;
1146 numvalue = strtoul(val, &err, 0);
a88a677f 1147 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 1148 fprintf(stderr, "bad numerical value %s\n", val);
1149 goto error;
1150 }
1151 x86_cpu_def->family = numvalue;
1152 } else if (!strcmp(featurestr, "model")) {
1153 char *err;
1154 numvalue = strtoul(val, &err, 0);
1155 if (!*val || *err || numvalue > 0xff) {
1156 fprintf(stderr, "bad numerical value %s\n", val);
1157 goto error;
1158 }
1159 x86_cpu_def->model = numvalue;
1160 } else if (!strcmp(featurestr, "stepping")) {
1161 char *err;
1162 numvalue = strtoul(val, &err, 0);
1163 if (!*val || *err || numvalue > 0xf) {
1164 fprintf(stderr, "bad numerical value %s\n", val);
1165 goto error;
1166 }
1167 x86_cpu_def->stepping = numvalue ;
1168 } else if (!strcmp(featurestr, "level")) {
1169 char *err;
1170 numvalue = strtoul(val, &err, 0);
1171 if (!*val || *err) {
1172 fprintf(stderr, "bad numerical value %s\n", val);
1173 goto error;
1174 }
1175 x86_cpu_def->level = numvalue;
1176 } else if (!strcmp(featurestr, "xlevel")) {
1177 char *err;
1178 numvalue = strtoul(val, &err, 0);
1179 if (!*val || *err) {
1180 fprintf(stderr, "bad numerical value %s\n", val);
1181 goto error;
1182 }
1183 if (numvalue < 0x80000000) {
2f7a21c4 1184 numvalue += 0x80000000;
c6dc6f63
AP		 1185 }
1186 x86_cpu_def->xlevel = numvalue;
1187 } else if (!strcmp(featurestr, "vendor")) {
1188 if (strlen(val) != 12) {
1189 fprintf(stderr, "vendor string must be 12 chars long\n");
1190 goto error;
1191 }
1192 x86_cpu_def->vendor1 = 0;
1193 x86_cpu_def->vendor2 = 0;
1194 x86_cpu_def->vendor3 = 0;
1195 for(i = 0; i < 4; i++) {
1196 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1197 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1198 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1199 }
1200 x86_cpu_def->vendor_override = 1;
1201 } else if (!strcmp(featurestr, "model_id")) {
1202 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1203 val);
b862d1fe
JR		 1204 } else if (!strcmp(featurestr, "tsc_freq")) {
1205 int64_t tsc_freq;
1206 char *err;
1207
1208 tsc_freq = strtosz_suffix_unit(val, &err,
1209 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1210 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 1211 fprintf(stderr, "bad numerical value %s\n", val);
1212 goto error;
1213 }
1214 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 1215 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1216 char *err;
1217 numvalue = strtoul(val, &err, 0);
1218 if (!*val || *err) {
1219 fprintf(stderr, "bad numerical value %s\n", val);
1220 goto error;
1221 }
1222 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 1223 } else {
1224 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1225 goto error;
1226 }
1227 } else if (!strcmp(featurestr, "check")) {
1228 check_cpuid = 1;
1229 } else if (!strcmp(featurestr, "enforce")) {
1230 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 1231 } else if (!strcmp(featurestr, "hv_relaxed")) {
1232 hyperv_enable_relaxed_timing(true);
1233 } else if (!strcmp(featurestr, "hv_vapic")) {
1234 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 1235 } else {
1236 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1237 goto error;
1238 }
1239 featurestr = strtok(NULL, ",");
1240 }
1241 x86_cpu_def->features |= plus_features;
1242 x86_cpu_def->ext_features |= plus_ext_features;
1243 x86_cpu_def->ext2_features |= plus_ext2_features;
1244 x86_cpu_def->ext3_features |= plus_ext3_features;
1245 x86_cpu_def->kvm_features |= plus_kvm_features;
296acb64 1246 x86_cpu_def->svm_features |= plus_svm_features;
c6dc6f63
AP		 1247 x86_cpu_def->features &= ~minus_features;
1248 x86_cpu_def->ext_features &= ~minus_ext_features;
1249 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1250 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1251 x86_cpu_def->kvm_features &= ~minus_kvm_features;
296acb64 1252 x86_cpu_def->svm_features &= ~minus_svm_features;
c6dc6f63
AP		 1253 if (check_cpuid) {
1254 if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
1255 goto error;
1256 }
d3c481b3 1257 g_free(s);
c6dc6f63
AP		 1258 return 0;
1259
1260error:
d3c481b3 1261 g_free(s);
c6dc6f63
AP		 1262 return -1;
1263}
1264
1265/* generate a composite string into buf of all cpuid names in featureset
1266 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1267 * if flags, suppress names undefined in featureset.
1268 */
1269static void listflags(char *buf, int bufsize, uint32_t fbits,
1270 const char **featureset, uint32_t flags)
1271{
1272 const char **p = &featureset[31];
1273 char *q, *b, bit;
1274 int nc;
1275
1276 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1277 *buf = '\0';
1278 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1279 if (fbits & 1 << bit && (*p || !flags)) {
1280 if (*p)
1281 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1282 else
1283 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1284 if (bufsize <= nc) {
1285 if (b) {
1286 memcpy(b, "...", sizeof("..."));
1287 }
1288 return;
1289 }
1290 q += nc;
1291 bufsize -= nc;
1292 }
1293}
1294
e916cbf8
PM		 1295/* generate CPU information. */
1296void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1297{
c6dc6f63
AP		 1298 x86_def_t *def;
1299 char buf[256];
1300
c6dc6f63
AP		 1301 for (def = x86_defs; def; def = def->next) {
1302 snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name);
6cdf8854 1303 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1304 }
ed2c54d4
AP		 1305 if (kvm_enabled()) {
1306 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1307 }
6cdf8854
PM		 1308 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1309 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1310 (*cpu_fprintf)(f, " f_edx: %s\n", buf);
1311 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1312 (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
1313 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1314 (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
1315 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1316 (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
c6dc6f63
AP		 1317}
1318
76b64a7a 1319CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1320{
1321 CpuDefinitionInfoList *cpu_list = NULL;
1322 x86_def_t *def;
1323
1324 for (def = x86_defs; def; def = def->next) {
1325 CpuDefinitionInfoList *entry;
1326 CpuDefinitionInfo *info;
1327
1328 info = g_malloc0(sizeof(*info));
1329 info->name = g_strdup(def->name);
1330
1331 entry = g_malloc0(sizeof(*entry));
1332 entry->value = info;
1333 entry->next = cpu_list;
1334 cpu_list = entry;
1335 }
1336
1337 return cpu_list;
1338}
1339
61dcd775 1340int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 1341{
61dcd775 1342 CPUX86State *env = &cpu->env;
c6dc6f63 1343 x86_def_t def1, *def = &def1;
71ad61d3 1344 Error *error = NULL;
c6dc6f63 1345
db0ad1ba
JR		 1346 memset(def, 0, sizeof(*def));
1347
c6dc6f63
AP		 1348 if (cpu_x86_find_by_name(def, cpu_model) < 0)
1349 return -1;
1350 if (def->vendor1) {
1351 env->cpuid_vendor1 = def->vendor1;
1352 env->cpuid_vendor2 = def->vendor2;
1353 env->cpuid_vendor3 = def->vendor3;
1354 } else {
1355 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1356 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1357 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1358 }
1359 env->cpuid_vendor_override = def->vendor_override;
8e1898bf 1360 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
71ad61d3 1361 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 1362 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
036e2222 1363 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
c6dc6f63 1364 env->cpuid_features = def->features;
c6dc6f63
AP		 1365 env->cpuid_ext_features = def->ext_features;
1366 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 1367 env->cpuid_ext3_features = def->ext3_features;
16b93aa8 1368 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
c6dc6f63 1369 env->cpuid_kvm_features = def->kvm_features;
296acb64 1370 env->cpuid_svm_features = def->svm_features;
b3baa152 1371 env->cpuid_ext4_features = def->ext4_features;
13526728 1372 env->cpuid_7_0_ebx = def->cpuid_7_0_ebx_features;
b3baa152 1373 env->cpuid_xlevel2 = def->xlevel2;
89e48965
AF		 1374 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1375 "tsc-frequency", &error);
551a2dec
AP		 1376 if (!kvm_enabled()) {
1377 env->cpuid_features &= TCG_FEATURES;
1378 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1379 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1380#ifdef TARGET_X86_64
1381 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1382#endif
1383 );
1384 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
296acb64 1385 env->cpuid_svm_features &= TCG_SVM_FEATURES;
551a2dec 1386 }
938d4c25 1387 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
71ad61d3
AF		 1388 if (error_is_set(&error)) {
1389 error_free(error);
1390 return -1;
1391 }
c6dc6f63
AP		 1392 return 0;
1393}
1394
1395#if !defined(CONFIG_USER_ONLY)
1396/* copy vendor id string to 32 bit register, nul pad as needed
1397 */
1398static void cpyid(const char *s, uint32_t *id)
1399{
1400 char *d = (char *)id;
1401 char i;
1402
1403 for (i = sizeof (*id); i--; )
1404 *d++ = *s ? *s++ : '\0';
1405}
1406
1407/* interpret radix and convert from string to arbitrary scalar,
1408 * otherwise flag failure
1409 */
1410#define setscalar(pval, str, perr) \
1411{ \
1412 char *pend; \
1413 unsigned long ul; \
1414 \
1415 ul = strtoul(str, &pend, 0); \
1416 *str && !*pend ? (*pval = ul) : (*perr = 1); \
1417}
1418
1419/* map cpuid options to feature bits, otherwise return failure
1420 * (option tags in *str are delimited by whitespace)
1421 */
1422static void setfeatures(uint32_t *pval, const char *str,
1423 const char **featureset, int *perr)
1424{
1425 const char *p, *q;
1426
1427 for (q = p = str; *p || *q; q = p) {
1428 while (iswhite(*p))
1429 q = ++p;
1430 while (*p && !iswhite(*p))
1431 ++p;
1432 if (!*q && !*p)
1433 return;
1434 if (!lookup_feature(pval, q, p, featureset)) {
1435 fprintf(stderr, "error: feature \"%.*s\" not available in set\n",
1436 (int)(p - q), q);
1437 *perr = 1;
1438 return;
1439 }
1440 }
1441}
1442
1443/* map config file options to x86_def_t form
1444 */
1445static int cpudef_setfield(const char *name, const char *str, void *opaque)
1446{
1447 x86_def_t *def = opaque;
1448 int err = 0;
1449
1450 if (!strcmp(name, "name")) {
99e1dec0 1451 g_free((void *)def->name);
d3c481b3 1452 def->name = g_strdup(str);
c6dc6f63
AP		 1453 } else if (!strcmp(name, "model_id")) {
1454 strncpy(def->model_id, str, sizeof (def->model_id));
1455 } else if (!strcmp(name, "level")) {
1456 setscalar(&def->level, str, &err)
1457 } else if (!strcmp(name, "vendor")) {
1458 cpyid(&str[0], &def->vendor1);
1459 cpyid(&str[4], &def->vendor2);
1460 cpyid(&str[8], &def->vendor3);
1461 } else if (!strcmp(name, "family")) {
1462 setscalar(&def->family, str, &err)
1463 } else if (!strcmp(name, "model")) {
1464 setscalar(&def->model, str, &err)
1465 } else if (!strcmp(name, "stepping")) {
1466 setscalar(&def->stepping, str, &err)
1467 } else if (!strcmp(name, "feature_edx")) {
1468 setfeatures(&def->features, str, feature_name, &err);
1469 } else if (!strcmp(name, "feature_ecx")) {
1470 setfeatures(&def->ext_features, str, ext_feature_name, &err);
1471 } else if (!strcmp(name, "extfeature_edx")) {
1472 setfeatures(&def->ext2_features, str, ext2_feature_name, &err);
1473 } else if (!strcmp(name, "extfeature_ecx")) {
1474 setfeatures(&def->ext3_features, str, ext3_feature_name, &err);
1475 } else if (!strcmp(name, "xlevel")) {
1476 setscalar(&def->xlevel, str, &err)
1477 } else {
1478 fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
1479 return (1);
1480 }
1481 if (err) {
1482 fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
1483 return (1);
1484 }
1485 return (0);
1486}
1487
1488/* register config file entry as x86_def_t
1489 */
1490static int cpudef_register(QemuOpts *opts, void *opaque)
1491{
7267c094 1492 x86_def_t *def = g_malloc0(sizeof (x86_def_t));
c6dc6f63
AP		 1493
1494 qemu_opt_foreach(opts, cpudef_setfield, def, 1);
1495 def->next = x86_defs;
1496 x86_defs = def;
1497 return (0);
1498}
0e26b7b8
BS		 1499
1500void cpu_clear_apic_feature(CPUX86State *env)
1501{
1502 env->cpuid_features &= ~CPUID_APIC;
1503}
1504
c6dc6f63
AP		 1505#endif /* !CONFIG_USER_ONLY */
1506
1507/* register "cpudef" models defined in configuration file. Here we first
1508 * preload any built-in definitions
1509 */
1510void x86_cpudef_setup(void)
1511{
93bfef4c
CV		 1512 int i, j;
1513 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1514
1515 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1516 builtin_x86_defs[i].next = x86_defs;
1517 builtin_x86_defs[i].flags = 1;
93bfef4c
CV		 1518
1519 /* Look for specific "cpudef" models that */
09faecf2 1520 /* have the QEMU version in .model_id */
93bfef4c
CV		 1521 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1522 if (strcmp(model_with_versions[j], builtin_x86_defs[i].name) == 0) {
1523 pstrcpy(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), "QEMU Virtual CPU version ");
1524 pstrcat(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), qemu_get_version());
1525 break;
1526 }
1527 }
1528
c6dc6f63
AP		 1529 x86_defs = &builtin_x86_defs[i];
1530 }
1531#if !defined(CONFIG_USER_ONLY)
3329f07b 1532 qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0);
c6dc6f63
AP		 1533#endif
1534}
1535
c6dc6f63
AP		 1536static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1537 uint32_t *ecx, uint32_t *edx)
1538{
1539 *ebx = env->cpuid_vendor1;
1540 *edx = env->cpuid_vendor2;
1541 *ecx = env->cpuid_vendor3;
1542
1543 /* sysenter isn't supported on compatibility mode on AMD, syscall
1544 * isn't supported in compatibility mode on Intel.
1545 * Normally we advertise the actual cpu vendor, but you can override
1546 * this if you want to use KVM's sysenter/syscall emulation
1547 * in compatibility mode and when doing cross vendor migration
1548 */
89354998 1549 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1550 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1551 }
1552}
1553
1554void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1555 uint32_t *eax, uint32_t *ebx,
1556 uint32_t *ecx, uint32_t *edx)
1557{
1558 /* test if maximum index reached */
1559 if (index & 0x80000000) {
b3baa152 1560 if (index > env->cpuid_xlevel) {
1561 if (env->cpuid_xlevel2 > 0) {
1562 /* Handle the Centaur's CPUID instruction. */
1563 if (index > env->cpuid_xlevel2) {
1564 index = env->cpuid_xlevel2;
1565 } else if (index < 0xC0000000) {
1566 index = env->cpuid_xlevel;
1567 }
1568 } else {
1569 index = env->cpuid_xlevel;
1570 }
1571 }
c6dc6f63
AP		 1572 } else {
1573 if (index > env->cpuid_level)
1574 index = env->cpuid_level;
1575 }
1576
1577 switch(index) {
1578 case 0:
1579 *eax = env->cpuid_level;
1580 get_cpuid_vendor(env, ebx, ecx, edx);
1581 break;
1582 case 1:
1583 *eax = env->cpuid_version;
1584 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1585 *ecx = env->cpuid_ext_features;
1586 *edx = env->cpuid_features;
1587 if (env->nr_cores * env->nr_threads > 1) {
1588 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1589 *edx |= 1 << 28; /* HTT bit */
1590 }
1591 break;
1592 case 2:
1593 /* cache info: needed for Pentium Pro compatibility */
1594 *eax = 1;
1595 *ebx = 0;
1596 *ecx = 0;
1597 *edx = 0x2c307d;
1598 break;
1599 case 4:
1600 /* cache info: needed for Core compatibility */
1601 if (env->nr_cores > 1) {
2f7a21c4 1602 *eax = (env->nr_cores - 1) << 26;
c6dc6f63 1603 } else {
2f7a21c4 1604 *eax = 0;
c6dc6f63
AP		 1605 }
1606 switch (count) {
1607 case 0: /* L1 dcache info */
1608 *eax |= 0x0000121;
1609 *ebx = 0x1c0003f;
1610 *ecx = 0x000003f;
1611 *edx = 0x0000001;
1612 break;
1613 case 1: /* L1 icache info */
1614 *eax |= 0x0000122;
1615 *ebx = 0x1c0003f;
1616 *ecx = 0x000003f;
1617 *edx = 0x0000001;
1618 break;
1619 case 2: /* L2 cache info */
1620 *eax |= 0x0000143;
1621 if (env->nr_threads > 1) {
1622 *eax |= (env->nr_threads - 1) << 14;
1623 }
1624 *ebx = 0x3c0003f;
1625 *ecx = 0x0000fff;
1626 *edx = 0x0000001;
1627 break;
1628 default: /* end of info */
1629 *eax = 0;
1630 *ebx = 0;
1631 *ecx = 0;
1632 *edx = 0;
1633 break;
1634 }
1635 break;
1636 case 5:
1637 /* mwait info: needed for Core compatibility */
1638 *eax = 0; /* Smallest monitor-line size in bytes */
1639 *ebx = 0; /* Largest monitor-line size in bytes */
1640 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1641 *edx = 0;
1642 break;
1643 case 6:
1644 /* Thermal and Power Leaf */
1645 *eax = 0;
1646 *ebx = 0;
1647 *ecx = 0;
1648 *edx = 0;
1649 break;
f7911686 1650 case 7:
13526728
EH		 1651 /* Structured Extended Feature Flags Enumeration Leaf */
1652 if (count == 0) {
1653 *eax = 0; /* Maximum ECX value for sub-leaves */
1654 *ebx = env->cpuid_7_0_ebx; /* Feature flags */
1655 *ecx = 0; /* Reserved */
1656 *edx = 0; /* Reserved */
f7911686
YW		 1657 } else {
1658 *eax = 0;
1659 *ebx = 0;
1660 *ecx = 0;
1661 *edx = 0;
1662 }
1663 break;
c6dc6f63
AP		 1664 case 9:
1665 /* Direct Cache Access Information Leaf */
1666 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1667 *ebx = 0;
1668 *ecx = 0;
1669 *edx = 0;
1670 break;
1671 case 0xA:
1672 /* Architectural Performance Monitoring Leaf */
a0fa8208
GN		 1673 if (kvm_enabled()) {
1674 KVMState *s = env->kvm_state;
1675
1676 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1677 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1678 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1679 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1680 } else {
1681 *eax = 0;
1682 *ebx = 0;
1683 *ecx = 0;
1684 *edx = 0;
1685 }
c6dc6f63 1686 break;
51e49430
SY		 1687 case 0xD:
1688 /* Processor Extended State */
1689 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1690 *eax = 0;
1691 *ebx = 0;
1692 *ecx = 0;
1693 *edx = 0;
1694 break;
1695 }
1696 if (kvm_enabled()) {
ba9bc59e
JK		 1697 KVMState *s = env->kvm_state;
1698
1699 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1700 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1701 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1702 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1703 } else {
1704 *eax = 0;
1705 *ebx = 0;
1706 *ecx = 0;
1707 *edx = 0;
1708 }
1709 break;
c6dc6f63
AP		 1710 case 0x80000000:
1711 *eax = env->cpuid_xlevel;
1712 *ebx = env->cpuid_vendor1;
1713 *edx = env->cpuid_vendor2;
1714 *ecx = env->cpuid_vendor3;
1715 break;
1716 case 0x80000001:
1717 *eax = env->cpuid_version;
1718 *ebx = 0;
1719 *ecx = env->cpuid_ext3_features;
1720 *edx = env->cpuid_ext2_features;
1721
1722 /* The Linux kernel checks for the CMPLegacy bit and
1723 * discards multiple thread information if it is set.
1724 * So dont set it here for Intel to make Linux guests happy.
1725 */
1726 if (env->nr_cores * env->nr_threads > 1) {
1727 uint32_t tebx, tecx, tedx;
1728 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1729 if (tebx != CPUID_VENDOR_INTEL_1 ||
1730 tedx != CPUID_VENDOR_INTEL_2 ||
1731 tecx != CPUID_VENDOR_INTEL_3) {
1732 *ecx |= 1 << 1; /* CmpLegacy bit */
1733 }
1734 }
c6dc6f63
AP		 1735 break;
1736 case 0x80000002:
1737 case 0x80000003:
1738 case 0x80000004:
1739 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1740 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1741 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1742 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1743 break;
1744 case 0x80000005:
1745 /* cache info (L1 cache) */
1746 *eax = 0x01ff01ff;
1747 *ebx = 0x01ff01ff;
1748 *ecx = 0x40020140;
1749 *edx = 0x40020140;
1750 break;
1751 case 0x80000006:
1752 /* cache info (L2 cache) */
1753 *eax = 0;
1754 *ebx = 0x42004200;
1755 *ecx = 0x02008140;
1756 *edx = 0;
1757 break;
1758 case 0x80000008:
1759 /* virtual & phys address size in low 2 bytes. */
1760/* XXX: This value must match the one used in the MMU code. */
1761 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1762 /* 64 bit processor */
1763/* XXX: The physical address space is limited to 42 bits in exec.c. */
1764 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1765 } else {
1766 if (env->cpuid_features & CPUID_PSE36)
1767 *eax = 0x00000024; /* 36 bits physical */
1768 else
1769 *eax = 0x00000020; /* 32 bits physical */
1770 }
1771 *ebx = 0;
1772 *ecx = 0;
1773 *edx = 0;
1774 if (env->nr_cores * env->nr_threads > 1) {
1775 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1776 }
1777 break;
1778 case 0x8000000A:
296acb64
JR		 1779 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1780 *eax = 0x00000001; /* SVM Revision */
1781 *ebx = 0x00000010; /* nr of ASIDs */
1782 *ecx = 0;
1783 *edx = env->cpuid_svm_features; /* optional features */
1784 } else {
1785 *eax = 0;
1786 *ebx = 0;
1787 *ecx = 0;
1788 *edx = 0;
1789 }
c6dc6f63 1790 break;
b3baa152 1791 case 0xC0000000:
1792 *eax = env->cpuid_xlevel2;
1793 *ebx = 0;
1794 *ecx = 0;
1795 *edx = 0;
1796 break;
1797 case 0xC0000001:
1798 /* Support for VIA CPU's CPUID instruction */
1799 *eax = env->cpuid_version;
1800 *ebx = 0;
1801 *ecx = 0;
1802 *edx = env->cpuid_ext4_features;
1803 break;
1804 case 0xC0000002:
1805 case 0xC0000003:
1806 case 0xC0000004:
1807 /* Reserved for the future, and now filled with zero */
1808 *eax = 0;
1809 *ebx = 0;
1810 *ecx = 0;
1811 *edx = 0;
1812 break;
c6dc6f63
AP		 1813 default:
1814 /* reserved values: zero */
1815 *eax = 0;
1816 *ebx = 0;
1817 *ecx = 0;
1818 *edx = 0;
1819 break;
1820 }
1821}
5fd2087a
AF		 1822
1823/* CPUClass::reset() */
1824static void x86_cpu_reset(CPUState *s)
1825{
1826 X86CPU *cpu = X86_CPU(s);
1827 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1828 CPUX86State *env = &cpu->env;
c1958aea
AF		 1829 int i;
1830
1831 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1832 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1833 log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
1834 }
5fd2087a
AF		 1835
1836 xcc->parent_reset(s);
1837
c1958aea
AF		 1838
1839 memset(env, 0, offsetof(CPUX86State, breakpoints));
1840
1841 tlb_flush(env, 1);
1842
1843 env->old_exception = -1;
1844
1845 /* init to reset state */
1846
1847#ifdef CONFIG_SOFTMMU
1848 env->hflags |= HF_SOFTMMU_MASK;
1849#endif
1850 env->hflags2 |= HF2_GIF_MASK;
1851
1852 cpu_x86_update_cr0(env, 0x60000010);
1853 env->a20_mask = ~0x0;
1854 env->smbase = 0x30000;
1855
1856 env->idt.limit = 0xffff;
1857 env->gdt.limit = 0xffff;
1858 env->ldt.limit = 0xffff;
1859 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1860 env->tr.limit = 0xffff;
1861 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1862
1863 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1864 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1865 DESC_R_MASK | DESC_A_MASK);
1866 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1867 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1868 DESC_A_MASK);
1869 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1870 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1871 DESC_A_MASK);
1872 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1873 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1874 DESC_A_MASK);
1875 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1876 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1877 DESC_A_MASK);
1878 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1879 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1880 DESC_A_MASK);
1881
1882 env->eip = 0xfff0;
1883 env->regs[R_EDX] = env->cpuid_version;
1884
1885 env->eflags = 0x2;
1886
1887 /* FPU init */
1888 for (i = 0; i < 8; i++) {
1889 env->fptags[i] = 1;
1890 }
1891 env->fpuc = 0x37f;
1892
1893 env->mxcsr = 0x1f80;
1894
1895 env->pat = 0x0007040600070406ULL;
1896 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1897
1898 memset(env->dr, 0, sizeof(env->dr));
1899 env->dr[6] = DR6_FIXED_1;
1900 env->dr[7] = DR7_FIXED_1;
1901 cpu_breakpoint_remove_all(env, BP_CPU);
1902 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM		 1903
1904#if !defined(CONFIG_USER_ONLY)
1905 /* We hard-wire the BSP to the first CPU. */
1906 if (env->cpu_index == 0) {
1907 apic_designate_bsp(env->apic_state);
1908 }
1909
1910 env->halted = !cpu_is_bsp(cpu);
1911#endif
5fd2087a
AF		 1912}
1913
dd673288
IM		 1914#ifndef CONFIG_USER_ONLY
1915bool cpu_is_bsp(X86CPU *cpu)
1916{
1917 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
1918}
65dee380
IM		 1919
1920/* TODO: remove me, when reset over QOM tree is implemented */
1921static void x86_cpu_machine_reset_cb(void *opaque)
1922{
1923 X86CPU *cpu = opaque;
1924 cpu_reset(CPU(cpu));
1925}
dd673288
IM		 1926#endif
1927
de024815
AF		 1928static void mce_init(X86CPU *cpu)
1929{
1930 CPUX86State *cenv = &cpu->env;
1931 unsigned int bank;
1932
1933 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
1934 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
1935 (CPUID_MCE | CPUID_MCA)) {
1936 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
1937 cenv->mcg_ctl = ~(uint64_t)0;
1938 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
1939 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
1940 }
1941 }
1942}
1943
7a059953
AF		 1944void x86_cpu_realize(Object *obj, Error **errp)
1945{
1946 X86CPU *cpu = X86_CPU(obj);
1947
65dee380
IM		 1948#ifndef CONFIG_USER_ONLY
1949 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
1950#endif
1951
7a059953
AF		 1952 mce_init(cpu);
1953 qemu_init_vcpu(&cpu->env);
65dee380 1954 cpu_reset(CPU(cpu));
7a059953
AF		 1955}
1956
de024815
AF		 1957static void x86_cpu_initfn(Object *obj)
1958{
1959 X86CPU *cpu = X86_CPU(obj);
1960 CPUX86State *env = &cpu->env;
d65e9815 1961 static int inited;
de024815
AF		 1962
1963 cpu_exec_init(env);
71ad61d3
AF		 1964
1965 object_property_add(obj, "family", "int",
95b8519d 1966 x86_cpuid_version_get_family,
71ad61d3 1967 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 1968 object_property_add(obj, "model", "int",
67e30c83 1969 x86_cpuid_version_get_model,
c5291a4f 1970 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 1971 object_property_add(obj, "stepping", "int",
35112e41 1972 x86_cpuid_version_get_stepping,
036e2222 1973 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 1974 object_property_add(obj, "level", "int",
1975 x86_cpuid_get_level,
1976 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 1977 object_property_add(obj, "xlevel", "int",
1978 x86_cpuid_get_xlevel,
1979 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 1980 object_property_add_str(obj, "vendor",
1981 x86_cpuid_get_vendor,
1982 x86_cpuid_set_vendor, NULL);
938d4c25 1983 object_property_add_str(obj, "model-id",
63e886eb 1984 x86_cpuid_get_model_id,
938d4c25 1985 x86_cpuid_set_model_id, NULL);
89e48965
AF		 1986 object_property_add(obj, "tsc-frequency", "int",
1987 x86_cpuid_get_tsc_freq,
1988 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
71ad61d3 1989
de024815 1990 env->cpuid_apic_id = env->cpu_index;
d65e9815
IM		 1991
1992 /* init various static tables used in TCG mode */
1993 if (tcg_enabled() && !inited) {
1994 inited = 1;
1995 optimize_flags_init();
1996#ifndef CONFIG_USER_ONLY
1997 cpu_set_debug_excp_handler(breakpoint_handler);
1998#endif
1999 }
de024815
AF		 2000}
2001
5fd2087a
AF		 2002static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2003{
2004 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2005 CPUClass *cc = CPU_CLASS(oc);
2006
2007 xcc->parent_reset = cc->reset;
2008 cc->reset = x86_cpu_reset;
2009}
2010
2011static const TypeInfo x86_cpu_type_info = {
2012 .name = TYPE_X86_CPU,
2013 .parent = TYPE_CPU,
2014 .instance_size = sizeof(X86CPU),
de024815 2015 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 2016 .abstract = false,
2017 .class_size = sizeof(X86CPUClass),
2018 .class_init = x86_cpu_common_class_init,
2019};
2020
2021static void x86_cpu_register_types(void)
2022{
2023 type_register_static(&x86_cpu_type_info);
2024}
2025
2026type_init(x86_cpu_register_types)
Qemu copy for testing