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target-i386: Report hyperv feature words through qom
[mirror_qemu.git] / target-i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
6410848b 26#include "sysemu/kvm_int.h"
1d31f66b 27#include "kvm_i386.h"
50efe82c
AS		 28#include "hyperv.h"
29
022c62cb 30#include "exec/gdbstub.h"
1de7afc9
PB		 31#include "qemu/host-utils.h"
32#include "qemu/config-file.h"
1c4a55db 33#include "qemu/error-report.h"
0d09e41a
PB		 34#include "hw/i386/pc.h"
35#include "hw/i386/apic.h"
e0723c45
PB		 36#include "hw/i386/apic_internal.h"
37#include "hw/i386/apic-msidef.h"
50efe82c 38
022c62cb 39#include "exec/ioport.h"
73aa529a 40#include "standard-headers/asm-x86/hyperv.h"
a2cb15b0 41#include "hw/pci/pci.h"
15eafc2e 42#include "hw/pci/msi.h"
68bfd0ad 43#include "migration/migration.h"
4c663752 44#include "exec/memattrs.h"
05330448
AL		 45
46//#define DEBUG_KVM
47
48#ifdef DEBUG_KVM
8c0d577e 49#define DPRINTF(fmt, ...) \
05330448
AL		 50 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
51#else
8c0d577e 52#define DPRINTF(fmt, ...) \
05330448
AL		 53 do { } while (0)
54#endif
55
1a03675d
GC		 56#define MSR_KVM_WALL_CLOCK 0x11
57#define MSR_KVM_SYSTEM_TIME 0x12
58
d1138251
EH		 59/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
60 * 255 kvm_msr_entry structs */
61#define MSR_BUF_SIZE 4096
d71b62a1 62
c0532a76
MT		 63#ifndef BUS_MCEERR_AR
64#define BUS_MCEERR_AR 4
65#endif
66#ifndef BUS_MCEERR_AO
67#define BUS_MCEERR_AO 5
68#endif
69
94a8d39a
JK		 70const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
71 KVM_CAP_INFO(SET_TSS_ADDR),
72 KVM_CAP_INFO(EXT_CPUID),
73 KVM_CAP_INFO(MP_STATE),
74 KVM_CAP_LAST_INFO
75};
25d2e361 76
c3a3a7d3
JK		 77static bool has_msr_star;
78static bool has_msr_hsave_pa;
c9b8f6b6 79static bool has_msr_tsc_aux;
f28558d3 80static bool has_msr_tsc_adjust;
aa82ba54 81static bool has_msr_tsc_deadline;
df67696e 82static bool has_msr_feature_control;
c5999bfc 83static bool has_msr_async_pf_en;
bc9a839d 84static bool has_msr_pv_eoi_en;
21e87c46 85static bool has_msr_misc_enable;
fc12d72e 86static bool has_msr_smbase;
79e9ebeb 87static bool has_msr_bndcfgs;
917367aa 88static bool has_msr_kvm_steal_time;
25d2e361 89static int lm_capable_kernel;
7bc3d711
PB		 90static bool has_msr_hv_hypercall;
91static bool has_msr_hv_vapic;
48a5f3bc 92static bool has_msr_hv_tsc;
f2a53c9e 93static bool has_msr_hv_crash;
744b8a94 94static bool has_msr_hv_reset;
8c145d7c 95static bool has_msr_hv_vpindex;
46eb8f98 96static bool has_msr_hv_runtime;
866eea9a 97static bool has_msr_hv_synic;
ff99aa64 98static bool has_msr_hv_stimer;
d1ae67f6 99static bool has_msr_mtrr;
18cd2c17 100static bool has_msr_xss;
b827df58 101
0d894367
PB		 102static bool has_msr_architectural_pmu;
103static uint32_t num_architectural_pmu_counters;
104
28143b40
TH		 105static int has_xsave;
106static int has_xcrs;
107static int has_pit_state2;
108
494e95e9
CP		 109static struct kvm_cpuid2 *cpuid_cache;
110
28143b40
TH		 111int kvm_has_pit_state2(void)
112{
113 return has_pit_state2;
114}
115
355023f2
PB		 116bool kvm_has_smm(void)
117{
118 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
119}
120
1d31f66b
PM		 121bool kvm_allows_irq0_override(void)
122{
123 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
124}
125
0fd7e098
LL		 126static int kvm_get_tsc(CPUState *cs)
127{
128 X86CPU *cpu = X86_CPU(cs);
129 CPUX86State *env = &cpu->env;
130 struct {
131 struct kvm_msrs info;
132 struct kvm_msr_entry entries[1];
133 } msr_data;
134 int ret;
135
136 if (env->tsc_valid) {
137 return 0;
138 }
139
140 msr_data.info.nmsrs = 1;
141 msr_data.entries[0].index = MSR_IA32_TSC;
142 env->tsc_valid = !runstate_is_running();
143
144 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
145 if (ret < 0) {
146 return ret;
147 }
148
48e1a45c 149 assert(ret == 1);
0fd7e098
LL		 150 env->tsc = msr_data.entries[0].data;
151 return 0;
152}
153
154static inline void do_kvm_synchronize_tsc(void *arg)
155{
156 CPUState *cpu = arg;
157
158 kvm_get_tsc(cpu);
159}
160
161void kvm_synchronize_all_tsc(void)
162{
163 CPUState *cpu;
164
165 if (kvm_enabled()) {
166 CPU_FOREACH(cpu) {
167 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
168 }
169 }
170}
171
b827df58
AK		 172static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
173{
174 struct kvm_cpuid2 *cpuid;
175 int r, size;
176
177 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 178 cpuid = g_malloc0(size);
b827df58
AK		 179 cpuid->nent = max;
180 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 181 if (r == 0 && cpuid->nent >= max) {
182 r = -E2BIG;
183 }
b827df58
AK		 184 if (r < 0) {
185 if (r == -E2BIG) {
7267c094 186 g_free(cpuid);
b827df58
AK		 187 return NULL;
188 } else {
189 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
190 strerror(-r));
191 exit(1);
192 }
193 }
194 return cpuid;
195}
196
dd87f8a6
EH		 197/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
198 * for all entries.
199 */
200static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
201{
202 struct kvm_cpuid2 *cpuid;
203 int max = 1;
494e95e9
CP		 204
205 if (cpuid_cache != NULL) {
206 return cpuid_cache;
207 }
dd87f8a6
EH		 208 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
209 max *= 2;
210 }
494e95e9 211 cpuid_cache = cpuid;
dd87f8a6
EH		 212 return cpuid;
213}
214
a443bc34 215static const struct kvm_para_features {
0c31b744
GC		 216 int cap;
217 int feature;
218} para_features[] = {
219 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
220 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
221 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 222 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 223};
224
ba9bc59e 225static int get_para_features(KVMState *s)
0c31b744
GC		 226{
227 int i, features = 0;
228
8e03c100 229 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 230 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 231 features |= (1 << para_features[i].feature);
232 }
233 }
234
235 return features;
236}
0c31b744
GC		 237
238
829ae2f9
EH		 239/* Returns the value for a specific register on the cpuid entry
240 */
241static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
242{
243 uint32_t ret = 0;
244 switch (reg) {
245 case R_EAX:
246 ret = entry->eax;
247 break;
248 case R_EBX:
249 ret = entry->ebx;
250 break;
251 case R_ECX:
252 ret = entry->ecx;
253 break;
254 case R_EDX:
255 ret = entry->edx;
256 break;
257 }
258 return ret;
259}
260
4fb73f1d
EH		 261/* Find matching entry for function/index on kvm_cpuid2 struct
262 */
263static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
264 uint32_t function,
265 uint32_t index)
266{
267 int i;
268 for (i = 0; i < cpuid->nent; ++i) {
269 if (cpuid->entries[i].function == function &&
270 cpuid->entries[i].index == index) {
271 return &cpuid->entries[i];
272 }
273 }
274 /* not found: */
275 return NULL;
276}
277
ba9bc59e 278uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 279 uint32_t index, int reg)
b827df58
AK		 280{
281 struct kvm_cpuid2 *cpuid;
b827df58
AK		 282 uint32_t ret = 0;
283 uint32_t cpuid_1_edx;
8c723b79 284 bool found = false;
b827df58 285
dd87f8a6 286 cpuid = get_supported_cpuid(s);
b827df58 287
4fb73f1d
EH		 288 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
289 if (entry) {
290 found = true;
291 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 292 }
293
7b46e5ce
EH		 294 /* Fixups for the data returned by KVM, below */
295
c2acb022
EH		 296 if (function == 1 && reg == R_EDX) {
297 /* KVM before 2.6.30 misreports the following features */
298 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 299 } else if (function == 1 && reg == R_ECX) {
300 /* We can set the hypervisor flag, even if KVM does not return it on
301 * GET_SUPPORTED_CPUID
302 */
303 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 304 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
305 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
306 * and the irqchip is in the kernel.
307 */
308 if (kvm_irqchip_in_kernel() &&
309 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
310 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
311 }
41e5e76d
EH		 312
313 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
314 * without the in-kernel irqchip
315 */
316 if (!kvm_irqchip_in_kernel()) {
317 ret &= ~CPUID_EXT_X2APIC;
b827df58 318 }
28b8e4d0
JK		 319 } else if (function == 6 && reg == R_EAX) {
320 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
c2acb022
EH		 321 } else if (function == 0x80000001 && reg == R_EDX) {
322 /* On Intel, kvm returns cpuid according to the Intel spec,
323 * so add missing bits according to the AMD spec:
324 */
325 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
326 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
b827df58
AK		 327 }
328
0c31b744 329 /* fallback for older kernels */
8c723b79 330 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 331 ret = get_para_features(s);
b9bec74b 332 }
0c31b744
GC		 333
334 return ret;
bb0300dc 335}
bb0300dc 336
3c85e74f
HY		 337typedef struct HWPoisonPage {
338 ram_addr_t ram_addr;
339 QLIST_ENTRY(HWPoisonPage) list;
340} HWPoisonPage;
341
342static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
343 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
344
345static void kvm_unpoison_all(void *param)
346{
347 HWPoisonPage *page, *next_page;
348
349 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
350 QLIST_REMOVE(page, list);
351 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 352 g_free(page);
3c85e74f
HY		 353 }
354}
355
3c85e74f
HY		 356static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
357{
358 HWPoisonPage *page;
359
360 QLIST_FOREACH(page, &hwpoison_page_list, list) {
361 if (page->ram_addr == ram_addr) {
362 return;
363 }
364 }
ab3ad07f 365 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 366 page->ram_addr = ram_addr;
367 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
368}
369
e7701825
MT		 370static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
371 int *max_banks)
372{
373 int r;
374
14a09518 375 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 376 if (r > 0) {
377 *max_banks = r;
378 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
379 }
380 return -ENOSYS;
381}
382
bee615d4 383static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 384{
bee615d4 385 CPUX86State *env = &cpu->env;
c34d440a
JK		 386 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
387 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
388 uint64_t mcg_status = MCG_STATUS_MCIP;
e7701825 389
c34d440a
JK		 390 if (code == BUS_MCEERR_AR) {
391 status |= MCI_STATUS_AR | 0x134;
392 mcg_status |= MCG_STATUS_EIPV;
393 } else {
394 status |= 0xc0;
395 mcg_status |= MCG_STATUS_RIPV;
419fb20a 396 }
8c5cf3b6 397 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
c34d440a
JK		 398 (MCM_ADDR_PHYS << 6) | 0xc,
399 cpu_x86_support_mca_broadcast(env) ?
400 MCE_INJECT_BROADCAST : 0);
419fb20a 401}
419fb20a
JK		 402
403static void hardware_memory_error(void)
404{
405 fprintf(stderr, "Hardware memory error!\n");
406 exit(1);
407}
408
20d695a9 409int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 410{
20d695a9
AF		 411 X86CPU *cpu = X86_CPU(c);
412 CPUX86State *env = &cpu->env;
419fb20a 413 ram_addr_t ram_addr;
a8170e5e 414 hwaddr paddr;
419fb20a
JK		 415
416 if ((env->mcg_cap & MCG_SER_P) && addr
c34d440a 417 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
07bdaa41
PB		 418 ram_addr = qemu_ram_addr_from_host(addr);
419 if (ram_addr == RAM_ADDR_INVALID ||
a60f24b5 420 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
419fb20a
JK		 421 fprintf(stderr, "Hardware memory error for memory used by "
422 "QEMU itself instead of guest system!\n");
423 /* Hope we are lucky for AO MCE */
424 if (code == BUS_MCEERR_AO) {
425 return 0;
426 } else {
427 hardware_memory_error();
428 }
429 }
3c85e74f 430 kvm_hwpoison_page_add(ram_addr);
bee615d4 431 kvm_mce_inject(cpu, paddr, code);
e56ff191 432 } else {
419fb20a
JK		 433 if (code == BUS_MCEERR_AO) {
434 return 0;
435 } else if (code == BUS_MCEERR_AR) {
436 hardware_memory_error();
437 } else {
438 return 1;
439 }
440 }
441 return 0;
442}
443
444int kvm_arch_on_sigbus(int code, void *addr)
445{
182735ef
AF		 446 X86CPU *cpu = X86_CPU(first_cpu);
447
448 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
419fb20a 449 ram_addr_t ram_addr;
a8170e5e 450 hwaddr paddr;
419fb20a
JK		 451
452 /* Hope we are lucky for AO MCE */
07bdaa41
PB		 453 ram_addr = qemu_ram_addr_from_host(addr);
454 if (ram_addr == RAM_ADDR_INVALID ||
182735ef 455 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
a60f24b5 456 addr, &paddr)) {
419fb20a
JK		 457 fprintf(stderr, "Hardware memory error for memory used by "
458 "QEMU itself instead of guest system!: %p\n", addr);
459 return 0;
460 }
3c85e74f 461 kvm_hwpoison_page_add(ram_addr);
182735ef 462 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
e56ff191 463 } else {
419fb20a
JK		 464 if (code == BUS_MCEERR_AO) {
465 return 0;
466 } else if (code == BUS_MCEERR_AR) {
467 hardware_memory_error();
468 } else {
469 return 1;
470 }
471 }
472 return 0;
473}
e7701825 474
1bc22652 475static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 476{
1bc22652
AF		 477 CPUX86State *env = &cpu->env;
478
ab443475
JK		 479 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
480 unsigned int bank, bank_num = env->mcg_cap & 0xff;
481 struct kvm_x86_mce mce;
482
483 env->exception_injected = -1;
484
485 /*
486 * There must be at least one bank in use if an MCE is pending.
487 * Find it and use its values for the event injection.
488 */
489 for (bank = 0; bank < bank_num; bank++) {
490 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
491 break;
492 }
493 }
494 assert(bank < bank_num);
495
496 mce.bank = bank;
497 mce.status = env->mce_banks[bank * 4 + 1];
498 mce.mcg_status = env->mcg_status;
499 mce.addr = env->mce_banks[bank * 4 + 2];
500 mce.misc = env->mce_banks[bank * 4 + 3];
501
1bc22652 502 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 503 }
ab443475
JK		 504 return 0;
505}
506
1dfb4dd9 507static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 508{
317ac620 509 CPUX86State *env = opaque;
b8cc45d6
GC		 510
511 if (running) {
512 env->tsc_valid = false;
513 }
514}
515
83b17af5 516unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 517{
83b17af5 518 X86CPU *cpu = X86_CPU(cs);
7e72a45c 519 return cpu->apic_id;
b164e48e
EH		 520}
521
92067bf4
IM		 522#ifndef KVM_CPUID_SIGNATURE_NEXT
523#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
524#endif
525
526static bool hyperv_hypercall_available(X86CPU *cpu)
527{
528 return cpu->hyperv_vapic ||
529 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
530}
531
532static bool hyperv_enabled(X86CPU *cpu)
533{
7bc3d711
PB		 534 CPUState *cs = CPU(cpu);
535 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
536 (hyperv_hypercall_available(cpu) ||
48a5f3bc 537 cpu->hyperv_time ||
f2a53c9e 538 cpu->hyperv_relaxed_timing ||
744b8a94 539 cpu->hyperv_crash ||
8c145d7c 540 cpu->hyperv_reset ||
46eb8f98 541 cpu->hyperv_vpindex ||
866eea9a 542 cpu->hyperv_runtime ||
ff99aa64
AS		 543 cpu->hyperv_synic ||
544 cpu->hyperv_stimer);
92067bf4
IM		 545}
546
5031283d
HZ		 547static int kvm_arch_set_tsc_khz(CPUState *cs)
548{
549 X86CPU *cpu = X86_CPU(cs);
550 CPUX86State *env = &cpu->env;
551 int r;
552
553 if (!env->tsc_khz) {
554 return 0;
555 }
556
557 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
558 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
559 -ENOTSUP;
560 if (r < 0) {
561 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
562 * TSC frequency doesn't match the one we want.
563 */
564 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
565 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
566 -ENOTSUP;
567 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
568 error_report("warning: TSC frequency mismatch between "
d6276d26
EH		 569 "VM (%" PRId64 " kHz) and host (%d kHz), "
570 "and TSC scaling unavailable",
571 env->tsc_khz, cur_freq);
5031283d
HZ		 572 return r;
573 }
574 }
575
576 return 0;
577}
578
c35bd19a
EY		 579static int hyperv_handle_properties(CPUState *cs)
580{
581 X86CPU *cpu = X86_CPU(cs);
582 CPUX86State *env = &cpu->env;
583
584 if (cpu->hyperv_relaxed_timing) {
585 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
586 }
587 if (cpu->hyperv_vapic) {
588 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
589 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
590 has_msr_hv_vapic = true;
591 }
592 if (cpu->hyperv_time &&
593 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
594 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
595 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
596 env->features[FEAT_HYPERV_EAX] |= 0x200;
597 has_msr_hv_tsc = true;
598 }
599 if (cpu->hyperv_crash && has_msr_hv_crash) {
600 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
601 }
602 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
603 if (cpu->hyperv_reset && has_msr_hv_reset) {
604 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
605 }
606 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
607 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
608 }
609 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
610 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
611 }
612 if (cpu->hyperv_synic) {
613 int sint;
614
615 if (!has_msr_hv_synic ||
616 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
617 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
618 return -ENOSYS;
619 }
620
621 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
622 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
623 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
624 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
625 }
626 }
627 if (cpu->hyperv_stimer) {
628 if (!has_msr_hv_stimer) {
629 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
630 return -ENOSYS;
631 }
632 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
633 }
634 return 0;
635}
636
68bfd0ad
MT		 637static Error *invtsc_mig_blocker;
638
f8bb0565 639#define KVM_MAX_CPUID_ENTRIES 100
0893d460 640
20d695a9 641int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 642{
643 struct {
486bd5a2 644 struct kvm_cpuid2 cpuid;
f8bb0565 645 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 646 } QEMU_PACKED cpuid_data;
20d695a9
AF		 647 X86CPU *cpu = X86_CPU(cs);
648 CPUX86State *env = &cpu->env;
486bd5a2 649 uint32_t limit, i, j, cpuid_i;
a33609ca 650 uint32_t unused;
bb0300dc 651 struct kvm_cpuid_entry2 *c;
bb0300dc 652 uint32_t signature[3];
234cc647 653 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 654 int r;
05330448 655
ef4cbe14
SW		 656 memset(&cpuid_data, 0, sizeof(cpuid_data));
657
05330448
AL		 658 cpuid_i = 0;
659
bb0300dc 660 /* Paravirtualization CPUIDs */
234cc647
PB		 661 if (hyperv_enabled(cpu)) {
662 c = &cpuid_data.entries[cpuid_i++];
663 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 664 if (!cpu->hyperv_vendor_id) {
665 memcpy(signature, "Microsoft Hv", 12);
666 } else {
667 size_t len = strlen(cpu->hyperv_vendor_id);
668
669 if (len > 12) {
670 error_report("hv-vendor-id truncated to 12 characters");
671 len = 12;
672 }
673 memset(signature, 0, 12);
674 memcpy(signature, cpu->hyperv_vendor_id, len);
675 }
eab70139 676 c->eax = HYPERV_CPUID_MIN;
234cc647
PB		 677 c->ebx = signature[0];
678 c->ecx = signature[1];
679 c->edx = signature[2];
0c31b744 680
234cc647
PB		 681 c = &cpuid_data.entries[cpuid_i++];
682 c->function = HYPERV_CPUID_INTERFACE;
eab70139
VR		 683 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
684 c->eax = signature[0];
234cc647
PB		 685 c->ebx = 0;
686 c->ecx = 0;
687 c->edx = 0;
eab70139
VR		 688
689 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 690 c->function = HYPERV_CPUID_VERSION;
691 c->eax = 0x00001bbc;
692 c->ebx = 0x00060001;
693
694 c = &cpuid_data.entries[cpuid_i++];
eab70139 695 c->function = HYPERV_CPUID_FEATURES;
c35bd19a
EY		 696 r = hyperv_handle_properties(cs);
697 if (r) {
698 return r;
46eb8f98 699 }
c35bd19a
EY		 700 c->eax = env->features[FEAT_HYPERV_EAX];
701 c->ebx = env->features[FEAT_HYPERV_EBX];
702 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 703
eab70139 704 c = &cpuid_data.entries[cpuid_i++];
eab70139 705 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
92067bf4 706 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 707 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
708 }
7bc3d711 709 if (has_msr_hv_vapic) {
eab70139
VR		 710 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
711 }
92067bf4 712 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 713
714 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 715 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
716 c->eax = 0x40;
717 c->ebx = 0x40;
718
234cc647 719 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 720 has_msr_hv_hypercall = true;
eab70139
VR		 721 }
722
f522d2ac
AW		 723 if (cpu->expose_kvm) {
724 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
725 c = &cpuid_data.entries[cpuid_i++];
726 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 727 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 728 c->ebx = signature[0];
729 c->ecx = signature[1];
730 c->edx = signature[2];
234cc647 731
f522d2ac
AW		 732 c = &cpuid_data.entries[cpuid_i++];
733 c->function = KVM_CPUID_FEATURES | kvm_base;
734 c->eax = env->features[FEAT_KVM];
234cc647 735
f522d2ac 736 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
bb0300dc 737
f522d2ac 738 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
bc9a839d 739
f522d2ac
AW		 740 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
741 }
917367aa 742
a33609ca 743 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 744
745 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 746 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
747 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
748 abort();
749 }
bb0300dc 750 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 751
752 switch (i) {
a36b1029
AL		 753 case 2: {
754 /* Keep reading function 2 till all the input is received */
755 int times;
756
a36b1029 757 c->function = i;
a33609ca
AL		 758 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
759 KVM_CPUID_FLAG_STATE_READ_NEXT;
760 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
761 times = c->eax & 0xff;
a36b1029
AL		 762
763 for (j = 1; j < times; ++j) {
f8bb0565
IM		 764 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
765 fprintf(stderr, "cpuid_data is full, no space for "
766 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
767 abort();
768 }
a33609ca 769 c = &cpuid_data.entries[cpuid_i++];
a36b1029 770 c->function = i;
a33609ca
AL		 771 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
772 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 773 }
774 break;
775 }
486bd5a2
AL		 776 case 4:
777 case 0xb:
778 case 0xd:
779 for (j = 0; ; j++) {
31e8c696
AP		 780 if (i == 0xd && j == 64) {
781 break;
782 }
486bd5a2
AL		 783 c->function = i;
784 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
785 c->index = j;
a33609ca 786 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 787
b9bec74b 788 if (i == 4 && c->eax == 0) {
486bd5a2 789 break;
b9bec74b
JK		 790 }
791 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 792 break;
b9bec74b
JK		 793 }
794 if (i == 0xd && c->eax == 0) {
31e8c696 795 continue;
b9bec74b 796 }
f8bb0565
IM		 797 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
798 fprintf(stderr, "cpuid_data is full, no space for "
799 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
800 abort();
801 }
a33609ca 802 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 803 }
804 break;
805 default:
486bd5a2 806 c->function = i;
a33609ca
AL		 807 c->flags = 0;
808 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 809 break;
810 }
05330448 811 }
0d894367
PB		 812
813 if (limit >= 0x0a) {
814 uint32_t ver;
815
816 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
817 if ((ver & 0xff) > 0) {
818 has_msr_architectural_pmu = true;
819 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
820
821 /* Shouldn't be more than 32, since that's the number of bits
822 * available in EBX to tell us _which_ counters are available.
823 * Play it safe.
824 */
825 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
826 num_architectural_pmu_counters = MAX_GP_COUNTERS;
827 }
828 }
829 }
830
a33609ca 831 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 832
833 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 834 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
835 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
836 abort();
837 }
bb0300dc 838 c = &cpuid_data.entries[cpuid_i++];
05330448 839
05330448 840 c->function = i;
a33609ca
AL		 841 c->flags = 0;
842 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 843 }
844
b3baa152
BW		 845 /* Call Centaur's CPUID instructions they are supported. */
846 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 847 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
848
849 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 850 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
851 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
852 abort();
853 }
b3baa152
BW		 854 c = &cpuid_data.entries[cpuid_i++];
855
856 c->function = i;
857 c->flags = 0;
858 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
859 }
860 }
861
05330448
AL		 862 cpuid_data.cpuid.nent = cpuid_i;
863
e7701825 864 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 865 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 866 (CPUID_MCE | CPUID_MCA)
a60f24b5 867 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 868 uint64_t mcg_cap, unsupported_caps;
e7701825 869 int banks;
32a42024 870 int ret;
e7701825 871
a60f24b5 872 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 873 if (ret < 0) {
874 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
875 return ret;
e7701825 876 }
75d49497 877
2590f15b 878 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 879 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 880 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 881 return -ENOTSUP;
75d49497 882 }
49b69cbf 883
5120901a
EH		 884 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
885 if (unsupported_caps) {
886 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
887 unsupported_caps);
888 }
889
2590f15b
EH		 890 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
891 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 892 if (ret < 0) {
893 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
894 return ret;
895 }
e7701825 896 }
e7701825 897
b8cc45d6
GC		 898 qemu_add_vm_change_state_handler(cpu_update_state, env);
899
df67696e
LJ		 900 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
901 if (c) {
902 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
903 !!(c->ecx & CPUID_EXT_SMX);
904 }
905
68bfd0ad
MT		 906 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
907 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
908 /* for migration */
909 error_setg(&invtsc_mig_blocker,
910 "State blocked by non-migratable CPU device"
911 " (invtsc flag)");
912 migrate_add_blocker(invtsc_mig_blocker);
913 /* for savevm */
914 vmstate_x86_cpu.unmigratable = 1;
915 }
916
7e680753 917 cpuid_data.cpuid.padding = 0;
1bc22652 918 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
fdc9c41a
JK		 919 if (r) {
920 return r;
921 }
e7429073 922
5031283d
HZ		 923 r = kvm_arch_set_tsc_khz(cs);
924 if (r < 0) {
925 return r;
e7429073 926 }
e7429073 927
bcffbeeb
HZ		 928 /* vcpu's TSC frequency is either specified by user, or following
929 * the value used by KVM if the former is not present. In the
930 * latter case, we query it from KVM and record in env->tsc_khz,
931 * so that vcpu's TSC frequency can be migrated later via this field.
932 */
933 if (!env->tsc_khz) {
934 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
935 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
936 -ENOTSUP;
937 if (r > 0) {
938 env->tsc_khz = r;
939 }
940 }
941
28143b40 942 if (has_xsave) {
fabacc0f
JK		 943 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
944 }
d71b62a1 945 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 946
d1ae67f6
AW		 947 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
948 has_msr_mtrr = true;
949 }
273c515c
PB		 950 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
951 has_msr_tsc_aux = false;
952 }
d1ae67f6 953
e7429073 954 return 0;
05330448
AL		 955}
956
50a2c6e5 957void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 958{
20d695a9 959 CPUX86State *env = &cpu->env;
dd673288 960
e73223a5 961 env->exception_injected = -1;
0e607a80 962 env->interrupt_injected = -1;
1a5e9d2f 963 env->xcr0 = 1;
ddced198 964 if (kvm_irqchip_in_kernel()) {
dd673288 965 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 966 KVM_MP_STATE_UNINITIALIZED;
967 } else {
968 env->mp_state = KVM_MP_STATE_RUNNABLE;
969 }
caa5af0f
JK		 970}
971
e0723c45
PB		 972void kvm_arch_do_init_vcpu(X86CPU *cpu)
973{
974 CPUX86State *env = &cpu->env;
975
976 /* APs get directly into wait-for-SIPI state. */
977 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
978 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
979 }
980}
981
c3a3a7d3 982static int kvm_get_supported_msrs(KVMState *s)
05330448 983{
75b10c43 984 static int kvm_supported_msrs;
c3a3a7d3 985 int ret = 0;
05330448
AL		 986
987 /* first time */
75b10c43 988 if (kvm_supported_msrs == 0) {
05330448
AL		 989 struct kvm_msr_list msr_list, *kvm_msr_list;
990
75b10c43 991 kvm_supported_msrs = -1;
05330448
AL		 992
993 /* Obtain MSR list from KVM. These are the MSRs that we must
994 * save/restore */
4c9f7372 995 msr_list.nmsrs = 0;
c3a3a7d3 996 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 997 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 998 return ret;
6fb6d245 999 }
d9db889f
JK		 1000 /* Old kernel modules had a bug and could write beyond the provided
1001 memory. Allocate at least a safe amount of 1K. */
7267c094 1002 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1003 msr_list.nmsrs *
1004 sizeof(msr_list.indices[0])));
05330448 1005
55308450 1006 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1007 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1008 if (ret >= 0) {
1009 int i;
1010
1011 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1012 if (kvm_msr_list->indices[i] == MSR_STAR) {
c3a3a7d3 1013 has_msr_star = true;
75b10c43
MT		 1014 continue;
1015 }
1016 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
c3a3a7d3 1017 has_msr_hsave_pa = true;
75b10c43 1018 continue;
05330448 1019 }
c9b8f6b6
AS		 1020 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1021 has_msr_tsc_aux = true;
1022 continue;
1023 }
f28558d3
WA		 1024 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1025 has_msr_tsc_adjust = true;
1026 continue;
1027 }
aa82ba54
LJ		 1028 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1029 has_msr_tsc_deadline = true;
1030 continue;
1031 }
fc12d72e
PB		 1032 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1033 has_msr_smbase = true;
1034 continue;
1035 }
21e87c46
AK		 1036 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1037 has_msr_misc_enable = true;
1038 continue;
1039 }
79e9ebeb
LJ		 1040 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1041 has_msr_bndcfgs = true;
1042 continue;
1043 }
18cd2c17
WL		 1044 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1045 has_msr_xss = true;
1046 continue;
1047 }
f2a53c9e
AS		 1048 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1049 has_msr_hv_crash = true;
1050 continue;
1051 }
744b8a94
AS		 1052 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1053 has_msr_hv_reset = true;
1054 continue;
1055 }
8c145d7c
AS		 1056 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1057 has_msr_hv_vpindex = true;
1058 continue;
1059 }
46eb8f98
AS		 1060 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1061 has_msr_hv_runtime = true;
1062 continue;
1063 }
866eea9a
AS		 1064 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1065 has_msr_hv_synic = true;
1066 continue;
1067 }
ff99aa64
AS		 1068 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1069 has_msr_hv_stimer = true;
1070 continue;
1071 }
05330448
AL		 1072 }
1073 }
1074
7267c094 1075 g_free(kvm_msr_list);
05330448
AL		 1076 }
1077
c3a3a7d3 1078 return ret;
05330448
AL		 1079}
1080
6410848b
PB		 1081static Notifier smram_machine_done;
1082static KVMMemoryListener smram_listener;
1083static AddressSpace smram_address_space;
1084static MemoryRegion smram_as_root;
1085static MemoryRegion smram_as_mem;
1086
1087static void register_smram_listener(Notifier *n, void *unused)
1088{
1089 MemoryRegion *smram =
1090 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1091
1092 /* Outer container... */
1093 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1094 memory_region_set_enabled(&smram_as_root, true);
1095
1096 /* ... with two regions inside: normal system memory with low
1097 * priority, and...
1098 */
1099 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1100 get_system_memory(), 0, ~0ull);
1101 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1102 memory_region_set_enabled(&smram_as_mem, true);
1103
1104 if (smram) {
1105 /* ... SMRAM with higher priority */
1106 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1107 memory_region_set_enabled(smram, true);
1108 }
1109
1110 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1111 kvm_memory_listener_register(kvm_state, &smram_listener,
1112 &smram_address_space, 1);
1113}
1114
b16565b3 1115int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1116{
11076198 1117 uint64_t identity_base = 0xfffbc000;
39d6960a 1118 uint64_t shadow_mem;
20420430 1119 int ret;
25d2e361 1120 struct utsname utsname;
20420430 1121
28143b40
TH		 1122#ifdef KVM_CAP_XSAVE
1123 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1124#endif
1125
1126#ifdef KVM_CAP_XCRS
1127 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1128#endif
1129
1130#ifdef KVM_CAP_PIT_STATE2
1131 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1132#endif
1133
c3a3a7d3 1134 ret = kvm_get_supported_msrs(s);
20420430 1135 if (ret < 0) {
20420430
SY		 1136 return ret;
1137 }
25d2e361
MT		 1138
1139 uname(&utsname);
1140 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1141
4c5b10b7 1142 /*
11076198
JK		 1143 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1144 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1145 * Since these must be part of guest physical memory, we need to allocate
1146 * them, both by setting their start addresses in the kernel and by
1147 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1148 *
1149 * Older KVM versions may not support setting the identity map base. In
1150 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1151 * size.
4c5b10b7 1152 */
11076198
JK		 1153 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1154 /* Allows up to 16M BIOSes. */
1155 identity_base = 0xfeffc000;
1156
1157 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1158 if (ret < 0) {
1159 return ret;
1160 }
4c5b10b7 1161 }
e56ff191 1162
11076198
JK		 1163 /* Set TSS base one page after EPT identity map. */
1164 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1165 if (ret < 0) {
1166 return ret;
1167 }
1168
11076198
JK		 1169 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1170 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1171 if (ret < 0) {
11076198 1172 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1173 return ret;
1174 }
3c85e74f 1175 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1176
4689b77b 1177 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1178 if (shadow_mem != -1) {
1179 shadow_mem /= 4096;
1180 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1181 if (ret < 0) {
1182 return ret;
39d6960a
JK		 1183 }
1184 }
6410848b
PB		 1185
1186 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1187 smram_machine_done.notify = register_smram_listener;
1188 qemu_add_machine_init_done_notifier(&smram_machine_done);
1189 }
11076198 1190 return 0;
05330448 1191}
b9bec74b 1192
05330448
AL		 1193static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1194{
1195 lhs->selector = rhs->selector;
1196 lhs->base = rhs->base;
1197 lhs->limit = rhs->limit;
1198 lhs->type = 3;
1199 lhs->present = 1;
1200 lhs->dpl = 3;
1201 lhs->db = 0;
1202 lhs->s = 1;
1203 lhs->l = 0;
1204 lhs->g = 0;
1205 lhs->avl = 0;
1206 lhs->unusable = 0;
1207}
1208
1209static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1210{
1211 unsigned flags = rhs->flags;
1212 lhs->selector = rhs->selector;
1213 lhs->base = rhs->base;
1214 lhs->limit = rhs->limit;
1215 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1216 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1217 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1218 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1219 lhs->s = (flags & DESC_S_MASK) != 0;
1220 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1221 lhs->g = (flags & DESC_G_MASK) != 0;
1222 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1223 lhs->unusable = !lhs->present;
7e680753 1224 lhs->padding = 0;
05330448
AL		 1225}
1226
1227static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1228{
1229 lhs->selector = rhs->selector;
1230 lhs->base = rhs->base;
1231 lhs->limit = rhs->limit;
4cae9c97
MC		 1232 if (rhs->unusable) {
1233 lhs->flags = 0;
1234 } else {
1235 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1236 (rhs->present * DESC_P_MASK) |
1237 (rhs->dpl << DESC_DPL_SHIFT) |
1238 (rhs->db << DESC_B_SHIFT) |
1239 (rhs->s * DESC_S_MASK) |
1240 (rhs->l << DESC_L_SHIFT) |
1241 (rhs->g * DESC_G_MASK) |
1242 (rhs->avl * DESC_AVL_MASK);
1243 }
05330448
AL		 1244}
1245
1246static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1247{
b9bec74b 1248 if (set) {
05330448 1249 *kvm_reg = *qemu_reg;
b9bec74b 1250 } else {
05330448 1251 *qemu_reg = *kvm_reg;
b9bec74b 1252 }
05330448
AL		 1253}
1254
1bc22652 1255static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1256{
1bc22652 1257 CPUX86State *env = &cpu->env;
05330448
AL		 1258 struct kvm_regs regs;
1259 int ret = 0;
1260
1261 if (!set) {
1bc22652 1262 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1263 if (ret < 0) {
05330448 1264 return ret;
b9bec74b 1265 }
05330448
AL		 1266 }
1267
1268 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1269 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1270 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1271 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1272 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1273 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1274 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1275 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1276#ifdef TARGET_X86_64
1277 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1278 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1279 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1280 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1281 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1282 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1283 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1284 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1285#endif
1286
1287 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1288 kvm_getput_reg(&regs.rip, &env->eip, set);
1289
b9bec74b 1290 if (set) {
1bc22652 1291 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1292 }
05330448
AL		 1293
1294 return ret;
1295}
1296
1bc22652 1297static int kvm_put_fpu(X86CPU *cpu)
05330448 1298{
1bc22652 1299 CPUX86State *env = &cpu->env;
05330448
AL		 1300 struct kvm_fpu fpu;
1301 int i;
1302
1303 memset(&fpu, 0, sizeof fpu);
1304 fpu.fsw = env->fpus & ~(7 << 11);
1305 fpu.fsw |= (env->fpstt & 7) << 11;
1306 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1307 fpu.last_opcode = env->fpop;
1308 fpu.last_ip = env->fpip;
1309 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1310 for (i = 0; i < 8; ++i) {
1311 fpu.ftwx |= (!env->fptags[i]) << i;
1312 }
05330448 1313 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1314 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1315 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1316 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1317 }
05330448
AL		 1318 fpu.mxcsr = env->mxcsr;
1319
1bc22652 1320 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1321}
1322
6b42494b
JK		 1323#define XSAVE_FCW_FSW 0
1324#define XSAVE_FTW_FOP 1
f1665b21
SY		 1325#define XSAVE_CWD_RIP 2
1326#define XSAVE_CWD_RDP 4
1327#define XSAVE_MXCSR 6
1328#define XSAVE_ST_SPACE 8
1329#define XSAVE_XMM_SPACE 40
1330#define XSAVE_XSTATE_BV 128
1331#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1332#define XSAVE_BNDREGS 240
1333#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1334#define XSAVE_OPMASK 272
1335#define XSAVE_ZMM_Hi256 288
1336#define XSAVE_Hi16_ZMM 416
f74eefe0 1337#define XSAVE_PKRU 672
f1665b21 1338
b503717d
EH		 1339#define XSAVE_BYTE_OFFSET(word_offset) \
1340 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1341
1342#define ASSERT_OFFSET(word_offset, field) \
1343 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1344 offsetof(X86XSaveArea, field))
1345
1346ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1347ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1348ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1349ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1350ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1351ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1352ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1353ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1354ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1355ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1356ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1357ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1358ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1359ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1360ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1361
1bc22652 1362static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1363{
1bc22652 1364 CPUX86State *env = &cpu->env;
86cd2ea0 1365 X86XSaveArea *xsave = env->kvm_xsave_buf;
42cc8fa6 1366 uint16_t cwd, swd, twd;
9be38598 1367 int i;
f1665b21 1368
28143b40 1369 if (!has_xsave) {
1bc22652 1370 return kvm_put_fpu(cpu);
b9bec74b 1371 }
f1665b21 1372
f1665b21 1373 memset(xsave, 0, sizeof(struct kvm_xsave));
6115c0a8 1374 twd = 0;
f1665b21
SY		 1375 swd = env->fpus & ~(7 << 11);
1376 swd |= (env->fpstt & 7) << 11;
1377 cwd = env->fpuc;
b9bec74b 1378 for (i = 0; i < 8; ++i) {
f1665b21 1379 twd |= (!env->fptags[i]) << i;
b9bec74b 1380 }
86cd2ea0
EH		 1381 xsave->legacy.fcw = cwd;
1382 xsave->legacy.fsw = swd;
1383 xsave->legacy.ftw = twd;
1384 xsave->legacy.fpop = env->fpop;
1385 xsave->legacy.fpip = env->fpip;
1386 xsave->legacy.fpdp = env->fpdp;
1387 memcpy(&xsave->legacy.fpregs, env->fpregs,
f1665b21 1388 sizeof env->fpregs);
86cd2ea0
EH		 1389 xsave->legacy.mxcsr = env->mxcsr;
1390 xsave->header.xstate_bv = env->xstate_bv;
1391 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
79e9ebeb 1392 sizeof env->bnd_regs);
86cd2ea0
EH		 1393 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1394 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
9aecd6f8 1395 sizeof env->opmask_regs);
bee81887 1396
86cd2ea0
EH		 1397 for (i = 0; i < CPU_NB_REGS; i++) {
1398 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1399 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1400 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
19cbd87c
EH		 1401 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1402 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1403 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1404 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1405 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1406 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1407 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1408 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
bee81887
PB		 1409 }
1410
9aecd6f8 1411#ifdef TARGET_X86_64
86cd2ea0 1412 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
b7711471 1413 16 * sizeof env->xmm_regs[16]);
86cd2ea0 1414 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
9aecd6f8 1415#endif
9be38598 1416 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1417}
1418
1bc22652 1419static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1420{
1bc22652 1421 CPUX86State *env = &cpu->env;
bdfc8480 1422 struct kvm_xcrs xcrs = {};
f1665b21 1423
28143b40 1424 if (!has_xcrs) {
f1665b21 1425 return 0;
b9bec74b 1426 }
f1665b21
SY		 1427
1428 xcrs.nr_xcrs = 1;
1429 xcrs.flags = 0;
1430 xcrs.xcrs[0].xcr = 0;
1431 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1432 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1433}
1434
1bc22652 1435static int kvm_put_sregs(X86CPU *cpu)
05330448 1436{
1bc22652 1437 CPUX86State *env = &cpu->env;
05330448
AL		 1438 struct kvm_sregs sregs;
1439
0e607a80
JK		 1440 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1441 if (env->interrupt_injected >= 0) {
1442 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1443 (uint64_t)1 << (env->interrupt_injected % 64);
1444 }
05330448
AL		 1445
1446 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1447 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1448 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1449 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1450 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1451 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1452 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1453 } else {
b9bec74b
JK		 1454 set_seg(&sregs.cs, &env->segs[R_CS]);
1455 set_seg(&sregs.ds, &env->segs[R_DS]);
1456 set_seg(&sregs.es, &env->segs[R_ES]);
1457 set_seg(&sregs.fs, &env->segs[R_FS]);
1458 set_seg(&sregs.gs, &env->segs[R_GS]);
1459 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1460 }
1461
1462 set_seg(&sregs.tr, &env->tr);
1463 set_seg(&sregs.ldt, &env->ldt);
1464
1465 sregs.idt.limit = env->idt.limit;
1466 sregs.idt.base = env->idt.base;
7e680753 1467 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1468 sregs.gdt.limit = env->gdt.limit;
1469 sregs.gdt.base = env->gdt.base;
7e680753 1470 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1471
1472 sregs.cr0 = env->cr[0];
1473 sregs.cr2 = env->cr[2];
1474 sregs.cr3 = env->cr[3];
1475 sregs.cr4 = env->cr[4];
1476
02e51483
CF		 1477 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1478 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1479
1480 sregs.efer = env->efer;
1481
1bc22652 1482 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1483}
1484
d71b62a1
EH		 1485static void kvm_msr_buf_reset(X86CPU *cpu)
1486{
1487 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1488}
1489
9c600a84
EH		 1490static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1491{
1492 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1493 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1494 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1495
1496 assert((void *)(entry + 1) <= limit);
1497
1abc2cae
EH		 1498 entry->index = index;
1499 entry->reserved = 0;
1500 entry->data = value;
9c600a84
EH		 1501 msrs->nmsrs++;
1502}
1503
7477cd38
MT		 1504static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1505{
1506 CPUX86State *env = &cpu->env;
48e1a45c 1507 int ret;
7477cd38
MT		 1508
1509 if (!has_msr_tsc_deadline) {
1510 return 0;
1511 }
1512
e25ffda7
EH		 1513 kvm_msr_buf_reset(cpu);
1514 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
7477cd38 1515
e25ffda7 1516 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1517 if (ret < 0) {
1518 return ret;
1519 }
1520
1521 assert(ret == 1);
1522 return 0;
7477cd38
MT		 1523}
1524
6bdf863d
JK		 1525/*
1526 * Provide a separate write service for the feature control MSR in order to
1527 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1528 * before writing any other state because forcibly leaving nested mode
1529 * invalidates the VCPU state.
1530 */
1531static int kvm_put_msr_feature_control(X86CPU *cpu)
1532{
48e1a45c
PB		 1533 int ret;
1534
1535 if (!has_msr_feature_control) {
1536 return 0;
1537 }
6bdf863d 1538
e25ffda7
EH		 1539 kvm_msr_buf_reset(cpu);
1540 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL,
6bdf863d 1541 cpu->env.msr_ia32_feature_control);
c7fe4b12 1542
e25ffda7 1543 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1544 if (ret < 0) {
1545 return ret;
1546 }
1547
1548 assert(ret == 1);
1549 return 0;
6bdf863d
JK		 1550}
1551
1bc22652 1552static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1553{
1bc22652 1554 CPUX86State *env = &cpu->env;
9c600a84 1555 int i;
48e1a45c 1556 int ret;
05330448 1557
d71b62a1
EH		 1558 kvm_msr_buf_reset(cpu);
1559
9c600a84
EH		 1560 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1561 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1562 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1563 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1564 if (has_msr_star) {
9c600a84 1565 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1566 }
c3a3a7d3 1567 if (has_msr_hsave_pa) {
9c600a84 1568 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1569 }
c9b8f6b6 1570 if (has_msr_tsc_aux) {
9c600a84 1571 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1572 }
f28558d3 1573 if (has_msr_tsc_adjust) {
9c600a84 1574 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1575 }
21e87c46 1576 if (has_msr_misc_enable) {
9c600a84 1577 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1578 env->msr_ia32_misc_enable);
1579 }
fc12d72e 1580 if (has_msr_smbase) {
9c600a84 1581 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1582 }
439d19f2 1583 if (has_msr_bndcfgs) {
9c600a84 1584 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1585 }
18cd2c17 1586 if (has_msr_xss) {
9c600a84 1587 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1588 }
05330448 1589#ifdef TARGET_X86_64
25d2e361 1590 if (lm_capable_kernel) {
9c600a84
EH		 1591 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1592 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1593 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1594 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1595 }
05330448 1596#endif
ff5c186b 1597 /*
0d894367
PB		 1598 * The following MSRs have side effects on the guest or are too heavy
1599 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1600 */
1601 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1602 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1603 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1604 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
c5999bfc 1605 if (has_msr_async_pf_en) {
9c600a84 1606 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1607 }
bc9a839d 1608 if (has_msr_pv_eoi_en) {
9c600a84 1609 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1610 }
917367aa 1611 if (has_msr_kvm_steal_time) {
9c600a84 1612 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1613 }
0d894367
PB		 1614 if (has_msr_architectural_pmu) {
1615 /* Stop the counter. */
9c600a84
EH		 1616 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1617 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
0d894367
PB		 1618
1619 /* Set the counter values. */
1620 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 1621 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1622 env->msr_fixed_counters[i]);
1623 }
1624 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84 1625 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1626 env->msr_gp_counters[i]);
9c600a84 1627 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1628 env->msr_gp_evtsel[i]);
1629 }
9c600a84 1630 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
0d894367 1631 env->msr_global_status);
9c600a84 1632 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
0d894367
PB		 1633 env->msr_global_ovf_ctrl);
1634
1635 /* Now start the PMU. */
9c600a84 1636 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
0d894367 1637 env->msr_fixed_ctr_ctrl);
9c600a84 1638 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
0d894367
PB		 1639 env->msr_global_ctrl);
1640 }
7bc3d711 1641 if (has_msr_hv_hypercall) {
9c600a84 1642 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1c90ef26 1643 env->msr_hv_guest_os_id);
9c600a84 1644 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1c90ef26 1645 env->msr_hv_hypercall);
eab70139 1646 }
7bc3d711 1647 if (has_msr_hv_vapic) {
9c600a84 1648 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1649 env->msr_hv_vapic);
eab70139 1650 }
48a5f3bc 1651 if (has_msr_hv_tsc) {
9c600a84 1652 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
48a5f3bc 1653 }
f2a53c9e
AS		 1654 if (has_msr_hv_crash) {
1655 int j;
1656
1657 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
9c600a84 1658 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1659 env->msr_hv_crash_params[j]);
1660
9c600a84 1661 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
f2a53c9e
AS		 1662 HV_X64_MSR_CRASH_CTL_NOTIFY);
1663 }
46eb8f98 1664 if (has_msr_hv_runtime) {
9c600a84 1665 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1666 }
866eea9a
AS		 1667 if (cpu->hyperv_synic) {
1668 int j;
1669
9c600a84 1670 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1671 env->msr_hv_synic_control);
9c600a84 1672 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
866eea9a 1673 env->msr_hv_synic_version);
9c600a84 1674 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1675 env->msr_hv_synic_evt_page);
9c600a84 1676 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1677 env->msr_hv_synic_msg_page);
1678
1679 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1680 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1681 env->msr_hv_synic_sint[j]);
1682 }
1683 }
ff99aa64
AS		 1684 if (has_msr_hv_stimer) {
1685 int j;
1686
1687 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1688 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1689 env->msr_hv_stimer_config[j]);
1690 }
1691
1692 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1693 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1694 env->msr_hv_stimer_count[j]);
1695 }
1696 }
d1ae67f6 1697 if (has_msr_mtrr) {
9c600a84
EH		 1698 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1699 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1700 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1701 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1702 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1703 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1704 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1705 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1706 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1707 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1708 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1709 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1710 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 1711 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1712 env->mtrr_var[i].base);
1713 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i),
1714 env->mtrr_var[i].mask);
d1ae67f6
AW		 1715 }
1716 }
6bdf863d
JK		 1717
1718 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1719 * kvm_put_msr_feature_control. */
ea643051 1720 }
57780495 1721 if (env->mcg_cap) {
d8da8574 1722 int i;
b9bec74b 1723
9c600a84
EH		 1724 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1725 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
c34d440a 1726 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1727 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1728 }
1729 }
1a03675d 1730
d71b62a1 1731 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1732 if (ret < 0) {
1733 return ret;
1734 }
05330448 1735
9c600a84 1736 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 1737 return 0;
05330448
AL		 1738}
1739
1740
1bc22652 1741static int kvm_get_fpu(X86CPU *cpu)
05330448 1742{
1bc22652 1743 CPUX86State *env = &cpu->env;
05330448
AL		 1744 struct kvm_fpu fpu;
1745 int i, ret;
1746
1bc22652 1747 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1748 if (ret < 0) {
05330448 1749 return ret;
b9bec74b 1750 }
05330448
AL		 1751
1752 env->fpstt = (fpu.fsw >> 11) & 7;
1753 env->fpus = fpu.fsw;
1754 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1755 env->fpop = fpu.last_opcode;
1756 env->fpip = fpu.last_ip;
1757 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1758 for (i = 0; i < 8; ++i) {
1759 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1760 }
05330448 1761 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 1762 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1763 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1764 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 1765 }
05330448
AL		 1766 env->mxcsr = fpu.mxcsr;
1767
1768 return 0;
1769}
1770
1bc22652 1771static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1772{
1bc22652 1773 CPUX86State *env = &cpu->env;
86cd2ea0 1774 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1775 int ret, i;
42cc8fa6 1776 uint16_t cwd, swd, twd;
f1665b21 1777
28143b40 1778 if (!has_xsave) {
1bc22652 1779 return kvm_get_fpu(cpu);
b9bec74b 1780 }
f1665b21 1781
1bc22652 1782 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1783 if (ret < 0) {
f1665b21 1784 return ret;
0f53994f 1785 }
f1665b21 1786
86cd2ea0
EH		 1787 cwd = xsave->legacy.fcw;
1788 swd = xsave->legacy.fsw;
1789 twd = xsave->legacy.ftw;
1790 env->fpop = xsave->legacy.fpop;
f1665b21
SY		 1791 env->fpstt = (swd >> 11) & 7;
1792 env->fpus = swd;
1793 env->fpuc = cwd;
b9bec74b 1794 for (i = 0; i < 8; ++i) {
f1665b21 1795 env->fptags[i] = !((twd >> i) & 1);
b9bec74b 1796 }
86cd2ea0
EH		 1797 env->fpip = xsave->legacy.fpip;
1798 env->fpdp = xsave->legacy.fpdp;
1799 env->mxcsr = xsave->legacy.mxcsr;
1800 memcpy(env->fpregs, &xsave->legacy.fpregs,
f1665b21 1801 sizeof env->fpregs);
86cd2ea0
EH		 1802 env->xstate_bv = xsave->header.xstate_bv;
1803 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
79e9ebeb 1804 sizeof env->bnd_regs);
86cd2ea0
EH		 1805 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1806 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
9aecd6f8 1807 sizeof env->opmask_regs);
bee81887 1808
86cd2ea0
EH		 1809 for (i = 0; i < CPU_NB_REGS; i++) {
1810 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1811 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1812 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
19cbd87c
EH		 1813 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1814 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1815 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1816 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1817 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1818 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1819 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1820 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
bee81887
PB		 1821 }
1822
9aecd6f8 1823#ifdef TARGET_X86_64
86cd2ea0 1824 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
b7711471 1825 16 * sizeof env->xmm_regs[16]);
86cd2ea0 1826 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
9aecd6f8 1827#endif
f1665b21 1828 return 0;
f1665b21
SY		 1829}
1830
1bc22652 1831static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1832{
1bc22652 1833 CPUX86State *env = &cpu->env;
f1665b21
SY		 1834 int i, ret;
1835 struct kvm_xcrs xcrs;
1836
28143b40 1837 if (!has_xcrs) {
f1665b21 1838 return 0;
b9bec74b 1839 }
f1665b21 1840
1bc22652 1841 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1842 if (ret < 0) {
f1665b21 1843 return ret;
b9bec74b 1844 }
f1665b21 1845
b9bec74b 1846 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1847 /* Only support xcr0 now */
0fd53fec
PB		 1848 if (xcrs.xcrs[i].xcr == 0) {
1849 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1850 break;
1851 }
b9bec74b 1852 }
f1665b21 1853 return 0;
f1665b21
SY		 1854}
1855
1bc22652 1856static int kvm_get_sregs(X86CPU *cpu)
05330448 1857{
1bc22652 1858 CPUX86State *env = &cpu->env;
05330448
AL		 1859 struct kvm_sregs sregs;
1860 uint32_t hflags;
0e607a80 1861 int bit, i, ret;
05330448 1862
1bc22652 1863 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1864 if (ret < 0) {
05330448 1865 return ret;
b9bec74b 1866 }
05330448 1867
0e607a80
JK		 1868 /* There can only be one pending IRQ set in the bitmap at a time, so try
1869 to find it and save its number instead (-1 for none). */
1870 env->interrupt_injected = -1;
1871 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1872 if (sregs.interrupt_bitmap[i]) {
1873 bit = ctz64(sregs.interrupt_bitmap[i]);
1874 env->interrupt_injected = i * 64 + bit;
1875 break;
1876 }
1877 }
05330448
AL		 1878
1879 get_seg(&env->segs[R_CS], &sregs.cs);
1880 get_seg(&env->segs[R_DS], &sregs.ds);
1881 get_seg(&env->segs[R_ES], &sregs.es);
1882 get_seg(&env->segs[R_FS], &sregs.fs);
1883 get_seg(&env->segs[R_GS], &sregs.gs);
1884 get_seg(&env->segs[R_SS], &sregs.ss);
1885
1886 get_seg(&env->tr, &sregs.tr);
1887 get_seg(&env->ldt, &sregs.ldt);
1888
1889 env->idt.limit = sregs.idt.limit;
1890 env->idt.base = sregs.idt.base;
1891 env->gdt.limit = sregs.gdt.limit;
1892 env->gdt.base = sregs.gdt.base;
1893
1894 env->cr[0] = sregs.cr0;
1895 env->cr[2] = sregs.cr2;
1896 env->cr[3] = sregs.cr3;
1897 env->cr[4] = sregs.cr4;
1898
05330448 1899 env->efer = sregs.efer;
cce47516
JK		 1900
1901 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
05330448 1902
b9bec74b
JK		 1903#define HFLAG_COPY_MASK \
1904 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1905 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1906 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1907 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
05330448 1908
19dc85db
RH		 1909 hflags = env->hflags & HFLAG_COPY_MASK;
1910 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
05330448
AL		 1911 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1912 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
b9bec74b 1913 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
05330448 1914 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
19dc85db
RH		 1915
1916 if (env->cr[4] & CR4_OSFXSR_MASK) {
1917 hflags |= HF_OSFXSR_MASK;
1918 }
05330448
AL		 1919
1920 if (env->efer & MSR_EFER_LMA) {
1921 hflags |= HF_LMA_MASK;
1922 }
1923
1924 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1925 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1926 } else {
1927 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
b9bec74b 1928 (DESC_B_SHIFT - HF_CS32_SHIFT);
05330448 1929 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
b9bec74b
JK		 1930 (DESC_B_SHIFT - HF_SS32_SHIFT);
1931 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1932 !(hflags & HF_CS32_MASK)) {
1933 hflags |= HF_ADDSEG_MASK;
1934 } else {
1935 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1936 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1937 }
05330448 1938 }
19dc85db 1939 env->hflags = hflags;
05330448
AL		 1940
1941 return 0;
1942}
1943
1bc22652 1944static int kvm_get_msrs(X86CPU *cpu)
05330448 1945{
1bc22652 1946 CPUX86State *env = &cpu->env;
d71b62a1 1947 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 1948 int ret, i;
05330448 1949
d71b62a1
EH		 1950 kvm_msr_buf_reset(cpu);
1951
9c600a84
EH		 1952 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1953 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1954 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1955 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 1956 if (has_msr_star) {
9c600a84 1957 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 1958 }
c3a3a7d3 1959 if (has_msr_hsave_pa) {
9c600a84 1960 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 1961 }
c9b8f6b6 1962 if (has_msr_tsc_aux) {
9c600a84 1963 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 1964 }
f28558d3 1965 if (has_msr_tsc_adjust) {
9c600a84 1966 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 1967 }
aa82ba54 1968 if (has_msr_tsc_deadline) {
9c600a84 1969 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 1970 }
21e87c46 1971 if (has_msr_misc_enable) {
9c600a84 1972 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 1973 }
fc12d72e 1974 if (has_msr_smbase) {
9c600a84 1975 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 1976 }
df67696e 1977 if (has_msr_feature_control) {
9c600a84 1978 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 1979 }
79e9ebeb 1980 if (has_msr_bndcfgs) {
9c600a84 1981 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 1982 }
18cd2c17 1983 if (has_msr_xss) {
9c600a84 1984 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17
WL		 1985 }
1986
b8cc45d6
GC		 1987
1988 if (!env->tsc_valid) {
9c600a84 1989 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 1990 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 1991 }
1992
05330448 1993#ifdef TARGET_X86_64
25d2e361 1994 if (lm_capable_kernel) {
9c600a84
EH		 1995 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
1996 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
1997 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
1998 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 1999 }
05330448 2000#endif
9c600a84
EH		 2001 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2002 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
c5999bfc 2003 if (has_msr_async_pf_en) {
9c600a84 2004 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2005 }
bc9a839d 2006 if (has_msr_pv_eoi_en) {
9c600a84 2007 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2008 }
917367aa 2009 if (has_msr_kvm_steal_time) {
9c600a84 2010 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2011 }
0d894367 2012 if (has_msr_architectural_pmu) {
9c600a84
EH		 2013 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2014 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2015 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2016 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
0d894367 2017 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 2018 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367
PB		 2019 }
2020 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84
EH		 2021 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2022 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2023 }
2024 }
1a03675d 2025
57780495 2026 if (env->mcg_cap) {
9c600a84
EH		 2027 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2028 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
b9bec74b 2029 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2030 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2031 }
57780495 2032 }
57780495 2033
1c90ef26 2034 if (has_msr_hv_hypercall) {
9c600a84
EH		 2035 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2036 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2037 }
5ef68987 2038 if (has_msr_hv_vapic) {
9c600a84 2039 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2040 }
48a5f3bc 2041 if (has_msr_hv_tsc) {
9c600a84 2042 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2043 }
f2a53c9e
AS		 2044 if (has_msr_hv_crash) {
2045 int j;
2046
2047 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
9c600a84 2048 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2049 }
2050 }
46eb8f98 2051 if (has_msr_hv_runtime) {
9c600a84 2052 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2053 }
866eea9a
AS		 2054 if (cpu->hyperv_synic) {
2055 uint32_t msr;
2056
9c600a84
EH		 2057 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2058 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2059 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2060 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2061 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2062 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2063 }
2064 }
ff99aa64
AS		 2065 if (has_msr_hv_stimer) {
2066 uint32_t msr;
2067
2068 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2069 msr++) {
9c600a84 2070 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2071 }
2072 }
d1ae67f6 2073 if (has_msr_mtrr) {
9c600a84
EH		 2074 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2075 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2076 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2077 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2078 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2079 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2080 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2081 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2082 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2083 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2084 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2085 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2086 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2087 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2088 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2089 }
2090 }
5ef68987 2091
d71b62a1 2092 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2093 if (ret < 0) {
05330448 2094 return ret;
b9bec74b 2095 }
05330448 2096
9c600a84 2097 assert(ret == cpu->kvm_msr_buf->nmsrs);
05330448 2098 for (i = 0; i < ret; i++) {
0d894367
PB		 2099 uint32_t index = msrs[i].index;
2100 switch (index) {
05330448
AL		 2101 case MSR_IA32_SYSENTER_CS:
2102 env->sysenter_cs = msrs[i].data;
2103 break;
2104 case MSR_IA32_SYSENTER_ESP:
2105 env->sysenter_esp = msrs[i].data;
2106 break;
2107 case MSR_IA32_SYSENTER_EIP:
2108 env->sysenter_eip = msrs[i].data;
2109 break;
0c03266a
JK		 2110 case MSR_PAT:
2111 env->pat = msrs[i].data;
2112 break;
05330448
AL		 2113 case MSR_STAR:
2114 env->star = msrs[i].data;
2115 break;
2116#ifdef TARGET_X86_64
2117 case MSR_CSTAR:
2118 env->cstar = msrs[i].data;
2119 break;
2120 case MSR_KERNELGSBASE:
2121 env->kernelgsbase = msrs[i].data;
2122 break;
2123 case MSR_FMASK:
2124 env->fmask = msrs[i].data;
2125 break;
2126 case MSR_LSTAR:
2127 env->lstar = msrs[i].data;
2128 break;
2129#endif
2130 case MSR_IA32_TSC:
2131 env->tsc = msrs[i].data;
2132 break;
c9b8f6b6
AS		 2133 case MSR_TSC_AUX:
2134 env->tsc_aux = msrs[i].data;
2135 break;
f28558d3
WA		 2136 case MSR_TSC_ADJUST:
2137 env->tsc_adjust = msrs[i].data;
2138 break;
aa82ba54
LJ		 2139 case MSR_IA32_TSCDEADLINE:
2140 env->tsc_deadline = msrs[i].data;
2141 break;
aa851e36
MT		 2142 case MSR_VM_HSAVE_PA:
2143 env->vm_hsave = msrs[i].data;
2144 break;
1a03675d
GC		 2145 case MSR_KVM_SYSTEM_TIME:
2146 env->system_time_msr = msrs[i].data;
2147 break;
2148 case MSR_KVM_WALL_CLOCK:
2149 env->wall_clock_msr = msrs[i].data;
2150 break;
57780495
MT		 2151 case MSR_MCG_STATUS:
2152 env->mcg_status = msrs[i].data;
2153 break;
2154 case MSR_MCG_CTL:
2155 env->mcg_ctl = msrs[i].data;
2156 break;
21e87c46
AK		 2157 case MSR_IA32_MISC_ENABLE:
2158 env->msr_ia32_misc_enable = msrs[i].data;
2159 break;
fc12d72e
PB		 2160 case MSR_IA32_SMBASE:
2161 env->smbase = msrs[i].data;
2162 break;
0779caeb
ACL		 2163 case MSR_IA32_FEATURE_CONTROL:
2164 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2165 break;
79e9ebeb
LJ		 2166 case MSR_IA32_BNDCFGS:
2167 env->msr_bndcfgs = msrs[i].data;
2168 break;
18cd2c17
WL		 2169 case MSR_IA32_XSS:
2170 env->xss = msrs[i].data;
2171 break;
57780495 2172 default:
57780495
MT		 2173 if (msrs[i].index >= MSR_MC0_CTL &&
2174 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2175 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2176 }
d8da8574 2177 break;
f6584ee2
GN		 2178 case MSR_KVM_ASYNC_PF_EN:
2179 env->async_pf_en_msr = msrs[i].data;
2180 break;
bc9a839d
MT		 2181 case MSR_KVM_PV_EOI_EN:
2182 env->pv_eoi_en_msr = msrs[i].data;
2183 break;
917367aa
MT		 2184 case MSR_KVM_STEAL_TIME:
2185 env->steal_time_msr = msrs[i].data;
2186 break;
0d894367
PB		 2187 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2188 env->msr_fixed_ctr_ctrl = msrs[i].data;
2189 break;
2190 case MSR_CORE_PERF_GLOBAL_CTRL:
2191 env->msr_global_ctrl = msrs[i].data;
2192 break;
2193 case MSR_CORE_PERF_GLOBAL_STATUS:
2194 env->msr_global_status = msrs[i].data;
2195 break;
2196 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2197 env->msr_global_ovf_ctrl = msrs[i].data;
2198 break;
2199 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2200 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2201 break;
2202 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2203 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2204 break;
2205 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2206 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2207 break;
1c90ef26
VR		 2208 case HV_X64_MSR_HYPERCALL:
2209 env->msr_hv_hypercall = msrs[i].data;
2210 break;
2211 case HV_X64_MSR_GUEST_OS_ID:
2212 env->msr_hv_guest_os_id = msrs[i].data;
2213 break;
5ef68987
VR		 2214 case HV_X64_MSR_APIC_ASSIST_PAGE:
2215 env->msr_hv_vapic = msrs[i].data;
2216 break;
48a5f3bc
VR		 2217 case HV_X64_MSR_REFERENCE_TSC:
2218 env->msr_hv_tsc = msrs[i].data;
2219 break;
f2a53c9e
AS		 2220 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2221 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2222 break;
46eb8f98
AS		 2223 case HV_X64_MSR_VP_RUNTIME:
2224 env->msr_hv_runtime = msrs[i].data;
2225 break;
866eea9a
AS		 2226 case HV_X64_MSR_SCONTROL:
2227 env->msr_hv_synic_control = msrs[i].data;
2228 break;
2229 case HV_X64_MSR_SVERSION:
2230 env->msr_hv_synic_version = msrs[i].data;
2231 break;
2232 case HV_X64_MSR_SIEFP:
2233 env->msr_hv_synic_evt_page = msrs[i].data;
2234 break;
2235 case HV_X64_MSR_SIMP:
2236 env->msr_hv_synic_msg_page = msrs[i].data;
2237 break;
2238 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2239 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2240 break;
2241 case HV_X64_MSR_STIMER0_CONFIG:
2242 case HV_X64_MSR_STIMER1_CONFIG:
2243 case HV_X64_MSR_STIMER2_CONFIG:
2244 case HV_X64_MSR_STIMER3_CONFIG:
2245 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2246 msrs[i].data;
2247 break;
2248 case HV_X64_MSR_STIMER0_COUNT:
2249 case HV_X64_MSR_STIMER1_COUNT:
2250 case HV_X64_MSR_STIMER2_COUNT:
2251 case HV_X64_MSR_STIMER3_COUNT:
2252 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2253 msrs[i].data;
866eea9a 2254 break;
d1ae67f6
AW		 2255 case MSR_MTRRdefType:
2256 env->mtrr_deftype = msrs[i].data;
2257 break;
2258 case MSR_MTRRfix64K_00000:
2259 env->mtrr_fixed[0] = msrs[i].data;
2260 break;
2261 case MSR_MTRRfix16K_80000:
2262 env->mtrr_fixed[1] = msrs[i].data;
2263 break;
2264 case MSR_MTRRfix16K_A0000:
2265 env->mtrr_fixed[2] = msrs[i].data;
2266 break;
2267 case MSR_MTRRfix4K_C0000:
2268 env->mtrr_fixed[3] = msrs[i].data;
2269 break;
2270 case MSR_MTRRfix4K_C8000:
2271 env->mtrr_fixed[4] = msrs[i].data;
2272 break;
2273 case MSR_MTRRfix4K_D0000:
2274 env->mtrr_fixed[5] = msrs[i].data;
2275 break;
2276 case MSR_MTRRfix4K_D8000:
2277 env->mtrr_fixed[6] = msrs[i].data;
2278 break;
2279 case MSR_MTRRfix4K_E0000:
2280 env->mtrr_fixed[7] = msrs[i].data;
2281 break;
2282 case MSR_MTRRfix4K_E8000:
2283 env->mtrr_fixed[8] = msrs[i].data;
2284 break;
2285 case MSR_MTRRfix4K_F0000:
2286 env->mtrr_fixed[9] = msrs[i].data;
2287 break;
2288 case MSR_MTRRfix4K_F8000:
2289 env->mtrr_fixed[10] = msrs[i].data;
2290 break;
2291 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2292 if (index & 1) {
2293 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
2294 } else {
2295 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2296 }
2297 break;
05330448
AL		 2298 }
2299 }
2300
2301 return 0;
2302}
2303
1bc22652 2304static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2305{
1bc22652 2306 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2307
1bc22652 2308 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2309}
2310
23d02d9b 2311static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2312{
259186a7 2313 CPUState *cs = CPU(cpu);
23d02d9b 2314 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2315 struct kvm_mp_state mp_state;
2316 int ret;
2317
259186a7 2318 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2319 if (ret < 0) {
2320 return ret;
2321 }
2322 env->mp_state = mp_state.mp_state;
c14750e8 2323 if (kvm_irqchip_in_kernel()) {
259186a7 2324 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2325 }
9bdbe550
HB		 2326 return 0;
2327}
2328
1bc22652 2329static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2330{
02e51483 2331 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2332 struct kvm_lapic_state kapic;
2333 int ret;
2334
3d4b2649 2335 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2336 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2337 if (ret < 0) {
2338 return ret;
2339 }
2340
2341 kvm_get_apic_state(apic, &kapic);
2342 }
2343 return 0;
2344}
2345
1bc22652 2346static int kvm_put_apic(X86CPU *cpu)
680c1c6f 2347{
02e51483 2348 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2349 struct kvm_lapic_state kapic;
2350
3d4b2649 2351 if (apic && kvm_irqchip_in_kernel()) {
680c1c6f
JK		 2352 kvm_put_apic_state(apic, &kapic);
2353
1bc22652 2354 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
680c1c6f
JK		 2355 }
2356 return 0;
2357}
2358
1bc22652 2359static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2360{
fc12d72e 2361 CPUState *cs = CPU(cpu);
1bc22652 2362 CPUX86State *env = &cpu->env;
076796f8 2363 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2364
2365 if (!kvm_has_vcpu_events()) {
2366 return 0;
2367 }
2368
31827373
JK		 2369 events.exception.injected = (env->exception_injected >= 0);
2370 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2371 events.exception.has_error_code = env->has_error_code;
2372 events.exception.error_code = env->error_code;
7e680753 2373 events.exception.pad = 0;
a0fb002c
JK		 2374
2375 events.interrupt.injected = (env->interrupt_injected >= 0);
2376 events.interrupt.nr = env->interrupt_injected;
2377 events.interrupt.soft = env->soft_interrupt;
2378
2379 events.nmi.injected = env->nmi_injected;
2380 events.nmi.pending = env->nmi_pending;
2381 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2382 events.nmi.pad = 0;
a0fb002c
JK		 2383
2384 events.sipi_vector = env->sipi_vector;
2385
fc12d72e
PB		 2386 if (has_msr_smbase) {
2387 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2388 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2389 if (kvm_irqchip_in_kernel()) {
2390 /* As soon as these are moved to the kernel, remove them
2391 * from cs->interrupt_request.
2392 */
2393 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2394 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2395 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2396 } else {
2397 /* Keep these in cs->interrupt_request. */
2398 events.smi.pending = 0;
2399 events.smi.latched_init = 0;
2400 }
2401 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2402 }
2403
ea643051
JK		 2404 events.flags = 0;
2405 if (level >= KVM_PUT_RESET_STATE) {
2406 events.flags |=
2407 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2408 }
aee028b9 2409
1bc22652 2410 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2411}
2412
1bc22652 2413static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2414{
1bc22652 2415 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2416 struct kvm_vcpu_events events;
2417 int ret;
2418
2419 if (!kvm_has_vcpu_events()) {
2420 return 0;
2421 }
2422
fc12d72e 2423 memset(&events, 0, sizeof(events));
1bc22652 2424 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2425 if (ret < 0) {
2426 return ret;
2427 }
31827373 2428 env->exception_injected =
a0fb002c
JK		 2429 events.exception.injected ? events.exception.nr : -1;
2430 env->has_error_code = events.exception.has_error_code;
2431 env->error_code = events.exception.error_code;
2432
2433 env->interrupt_injected =
2434 events.interrupt.injected ? events.interrupt.nr : -1;
2435 env->soft_interrupt = events.interrupt.soft;
2436
2437 env->nmi_injected = events.nmi.injected;
2438 env->nmi_pending = events.nmi.pending;
2439 if (events.nmi.masked) {
2440 env->hflags2 |= HF2_NMI_MASK;
2441 } else {
2442 env->hflags2 &= ~HF2_NMI_MASK;
2443 }
2444
fc12d72e
PB		 2445 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2446 if (events.smi.smm) {
2447 env->hflags |= HF_SMM_MASK;
2448 } else {
2449 env->hflags &= ~HF_SMM_MASK;
2450 }
2451 if (events.smi.pending) {
2452 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2453 } else {
2454 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2455 }
2456 if (events.smi.smm_inside_nmi) {
2457 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2458 } else {
2459 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2460 }
2461 if (events.smi.latched_init) {
2462 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2463 } else {
2464 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2465 }
2466 }
2467
a0fb002c 2468 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2469
2470 return 0;
2471}
2472
1bc22652 2473static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2474{
ed2803da 2475 CPUState *cs = CPU(cpu);
1bc22652 2476 CPUX86State *env = &cpu->env;
b0b1d690 2477 int ret = 0;
b0b1d690
JK		 2478 unsigned long reinject_trap = 0;
2479
2480 if (!kvm_has_vcpu_events()) {
2481 if (env->exception_injected == 1) {
2482 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2483 } else if (env->exception_injected == 3) {
2484 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2485 }
2486 env->exception_injected = -1;
2487 }
2488
2489 /*
2490 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2491 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2492 * by updating the debug state once again if single-stepping is on.
2493 * Another reason to call kvm_update_guest_debug here is a pending debug
2494 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2495 * reinject them via SET_GUEST_DEBUG.
2496 */
2497 if (reinject_trap ||
ed2803da 2498 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2499 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2500 }
b0b1d690
JK		 2501 return ret;
2502}
2503
1bc22652 2504static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2505{
1bc22652 2506 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2507 struct kvm_debugregs dbgregs;
2508 int i;
2509
2510 if (!kvm_has_debugregs()) {
2511 return 0;
2512 }
2513
2514 for (i = 0; i < 4; i++) {
2515 dbgregs.db[i] = env->dr[i];
2516 }
2517 dbgregs.dr6 = env->dr[6];
2518 dbgregs.dr7 = env->dr[7];
2519 dbgregs.flags = 0;
2520
1bc22652 2521 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2522}
2523
1bc22652 2524static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2525{
1bc22652 2526 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2527 struct kvm_debugregs dbgregs;
2528 int i, ret;
2529
2530 if (!kvm_has_debugregs()) {
2531 return 0;
2532 }
2533
1bc22652 2534 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2535 if (ret < 0) {
b9bec74b 2536 return ret;
ff44f1a3
JK		 2537 }
2538 for (i = 0; i < 4; i++) {
2539 env->dr[i] = dbgregs.db[i];
2540 }
2541 env->dr[4] = env->dr[6] = dbgregs.dr6;
2542 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2543
2544 return 0;
2545}
2546
20d695a9 2547int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2548{
20d695a9 2549 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2550 int ret;
2551
2fa45344 2552 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2553
48e1a45c 2554 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2555 ret = kvm_put_msr_feature_control(x86_cpu);
2556 if (ret < 0) {
2557 return ret;
2558 }
2559 }
2560
36f96c4b
HZ		 2561 if (level == KVM_PUT_FULL_STATE) {
2562 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2563 * because TSC frequency mismatch shouldn't abort migration,
2564 * unless the user explicitly asked for a more strict TSC
2565 * setting (e.g. using an explicit "tsc-freq" option).
2566 */
2567 kvm_arch_set_tsc_khz(cpu);
2568 }
2569
1bc22652 2570 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2571 if (ret < 0) {
05330448 2572 return ret;
b9bec74b 2573 }
1bc22652 2574 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2575 if (ret < 0) {
f1665b21 2576 return ret;
b9bec74b 2577 }
1bc22652 2578 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2579 if (ret < 0) {
05330448 2580 return ret;
b9bec74b 2581 }
1bc22652 2582 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2583 if (ret < 0) {
05330448 2584 return ret;
b9bec74b 2585 }
ab443475 2586 /* must be before kvm_put_msrs */
1bc22652 2587 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2588 if (ret < 0) {
2589 return ret;
2590 }
1bc22652 2591 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2592 if (ret < 0) {
05330448 2593 return ret;
b9bec74b 2594 }
ea643051 2595 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2596 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2597 if (ret < 0) {
ea643051 2598 return ret;
b9bec74b 2599 }
1bc22652 2600 ret = kvm_put_apic(x86_cpu);
680c1c6f
JK		 2601 if (ret < 0) {
2602 return ret;
2603 }
ea643051 2604 }
7477cd38
MT		 2605
2606 ret = kvm_put_tscdeadline_msr(x86_cpu);
2607 if (ret < 0) {
2608 return ret;
2609 }
2610
1bc22652 2611 ret = kvm_put_vcpu_events(x86_cpu, level);
b9bec74b 2612 if (ret < 0) {
a0fb002c 2613 return ret;
b9bec74b 2614 }
1bc22652 2615 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2616 if (ret < 0) {
b0b1d690 2617 return ret;
b9bec74b 2618 }
b0b1d690 2619 /* must be last */
1bc22652 2620 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2621 if (ret < 0) {
ff44f1a3 2622 return ret;
b9bec74b 2623 }
05330448
AL		 2624 return 0;
2625}
2626
20d695a9 2627int kvm_arch_get_registers(CPUState *cs)
05330448 2628{
20d695a9 2629 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2630 int ret;
2631
20d695a9 2632 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2633
1bc22652 2634 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2635 if (ret < 0) {
f4f1110e 2636 goto out;
b9bec74b 2637 }
1bc22652 2638 ret = kvm_get_xsave(cpu);
b9bec74b 2639 if (ret < 0) {
f4f1110e 2640 goto out;
b9bec74b 2641 }
1bc22652 2642 ret = kvm_get_xcrs(cpu);
b9bec74b 2643 if (ret < 0) {
f4f1110e 2644 goto out;
b9bec74b 2645 }
1bc22652 2646 ret = kvm_get_sregs(cpu);
b9bec74b 2647 if (ret < 0) {
f4f1110e 2648 goto out;
b9bec74b 2649 }
1bc22652 2650 ret = kvm_get_msrs(cpu);
b9bec74b 2651 if (ret < 0) {
f4f1110e 2652 goto out;
b9bec74b 2653 }
23d02d9b 2654 ret = kvm_get_mp_state(cpu);
b9bec74b 2655 if (ret < 0) {
f4f1110e 2656 goto out;
b9bec74b 2657 }
1bc22652 2658 ret = kvm_get_apic(cpu);
680c1c6f 2659 if (ret < 0) {
f4f1110e 2660 goto out;
680c1c6f 2661 }
1bc22652 2662 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2663 if (ret < 0) {
f4f1110e 2664 goto out;
b9bec74b 2665 }
1bc22652 2666 ret = kvm_get_debugregs(cpu);
b9bec74b 2667 if (ret < 0) {
f4f1110e 2668 goto out;
b9bec74b 2669 }
f4f1110e
RH		 2670 ret = 0;
2671 out:
2672 cpu_sync_bndcs_hflags(&cpu->env);
2673 return ret;
05330448
AL		 2674}
2675
20d695a9 2676void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2677{
20d695a9
AF		 2678 X86CPU *x86_cpu = X86_CPU(cpu);
2679 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2680 int ret;
2681
276ce815 2682 /* Inject NMI */
fc12d72e
PB		 2683 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2684 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2685 qemu_mutex_lock_iothread();
2686 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2687 qemu_mutex_unlock_iothread();
2688 DPRINTF("injected NMI\n");
2689 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2690 if (ret < 0) {
2691 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2692 strerror(-ret));
2693 }
2694 }
2695 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2696 qemu_mutex_lock_iothread();
2697 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2698 qemu_mutex_unlock_iothread();
2699 DPRINTF("injected SMI\n");
2700 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2701 if (ret < 0) {
2702 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2703 strerror(-ret));
2704 }
ce377af3 2705 }
276ce815
LJ		 2706 }
2707
15eafc2e 2708 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2709 qemu_mutex_lock_iothread();
2710 }
2711
e0723c45
PB		 2712 /* Force the VCPU out of its inner loop to process any INIT requests
2713 * or (for userspace APIC, but it is cheap to combine the checks here)
2714 * pending TPR access reports.
2715 */
2716 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2717 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2718 !(env->hflags & HF_SMM_MASK)) {
2719 cpu->exit_request = 1;
2720 }
2721 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2722 cpu->exit_request = 1;
2723 }
e0723c45 2724 }
05330448 2725
15eafc2e 2726 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 2727 /* Try to inject an interrupt if the guest can accept it */
2728 if (run->ready_for_interrupt_injection &&
259186a7 2729 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2730 (env->eflags & IF_MASK)) {
2731 int irq;
2732
259186a7 2733 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2734 irq = cpu_get_pic_interrupt(env);
2735 if (irq >= 0) {
2736 struct kvm_interrupt intr;
2737
2738 intr.irq = irq;
db1669bc 2739 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2740 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2741 if (ret < 0) {
2742 fprintf(stderr,
2743 "KVM: injection failed, interrupt lost (%s)\n",
2744 strerror(-ret));
2745 }
db1669bc
JK		 2746 }
2747 }
05330448 2748
db1669bc
JK		 2749 /* If we have an interrupt but the guest is not ready to receive an
2750 * interrupt, request an interrupt window exit. This will
2751 * cause a return to userspace as soon as the guest is ready to
2752 * receive interrupts. */
259186a7 2753 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2754 run->request_interrupt_window = 1;
2755 } else {
2756 run->request_interrupt_window = 0;
2757 }
2758
2759 DPRINTF("setting tpr\n");
02e51483 2760 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2761
2762 qemu_mutex_unlock_iothread();
db1669bc 2763 }
05330448
AL		 2764}
2765
4c663752 2766MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2767{
20d695a9
AF		 2768 X86CPU *x86_cpu = X86_CPU(cpu);
2769 CPUX86State *env = &x86_cpu->env;
2770
fc12d72e
PB		 2771 if (run->flags & KVM_RUN_X86_SMM) {
2772 env->hflags |= HF_SMM_MASK;
2773 } else {
2774 env->hflags &= HF_SMM_MASK;
2775 }
b9bec74b 2776 if (run->if_flag) {
05330448 2777 env->eflags |= IF_MASK;
b9bec74b 2778 } else {
05330448 2779 env->eflags &= ~IF_MASK;
b9bec74b 2780 }
4b8523ee
JK		 2781
2782 /* We need to protect the apic state against concurrent accesses from
2783 * different threads in case the userspace irqchip is used. */
2784 if (!kvm_irqchip_in_kernel()) {
2785 qemu_mutex_lock_iothread();
2786 }
02e51483
CF		 2787 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2788 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2789 if (!kvm_irqchip_in_kernel()) {
2790 qemu_mutex_unlock_iothread();
2791 }
f794aa4a 2792 return cpu_get_mem_attrs(env);
05330448
AL		 2793}
2794
20d695a9 2795int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2796{
20d695a9
AF		 2797 X86CPU *cpu = X86_CPU(cs);
2798 CPUX86State *env = &cpu->env;
232fc23b 2799
259186a7 2800 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2801 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2802 assert(env->mcg_cap);
2803
259186a7 2804 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2805
dd1750d7 2806 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2807
2808 if (env->exception_injected == EXCP08_DBLE) {
2809 /* this means triple fault */
2810 qemu_system_reset_request();
fcd7d003 2811 cs->exit_request = 1;
ab443475
JK		 2812 return 0;
2813 }
2814 env->exception_injected = EXCP12_MCHK;
2815 env->has_error_code = 0;
2816
259186a7 2817 cs->halted = 0;
ab443475
JK		 2818 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2819 env->mp_state = KVM_MP_STATE_RUNNABLE;
2820 }
2821 }
2822
fc12d72e
PB		 2823 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2824 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2825 kvm_cpu_synchronize_state(cs);
2826 do_cpu_init(cpu);
2827 }
2828
db1669bc
JK		 2829 if (kvm_irqchip_in_kernel()) {
2830 return 0;
2831 }
2832
259186a7
AF		 2833 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2834 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2835 apic_poll_irq(cpu->apic_state);
5d62c43a 2836 }
259186a7 2837 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2838 (env->eflags & IF_MASK)) ||
259186a7
AF		 2839 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2840 cs->halted = 0;
6792a57b 2841 }
259186a7 2842 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2843 kvm_cpu_synchronize_state(cs);
232fc23b 2844 do_cpu_sipi(cpu);
0af691d7 2845 }
259186a7
AF		 2846 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2847 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2848 kvm_cpu_synchronize_state(cs);
02e51483 2849 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2850 env->tpr_access_type);
2851 }
0af691d7 2852
259186a7 2853 return cs->halted;
0af691d7
MT		 2854}
2855
839b5630 2856static int kvm_handle_halt(X86CPU *cpu)
05330448 2857{
259186a7 2858 CPUState *cs = CPU(cpu);
839b5630
AF		 2859 CPUX86State *env = &cpu->env;
2860
259186a7 2861 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2862 (env->eflags & IF_MASK)) &&
259186a7
AF		 2863 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2864 cs->halted = 1;
bb4ea393 2865 return EXCP_HLT;
05330448
AL		 2866 }
2867
bb4ea393 2868 return 0;
05330448
AL		 2869}
2870
f7575c96 2871static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 2872{
f7575c96
AF		 2873 CPUState *cs = CPU(cpu);
2874 struct kvm_run *run = cs->kvm_run;
d362e757 2875
02e51483 2876 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 2877 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2878 : TPR_ACCESS_READ);
2879 return 1;
2880}
2881
f17ec444 2882int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 2883{
38972938 2884 static const uint8_t int3 = 0xcc;
64bf3f4e 2885
f17ec444
AF		 2886 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2887 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 2888 return -EINVAL;
b9bec74b 2889 }
e22a25c9
AL		 2890 return 0;
2891}
2892
f17ec444 2893int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 2894{
2895 uint8_t int3;
2896
f17ec444
AF		 2897 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2898 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 2899 return -EINVAL;
b9bec74b 2900 }
e22a25c9
AL		 2901 return 0;
2902}
2903
2904static struct {
2905 target_ulong addr;
2906 int len;
2907 int type;
2908} hw_breakpoint[4];
2909
2910static int nb_hw_breakpoint;
2911
2912static int find_hw_breakpoint(target_ulong addr, int len, int type)
2913{
2914 int n;
2915
b9bec74b 2916 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 2917 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 2918 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 2919 return n;
b9bec74b
JK		 2920 }
2921 }
e22a25c9
AL		 2922 return -1;
2923}
2924
2925int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2926 target_ulong len, int type)
2927{
2928 switch (type) {
2929 case GDB_BREAKPOINT_HW:
2930 len = 1;
2931 break;
2932 case GDB_WATCHPOINT_WRITE:
2933 case GDB_WATCHPOINT_ACCESS:
2934 switch (len) {
2935 case 1:
2936 break;
2937 case 2:
2938 case 4:
2939 case 8:
b9bec74b 2940 if (addr & (len - 1)) {
e22a25c9 2941 return -EINVAL;
b9bec74b 2942 }
e22a25c9
AL		 2943 break;
2944 default:
2945 return -EINVAL;
2946 }
2947 break;
2948 default:
2949 return -ENOSYS;
2950 }
2951
b9bec74b 2952 if (nb_hw_breakpoint == 4) {
e22a25c9 2953 return -ENOBUFS;
b9bec74b
JK		 2954 }
2955 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 2956 return -EEXIST;
b9bec74b 2957 }
e22a25c9
AL		 2958 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2959 hw_breakpoint[nb_hw_breakpoint].len = len;
2960 hw_breakpoint[nb_hw_breakpoint].type = type;
2961 nb_hw_breakpoint++;
2962
2963 return 0;
2964}
2965
2966int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2967 target_ulong len, int type)
2968{
2969 int n;
2970
2971 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 2972 if (n < 0) {
e22a25c9 2973 return -ENOENT;
b9bec74b 2974 }
e22a25c9
AL		 2975 nb_hw_breakpoint--;
2976 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2977
2978 return 0;
2979}
2980
2981void kvm_arch_remove_all_hw_breakpoints(void)
2982{
2983 nb_hw_breakpoint = 0;
2984}
2985
2986static CPUWatchpoint hw_watchpoint;
2987
a60f24b5 2988static int kvm_handle_debug(X86CPU *cpu,
48405526 2989 struct kvm_debug_exit_arch *arch_info)
e22a25c9 2990{
ed2803da 2991 CPUState *cs = CPU(cpu);
a60f24b5 2992 CPUX86State *env = &cpu->env;
f2574737 2993 int ret = 0;
e22a25c9
AL		 2994 int n;
2995
2996 if (arch_info->exception == 1) {
2997 if (arch_info->dr6 & (1 << 14)) {
ed2803da 2998 if (cs->singlestep_enabled) {
f2574737 2999 ret = EXCP_DEBUG;
b9bec74b 3000 }
e22a25c9 3001 } else {
b9bec74b
JK		 3002 for (n = 0; n < 4; n++) {
3003 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3004 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3005 case 0x0:
f2574737 3006 ret = EXCP_DEBUG;
e22a25c9
AL		 3007 break;
3008 case 0x1:
f2574737 3009 ret = EXCP_DEBUG;
ff4700b0 3010 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3011 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3012 hw_watchpoint.flags = BP_MEM_WRITE;
3013 break;
3014 case 0x3:
f2574737 3015 ret = EXCP_DEBUG;
ff4700b0 3016 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3017 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3018 hw_watchpoint.flags = BP_MEM_ACCESS;
3019 break;
3020 }
b9bec74b
JK		 3021 }
3022 }
e22a25c9 3023 }
ff4700b0 3024 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3025 ret = EXCP_DEBUG;
b9bec74b 3026 }
f2574737 3027 if (ret == 0) {
ff4700b0 3028 cpu_synchronize_state(cs);
48405526 3029 assert(env->exception_injected == -1);
b0b1d690 3030
f2574737 3031 /* pass to guest */
48405526
BS		 3032 env->exception_injected = arch_info->exception;
3033 env->has_error_code = 0;
b0b1d690 3034 }
e22a25c9 3035
f2574737 3036 return ret;
e22a25c9
AL		 3037}
3038
20d695a9 3039void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3040{
3041 const uint8_t type_code[] = {
3042 [GDB_BREAKPOINT_HW] = 0x0,
3043 [GDB_WATCHPOINT_WRITE] = 0x1,
3044 [GDB_WATCHPOINT_ACCESS] = 0x3
3045 };
3046 const uint8_t len_code[] = {
3047 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3048 };
3049 int n;
3050
a60f24b5 3051 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3052 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3053 }
e22a25c9
AL		 3054 if (nb_hw_breakpoint > 0) {
3055 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3056 dbg->arch.debugreg[7] = 0x0600;
3057 for (n = 0; n < nb_hw_breakpoint; n++) {
3058 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3059 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3060 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3061 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3062 }
3063 }
3064}
4513d923 3065
2a4dac83
JK		 3066static bool host_supports_vmx(void)
3067{
3068 uint32_t ecx, unused;
3069
3070 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3071 return ecx & CPUID_EXT_VMX;
3072}
3073
3074#define VMX_INVALID_GUEST_STATE 0x80000021
3075
20d695a9 3076int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3077{
20d695a9 3078 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3079 uint64_t code;
3080 int ret;
3081
3082 switch (run->exit_reason) {
3083 case KVM_EXIT_HLT:
3084 DPRINTF("handle_hlt\n");
4b8523ee 3085 qemu_mutex_lock_iothread();
839b5630 3086 ret = kvm_handle_halt(cpu);
4b8523ee 3087 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3088 break;
3089 case KVM_EXIT_SET_TPR:
3090 ret = 0;
3091 break;
d362e757 3092 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3093 qemu_mutex_lock_iothread();
f7575c96 3094 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3095 qemu_mutex_unlock_iothread();
d362e757 3096 break;
2a4dac83
JK		 3097 case KVM_EXIT_FAIL_ENTRY:
3098 code = run->fail_entry.hardware_entry_failure_reason;
3099 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3100 code);
3101 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3102 fprintf(stderr,
12619721 3103 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3104 "unrestricted mode\n"
3105 "support, the failure can be most likely due to the guest "
3106 "entering an invalid\n"
3107 "state for Intel VT. For example, the guest maybe running "
3108 "in big real mode\n"
3109 "which is not supported on less recent Intel processors."
3110 "\n\n");
3111 }
3112 ret = -1;
3113 break;
3114 case KVM_EXIT_EXCEPTION:
3115 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3116 run->ex.exception, run->ex.error_code);
3117 ret = -1;
3118 break;
f2574737
JK		 3119 case KVM_EXIT_DEBUG:
3120 DPRINTF("kvm_exit_debug\n");
4b8523ee 3121 qemu_mutex_lock_iothread();
a60f24b5 3122 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3123 qemu_mutex_unlock_iothread();
f2574737 3124 break;
50efe82c
AS		 3125 case KVM_EXIT_HYPERV:
3126 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3127 break;
15eafc2e
PB		 3128 case KVM_EXIT_IOAPIC_EOI:
3129 ioapic_eoi_broadcast(run->eoi.vector);
3130 ret = 0;
3131 break;
2a4dac83
JK		 3132 default:
3133 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3134 ret = -1;
3135 break;
3136 }
3137
3138 return ret;
3139}
3140
20d695a9 3141bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3142{
20d695a9
AF		 3143 X86CPU *cpu = X86_CPU(cs);
3144 CPUX86State *env = &cpu->env;
3145
dd1750d7 3146 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3147 return !(env->cr[0] & CR0_PE_MASK) ||
3148 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3149}
84b058d7
JK		 3150
3151void kvm_arch_init_irq_routing(KVMState *s)
3152{
3153 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3154 /* If kernel can't do irq routing, interrupt source
3155 * override 0->2 cannot be set up as required by HPET.
3156 * So we have to disable it.
3157 */
3158 no_hpet = 1;
3159 }
cc7e0ddf 3160 /* We know at this point that we're using the in-kernel
614e41bc 3161 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3162 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3163 */
614e41bc 3164 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3165 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3166
3167 if (kvm_irqchip_is_split()) {
3168 int i;
3169
3170 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3171 MSI routes for signaling interrupts to the local apics. */
3172 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3173 struct MSIMessage msg = { 0x0, 0x0 };
3174 if (kvm_irqchip_add_msi_route(s, msg, NULL) < 0) {
3175 error_report("Could not enable split IRQ mode.");
3176 exit(1);
3177 }
3178 }
3179 }
3180}
3181
3182int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3183{
3184 int ret;
3185 if (machine_kernel_irqchip_split(ms)) {
3186 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3187 if (ret) {
3188 error_report("Could not enable split irqchip mode: %s\n",
3189 strerror(-ret));
3190 exit(1);
3191 } else {
3192 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3193 kvm_split_irqchip = true;
3194 return 1;
3195 }
3196 } else {
3197 return 0;
3198 }
84b058d7 3199}
b139bd30
JK		 3200
3201/* Classic KVM device assignment interface. Will remain x86 only. */
3202int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3203 uint32_t flags, uint32_t *dev_id)
3204{
3205 struct kvm_assigned_pci_dev dev_data = {
3206 .segnr = dev_addr->domain,
3207 .busnr = dev_addr->bus,
3208 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3209 .flags = flags,
3210 };
3211 int ret;
3212
3213 dev_data.assigned_dev_id =
3214 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3215
3216 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3217 if (ret < 0) {
3218 return ret;
3219 }
3220
3221 *dev_id = dev_data.assigned_dev_id;
3222
3223 return 0;
3224}
3225
3226int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3227{
3228 struct kvm_assigned_pci_dev dev_data = {
3229 .assigned_dev_id = dev_id,
3230 };
3231
3232 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3233}
3234
3235static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3236 uint32_t irq_type, uint32_t guest_irq)
3237{
3238 struct kvm_assigned_irq assigned_irq = {
3239 .assigned_dev_id = dev_id,
3240 .guest_irq = guest_irq,
3241 .flags = irq_type,
3242 };
3243
3244 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3245 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3246 } else {
3247 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3248 }
3249}
3250
3251int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3252 uint32_t guest_irq)
3253{
3254 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3255 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3256
3257 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3258}
3259
3260int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3261{
3262 struct kvm_assigned_pci_dev dev_data = {
3263 .assigned_dev_id = dev_id,
3264 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3265 };
3266
3267 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3268}
3269
3270static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3271 uint32_t type)
3272{
3273 struct kvm_assigned_irq assigned_irq = {
3274 .assigned_dev_id = dev_id,
3275 .flags = type,
3276 };
3277
3278 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3279}
3280
3281int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3282{
3283 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3284 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3285}
3286
3287int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3288{
3289 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3290 KVM_DEV_IRQ_GUEST_MSI, virq);
3291}
3292
3293int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3294{
3295 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3296 KVM_DEV_IRQ_HOST_MSI);
3297}
3298
3299bool kvm_device_msix_supported(KVMState *s)
3300{
3301 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3302 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3303 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3304}
3305
3306int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3307 uint32_t nr_vectors)
3308{
3309 struct kvm_assigned_msix_nr msix_nr = {
3310 .assigned_dev_id = dev_id,
3311 .entry_nr = nr_vectors,
3312 };
3313
3314 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3315}
3316
3317int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3318 int virq)
3319{
3320 struct kvm_assigned_msix_entry msix_entry = {
3321 .assigned_dev_id = dev_id,
3322 .gsi = virq,
3323 .entry = vector,
3324 };
3325
3326 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3327}
3328
3329int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3330{
3331 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3332 KVM_DEV_IRQ_GUEST_MSIX, 0);
3333}
3334
3335int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3336{
3337 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3338 KVM_DEV_IRQ_HOST_MSIX);
3339}
9e03a040
FB		 3340
3341int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3342 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040
FB		 3343{
3344 return 0;
3345}
1850b6b7
EA		 3346
3347int kvm_arch_msi_data_to_gsi(uint32_t data)
3348{
3349 abort();
3350}
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