]>
Commit | Line | Data |
---|---|---|
1 | /** @file\r | |
2 | \r | |
3 | Copyright (c) 2007, Intel Corporation\r | |
4 | All rights reserved. This program and the accompanying materials\r | |
5 | are licensed and made available under the terms and conditions of the BSD License\r | |
6 | which accompanies this distribution. The full text of the license may be found at\r | |
7 | http://opensource.org/licenses/bsd-license.php\r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | \r | |
12 | Module Name:\r | |
13 | \r | |
14 | EhciReg.h\r | |
15 | \r | |
16 | Abstract:\r | |
17 | \r | |
18 | This file contains the definination for host controller register operation routines\r | |
19 | \r | |
20 | Revision History\r | |
21 | \r | |
22 | **/\r | |
23 | \r | |
24 | #ifndef _EFI_EHCI_REG_H_\r | |
25 | #define _EFI_EHCI_REG_H_\r | |
26 | \r | |
27 | \r | |
28 | enum {\r | |
29 | //\r | |
30 | // Capability register offset\r | |
31 | //\r | |
32 | EHC_CAPLENGTH_OFFSET = 0, // Capability register length offset\r | |
33 | EHC_HCSPARAMS_OFFSET = 0x04, // Structural Parameters 04-07h\r | |
34 | EHC_HCCPARAMS_OFFSET = 0x08, // Capability parameters offset\r | |
35 | \r | |
36 | //\r | |
37 | // Capability register bit definition\r | |
38 | //\r | |
39 | HCSP_NPORTS = 0x0F, // Number of root hub port\r | |
40 | HCCP_64BIT = 0x01, // 64-bit addressing capability\r | |
41 | \r | |
42 | //\r | |
43 | // Operational register offset\r | |
44 | //\r | |
45 | EHC_USBCMD_OFFSET = 0x0, // USB command register offset\r | |
46 | EHC_USBSTS_OFFSET = 0x04, // Statue register offset\r | |
47 | EHC_USBINTR_OFFSET = 0x08, // USB interrutp offset\r | |
48 | EHC_FRINDEX_OFFSET = 0x0C, // Frame index offset\r | |
49 | EHC_CTRLDSSEG_OFFSET = 0x10, // Control data structure segment offset\r | |
50 | EHC_FRAME_BASE_OFFSET = 0x14, // Frame list base address offset\r | |
51 | EHC_ASYNC_HEAD_OFFSET = 0x18, // Next asynchronous list address offset\r | |
52 | EHC_CONFIG_FLAG_OFFSET = 0x40, // Configure flag register offset\r | |
53 | EHC_PORT_STAT_OFFSET = 0x44, // Port status/control offset\r | |
54 | \r | |
55 | EHC_FRAME_LEN = 1024,\r | |
56 | \r | |
57 | //\r | |
58 | // Register bit definition\r | |
59 | //\r | |
60 | CONFIGFLAG_ROUTE_EHC = 0x01, // Route port to EHC\r | |
61 | \r | |
62 | USBCMD_RUN = 0x01, // Run/stop\r | |
63 | USBCMD_RESET = 0x02, // Start the host controller reset\r | |
64 | USBCMD_ENABLE_PERIOD = 0x10, // Enable periodic schedule\r | |
65 | USBCMD_ENABLE_ASYNC = 0x20, // Enable asynchronous schedule\r | |
66 | USBCMD_IAAD = 0x40, // Interrupt on async advance doorbell\r | |
67 | \r | |
68 | USBSTS_IAA = 0x20, // Interrupt on async advance\r | |
69 | USBSTS_PERIOD_ENABLED = 0x4000, // Periodic schedule status\r | |
70 | USBSTS_ASYNC_ENABLED = 0x8000, // Asynchronous schedule status\r | |
71 | USBSTS_HALT = 0x1000, // Host controller halted\r | |
72 | USBSTS_SYS_ERROR = 0x10, // Host system error\r | |
73 | USBSTS_INTACK_MASK = 0x003F, // Mask for the interrupt ACK, the WC\r | |
74 | // (write clean) bits in USBSTS register\r | |
75 | \r | |
76 | PORTSC_CONN = 0x01, // Current Connect Status\r | |
77 | PORTSC_CONN_CHANGE = 0x02, // Connect Status Change\r | |
78 | PORTSC_ENABLED = 0x04, // Port Enable / Disable\r | |
79 | PORTSC_ENABLE_CHANGE = 0x08, // Port Enable / Disable Change\r | |
80 | PORTSC_OVERCUR = 0x10, // Over current Active\r | |
81 | PORTSC_OVERCUR_CHANGE = 0x20, // Over current Change\r | |
82 | PORSTSC_RESUME = 0x40, // Force Port Resume\r | |
83 | PORTSC_SUSPEND = 0x80, // Port Suspend State\r | |
84 | PORTSC_RESET = 0x100, // Port Reset\r | |
85 | PORTSC_LINESTATE_K = 0x400, // Line Status K-state\r | |
86 | PORTSC_LINESTATE_J = 0x800, // Line Status J-state\r | |
87 | PORTSC_POWER = 0x1000, // Port Power\r | |
88 | PORTSC_OWNER = 0x2000, // Port Owner\r | |
89 | PORTSC_CHANGE_MASK = 0x2A, // Mask of the port change bits,\r | |
90 | // they are WC (write clean)\r | |
91 | //\r | |
92 | // PCI Configuration Registers\r | |
93 | //\r | |
94 | EHC_PCI_CLASSC = 0x09,\r | |
95 | EHC_PCI_CLASSC_PI = 0x20,\r | |
96 | EHC_BAR_INDEX = 0 /* how many bytes away from USB_BASE to 0x10 */\r | |
97 | };\r | |
98 | \r | |
99 | #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r | |
100 | \r | |
101 | #define EHC_ADDR(High, QhHw32) \\r | |
102 | ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))\r | |
103 | \r | |
104 | #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r | |
105 | \r | |
106 | //\r | |
107 | // Structure to map the hardware port states to the\r | |
108 | // UEFI's port states.\r | |
109 | //\r | |
110 | typedef struct {\r | |
111 | UINT16 HwState;\r | |
112 | UINT16 UefiState;\r | |
113 | } USB_PORT_STATE_MAP;\r | |
114 | \r | |
115 | //\r | |
116 | // Ehci Data and Ctrl Structures\r | |
117 | //\r | |
118 | #pragma pack(1)\r | |
119 | typedef struct {\r | |
120 | UINT8 PI;\r | |
121 | UINT8 SubClassCode;\r | |
122 | UINT8 BaseCode;\r | |
123 | } USB_CLASSC;\r | |
124 | #pragma pack()\r | |
125 | \r | |
126 | \r | |
127 | UINT32\r | |
128 | EhcReadCapRegister (\r | |
129 | IN USB2_HC_DEV *Ehc,\r | |
130 | IN UINT32 Offset\r | |
131 | )\r | |
132 | /*++\r | |
133 | \r | |
134 | Routine Description:\r | |
135 | \r | |
136 | Read EHCI capability register\r | |
137 | \r | |
138 | Arguments:\r | |
139 | \r | |
140 | Ehc - The Ehc device\r | |
141 | Offset - Capability register address\r | |
142 | \r | |
143 | Returns:\r | |
144 | \r | |
145 | The register content read\r | |
146 | \r | |
147 | --*/\r | |
148 | ;\r | |
149 | \r | |
150 | \r | |
151 | /**\r | |
152 | Read Ehc Operation register\r | |
153 | \r | |
154 | @param Ehc The EHCI device\r | |
155 | @param Offset The operation register offset\r | |
156 | \r | |
157 | @return The register content read\r | |
158 | \r | |
159 | **/\r | |
160 | UINT32\r | |
161 | EhcReadOpReg (\r | |
162 | IN USB2_HC_DEV *Ehc,\r | |
163 | IN UINT32 Offset\r | |
164 | )\r | |
165 | ;\r | |
166 | \r | |
167 | \r | |
168 | /**\r | |
169 | Write the data to the EHCI operation register\r | |
170 | \r | |
171 | @param Ehc The EHCI device\r | |
172 | @param Offset EHCI operation register offset\r | |
173 | @param Data The data to write\r | |
174 | \r | |
175 | @return None\r | |
176 | \r | |
177 | **/\r | |
178 | VOID\r | |
179 | EhcWriteOpReg (\r | |
180 | IN USB2_HC_DEV *Ehc,\r | |
181 | IN UINT32 Offset,\r | |
182 | IN UINT32 Data\r | |
183 | )\r | |
184 | ;\r | |
185 | \r | |
186 | \r | |
187 | /**\r | |
188 | Add support for UEFI Over Legacy (UoL) feature, stop\r | |
189 | the legacy USB SMI support\r | |
190 | \r | |
191 | @param Ehc The EHCI device.\r | |
192 | \r | |
193 | @return None\r | |
194 | \r | |
195 | **/\r | |
196 | VOID\r | |
197 | EhcClearLegacySupport (\r | |
198 | IN USB2_HC_DEV *Ehc\r | |
199 | )\r | |
200 | ;\r | |
201 | \r | |
202 | \r | |
203 | \r | |
204 | /**\r | |
205 | Set door bell and wait it to be ACKed by host controller.\r | |
206 | This function is used to synchronize with the hardware.\r | |
207 | \r | |
208 | @param Ehc The EHCI device\r | |
209 | @param Timeout The time to wait before abort (in millisecond, ms)\r | |
210 | \r | |
211 | @return EFI_SUCCESS : Synchronized with the hardware\r | |
212 | @return EFI_TIMEOUT : Time out happened while waiting door bell to set\r | |
213 | \r | |
214 | **/\r | |
215 | EFI_STATUS\r | |
216 | EhcSetAndWaitDoorBell (\r | |
217 | IN USB2_HC_DEV *Ehc,\r | |
218 | IN UINT32 Timeout\r | |
219 | )\r | |
220 | ;\r | |
221 | \r | |
222 | \r | |
223 | /**\r | |
224 | Clear all the interrutp status bits, these bits\r | |
225 | are Write-Clean\r | |
226 | \r | |
227 | @param Ehc The EHCI device\r | |
228 | \r | |
229 | @return None\r | |
230 | \r | |
231 | **/\r | |
232 | VOID\r | |
233 | EhcAckAllInterrupt (\r | |
234 | IN USB2_HC_DEV *Ehc\r | |
235 | )\r | |
236 | ;\r | |
237 | \r | |
238 | \r | |
239 | \r | |
240 | /**\r | |
241 | Whether Ehc is halted\r | |
242 | \r | |
243 | @param Ehc The EHCI device\r | |
244 | \r | |
245 | @return TRUE : The controller is halted\r | |
246 | @return FALSE : It isn't halted\r | |
247 | \r | |
248 | **/\r | |
249 | BOOLEAN\r | |
250 | EhcIsHalt (\r | |
251 | IN USB2_HC_DEV *Ehc\r | |
252 | )\r | |
253 | ;\r | |
254 | \r | |
255 | \r | |
256 | /**\r | |
257 | Whether system error occurred\r | |
258 | \r | |
259 | @param Ehc The EHCI device\r | |
260 | \r | |
261 | @return TRUE : System error happened\r | |
262 | @return FALSE : No system error\r | |
263 | \r | |
264 | **/\r | |
265 | BOOLEAN\r | |
266 | EhcIsSysError (\r | |
267 | IN USB2_HC_DEV *Ehc\r | |
268 | )\r | |
269 | ;\r | |
270 | \r | |
271 | \r | |
272 | \r | |
273 | /**\r | |
274 | Reset the host controller\r | |
275 | \r | |
276 | @param Ehc The EHCI device\r | |
277 | @param Timeout Time to wait before abort (in millisecond, ms)\r | |
278 | \r | |
279 | @return EFI_SUCCESS : The host controller is reset\r | |
280 | @return Others : Failed to reset the host\r | |
281 | \r | |
282 | **/\r | |
283 | EFI_STATUS\r | |
284 | EhcResetHC (\r | |
285 | IN USB2_HC_DEV *Ehc,\r | |
286 | IN UINT32 Timeout\r | |
287 | )\r | |
288 | ;\r | |
289 | \r | |
290 | \r | |
291 | \r | |
292 | /**\r | |
293 | Halt the host controller\r | |
294 | \r | |
295 | @param Ehc The EHCI device\r | |
296 | @param Timeout Time to wait before abort\r | |
297 | \r | |
298 | @return EFI_SUCCESS : The EHCI is halt\r | |
299 | @return EFI_TIMEOUT : Failed to halt the controller before Timeout\r | |
300 | \r | |
301 | **/\r | |
302 | EFI_STATUS\r | |
303 | EhcHaltHC (\r | |
304 | IN USB2_HC_DEV *Ehc,\r | |
305 | IN UINT32 Timeout\r | |
306 | )\r | |
307 | ;\r | |
308 | \r | |
309 | \r | |
310 | \r | |
311 | /**\r | |
312 | Set the EHCI to run\r | |
313 | \r | |
314 | @param Ehc The EHCI device\r | |
315 | @param Timeout Time to wait before abort\r | |
316 | \r | |
317 | @return EFI_SUCCESS : The EHCI is running\r | |
318 | @return Others : Failed to set the EHCI to run\r | |
319 | \r | |
320 | **/\r | |
321 | EFI_STATUS\r | |
322 | EhcRunHC (\r | |
323 | IN USB2_HC_DEV *Ehc,\r | |
324 | IN UINT32 Timeout\r | |
325 | )\r | |
326 | ;\r | |
327 | \r | |
328 | \r | |
329 | \r | |
330 | /**\r | |
331 | Initialize the HC hardware.\r | |
332 | EHCI spec lists the five things to do to initialize the hardware\r | |
333 | 1. Program CTRLDSSEGMENT\r | |
334 | 2. Set USBINTR to enable interrupts\r | |
335 | 3. Set periodic list base\r | |
336 | 4. Set USBCMD, interrupt threshold, frame list size etc\r | |
337 | 5. Write 1 to CONFIGFLAG to route all ports to EHCI\r | |
338 | \r | |
339 | @param Ehc The EHCI device\r | |
340 | \r | |
341 | @return EFI_SUCCESS : The EHCI has come out of halt state\r | |
342 | @return EFI_TIMEOUT : Time out happened\r | |
343 | \r | |
344 | **/\r | |
345 | EFI_STATUS\r | |
346 | EhcInitHC (\r | |
347 | IN USB2_HC_DEV *Ehc\r | |
348 | )\r | |
349 | ;\r | |
350 | \r | |
351 | #endif\r |