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1 | /** @file\r | |
2 | SMM profile internal header file.\r | |
3 | \r | |
4 | Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>\r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef _SMM_PROFILE_INTERNAL_H_\r | |
16 | #define _SMM_PROFILE_INTERNAL_H_\r | |
17 | \r | |
18 | #include <Guid/GlobalVariable.h>\r | |
19 | #include <Guid/Acpi.h>\r | |
20 | #include <Protocol/SmmReadyToLock.h>\r | |
21 | #include <Library/UefiRuntimeServicesTableLib.h>\r | |
22 | #include <Library/DxeServicesTableLib.h>\r | |
23 | #include <Library/CpuLib.h>\r | |
24 | #include <IndustryStandard/Acpi.h>\r | |
25 | \r | |
26 | #include "SmmProfileArch.h"\r | |
27 | \r | |
28 | //\r | |
29 | // Configure the SMM_PROFILE DTS region size\r | |
30 | //\r | |
31 | #define SMM_PROFILE_DTS_SIZE (4 * 1024 * 1024) // 4M\r | |
32 | \r | |
33 | #define MAX_PF_PAGE_COUNT 0x2\r | |
34 | \r | |
35 | #define PEBS_RECORD_NUMBER 0x2\r | |
36 | \r | |
37 | #define MAX_PF_ENTRY_COUNT 10\r | |
38 | \r | |
39 | //\r | |
40 | // This MACRO just enable unit test for the profile\r | |
41 | // Please disable it.\r | |
42 | //\r | |
43 | \r | |
44 | #define IA32_PF_EC_P (1u << 0)\r | |
45 | #define IA32_PF_EC_WR (1u << 1)\r | |
46 | #define IA32_PF_EC_US (1u << 2)\r | |
47 | #define IA32_PF_EC_RSVD (1u << 3)\r | |
48 | #define IA32_PF_EC_ID (1u << 4)\r | |
49 | \r | |
50 | #define SMM_PROFILE_NAME L"SmmProfileData"\r | |
51 | \r | |
52 | //\r | |
53 | // CPU generic definition\r | |
54 | //\r | |
55 | #define CPUID1_EDX_XD_SUPPORT 0x100000\r | |
56 | #define MSR_EFER 0xc0000080\r | |
57 | #define MSR_EFER_XD 0x800\r | |
58 | \r | |
59 | #define CPUID1_EDX_BTS_AVAILABLE 0x200000\r | |
60 | \r | |
61 | #define DR6_SINGLE_STEP 0x4000\r | |
62 | #define RFLAG_TF 0x100\r | |
63 | \r | |
64 | #define MSR_DEBUG_CTL 0x1D9\r | |
65 | #define MSR_DEBUG_CTL_LBR 0x1\r | |
66 | #define MSR_DEBUG_CTL_TR 0x40\r | |
67 | #define MSR_DEBUG_CTL_BTS 0x80\r | |
68 | #define MSR_DEBUG_CTL_BTINT 0x100\r | |
69 | #define MSR_DS_AREA 0x600\r | |
70 | \r | |
71 | typedef struct {\r | |
72 | EFI_PHYSICAL_ADDRESS Base;\r | |
73 | EFI_PHYSICAL_ADDRESS Top;\r | |
74 | } MEMORY_RANGE;\r | |
75 | \r | |
76 | typedef struct {\r | |
77 | MEMORY_RANGE Range;\r | |
78 | BOOLEAN Present;\r | |
79 | BOOLEAN Nx;\r | |
80 | } MEMORY_PROTECTION_RANGE;\r | |
81 | \r | |
82 | typedef struct {\r | |
83 | UINT64 HeaderSize;\r | |
84 | UINT64 MaxDataEntries;\r | |
85 | UINT64 MaxDataSize;\r | |
86 | UINT64 CurDataEntries;\r | |
87 | UINT64 CurDataSize;\r | |
88 | UINT64 TsegStart;\r | |
89 | UINT64 TsegSize;\r | |
90 | UINT64 NumSmis;\r | |
91 | UINT64 NumCpus;\r | |
92 | } SMM_PROFILE_HEADER;\r | |
93 | \r | |
94 | typedef struct {\r | |
95 | UINT64 SmiNum;\r | |
96 | UINT64 CpuNum;\r | |
97 | UINT64 ApicId;\r | |
98 | UINT64 ErrorCode;\r | |
99 | UINT64 Instruction;\r | |
100 | UINT64 Address;\r | |
101 | UINT64 SmiCmd;\r | |
102 | } SMM_PROFILE_ENTRY;\r | |
103 | \r | |
104 | extern SMM_S3_RESUME_STATE *mSmmS3ResumeState;\r | |
105 | extern UINTN gSmiExceptionHandlers[];\r | |
106 | extern BOOLEAN mXdSupported;\r | |
107 | extern UINTN *mPFEntryCount;\r | |
108 | extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];\r | |
109 | extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];\r | |
110 | \r | |
111 | //\r | |
112 | // Internal functions\r | |
113 | //\r | |
114 | \r | |
115 | /**\r | |
116 | Update IDT table to replace page fault handler and INT 1 handler.\r | |
117 | \r | |
118 | **/\r | |
119 | VOID\r | |
120 | InitIdtr (\r | |
121 | VOID\r | |
122 | );\r | |
123 | \r | |
124 | /**\r | |
125 | Check if the memory address will be mapped by 4KB-page.\r | |
126 | \r | |
127 | @param Address The address of Memory.\r | |
128 | \r | |
129 | **/\r | |
130 | BOOLEAN\r | |
131 | IsAddressSplit (\r | |
132 | IN EFI_PHYSICAL_ADDRESS Address\r | |
133 | );\r | |
134 | \r | |
135 | /**\r | |
136 | Check if the memory address will be mapped by 4KB-page.\r | |
137 | \r | |
138 | @param Address The address of Memory.\r | |
139 | @param Nx The flag indicates if the memory is execute-disable.\r | |
140 | \r | |
141 | **/\r | |
142 | BOOLEAN\r | |
143 | IsAddressValid (\r | |
144 | IN EFI_PHYSICAL_ADDRESS Address,\r | |
145 | IN BOOLEAN *Nx\r | |
146 | );\r | |
147 | \r | |
148 | /**\r | |
149 | Page Fault handler for SMM use.\r | |
150 | \r | |
151 | **/\r | |
152 | VOID\r | |
153 | SmiDefaultPFHandler (\r | |
154 | VOID\r | |
155 | );\r | |
156 | \r | |
157 | /**\r | |
158 | Clear TF in FLAGS.\r | |
159 | \r | |
160 | @param SystemContext A pointer to the processor context when\r | |
161 | the interrupt occurred on the processor.\r | |
162 | \r | |
163 | **/\r | |
164 | VOID\r | |
165 | ClearTrapFlag (\r | |
166 | IN OUT EFI_SYSTEM_CONTEXT SystemContext\r | |
167 | );\r | |
168 | \r | |
169 | #endif // _SMM_PROFILE_H_\r |