ArmPkg/Library/ArmLib/Arm11/Arm11Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <AsmMacroIoLib.h>
  17
  18 .text
  19 .align 2
  20 GCC_ASM_EXPORT(ArmDisableCachesAndMmu)
  21 GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
  22 GCC_ASM_EXPORT(ArmCleanDataCache)
  23 GCC_ASM_EXPORT(ArmInvalidateDataCache)
  24 GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
  25 GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
  26 GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
  27 GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
  28 GCC_ASM_EXPORT(ArmEnableMmu)
  29 GCC_ASM_EXPORT(ArmDisableMmu)
  30 GCC_ASM_EXPORT(ArmMmuEnabled)
  31 GCC_ASM_EXPORT(ArmEnableDataCache)
  32 GCC_ASM_EXPORT(ArmDisableDataCache)
  33 GCC_ASM_EXPORT(ArmEnableInstructionCache)
  34 GCC_ASM_EXPORT(ArmDisableInstructionCache)
  35 GCC_ASM_EXPORT(ArmEnableBranchPrediction)
  36 GCC_ASM_EXPORT(ArmDisableBranchPrediction)
  37 GCC_ASM_EXPORT(ArmDataMemoryBarrier)
  38 GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
  39 GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
  40 GCC_ASM_EXPORT(ArmSetLowVectors)
  41 GCC_ASM_EXPORT(ArmSetHighVectors)
  42 GCC_ASM_EXPORT(ArmIsMpCore)
  43 GCC_ASM_EXPORT(ArmCallWFI)
  44 GCC_ASM_EXPORT(ArmReadMpidr)
  45 GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
  46 GCC_ASM_EXPORT(ArmEnableFiq)
  47 GCC_ASM_EXPORT(ArmDisableFiq)
  48 GCC_ASM_EXPORT(ArmEnableInterrupts)
  49 GCC_ASM_EXPORT(ArmDisableInterrupts)
  50 GCC_ASM_EXPORT (ArmEnableVFP)
  51
  52 Arm11PartNumberMask:  .word       0xFFF0
  53 Arm11PartNumber:      .word       0xB020
  54
  55 .set DC_ON, (0x1<<2)
  56 .set IC_ON, (0x1<<12)
  57 .set XP_ON, (0x1<<23)
  58 .set CTRL_M_BIT,  (1 << 0)
  59 .set CTRL_C_BIT,  (1 << 2)
  60 .set CTRL_I_BIT,  (1 << 12)
  61
  62 ASM_PFX(ArmDisableCachesAndMmu):
  63   mrc   p15, 0, r0, c1, c0, 0           @ Get control register
  64   bic   r0, r0, #CTRL_M_BIT             @ Disable MMU
  65   bic   r0, r0, #CTRL_C_BIT             @ Disable D Cache
  66   bic   r0, r0, #CTRL_I_BIT             @ Disable I Cache
  67   mcr   p15, 0, r0, c1, c0, 0           @ Write control register
  68   bx      LR
  69
  70 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  71   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  72   bx      lr
  73
  74
  75 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  76   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  77   bx      lr
  78
  79
  80 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  81   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  82   bx      lr
  83
  84
  85 ASM_PFX(ArmCleanDataCache):
  86   mcr     p15, 0, r0, c7, c10, 0  @ clean entire data cache
  87   bx      lr
  88
  89
  90 ASM_PFX(ArmCleanInvalidateDataCache):
  91   mcr     p15, 0, r0, c7, c14, 0  @ clean and invalidate entire data cache
  92   bx      lr
  93
  94
  95 ASM_PFX(ArmInvalidateDataCache):
  96   mcr     p15, 0, r0, c7, c6, 0  @ invalidate entire data cache
  97   bx      lr
  98
  99
 100 ASM_PFX(ArmInvalidateInstructionCache):
 101   mcr     p15, 0, r0, c7, c5, 0  @invalidate entire instruction cache
 102   mov     R0,#0
 103   mcr     p15,0,R0,c7,c5,4       @Flush Prefetch buffer
 104   bx      lr
 105
 106 ASM_PFX(ArmEnableMmu):
 107   mrc     p15,0,R0,c1,c0,0
 108   orr     R0,R0,#1
 109   mcr     p15,0,R0,c1,c0,0
 110   bx      LR
 111
 112 ASM_PFX(ArmMmuEnabled):
 113   mrc     p15,0,R0,c1,c0,0
 114   and     R0,R0,#1
 115   bx      LR
 116
 117 ASM_PFX(ArmDisableMmu):
 118   mrc     p15,0,R0,c1,c0,0
 119   bic     R0,R0,#1
 120   mcr     p15,0,R0,c1,c0,0
 121   mov     R0,#0
 122   mcr     p15,0,R0,c7,c10,4     @Data synchronization barrier
 123   mov     R0,#0
 124   mcr     p15,0,R0,c7,c5,4      @Flush Prefetch buffer
 125   bx      LR
 126
 127 ASM_PFX(ArmEnableDataCache):
 128   LoadConstantToReg(DC_ON, R1)  @ldr     R1,=DC_ON
 129   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 130   orr     R0,R0,R1              @Set C bit
 131   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 132   bx      LR
 133
 134 ASM_PFX(ArmDisableDataCache):
 135   LoadConstantToReg(DC_ON, R1)  @ldr     R1,=DC_ON
 136   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 137   bic     R0,R0,R1              @Clear C bit
 138   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 139   bx      LR
 140
 141 ASM_PFX(ArmEnableInstructionCache):
 142   ldr     R1,=IC_ON
 143   mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
 144   orr     R0,R0,R1             @Set I bit
 145   mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
 146   bx      LR
 147
 148 ASM_PFX(ArmDisableInstructionCache):
 149   ldr     R1,=IC_ON
 150   mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
 151   bic     R0,R0,R1             @Clear I bit.
 152   mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
 153   bx      LR
 154
 155 ASM_PFX(ArmEnableBranchPrediction):
 156   mrc     p15, 0, r0, c1, c0, 0
 157   orr     r0, r0, #0x00000800
 158   mcr     p15, 0, r0, c1, c0, 0
 159   bx      LR
 160
 161 ASM_PFX(ArmDisableBranchPrediction):
 162   mrc     p15, 0, r0, c1, c0, 0
 163   bic     r0, r0, #0x00000800
 164   mcr     p15, 0, r0, c1, c0, 0
 165   bx      LR
 166
 167 ASM_PFX(ArmDataMemoryBarrier):
 168   mov R0, #0
 169   mcr P15, #0, R0, C7, C10, #5
 170   bx      LR
 171
 172 ASM_PFX(ArmDataSyncronizationBarrier):
 173   mov R0, #0
 174   mcr P15, #0, R0, C7, C10, #4
 175   bx      LR
 176
 177 ASM_PFX(ArmInstructionSynchronizationBarrier):
 178   mov R0, #0
 179   mcr P15, #0, R0, C7, C5, #4
 180   bx      LR
 181
 182 ASM_PFX(ArmSetLowVectors):
 183   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 184   bic     r0, r0, #0x00002000   @ clear V bit
 185   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 186   bx      LR
 187
 188 ASM_PFX(ArmSetHighVectors):
 189   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 190   orr     r0, r0, #0x00002000   @ clear V bit
 191   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 192   bx      LR
 193
 194 ASM_PFX(ArmIsMpCore):
 195   push    { r1 }
 196   mrc     p15, 0, r0, c0, c0, 0
 197   # Extract Part Number to check it is an ARM11MP core (0xB02)
 198   LoadConstantToReg (Arm11PartNumberMask, r1)
 199   and     r0, r0, r1
 200   LoadConstantToReg (Arm11PartNumber, r1)
 201   cmp     r0, r1
 202   movne   r0, #0
 203   pop     { r1 }
 204   bx      lr
 205
 206 ASM_PFX(ArmCallWFI):
 207   wfi
 208   bx      lr
 209
 210 ASM_PFX(ArmReadMpidr):
 211   mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR
 212   bx      lr
 213
 214 ASM_PFX(ArmEnableFiq):
 215   mrs     R0,CPSR
 216   bic     R0,R0,#0x40    @Enable FIQ interrupts
 217   msr     CPSR_c,R0
 218   bx      LR
 219
 220 ASM_PFX(ArmDisableFiq):
 221   mrs     R0,CPSR
 222   orr     R1,R0,#0x40    @Disable FIQ interrupts
 223   msr     CPSR_c,R1
 224   tst     R0,#0x80
 225   moveq   R0,#1
 226   movne   R0,#0
 227   bx      LR
 228
 229 ASM_PFX(ArmEnableInterrupts):
 230   mrs     R0,CPSR
 231   bic     R0,R0,#0x80    @Enable IRQ interrupts
 232   msr     CPSR_c,R0
 233   bx      LR
 234
 235 ASM_PFX(ArmDisableInterrupts):
 236   mrs     R0,CPSR
 237   orr     R1,R0,#0x80    @Disable IRQ interrupts
 238   msr     CPSR_c,R1
 239   tst     R0,#0x80
 240   moveq   R0,#1
 241   movne   R0,#0
 242   bx      LR
 243
 244 ASM_PFX(ArmEnableVFP):
 245   # Read CPACR (Coprocessor Access Control Register)
 246   mrc     p15, 0, r0, c1, c0, 2
 247   # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 248   orr     r0, r0, #0x00f00000
 249   # Write back CPACR (Coprocessor Access Control Register)
 250   mcr     p15, 0, r0, c1, c0, 2
 251   # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 252   mov     r0, #0x40000000
 253   #TODO: Fixme - need compilation flag
 254   #fmxr    FPEXC, r0
 255   bx      lr
 256
 257 ASM_FUNCTION_REMOVE_IF_UNREFERENCED