| 3402aac7 |
1 | #------------------------------------------------------------------------------\r |
| 1e57a462 |
2 | #\r |
| 3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
| 4 | # Copyright (c) 2011, ARM Limited. All rights reserved.\r |
| 5 | #\r |
| 6 | # This program and the accompanying materials\r |
| 7 | # are licensed and made available under the terms and conditions of the BSD License\r |
| 8 | # which accompanies this distribution. The full text of the license may be found at\r |
| 9 | # http://opensource.org/licenses/bsd-license.php\r |
| 10 | #\r |
| 11 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 12 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 13 | #\r |
| 14 | #------------------------------------------------------------------------------\r |
| 15 | \r |
| 16 | #include <AsmMacroIoLib.h>\r |
| 17 | \r |
| 18 | .text\r |
| 19 | .align 2\r |
| 20 | GCC_ASM_EXPORT(ArmDisableCachesAndMmu)\r |
| 1e57a462 |
21 | GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)\r |
| 22 | GCC_ASM_EXPORT(ArmCleanDataCache)\r |
| 23 | GCC_ASM_EXPORT(ArmInvalidateDataCache)\r |
| 24 | GCC_ASM_EXPORT(ArmInvalidateInstructionCache)\r |
| 25 | GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)\r |
| 26 | GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)\r |
| 27 | GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)\r |
| 28 | GCC_ASM_EXPORT(ArmEnableMmu)\r |
| 29 | GCC_ASM_EXPORT(ArmDisableMmu)\r |
| 30 | GCC_ASM_EXPORT(ArmMmuEnabled)\r |
| 31 | GCC_ASM_EXPORT(ArmEnableDataCache)\r |
| 32 | GCC_ASM_EXPORT(ArmDisableDataCache)\r |
| 33 | GCC_ASM_EXPORT(ArmEnableInstructionCache)\r |
| 34 | GCC_ASM_EXPORT(ArmDisableInstructionCache)\r |
| 35 | GCC_ASM_EXPORT(ArmEnableBranchPrediction)\r |
| 36 | GCC_ASM_EXPORT(ArmDisableBranchPrediction)\r |
| 37 | GCC_ASM_EXPORT(ArmDataMemoryBarrier)\r |
| 38 | GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)\r |
| 39 | GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)\r |
| 40 | GCC_ASM_EXPORT(ArmSetLowVectors)\r |
| 41 | GCC_ASM_EXPORT(ArmSetHighVectors)\r |
| 42 | GCC_ASM_EXPORT(ArmIsMpCore)\r |
| 43 | GCC_ASM_EXPORT(ArmCallWFI)\r |
| 44 | GCC_ASM_EXPORT(ArmReadMpidr)\r |
| 45 | GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)\r |
| 46 | GCC_ASM_EXPORT(ArmEnableFiq)\r |
| 47 | GCC_ASM_EXPORT(ArmDisableFiq)\r |
| 48 | GCC_ASM_EXPORT(ArmEnableInterrupts)\r |
| 49 | GCC_ASM_EXPORT(ArmDisableInterrupts)\r |
| 50 | GCC_ASM_EXPORT (ArmEnableVFP)\r |
| 51 | \r |
| 52 | Arm11PartNumberMask: .word 0xFFF0\r |
| 91c38d4e |
53 | Arm11PartNumber: .word 0xB020\r |
| 1e57a462 |
54 | \r |
| 55 | .set DC_ON, (0x1<<2)\r |
| 56 | .set IC_ON, (0x1<<12)\r |
| 57 | .set XP_ON, (0x1<<23)\r |
| 58 | .set CTRL_M_BIT, (1 << 0)\r |
| 59 | .set CTRL_C_BIT, (1 << 2)\r |
| 60 | .set CTRL_I_BIT, (1 << 12)\r |
| 61 | \r |
| 62 | ASM_PFX(ArmDisableCachesAndMmu):\r |
| 63 | mrc p15, 0, r0, c1, c0, 0 @ Get control register\r |
| 64 | bic r0, r0, #CTRL_M_BIT @ Disable MMU\r |
| 65 | bic r0, r0, #CTRL_C_BIT @ Disable D Cache\r |
| 66 | bic r0, r0, #CTRL_I_BIT @ Disable I Cache\r |
| 67 | mcr p15, 0, r0, c1, c0, 0 @ Write control register\r |
| 68 | bx LR\r |
| 69 | \r |
| 1e57a462 |
70 | ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r |
| 3402aac7 |
71 | mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line\r |
| 1e57a462 |
72 | bx lr\r |
| 73 | \r |
| 74 | \r |
| 75 | ASM_PFX(ArmCleanDataCacheEntryByMVA):\r |
| 3402aac7 |
76 | mcr p15, 0, r0, c7, c10, 1 @clean single data cache line\r |
| 1e57a462 |
77 | bx lr\r |
| 78 | \r |
| 79 | \r |
| 80 | ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r |
| 81 | mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line\r |
| 82 | bx lr\r |
| 83 | \r |
| 84 | \r |
| 85 | ASM_PFX(ArmCleanDataCache):\r |
| 86 | mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache\r |
| 87 | bx lr\r |
| 88 | \r |
| 89 | \r |
| 90 | ASM_PFX(ArmCleanInvalidateDataCache):\r |
| 91 | mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache\r |
| 92 | bx lr\r |
| 93 | \r |
| 94 | \r |
| 95 | ASM_PFX(ArmInvalidateDataCache):\r |
| 96 | mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache\r |
| 97 | bx lr\r |
| 98 | \r |
| 99 | \r |
| 100 | ASM_PFX(ArmInvalidateInstructionCache):\r |
| 101 | mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache\r |
| 102 | mov R0,#0\r |
| 103 | mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer\r |
| 104 | bx lr\r |
| 105 | \r |
| 106 | ASM_PFX(ArmEnableMmu):\r |
| 107 | mrc p15,0,R0,c1,c0,0\r |
| 108 | orr R0,R0,#1\r |
| 109 | mcr p15,0,R0,c1,c0,0\r |
| 110 | bx LR\r |
| 111 | \r |
| 112 | ASM_PFX(ArmMmuEnabled):\r |
| 113 | mrc p15,0,R0,c1,c0,0\r |
| 114 | and R0,R0,#1\r |
| 115 | bx LR\r |
| 116 | \r |
| 117 | ASM_PFX(ArmDisableMmu):\r |
| 118 | mrc p15,0,R0,c1,c0,0\r |
| 119 | bic R0,R0,#1\r |
| 120 | mcr p15,0,R0,c1,c0,0\r |
| 121 | mov R0,#0\r |
| 122 | mcr p15,0,R0,c7,c10,4 @Data synchronization barrier\r |
| 123 | mov R0,#0\r |
| 124 | mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer\r |
| 125 | bx LR\r |
| 126 | \r |
| 127 | ASM_PFX(ArmEnableDataCache):\r |
| 128 | LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON\r |
| 129 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r |
| 130 | orr R0,R0,R1 @Set C bit\r |
| 131 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r |
| 132 | bx LR\r |
| 3402aac7 |
133 | \r |
| 1e57a462 |
134 | ASM_PFX(ArmDisableDataCache):\r |
| 135 | LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON\r |
| 136 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r |
| 137 | bic R0,R0,R1 @Clear C bit\r |
| 138 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r |
| 139 | bx LR\r |
| 140 | \r |
| 141 | ASM_PFX(ArmEnableInstructionCache):\r |
| 142 | ldr R1,=IC_ON\r |
| 143 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r |
| 144 | orr R0,R0,R1 @Set I bit\r |
| 145 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r |
| 146 | bx LR\r |
| 3402aac7 |
147 | \r |
| 1e57a462 |
148 | ASM_PFX(ArmDisableInstructionCache):\r |
| 149 | ldr R1,=IC_ON\r |
| 150 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r |
| 151 | bic R0,R0,R1 @Clear I bit.\r |
| 152 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r |
| 153 | bx LR\r |
| 154 | \r |
| 155 | ASM_PFX(ArmEnableBranchPrediction):\r |
| 156 | mrc p15, 0, r0, c1, c0, 0\r |
| 157 | orr r0, r0, #0x00000800\r |
| 158 | mcr p15, 0, r0, c1, c0, 0\r |
| 159 | bx LR\r |
| 160 | \r |
| 161 | ASM_PFX(ArmDisableBranchPrediction):\r |
| 162 | mrc p15, 0, r0, c1, c0, 0\r |
| 163 | bic r0, r0, #0x00000800\r |
| 164 | mcr p15, 0, r0, c1, c0, 0\r |
| 165 | bx LR\r |
| 166 | \r |
| 167 | ASM_PFX(ArmDataMemoryBarrier):\r |
| 168 | mov R0, #0\r |
| 3402aac7 |
169 | mcr P15, #0, R0, C7, C10, #5\r |
| 1e57a462 |
170 | bx LR\r |
| 3402aac7 |
171 | \r |
| 1e57a462 |
172 | ASM_PFX(ArmDataSyncronizationBarrier):\r |
| 173 | mov R0, #0\r |
| 3402aac7 |
174 | mcr P15, #0, R0, C7, C10, #4\r |
| 1e57a462 |
175 | bx LR\r |
| 3402aac7 |
176 | \r |
| 1e57a462 |
177 | ASM_PFX(ArmInstructionSynchronizationBarrier):\r |
| 178 | mov R0, #0\r |
| 3402aac7 |
179 | mcr P15, #0, R0, C7, C5, #4\r |
| 1e57a462 |
180 | bx LR\r |
| 181 | \r |
| 182 | ASM_PFX(ArmSetLowVectors):\r |
| 183 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r |
| 184 | bic r0, r0, #0x00002000 @ clear V bit\r |
| 185 | mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r |
| 186 | bx LR\r |
| 187 | \r |
| 188 | ASM_PFX(ArmSetHighVectors):\r |
| 189 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r |
| 190 | orr r0, r0, #0x00002000 @ clear V bit\r |
| 191 | mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r |
| 192 | bx LR\r |
| 193 | \r |
| 194 | ASM_PFX(ArmIsMpCore):\r |
| 195 | push { r1 }\r |
| 196 | mrc p15, 0, r0, c0, c0, 0\r |
| 197 | # Extract Part Number to check it is an ARM11MP core (0xB02)\r |
| 198 | LoadConstantToReg (Arm11PartNumberMask, r1)\r |
| 199 | and r0, r0, r1\r |
| 200 | LoadConstantToReg (Arm11PartNumber, r1)\r |
| 201 | cmp r0, r1\r |
| 202 | movne r0, #0\r |
| 203 | pop { r1 }\r |
| 3402aac7 |
204 | bx lr\r |
| 1e57a462 |
205 | \r |
| 206 | ASM_PFX(ArmCallWFI):\r |
| 207 | wfi\r |
| 208 | bx lr\r |
| 209 | \r |
| 210 | ASM_PFX(ArmReadMpidr):\r |
| 211 | mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r |
| 212 | bx lr\r |
| 213 | \r |
| 214 | ASM_PFX(ArmEnableFiq):\r |
| 215 | mrs R0,CPSR\r |
| 216 | bic R0,R0,#0x40 @Enable FIQ interrupts\r |
| 217 | msr CPSR_c,R0\r |
| 218 | bx LR\r |
| 219 | \r |
| 220 | ASM_PFX(ArmDisableFiq):\r |
| 221 | mrs R0,CPSR\r |
| 222 | orr R1,R0,#0x40 @Disable FIQ interrupts\r |
| 223 | msr CPSR_c,R1\r |
| 224 | tst R0,#0x80\r |
| 225 | moveq R0,#1\r |
| 226 | movne R0,#0\r |
| 227 | bx LR\r |
| 228 | \r |
| 229 | ASM_PFX(ArmEnableInterrupts):\r |
| 230 | mrs R0,CPSR\r |
| 231 | bic R0,R0,#0x80 @Enable IRQ interrupts\r |
| 232 | msr CPSR_c,R0\r |
| 233 | bx LR\r |
| 234 | \r |
| 235 | ASM_PFX(ArmDisableInterrupts):\r |
| 236 | mrs R0,CPSR\r |
| 237 | orr R1,R0,#0x80 @Disable IRQ interrupts\r |
| 238 | msr CPSR_c,R1\r |
| 239 | tst R0,#0x80\r |
| 240 | moveq R0,#1\r |
| 241 | movne R0,#0\r |
| 242 | bx LR\r |
| 243 | \r |
| 244 | ASM_PFX(ArmEnableVFP):\r |
| 245 | # Read CPACR (Coprocessor Access Control Register)\r |
| 246 | mrc p15, 0, r0, c1, c0, 2\r |
| 247 | # Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r |
| 248 | orr r0, r0, #0x00f00000\r |
| 249 | # Write back CPACR (Coprocessor Access Control Register)\r |
| 250 | mcr p15, 0, r0, c1, c0, 2\r |
| 251 | # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r |
| 252 | mov r0, #0x40000000\r |
| 253 | #TODO: Fixme - need compilation flag\r |
| 254 | #fmxr FPEXC, r0\r |
| 255 | bx lr\r |
| 256 | \r |
| 257 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |
projects / mirror_edk2.git / blame