ArmPkg/ArmLib: Removed duplicated invalidate TLB function

ArmInvalidateInstructionAndDataTlb() was doing the same thing as
ArmInvalidateTlb().
Both invalidate Data and Instruction TLBs.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16253 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 0bb0d4a0639a27ad716a4e1cbc55d6086d81ba14..526b06a5caae958ede01ef276f0d52dcc23b8e38 100644 (file)
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -336,12 +336,6 @@ ArmDisableCachesAndMmu (
   VOID\r
   );\r
 \r
-VOID\r
-EFIAPI\r
-ArmInvalidateInstructionAndDataTlb (\r
-  VOID\r
-  );\r
-\r
 VOID\r
 EFIAPI\r
 ArmEnableInterrupts (\r
@@ -402,6 +396,9 @@ ArmGetFiqState (
   VOID\r
   );\r
 \r
+/**\r
+ * Invalidate Data and Instruction TLBs\r
+ */\r
 VOID\r
 EFIAPI\r
 ArmInvalidateTlb (\r

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index 76007505f30402f610b59019c1164df8827d4ecc..98eba3cac25ee6bbdc0e1ac93a76d6b51a9fc7b4 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -48,7 +48,6 @@ GCC_ASM_EXPORT (ArmWriteVBar)
 GCC_ASM_EXPORT (ArmReadVBar)\r
 GCC_ASM_EXPORT (ArmEnableVFP)\r
 GCC_ASM_EXPORT (ArmCallWFI)\r
-GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)\r
 GCC_ASM_EXPORT (ArmReadMpidr)\r
 GCC_ASM_EXPORT (ArmReadTpidrurw)\r
 GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
@@ -450,18 +449,6 @@ ASM_PFX(ArmCallWFI):
   ret\r
 \r
 \r
-ASM_PFX(ArmInvalidateInstructionAndDataTlb):\r
-   EL1_OR_EL2_OR_EL3(x0)\r
-1: tlbi  vmalle1\r
-   b     4f\r
-2: tlbi  alle2\r
-   b     4f\r
-3: tlbi  alle3\r
-4: dsb   sy\r
-   isb\r
-   ret\r
-\r
-\r
 ASM_PFX(ArmReadMpidr):\r
   mrs   x0, mpidr_el1           // read EL1 MPIDR\r
   ret\r

diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
index 60e92fdc6a484ecfbdfb04b64d004d39e3b90c13..25612f35ec6365f46f1ca2fbeb1ce4f7ac2f7747 100644 (file)
--- a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
@@ -18,7 +18,6 @@
 .text\r
 .align 2\r
 GCC_ASM_EXPORT(ArmDisableCachesAndMmu)\r
-GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)\r
 GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)\r
 GCC_ASM_EXPORT(ArmCleanDataCache)\r
 GCC_ASM_EXPORT(ArmInvalidateDataCache)\r
@@ -68,10 +67,6 @@ ASM_PFX(ArmDisableCachesAndMmu):
   mcr   p15, 0, r0, c1, c0, 0           @ Write control register\r
   bx      LR\r
 \r
-ASM_PFX(ArmInvalidateInstructionAndDataTlb):\r
-  mcr     p15, 0, r0, c8, c7, 0      @ Invalidate Inst TLB and Data TLB\r
-  bx lr\r
-\r
 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line\r
   bx      lr\r

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
index c31d49bcfb01c04912c4647a028af5421abc4aeb..af5ec23a1a4f5d67f123932a394567bf24342c04 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
@@ -47,7 +47,6 @@ GCC_ASM_EXPORT (ArmWriteVBar)
 GCC_ASM_EXPORT (ArmEnableVFP)\r
 GCC_ASM_EXPORT (ArmCallWFI)\r
 GCC_ASM_EXPORT (ArmReadCbar)\r
-GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)\r
 GCC_ASM_EXPORT (ArmReadMpidr)\r
 GCC_ASM_EXPORT (ArmReadTpidrurw)\r
 GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
@@ -368,11 +367,6 @@ ASM_PFX(ArmReadCbar):
   mrc     p15, 4, r0, c15, c0, 0  @ Read Configuration Base Address Register\r
   bx      lr\r
 \r
-ASM_PFX(ArmInvalidateInstructionAndDataTlb):\r
-  mcr     p15, 0, r0, c8, c7, 0      @ Invalidate Inst TLB and Data TLB\r
-  dsb\r
-  bx lr\r
-\r
 ASM_PFX(ArmReadMpidr):\r
   mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR\r
   bx      lr\r

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
index 368138933a356fdddec7ebc3951c11a685227eef..2b13811dc6cfc31479de320ac9ed2d6c656a6d8a 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
@@ -44,7 +44,6 @@
     EXPORT  ArmEnableVFP\r
     EXPORT  ArmCallWFI\r
     EXPORT  ArmReadCbar\r
-    EXPORT  ArmInvalidateInstructionAndDataTlb\r
     EXPORT  ArmReadMpidr\r
     EXPORT  ArmReadTpidrurw\r
     EXPORT  ArmWriteTpidrurw\r
@@ -362,11 +361,6 @@ ArmReadCbar
   mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register\r
   bx      lr\r
 \r
-ArmInvalidateInstructionAndDataTlb\r
-  mcr     p15, 0, r0, c8, c7, 0      ; Invalidate Inst TLB and Data TLB\r
-  dsb\r
-  bx lr\r
-\r
 ArmReadMpidr\r
   mrc     p15, 0, r0, c0, c0, 5     ; read MPIDR\r
   bx      lr\r

diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c
index 015c1613c6d66e99d5e70244da323a21f73d965c..15584f19010764a693da873f9999c8d573cea614 100644 (file)
--- a/ArmPlatformPkg/Sec/Sec.c
+++ b/ArmPlatformPkg/Sec/Sec.c
@@ -42,7 +42,7 @@ CEntryPoint (
   ArmInvalidateInstructionCache ();\r
 \r
   // Invalidate I & D TLBs\r
-  ArmInvalidateInstructionAndDataTlb ();\r
+  ArmInvalidateTlb ();\r
 \r
   // CPU specific settings\r
   ArmCpuSetup (MpId);\r