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2 Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
4 The PCI Segment Library function provide services to read, write, and modify the PCI configuration
5 registers on PCI root bridges on any supported PCI segment. These library services take a single
6 address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.
7 The layout of this address parameter is as follows:
9 PCI Register: Bits 0..11
10 PCI Function Bits 12..14
11 PCI Device Bits 15..19
13 Reserved Bits 28..31. Must be 0.
14 PCI Segment Bits 32..47
15 Reserved Bits 48..63. Must be 0.
17 | Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |
18 63 48 47 32 31 28 27 20 19 15 14 12 11 0
20 These functions perform PCI configuration cycles using the default PCI configuration access
21 method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
22 may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate
23 access method. Modules will typically use the PCI Segment Library for its PCI configuration
24 accesses when PCI Segments other than Segment #0 must be accessed.
26 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
27 This program and the accompanying materials
28 are licensed and made available under the terms and conditions of the BSD License
29 which accompanies this distribution. The full text of the license may be found at
30 http://opensource.org/licenses/bsd-license.php
32 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
33 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
37 #ifndef __PCI_SEGMENT_LIB__
38 #define __PCI_SEGMENT_LIB__
42 Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
43 and PCI Register to an address that can be passed to the PCI Segment Library functions.
45 Computes an address that is compatible with the PCI Segment Library functions.
46 The unused upper bits of Segment, Bus, Device, Function,
47 and Register are stripped prior to the generation of the address.
49 @param Segment PCI Segment number. Range 0..65535.
50 @param Bus PCI Bus number. Range 0..255.
51 @param Device PCI Device number. Range 0..31.
52 @param Function PCI Function number. Range 0..7.
53 @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.
55 @return The address that is compatible with the PCI Segment Library functions.
58 #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \
60 ( ((Register) & 0xfff) | \
61 (((Function) & 0x07) << 12) | \
62 (((Device) & 0x1f) << 15) | \
63 (((Bus) & 0xff) << 20) | \
64 (LShiftU64 ((Segment) & 0xffff, 32)) \
66 ( ((Register) & 0xfff) | \
67 (((Function) & 0x07) << 12) | \
68 (((Device) & 0x1f) << 15) | \
69 (((Bus) & 0xff) << 20) \
74 Register a PCI device so PCI configuration registers may be accessed after
75 SetVirtualAddressMap().
77 If any reserved bits in Address are set, then ASSERT().
79 @param Address Address that encodes the PCI Bus, Device, Function and
82 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
83 @retval RETURN_UNSUPPORTED An attempt was made to call this function
84 after ExitBootServices().
85 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
86 at runtime could not be mapped.
87 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
88 complete the registration.
93 PciSegmentRegisterForRuntimeAccess (
98 Reads an 8-bit PCI configuration register.
100 Reads and returns the 8-bit PCI configuration register specified by Address.
101 This function must guarantee that all PCI read and write operations are serialized.
103 If any reserved bits in Address are set, then ASSERT().
105 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
107 @return The 8-bit PCI configuration register specified by Address.
117 Writes an 8-bit PCI configuration register.
119 Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
120 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
122 If any reserved bits in Address are set, then ASSERT().
124 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
125 @param Value The value to write.
127 @return The value written to the PCI configuration register.
138 Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
140 Reads the 8-bit PCI configuration register specified by Address,
141 performs a bitwise OR between the read result and the value specified by OrData,
142 and writes the result to the 8-bit PCI configuration register specified by Address.
143 The value written to the PCI configuration register is returned.
144 This function must guarantee that all PCI read and write operations are serialized.
146 If any reserved bits in Address are set, then ASSERT().
148 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
149 @param OrData The value to OR with the PCI configuration register.
151 @return The value written to the PCI configuration register.
162 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
164 Reads the 8-bit PCI configuration register specified by Address,
165 performs a bitwise AND between the read result and the value specified by AndData,
166 and writes the result to the 8-bit PCI configuration register specified by Address.
167 The value written to the PCI configuration register is returned.
168 This function must guarantee that all PCI read and write operations are serialized.
169 If any reserved bits in Address are set, then ASSERT().
171 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
172 @param AndData The value to AND with the PCI configuration register.
174 @return The value written to the PCI configuration register.
185 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
186 followed a bitwise OR with another 8-bit value.
188 Reads the 8-bit PCI configuration register specified by Address,
189 performs a bitwise AND between the read result and the value specified by AndData,
190 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
191 and writes the result to the 8-bit PCI configuration register specified by Address.
192 The value written to the PCI configuration register is returned.
193 This function must guarantee that all PCI read and write operations are serialized.
195 If any reserved bits in Address are set, then ASSERT().
197 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
198 @param AndData The value to AND with the PCI configuration register.
199 @param OrData The value to OR with the PCI configuration register.
201 @return The value written to the PCI configuration register.
206 PciSegmentAndThenOr8 (
213 Reads a bit field of a PCI configuration register.
215 Reads the bit field in an 8-bit PCI configuration register. The bit field is
216 specified by the StartBit and the EndBit. The value of the bit field is
219 If any reserved bits in Address are set, then ASSERT().
220 If StartBit is greater than 7, then ASSERT().
221 If EndBit is greater than 7, then ASSERT().
222 If EndBit is less than StartBit, then ASSERT().
224 @param Address PCI configuration register to read.
225 @param StartBit The ordinal of the least significant bit in the bit field.
227 @param EndBit The ordinal of the most significant bit in the bit field.
230 @return The value of the bit field read from the PCI configuration register.
235 PciSegmentBitFieldRead8 (
242 Writes a bit field to a PCI configuration register.
244 Writes Value to the bit field of the PCI configuration register. The bit
245 field is specified by the StartBit and the EndBit. All other bits in the
246 destination PCI configuration register are preserved. The new value of the
247 8-bit register is returned.
249 If any reserved bits in Address are set, then ASSERT().
250 If StartBit is greater than 7, then ASSERT().
251 If EndBit is greater than 7, then ASSERT().
252 If EndBit is less than StartBit, then ASSERT().
253 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
255 @param Address PCI configuration register to write.
256 @param StartBit The ordinal of the least significant bit in the bit field.
258 @param EndBit The ordinal of the most significant bit in the bit field.
260 @param Value New value of the bit field.
262 @return The value written back to the PCI configuration register.
267 PciSegmentBitFieldWrite8 (
275 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
276 writes the result back to the bit field in the 8-bit port.
278 Reads the 8-bit PCI configuration register specified by Address, performs a
279 bitwise OR between the read result and the value specified by
280 OrData, and writes the result to the 8-bit PCI configuration register
281 specified by Address. The value written to the PCI configuration register is
282 returned. This function must guarantee that all PCI read and write operations
283 are serialized. Extra left bits in OrData are stripped.
285 If any reserved bits in Address are set, then ASSERT().
286 If StartBit is greater than 7, then ASSERT().
287 If EndBit is greater than 7, then ASSERT().
288 If EndBit is less than StartBit, then ASSERT().
289 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
291 @param Address PCI configuration register to write.
292 @param StartBit The ordinal of the least significant bit in the bit field.
294 @param EndBit The ordinal of the most significant bit in the bit field.
296 @param OrData The value to OR with the PCI configuration register.
298 @return The value written back to the PCI configuration register.
303 PciSegmentBitFieldOr8 (
311 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
312 AND, and writes the result back to the bit field in the 8-bit register.
314 Reads the 8-bit PCI configuration register specified by Address, performs a
315 bitwise AND between the read result and the value specified by AndData, and
316 writes the result to the 8-bit PCI configuration register specified by
317 Address. The value written to the PCI configuration register is returned.
318 This function must guarantee that all PCI read and write operations are
319 serialized. Extra left bits in AndData are stripped.
321 If any reserved bits in Address are set, then ASSERT().
322 If StartBit is greater than 7, then ASSERT().
323 If EndBit is greater than 7, then ASSERT().
324 If EndBit is less than StartBit, then ASSERT().
325 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
327 @param Address PCI configuration register to write.
328 @param StartBit The ordinal of the least significant bit in the bit field.
330 @param EndBit The ordinal of the most significant bit in the bit field.
332 @param AndData The value to AND with the PCI configuration register.
334 @return The value written back to the PCI configuration register.
339 PciSegmentBitFieldAnd8 (
347 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
348 bitwise OR, and writes the result back to the bit field in the
351 Reads the 8-bit PCI configuration register specified by Address, performs a
352 bitwise AND followed by a bitwise OR between the read result and
353 the value specified by AndData, and writes the result to the 8-bit PCI
354 configuration register specified by Address. The value written to the PCI
355 configuration register is returned. This function must guarantee that all PCI
356 read and write operations are serialized. Extra left bits in both AndData and
359 If any reserved bits in Address are set, then ASSERT().
360 If StartBit is greater than 7, then ASSERT().
361 If EndBit is greater than 7, then ASSERT().
362 If EndBit is less than StartBit, then ASSERT().
363 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
364 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
366 @param Address PCI configuration register to write.
367 @param StartBit The ordinal of the least significant bit in the bit field.
369 @param EndBit The ordinal of the most significant bit in the bit field.
371 @param AndData The value to AND with the PCI configuration register.
372 @param OrData The value to OR with the result of the AND operation.
374 @return The value written back to the PCI configuration register.
379 PciSegmentBitFieldAndThenOr8 (
388 Reads a 16-bit PCI configuration register.
390 Reads and returns the 16-bit PCI configuration register specified by Address.
391 This function must guarantee that all PCI read and write operations are serialized.
393 If any reserved bits in Address are set, then ASSERT().
394 If Address is not aligned on a 16-bit boundary, then ASSERT().
396 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
398 @return The 16-bit PCI configuration register specified by Address.
408 Writes a 16-bit PCI configuration register.
410 Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
411 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
413 If any reserved bits in Address are set, then ASSERT().
414 If Address is not aligned on a 16-bit boundary, then ASSERT().
416 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
417 @param Value The value to write.
419 @return The parameter of Value.
430 Performs a bitwise OR of a 16-bit PCI configuration register with
433 Reads the 16-bit PCI configuration register specified by Address, performs a
434 bitwise OR between the read result and the value specified by
435 OrData, and writes the result to the 16-bit PCI configuration register
436 specified by Address. The value written to the PCI configuration register is
437 returned. This function must guarantee that all PCI read and write operations
440 If any reserved bits in Address are set, then ASSERT().
441 If Address is not aligned on a 16-bit boundary, then ASSERT().
443 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
445 @param OrData The value to OR with the PCI configuration register.
447 @return The value written back to the PCI configuration register.
458 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
460 Reads the 16-bit PCI configuration register specified by Address,
461 performs a bitwise AND between the read result and the value specified by AndData,
462 and writes the result to the 16-bit PCI configuration register specified by Address.
463 The value written to the PCI configuration register is returned.
464 This function must guarantee that all PCI read and write operations are serialized.
466 If any reserved bits in Address are set, then ASSERT().
467 If Address is not aligned on a 16-bit boundary, then ASSERT().
469 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
470 @param AndData The value to AND with the PCI configuration register.
472 @return The value written to the PCI configuration register.
483 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
484 followed a bitwise OR with another 16-bit value.
486 Reads the 16-bit PCI configuration register specified by Address,
487 performs a bitwise AND between the read result and the value specified by AndData,
488 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
489 and writes the result to the 16-bit PCI configuration register specified by Address.
490 The value written to the PCI configuration register is returned.
491 This function must guarantee that all PCI read and write operations are serialized.
493 If any reserved bits in Address are set, then ASSERT().
494 If Address is not aligned on a 16-bit boundary, then ASSERT().
496 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
497 @param AndData The value to AND with the PCI configuration register.
498 @param OrData The value to OR with the PCI configuration register.
500 @return The value written to the PCI configuration register.
505 PciSegmentAndThenOr16 (
512 Reads a bit field of a PCI configuration register.
514 Reads the bit field in a 16-bit PCI configuration register. The bit field is
515 specified by the StartBit and the EndBit. The value of the bit field is
518 If any reserved bits in Address are set, then ASSERT().
519 If Address is not aligned on a 16-bit boundary, then ASSERT().
520 If StartBit is greater than 15, then ASSERT().
521 If EndBit is greater than 15, then ASSERT().
522 If EndBit is less than StartBit, then ASSERT().
524 @param Address PCI configuration register to read.
525 @param StartBit The ordinal of the least significant bit in the bit field.
527 @param EndBit The ordinal of the most significant bit in the bit field.
530 @return The value of the bit field read from the PCI configuration register.
535 PciSegmentBitFieldRead16 (
542 Writes a bit field to a PCI configuration register.
544 Writes Value to the bit field of the PCI configuration register. The bit
545 field is specified by the StartBit and the EndBit. All other bits in the
546 destination PCI configuration register are preserved. The new value of the
547 16-bit register is returned.
549 If any reserved bits in Address are set, then ASSERT().
550 If Address is not aligned on a 16-bit boundary, then ASSERT().
551 If StartBit is greater than 15, then ASSERT().
552 If EndBit is greater than 15, then ASSERT().
553 If EndBit is less than StartBit, then ASSERT().
554 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
556 @param Address PCI configuration register to write.
557 @param StartBit The ordinal of the least significant bit in the bit field.
559 @param EndBit The ordinal of the most significant bit in the bit field.
561 @param Value New value of the bit field.
563 @return The value written back to the PCI configuration register.
568 PciSegmentBitFieldWrite16 (
576 Reads the 16-bit PCI configuration register specified by Address,
577 performs a bitwise OR between the read result and the value specified by OrData,
578 and writes the result to the 16-bit PCI configuration register specified by Address.
580 If any reserved bits in Address are set, then ASSERT().
581 If Address is not aligned on a 16-bit boundary, then ASSERT().
582 If StartBit is greater than 15, then ASSERT().
583 If EndBit is greater than 15, then ASSERT().
584 If EndBit is less than StartBit, then ASSERT().
585 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
587 @param Address PCI configuration register to write.
588 @param StartBit The ordinal of the least significant bit in the bit field.
590 @param EndBit The ordinal of the most significant bit in the bit field.
592 @param OrData The value to OR with the PCI configuration register.
594 @return The value written back to the PCI configuration register.
599 PciSegmentBitFieldOr16 (
607 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
608 and writes the result back to the bit field in the 16-bit port.
610 Reads the 16-bit PCI configuration register specified by Address,
611 performs a bitwise OR between the read result and the value specified by OrData,
612 and writes the result to the 16-bit PCI configuration register specified by Address.
613 The value written to the PCI configuration register is returned.
614 This function must guarantee that all PCI read and write operations are serialized.
615 Extra left bits in OrData are stripped.
617 If any reserved bits in Address are set, then ASSERT().
618 If Address is not aligned on a 16-bit boundary, then ASSERT().
619 If StartBit is greater than 7, then ASSERT().
620 If EndBit is greater than 7, then ASSERT().
621 If EndBit is less than StartBit, then ASSERT().
622 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
624 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
625 @param StartBit The ordinal of the least significant bit in the bit field.
626 The ordinal of the least significant bit in a byte is bit 0.
627 @param EndBit The ordinal of the most significant bit in the bit field.
628 The ordinal of the most significant bit in a byte is bit 7.
629 @param AndData The value to AND with the read value from the PCI configuration register.
631 @return The value written to the PCI configuration register.
636 PciSegmentBitFieldAnd16 (
644 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
645 bitwise OR, and writes the result back to the bit field in the
648 Reads the 16-bit PCI configuration register specified by Address, performs a
649 bitwise AND followed by a bitwise OR between the read result and
650 the value specified by AndData, and writes the result to the 16-bit PCI
651 configuration register specified by Address. The value written to the PCI
652 configuration register is returned. This function must guarantee that all PCI
653 read and write operations are serialized. Extra left bits in both AndData and
656 If any reserved bits in Address are set, then ASSERT().
657 If StartBit is greater than 15, then ASSERT().
658 If EndBit is greater than 15, then ASSERT().
659 If EndBit is less than StartBit, then ASSERT().
660 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
661 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
663 @param Address PCI configuration register to write.
664 @param StartBit The ordinal of the least significant bit in the bit field.
666 @param EndBit The ordinal of the most significant bit in the bit field.
668 @param AndData The value to AND with the PCI configuration register.
669 @param OrData The value to OR with the result of the AND operation.
671 @return The value written back to the PCI configuration register.
676 PciSegmentBitFieldAndThenOr16 (
685 Reads a 32-bit PCI configuration register.
687 Reads and returns the 32-bit PCI configuration register specified by Address.
688 This function must guarantee that all PCI read and write operations are serialized.
690 If any reserved bits in Address are set, then ASSERT().
691 If Address is not aligned on a 32-bit boundary, then ASSERT().
693 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
695 @return The 32-bit PCI configuration register specified by Address.
705 Writes a 32-bit PCI configuration register.
707 Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
708 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
710 If any reserved bits in Address are set, then ASSERT().
711 If Address is not aligned on a 32-bit boundary, then ASSERT().
713 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
714 @param Value The value to write.
716 @return The parameter of Value.
727 Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
729 Reads the 32-bit PCI configuration register specified by Address,
730 performs a bitwise OR between the read result and the value specified by OrData,
731 and writes the result to the 32-bit PCI configuration register specified by Address.
732 The value written to the PCI configuration register is returned.
733 This function must guarantee that all PCI read and write operations are serialized.
735 If any reserved bits in Address are set, then ASSERT().
736 If Address is not aligned on a 32-bit boundary, then ASSERT().
738 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
739 @param OrData The value to OR with the PCI configuration register.
741 @return The value written to the PCI configuration register.
752 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
754 Reads the 32-bit PCI configuration register specified by Address,
755 performs a bitwise AND between the read result and the value specified by AndData,
756 and writes the result to the 32-bit PCI configuration register specified by Address.
757 The value written to the PCI configuration register is returned.
758 This function must guarantee that all PCI read and write operations are serialized.
760 If any reserved bits in Address are set, then ASSERT().
761 If Address is not aligned on a 32-bit boundary, then ASSERT().
763 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
764 @param AndData The value to AND with the PCI configuration register.
766 @return The value written to the PCI configuration register.
777 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
778 followed a bitwise OR with another 32-bit value.
780 Reads the 32-bit PCI configuration register specified by Address,
781 performs a bitwise AND between the read result and the value specified by AndData,
782 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
783 and writes the result to the 32-bit PCI configuration register specified by Address.
784 The value written to the PCI configuration register is returned.
785 This function must guarantee that all PCI read and write operations are serialized.
787 If any reserved bits in Address are set, then ASSERT().
788 If Address is not aligned on a 32-bit boundary, then ASSERT().
790 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
791 @param AndData The value to AND with the PCI configuration register.
792 @param OrData The value to OR with the PCI configuration register.
794 @return The value written to the PCI configuration register.
799 PciSegmentAndThenOr32 (
806 Reads a bit field of a PCI configuration register.
808 Reads the bit field in a 32-bit PCI configuration register. The bit field is
809 specified by the StartBit and the EndBit. The value of the bit field is
812 If any reserved bits in Address are set, then ASSERT().
813 If Address is not aligned on a 32-bit boundary, then ASSERT().
814 If StartBit is greater than 31, then ASSERT().
815 If EndBit is greater than 31, then ASSERT().
816 If EndBit is less than StartBit, then ASSERT().
818 @param Address PCI configuration register to read.
819 @param StartBit The ordinal of the least significant bit in the bit field.
821 @param EndBit The ordinal of the most significant bit in the bit field.
824 @return The value of the bit field read from the PCI configuration register.
829 PciSegmentBitFieldRead32 (
836 Writes a bit field to a PCI configuration register.
838 Writes Value to the bit field of the PCI configuration register. The bit
839 field is specified by the StartBit and the EndBit. All other bits in the
840 destination PCI configuration register are preserved. The new value of the
841 32-bit register is returned.
843 If any reserved bits in Address are set, then ASSERT().
844 If Address is not aligned on a 32-bit boundary, then ASSERT().
845 If StartBit is greater than 31, then ASSERT().
846 If EndBit is greater than 31, then ASSERT().
847 If EndBit is less than StartBit, then ASSERT().
848 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
850 @param Address PCI configuration register to write.
851 @param StartBit The ordinal of the least significant bit in the bit field.
853 @param EndBit The ordinal of the most significant bit in the bit field.
855 @param Value New value of the bit field.
857 @return The value written back to the PCI configuration register.
862 PciSegmentBitFieldWrite32 (
870 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
871 writes the result back to the bit field in the 32-bit port.
873 Reads the 32-bit PCI configuration register specified by Address, performs a
874 bitwise OR between the read result and the value specified by
875 OrData, and writes the result to the 32-bit PCI configuration register
876 specified by Address. The value written to the PCI configuration register is
877 returned. This function must guarantee that all PCI read and write operations
878 are serialized. Extra left bits in OrData are stripped.
880 If any reserved bits in Address are set, then ASSERT().
881 If StartBit is greater than 31, then ASSERT().
882 If EndBit is greater than 31, then ASSERT().
883 If EndBit is less than StartBit, then ASSERT().
884 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
886 @param Address PCI configuration register to write.
887 @param StartBit The ordinal of the least significant bit in the bit field.
889 @param EndBit The ordinal of the most significant bit in the bit field.
891 @param OrData The value to OR with the PCI configuration register.
893 @return The value written back to the PCI configuration register.
898 PciSegmentBitFieldOr32 (
906 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
907 AND, and writes the result back to the bit field in the 32-bit register.
910 Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
911 AND between the read result and the value specified by AndData, and writes the result
912 to the 32-bit PCI configuration register specified by Address. The value written to
913 the PCI configuration register is returned. This function must guarantee that all PCI
914 read and write operations are serialized. Extra left bits in AndData are stripped.
915 If any reserved bits in Address are set, then ASSERT().
916 If Address is not aligned on a 32-bit boundary, then ASSERT().
917 If StartBit is greater than 31, then ASSERT().
918 If EndBit is greater than 31, then ASSERT().
919 If EndBit is less than StartBit, then ASSERT().
920 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
922 @param Address PCI configuration register to write.
923 @param StartBit The ordinal of the least significant bit in the bit field.
925 @param EndBit The ordinal of the most significant bit in the bit field.
927 @param AndData The value to AND with the PCI configuration register.
929 @return The value written back to the PCI configuration register.
934 PciSegmentBitFieldAnd32 (
942 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
943 bitwise OR, and writes the result back to the bit field in the
946 Reads the 32-bit PCI configuration register specified by Address, performs a
947 bitwise AND followed by a bitwise OR between the read result and
948 the value specified by AndData, and writes the result to the 32-bit PCI
949 configuration register specified by Address. The value written to the PCI
950 configuration register is returned. This function must guarantee that all PCI
951 read and write operations are serialized. Extra left bits in both AndData and
954 If any reserved bits in Address are set, then ASSERT().
955 If StartBit is greater than 31, then ASSERT().
956 If EndBit is greater than 31, then ASSERT().
957 If EndBit is less than StartBit, then ASSERT().
958 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
959 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
961 @param Address PCI configuration register to write.
962 @param StartBit The ordinal of the least significant bit in the bit field.
964 @param EndBit The ordinal of the most significant bit in the bit field.
966 @param AndData The value to AND with the PCI configuration register.
967 @param OrData The value to OR with the result of the AND operation.
969 @return The value written back to the PCI configuration register.
974 PciSegmentBitFieldAndThenOr32 (
983 Reads a range of PCI configuration registers into a caller supplied buffer.
985 Reads the range of PCI configuration registers specified by StartAddress and
986 Size into the buffer specified by Buffer. This function only allows the PCI
987 configuration registers from a single PCI function to be read. Size is
988 returned. When possible 32-bit PCI configuration read cycles are used to read
989 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
990 and 16-bit PCI configuration read cycles may be used at the beginning and the
993 If any reserved bits in StartAddress are set, then ASSERT().
994 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
995 If Size > 0 and Buffer is NULL, then ASSERT().
997 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
998 Function and Register.
999 @param Size Size in bytes of the transfer.
1000 @param Buffer Pointer to a buffer receiving the data read.
1007 PciSegmentReadBuffer (
1008 IN UINT64 StartAddress
,
1014 Copies the data in a caller supplied buffer to a specified range of PCI
1015 configuration space.
1017 Writes the range of PCI configuration registers specified by StartAddress and
1018 Size from the buffer specified by Buffer. This function only allows the PCI
1019 configuration registers from a single PCI function to be written. Size is
1020 returned. When possible 32-bit PCI configuration write cycles are used to
1021 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1022 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1023 and the end of the range.
1025 If any reserved bits in StartAddress are set, then ASSERT().
1026 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1027 If Size > 0 and Buffer is NULL, then ASSERT().
1029 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
1030 Function and Register.
1031 @param Size Size in bytes of the transfer.
1032 @param Buffer Pointer to a buffer containing the data to write.
1034 @return The parameter of Size.
1039 PciSegmentWriteBuffer (
1040 IN UINT64 StartAddress
,