2 Board config definitions for each of the boards supported by this platform
5 Copyright (c) 2013 Intel Corporation.
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #ifndef __PLATFORM_BOARDS_H__
20 #define __PLATFORM_BOARDS_H__
23 // Constant definition
27 // Default resume well TPM reset.
29 #define PLATFORM_RESUMEWELL_TPM_RST_GPIO 5
32 // Basic Configs for GPIO table definitions.
34 #define NULL_LEGACY_GPIO_INITIALIZER {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}
35 #define ALL_INPUT_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x00,0x00,0x00,0x3f,0x00}
36 #define QUARK_EMULATION_LEGACY_GPIO_INITIALIZER ALL_INPUT_LEGACY_GPIO_INITIALIZER
37 #define CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x3f,0x3f,0x00,0x3f,0x00}
38 #define KIPS_BAY_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x25,0x10,0x00,0x00,0x00,0x00,0x3f,0x00}
39 #define CROSS_HILL_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x03,0x10,0x00,0x03,0x03,0x00,0x3f,0x00}
40 #define CLANTON_HILL_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x06,0x10,0x00,0x04,0x04,0x00,0x3f,0x00}
41 #define GALILEO_LEGACY_GPIO_INITIALIZER {0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x21,0x14,0x00,0x00,0x00,0x00,0x3f,0x00}
42 #define GALILEO_GEN2_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x1c,0x02,0x00,0x00,0x00,0x00,0x3f,0x00}
44 #define NULL_GPIO_CONTROLLER_INITIALIZER {0,0,0,0,0,0,0,0}
45 #define ALL_INPUT_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER
46 #define QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER
47 #define CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER
48 #define KIPS_BAY_GPIO_CONTROLLER_INITIALIZER {0x05,0x05,0,0,0,0,0,0}
49 #define CROSS_HILL_GPIO_CONTROLLER_INITIALIZER {0x0D,0x2D,0,0,0,0,0,0}
50 #define CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER {0x01,0x39,0,0,0,0,0,0}
51 #define GALILEO_GPIO_CONTROLLER_INITIALIZER {0x05,0x15,0,0,0,0,0,0}
52 #define GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER {0x05,0x05,0,0,0,0,0,0}
55 // Legacy Gpio to be used to assert / deassert PCI express PERST# signal
56 // on Galileo Gen 2 platform.
58 #define GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO 0
61 // Io expander slave address.
65 // On Galileo value of Jumper J2 determines slave address of io expander.
67 #define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO 5
68 #define GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR 0x20
69 #define GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR 0x21
72 // Three IO Expmanders at fixed addresses on Galileo Gen2.
74 #define GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR 0x25
75 #define GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR 0x26
76 #define GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR 0x27
79 // Led GPIOs for flash update / recovery.
81 #define GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO 1
82 #define GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO 5
85 // Legacy GPIO config struct for each element in PLATFORM_LEGACY_GPIO_TABLE_DEFINITION.
88 UINT32 CoreWellEnable
; ///< Value for QNC NC Reg R_QNC_GPIO_CGEN_CORE_WELL.
89 UINT32 CoreWellIoSelect
; ///< Value for QNC NC Reg R_QNC_GPIO_CGIO_CORE_WELL.
90 UINT32 CoreWellLvlForInputOrOutput
; ///< Value for QNC NC Reg R_QNC_GPIO_CGLVL_CORE_WELL.
91 UINT32 CoreWellTriggerPositiveEdge
; ///< Value for QNC NC Reg R_QNC_GPIO_CGTPE_CORE_WELL.
92 UINT32 CoreWellTriggerNegativeEdge
; ///< Value for QNC NC Reg R_QNC_GPIO_CGTNE_CORE_WELL.
93 UINT32 CoreWellGPEEnable
; ///< Value for QNC NC Reg R_QNC_GPIO_CGGPE_CORE_WELL.
94 UINT32 CoreWellSMIEnable
; ///< Value for QNC NC Reg R_QNC_GPIO_CGSMI_CORE_WELL.
95 UINT32 CoreWellTriggerStatus
; ///< Value for QNC NC Reg R_QNC_GPIO_CGTS_CORE_WELL.
96 UINT32 CoreWellNMIEnable
; ///< Value for QNC NC Reg R_QNC_GPIO_CGNMIEN_CORE_WELL.
97 UINT32 ResumeWellEnable
; ///< Value for QNC NC Reg R_QNC_GPIO_RGEN_RESUME_WELL.
98 UINT32 ResumeWellIoSelect
; ///< Value for QNC NC Reg R_QNC_GPIO_RGIO_RESUME_WELL.
99 UINT32 ResumeWellLvlForInputOrOutput
;///< Value for QNC NC Reg R_QNC_GPIO_RGLVL_RESUME_WELL.
100 UINT32 ResumeWellTriggerPositiveEdge
;///< Value for QNC NC Reg R_QNC_GPIO_RGTPE_RESUME_WELL.
101 UINT32 ResumeWellTriggerNegativeEdge
;///< Value for QNC NC Reg R_QNC_GPIO_RGTNE_RESUME_WELL.
102 UINT32 ResumeWellGPEEnable
; ///< Value for QNC NC Reg R_QNC_GPIO_RGGPE_RESUME_WELL.
103 UINT32 ResumeWellSMIEnable
; ///< Value for QNC NC Reg R_QNC_GPIO_RGSMI_RESUME_WELL.
104 UINT32 ResumeWellTriggerStatus
; ///< Value for QNC NC Reg R_QNC_GPIO_RGTS_RESUME_WELL.
105 UINT32 ResumeWellNMIEnable
; ///< Value for QNC NC Reg R_QNC_GPIO_RGNMIEN_RESUME_WELL.
106 } BOARD_LEGACY_GPIO_CONFIG
;
109 // GPIO controller config struct for each element in PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION.
112 UINT32 PortADR
; ///< Value for IOH REG GPIO_SWPORTA_DR.
113 UINT32 PortADir
; ///< Value for IOH REG GPIO_SWPORTA_DDR.
114 UINT32 IntEn
; ///< Value for IOH REG GPIO_INTEN.
115 UINT32 IntMask
; ///< Value for IOH REG GPIO_INTMASK.
116 UINT32 IntType
; ///< Value for IOH REG GPIO_INTTYPE_LEVEL.
117 UINT32 IntPolarity
; ///< Value for IOH REG GPIO_INT_POLARITY.
118 UINT32 Debounce
; ///< Value for IOH REG GPIO_DEBOUNCE.
119 UINT32 LsSync
; ///< Value for IOH REG GPIO_LS_SYNC.
120 } BOARD_GPIO_CONTROLLER_CONFIG
;
123 /// Table of BOARD_LEGACY_GPIO_CONFIG structures for each board supported
124 /// by this platform package.
125 /// Table indexed with EFI_PLATFORM_TYPE enum value.
127 #define PLATFORM_LEGACY_GPIO_TABLE_DEFINITION \
128 /* EFI_PLATFORM_TYPE - TypeUnknown*/\
129 NULL_LEGACY_GPIO_INITIALIZER,\
130 /* EFI_PLATFORM_TYPE - QuarkEmulation*/\
131 QUARK_EMULATION_LEGACY_GPIO_INITIALIZER,\
132 /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\
133 CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER,\
134 /* EFI_PLATFORM_TYPE - KipsBay*/\
135 KIPS_BAY_LEGACY_GPIO_INITIALIZER,\
136 /* EFI_PLATFORM_TYPE - CrossHill*/\
137 CROSS_HILL_LEGACY_GPIO_INITIALIZER,\
138 /* EFI_PLATFORM_TYPE - ClantonHill*/\
139 CLANTON_HILL_LEGACY_GPIO_INITIALIZER,\
140 /* EFI_PLATFORM_TYPE - Galileo*/\
141 GALILEO_LEGACY_GPIO_INITIALIZER,\
142 /* EFI_PLATFORM_TYPE - TypePlatformRsv7*/\
143 NULL_LEGACY_GPIO_INITIALIZER,\
144 /* EFI_PLATFORM_TYPE - GalileoGen2*/\
145 GALILEO_GEN2_LEGACY_GPIO_INITIALIZER,\
148 /// Table of BOARD_GPIO_CONTROLLER_CONFIG structures for each board
149 /// supported by this platform package.
150 /// Table indexed with EFI_PLATFORM_TYPE enum value.
152 #define PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION \
153 /* EFI_PLATFORM_TYPE - TypeUnknown*/\
154 NULL_GPIO_CONTROLLER_INITIALIZER,\
155 /* EFI_PLATFORM_TYPE - QuarkEmulation*/\
156 QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER,\
157 /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\
158 CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER,\
159 /* EFI_PLATFORM_TYPE - KipsBay*/\
160 KIPS_BAY_GPIO_CONTROLLER_INITIALIZER,\
161 /* EFI_PLATFORM_TYPE - CrossHill*/\
162 CROSS_HILL_GPIO_CONTROLLER_INITIALIZER,\
163 /* EFI_PLATFORM_TYPE - ClantonHill*/\
164 CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER,\
165 /* EFI_PLATFORM_TYPE - Galileo*/\
166 GALILEO_GPIO_CONTROLLER_INITIALIZER,\
167 /* EFI_PLATFORM_TYPE - TypePlatformRsv7 */\
168 NULL_GPIO_CONTROLLER_INITIALIZER,\
169 /* EFI_PLATFORM_TYPE - GalileoGen2*/\
170 GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER,\