2 Main file for Pci shell Debug1 function.
4 Copyright (c) 2005 - 2017, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>
6 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include "UefiShellDebug1CommandsLib.h"
18 #include <Protocol/PciRootBridgeIo.h>
19 #include <Library/ShellLib.h>
20 #include <IndustryStandard/Pci.h>
21 #include <IndustryStandard/Acpi.h>
25 // Printable strings for Pci class code
28 CHAR16
*BaseClass
; // Pointer to the PCI base class string
29 CHAR16
*SubClass
; // Pointer to the PCI sub class string
30 CHAR16
*PIFClass
; // Pointer to the PCI programming interface string
34 // a structure holding a single entry, which also points to its lower level
37 typedef struct PCI_CLASS_ENTRY_TAG
{
38 UINT8 Code
; // Class, subclass or I/F code
39 CHAR16
*DescText
; // Description string
40 struct PCI_CLASS_ENTRY_TAG
*LowerLevelClass
; // Subclass or I/F if any
44 // Declarations of entries which contain printable strings for class codes
45 // in PCI configuration space
47 PCI_CLASS_ENTRY PCIBlankEntry
[];
48 PCI_CLASS_ENTRY PCISubClass_00
[];
49 PCI_CLASS_ENTRY PCISubClass_01
[];
50 PCI_CLASS_ENTRY PCISubClass_02
[];
51 PCI_CLASS_ENTRY PCISubClass_03
[];
52 PCI_CLASS_ENTRY PCISubClass_04
[];
53 PCI_CLASS_ENTRY PCISubClass_05
[];
54 PCI_CLASS_ENTRY PCISubClass_06
[];
55 PCI_CLASS_ENTRY PCISubClass_07
[];
56 PCI_CLASS_ENTRY PCISubClass_08
[];
57 PCI_CLASS_ENTRY PCISubClass_09
[];
58 PCI_CLASS_ENTRY PCISubClass_0a
[];
59 PCI_CLASS_ENTRY PCISubClass_0b
[];
60 PCI_CLASS_ENTRY PCISubClass_0c
[];
61 PCI_CLASS_ENTRY PCISubClass_0d
[];
62 PCI_CLASS_ENTRY PCISubClass_0e
[];
63 PCI_CLASS_ENTRY PCISubClass_0f
[];
64 PCI_CLASS_ENTRY PCISubClass_10
[];
65 PCI_CLASS_ENTRY PCISubClass_11
[];
66 PCI_CLASS_ENTRY PCISubClass_12
[];
67 PCI_CLASS_ENTRY PCISubClass_13
[];
68 PCI_CLASS_ENTRY PCIPIFClass_0100
[];
69 PCI_CLASS_ENTRY PCIPIFClass_0101
[];
70 PCI_CLASS_ENTRY PCIPIFClass_0105
[];
71 PCI_CLASS_ENTRY PCIPIFClass_0106
[];
72 PCI_CLASS_ENTRY PCIPIFClass_0107
[];
73 PCI_CLASS_ENTRY PCIPIFClass_0108
[];
74 PCI_CLASS_ENTRY PCIPIFClass_0109
[];
75 PCI_CLASS_ENTRY PCIPIFClass_0300
[];
76 PCI_CLASS_ENTRY PCIPIFClass_0604
[];
77 PCI_CLASS_ENTRY PCIPIFClass_0609
[];
78 PCI_CLASS_ENTRY PCIPIFClass_060b
[];
79 PCI_CLASS_ENTRY PCIPIFClass_0700
[];
80 PCI_CLASS_ENTRY PCIPIFClass_0701
[];
81 PCI_CLASS_ENTRY PCIPIFClass_0703
[];
82 PCI_CLASS_ENTRY PCIPIFClass_0800
[];
83 PCI_CLASS_ENTRY PCIPIFClass_0801
[];
84 PCI_CLASS_ENTRY PCIPIFClass_0802
[];
85 PCI_CLASS_ENTRY PCIPIFClass_0803
[];
86 PCI_CLASS_ENTRY PCIPIFClass_0904
[];
87 PCI_CLASS_ENTRY PCIPIFClass_0c00
[];
88 PCI_CLASS_ENTRY PCIPIFClass_0c03
[];
89 PCI_CLASS_ENTRY PCIPIFClass_0c07
[];
90 PCI_CLASS_ENTRY PCIPIFClass_0d01
[];
91 PCI_CLASS_ENTRY PCIPIFClass_0e00
[];
94 // Base class strings entries
96 PCI_CLASS_ENTRY gClassStringList
[] = {
104 L
"Mass Storage Controller",
109 L
"Network Controller",
114 L
"Display Controller",
119 L
"Multimedia Device",
124 L
"Memory Controller",
134 L
"Simple Communications Controllers",
139 L
"Base System Peripherals",
159 L
"Serial Bus Controllers",
164 L
"Wireless Controllers",
169 L
"Intelligent IO Controllers",
174 L
"Satellite Communications Controllers",
179 L
"Encryption/Decryption Controllers",
184 L
"Data Acquisition & Signal Processing Controllers",
189 L
"Processing Accelerators",
194 L
"Non-Essential Instrumentation",
199 L
"Device does not fit in any defined classes",
205 /* null string ends the list */NULL
210 // Subclass strings entries
212 PCI_CLASS_ENTRY PCIBlankEntry
[] = {
221 /* null string ends the list */NULL
225 PCI_CLASS_ENTRY PCISubClass_00
[] = {
228 L
"All devices other than VGA",
233 L
"VGA-compatible devices",
239 /* null string ends the list */NULL
243 PCI_CLASS_ENTRY PCISubClass_01
[] = {
256 L
"Floppy disk controller",
271 L
"ATA controller with ADMA interface",
276 L
"Serial ATA controller",
281 L
"Serial Attached SCSI (SAS) controller ",
286 L
"Non-volatile memory subsystem",
291 L
"Universal Flash Storage (UFS) controller ",
296 L
"Other mass storage controller",
302 /* null string ends the list */NULL
306 PCI_CLASS_ENTRY PCISubClass_02
[] = {
309 L
"Ethernet controller",
314 L
"Token ring controller",
334 L
"WorldFip controller",
339 L
"PICMG 2.14 Multi Computing",
344 L
"InfiniBand controller",
349 L
"Other network controller",
355 /* null string ends the list */NULL
359 PCI_CLASS_ENTRY PCISubClass_03
[] = {
362 L
"VGA/8514 controller",
377 L
"Other display controller",
383 /* null string ends the list */PCIBlankEntry
387 PCI_CLASS_ENTRY PCISubClass_04
[] = {
400 L
"Computer Telephony device",
405 L
"Mixed mode device",
410 L
"Other multimedia device",
416 /* null string ends the list */NULL
420 PCI_CLASS_ENTRY PCISubClass_05
[] = {
423 L
"RAM memory controller",
428 L
"Flash memory controller",
433 L
"Other memory controller",
439 /* null string ends the list */NULL
443 PCI_CLASS_ENTRY PCISubClass_06
[] = {
461 L
"PCI/Micro Channel bridge",
471 L
"PCI/PCMCIA bridge",
491 L
"Semi-transparent PCI-to-PCI bridge",
496 L
"InfiniBand-to-PCI host bridge",
501 L
"Advanced Switching to PCI host bridge",
506 L
"Other bridge type",
512 /* null string ends the list */NULL
516 PCI_CLASS_ENTRY PCISubClass_07
[] = {
519 L
"Serial controller",
529 L
"Multiport serial controller",
539 L
"GPIB (IEEE 488.1/2) controller",
549 L
"Other communication device",
555 /* null string ends the list */NULL
559 PCI_CLASS_ENTRY PCISubClass_08
[] = {
582 L
"Generic PCI Hot-Plug controller",
587 L
"SD Host controller",
597 L
"Root Complex Event Collector",
602 L
"Other system peripheral",
608 /* null string ends the list */NULL
612 PCI_CLASS_ENTRY PCISubClass_09
[] = {
615 L
"Keyboard controller",
630 L
"Scanner controller",
635 L
"Gameport controller",
640 L
"Other input controller",
646 /* null string ends the list */NULL
650 PCI_CLASS_ENTRY PCISubClass_0a
[] = {
653 L
"Generic docking station",
658 L
"Other type of docking station",
664 /* null string ends the list */NULL
668 PCI_CLASS_ENTRY PCISubClass_0b
[] = {
712 /* null string ends the list */NULL
716 PCI_CLASS_ENTRY PCISubClass_0c
[] = {
744 L
"System Management Bus",
759 L
"SERCOS Interface Standard (IEC 61491)",
775 /* null string ends the list */NULL
779 PCI_CLASS_ENTRY PCISubClass_0d
[] = {
782 L
"iRDA compatible controller",
807 L
"Ethernet (802.11a - 5 GHz)",
812 L
"Ethernet (802.11b - 2.4 GHz)",
817 L
"Other type of wireless controller",
823 /* null string ends the list */NULL
827 PCI_CLASS_ENTRY PCISubClass_0e
[] = {
836 /* null string ends the list */NULL
840 PCI_CLASS_ENTRY PCISubClass_0f
[] = {
863 L
"Other satellite communication controller",
869 /* null string ends the list */NULL
873 PCI_CLASS_ENTRY PCISubClass_10
[] = {
876 L
"Network & computing Encrypt/Decrypt",
881 L
"Entertainment Encrypt/Decrypt",
886 L
"Other Encrypt/Decrypt",
892 /* null string ends the list */NULL
896 PCI_CLASS_ENTRY PCISubClass_11
[] = {
904 L
"Performance Counters",
909 L
"Communications synchronization plus time and frequency test/measurement ",
919 L
"Other DAQ & SP controllers",
925 /* null string ends the list */NULL
929 PCI_CLASS_ENTRY PCISubClass_12
[] = {
932 L
"Processing Accelerator",
938 /* null string ends the list */NULL
942 PCI_CLASS_ENTRY PCISubClass_13
[] = {
945 L
"Non-Essential Instrumentation Function",
951 /* null string ends the list */NULL
956 // Programming Interface entries
958 PCI_CLASS_ENTRY PCIPIFClass_0100
[] = {
966 L
"SCSI storage device SOP using PQI",
971 L
"SCSI controller SOP using PQI",
976 L
"SCSI storage device and controller SOP using PQI",
981 L
"SCSI storage device SOP using NVMe",
987 /* null string ends the list */NULL
991 PCI_CLASS_ENTRY PCIPIFClass_0101
[] = {
1019 L
"OM-primary, OM-secondary",
1024 L
"PI-primary, OM-secondary",
1029 L
"OM/PI-primary, OM-secondary",
1039 L
"OM-primary, PI-secondary",
1044 L
"PI-primary, PI-secondary",
1049 L
"OM/PI-primary, PI-secondary",
1059 L
"OM-primary, OM/PI-secondary",
1064 L
"PI-primary, OM/PI-secondary",
1069 L
"OM/PI-primary, OM/PI-secondary",
1079 L
"Master, OM-primary",
1084 L
"Master, PI-primary",
1089 L
"Master, OM/PI-primary",
1094 L
"Master, OM-secondary",
1099 L
"Master, OM-primary, OM-secondary",
1104 L
"Master, PI-primary, OM-secondary",
1109 L
"Master, OM/PI-primary, OM-secondary",
1114 L
"Master, OM-secondary",
1119 L
"Master, OM-primary, PI-secondary",
1124 L
"Master, PI-primary, PI-secondary",
1129 L
"Master, OM/PI-primary, PI-secondary",
1134 L
"Master, OM-secondary",
1139 L
"Master, OM-primary, OM/PI-secondary",
1144 L
"Master, PI-primary, OM/PI-secondary",
1149 L
"Master, OM/PI-primary, OM/PI-secondary",
1155 /* null string ends the list */NULL
1159 PCI_CLASS_ENTRY PCIPIFClass_0105
[] = {
1167 L
"Continuous operation",
1173 /* null string ends the list */NULL
1177 PCI_CLASS_ENTRY PCIPIFClass_0106
[] = {
1190 L
"Serial Storage Bus",
1196 /* null string ends the list */NULL
1200 PCI_CLASS_ENTRY PCIPIFClass_0107
[] = {
1214 /* null string ends the list */NULL
1218 PCI_CLASS_ENTRY PCIPIFClass_0108
[] = {
1237 /* null string ends the list */NULL
1241 PCI_CLASS_ENTRY PCIPIFClass_0109
[] = {
1255 /* null string ends the list */NULL
1259 PCI_CLASS_ENTRY PCIPIFClass_0300
[] = {
1273 /* null string ends the list */NULL
1277 PCI_CLASS_ENTRY PCIPIFClass_0604
[] = {
1285 L
"Subtractive decode",
1291 /* null string ends the list */NULL
1295 PCI_CLASS_ENTRY PCIPIFClass_0609
[] = {
1298 L
"Primary PCI bus side facing the system host processor",
1303 L
"Secondary PCI bus side facing the system host processor",
1309 /* null string ends the list */NULL
1313 PCI_CLASS_ENTRY PCIPIFClass_060b
[] = {
1321 L
"ASI-SIG Defined Portal",
1327 /* null string ends the list */NULL
1331 PCI_CLASS_ENTRY PCIPIFClass_0700
[] = {
1334 L
"Generic XT-compatible",
1339 L
"16450-compatible",
1344 L
"16550-compatible",
1349 L
"16650-compatible",
1354 L
"16750-compatible",
1359 L
"16850-compatible",
1364 L
"16950-compatible",
1370 /* null string ends the list */NULL
1374 PCI_CLASS_ENTRY PCIPIFClass_0701
[] = {
1387 L
"ECP 1.X-compliant",
1397 L
"IEEE 1284 target (not a controller)",
1403 /* null string ends the list */NULL
1407 PCI_CLASS_ENTRY PCIPIFClass_0703
[] = {
1415 L
"Hayes-compatible 16450",
1420 L
"Hayes-compatible 16550",
1425 L
"Hayes-compatible 16650",
1430 L
"Hayes-compatible 16750",
1436 /* null string ends the list */NULL
1440 PCI_CLASS_ENTRY PCIPIFClass_0800
[] = {
1463 L
"IO(x) APIC interrupt controller",
1469 /* null string ends the list */NULL
1473 PCI_CLASS_ENTRY PCIPIFClass_0801
[] = {
1492 /* null string ends the list */NULL
1496 PCI_CLASS_ENTRY PCIPIFClass_0802
[] = {
1515 /* null string ends the list */NULL
1519 PCI_CLASS_ENTRY PCIPIFClass_0803
[] = {
1538 /* null string ends the list */NULL
1542 PCI_CLASS_ENTRY PCIPIFClass_0904
[] = {
1556 /* null string ends the list */NULL
1560 PCI_CLASS_ENTRY PCIPIFClass_0c00
[] = {
1568 L
"Using 1394 OpenHCI spec",
1574 /* null string ends the list */NULL
1578 PCI_CLASS_ENTRY PCIPIFClass_0c03
[] = {
1601 L
"No specific programming interface",
1606 L
"(Not Host Controller)",
1612 /* null string ends the list */NULL
1616 PCI_CLASS_ENTRY PCIPIFClass_0c07
[] = {
1624 L
"Keyboard Controller Style",
1635 /* null string ends the list */NULL
1639 PCI_CLASS_ENTRY PCIPIFClass_0d01
[] = {
1642 L
"Consumer IR controller",
1647 L
"UWB Radio controller",
1653 /* null string ends the list */NULL
1657 PCI_CLASS_ENTRY PCIPIFClass_0e00
[] = {
1660 L
"Message FIFO at offset 40h",
1671 /* null string ends the list */NULL
1677 Generates printable Unicode strings that represent PCI device class,
1678 subclass and programmed I/F based on a value passed to the function.
1680 @param[in] ClassCode Value representing the PCI "Class Code" register read from a
1681 PCI device. The encodings are:
1682 bits 23:16 - Base Class Code
1683 bits 15:8 - Sub-Class Code
1684 bits 7:0 - Programming Interface
1685 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains
1686 printable class strings corresponding to ClassCode. The
1687 caller must not modify the strings that are pointed by
1688 the fields in ClassStrings.
1691 PciGetClassStrings (
1692 IN UINT32 ClassCode
,
1693 IN OUT PCI_CLASS_STRINGS
*ClassStrings
1698 PCI_CLASS_ENTRY
*CurrentClass
;
1701 // Assume no strings found
1703 ClassStrings
->BaseClass
= L
"UNDEFINED";
1704 ClassStrings
->SubClass
= L
"UNDEFINED";
1705 ClassStrings
->PIFClass
= L
"UNDEFINED";
1707 CurrentClass
= gClassStringList
;
1708 Code
= (UINT8
) (ClassCode
>> 16);
1712 // Go through all entries of the base class, until the entry with a matching
1713 // base class code is found. If reaches an entry with a null description
1714 // text, the last entry is met, which means no text for the base class was
1715 // found, so no more action is needed.
1717 while (Code
!= CurrentClass
[Index
].Code
) {
1718 if (NULL
== CurrentClass
[Index
].DescText
) {
1725 // A base class was found. Assign description, and check if this class has
1726 // sub-class defined. If sub-class defined, no more action is needed,
1727 // otherwise, continue to find description for the sub-class code.
1729 ClassStrings
->BaseClass
= CurrentClass
[Index
].DescText
;
1730 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1734 // find Subclass entry
1736 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1737 Code
= (UINT8
) (ClassCode
>> 8);
1741 // Go through all entries of the sub-class, until the entry with a matching
1742 // sub-class code is found. If reaches an entry with a null description
1743 // text, the last entry is met, which means no text for the sub-class was
1744 // found, so no more action is needed.
1746 while (Code
!= CurrentClass
[Index
].Code
) {
1747 if (NULL
== CurrentClass
[Index
].DescText
) {
1754 // A class was found for the sub-class code. Assign description, and check if
1755 // this sub-class has programming interface defined. If no, no more action is
1756 // needed, otherwise, continue to find description for the programming
1759 ClassStrings
->SubClass
= CurrentClass
[Index
].DescText
;
1760 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1764 // Find programming interface entry
1766 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1767 Code
= (UINT8
) ClassCode
;
1771 // Go through all entries of the I/F entries, until the entry with a
1772 // matching I/F code is found. If reaches an entry with a null description
1773 // text, the last entry is met, which means no text was found, so no more
1774 // action is needed.
1776 while (Code
!= CurrentClass
[Index
].Code
) {
1777 if (NULL
== CurrentClass
[Index
].DescText
) {
1784 // A class was found for the I/F code. Assign description, done!
1786 ClassStrings
->PIFClass
= CurrentClass
[Index
].DescText
;
1791 Print strings that represent PCI device class, subclass and programmed I/F.
1793 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI
1794 configuration space.
1795 @param[in] IncludePIF If the printed string should include the programming I/F part
1799 IN UINT8
*ClassCodePtr
,
1800 IN BOOLEAN IncludePIF
1804 PCI_CLASS_STRINGS ClassStrings
;
1807 ClassCode
|= (UINT32
)ClassCodePtr
[0];
1808 ClassCode
|= (UINT32
)(ClassCodePtr
[1] << 8);
1809 ClassCode
|= (UINT32
)(ClassCodePtr
[2] << 16);
1812 // Get name from class code
1814 PciGetClassStrings (ClassCode
, &ClassStrings
);
1818 // Print base class, sub class, and programming inferface name
1820 ShellPrintEx (-1, -1, L
"%s - %s - %s",
1821 ClassStrings
.BaseClass
,
1822 ClassStrings
.SubClass
,
1823 ClassStrings
.PIFClass
1828 // Only print base class and sub class name
1830 ShellPrintEx (-1, -1, L
"%s - %s",
1831 ClassStrings
.BaseClass
,
1832 ClassStrings
.SubClass
1838 This function finds out the protocol which is in charge of the given
1839 segment, and its bus range covers the current bus number. It lookes
1840 each instances of RootBridgeIoProtocol handle, until the one meets the
1843 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1844 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1845 @param[in] Segment Segment number of device we are dealing with.
1846 @param[in] Bus Bus number of device we are dealing with.
1847 @param[out] IoDev Handle used to access configuration space of PCI device.
1849 @retval EFI_SUCCESS The command completed successfully.
1850 @retval EFI_INVALID_PARAMETER Invalid parameter.
1854 PciFindProtocolInterface (
1855 IN EFI_HANDLE
*HandleBuf
,
1856 IN UINTN HandleCount
,
1859 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
1863 This function gets the protocol interface from the given handle, and
1864 obtains its address space descriptors.
1866 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
1867 @param[out] IoDev Handle used to access configuration space of PCI device.
1868 @param[out] Descriptors Points to the address space descriptors.
1870 @retval EFI_SUCCESS The command completed successfully
1873 PciGetProtocolAndResource (
1874 IN EFI_HANDLE Handle
,
1875 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
1876 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
1880 This function get the next bus range of given address space descriptors.
1881 It also moves the pointer backward a node, to get prepared to be called
1884 @param[in, out] Descriptors Points to current position of a serial of address space
1886 @param[out] MinBus The lower range of bus number.
1887 @param[out] MaxBus The upper range of bus number.
1888 @param[out] IsEnd Meet end of the serial of descriptors.
1890 @retval EFI_SUCCESS The command completed successfully.
1893 PciGetNextBusRange (
1894 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
1901 Explain the data in PCI configuration space. The part which is common for
1902 PCI device and bridge is interpreted in this function. It calls other
1903 functions to interpret data unique for device or bridge.
1905 @param[in] ConfigSpace Data in PCI configuration space.
1906 @param[in] Address Address used to access configuration space of this PCI device.
1907 @param[in] IoDev Handle used to access configuration space of PCI device.
1911 IN PCI_CONFIG_SPACE
*ConfigSpace
,
1913 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1917 Explain the device specific part of data in PCI configuration space.
1919 @param[in] Device Data in PCI configuration space.
1920 @param[in] Address Address used to access configuration space of this PCI device.
1921 @param[in] IoDev Handle used to access configuration space of PCI device.
1923 @retval EFI_SUCCESS The command completed successfully.
1926 PciExplainDeviceData (
1927 IN PCI_DEVICE_HEADER_TYPE_REGION
*Device
,
1929 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1933 Explain the bridge specific part of data in PCI configuration space.
1935 @param[in] Bridge Bridge specific data region in PCI configuration space.
1936 @param[in] Address Address used to access configuration space of this PCI device.
1937 @param[in] IoDev Handle used to access configuration space of PCI device.
1939 @retval EFI_SUCCESS The command completed successfully.
1942 PciExplainBridgeData (
1943 IN PCI_BRIDGE_CONTROL_REGISTER
*Bridge
,
1945 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1949 Explain the Base Address Register(Bar) in PCI configuration space.
1951 @param[in] Bar Points to the Base Address Register intended to interpret.
1952 @param[in] Command Points to the register Command.
1953 @param[in] Address Address used to access configuration space of this PCI device.
1954 @param[in] IoDev Handle used to access configuration space of PCI device.
1955 @param[in, out] Index The Index.
1957 @retval EFI_SUCCESS The command completed successfully.
1964 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1969 Explain the cardbus specific part of data in PCI configuration space.
1971 @param[in] CardBus CardBus specific region of PCI configuration space.
1972 @param[in] Address Address used to access configuration space of this PCI device.
1973 @param[in] IoDev Handle used to access configuration space of PCI device.
1975 @retval EFI_SUCCESS The command completed successfully.
1978 PciExplainCardBusData (
1979 IN PCI_CARDBUS_CONTROL_REGISTER
*CardBus
,
1981 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1985 Explain each meaningful bit of register Status. The definition of Status is
1986 slightly different depending on the PCI header type.
1988 @param[in] Status Points to the content of register Status.
1989 @param[in] MainStatus Indicates if this register is main status(not secondary
1991 @param[in] HeaderType Header type of this PCI device.
1993 @retval EFI_SUCCESS The command completed successfully.
1998 IN BOOLEAN MainStatus
,
1999 IN PCI_HEADER_TYPE HeaderType
2003 Explain each meaningful bit of register Command.
2005 @param[in] Command Points to the content of register Command.
2007 @retval EFI_SUCCESS The command completed successfully.
2015 Explain each meaningful bit of register Bridge Control.
2017 @param[in] BridgeControl Points to the content of register Bridge Control.
2018 @param[in] HeaderType The headertype.
2020 @retval EFI_SUCCESS The command completed successfully.
2023 PciExplainBridgeControl (
2024 IN UINT16
*BridgeControl
,
2025 IN PCI_HEADER_TYPE HeaderType
2029 Locate capability register block per capability ID.
2031 @param[in] ConfigSpace Data in PCI configuration space.
2032 @param[in] CapabilityId The capability ID.
2034 @return The offset of the register block per capability ID.
2037 LocatePciCapability (
2038 IN PCI_CONFIG_SPACE
*ConfigSpace
,
2039 IN UINT8 CapabilityId
2043 Display Pcie device structure.
2045 @param[in] PciExpressCap PCI Express capability buffer.
2046 @param[in] ExtendedConfigSpace PCI Express extended configuration space.
2047 @param[in] ExtendedCapability PCI Express extended capability ID to explain.
2050 PciExplainPciExpress (
2051 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
,
2052 IN UINT8
*ExtendedConfigSpace
,
2053 IN CONST UINT16 ExtendedCapability
2057 Print out information of the capability information.
2059 @param[in] PciExpressCap The pointer to the structure about the device.
2061 @retval EFI_SUCCESS The operation was successful.
2065 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2069 Print out information of the device capability information.
2071 @param[in] PciExpressCap The pointer to the structure about the device.
2073 @retval EFI_SUCCESS The operation was successful.
2076 ExplainPcieDeviceCap (
2077 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2081 Print out information of the device control information.
2083 @param[in] PciExpressCap The pointer to the structure about the device.
2085 @retval EFI_SUCCESS The operation was successful.
2088 ExplainPcieDeviceControl (
2089 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2093 Print out information of the device status information.
2095 @param[in] PciExpressCap The pointer to the structure about the device.
2097 @retval EFI_SUCCESS The operation was successful.
2100 ExplainPcieDeviceStatus (
2101 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2105 Print out information of the device link information.
2107 @param[in] PciExpressCap The pointer to the structure about the device.
2109 @retval EFI_SUCCESS The operation was successful.
2112 ExplainPcieLinkCap (
2113 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2117 Print out information of the device link control information.
2119 @param[in] PciExpressCap The pointer to the structure about the device.
2121 @retval EFI_SUCCESS The operation was successful.
2124 ExplainPcieLinkControl (
2125 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2129 Print out information of the device link status information.
2131 @param[in] PciExpressCap The pointer to the structure about the device.
2133 @retval EFI_SUCCESS The operation was successful.
2136 ExplainPcieLinkStatus (
2137 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2141 Print out information of the device slot information.
2143 @param[in] PciExpressCap The pointer to the structure about the device.
2145 @retval EFI_SUCCESS The operation was successful.
2148 ExplainPcieSlotCap (
2149 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2153 Print out information of the device slot control information.
2155 @param[in] PciExpressCap The pointer to the structure about the device.
2157 @retval EFI_SUCCESS The operation was successful.
2160 ExplainPcieSlotControl (
2161 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2165 Print out information of the device slot status information.
2167 @param[in] PciExpressCap The pointer to the structure about the device.
2169 @retval EFI_SUCCESS The operation was successful.
2172 ExplainPcieSlotStatus (
2173 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2177 Print out information of the device root information.
2179 @param[in] PciExpressCap The pointer to the structure about the device.
2181 @retval EFI_SUCCESS The operation was successful.
2184 ExplainPcieRootControl (
2185 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2189 Print out information of the device root capability information.
2191 @param[in] PciExpressCap The pointer to the structure about the device.
2193 @retval EFI_SUCCESS The operation was successful.
2196 ExplainPcieRootCap (
2197 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2201 Print out information of the device root status information.
2203 @param[in] PciExpressCap The pointer to the structure about the device.
2205 @retval EFI_SUCCESS The operation was successful.
2208 ExplainPcieRootStatus (
2209 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2212 typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION
) (IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
);
2218 } PCIE_CAPREG_FIELD_WIDTH
;
2221 PcieExplainTypeCommon
,
2222 PcieExplainTypeDevice
,
2223 PcieExplainTypeLink
,
2224 PcieExplainTypeSlot
,
2225 PcieExplainTypeRoot
,
2227 } PCIE_EXPLAIN_TYPE
;
2233 PCIE_CAPREG_FIELD_WIDTH Width
;
2234 PCIE_EXPLAIN_FUNCTION Func
;
2235 PCIE_EXPLAIN_TYPE Type
;
2236 } PCIE_EXPLAIN_STRUCT
;
2238 PCIE_EXPLAIN_STRUCT PcieExplainList
[] = {
2240 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID
),
2244 PcieExplainTypeCommon
2247 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR
),
2251 PcieExplainTypeCommon
2254 STRING_TOKEN (STR_PCIEX_CAP_REGISTER
),
2258 PcieExplainTypeCommon
2261 STRING_TOKEN (STR_PCIEX_DEVICE_CAP
),
2264 ExplainPcieDeviceCap
,
2265 PcieExplainTypeDevice
2268 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL
),
2271 ExplainPcieDeviceControl
,
2272 PcieExplainTypeDevice
2275 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS
),
2278 ExplainPcieDeviceStatus
,
2279 PcieExplainTypeDevice
2282 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES
),
2289 STRING_TOKEN (STR_PCIEX_LINK_CONTROL
),
2292 ExplainPcieLinkControl
,
2296 STRING_TOKEN (STR_PCIEX_LINK_STATUS
),
2299 ExplainPcieLinkStatus
,
2303 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES
),
2310 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL
),
2313 ExplainPcieSlotControl
,
2317 STRING_TOKEN (STR_PCIEX_SLOT_STATUS
),
2320 ExplainPcieSlotStatus
,
2324 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL
),
2327 ExplainPcieRootControl
,
2331 STRING_TOKEN (STR_PCIEX_RSVDP
),
2338 STRING_TOKEN (STR_PCIEX_ROOT_STATUS
),
2341 ExplainPcieRootStatus
,
2347 (PCIE_CAPREG_FIELD_WIDTH
)0,
2356 PCI_CONFIG_SPACE
*mConfigSpace
= NULL
;
2357 STATIC CONST SHELL_PARAM_ITEM ParamList
[] = {
2360 {L
"-ec", TypeValue
},
2364 CHAR16
*DevicePortTypeTable
[] = {
2365 L
"PCI Express Endpoint",
2366 L
"Legacy PCI Express Endpoint",
2369 L
"Root Port of PCI Express Root Complex",
2370 L
"Upstream Port of PCI Express Switch",
2371 L
"Downstream Port of PCI Express Switch",
2372 L
"PCI Express to PCI/PCI-X Bridge",
2373 L
"PCI/PCI-X to PCI Express Bridge",
2374 L
"Root Complex Integrated Endpoint",
2375 L
"Root Complex Event Collector"
2378 CHAR16
*L0sLatencyStrTable
[] = {
2380 L
"64ns to less than 128ns",
2381 L
"128ns to less than 256ns",
2382 L
"256ns to less than 512ns",
2383 L
"512ns to less than 1us",
2384 L
"1us to less than 2us",
2389 CHAR16
*L1LatencyStrTable
[] = {
2391 L
"1us to less than 2us",
2392 L
"2us to less than 4us",
2393 L
"4us to less than 8us",
2394 L
"8us to less than 16us",
2395 L
"16us to less than 32us",
2400 CHAR16
*ASPMCtrlStrTable
[] = {
2402 L
"L0s Entry Enabled",
2403 L
"L1 Entry Enabled",
2404 L
"L0s and L1 Entry Enabled"
2407 CHAR16
*SlotPwrLmtScaleTable
[] = {
2414 CHAR16
*IndicatorTable
[] = {
2423 Function for 'pci' command.
2425 @param[in] ImageHandle Handle to the Image (NULL if Internal).
2426 @param[in] SystemTable Pointer to the System Table (NULL if Internal).
2430 ShellCommandRunPci (
2431 IN EFI_HANDLE ImageHandle
,
2432 IN EFI_SYSTEM_TABLE
*SystemTable
2440 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
;
2442 PCI_DEVICE_INDEPENDENT_REGION PciHeader
;
2443 PCI_CONFIG_SPACE ConfigSpace
;
2447 BOOLEAN ExplainData
;
2451 UINTN HandleBufSize
;
2452 EFI_HANDLE
*HandleBuf
;
2454 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2458 LIST_ENTRY
*Package
;
2459 CHAR16
*ProblemParam
;
2460 SHELL_STATUS ShellStatus
;
2463 UINT16 ExtendedCapability
;
2464 UINT8 PcieCapabilityPtr
;
2465 UINT8
*ExtendedConfigSpace
;
2466 UINTN ExtendedConfigSize
;
2468 ShellStatus
= SHELL_SUCCESS
;
2469 Status
= EFI_SUCCESS
;
2476 // initialize the shell lib (we must be in non-auto-init...)
2478 Status
= ShellInitialize();
2479 ASSERT_EFI_ERROR(Status
);
2481 Status
= CommandInit();
2482 ASSERT_EFI_ERROR(Status
);
2485 // parse the command line
2487 Status
= ShellCommandLineParse (ParamList
, &Package
, &ProblemParam
, TRUE
);
2488 if (EFI_ERROR(Status
)) {
2489 if (Status
== EFI_VOLUME_CORRUPTED
&& ProblemParam
!= NULL
) {
2490 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, L
"pci", ProblemParam
);
2491 FreePool(ProblemParam
);
2492 ShellStatus
= SHELL_INVALID_PARAMETER
;
2498 if (ShellCommandLineGetCount(Package
) == 2) {
2499 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_FEW
), gShellDebug1HiiHandle
, L
"pci");
2500 ShellStatus
= SHELL_INVALID_PARAMETER
;
2504 if (ShellCommandLineGetCount(Package
) > 4) {
2505 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_MANY
), gShellDebug1HiiHandle
, L
"pci");
2506 ShellStatus
= SHELL_INVALID_PARAMETER
;
2509 if (ShellCommandLineGetFlag(Package
, L
"-ec") && ShellCommandLineGetValue(Package
, L
"-ec") == NULL
) {
2510 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_NO_VALUE
), gShellDebug1HiiHandle
, L
"pci", L
"-ec");
2511 ShellStatus
= SHELL_INVALID_PARAMETER
;
2514 if (ShellCommandLineGetFlag(Package
, L
"-s") && ShellCommandLineGetValue(Package
, L
"-s") == NULL
) {
2515 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_NO_VALUE
), gShellDebug1HiiHandle
, L
"pci", L
"-s");
2516 ShellStatus
= SHELL_INVALID_PARAMETER
;
2520 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and
2521 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough
2522 // space for handles and call it again.
2524 HandleBufSize
= sizeof (EFI_HANDLE
);
2525 HandleBuf
= (EFI_HANDLE
*) AllocateZeroPool (HandleBufSize
);
2526 if (HandleBuf
== NULL
) {
2527 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
, L
"pci");
2528 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2532 Status
= gBS
->LocateHandle (
2534 &gEfiPciRootBridgeIoProtocolGuid
,
2540 if (Status
== EFI_BUFFER_TOO_SMALL
) {
2541 HandleBuf
= ReallocatePool (sizeof (EFI_HANDLE
), HandleBufSize
, HandleBuf
);
2542 if (HandleBuf
== NULL
) {
2543 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
, L
"pci");
2544 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2548 Status
= gBS
->LocateHandle (
2550 &gEfiPciRootBridgeIoProtocolGuid
,
2557 if (EFI_ERROR (Status
)) {
2558 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PCIRBIO_NF
), gShellDebug1HiiHandle
, L
"pci");
2559 ShellStatus
= SHELL_NOT_FOUND
;
2563 HandleCount
= HandleBufSize
/ sizeof (EFI_HANDLE
);
2565 // Argument Count == 1(no other argument): enumerate all pci functions
2567 if (ShellCommandLineGetCount(Package
) == 1) {
2568 gST
->ConOut
->QueryMode (
2570 gST
->ConOut
->Mode
->Mode
,
2577 if ((ScreenSize
& 1) == 1) {
2584 // For each handle, which decides a segment and a bus number range,
2585 // enumerate all devices on it.
2587 for (Index
= 0; Index
< HandleCount
; Index
++) {
2588 Status
= PciGetProtocolAndResource (
2593 if (EFI_ERROR (Status
)) {
2594 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR
), gShellDebug1HiiHandle
, L
"pci");
2595 ShellStatus
= SHELL_NOT_FOUND
;
2599 // No document say it's impossible for a RootBridgeIo protocol handle
2600 // to have more than one address space descriptors, so find out every
2601 // bus range and for each of them do device enumeration.
2604 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2606 if (EFI_ERROR (Status
)) {
2607 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR
), gShellDebug1HiiHandle
, L
"pci");
2608 ShellStatus
= SHELL_NOT_FOUND
;
2616 for (Bus
= MinBus
; Bus
<= MaxBus
; Bus
++) {
2618 // For each devices, enumerate all functions it contains
2620 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2622 // For each function, read its configuration space and print summary
2624 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2625 if (ShellGetExecutionBreakFlag ()) {
2626 ShellStatus
= SHELL_ABORTED
;
2629 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2639 // If VendorId = 0xffff, there does not exist a device at this
2640 // location. For each device, if there is any function on it,
2641 // there must be 1 function at Function 0. So if Func = 0, there
2642 // will be no more functions in the same device, so we can break
2643 // loop to deal with the next device.
2645 if (PciHeader
.VendorId
== 0xffff && Func
== 0) {
2649 if (PciHeader
.VendorId
!= 0xffff) {
2652 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_TITLE
), gShellDebug1HiiHandle
);
2660 sizeof (PciHeader
) / sizeof (UINT32
),
2665 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P1
), gShellDebug1HiiHandle
,
2666 IoDev
->SegmentNumber
,
2672 PciPrintClassCode (PciHeader
.ClassCode
, FALSE
);
2674 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P2
), gShellDebug1HiiHandle
,
2677 PciHeader
.ClassCode
[0]
2681 if (ScreenCount
>= ScreenSize
&& ScreenSize
!= 0) {
2683 // If ScreenSize == 0 we have the console redirected so don't
2689 // If this is not a multi-function device, we can leave the loop
2690 // to deal with the next device.
2692 if (Func
== 0 && ((PciHeader
.HeaderType
& HEADER_TYPE_MULTI_FUNCTION
) == 0x00)) {
2700 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
2701 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
2702 // devices on all bus, we can leave loop.
2704 if (Descriptors
== NULL
) {
2710 Status
= EFI_SUCCESS
;
2714 ExplainData
= FALSE
;
2719 ExtendedCapability
= 0xFFFF;
2720 if (ShellCommandLineGetFlag(Package
, L
"-i")) {
2724 Temp
= ShellCommandLineGetValue(Package
, L
"-s");
2727 // Input converted to hexadecimal number.
2729 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2730 Segment
= (UINT16
) RetVal
;
2732 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2733 ShellStatus
= SHELL_INVALID_PARAMETER
;
2739 // The first Argument(except "-i") is assumed to be Bus number, second
2740 // to be Device number, and third to be Func number.
2742 Temp
= ShellCommandLineGetRawValue(Package
, 1);
2745 // Input converted to hexadecimal number.
2747 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2748 Bus
= (UINT16
) RetVal
;
2750 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2751 ShellStatus
= SHELL_INVALID_PARAMETER
;
2755 if (Bus
> PCI_MAX_BUS
) {
2756 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2757 ShellStatus
= SHELL_INVALID_PARAMETER
;
2761 Temp
= ShellCommandLineGetRawValue(Package
, 2);
2764 // Input converted to hexadecimal number.
2766 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2767 Device
= (UINT16
) RetVal
;
2769 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2770 ShellStatus
= SHELL_INVALID_PARAMETER
;
2774 if (Device
> PCI_MAX_DEVICE
){
2775 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2776 ShellStatus
= SHELL_INVALID_PARAMETER
;
2781 Temp
= ShellCommandLineGetRawValue(Package
, 3);
2784 // Input converted to hexadecimal number.
2786 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2787 Func
= (UINT16
) RetVal
;
2789 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2790 ShellStatus
= SHELL_INVALID_PARAMETER
;
2794 if (Func
> PCI_MAX_FUNC
){
2795 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2796 ShellStatus
= SHELL_INVALID_PARAMETER
;
2801 Temp
= ShellCommandLineGetValue (Package
, L
"-ec");
2804 // Input converted to hexadecimal number.
2806 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2807 ExtendedCapability
= (UINT16
) RetVal
;
2809 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2810 ShellStatus
= SHELL_INVALID_PARAMETER
;
2816 // Find the protocol interface who's in charge of current segment, and its
2817 // bus range covers the current bus
2819 Status
= PciFindProtocolInterface (
2827 if (EFI_ERROR (Status
)) {
2829 -1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_FIND
), gShellDebug1HiiHandle
, L
"pci",
2833 ShellStatus
= SHELL_NOT_FOUND
;
2837 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2838 Status
= IoDev
->Pci
.Read (
2842 sizeof (ConfigSpace
),
2846 if (EFI_ERROR (Status
)) {
2847 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_CFG
), gShellDebug1HiiHandle
, L
"pci");
2848 ShellStatus
= SHELL_ACCESS_DENIED
;
2852 mConfigSpace
= &ConfigSpace
;
2857 STRING_TOKEN (STR_PCI_INFO
),
2858 gShellDebug1HiiHandle
,
2870 // Dump standard header of configuration space
2872 SizeOfHeader
= sizeof (ConfigSpace
.Common
) + sizeof (ConfigSpace
.NonCommon
);
2874 DumpHex (2, 0, SizeOfHeader
, &ConfigSpace
);
2875 ShellPrintEx(-1,-1, L
"\r\n");
2878 // Dump device dependent Part of configuration space
2883 sizeof (ConfigSpace
) - SizeOfHeader
,
2887 ExtendedConfigSpace
= NULL
;
2888 ExtendedConfigSize
= 0;
2889 PcieCapabilityPtr
= LocatePciCapability (&ConfigSpace
, EFI_PCI_CAPABILITY_ID_PCIEXP
);
2890 if (PcieCapabilityPtr
!= 0) {
2891 ExtendedConfigSize
= 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET
;
2892 ExtendedConfigSpace
= AllocatePool (ExtendedConfigSize
);
2893 if (ExtendedConfigSpace
!= NULL
) {
2894 Status
= IoDev
->Pci
.Read (
2897 EFI_PCI_ADDRESS (Bus
, Device
, Func
, EFI_PCIE_CAPABILITY_BASE_OFFSET
),
2898 ExtendedConfigSize
/ sizeof (UINT32
),
2901 if (EFI_ERROR (Status
)) {
2902 SHELL_FREE_NON_NULL (ExtendedConfigSpace
);
2907 if ((ExtendedConfigSpace
!= NULL
) && !ShellGetExecutionBreakFlag ()) {
2909 // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)
2911 ShellPrintEx (-1, -1, L
"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");
2915 EFI_PCIE_CAPABILITY_BASE_OFFSET
,
2922 // If "-i" appears in command line, interpret data in configuration space
2925 PciExplainPci (&ConfigSpace
, Address
, IoDev
);
2926 if ((ExtendedConfigSpace
!= NULL
) && !ShellGetExecutionBreakFlag ()) {
2927 PciExplainPciExpress (
2928 (PCI_CAPABILITY_PCIEXP
*) ((UINT8
*) &ConfigSpace
+ PcieCapabilityPtr
),
2929 ExtendedConfigSpace
,
2936 if (HandleBuf
!= NULL
) {
2937 FreePool (HandleBuf
);
2939 if (Package
!= NULL
) {
2940 ShellCommandLineFreeVarList (Package
);
2942 mConfigSpace
= NULL
;
2947 This function finds out the protocol which is in charge of the given
2948 segment, and its bus range covers the current bus number. It lookes
2949 each instances of RootBridgeIoProtocol handle, until the one meets the
2952 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2953 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2954 @param[in] Segment Segment number of device we are dealing with.
2955 @param[in] Bus Bus number of device we are dealing with.
2956 @param[out] IoDev Handle used to access configuration space of PCI device.
2958 @retval EFI_SUCCESS The command completed successfully.
2959 @retval EFI_INVALID_PARAMETER Invalid parameter.
2963 PciFindProtocolInterface (
2964 IN EFI_HANDLE
*HandleBuf
,
2965 IN UINTN HandleCount
,
2968 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
2973 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2979 // Go through all handles, until the one meets the criteria is found
2981 for (Index
= 0; Index
< HandleCount
; Index
++) {
2982 Status
= PciGetProtocolAndResource (HandleBuf
[Index
], IoDev
, &Descriptors
);
2983 if (EFI_ERROR (Status
)) {
2987 // When Descriptors == NULL, the Configuration() is not implemented,
2988 // so we only check the Segment number
2990 if (Descriptors
== NULL
&& Segment
== (*IoDev
)->SegmentNumber
) {
2994 if ((*IoDev
)->SegmentNumber
!= Segment
) {
2999 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
3000 if (EFI_ERROR (Status
)) {
3008 if (MinBus
<= Bus
&& MaxBus
>= Bus
) {
3014 return EFI_NOT_FOUND
;
3018 This function gets the protocol interface from the given handle, and
3019 obtains its address space descriptors.
3021 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
3022 @param[out] IoDev Handle used to access configuration space of PCI device.
3023 @param[out] Descriptors Points to the address space descriptors.
3025 @retval EFI_SUCCESS The command completed successfully
3028 PciGetProtocolAndResource (
3029 IN EFI_HANDLE Handle
,
3030 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
3031 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
3037 // Get inferface from protocol
3039 Status
= gBS
->HandleProtocol (
3041 &gEfiPciRootBridgeIoProtocolGuid
,
3045 if (EFI_ERROR (Status
)) {
3049 // Call Configuration() to get address space descriptors
3051 Status
= (*IoDev
)->Configuration (*IoDev
, (VOID
**)Descriptors
);
3052 if (Status
== EFI_UNSUPPORTED
) {
3053 *Descriptors
= NULL
;
3062 This function get the next bus range of given address space descriptors.
3063 It also moves the pointer backward a node, to get prepared to be called
3066 @param[in, out] Descriptors Points to current position of a serial of address space
3068 @param[out] MinBus The lower range of bus number.
3069 @param[out] MaxBus The upper range of bus number.
3070 @param[out] IsEnd Meet end of the serial of descriptors.
3072 @retval EFI_SUCCESS The command completed successfully.
3075 PciGetNextBusRange (
3076 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
3085 // When *Descriptors is NULL, Configuration() is not implemented, so assume
3086 // range is 0~PCI_MAX_BUS
3088 if ((*Descriptors
) == NULL
) {
3090 *MaxBus
= PCI_MAX_BUS
;
3094 // *Descriptors points to one or more address space descriptors, which
3095 // ends with a end tagged descriptor. Examine each of the descriptors,
3096 // if a bus typed one is found and its bus range covers bus, this handle
3097 // is the handle we are looking for.
3100 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
3101 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
3102 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
3103 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
3105 return (EFI_SUCCESS
);
3111 if ((*Descriptors
)->Desc
== ACPI_END_TAG_DESCRIPTOR
) {
3119 Explain the data in PCI configuration space. The part which is common for
3120 PCI device and bridge is interpreted in this function. It calls other
3121 functions to interpret data unique for device or bridge.
3123 @param[in] ConfigSpace Data in PCI configuration space.
3124 @param[in] Address Address used to access configuration space of this PCI device.
3125 @param[in] IoDev Handle used to access configuration space of PCI device.
3129 IN PCI_CONFIG_SPACE
*ConfigSpace
,
3131 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3134 PCI_DEVICE_INDEPENDENT_REGION
*Common
;
3135 PCI_HEADER_TYPE HeaderType
;
3137 Common
= &(ConfigSpace
->Common
);
3139 ShellPrintEx (-1, -1, L
"\r\n");
3142 // Print Vendor Id and Device Id
3144 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_VID_DID
), gShellDebug1HiiHandle
,
3145 INDEX_OF (&(Common
->VendorId
)),
3147 INDEX_OF (&(Common
->DeviceId
)),
3152 // Print register Command
3154 PciExplainCommand (&(Common
->Command
));
3157 // Print register Status
3159 PciExplainStatus (&(Common
->Status
), TRUE
, PciUndefined
);
3162 // Print register Revision ID
3164 ShellPrintEx(-1, -1, L
"\r\n");
3165 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_RID
), gShellDebug1HiiHandle
,
3166 INDEX_OF (&(Common
->RevisionID
)),
3171 // Print register BIST
3173 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_BIST
), gShellDebug1HiiHandle
, INDEX_OF (&(Common
->BIST
)));
3174 if ((Common
->BIST
& BIT7
) != 0) {
3175 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP
), gShellDebug1HiiHandle
, 0x0f & Common
->BIST
);
3177 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP_NO
), gShellDebug1HiiHandle
);
3180 // Print register Cache Line Size
3182 ShellPrintHiiEx(-1, -1, NULL
,
3183 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE
),
3184 gShellDebug1HiiHandle
,
3185 INDEX_OF (&(Common
->CacheLineSize
)),
3186 Common
->CacheLineSize
3190 // Print register Latency Timer
3192 ShellPrintHiiEx(-1, -1, NULL
,
3193 STRING_TOKEN (STR_PCI2_LATENCY_TIMER
),
3194 gShellDebug1HiiHandle
,
3195 INDEX_OF (&(Common
->LatencyTimer
)),
3196 Common
->LatencyTimer
3200 // Print register Header Type
3202 ShellPrintHiiEx(-1, -1, NULL
,
3203 STRING_TOKEN (STR_PCI2_HEADER_TYPE
),
3204 gShellDebug1HiiHandle
,
3205 INDEX_OF (&(Common
->HeaderType
)),
3209 if ((Common
->HeaderType
& BIT7
) != 0) {
3210 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION
), gShellDebug1HiiHandle
);
3213 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION
), gShellDebug1HiiHandle
);
3216 HeaderType
= (PCI_HEADER_TYPE
)(UINT8
) (Common
->HeaderType
& 0x7f);
3217 switch (HeaderType
) {
3219 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_PCI_DEVICE
), gShellDebug1HiiHandle
);
3223 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_P2P_BRIDGE
), gShellDebug1HiiHandle
);
3226 case PciCardBusBridge
:
3227 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE
), gShellDebug1HiiHandle
);
3231 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED
), gShellDebug1HiiHandle
);
3232 HeaderType
= PciUndefined
;
3236 // Print register Class Code
3238 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CLASS
), gShellDebug1HiiHandle
);
3239 PciPrintClassCode ((UINT8
*) Common
->ClassCode
, TRUE
);
3240 ShellPrintEx (-1, -1, L
"\r\n");
3244 Explain the device specific part of data in PCI configuration space.
3246 @param[in] Device Data in PCI configuration space.
3247 @param[in] Address Address used to access configuration space of this PCI device.
3248 @param[in] IoDev Handle used to access configuration space of PCI device.
3250 @retval EFI_SUCCESS The command completed successfully.
3253 PciExplainDeviceData (
3254 IN PCI_DEVICE_HEADER_TYPE_REGION
*Device
,
3256 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3265 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not
3266 // exist. If these no Bar for this function, print "none", otherwise
3267 // list detail information about this Bar.
3269 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDR
), gShellDebug1HiiHandle
, INDEX_OF (Device
->Bar
));
3272 BarCount
= sizeof (Device
->Bar
) / sizeof (Device
->Bar
[0]);
3273 for (Index
= 0; Index
< BarCount
; Index
++) {
3274 if (Device
->Bar
[Index
] == 0) {
3280 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE
), gShellDebug1HiiHandle
);
3281 ShellPrintEx (-1, -1, L
" --------------------------------------------------------------------------");
3284 Status
= PciExplainBar (
3285 &(Device
->Bar
[Index
]),
3286 &(mConfigSpace
->Common
.Command
),
3292 if (EFI_ERROR (Status
)) {
3298 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
3301 ShellPrintEx (-1, -1, L
"\r\n --------------------------------------------------------------------------");
3305 // Print register Expansion ROM Base Address
3307 if ((Device
->ExpansionRomBar
& BIT0
) == 0) {
3308 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED
), gShellDebug1HiiHandle
, INDEX_OF (&(Device
->ExpansionRomBar
)));
3311 ShellPrintHiiEx(-1, -1, NULL
,
3312 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE
),
3313 gShellDebug1HiiHandle
,
3314 INDEX_OF (&(Device
->ExpansionRomBar
)),
3315 Device
->ExpansionRomBar
3319 // Print register Cardbus CIS ptr
3321 ShellPrintHiiEx(-1, -1, NULL
,
3322 STRING_TOKEN (STR_PCI2_CARDBUS_CIS
),
3323 gShellDebug1HiiHandle
,
3324 INDEX_OF (&(Device
->CISPtr
)),
3329 // Print register Sub-vendor ID and subsystem ID
3331 ShellPrintHiiEx(-1, -1, NULL
,
3332 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID
),
3333 gShellDebug1HiiHandle
,
3334 INDEX_OF (&(Device
->SubsystemVendorID
)),
3335 Device
->SubsystemVendorID
3338 ShellPrintHiiEx(-1, -1, NULL
,
3339 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID
),
3340 gShellDebug1HiiHandle
,
3341 INDEX_OF (&(Device
->SubsystemID
)),
3346 // Print register Capabilities Ptr
3348 ShellPrintHiiEx(-1, -1, NULL
,
3349 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR
),
3350 gShellDebug1HiiHandle
,
3351 INDEX_OF (&(Device
->CapabilityPtr
)),
3352 Device
->CapabilityPtr
3356 // Print register Interrupt Line and interrupt pin
3358 ShellPrintHiiEx(-1, -1, NULL
,
3359 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE
),
3360 gShellDebug1HiiHandle
,
3361 INDEX_OF (&(Device
->InterruptLine
)),
3362 Device
->InterruptLine
3365 ShellPrintHiiEx(-1, -1, NULL
,
3366 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3367 gShellDebug1HiiHandle
,
3368 INDEX_OF (&(Device
->InterruptPin
)),
3369 Device
->InterruptPin
3373 // Print register Min_Gnt and Max_Lat
3375 ShellPrintHiiEx(-1, -1, NULL
,
3376 STRING_TOKEN (STR_PCI2_MIN_GNT
),
3377 gShellDebug1HiiHandle
,
3378 INDEX_OF (&(Device
->MinGnt
)),
3382 ShellPrintHiiEx(-1, -1, NULL
,
3383 STRING_TOKEN (STR_PCI2_MAX_LAT
),
3384 gShellDebug1HiiHandle
,
3385 INDEX_OF (&(Device
->MaxLat
)),
3393 Explain the bridge specific part of data in PCI configuration space.
3395 @param[in] Bridge Bridge specific data region in PCI configuration space.
3396 @param[in] Address Address used to access configuration space of this PCI device.
3397 @param[in] IoDev Handle used to access configuration space of PCI device.
3399 @retval EFI_SUCCESS The command completed successfully.
3402 PciExplainBridgeData (
3403 IN PCI_BRIDGE_CONTROL_REGISTER
*Bridge
,
3405 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3415 // Print Base Address Registers. When Bar = 0, this Bar does not
3416 // exist. If these no Bar for this function, print "none", otherwise
3417 // list detail information about this Bar.
3419 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDRESS
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->Bar
)));
3422 BarCount
= sizeof (Bridge
->Bar
) / sizeof (Bridge
->Bar
[0]);
3424 for (Index
= 0; Index
< BarCount
; Index
++) {
3425 if (Bridge
->Bar
[Index
] == 0) {
3431 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE_2
), gShellDebug1HiiHandle
);
3432 ShellPrintEx (-1, -1, L
" --------------------------------------------------------------------------");
3435 Status
= PciExplainBar (
3436 &(Bridge
->Bar
[Index
]),
3437 &(mConfigSpace
->Common
.Command
),
3443 if (EFI_ERROR (Status
)) {
3449 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
3451 ShellPrintEx (-1, -1, L
"\r\n --------------------------------------------------------------------------");
3455 // Expansion register ROM Base Address
3457 if ((Bridge
->ExpansionRomBAR
& BIT0
) == 0) {
3458 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->ExpansionRomBAR
)));
3461 ShellPrintHiiEx(-1, -1, NULL
,
3462 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2
),
3463 gShellDebug1HiiHandle
,
3464 INDEX_OF (&(Bridge
->ExpansionRomBAR
)),
3465 Bridge
->ExpansionRomBAR
3469 // Print Bus Numbers(Primary, Secondary, and Subordinate
3471 ShellPrintHiiEx(-1, -1, NULL
,
3472 STRING_TOKEN (STR_PCI2_BUS_NUMBERS
),
3473 gShellDebug1HiiHandle
,
3474 INDEX_OF (&(Bridge
->PrimaryBus
)),
3475 INDEX_OF (&(Bridge
->SecondaryBus
)),
3476 INDEX_OF (&(Bridge
->SubordinateBus
))
3479 ShellPrintEx (-1, -1, L
" ------------------------------------------------------\r\n");
3481 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->PrimaryBus
);
3482 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SecondaryBus
);
3483 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SubordinateBus
);
3486 // Print register Secondary Latency Timer
3488 ShellPrintHiiEx(-1, -1, NULL
,
3489 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER
),
3490 gShellDebug1HiiHandle
,
3491 INDEX_OF (&(Bridge
->SecondaryLatencyTimer
)),
3492 Bridge
->SecondaryLatencyTimer
3496 // Print register Secondary Status
3498 PciExplainStatus (&(Bridge
->SecondaryStatus
), FALSE
, PciP2pBridge
);
3501 // Print I/O and memory ranges this bridge forwards. There are 3 resource
3502 // types: I/O, memory, and pre-fetchable memory. For each resource type,
3503 // base and limit address are listed.
3505 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE
), gShellDebug1HiiHandle
);
3506 ShellPrintEx (-1, -1, L
"----------------------------------------------------------------------\r\n");
3511 IoAddress32
= (Bridge
->IoBaseUpper16
<< 16 | Bridge
->IoBase
<< 8);
3512 IoAddress32
&= 0xfffff000;
3513 ShellPrintHiiEx(-1, -1, NULL
,
3514 STRING_TOKEN (STR_PCI2_TWO_VARS
),
3515 gShellDebug1HiiHandle
,
3516 INDEX_OF (&(Bridge
->IoBase
)),
3520 IoAddress32
= (Bridge
->IoLimitUpper16
<< 16 | Bridge
->IoLimit
<< 8);
3521 IoAddress32
|= 0x00000fff;
3522 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR
), gShellDebug1HiiHandle
, IoAddress32
);
3525 // Memory Base & Limit
3527 ShellPrintHiiEx(-1, -1, NULL
,
3528 STRING_TOKEN (STR_PCI2_MEMORY
),
3529 gShellDebug1HiiHandle
,
3530 INDEX_OF (&(Bridge
->MemoryBase
)),
3531 (Bridge
->MemoryBase
<< 16) & 0xfff00000
3534 ShellPrintHiiEx(-1, -1, NULL
,
3535 STRING_TOKEN (STR_PCI2_ONE_VAR
),
3536 gShellDebug1HiiHandle
,
3537 (Bridge
->MemoryLimit
<< 16) | 0x000fffff
3541 // Pre-fetch-able Memory Base & Limit
3543 ShellPrintHiiEx(-1, -1, NULL
,
3544 STRING_TOKEN (STR_PCI2_PREFETCHABLE
),
3545 gShellDebug1HiiHandle
,
3546 INDEX_OF (&(Bridge
->PrefetchableMemoryBase
)),
3547 Bridge
->PrefetchableBaseUpper32
,
3548 (Bridge
->PrefetchableMemoryBase
<< 16) & 0xfff00000
3551 ShellPrintHiiEx(-1, -1, NULL
,
3552 STRING_TOKEN (STR_PCI2_TWO_VARS_2
),
3553 gShellDebug1HiiHandle
,
3554 Bridge
->PrefetchableLimitUpper32
,
3555 (Bridge
->PrefetchableMemoryLimit
<< 16) | 0x000fffff
3559 // Print register Capabilities Pointer
3561 ShellPrintHiiEx(-1, -1, NULL
,
3562 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2
),
3563 gShellDebug1HiiHandle
,
3564 INDEX_OF (&(Bridge
->CapabilityPtr
)),
3565 Bridge
->CapabilityPtr
3569 // Print register Bridge Control
3571 PciExplainBridgeControl (&(Bridge
->BridgeControl
), PciP2pBridge
);
3574 // Print register Interrupt Line & PIN
3576 ShellPrintHiiEx(-1, -1, NULL
,
3577 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2
),
3578 gShellDebug1HiiHandle
,
3579 INDEX_OF (&(Bridge
->InterruptLine
)),
3580 Bridge
->InterruptLine
3583 ShellPrintHiiEx(-1, -1, NULL
,
3584 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3585 gShellDebug1HiiHandle
,
3586 INDEX_OF (&(Bridge
->InterruptPin
)),
3587 Bridge
->InterruptPin
3594 Explain the Base Address Register(Bar) in PCI configuration space.
3596 @param[in] Bar Points to the Base Address Register intended to interpret.
3597 @param[in] Command Points to the register Command.
3598 @param[in] Address Address used to access configuration space of this PCI device.
3599 @param[in] IoDev Handle used to access configuration space of PCI device.
3600 @param[in, out] Index The Index.
3602 @retval EFI_SUCCESS The command completed successfully.
3609 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3630 // According the bar type, list detail about this bar, for example: 32 or
3631 // 64 bits; pre-fetchable or not.
3633 if ((*Bar
& BIT0
) == 0) {
3635 // This bar is of memory type
3639 if ((*Bar
& BIT1
) == 0 && (*Bar
& BIT2
) == 0) {
3640 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3641 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3642 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_32_BITS
), gShellDebug1HiiHandle
);
3644 } else if ((*Bar
& BIT1
) == 0 && (*Bar
& BIT2
) != 0) {
3646 CopyMem (&Bar64
, Bar
, sizeof (UINT64
));
3647 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_2
), gShellDebug1HiiHandle
, (UINT32
) RShiftU64 ((Bar64
& 0xfffffffffffffff0ULL
), 32));
3648 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_3
), gShellDebug1HiiHandle
, (UINT32
) (Bar64
& 0xfffffffffffffff0ULL
));
3649 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3650 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_64_BITS
), gShellDebug1HiiHandle
);
3658 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3659 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM_2
), gShellDebug1HiiHandle
);
3662 if ((*Bar
& BIT3
) == 0) {
3663 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO
), gShellDebug1HiiHandle
);
3666 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_YES
), gShellDebug1HiiHandle
);
3671 // This bar is of io type
3674 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_4
), gShellDebug1HiiHandle
, *Bar
& 0xfffffffc);
3675 ShellPrintEx (-1, -1, L
"I/O ");
3679 // Get BAR length(or the amount of resource this bar demands for). To get
3680 // Bar length, first we should temporarily disable I/O and memory access
3681 // of this function(by set bits in the register Command), then write all
3682 // "1"s to this bar. The bar value read back is the amount of resource
3683 // this bar demands for.
3686 // Disable io & mem access
3688 OldCommand
= *Command
;
3689 NewCommand
= (UINT16
) (OldCommand
& 0xfffc);
3690 RegAddress
= Address
| INDEX_OF (Command
);
3691 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &NewCommand
);
3693 RegAddress
= Address
| INDEX_OF (Bar
);
3696 // Read after write the BAR to get the size
3700 NewBar32
= 0xffffffff;
3702 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3703 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3704 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &OldBar32
);
3707 NewBar32
= NewBar32
& 0xfffffff0;
3708 NewBar32
= (~NewBar32
) + 1;
3711 NewBar32
= NewBar32
& 0xfffffffc;
3712 NewBar32
= (~NewBar32
) + 1;
3713 NewBar32
= NewBar32
& 0x0000ffff;
3718 CopyMem (&OldBar64
, Bar
, sizeof (UINT64
));
3719 NewBar64
= 0xffffffffffffffffULL
;
3721 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3722 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3723 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &OldBar64
);
3726 NewBar64
= NewBar64
& 0xfffffffffffffff0ULL
;
3727 NewBar64
= (~NewBar64
) + 1;
3730 NewBar64
= NewBar64
& 0xfffffffffffffffcULL
;
3731 NewBar64
= (~NewBar64
) + 1;
3732 NewBar64
= NewBar64
& 0x000000000000ffff;
3736 // Enable io & mem access
3738 RegAddress
= Address
| INDEX_OF (Command
);
3739 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &OldCommand
);
3743 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32
), gShellDebug1HiiHandle
, NewBar32
);
3744 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_2
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffff0) - 1);
3747 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) RShiftU64 (NewBar64
, 32));
3748 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) NewBar64
);
3749 ShellPrintEx (-1, -1, L
" ");
3750 ShellPrintHiiEx(-1, -1, NULL
,
3751 STRING_TOKEN (STR_PCI2_RSHIFT
),
3752 gShellDebug1HiiHandle
,
3753 (UINT32
) RShiftU64 ((NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1), 32)
3755 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) (NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1));
3759 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_3
), gShellDebug1HiiHandle
, NewBar32
);
3760 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_4
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffffc) - 1);
3767 Explain the cardbus specific part of data in PCI configuration space.
3769 @param[in] CardBus CardBus specific region of PCI configuration space.
3770 @param[in] Address Address used to access configuration space of this PCI device.
3771 @param[in] IoDev Handle used to access configuration space of PCI device.
3773 @retval EFI_SUCCESS The command completed successfully.
3776 PciExplainCardBusData (
3777 IN PCI_CARDBUS_CONTROL_REGISTER
*CardBus
,
3779 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3783 PCI_CARDBUS_DATA
*CardBusData
;
3785 ShellPrintHiiEx(-1, -1, NULL
,
3786 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET
),
3787 gShellDebug1HiiHandle
,
3788 INDEX_OF (&(CardBus
->CardBusSocketReg
)),
3789 CardBus
->CardBusSocketReg
3793 // Print Secondary Status
3795 PciExplainStatus (&(CardBus
->SecondaryStatus
), FALSE
, PciCardBusBridge
);
3798 // Print Bus Numbers(Primary bus number, CardBus bus number, and
3799 // Subordinate bus number
3801 ShellPrintHiiEx(-1, -1, NULL
,
3802 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2
),
3803 gShellDebug1HiiHandle
,
3804 INDEX_OF (&(CardBus
->PciBusNumber
)),
3805 INDEX_OF (&(CardBus
->CardBusBusNumber
)),
3806 INDEX_OF (&(CardBus
->SubordinateBusNumber
))
3809 ShellPrintEx (-1, -1, L
" ------------------------------------------------------\r\n");
3811 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS
), gShellDebug1HiiHandle
, CardBus
->PciBusNumber
);
3812 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_2
), gShellDebug1HiiHandle
, CardBus
->CardBusBusNumber
);
3813 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_3
), gShellDebug1HiiHandle
, CardBus
->SubordinateBusNumber
);
3816 // Print CardBus Latency Timer
3818 ShellPrintHiiEx(-1, -1, NULL
,
3819 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY
),
3820 gShellDebug1HiiHandle
,
3821 INDEX_OF (&(CardBus
->CardBusLatencyTimer
)),
3822 CardBus
->CardBusLatencyTimer
3826 // Print Memory/Io ranges this cardbus bridge forwards
3828 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2
), gShellDebug1HiiHandle
);
3829 ShellPrintEx (-1, -1, L
"----------------------------------------------------------------------\r\n");
3831 ShellPrintHiiEx(-1, -1, NULL
,
3832 STRING_TOKEN (STR_PCI2_MEM_3
),
3833 gShellDebug1HiiHandle
,
3834 INDEX_OF (&(CardBus
->MemoryBase0
)),
3835 CardBus
->BridgeControl
& BIT8
? L
" Prefetchable" : L
"Non-Prefetchable",
3836 CardBus
->MemoryBase0
& 0xfffff000,
3837 CardBus
->MemoryLimit0
| 0x00000fff
3840 ShellPrintHiiEx(-1, -1, NULL
,
3841 STRING_TOKEN (STR_PCI2_MEM_3
),
3842 gShellDebug1HiiHandle
,
3843 INDEX_OF (&(CardBus
->MemoryBase1
)),
3844 CardBus
->BridgeControl
& BIT9
? L
" Prefetchable" : L
"Non-Prefetchable",
3845 CardBus
->MemoryBase1
& 0xfffff000,
3846 CardBus
->MemoryLimit1
| 0x00000fff
3849 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase0
& BIT0
);
3850 ShellPrintHiiEx(-1, -1, NULL
,
3851 STRING_TOKEN (STR_PCI2_IO_2
),
3852 gShellDebug1HiiHandle
,
3853 INDEX_OF (&(CardBus
->IoBase0
)),
3854 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3855 CardBus
->IoBase0
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3856 (CardBus
->IoLimit0
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3859 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase1
& BIT0
);
3860 ShellPrintHiiEx(-1, -1, NULL
,
3861 STRING_TOKEN (STR_PCI2_IO_2
),
3862 gShellDebug1HiiHandle
,
3863 INDEX_OF (&(CardBus
->IoBase1
)),
3864 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3865 CardBus
->IoBase1
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3866 (CardBus
->IoLimit1
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3870 // Print register Interrupt Line & PIN
3872 ShellPrintHiiEx(-1, -1, NULL
,
3873 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3
),
3874 gShellDebug1HiiHandle
,
3875 INDEX_OF (&(CardBus
->InterruptLine
)),
3876 CardBus
->InterruptLine
,
3877 INDEX_OF (&(CardBus
->InterruptPin
)),
3878 CardBus
->InterruptPin
3882 // Print register Bridge Control
3884 PciExplainBridgeControl (&(CardBus
->BridgeControl
), PciCardBusBridge
);
3887 // Print some registers in data region of PCI configuration space for cardbus
3888 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base
3891 CardBusData
= (PCI_CARDBUS_DATA
*) ((UINT8
*) CardBus
+ sizeof (PCI_CARDBUS_CONTROL_REGISTER
));
3893 ShellPrintHiiEx(-1, -1, NULL
,
3894 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2
),
3895 gShellDebug1HiiHandle
,
3896 INDEX_OF (&(CardBusData
->SubVendorId
)),
3897 CardBusData
->SubVendorId
,
3898 INDEX_OF (&(CardBusData
->SubSystemId
)),
3899 CardBusData
->SubSystemId
3902 ShellPrintHiiEx(-1, -1, NULL
,
3903 STRING_TOKEN (STR_PCI2_OPTIONAL
),
3904 gShellDebug1HiiHandle
,
3905 INDEX_OF (&(CardBusData
->LegacyBase
)),
3906 CardBusData
->LegacyBase
3913 Explain each meaningful bit of register Status. The definition of Status is
3914 slightly different depending on the PCI header type.
3916 @param[in] Status Points to the content of register Status.
3917 @param[in] MainStatus Indicates if this register is main status(not secondary
3919 @param[in] HeaderType Header type of this PCI device.
3921 @retval EFI_SUCCESS The command completed successfully.
3926 IN BOOLEAN MainStatus
,
3927 IN PCI_HEADER_TYPE HeaderType
3931 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3934 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3937 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES
), gShellDebug1HiiHandle
, (*Status
& BIT4
) != 0);
3940 // Bit 5 is meaningless for CardBus Bridge
3942 if (HeaderType
== PciCardBusBridge
) {
3943 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE
), gShellDebug1HiiHandle
, (*Status
& BIT5
) != 0);
3946 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE_2
), gShellDebug1HiiHandle
, (*Status
& BIT5
) != 0);
3949 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST_BACK
), gShellDebug1HiiHandle
, (*Status
& BIT7
) != 0);
3951 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MASTER_DATA
), gShellDebug1HiiHandle
, (*Status
& BIT8
) != 0);
3953 // Bit 9 and bit 10 together decides the DEVSEL timing
3955 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING
), gShellDebug1HiiHandle
);
3956 if ((*Status
& BIT9
) == 0 && (*Status
& BIT10
) == 0) {
3957 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST
), gShellDebug1HiiHandle
);
3959 } else if ((*Status
& BIT9
) != 0 && (*Status
& BIT10
) == 0) {
3960 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEDIUM
), gShellDebug1HiiHandle
);
3962 } else if ((*Status
& BIT9
) == 0 && (*Status
& BIT10
) != 0) {
3963 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SLOW
), gShellDebug1HiiHandle
);
3966 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED_2
), gShellDebug1HiiHandle
);
3969 ShellPrintHiiEx(-1, -1, NULL
,
3970 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET
),
3971 gShellDebug1HiiHandle
,
3972 (*Status
& BIT11
) != 0
3975 ShellPrintHiiEx(-1, -1, NULL
,
3976 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET
),
3977 gShellDebug1HiiHandle
,
3978 (*Status
& BIT12
) != 0
3981 ShellPrintHiiEx(-1, -1, NULL
,
3982 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER
),
3983 gShellDebug1HiiHandle
,
3984 (*Status
& BIT13
) != 0
3988 ShellPrintHiiEx(-1, -1, NULL
,
3989 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR
),
3990 gShellDebug1HiiHandle
,
3991 (*Status
& BIT14
) != 0
3995 ShellPrintHiiEx(-1, -1, NULL
,
3996 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR
),
3997 gShellDebug1HiiHandle
,
3998 (*Status
& BIT14
) != 0
4002 ShellPrintHiiEx(-1, -1, NULL
,
4003 STRING_TOKEN (STR_PCI2_DETECTED_ERROR
),
4004 gShellDebug1HiiHandle
,
4005 (*Status
& BIT15
) != 0
4012 Explain each meaningful bit of register Command.
4014 @param[in] Command Points to the content of register Command.
4016 @retval EFI_SUCCESS The command completed successfully.
4024 // Print the binary value of register Command
4026 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_COMMAND
), gShellDebug1HiiHandle
, INDEX_OF (Command
), *Command
);
4029 // Explain register Command bit by bit
4031 ShellPrintHiiEx(-1, -1, NULL
,
4032 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED
),
4033 gShellDebug1HiiHandle
,
4034 (*Command
& BIT0
) != 0
4037 ShellPrintHiiEx(-1, -1, NULL
,
4038 STRING_TOKEN (STR_PCI2_MEMORY_SPACE
),
4039 gShellDebug1HiiHandle
,
4040 (*Command
& BIT1
) != 0
4043 ShellPrintHiiEx(-1, -1, NULL
,
4044 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER
),
4045 gShellDebug1HiiHandle
,
4046 (*Command
& BIT2
) != 0
4049 ShellPrintHiiEx(-1, -1, NULL
,
4050 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE
),
4051 gShellDebug1HiiHandle
,
4052 (*Command
& BIT3
) != 0
4055 ShellPrintHiiEx(-1, -1, NULL
,
4056 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE
),
4057 gShellDebug1HiiHandle
,
4058 (*Command
& BIT4
) != 0
4061 ShellPrintHiiEx(-1, -1, NULL
,
4062 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING
),
4063 gShellDebug1HiiHandle
,
4064 (*Command
& BIT5
) != 0
4067 ShellPrintHiiEx(-1, -1, NULL
,
4068 STRING_TOKEN (STR_PCI2_ASSERT_PERR
),
4069 gShellDebug1HiiHandle
,
4070 (*Command
& BIT6
) != 0
4073 ShellPrintHiiEx(-1, -1, NULL
,
4074 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING
),
4075 gShellDebug1HiiHandle
,
4076 (*Command
& BIT7
) != 0
4079 ShellPrintHiiEx(-1, -1, NULL
,
4080 STRING_TOKEN (STR_PCI2_SERR_DRIVER
),
4081 gShellDebug1HiiHandle
,
4082 (*Command
& BIT8
) != 0
4085 ShellPrintHiiEx(-1, -1, NULL
,
4086 STRING_TOKEN (STR_PCI2_FAST_BACK_2
),
4087 gShellDebug1HiiHandle
,
4088 (*Command
& BIT9
) != 0
4095 Explain each meaningful bit of register Bridge Control.
4097 @param[in] BridgeControl Points to the content of register Bridge Control.
4098 @param[in] HeaderType The headertype.
4100 @retval EFI_SUCCESS The command completed successfully.
4103 PciExplainBridgeControl (
4104 IN UINT16
*BridgeControl
,
4105 IN PCI_HEADER_TYPE HeaderType
4108 ShellPrintHiiEx(-1, -1, NULL
,
4109 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL
),
4110 gShellDebug1HiiHandle
,
4111 INDEX_OF (BridgeControl
),
4115 ShellPrintHiiEx(-1, -1, NULL
,
4116 STRING_TOKEN (STR_PCI2_PARITY_ERROR
),
4117 gShellDebug1HiiHandle
,
4118 (*BridgeControl
& BIT0
) != 0
4120 ShellPrintHiiEx(-1, -1, NULL
,
4121 STRING_TOKEN (STR_PCI2_SERR_ENABLE
),
4122 gShellDebug1HiiHandle
,
4123 (*BridgeControl
& BIT1
) != 0
4125 ShellPrintHiiEx(-1, -1, NULL
,
4126 STRING_TOKEN (STR_PCI2_ISA_ENABLE
),
4127 gShellDebug1HiiHandle
,
4128 (*BridgeControl
& BIT2
) != 0
4130 ShellPrintHiiEx(-1, -1, NULL
,
4131 STRING_TOKEN (STR_PCI2_VGA_ENABLE
),
4132 gShellDebug1HiiHandle
,
4133 (*BridgeControl
& BIT3
) != 0
4135 ShellPrintHiiEx(-1, -1, NULL
,
4136 STRING_TOKEN (STR_PCI2_MASTER_ABORT
),
4137 gShellDebug1HiiHandle
,
4138 (*BridgeControl
& BIT5
) != 0
4142 // Register Bridge Control has some slight differences between P2P bridge
4143 // and Cardbus bridge from bit 6 to bit 11.
4145 if (HeaderType
== PciP2pBridge
) {
4146 ShellPrintHiiEx(-1, -1, NULL
,
4147 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET
),
4148 gShellDebug1HiiHandle
,
4149 (*BridgeControl
& BIT6
) != 0
4151 ShellPrintHiiEx(-1, -1, NULL
,
4152 STRING_TOKEN (STR_PCI2_FAST_ENABLE
),
4153 gShellDebug1HiiHandle
,
4154 (*BridgeControl
& BIT7
) != 0
4156 ShellPrintHiiEx(-1, -1, NULL
,
4157 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER
),
4158 gShellDebug1HiiHandle
,
4159 (*BridgeControl
& BIT8
)!=0 ? L
"2^10" : L
"2^15"
4161 ShellPrintHiiEx(-1, -1, NULL
,
4162 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER
),
4163 gShellDebug1HiiHandle
,
4164 (*BridgeControl
& BIT9
)!=0 ? L
"2^10" : L
"2^15"
4166 ShellPrintHiiEx(-1, -1, NULL
,
4167 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS
),
4168 gShellDebug1HiiHandle
,
4169 (*BridgeControl
& BIT10
) != 0
4171 ShellPrintHiiEx(-1, -1, NULL
,
4172 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR
),
4173 gShellDebug1HiiHandle
,
4174 (*BridgeControl
& BIT11
) != 0
4178 ShellPrintHiiEx(-1, -1, NULL
,
4179 STRING_TOKEN (STR_PCI2_CARDBUS_RESET
),
4180 gShellDebug1HiiHandle
,
4181 (*BridgeControl
& BIT6
) != 0
4183 ShellPrintHiiEx(-1, -1, NULL
,
4184 STRING_TOKEN (STR_PCI2_IREQ_ENABLE
),
4185 gShellDebug1HiiHandle
,
4186 (*BridgeControl
& BIT7
) != 0
4188 ShellPrintHiiEx(-1, -1, NULL
,
4189 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE
),
4190 gShellDebug1HiiHandle
,
4191 (*BridgeControl
& BIT10
) != 0
4199 Locate capability register block per capability ID.
4201 @param[in] ConfigSpace Data in PCI configuration space.
4202 @param[in] CapabilityId The capability ID.
4204 @return The offset of the register block per capability ID,
4205 or 0 if the register block cannot be found.
4208 LocatePciCapability (
4209 IN PCI_CONFIG_SPACE
*ConfigSpace
,
4210 IN UINT8 CapabilityId
4213 UINT8 CapabilityPtr
;
4214 EFI_PCI_CAPABILITY_HDR
*CapabilityEntry
;
4217 // To check the cpability of this device supports
4219 if ((ConfigSpace
->Common
.Status
& EFI_PCI_STATUS_CAPABILITY
) == 0) {
4223 switch ((PCI_HEADER_TYPE
)(ConfigSpace
->Common
.HeaderType
& 0x7f)) {
4225 CapabilityPtr
= ConfigSpace
->NonCommon
.Device
.CapabilityPtr
;
4228 CapabilityPtr
= ConfigSpace
->NonCommon
.Bridge
.CapabilityPtr
;
4230 case PciCardBusBridge
:
4231 CapabilityPtr
= ConfigSpace
->NonCommon
.CardBus
.Cap_Ptr
;
4237 while ((CapabilityPtr
>= 0x40) && ((CapabilityPtr
& 0x03) == 0x00)) {
4238 CapabilityEntry
= (EFI_PCI_CAPABILITY_HDR
*) ((UINT8
*) ConfigSpace
+ CapabilityPtr
);
4239 if (CapabilityEntry
->CapabilityID
== CapabilityId
) {
4240 return CapabilityPtr
;
4244 // Certain PCI device may incorrectly have capability pointing to itself,
4245 // break to avoid dead loop.
4247 if (CapabilityPtr
== CapabilityEntry
->NextItemPtr
) {
4251 CapabilityPtr
= CapabilityEntry
->NextItemPtr
;
4258 Print out information of the capability information.
4260 @param[in] PciExpressCap The pointer to the structure about the device.
4262 @retval EFI_SUCCESS The operation was successful.
4266 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4269 CHAR16
*DevicePortType
;
4271 ShellPrintEx (-1, -1,
4272 L
" Capability Version(3:0): %E0x%04x%N\r\n",
4273 PciExpressCap
->Capability
.Bits
.Version
4275 if (PciExpressCap
->Capability
.Bits
.DevicePortType
< ARRAY_SIZE (DevicePortTypeTable
)) {
4276 DevicePortType
= DevicePortTypeTable
[PciExpressCap
->Capability
.Bits
.DevicePortType
];
4278 DevicePortType
= L
"Unknown Type";
4280 ShellPrintEx (-1, -1,
4281 L
" Device/PortType(7:4): %E%s%N\r\n",
4285 // 'Slot Implemented' is only valid for:
4286 // a) Root Port of PCI Express Root Complex, or
4287 // b) Downstream Port of PCI Express Switch
4289 if (PciExpressCap
->Capability
.Bits
.DevicePortType
== PCIE_DEVICE_PORT_TYPE_ROOT_PORT
||
4290 PciExpressCap
->Capability
.Bits
.DevicePortType
== PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT
) {
4291 ShellPrintEx (-1, -1,
4292 L
" Slot Implemented(8): %E%d%N\r\n",
4293 PciExpressCap
->Capability
.Bits
.SlotImplemented
4296 ShellPrintEx (-1, -1,
4297 L
" Interrupt Message Number(13:9): %E0x%05x%N\r\n",
4298 PciExpressCap
->Capability
.Bits
.InterruptMessageNumber
4304 Print out information of the device capability information.
4306 @param[in] PciExpressCap The pointer to the structure about the device.
4308 @retval EFI_SUCCESS The operation was successful.
4311 ExplainPcieDeviceCap (
4312 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4315 UINT8 DevicePortType
;
4319 DevicePortType
= (UINT8
)PciExpressCap
->Capability
.Bits
.DevicePortType
;
4320 ShellPrintEx (-1, -1, L
" Max_Payload_Size Supported(2:0): ");
4321 if (PciExpressCap
->DeviceCapability
.Bits
.MaxPayloadSize
< 6) {
4322 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PciExpressCap
->DeviceCapability
.Bits
.MaxPayloadSize
+ 7));
4324 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4326 ShellPrintEx (-1, -1,
4327 L
" Phantom Functions Supported(4:3): %E%d%N\r\n",
4328 PciExpressCap
->DeviceCapability
.Bits
.PhantomFunctions
4330 ShellPrintEx (-1, -1,
4331 L
" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",
4332 PciExpressCap
->DeviceCapability
.Bits
.ExtendedTagField
? 8 : 5
4335 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint
4337 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
4338 L0sLatency
= (UINT8
)PciExpressCap
->DeviceCapability
.Bits
.EndpointL0sAcceptableLatency
;
4339 L1Latency
= (UINT8
)PciExpressCap
->DeviceCapability
.Bits
.EndpointL1AcceptableLatency
;
4340 ShellPrintEx (-1, -1, L
" Endpoint L0s Acceptable Latency(8:6): ");
4341 if (L0sLatency
< 4) {
4342 ShellPrintEx (-1, -1, L
"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency
+ 6));
4344 if (L0sLatency
< 7) {
4345 ShellPrintEx (-1, -1, L
"%EMaximum of %d us%N\r\n", 1 << (L0sLatency
- 3));
4347 ShellPrintEx (-1, -1, L
"%ENo limit%N\r\n");
4350 ShellPrintEx (-1, -1, L
" Endpoint L1 Acceptable Latency(11:9): ");
4351 if (L1Latency
< 7) {
4352 ShellPrintEx (-1, -1, L
"%EMaximum of %d us%N\r\n", 1 << (L1Latency
+ 1));
4354 ShellPrintEx (-1, -1, L
"%ENo limit%N\r\n");
4357 ShellPrintEx (-1, -1,
4358 L
" Role-based Error Reporting(15): %E%d%N\r\n",
4359 PciExpressCap
->DeviceCapability
.Bits
.RoleBasedErrorReporting
4362 // Only valid for Upstream Port:
4363 // a) Captured Slot Power Limit Value
4364 // b) Captured Slot Power Scale
4366 if (DevicePortType
== PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT
) {
4367 ShellPrintEx (-1, -1,
4368 L
" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",
4369 PciExpressCap
->DeviceCapability
.Bits
.CapturedSlotPowerLimitValue
4371 ShellPrintEx (-1, -1,
4372 L
" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",
4373 SlotPwrLmtScaleTable
[PciExpressCap
->DeviceCapability
.Bits
.CapturedSlotPowerLimitScale
]
4377 // Function Level Reset Capability is only valid for Endpoint
4379 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
4380 ShellPrintEx (-1, -1,
4381 L
" Function Level Reset Capability(28): %E%d%N\r\n",
4382 PciExpressCap
->DeviceCapability
.Bits
.FunctionLevelReset
4389 Print out information of the device control information.
4391 @param[in] PciExpressCap The pointer to the structure about the device.
4393 @retval EFI_SUCCESS The operation was successful.
4396 ExplainPcieDeviceControl (
4397 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4400 ShellPrintEx (-1, -1,
4401 L
" Correctable Error Reporting Enable(0): %E%d%N\r\n",
4402 PciExpressCap
->DeviceControl
.Bits
.CorrectableError
4404 ShellPrintEx (-1, -1,
4405 L
" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",
4406 PciExpressCap
->DeviceControl
.Bits
.NonFatalError
4408 ShellPrintEx (-1, -1,
4409 L
" Fatal Error Reporting Enable(2): %E%d%N\r\n",
4410 PciExpressCap
->DeviceControl
.Bits
.FatalError
4412 ShellPrintEx (-1, -1,
4413 L
" Unsupported Request Reporting Enable(3): %E%d%N\r\n",
4414 PciExpressCap
->DeviceControl
.Bits
.UnsupportedRequest
4416 ShellPrintEx (-1, -1,
4417 L
" Enable Relaxed Ordering(4): %E%d%N\r\n",
4418 PciExpressCap
->DeviceControl
.Bits
.RelaxedOrdering
4420 ShellPrintEx (-1, -1, L
" Max_Payload_Size(7:5): ");
4421 if (PciExpressCap
->DeviceControl
.Bits
.MaxPayloadSize
< 6) {
4422 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PciExpressCap
->DeviceControl
.Bits
.MaxPayloadSize
+ 7));
4424 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4426 ShellPrintEx (-1, -1,
4427 L
" Extended Tag Field Enable(8): %E%d%N\r\n",
4428 PciExpressCap
->DeviceControl
.Bits
.ExtendedTagField
4430 ShellPrintEx (-1, -1,
4431 L
" Phantom Functions Enable(9): %E%d%N\r\n",
4432 PciExpressCap
->DeviceControl
.Bits
.PhantomFunctions
4434 ShellPrintEx (-1, -1,
4435 L
" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",
4436 PciExpressCap
->DeviceControl
.Bits
.AuxPower
4438 ShellPrintEx (-1, -1,
4439 L
" Enable No Snoop(11): %E%d%N\r\n",
4440 PciExpressCap
->DeviceControl
.Bits
.NoSnoop
4442 ShellPrintEx (-1, -1, L
" Max_Read_Request_Size(14:12): ");
4443 if (PciExpressCap
->DeviceControl
.Bits
.MaxReadRequestSize
< 6) {
4444 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PciExpressCap
->DeviceControl
.Bits
.MaxReadRequestSize
+ 7));
4446 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4449 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges
4451 if (PciExpressCap
->Capability
.Bits
.DevicePortType
== PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE
) {
4452 ShellPrintEx (-1, -1,
4453 L
" Bridge Configuration Retry Enable(15): %E%d%N\r\n",
4454 PciExpressCap
->DeviceControl
.Bits
.BridgeConfigurationRetryOrFunctionLevelReset
4461 Print out information of the device status information.
4463 @param[in] PciExpressCap The pointer to the structure about the device.
4465 @retval EFI_SUCCESS The operation was successful.
4468 ExplainPcieDeviceStatus (
4469 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4472 ShellPrintEx (-1, -1,
4473 L
" Correctable Error Detected(0): %E%d%N\r\n",
4474 PciExpressCap
->DeviceStatus
.Bits
.CorrectableError
4476 ShellPrintEx (-1, -1,
4477 L
" Non-Fatal Error Detected(1): %E%d%N\r\n",
4478 PciExpressCap
->DeviceStatus
.Bits
.NonFatalError
4480 ShellPrintEx (-1, -1,
4481 L
" Fatal Error Detected(2): %E%d%N\r\n",
4482 PciExpressCap
->DeviceStatus
.Bits
.FatalError
4484 ShellPrintEx (-1, -1,
4485 L
" Unsupported Request Detected(3): %E%d%N\r\n",
4486 PciExpressCap
->DeviceStatus
.Bits
.UnsupportedRequest
4488 ShellPrintEx (-1, -1,
4489 L
" AUX Power Detected(4): %E%d%N\r\n",
4490 PciExpressCap
->DeviceStatus
.Bits
.AuxPower
4492 ShellPrintEx (-1, -1,
4493 L
" Transactions Pending(5): %E%d%N\r\n",
4494 PciExpressCap
->DeviceStatus
.Bits
.TransactionsPending
4500 Print out information of the device link information.
4502 @param[in] PciExpressCap The pointer to the structure about the device.
4504 @retval EFI_SUCCESS The operation was successful.
4507 ExplainPcieLinkCap (
4508 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4511 CHAR16
*MaxLinkSpeed
;
4514 switch (PciExpressCap
->LinkCapability
.Bits
.MaxLinkSpeed
) {
4516 MaxLinkSpeed
= L
"2.5 GT/s";
4519 MaxLinkSpeed
= L
"5.0 GT/s";
4522 MaxLinkSpeed
= L
"8.0 GT/s";
4525 MaxLinkSpeed
= L
"Unknown";
4528 ShellPrintEx (-1, -1,
4529 L
" Maximum Link Speed(3:0): %E%s%N\r\n",
4532 ShellPrintEx (-1, -1,
4533 L
" Maximum Link Width(9:4): %Ex%d%N\r\n",
4534 PciExpressCap
->LinkCapability
.Bits
.MaxLinkWidth
4536 switch (PciExpressCap
->LinkCapability
.Bits
.Aspm
) {
4547 AspmValue
= L
"L0s and L1";
4550 AspmValue
= L
"Reserved";
4553 ShellPrintEx (-1, -1,
4554 L
" Active State Power Management Support(11:10): %E%s Supported%N\r\n",
4557 ShellPrintEx (-1, -1,
4558 L
" L0s Exit Latency(14:12): %E%s%N\r\n",
4559 L0sLatencyStrTable
[PciExpressCap
->LinkCapability
.Bits
.L0sExitLatency
]
4561 ShellPrintEx (-1, -1,
4562 L
" L1 Exit Latency(17:15): %E%s%N\r\n",
4563 L1LatencyStrTable
[PciExpressCap
->LinkCapability
.Bits
.L1ExitLatency
]
4565 ShellPrintEx (-1, -1,
4566 L
" Clock Power Management(18): %E%d%N\r\n",
4567 PciExpressCap
->LinkCapability
.Bits
.ClockPowerManagement
4569 ShellPrintEx (-1, -1,
4570 L
" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",
4571 PciExpressCap
->LinkCapability
.Bits
.SurpriseDownError
4573 ShellPrintEx (-1, -1,
4574 L
" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",
4575 PciExpressCap
->LinkCapability
.Bits
.DataLinkLayerLinkActive
4577 ShellPrintEx (-1, -1,
4578 L
" Link Bandwidth Notification Capability(21): %E%d%N\r\n",
4579 PciExpressCap
->LinkCapability
.Bits
.LinkBandwidthNotification
4581 ShellPrintEx (-1, -1,
4582 L
" Port Number(31:24): %E0x%02x%N\r\n",
4583 PciExpressCap
->LinkCapability
.Bits
.PortNumber
4589 Print out information of the device link control information.
4591 @param[in] PciExpressCap The pointer to the structure about the device.
4593 @retval EFI_SUCCESS The operation was successful.
4596 ExplainPcieLinkControl (
4597 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4600 UINT8 DevicePortType
;
4602 DevicePortType
= (UINT8
)PciExpressCap
->Capability
.Bits
.DevicePortType
;
4603 ShellPrintEx (-1, -1,
4604 L
" Active State Power Management Control(1:0): %E%s%N\r\n",
4605 ASPMCtrlStrTable
[PciExpressCap
->LinkControl
.Bits
.AspmControl
]
4608 // RCB is not applicable to switches
4610 if (!IS_PCIE_SWITCH(DevicePortType
)) {
4611 ShellPrintEx (-1, -1,
4612 L
" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",
4613 1 << (PciExpressCap
->LinkControl
.Bits
.ReadCompletionBoundary
+ 6)
4617 // Link Disable is reserved on
4619 // b) PCI Express to PCI/PCI-X bridges
4620 // c) Upstream Ports of Switches
4622 if (!IS_PCIE_ENDPOINT (DevicePortType
) &&
4623 DevicePortType
!= PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT
&&
4624 DevicePortType
!= PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE
) {
4625 ShellPrintEx (-1, -1,
4626 L
" Link Disable(4): %E%d%N\r\n",
4627 PciExpressCap
->LinkControl
.Bits
.LinkDisable
4630 ShellPrintEx (-1, -1,
4631 L
" Common Clock Configuration(6): %E%d%N\r\n",
4632 PciExpressCap
->LinkControl
.Bits
.CommonClockConfiguration
4634 ShellPrintEx (-1, -1,
4635 L
" Extended Synch(7): %E%d%N\r\n",
4636 PciExpressCap
->LinkControl
.Bits
.ExtendedSynch
4638 ShellPrintEx (-1, -1,
4639 L
" Enable Clock Power Management(8): %E%d%N\r\n",
4640 PciExpressCap
->LinkControl
.Bits
.ClockPowerManagement
4642 ShellPrintEx (-1, -1,
4643 L
" Hardware Autonomous Width Disable(9): %E%d%N\r\n",
4644 PciExpressCap
->LinkControl
.Bits
.HardwareAutonomousWidthDisable
4646 ShellPrintEx (-1, -1,
4647 L
" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",
4648 PciExpressCap
->LinkControl
.Bits
.LinkBandwidthManagementInterrupt
4650 ShellPrintEx (-1, -1,
4651 L
" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",
4652 PciExpressCap
->LinkControl
.Bits
.LinkAutonomousBandwidthInterrupt
4658 Print out information of the device link status information.
4660 @param[in] PciExpressCap The pointer to the structure about the device.
4662 @retval EFI_SUCCESS The operation was successful.
4665 ExplainPcieLinkStatus (
4666 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4669 CHAR16
*CurLinkSpeed
;
4671 switch (PciExpressCap
->LinkStatus
.Bits
.CurrentLinkSpeed
) {
4673 CurLinkSpeed
= L
"2.5 GT/s";
4676 CurLinkSpeed
= L
"5.0 GT/s";
4679 CurLinkSpeed
= L
"8.0 GT/s";
4682 CurLinkSpeed
= L
"Reserved";
4685 ShellPrintEx (-1, -1,
4686 L
" Current Link Speed(3:0): %E%s%N\r\n",
4689 ShellPrintEx (-1, -1,
4690 L
" Negotiated Link Width(9:4): %Ex%d%N\r\n",
4691 PciExpressCap
->LinkStatus
.Bits
.NegotiatedLinkWidth
4693 ShellPrintEx (-1, -1,
4694 L
" Link Training(11): %E%d%N\r\n",
4695 PciExpressCap
->LinkStatus
.Bits
.LinkTraining
4697 ShellPrintEx (-1, -1,
4698 L
" Slot Clock Configuration(12): %E%d%N\r\n",
4699 PciExpressCap
->LinkStatus
.Bits
.SlotClockConfiguration
4701 ShellPrintEx (-1, -1,
4702 L
" Data Link Layer Link Active(13): %E%d%N\r\n",
4703 PciExpressCap
->LinkStatus
.Bits
.DataLinkLayerLinkActive
4705 ShellPrintEx (-1, -1,
4706 L
" Link Bandwidth Management Status(14): %E%d%N\r\n",
4707 PciExpressCap
->LinkStatus
.Bits
.LinkBandwidthManagement
4709 ShellPrintEx (-1, -1,
4710 L
" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",
4711 PciExpressCap
->LinkStatus
.Bits
.LinkAutonomousBandwidth
4717 Print out information of the device slot information.
4719 @param[in] PciExpressCap The pointer to the structure about the device.
4721 @retval EFI_SUCCESS The operation was successful.
4724 ExplainPcieSlotCap (
4725 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4728 ShellPrintEx (-1, -1,
4729 L
" Attention Button Present(0): %E%d%N\r\n",
4730 PciExpressCap
->SlotCapability
.Bits
.AttentionButton
4732 ShellPrintEx (-1, -1,
4733 L
" Power Controller Present(1): %E%d%N\r\n",
4734 PciExpressCap
->SlotCapability
.Bits
.PowerController
4736 ShellPrintEx (-1, -1,
4737 L
" MRL Sensor Present(2): %E%d%N\r\n",
4738 PciExpressCap
->SlotCapability
.Bits
.MrlSensor
4740 ShellPrintEx (-1, -1,
4741 L
" Attention Indicator Present(3): %E%d%N\r\n",
4742 PciExpressCap
->SlotCapability
.Bits
.AttentionIndicator
4744 ShellPrintEx (-1, -1,
4745 L
" Power Indicator Present(4): %E%d%N\r\n",
4746 PciExpressCap
->SlotCapability
.Bits
.PowerIndicator
4748 ShellPrintEx (-1, -1,
4749 L
" Hot-Plug Surprise(5): %E%d%N\r\n",
4750 PciExpressCap
->SlotCapability
.Bits
.HotPlugSurprise
4752 ShellPrintEx (-1, -1,
4753 L
" Hot-Plug Capable(6): %E%d%N\r\n",
4754 PciExpressCap
->SlotCapability
.Bits
.HotPlugCapable
4756 ShellPrintEx (-1, -1,
4757 L
" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",
4758 PciExpressCap
->SlotCapability
.Bits
.SlotPowerLimitValue
4760 ShellPrintEx (-1, -1,
4761 L
" Slot Power Limit Scale(16:15): %E%s%N\r\n",
4762 SlotPwrLmtScaleTable
[PciExpressCap
->SlotCapability
.Bits
.SlotPowerLimitScale
]
4764 ShellPrintEx (-1, -1,
4765 L
" Electromechanical Interlock Present(17): %E%d%N\r\n",
4766 PciExpressCap
->SlotCapability
.Bits
.ElectromechanicalInterlock
4768 ShellPrintEx (-1, -1,
4769 L
" No Command Completed Support(18): %E%d%N\r\n",
4770 PciExpressCap
->SlotCapability
.Bits
.NoCommandCompleted
4772 ShellPrintEx (-1, -1,
4773 L
" Physical Slot Number(31:19): %E%d%N\r\n",
4774 PciExpressCap
->SlotCapability
.Bits
.PhysicalSlotNumber
4781 Print out information of the device slot control information.
4783 @param[in] PciExpressCap The pointer to the structure about the device.
4785 @retval EFI_SUCCESS The operation was successful.
4788 ExplainPcieSlotControl (
4789 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4792 ShellPrintEx (-1, -1,
4793 L
" Attention Button Pressed Enable(0): %E%d%N\r\n",
4794 PciExpressCap
->SlotControl
.Bits
.AttentionButtonPressed
4796 ShellPrintEx (-1, -1,
4797 L
" Power Fault Detected Enable(1): %E%d%N\r\n",
4798 PciExpressCap
->SlotControl
.Bits
.PowerFaultDetected
4800 ShellPrintEx (-1, -1,
4801 L
" MRL Sensor Changed Enable(2): %E%d%N\r\n",
4802 PciExpressCap
->SlotControl
.Bits
.MrlSensorChanged
4804 ShellPrintEx (-1, -1,
4805 L
" Presence Detect Changed Enable(3): %E%d%N\r\n",
4806 PciExpressCap
->SlotControl
.Bits
.PresenceDetectChanged
4808 ShellPrintEx (-1, -1,
4809 L
" Command Completed Interrupt Enable(4): %E%d%N\r\n",
4810 PciExpressCap
->SlotControl
.Bits
.CommandCompletedInterrupt
4812 ShellPrintEx (-1, -1,
4813 L
" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",
4814 PciExpressCap
->SlotControl
.Bits
.HotPlugInterrupt
4816 ShellPrintEx (-1, -1,
4817 L
" Attention Indicator Control(7:6): %E%s%N\r\n",
4819 PciExpressCap
->SlotControl
.Bits
.AttentionIndicator
]
4821 ShellPrintEx (-1, -1,
4822 L
" Power Indicator Control(9:8): %E%s%N\r\n",
4823 IndicatorTable
[PciExpressCap
->SlotControl
.Bits
.PowerIndicator
]
4825 ShellPrintEx (-1, -1, L
" Power Controller Control(10): %EPower ");
4827 PciExpressCap
->SlotControl
.Bits
.PowerController
) {
4828 ShellPrintEx (-1, -1, L
"Off%N\r\n");
4830 ShellPrintEx (-1, -1, L
"On%N\r\n");
4832 ShellPrintEx (-1, -1,
4833 L
" Electromechanical Interlock Control(11): %E%d%N\r\n",
4834 PciExpressCap
->SlotControl
.Bits
.ElectromechanicalInterlock
4836 ShellPrintEx (-1, -1,
4837 L
" Data Link Layer State Changed Enable(12): %E%d%N\r\n",
4838 PciExpressCap
->SlotControl
.Bits
.DataLinkLayerStateChanged
4844 Print out information of the device slot status information.
4846 @param[in] PciExpressCap The pointer to the structure about the device.
4848 @retval EFI_SUCCESS The operation was successful.
4851 ExplainPcieSlotStatus (
4852 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4855 ShellPrintEx (-1, -1,
4856 L
" Attention Button Pressed(0): %E%d%N\r\n",
4857 PciExpressCap
->SlotStatus
.Bits
.AttentionButtonPressed
4859 ShellPrintEx (-1, -1,
4860 L
" Power Fault Detected(1): %E%d%N\r\n",
4861 PciExpressCap
->SlotStatus
.Bits
.PowerFaultDetected
4863 ShellPrintEx (-1, -1,
4864 L
" MRL Sensor Changed(2): %E%d%N\r\n",
4865 PciExpressCap
->SlotStatus
.Bits
.MrlSensorChanged
4867 ShellPrintEx (-1, -1,
4868 L
" Presence Detect Changed(3): %E%d%N\r\n",
4869 PciExpressCap
->SlotStatus
.Bits
.PresenceDetectChanged
4871 ShellPrintEx (-1, -1,
4872 L
" Command Completed(4): %E%d%N\r\n",
4873 PciExpressCap
->SlotStatus
.Bits
.CommandCompleted
4875 ShellPrintEx (-1, -1, L
" MRL Sensor State(5): %EMRL ");
4877 PciExpressCap
->SlotStatus
.Bits
.MrlSensor
) {
4878 ShellPrintEx (-1, -1, L
" Opened%N\r\n");
4880 ShellPrintEx (-1, -1, L
" Closed%N\r\n");
4882 ShellPrintEx (-1, -1, L
" Presence Detect State(6): ");
4884 PciExpressCap
->SlotStatus
.Bits
.PresenceDetect
) {
4885 ShellPrintEx (-1, -1, L
"%ECard Present in slot%N\r\n");
4887 ShellPrintEx (-1, -1, L
"%ESlot Empty%N\r\n");
4889 ShellPrintEx (-1, -1, L
" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");
4891 PciExpressCap
->SlotStatus
.Bits
.ElectromechanicalInterlock
) {
4892 ShellPrintEx (-1, -1, L
"Engaged%N\r\n");
4894 ShellPrintEx (-1, -1, L
"Disengaged%N\r\n");
4896 ShellPrintEx (-1, -1,
4897 L
" Data Link Layer State Changed(8): %E%d%N\r\n",
4898 PciExpressCap
->SlotStatus
.Bits
.DataLinkLayerStateChanged
4904 Print out information of the device root information.
4906 @param[in] PciExpressCap The pointer to the structure about the device.
4908 @retval EFI_SUCCESS The operation was successful.
4911 ExplainPcieRootControl (
4912 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4915 ShellPrintEx (-1, -1,
4916 L
" System Error on Correctable Error Enable(0): %E%d%N\r\n",
4917 PciExpressCap
->RootControl
.Bits
.SystemErrorOnCorrectableError
4919 ShellPrintEx (-1, -1,
4920 L
" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",
4921 PciExpressCap
->RootControl
.Bits
.SystemErrorOnNonFatalError
4923 ShellPrintEx (-1, -1,
4924 L
" System Error on Fatal Error Enable(2): %E%d%N\r\n",
4925 PciExpressCap
->RootControl
.Bits
.SystemErrorOnFatalError
4927 ShellPrintEx (-1, -1,
4928 L
" PME Interrupt Enable(3): %E%d%N\r\n",
4929 PciExpressCap
->RootControl
.Bits
.PmeInterrupt
4931 ShellPrintEx (-1, -1,
4932 L
" CRS Software Visibility Enable(4): %E%d%N\r\n",
4933 PciExpressCap
->RootControl
.Bits
.CrsSoftwareVisibility
4940 Print out information of the device root capability information.
4942 @param[in] PciExpressCap The pointer to the structure about the device.
4944 @retval EFI_SUCCESS The operation was successful.
4947 ExplainPcieRootCap (
4948 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4951 ShellPrintEx (-1, -1,
4952 L
" CRS Software Visibility(0): %E%d%N\r\n",
4953 PciExpressCap
->RootCapability
.Bits
.CrsSoftwareVisibility
4960 Print out information of the device root status information.
4962 @param[in] PciExpressCap The pointer to the structure about the device.
4964 @retval EFI_SUCCESS The operation was successful.
4967 ExplainPcieRootStatus (
4968 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4971 ShellPrintEx (-1, -1,
4972 L
" PME Requester ID(15:0): %E0x%04x%N\r\n",
4973 PciExpressCap
->RootStatus
.Bits
.PmeRequesterId
4975 ShellPrintEx (-1, -1,
4976 L
" PME Status(16): %E%d%N\r\n",
4977 PciExpressCap
->RootStatus
.Bits
.PmeStatus
4979 ShellPrintEx (-1, -1,
4980 L
" PME Pending(17): %E%d%N\r\n",
4981 PciExpressCap
->RootStatus
.Bits
.PmePending
4987 Function to interpret and print out the link control structure
4989 @param[in] HeaderAddress The Address of this capability header.
4990 @param[in] HeadersBaseAddress The address of all the extended capability headers.
4993 PrintInterpretedExtendedCompatibilityLinkControl (
4994 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
4995 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
4998 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
*Header
;
4999 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
*)HeaderAddress
;
5003 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL
),
5004 gShellDebug1HiiHandle
,
5005 Header
->RootComplexLinkCapabilities
,
5006 Header
->RootComplexLinkControl
,
5007 Header
->RootComplexLinkStatus
5011 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5012 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
),
5013 (VOID
*) (HeaderAddress
)
5015 return (EFI_SUCCESS
);
5019 Function to interpret and print out the power budgeting structure
5021 @param[in] HeaderAddress The Address of this capability header.
5022 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5025 PrintInterpretedExtendedCompatibilityPowerBudgeting (
5026 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5027 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5030 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
*Header
;
5031 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
*)HeaderAddress
;
5035 STRING_TOKEN (STR_PCI_EXT_CAP_POWER
),
5036 gShellDebug1HiiHandle
,
5039 Header
->PowerBudgetCapability
5043 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5044 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
),
5045 (VOID
*) (HeaderAddress
)
5047 return (EFI_SUCCESS
);
5051 Function to interpret and print out the ACS structure
5053 @param[in] HeaderAddress The Address of this capability header.
5054 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5057 PrintInterpretedExtendedCompatibilityAcs (
5058 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5059 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5062 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
*Header
;
5066 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
*)HeaderAddress
;
5071 STRING_TOKEN (STR_PCI_EXT_CAP_ACS
),
5072 gShellDebug1HiiHandle
,
5073 Header
->AcsCapability
,
5076 if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header
)) {
5077 VectorSize
= PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header
);
5078 if (VectorSize
== 0) {
5081 for (LoopCounter
= 0 ; LoopCounter
* 8 < VectorSize
; LoopCounter
++) {
5084 STRING_TOKEN (STR_PCI_EXT_CAP_ACS2
),
5085 gShellDebug1HiiHandle
,
5087 Header
->EgressControlVectorArray
[LoopCounter
]
5093 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5094 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
) + (VectorSize
/ 8) - 1,
5095 (VOID
*) (HeaderAddress
)
5097 return (EFI_SUCCESS
);
5101 Function to interpret and print out the latency tolerance reporting structure
5103 @param[in] HeaderAddress The Address of this capability header.
5104 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5107 PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (
5108 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5109 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5112 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
*Header
;
5113 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
*)HeaderAddress
;
5117 STRING_TOKEN (STR_PCI_EXT_CAP_LAT
),
5118 gShellDebug1HiiHandle
,
5119 Header
->MaxSnoopLatency
,
5120 Header
->MaxNoSnoopLatency
5124 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5125 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
),
5126 (VOID
*) (HeaderAddress
)
5128 return (EFI_SUCCESS
);
5132 Function to interpret and print out the serial number structure
5134 @param[in] HeaderAddress The Address of this capability header.
5135 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5138 PrintInterpretedExtendedCompatibilitySerialNumber (
5139 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5140 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5143 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
*Header
;
5144 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
*)HeaderAddress
;
5148 STRING_TOKEN (STR_PCI_EXT_CAP_SN
),
5149 gShellDebug1HiiHandle
,
5150 Header
->SerialNumber
5154 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5155 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
),
5156 (VOID
*) (HeaderAddress
)
5158 return (EFI_SUCCESS
);
5162 Function to interpret and print out the RCRB structure
5164 @param[in] HeaderAddress The Address of this capability header.
5165 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5168 PrintInterpretedExtendedCompatibilityRcrb (
5169 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5170 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5173 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
*Header
;
5174 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
*)HeaderAddress
;
5178 STRING_TOKEN (STR_PCI_EXT_CAP_RCRB
),
5179 gShellDebug1HiiHandle
,
5182 Header
->RcrbCapabilities
,
5187 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5188 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
),
5189 (VOID
*) (HeaderAddress
)
5191 return (EFI_SUCCESS
);
5195 Function to interpret and print out the vendor specific structure
5197 @param[in] HeaderAddress The Address of this capability header.
5198 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5201 PrintInterpretedExtendedCompatibilityVendorSpecific (
5202 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5203 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5206 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
*Header
;
5207 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
*)HeaderAddress
;
5211 STRING_TOKEN (STR_PCI_EXT_CAP_VEN
),
5212 gShellDebug1HiiHandle
,
5213 Header
->VendorSpecificHeader
5217 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5218 PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(Header
),
5219 (VOID
*) (HeaderAddress
)
5221 return (EFI_SUCCESS
);
5225 Function to interpret and print out the Event Collector Endpoint Association structure
5227 @param[in] HeaderAddress The Address of this capability header.
5228 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5231 PrintInterpretedExtendedCompatibilityECEA (
5232 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5233 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5236 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
*Header
;
5237 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
*)HeaderAddress
;
5241 STRING_TOKEN (STR_PCI_EXT_CAP_ECEA
),
5242 gShellDebug1HiiHandle
,
5243 Header
->AssociationBitmap
5247 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5248 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
),
5249 (VOID
*) (HeaderAddress
)
5251 return (EFI_SUCCESS
);
5255 Function to interpret and print out the ARI structure
5257 @param[in] HeaderAddress The Address of this capability header.
5258 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5261 PrintInterpretedExtendedCompatibilityAri (
5262 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5263 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5266 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
*Header
;
5267 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
*)HeaderAddress
;
5271 STRING_TOKEN (STR_PCI_EXT_CAP_ARI
),
5272 gShellDebug1HiiHandle
,
5273 Header
->AriCapability
,
5278 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5279 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
),
5280 (VOID
*) (HeaderAddress
)
5282 return (EFI_SUCCESS
);
5286 Function to interpret and print out the DPA structure
5288 @param[in] HeaderAddress The Address of this capability header.
5289 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5292 PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (
5293 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5294 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5297 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
*Header
;
5299 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
*)HeaderAddress
;
5303 STRING_TOKEN (STR_PCI_EXT_CAP_DPA
),
5304 gShellDebug1HiiHandle
,
5305 Header
->DpaCapability
,
5306 Header
->DpaLatencyIndicator
,
5310 for (LinkCount
= 0 ; LinkCount
< PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header
) + 1 ; LinkCount
++) {
5313 STRING_TOKEN (STR_PCI_EXT_CAP_DPA2
),
5314 gShellDebug1HiiHandle
,
5316 Header
->DpaPowerAllocationArray
[LinkCount
]
5321 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5322 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header
),
5323 (VOID
*) (HeaderAddress
)
5325 return (EFI_SUCCESS
);
5329 Function to interpret and print out the link declaration structure
5331 @param[in] HeaderAddress The Address of this capability header.
5332 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5335 PrintInterpretedExtendedCompatibilityLinkDeclaration (
5336 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5337 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5340 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
*Header
;
5342 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
*)HeaderAddress
;
5346 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR
),
5347 gShellDebug1HiiHandle
,
5348 Header
->ElementSelfDescription
5351 for (LinkCount
= 0 ; LinkCount
< PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header
) ; LinkCount
++) {
5354 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2
),
5355 gShellDebug1HiiHandle
,
5357 Header
->LinkEntry
[LinkCount
]
5362 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5363 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header
)-1)*sizeof(UINT32
),
5364 (VOID
*) (HeaderAddress
)
5366 return (EFI_SUCCESS
);
5370 Function to interpret and print out the Advanced Error Reporting structure
5372 @param[in] HeaderAddress The Address of this capability header.
5373 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5376 PrintInterpretedExtendedCompatibilityAer (
5377 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5378 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5381 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
*Header
;
5382 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
*)HeaderAddress
;
5386 STRING_TOKEN (STR_PCI_EXT_CAP_AER
),
5387 gShellDebug1HiiHandle
,
5388 Header
->UncorrectableErrorStatus
,
5389 Header
->UncorrectableErrorMask
,
5390 Header
->UncorrectableErrorSeverity
,
5391 Header
->CorrectableErrorStatus
,
5392 Header
->CorrectableErrorMask
,
5393 Header
->AdvancedErrorCapabilitiesAndControl
,
5394 Header
->HeaderLog
[0],
5395 Header
->HeaderLog
[1],
5396 Header
->HeaderLog
[2],
5397 Header
->HeaderLog
[3],
5398 Header
->RootErrorCommand
,
5399 Header
->RootErrorStatus
,
5400 Header
->ErrorSourceIdentification
,
5401 Header
->CorrectableErrorSourceIdentification
,
5402 Header
->TlpPrefixLog
[0],
5403 Header
->TlpPrefixLog
[1],
5404 Header
->TlpPrefixLog
[2],
5405 Header
->TlpPrefixLog
[3]
5409 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5410 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
),
5411 (VOID
*) (HeaderAddress
)
5413 return (EFI_SUCCESS
);
5417 Function to interpret and print out the multicast structure
5419 @param[in] HeaderAddress The Address of this capability header.
5420 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5421 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5424 PrintInterpretedExtendedCompatibilityMulticast (
5425 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5426 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5427 IN CONST PCI_CAPABILITY_PCIEXP
*PciExpressCapPtr
5430 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
*Header
;
5431 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
*)HeaderAddress
;
5435 STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST
),
5436 gShellDebug1HiiHandle
,
5437 Header
->MultiCastCapability
,
5438 Header
->MulticastControl
,
5439 Header
->McBaseAddress
,
5440 Header
->McReceiveAddress
,
5442 Header
->McBlockUntranslated
,
5443 Header
->McOverlayBar
5448 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5449 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
),
5450 (VOID
*) (HeaderAddress
)
5453 return (EFI_SUCCESS
);
5457 Function to interpret and print out the virtual channel and multi virtual channel structure
5459 @param[in] HeaderAddress The Address of this capability header.
5460 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5463 PrintInterpretedExtendedCompatibilityVirtualChannel (
5464 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5465 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5468 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
*Header
;
5469 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
*CapabilityItem
;
5471 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
*)HeaderAddress
;
5475 STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE
),
5476 gShellDebug1HiiHandle
,
5477 Header
->ExtendedVcCount
,
5478 Header
->PortVcCapability1
,
5479 Header
->PortVcCapability2
,
5480 Header
->VcArbTableOffset
,
5481 Header
->PortVcControl
,
5482 Header
->PortVcStatus
5484 for (ItemCount
= 0 ; ItemCount
< Header
->ExtendedVcCount
; ItemCount
++) {
5485 CapabilityItem
= &Header
->Capability
[ItemCount
];
5488 STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM
),
5489 gShellDebug1HiiHandle
,
5491 CapabilityItem
->VcResourceCapability
,
5492 CapabilityItem
->PortArbTableOffset
,
5493 CapabilityItem
->VcResourceControl
,
5494 CapabilityItem
->VcResourceStatus
5500 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5501 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
)
5502 + Header
->ExtendedVcCount
* sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
),
5503 (VOID
*) (HeaderAddress
)
5506 return (EFI_SUCCESS
);
5510 Function to interpret and print out the resizeable bar structure
5512 @param[in] HeaderAddress The Address of this capability header.
5513 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5516 PrintInterpretedExtendedCompatibilityResizeableBar (
5517 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5518 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5521 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
*Header
;
5523 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
*)HeaderAddress
;
5525 for (ItemCount
= 0 ; ItemCount
< (UINT32
)GET_NUMBER_RESIZABLE_BARS(Header
) ; ItemCount
++) {
5528 STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR
),
5529 gShellDebug1HiiHandle
,
5531 Header
->Capability
[ItemCount
].ResizableBarCapability
,
5532 Header
->Capability
[ItemCount
].ResizableBarControl
5538 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5539 (UINT32
)GET_NUMBER_RESIZABLE_BARS(Header
) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY
),
5540 (VOID
*) (HeaderAddress
)
5543 return (EFI_SUCCESS
);
5547 Function to interpret and print out the TPH structure
5549 @param[in] HeaderAddress The Address of this capability header.
5550 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5553 PrintInterpretedExtendedCompatibilityTph (
5554 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5555 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5558 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
*Header
;
5559 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
*)HeaderAddress
;
5563 STRING_TOKEN (STR_PCI_EXT_CAP_TPH
),
5564 gShellDebug1HiiHandle
,
5565 Header
->TphRequesterCapability
,
5566 Header
->TphRequesterControl
5570 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)Header
->TphStTable
- (UINT8
*)HeadersBaseAddress
),
5571 GET_TPH_TABLE_SIZE(Header
),
5572 (VOID
*)Header
->TphStTable
5577 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5578 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
) + GET_TPH_TABLE_SIZE(Header
) - sizeof(UINT16
),
5579 (VOID
*) (HeaderAddress
)
5582 return (EFI_SUCCESS
);
5586 Function to interpret and print out the secondary PCIe capability structure
5588 @param[in] HeaderAddress The Address of this capability header.
5589 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5590 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5593 PrintInterpretedExtendedCompatibilitySecondary (
5594 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5595 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5596 IN CONST PCI_CAPABILITY_PCIEXP
*PciExpressCap
5599 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
*Header
;
5600 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
*)HeaderAddress
;
5604 STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY
),
5605 gShellDebug1HiiHandle
,
5606 Header
->LinkControl3
.Uint32
,
5607 Header
->LaneErrorStatus
5611 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)Header
->EqualizationControl
- (UINT8
*)HeadersBaseAddress
),
5612 PciExpressCap
->LinkCapability
.Bits
.MaxLinkWidth
* sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL
),
5613 (VOID
*)Header
->EqualizationControl
5618 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5619 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
) - sizeof (Header
->EqualizationControl
)
5620 + PciExpressCap
->LinkCapability
.Bits
.MaxLinkWidth
* sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL
),
5621 (VOID
*) (HeaderAddress
)
5624 return (EFI_SUCCESS
);
5628 Display Pcie extended capability details
5630 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5631 @param[in] HeaderAddress The address of this capability header.
5632 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5635 PrintPciExtendedCapabilityDetails(
5636 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5637 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5638 IN CONST PCI_CAPABILITY_PCIEXP
*PciExpressCapPtr
5641 switch (HeaderAddress
->CapabilityId
){
5642 case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID
:
5643 return PrintInterpretedExtendedCompatibilityAer(HeaderAddress
, HeadersBaseAddress
);
5644 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID
:
5645 return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress
, HeadersBaseAddress
);
5646 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID
:
5647 return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress
, HeadersBaseAddress
);
5648 case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID
:
5649 return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress
, HeadersBaseAddress
);
5650 case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID
:
5651 return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress
, HeadersBaseAddress
);
5652 case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID
:
5653 return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress
, HeadersBaseAddress
);
5654 case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID
:
5655 return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress
, HeadersBaseAddress
);
5656 case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID
:
5657 return PrintInterpretedExtendedCompatibilityAri(HeaderAddress
, HeadersBaseAddress
);
5658 case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID
:
5659 return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress
, HeadersBaseAddress
);
5660 case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID
:
5661 return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress
, HeadersBaseAddress
);
5662 case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID
:
5663 return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress
, HeadersBaseAddress
);
5664 case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID
:
5665 return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress
, HeadersBaseAddress
);
5666 case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID
:
5667 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID
:
5668 return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress
, HeadersBaseAddress
);
5669 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID
:
5671 // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b
5673 return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress
, HeadersBaseAddress
, PciExpressCapPtr
);
5674 case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID
:
5675 return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress
, HeadersBaseAddress
);
5676 case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID
:
5677 return PrintInterpretedExtendedCompatibilityTph(HeaderAddress
, HeadersBaseAddress
);
5678 case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID
:
5679 return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress
, HeadersBaseAddress
, PciExpressCapPtr
);
5681 ShellPrintEx (-1, -1,
5682 L
"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",
5683 HeaderAddress
->CapabilityId
5691 Display Pcie device structure.
5693 @param[in] PciExpressCap PCI Express capability buffer.
5694 @param[in] ExtendedConfigSpace PCI Express extended configuration space.
5695 @param[in] ExtendedCapability PCI Express extended capability ID to explain.
5698 PciExplainPciExpress (
5699 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
,
5700 IN UINT8
*ExtendedConfigSpace
,
5701 IN CONST UINT16 ExtendedCapability
5704 UINT8 DevicePortType
;
5708 PCI_EXP_EXT_HDR
*ExtHdr
;
5710 DevicePortType
= (UINT8
)PciExpressCap
->Capability
.Bits
.DevicePortType
;
5712 ShellPrintEx (-1, -1, L
"\r\nPci Express device capability structure:\r\n");
5714 for (Index
= 0; PcieExplainList
[Index
].Type
< PcieExplainTypeMax
; Index
++) {
5715 if (ShellGetExecutionBreakFlag()) {
5718 RegAddr
= (UINT8
*) PciExpressCap
+ PcieExplainList
[Index
].Offset
;
5719 switch (PcieExplainList
[Index
].Width
) {
5720 case FieldWidthUINT8
:
5721 RegValue
= *(UINT8
*) RegAddr
;
5723 case FieldWidthUINT16
:
5724 RegValue
= *(UINT16
*) RegAddr
;
5726 case FieldWidthUINT32
:
5727 RegValue
= *(UINT32
*) RegAddr
;
5733 ShellPrintHiiEx(-1, -1, NULL
,
5734 PcieExplainList
[Index
].Token
,
5735 gShellDebug1HiiHandle
,
5736 PcieExplainList
[Index
].Offset
,
5739 if (PcieExplainList
[Index
].Func
== NULL
) {
5742 switch (PcieExplainList
[Index
].Type
) {
5743 case PcieExplainTypeLink
:
5745 // Link registers should not be used by
5746 // a) Root Complex Integrated Endpoint
5747 // b) Root Complex Event Collector
5749 if (DevicePortType
== PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT
||
5750 DevicePortType
== PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR
) {
5754 case PcieExplainTypeSlot
:
5756 // Slot registers are only valid for
5757 // a) Root Port of PCI Express Root Complex
5758 // b) Downstream Port of PCI Express Switch
5759 // and when SlotImplemented bit is set in PCIE cap register.
5761 if ((DevicePortType
!= PCIE_DEVICE_PORT_TYPE_ROOT_PORT
&&
5762 DevicePortType
!= PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT
) ||
5763 !PciExpressCap
->Capability
.Bits
.SlotImplemented
) {
5767 case PcieExplainTypeRoot
:
5769 // Root registers are only valid for
5770 // Root Port of PCI Express Root Complex
5772 if (DevicePortType
!= PCIE_DEVICE_PORT_TYPE_ROOT_PORT
) {
5779 PcieExplainList
[Index
].Func (PciExpressCap
);
5782 ExtHdr
= (PCI_EXP_EXT_HDR
*)ExtendedConfigSpace
;
5783 while (ExtHdr
->CapabilityId
!= 0 && ExtHdr
->CapabilityVersion
!= 0) {
5785 // Process this item
5787 if (ExtendedCapability
== 0xFFFF || ExtendedCapability
== ExtHdr
->CapabilityId
) {
5791 PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR
*)ExtendedConfigSpace
, ExtHdr
, PciExpressCap
);
5795 // Advance to the next item if it exists
5797 if (ExtHdr
->NextCapabilityOffset
!= 0) {
5798 ExtHdr
= (PCI_EXP_EXT_HDR
*)(ExtendedConfigSpace
+ ExtHdr
->NextCapabilityOffset
- EFI_PCIE_CAPABILITY_BASE_OFFSET
);