1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Exception handlers used in SM mode
19 ;-------------------------------------------------------------------------------
21 EXTERNDEF gcStmPsd:BYTE
23 EXTERNDEF SmmStmExceptionHandler:PROC
24 EXTERNDEF SmmStmSetup:PROC
25 EXTERNDEF SmmStmTeardown:PROC
26 EXTERNDEF gStmXdSupported:BYTE
32 MSR_IA32_MISC_ENABLE EQU 1A0h
33 MSR_EFER EQU 0c0000080h
39 ; This structure serves as a template for all processors.
46 DB 0Fh ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
59 DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint
60 DQ 0 ; SmmSmiHandlerRsp
63 DD 80010100h ; RequiredStmSmmRevId
67 DW 01Fh ; ExceptionFilter
70 DQ 0 ; BiosHwResourceRequirementsPtr
72 DB 0 ; PhysicalAddressBits
73 PSD_SIZE = $ - offset gcStmPsd
76 ;------------------------------------------------------------------------------
77 ; SMM Exception handlers
78 ;------------------------------------------------------------------------------
82 call SmmStmExceptionHandler
86 DB 0fh, 01h, 0c1h ; VMCALL
92 ; Check XD disable bit
95 mov rax, offset ASM_PFX(gStmXdSupported)
99 mov ecx, MSR_IA32_MISC_ENABLE
101 mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]
102 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
104 and dx, 0FFFBh ; clear XD Disable bit if it is set
109 or ax, MSR_EFER_XD ; enable NXE
118 mov rax, offset ASM_PFX(gStmXdSupported)
122 pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
125 mov ecx, MSR_IA32_MISC_ENABLE
127 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
136 ; Check XD disable bit
139 mov rax, offset ASM_PFX(gStmXdSupported)
143 mov ecx, MSR_IA32_MISC_ENABLE
145 mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]
146 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
148 and dx, 0FFFBh ; clear XD Disable bit if it is set
153 or ax, MSR_EFER_XD ; enable NXE
162 mov rax, offset ASM_PFX(gStmXdSupported)
166 pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
169 mov ecx, MSR_IA32_MISC_ENABLE
171 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM