/** @file\r
\r
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r
+ Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
\r
// ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions\r
#define AARCH64_PFR0_FP (0xF << 16)\r
+#define AARCH64_PFR0_GIC (0xF << 24)\r
\r
// SCR - Secure Configuration Register definitions\r
#define SCR_NS (1 << 0)\r
#define SCR_AW (1 << 5)\r
\r
// MIDR - Main ID Register definitions\r
+#define ARM_CPU_TYPE_SHIFT 4\r
#define ARM_CPU_TYPE_MASK 0xFFF\r
#define ARM_CPU_TYPE_AEMv8 0xD0F\r
#define ARM_CPU_TYPE_A53 0xD03\r
#define ARM_CPU_TYPE_A57 0xD07\r
+#define ARM_CPU_TYPE_A72 0xD08\r
#define ARM_CPU_TYPE_A15 0xC0F\r
#define ARM_CPU_TYPE_A9 0xC09\r
+#define ARM_CPU_TYPE_A7 0xC07\r
#define ARM_CPU_TYPE_A5 0xC05\r
\r
#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )\r
#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r
\r
// Hypervisor Configuration Register\r
-#define ARM_HCR_FMO BIT3\r
-#define ARM_HCR_IMO BIT4\r
-#define ARM_HCR_AMO BIT5\r
-#define ARM_HCR_TGE BIT27\r
+#define ARM_HCR_FMO BIT3\r
+#define ARM_HCR_IMO BIT4\r
+#define ARM_HCR_AMO BIT5\r
+#define ARM_HCR_TSC BIT19\r
+#define ARM_HCR_TGE BIT27\r
+\r
+// Exception Syndrome Register\r
+#define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))\r
+#define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))\r
+\r
+#define AARCH64_ESR_EC_SMC32 (0x13 << 26)\r
+#define AARCH64_ESR_EC_SMC64 (0x17 << 26)\r
\r
// AArch64 Exception Level\r
#define AARCH64_EL3 0xC\r
#define AARCH64_EL2 0x8\r
#define AARCH64_EL1 0x4\r
\r
+// Saved Program Status Register definitions\r
+#define SPSR_A BIT8\r
+#define SPSR_I BIT7\r
+#define SPSR_F BIT6\r
+\r
+#define SPSR_AARCH32 BIT4\r
+\r
+#define SPSR_AARCH32_MODE_USER 0x0\r
+#define SPSR_AARCH32_MODE_FIQ 0x1\r
+#define SPSR_AARCH32_MODE_IRQ 0x2\r
+#define SPSR_AARCH32_MODE_SVC 0x3\r
+#define SPSR_AARCH32_MODE_ABORT 0x7\r
+#define SPSR_AARCH32_MODE_UNDEF 0xB\r
+#define SPSR_AARCH32_MODE_SYS 0xF\r
+\r
+// Counter-timer Hypervisor Control register definitions\r
+#define CNTHCTL_EL2_EL1PCTEN BIT0\r
+#define CNTHCTL_EL2_EL1PCEN BIT1\r
+\r
#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)\r
\r
+// Vector table offset definitions\r
+#define ARM_VECTOR_CUR_SP0_SYNC 0x000\r
+#define ARM_VECTOR_CUR_SP0_IRQ 0x080\r
+#define ARM_VECTOR_CUR_SP0_FIQ 0x100\r
+#define ARM_VECTOR_CUR_SP0_SERR 0x180\r
+\r
+#define ARM_VECTOR_CUR_SPx_SYNC 0x200\r
+#define ARM_VECTOR_CUR_SPx_IRQ 0x280\r
+#define ARM_VECTOR_CUR_SPx_FIQ 0x300\r
+#define ARM_VECTOR_CUR_SPx_SERR 0x380\r
+\r
+#define ARM_VECTOR_LOW_A64_SYNC 0x400\r
+#define ARM_VECTOR_LOW_A64_IRQ 0x480\r
+#define ARM_VECTOR_LOW_A64_FIQ 0x500\r
+#define ARM_VECTOR_LOW_A64_SERR 0x580\r
+\r
+#define ARM_VECTOR_LOW_A32_SYNC 0x600\r
+#define ARM_VECTOR_LOW_A32_IRQ 0x680\r
+#define ARM_VECTOR_LOW_A32_FIQ 0x700\r
+#define ARM_VECTOR_LOW_A32_SERR 0x780\r
+\r
+#define VECTOR_BASE(tbl) \\r
+ .section .text.##tbl##,"ax"; \\r
+ .align 11; \\r
+ .org 0x0; \\r
+ GCC_ASM_EXPORT(tbl); \\r
+ ASM_PFX(tbl): \\r
+\r
+#define VECTOR_ENTRY(tbl, off) \\r
+ .org off\r
+\r
+#define VECTOR_END(tbl) \\r
+ .org 0x800; \\r
+ .previous\r
+\r
VOID\r
EFIAPI\r
ArmEnableSWPInstruction (\r
IN UINTN Hcr\r
);\r
\r
+UINTN\r
+ArmReadHcr (\r
+ VOID\r
+ );\r
+\r
UINTN\r
ArmReadCurrentEL (\r
VOID\r
IN UINT64 PageAttributes\r
);\r
\r
-UINT64\r
-GcdAttributeToPageAttribute (\r
- IN UINT64 GcdAttributes\r
- );\r
-\r
UINTN\r
ArmWriteCptr (\r
IN UINT64 Cptr\r