IN UINT32 AddrLen\r
);\r
\r
+UINT32\r
+Lan9118RawMmioRead32(\r
+ UINTN Address,\r
+ UINTN Delay\r
+ );\r
+#define Lan9118MmioRead32(a) \\r
+ Lan9118RawMmioRead32(a, a ## _RD_DELAY)\r
+\r
+UINT32\r
+Lan9118RawMmioWrite32(\r
+ UINTN Address,\r
+ UINT32 Value,\r
+ UINTN Delay\r
+ );\r
+#define Lan9118MmioWrite32(a, v) \\r
+ Lan9118RawMmioWrite32(a, v, a ## _WR_DELAY)\r
+\r
/* ------------------ MAC CSR Access ------------------- */\r
\r
// Read from MAC indirect registers\r
// Flags for PHY reset\r
#define PHY_RESET_PMT BIT0\r
#define PHY_RESET_BCR BIT1\r
-#define PHY_RESET_CHECK_LINK BIT2\r
-#define PHY_SOFT_RESET_CLEAR_INT BIT3\r
+#define PHY_SOFT_RESET_CLEAR_INT BIT2\r
\r
// Perform PHY software reset\r
EFI_STATUS\r