MdeModulePkg/Xhci: Fix TRT when data length is 0

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciSched.c

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
index dc36945962a0d02bebc46b6ab0066c0b37e4720d..7cbc9a8502eab0aebc282e516e71f37494cb24e2 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
@@ -298,10 +298,15 @@ XhcCreateTransferTrb (
       TrbStart->TrbCtrSetup.IOC           = 1;\r
       TrbStart->TrbCtrSetup.IDT           = 1;\r
       TrbStart->TrbCtrSetup.Type          = TRB_TYPE_SETUP_STAGE;\r
-      if (Urb->Ep.Direction == EfiUsbDataIn) {\r
-        TrbStart->TrbCtrSetup.TRT = 3;\r
-      } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r
-        TrbStart->TrbCtrSetup.TRT = 2;\r
+      if (Urb->DataLen > 0) {\r
+        if (Urb->Ep.Direction == EfiUsbDataIn) {\r
+          TrbStart->TrbCtrSetup.TRT = 3;\r
+        } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r
+          TrbStart->TrbCtrSetup.TRT = 2;\r
+        } else {\r
+          DEBUG ((DEBUG_ERROR, "XhcCreateTransferTrb: Direction sholud be IN or OUT when Data exists!\n"));\r
+          ASSERT (FALSE);\r
+        }\r
       } else {\r
         TrbStart->TrbCtrSetup.TRT = 0;\r
       }\r