MdeModulePkg/Xhci: Fix TRT when data length is 0

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3418

According to xhci spec, at USB packet level, a Control Transfer
consists of multiple transactions partitioned into stages: a
setup stage, an optional data stage, and a terminating status
stage. If Data Stage does not exist, the Transfer Type flag(TRT)
should be No Data Stage.
So if data length equals to 0, TRT is set to 0.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Wenyi Xie <xiewenyi2@huawei.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
index dc36945962a0d02bebc46b6ab0066c0b37e4720d..7cbc9a8502eab0aebc282e516e71f37494cb24e2 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
@@ -298,10 +298,15 @@ XhcCreateTransferTrb (
       TrbStart->TrbCtrSetup.IOC           = 1;\r
       TrbStart->TrbCtrSetup.IDT           = 1;\r
       TrbStart->TrbCtrSetup.Type          = TRB_TYPE_SETUP_STAGE;\r
-      if (Urb->Ep.Direction == EfiUsbDataIn) {\r
-        TrbStart->TrbCtrSetup.TRT = 3;\r
-      } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r
-        TrbStart->TrbCtrSetup.TRT = 2;\r
+      if (Urb->DataLen > 0) {\r
+        if (Urb->Ep.Direction == EfiUsbDataIn) {\r
+          TrbStart->TrbCtrSetup.TRT = 3;\r
+        } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r
+          TrbStart->TrbCtrSetup.TRT = 2;\r
+        } else {\r
+          DEBUG ((DEBUG_ERROR, "XhcCreateTransferTrb: Direction sholud be IN or OUT when Data exists!\n"));\r
+          ASSERT (FALSE);\r
+        }\r
       } else {\r
         TrbStart->TrbCtrSetup.TRT = 0;\r
       }\r

diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
index 32d72ef03c2d17b18ba6a5ea4740f12065849f99..5b9892a1cbbbeac8052e08adc1099e165f34ad96 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
@@ -291,10 +291,15 @@ XhcPeiCreateTransferTrb (
       TrbStart->TrbCtrSetup.IOC           = 1;\r
       TrbStart->TrbCtrSetup.IDT           = 1;\r
       TrbStart->TrbCtrSetup.Type          = TRB_TYPE_SETUP_STAGE;\r
-      if (Urb->Ep.Direction == EfiUsbDataIn) {\r
-        TrbStart->TrbCtrSetup.TRT = 3;\r
-      } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r
-        TrbStart->TrbCtrSetup.TRT = 2;\r
+      if (Urb->DataLen > 0) {\r
+        if (Urb->Ep.Direction == EfiUsbDataIn) {\r
+          TrbStart->TrbCtrSetup.TRT = 3;\r
+        } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r
+          TrbStart->TrbCtrSetup.TRT = 2;\r
+        } else {\r
+          DEBUG ((DEBUG_ERROR, "XhcPeiCreateTransferTrb: Direction sholud be IN or OUT when Data exists!\n"));\r
+          ASSERT (FALSE);\r
+        }\r
       } else {\r
         TrbStart->TrbCtrSetup.TRT = 0;\r
       }\r