UefiCpuPkg/Universal/Acpi/S3Resume2Pei: Add support for PCD PcdPteMemoryEncryptionAdd...

[mirror_edk2.git] / OvmfPkg / Library / AcpiTimerLib / BaseAcpiTimerLib.c

diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
index 58938b5d8bb8647eb9410c79fdcca9cd708015cf..a839495e673dbd7f124fed24fd2dbda590d7bd80 100644 (file)
--- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
@@ -15,21 +15,8 @@
 #include <Library/DebugLib.h>\r
 #include <Library/IoLib.h>\r
 #include <Library/PciLib.h>\r
-#include <Library/PcdLib.h>\r
 #include <OvmfPlatforms.h>\r
 \r
-//\r
-// Power Management PCI Configuration Register fields\r
-//\r
-#define PMBA_RTE      BIT0\r
-#define PIIX4_PMIOSE  BIT0\r
-#define Q35_ACPI_EN   BIT7\r
-\r
-//\r
-// Offset in the Power Management Base Address to the ACPI Timer\r
-//\r
-#define ACPI_TIMER_OFFSET  0x8\r
-\r
 //\r
 // Cached ACPI Timer IO Address\r
 //\r
@@ -50,6 +37,8 @@ AcpiTimerLibConstructor (
 {\r
   UINT16 HostBridgeDevId;\r
   UINTN Pmba;\r
+  UINT32 PmbaAndVal;\r
+  UINT32 PmbaOrVal;\r
   UINTN AcpiCtlReg;\r
   UINT8 AcpiEnBit;\r
 \r
@@ -59,14 +48,18 @@ AcpiTimerLibConstructor (
   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
-      Pmba       = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
-      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC\r
-      AcpiEnBit  = PIIX4_PMIOSE;\r
+      Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+      PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r
+      PmbaOrVal  = PIIX4_PMBA_VALUE;\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
+      AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;\r
       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
-      Pmba       = POWER_MGMT_REGISTER_Q35 (0x40);\r
-      AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (0x44); // ACPI_CNTL\r
-      AcpiEnBit  = Q35_ACPI_EN;\r
+      Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
+      PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r
+      PmbaOrVal  = ICH9_PMBASE_VALUE;\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
+      AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;\r
       break;\r
     default:\r
       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
@@ -75,17 +68,15 @@ AcpiTimerLibConstructor (
       return RETURN_UNSUPPORTED;\r
   }\r
 \r
-  mAcpiTimerIoAddr = (PciRead32 (Pmba) & ~PMBA_RTE) + ACPI_TIMER_OFFSET;\r
-\r
   //\r
   // Check to see if the Power Management Base Address is already enabled\r
   //\r
   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
     //\r
     // If the Power Management Base Address is not programmed,\r
-    // then program the Power Management Base Address from a PCD.\r
+    // then program it now.\r
     //\r
-    PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
+    PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r
 \r
     //\r
     // Enable PMBA I/O port decodes\r
@@ -93,6 +84,7 @@ AcpiTimerLibConstructor (
     PciOr8 (AcpiCtlReg, AcpiEnBit);\r
   }\r
 \r
+  mAcpiTimerIoAddr = (PciRead32 (Pmba) & ~PMBA_RTE) + ACPI_TIMER_OFFSET;\r
   return RETURN_SUCCESS;\r
 }\r
 \r