SourceLevelDebugPkg: Remove X86 ASM and S files

[mirror_edk2.git] / UefiCpuPkg / Library / BaseUefiCpuLib / X64 / InitializeFpu.asm

diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.asm b/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.asm
index 34c6de6f53cf482e9b77ae1c4f8c8dd5d58b055e..331af15cc666401f54a8399239504d952fe13148 100644 (file)
--- a/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.asm
+++ b/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.asm
@@ -1,7 +1,7 @@
 ;------------------------------------------------------------------------------\r
 ;*\r
-;*   Copyright 2009, Intel Corporation\r
-;*   All rights reserved. This program and the accompanying materials\r
+;*   Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>\r
+;*   This program and the accompanying materials\r
 ;*   are licensed and made available under the terms and conditions of the BSD License\r
 ;*   which accompanies this distribution.  The full text of the license may be found at\r
 ;*   http://opensource.org/licenses/bsd-license.php\r
@@ -16,9 +16,9 @@
 .const\r
 ;\r
 ; Float control word initial value: \r
-; all exceptions masked, double-precision, round-to-nearest\r
+; all exceptions masked, double-extended-precision, round-to-nearest\r
 ;\r
-mFpuControlWord       DW      027Fh\r
+mFpuControlWord       DW      037Fh\r
 ;\r
 ; Multimedia-extensions control word:\r
 ; all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
@@ -28,20 +28,23 @@ mMmxControlWord       DD      01F80h
 .code\r
 \r
 \r
-;
+;\r
 ; Initializes floating point units for requirement of UEFI specification.\r
 ;\r
 ; This function initializes floating-point control word to 0x027F (all exceptions\r
 ; masked,double-precision, round-to-nearest) and multimedia-extensions control word\r
 ; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r
-; for masked underflow).
+; for masked underflow).\r
 ;\r
 InitializeFloatingPointUnits PROC PUBLIC\r
 \r
     ;\r
     ; Initialize floating point units\r
     ;\r
-    finit\r
+    ; The following opcodes stand for instruction 'finit' \r
+    ; to be supported by some 64-bit assemblers\r
+    ;\r
+    DB      9Bh, 0DBh, 0E3h\r
     fldcw   mFpuControlWord\r
     \r
     ;\r