UINT32 RegEcx;\r
UINT32 RegEdx;\r
\r
- AsmCpuid(CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);\r
+ AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);\r
return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&\r
RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&\r
RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);\r
CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r
CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;\r
CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;\r
- CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;\r
CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;\r
UINT32 MaxStandardCpuIdIndex;\r
UINT32 MaxExtendedCpuIdIndex;\r
UINTN LevelType;\r
UINT32 MaxLogicProcessorsPerPackage;\r
UINT32 MaxCoresPerPackage;\r
- UINT32 MaxThreadPerPackageMask;\r
- UINT32 ActualThreadPerPackageMask;\r
- UINT32 MaxCoresPerNode;\r
- UINT32 CorePerNodeMask;\r
- UINT32 ApicIdShift;\r
UINTN ThreadBits;\r
UINTN CoreBits;\r
\r
//\r
// Check if the processor is capable of supporting more than one logical processor.\r
//\r
- AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
+ AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
if (VersionInfoEdx.Bits.HTT == 0) {\r
if (Thread != NULL) {\r
*Thread = 0;\r
//\r
// Get max index of CPUID\r
//\r
- AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r
- AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);\r
+ AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);\r
\r
//\r
// If the extended topology enumeration leaf is available, it\r
// the SMT sub-field of x2APIC ID.\r
//\r
LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
- ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
+ ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;\r
\r
//\r
//\r
SubIndex = 1;\r
do {\r
- AsmCpuidEx(\r
+ AsmCpuidEx (\r
CPUID_EXTENDED_TOPOLOGY,\r
SubIndex,\r
&ExtendedTopologyEax.Uint32,\r
//\r
// Get logical processor count\r
//\r
- AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r
+ AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r
MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r
\r
//\r
//\r
if (StandardSignatureIsAuthenticAMD()) {\r
if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {\r
- AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r
+ AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r
if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {\r
- AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,\r
- &AmdProcessorTopologyEcx.Uint32, NULL);\r
//\r
- // Get cores per processor package\r
+ // Account for max possible thread count to decode ApicId\r
//\r
- MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r
+ AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);\r
+ MaxLogicProcessorsPerPackage = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;\r
\r
//\r
- // Account for actual thread count (e.g., SMT disabled)\r
- //\r
- AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);\r
- MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;\r
- ActualThreadPerPackageMask = 1;\r
- while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {\r
- ActualThreadPerPackageMask <<= 1;\r
- }\r
-\r
- //\r
- // Adjust APIC Id to report concatenation of Package|Core|Thread.\r
+ // Get cores per processor package\r
//\r
- if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {\r
- MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);\r
-\r
- CorePerNodeMask = 1;\r
- while (CorePerNodeMask < MaxCoresPerNode) {\r
- CorePerNodeMask <<= 1;\r
- }\r
- CorePerNodeMask -= 1;\r
-\r
- ApicIdShift = 0;\r
- do {\r
- ApicIdShift += 1;\r
- ActualThreadPerPackageMask <<= 1;\r
- } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);\r
-\r
- InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);\r
- }\r
+ AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);\r
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r
}\r
}\r
}\r
// Extract core count based on CACHE information\r
//\r
if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
- AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
+ AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
if (CacheParamsEax.Uint32 != 0) {\r
MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r
}\r