UefiCpuPkg: ApicLib
authorLeo Duran <leo.duran@amd.com>
Tue, 1 Aug 2017 19:35:13 +0000 (03:35 +0800)
committerLiming Gao <liming.gao@intel.com>
Tue, 5 Sep 2017 05:03:22 +0000 (13:03 +0800)
GetProcessorLocationByApicId ()
- Use max possible thread count to decode InitialApicId on AMD processor.
- Clean-up on C Coding standards.

Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c

index 2091e5e..b0b7e32 100644 (file)
@@ -48,7 +48,7 @@ StandardSignatureIsAuthenticAMD (
   UINT32  RegEcx;\r
   UINT32  RegEdx;\r
 \r
-  AsmCpuid(CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);\r
+  AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);\r
   return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&\r
           RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&\r
           RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);\r
@@ -1000,7 +1000,6 @@ GetProcessorLocationByApicId (
   CPUID_EXTENDED_TOPOLOGY_ECX         ExtendedTopologyEcx;\r
   CPUID_AMD_EXTENDED_CPU_SIG_ECX      AmdExtendedCpuSigEcx;\r
   CPUID_AMD_PROCESSOR_TOPOLOGY_EBX    AmdProcessorTopologyEbx;\r
-  CPUID_AMD_PROCESSOR_TOPOLOGY_ECX    AmdProcessorTopologyEcx;\r
   CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX  AmdVirPhyAddressSizeEcx;\r
   UINT32                              MaxStandardCpuIdIndex;\r
   UINT32                              MaxExtendedCpuIdIndex;\r
@@ -1008,18 +1007,13 @@ GetProcessorLocationByApicId (
   UINTN                               LevelType;\r
   UINT32                              MaxLogicProcessorsPerPackage;\r
   UINT32                              MaxCoresPerPackage;\r
-  UINT32                              MaxThreadPerPackageMask;\r
-  UINT32                              ActualThreadPerPackageMask;\r
-  UINT32                              MaxCoresPerNode;\r
-  UINT32                              CorePerNodeMask;\r
-  UINT32                              ApicIdShift;\r
   UINTN                               ThreadBits;\r
   UINTN                               CoreBits;\r
 \r
   //\r
   // Check if the processor is capable of supporting more than one logical processor.\r
   //\r
-  AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
+  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
   if (VersionInfoEdx.Bits.HTT == 0) {\r
     if (Thread != NULL) {\r
       *Thread = 0;\r
@@ -1042,8 +1036,8 @@ GetProcessorLocationByApicId (
   //\r
   // Get max index of CPUID\r
   //\r
-  AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r
-  AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);\r
+  AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r
+  AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);\r
 \r
   //\r
   // If the extended topology enumeration leaf is available, it\r
@@ -1072,7 +1066,7 @@ GetProcessorLocationByApicId (
       // the SMT sub-field of x2APIC ID.\r
       //\r
       LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
-      ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
+      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
       ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;\r
 \r
       //\r
@@ -1081,7 +1075,7 @@ GetProcessorLocationByApicId (
       //\r
       SubIndex = 1;\r
       do {\r
-        AsmCpuidEx(\r
+        AsmCpuidEx (\r
           CPUID_EXTENDED_TOPOLOGY,\r
           SubIndex,\r
           &ExtendedTopologyEax.Uint32,\r
@@ -1103,7 +1097,7 @@ GetProcessorLocationByApicId (
     //\r
     // Get logical processor count\r
     //\r
-    AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r
+    AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r
     MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r
 \r
     //\r
@@ -1116,45 +1110,19 @@ GetProcessorLocationByApicId (
     //\r
     if (StandardSignatureIsAuthenticAMD()) {\r
       if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {\r
-        AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r
+        AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r
         if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {\r
-          AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,\r
-            &AmdProcessorTopologyEcx.Uint32, NULL);\r
           //\r
-          // Get cores per processor package\r
+          // Account for max possible thread count to decode ApicId\r
           //\r
-          MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r
+          AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);\r
+          MaxLogicProcessorsPerPackage = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;\r
 \r
           //\r
-          // Account for actual thread count (e.g., SMT disabled)\r
-          //\r
-          AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);\r
-          MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;\r
-          ActualThreadPerPackageMask = 1;\r
-          while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {\r
-            ActualThreadPerPackageMask <<= 1;\r
-          }\r
-\r
-          //\r
-          // Adjust APIC Id to report concatenation of Package|Core|Thread.\r
+          // Get cores per processor package\r
           //\r
-          if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {\r
-            MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);\r
-\r
-            CorePerNodeMask = 1;\r
-            while (CorePerNodeMask < MaxCoresPerNode) {\r
-              CorePerNodeMask <<= 1;\r
-            }\r
-            CorePerNodeMask -= 1;\r
-\r
-            ApicIdShift = 0;\r
-            do {\r
-              ApicIdShift += 1;\r
-              ActualThreadPerPackageMask <<= 1;\r
-            } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);\r
-\r
-            InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);\r
-          }\r
+          AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);\r
+          MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r
         }\r
       }\r
     }\r
@@ -1163,7 +1131,7 @@ GetProcessorLocationByApicId (
       // Extract core count based on CACHE information\r
       //\r
       if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
-        AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
+        AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
         if (CacheParamsEax.Uint32 != 0) {\r
           MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r
         }\r
index d5d4efa..1f4dcf7 100644 (file)
@@ -49,7 +49,7 @@ StandardSignatureIsAuthenticAMD (
   UINT32  RegEcx;\r
   UINT32  RegEdx;\r
 \r
-  AsmCpuid(CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);\r
+  AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);\r
   return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&\r
           RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&\r
           RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);\r
@@ -1095,7 +1095,6 @@ GetProcessorLocationByApicId (
   CPUID_EXTENDED_TOPOLOGY_ECX         ExtendedTopologyEcx;\r
   CPUID_AMD_EXTENDED_CPU_SIG_ECX      AmdExtendedCpuSigEcx;\r
   CPUID_AMD_PROCESSOR_TOPOLOGY_EBX    AmdProcessorTopologyEbx;\r
-  CPUID_AMD_PROCESSOR_TOPOLOGY_ECX    AmdProcessorTopologyEcx;\r
   CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX  AmdVirPhyAddressSizeEcx;\r
   UINT32                              MaxStandardCpuIdIndex;\r
   UINT32                              MaxExtendedCpuIdIndex;\r
@@ -1103,18 +1102,13 @@ GetProcessorLocationByApicId (
   UINTN                               LevelType;\r
   UINT32                              MaxLogicProcessorsPerPackage;\r
   UINT32                              MaxCoresPerPackage;\r
-  UINT32                              MaxThreadPerPackageMask;\r
-  UINT32                              ActualThreadPerPackageMask;\r
-  UINT32                              MaxCoresPerNode;\r
-  UINT32                              CorePerNodeMask;\r
-  UINT32                              ApicIdShift;\r
   UINTN                               ThreadBits;\r
   UINTN                               CoreBits;\r
 \r
   //\r
   // Check if the processor is capable of supporting more than one logical processor.\r
   //\r
-  AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
+  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
   if (VersionInfoEdx.Bits.HTT == 0) {\r
     if (Thread != NULL) {\r
       *Thread = 0;\r
@@ -1137,8 +1131,8 @@ GetProcessorLocationByApicId (
   //\r
   // Get max index of CPUID\r
   //\r
-  AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r
-  AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);\r
+  AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r
+  AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);\r
 \r
   //\r
   // If the extended topology enumeration leaf is available, it\r
@@ -1167,7 +1161,7 @@ GetProcessorLocationByApicId (
       // the SMT sub-field of x2APIC ID.\r
       //\r
       LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
-      ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
+      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
       ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;\r
 \r
       //\r
@@ -1176,7 +1170,7 @@ GetProcessorLocationByApicId (
       //\r
       SubIndex = 1;\r
       do {\r
-        AsmCpuidEx(\r
+        AsmCpuidEx (\r
           CPUID_EXTENDED_TOPOLOGY,\r
           SubIndex,\r
           &ExtendedTopologyEax.Uint32,\r
@@ -1198,7 +1192,7 @@ GetProcessorLocationByApicId (
     //\r
     // Get logical processor count\r
     //\r
-    AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r
+    AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r
     MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r
 \r
     //\r
@@ -1211,45 +1205,19 @@ GetProcessorLocationByApicId (
     //\r
     if (StandardSignatureIsAuthenticAMD()) {\r
       if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {\r
-        AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r
+        AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r
         if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {\r
-          AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,\r
-            &AmdProcessorTopologyEcx.Uint32, NULL);\r
           //\r
-          // Get cores per processor package\r
+          // Account for max possible thread count to decode ApicId\r
           //\r
-          MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r
+          AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);\r
+          MaxLogicProcessorsPerPackage = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;\r
 \r
           //\r
-          // Account for actual thread count (e.g., SMT disabled)\r
-          //\r
-          AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);\r
-          MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;\r
-          ActualThreadPerPackageMask = 1;\r
-          while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {\r
-            ActualThreadPerPackageMask <<= 1;\r
-          }\r
-\r
-          //\r
-          // Adjust APIC Id to report concatenation of Package|Core|Thread.\r
+          // Get cores per processor package\r
           //\r
-          if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {\r
-            MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);\r
-\r
-            CorePerNodeMask = 1;\r
-            while (CorePerNodeMask < MaxCoresPerNode) {\r
-              CorePerNodeMask <<= 1;\r
-            }\r
-            CorePerNodeMask -= 1;\r
-\r
-            ApicIdShift = 0;\r
-            do {\r
-              ApicIdShift += 1;\r
-              ActualThreadPerPackageMask <<= 1;\r
-            } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);\r
-\r
-            InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);\r
-          }\r
+          AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);\r
+          MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r
         }\r
       }\r
     }\r
@@ -1258,7 +1226,7 @@ GetProcessorLocationByApicId (
       // Extract core count based on CACHE information\r
       //\r
       if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
-        AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
+        AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r
         if (CacheParamsEax.Uint32 != 0) {\r
           MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r
         }\r